mmc: msm_sdcc: perform DLL retuning if clock rate is changed
Using HS200/SDR104 bus speed mode requires DLL (Delay Locked
Loop for sampling clock generation) HW block to be tuned if
clock rate is >100MHz so that both host and card are in sync.
During card initialization, driver uses the tuning command to
search for an optimal sampling point and then programs the
DLL HW with this optimal sampling point.
But if MMC core layer switches the clock frequency to <100MHz
(when HS200/SDR104 timing mode is set) and then increases it
back to >100MHz without calling execute_tuning host ops,
DLL may go to unlocked state. So this change makes sure
that execute_tuning is performed explicitly if clock frequency
switch happens without execute_tuning.
CRs-Fixed: 424685
Change-Id: I19ee19965ca5b6a73a09f9332d34b56602051ebd
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 96234fc..293a393 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -162,6 +162,7 @@
static int msmsdcc_runtime_resume(struct device *dev);
static int msmsdcc_dt_get_array(struct device *dev, const char *prop_name,
u32 **out_array, int *len, int size);
+static int msmsdcc_execute_tuning(struct mmc_host *mmc, u32 opcode);
static inline unsigned short msmsdcc_get_nr_sg(struct msmsdcc_host *host)
{
@@ -1416,6 +1417,10 @@
else
data->error = -ETIMEDOUT;
}
+ /* In case of DATA CRC/timeout error, execute tuning again */
+ if (host->tuning_needed && !host->tuning_in_progress)
+ host->tuning_done = false;
+
} else if (status & MCI_RXOVERRUN) {
pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
data->error = -EIO;
@@ -1768,6 +1773,8 @@
msmsdcc_dump_sdcc_state(host);
/* Execute full tuning in case of CRC errors */
host->saved_tuning_phase = INVALID_TUNING_PHASE;
+ if (host->tuning_needed)
+ host->tuning_done = false;
cmd->error = -EILSEQ;
}
@@ -2149,6 +2156,22 @@
}
}
+ /*
+ * Check if DLL retuning is required? If yes, perform it here before
+ * starting new request.
+ */
+ if (host->tuning_needed && !host->tuning_in_progress &&
+ !host->tuning_done) {
+ pr_debug("%s: %s: execute_tuning for timing mode = %d\n",
+ mmc_hostname(mmc), __func__, host->mmc->ios.timing);
+ if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
+ msmsdcc_execute_tuning(mmc,
+ MMC_SEND_TUNING_BLOCK);
+ else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
+ msmsdcc_execute_tuning(mmc,
+ MMC_SEND_TUNING_BLOCK_HS200);
+ }
+
spin_lock_irqsave(&host->lock, flags);
if (host->eject) {
@@ -3345,10 +3368,24 @@
/* Card clock frequency must be > 100MHz to enable tuning */
clk |= (4 << 14);
host->tuning_needed = 1;
- } else if (ios->timing == MMC_TIMING_UHS_DDR50) {
- clk |= (3 << 14);
} else {
- clk |= (2 << 14); /* feedback clock */
+ if (ios->timing == MMC_TIMING_UHS_DDR50)
+ clk |= (3 << 14);
+ else
+ clk |= (2 << 14); /* feedback clock */
+
+ host->tuning_done = false;
+ if (atomic_read(&host->clks_on)) {
+ /* Write 1 to DLL_RST bit of MCI_DLL_CONFIG register */
+ writel_relaxed((readl_relaxed(host->base +
+ MCI_DLL_CONFIG) | MCI_DLL_RST),
+ host->base + MCI_DLL_CONFIG);
+
+ /* Write 1 to DLL_PDN bit of MCI_DLL_CONFIG register */
+ writel_relaxed((readl_relaxed(host->base +
+ MCI_DLL_CONFIG) | MCI_DLL_PDN),
+ host->base + MCI_DLL_CONFIG);
+ }
}
/* Select free running MCLK as input clock of cm_dll_sdc4 */
@@ -4183,6 +4220,8 @@
out:
spin_lock_irqsave(&host->lock, flags);
host->tuning_in_progress = 0;
+ if (!rc)
+ host->tuning_done = true;
spin_unlock_irqrestore(&host->lock, flags);
exit:
pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__);
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index bb1b211..500b5fb 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -401,6 +401,7 @@
bool io_pad_pwr_switch;
bool tuning_in_progress;
bool tuning_needed;
+ bool tuning_done;
bool en_auto_cmd19;
bool en_auto_cmd21;
bool sdio_gpio_lpm;