| /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /include/ "skeleton.dtsi" |
| /include/ "msm8910-ion.dtsi" |
| |
| / { |
| model = "Qualcomm MSM 8910"; |
| compatible = "qcom,msm8910"; |
| interrupt-parent = <&intc>; |
| |
| intc: interrupt-controller@f9000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xf9000000 0x1000>, |
| <0xf9002000 0x1000>; |
| }; |
| |
| msmgpio: gpio@fd510000 { |
| compatible = "qcom,msm-gpio"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0xfd510000 0x4000>; |
| #gpio-cells = <2>; |
| }; |
| |
| timer { |
| compatible = "qcom,msm-qtimer", "arm,armv7-timer"; |
| interrupts = <1 2 0 1 3 0>; |
| clock-frequency = <19200000>; |
| }; |
| |
| serial@f991f000 { |
| compatible = "qcom,msm-lsuart-v14"; |
| reg = <0xf991f000 0x1000>; |
| interrupts = <0 109 0>; |
| status = "disabled"; |
| }; |
| |
| usb@f9a55000 { |
| compatible = "qcom,hsusb-otg"; |
| reg = <0xf9a55000 0x400>; |
| interrupts = <0 134 0>; |
| interrupt-names = "core_irq"; |
| HSUSB_VDDCX-supply = <&pm8110_s1>; |
| HSUSB_1p8-supply = <&pm8110_l10>; |
| HSUSB_3p3-supply = <&pm8110_l20>; |
| |
| qcom,hsusb-otg-phy-type = <2>; |
| qcom,hsusb-otg-mode = <1>; |
| qcom,hsusb-otg-otg-control = <1>; |
| qcom,hsusb-otg-disable-reset; |
| }; |
| |
| android_usb { |
| compatible = "qcom,android-usb"; |
| }; |
| |
| sdcc1: qcom,sdcc@f9824000 { |
| cell-index = <1>; /* SDC1 eMMC slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf9824000 0x800>; |
| reg-names = "core_mem"; |
| interrupts = <0 123 0>; |
| interrupt-names = "core_irq"; |
| |
| vdd-supply = <&pm8110_l17>; |
| qcom,vdd-always-on; |
| qcom,vdd-lpm-sup; |
| qcom,vdd-voltage-level = <2900000 2900000>; |
| qcom,vdd-current-level = <9000 400000>; |
| |
| vdd-io-supply = <&pm8110_l6>; |
| qcom,vdd-io-always-on; |
| qcom,vdd-io-lpm-sup; |
| qcom,vdd-io-voltage-level = <1800000 1800000>; |
| qcom,vdd-io-current-level = <9000 60000>; |
| |
| qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ |
| qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ |
| |
| qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| qcom,sup-voltages = <2900 2900>; |
| qcom,bus-width = <8>; |
| qcom,nonremovable; |
| qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; |
| }; |
| |
| sdcc2: qcom,sdcc@f98a4000 { |
| cell-index = <2>; /* SDC2 SD card slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf98a4000 0x800>; |
| reg-names = "core_mem"; |
| interrupts = <0 125 0>; |
| interrupt-names = "core_irq"; |
| |
| vdd-supply = <&pm8110_l18>; |
| qcom,vdd-voltage-level = <2950000 2950000>; |
| qcom,vdd-current-level = <9000 400000>; |
| |
| vdd-io-supply = <&pm8110_l21>; |
| qcom,vdd-io-voltage-level = <1800000 2950000>; |
| qcom,vdd-io-current-level = <9000 50000>; |
| |
| qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ |
| qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ |
| |
| qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| qcom,sup-voltages = <2950 2950>; |
| qcom,bus-width = <4>; |
| qcom,xpc; |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; |
| qcom,current-limit = <800>; |
| }; |
| |
| qcom,smem@fa00000 { |
| compatible = "qcom,smem"; |
| reg = <0xfa00000 0x200000>, |
| <0xfa006000 0x1000>, |
| <0xfc428000 0x4000>; |
| reg-names = "smem", "irq-reg-base", "aux-mem1"; |
| |
| qcom,smd-modem { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <0>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x1000>; |
| qcom,pil-string = "modem"; |
| interrupts = <0 25 1>; |
| }; |
| |
| qcom,smsm-modem { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <0>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x2000>; |
| interrupts = <0 26 1>; |
| }; |
| |
| qcom,smd-adsp { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <1>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x100>; |
| qcom,pil-string = "adsp"; |
| interrupts = <0 156 1>; |
| }; |
| |
| qcom,smsm-adsp { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <1>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x200>; |
| interrupts = <0 157 1>; |
| }; |
| |
| qcom,smd-wcnss { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <6>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x20000>; |
| qcom,pil-string = "wcnss"; |
| interrupts = <0 142 1>; |
| }; |
| |
| qcom,smsm-wcnss { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <6>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x80000>; |
| interrupts = <0 144 1>; |
| }; |
| |
| qcom,smd-rpm { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <15>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x1>; |
| interrupts = <0 168 1>; |
| qcom,irq-no-suspend; |
| }; |
| |
| qcom,wdt@f9017000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0xf9017000 0x1000>; |
| interrupts = <0 3 0>, <0 4 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping = <1>; |
| }; |
| }; |
| |
| /include/ "msm8910-regulator.dtsi" |