| commit | 37d5993c5cc9bc83762ae1b5bd287438022e8afe | [log] [tgz] |
|---|---|---|
| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | Sat Dec 10 20:38:32 2011 +0800 |
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | Sun Dec 11 03:01:09 2011 +0800 |
| tree | 9d05123c5b167ab8bb3b815e5becf537d54bfd92 | |
| parent | 974edd30beafdb136cdfc6839a143e23c826dc89 [diff] |
ASoC: Fix WM8996 24.576MHz clock operation Record the clock after the divider as that is what all SYSCLK users see. Without this the other clock configuration in the device comes out at half rate. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org