| commit | 3863c74b512c1afd3ce6b2f81d8dea9f1d860968 | [log] [tgz] |
|---|---|---|
| author | Thara Gopinath <thara@ti.com> | Tue Dec 08 16:33:15 2009 -0700 |
| committer | paul <paul@twilight.(none)> | Fri Dec 11 17:00:42 2009 -0700 |
| tree | 1d7d15664c0ae3a71be7949e9c52ca2f79a73811 | |
| parent | 18862cbe47e37beba98f22c088fbe6fe029df889 [diff] |
OMAP3: PM: Fix for MPU power domain MEM BANK position MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>