tree 1d7d15664c0ae3a71be7949e9c52ca2f79a73811
parent 18862cbe47e37beba98f22c088fbe6fe029df889
author Thara Gopinath <thara@ti.com> 1260315195 -0700
committer paul <paul@twilight.(none)> 1260576042 -0700

OMAP3: PM: Fix for MPU power domain MEM BANK position

MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>