Merge "msm: 8960: set SDC1 CMD and DATA line to pull up state during LPM" into msm-3.0
diff --git a/AndroidKernel.mk b/AndroidKernel.mk
index dcb81d7..97aa85d 100644
--- a/AndroidKernel.mk
+++ b/AndroidKernel.mk
@@ -8,6 +8,29 @@
KERNEL_HEADERS_INSTALL := $(KERNEL_OUT)/usr
KERNEL_MODULES_INSTALL := system
KERNEL_MODULES_OUT := $(TARGET_OUT)/lib/modules
+KERNEL_IMG=$(KERNEL_OUT)/arch/arm/boot/Image
+
+MSM_ARCH ?= $(shell $(PERL) -e 'while (<>) {$$a = $$1 if /CONFIG_ARCH_((?:MSM|QSD)[a-zA-Z0-9]+)=y/; $$r = $$1 if /CONFIG_MSM_SOC_REV_(?!NONE)(\w+)=y/;} print lc("$$a$$r\n");' $(KERNEL_CONFIG))
+KERNEL_USE_OF ?= $(shell $(PERL) -e '$$of = "n"; while (<>) { if (/CONFIG_USE_OF=y/) { $$of = "y"; break; } } print $$of;' kernel/arch/arm/configs/$(KERNEL_DEFCONFIG))
+
+ifeq "$(KERNEL_USE_OF)" "y"
+KERNEL_ZIMG = $(KERNEL_OUT)/arch/arm/boot/zImage
+DTB_FILE = $(KERNEL_OUT)/arch/arm/boot/$(MSM_ARCH).dtb
+DTS_FILE = $(KERNEL_OUT)/../../../../../../kernel/arch/arm/boot/dts/$(MSM_ARCH).dts
+FULL_KERNEL = $(KERNEL_OUT)/arch/arm/boot/$(MSM_ARCH)-zImage
+DTC = $(KERNEL_OUT)/scripts/dtc/dtc
+
+define append-dtb
+md $(KERNEL_OUT)/arch/arm/boot;\
+$(DTC) -p 1024 -O dtb -o $(DTB_FILE) $(DTS_FILE);\
+cat $(KERNEL_ZIMG) $(DTB_FILE) > $(FULL_KERNEL)
+endef
+else
+FULL_KERNEL = $(KERNEL_IMG)
+
+define append-dtb
+endef
+endif
ifeq ($(TARGET_USES_UNCOMPRESSED_KERNEL),true)
$(info Using uncompressed kernel)
@@ -47,6 +70,7 @@
$(MAKE) -C kernel O=../$(KERNEL_OUT) INSTALL_MOD_PATH=../../$(KERNEL_MODULES_INSTALL) ARCH=arm CROSS_COMPILE=arm-eabi- modules_install
$(mv-modules)
$(clean-module-folder)
+ $(append-dtb)
$(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(KERNEL_CONFIG)
$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- headers_install
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index cc9a1b7..b71df28 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -332,7 +332,7 @@
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
-CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=16
+CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
CONFIG_FB_MSM=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index eb34964..9fd7e71 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -332,7 +332,7 @@
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
-CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=16
+CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
CONFIG_FB_MSM=y
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index 21800fb..90c83d4 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -311,7 +311,7 @@
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
-CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=16
+CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
CONFIG_FB_MSM=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 6be8772..10b55dc 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -317,7 +317,7 @@
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
-CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=16
+CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
CONFIG_FB_MSM=y
@@ -429,6 +429,7 @@
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_TIMER_STATS=y
+CONFIG_SLUB_DEBUG_ON=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index f77e883..f08bfb7 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -170,6 +170,7 @@
select MSM_SCM if SMP
select MSM_DIRECT_SCLK_ACCESS
select REGULATOR
+ select MSM_RPM_REGULATOR
select MSM_RPM
select MSM_XO
select MSM_QDSP6_APR
@@ -208,6 +209,9 @@
select MSM_QDSP6_APR
select MSM_AUDIO_QDSP6 if SND_SOC
select MULTI_IRQ_HANDLER
+ select MSM_RPM
+ select MSM_SPM_V2
+ select MSM_L2_SPM
config ARCH_MSMCOPPER
bool "MSM Copper"
@@ -422,6 +426,14 @@
help
Support for the Qualcomm MSM7627A Refrence Design.
+config MACH_MSM7627A_EVB
+ depends on ARCH_MSM7X27A
+ depends on !MSM_STACKED_MEMORY
+ default y
+ bool "MSM7627A EVB"
+ help
+ Support for the Qualcomm MSM7627A Reference Design.
+
config MACH_MSM7X30_SURF
depends on ARCH_MSM7X30
depends on !MSM_STACKED_MEMORY
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 53b7dab..234fb53 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -141,6 +141,7 @@
obj-$(CONFIG_MSM_AUDIO_QDSP6) += qdsp6v2/
obj-$(CONFIG_MSM_HW3D) += hw3d.o
ifdef CONFIG_PM
+ obj-$(CONFIG_ARCH_APQ8064) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM8960) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM8X60) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM9615) += pm-8x60.o
@@ -179,6 +180,7 @@
obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator-8660.o
obj-$(CONFIG_ARCH_MSM8960) += rpm-regulator-8960.o
obj-$(CONFIG_ARCH_MSM9615) += rpm-regulator-9615.o
+obj-$(CONFIG_ARCH_MSM8930) += rpm-regulator-8930.o
endif
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
@@ -193,6 +195,7 @@
obj-$(CONFIG_MSM_WCNSS_SSR_8960) += wcnss-ssr-8960.o
ifdef CONFIG_CPU_IDLE
+ obj-$(CONFIG_ARCH_APQ8064) += cpuidle.o
obj-$(CONFIG_ARCH_MSM8960) += cpuidle.o
obj-$(CONFIG_ARCH_MSM8X60) += cpuidle.o
obj-$(CONFIG_ARCH_MSM9615) += cpuidle.o
@@ -223,6 +226,7 @@
obj-$(CONFIG_MACH_MSM7X27A_SURF) += board-msm7x27a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
+obj-$(CONFIG_MACH_MSM7627A_EVB) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
@@ -235,7 +239,7 @@
obj-$(CONFIG_ARCH_MSM8960) += devices-8960.o
obj-$(CONFIG_ARCH_APQ8064) += devices-8960.o devices-8064.o
board-8960-all-objs += board-8960.o board-8960-camera.o board-8960-display.o board-8960-pmic.o board-8960-storage.o board-8960-gpiomux.o
-board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o
+board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o devices-8930.o
board-8064-all-objs += board-8064.o board-8064-pmic.o board-8064-storage.o board-8064-gpiomux.o
obj-$(CONFIG_MACH_MSM8960_SIM) += board-8960-all.o board-8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_RUMI3) += board-8960-all.o board-8960-regulator.o
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index 187b92e..ee1c91a 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -40,6 +40,7 @@
#include "devices.h"
#include <mach/gpio.h>
#include <mach/gpiomux.h>
+#include <mach/rpm.h>
#ifdef CONFIG_ANDROID_PMEM
#include <linux/android_pmem.h>
#endif
@@ -48,10 +49,16 @@
#include <asm/setup.h>
#include <mach/dma.h>
#include <mach/msm_bus_board.h>
+#include <mach/pm.h>
+#include <mach/cpuidle.h>
#include "msm_watchdog.h"
#include "board-8064.h"
#include "acpuclock.h"
+#include "spm.h"
+#include "mpm.h"
+#include "rpm_resources.h"
+#include "pm-boot.h"
#define MSM_PMEM_ADSP_SIZE 0x7800000
#define MSM_PMEM_AUDIO_SIZE 0x2B4000
@@ -565,6 +572,13 @@
static void __init apq8064_init_irq(void)
{
+ struct msm_mpm_device_data *data = NULL;
+
+#ifdef CONFIG_MSM_MPM
+ data = &apq8064_mpm_dev_data;
+#endif
+
+ msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -604,6 +618,368 @@
.id = 3,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8821_s1,
+
+ },
+};
+
+static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
+ {
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
+ MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
+ true,
+ 100, 8000, 100000, 1,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
+ MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
+ true,
+ 2000, 6000, 60100000, 3000,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
+ false,
+ 4200, 5000, 60350000, 3500,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
+ false,
+ 6300, 4500, 65350000, 4800,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
+ false,
+ 11700, 2500, 67850000, 5500,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
+ false,
+ 13800, 2000, 71850000, 6800,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
+ false,
+ 29700, 500, 75850000, 8800,
+ },
+
+ {
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
+ false,
+ 29700, 0, 76350000, 9800,
+ },
+};
+
+static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
+ .mode = MSM_PM_BOOT_CONFIG_TZ,
+};
+
+static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
+ .levels = &msm_rpmrs_levels[0],
+ .num_levels = ARRAY_SIZE(msm_rpmrs_levels),
+ .vdd_mem_levels = {
+ [MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
+ [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
+ [MSM_RPMRS_VDD_MEM_MAX] = 1150000,
+ },
+ .vdd_dig_levels = {
+ [MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
+ [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
+ [MSM_RPMRS_VDD_DIG_MAX] = 1150000,
+ },
+ .vdd_mask = 0x7FFFFF,
+ .rpmrs_target_id = {
+ [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
+ [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
+ [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
+ [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
+ [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
+ [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
+ [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
+ },
+};
+
+static struct msm_cpuidle_state msm_cstates[] __initdata = {
+ {0, 0, "C0", "WFI",
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
+
+ {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
+
+ {0, 2, "C2", "POWER_COLLAPSE",
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
+
+ {1, 0, "C0", "WFI",
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
+
+ {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
+
+ {2, 0, "C0", "WFI",
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
+
+ {2, 1, "C1", "STANDALONE_POWER_COLLAPSE",
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
+
+ {3, 0, "C0", "WFI",
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
+
+ {3, 1, "C1", "STANDALONE_POWER_COLLAPSE",
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
+};
+
+static struct msm_pm_platform_data msm_pm_data[] = {
+ [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 1,
+ .suspend_enabled = 1,
+ },
+
+ [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
+ .idle_supported = 0,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 0,
+ .idle_enabled = 1,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
+ .idle_supported = 0,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 0,
+ .idle_enabled = 1,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
+ .idle_supported = 0,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ },
+
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 0,
+ .idle_enabled = 1,
+ .suspend_enabled = 0,
+ },
+};
+
+static uint8_t spm_wfi_cmd_sequence[] __initdata = {
+ 0x03, 0x0f,
+};
+
+static uint8_t spm_power_collapse_without_rpm[] __initdata = {
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x03, 0x01,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
+static uint8_t spm_power_collapse_with_rpm[] __initdata = {
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x07, 0x01, 0x0B,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
+static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
+ [0] = {
+ .mode = MSM_SPM_MODE_CLOCK_GATING,
+ .notify_rpm = false,
+ .cmd = spm_wfi_cmd_sequence,
+ },
+ [1] = {
+ .mode = MSM_SPM_MODE_POWER_COLLAPSE,
+ .notify_rpm = false,
+ .cmd = spm_power_collapse_without_rpm,
+ },
+ [2] = {
+ .mode = MSM_SPM_MODE_POWER_COLLAPSE,
+ .notify_rpm = true,
+ .cmd = spm_power_collapse_with_rpm,
+ },
+};
+
+static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
+ 0x00, 0x20, 0x03, 0x20,
+ 0x00, 0x0f,
+};
+
+static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
+ 0x00, 0x20, 0x34, 0x64,
+ 0x48, 0x07, 0x48, 0x20,
+ 0x50, 0x64, 0x04, 0x34,
+ 0x50, 0x0f,
+};
+static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
+ 0x00, 0x10, 0x34, 0x64,
+ 0x48, 0x07, 0x48, 0x10,
+ 0x50, 0x64, 0x04, 0x34,
+ 0x50, 0x0F,
+};
+
+static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
+ [0] = {
+ .mode = MSM_SPM_L2_MODE_RETENTION,
+ .notify_rpm = false,
+ .cmd = l2_spm_wfi_cmd_sequence,
+ },
+ [1] = {
+ .mode = MSM_SPM_L2_MODE_GDHS,
+ .notify_rpm = true,
+ .cmd = l2_spm_gdhs_cmd_sequence,
+ },
+ [2] = {
+ .mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
+ .notify_rpm = true,
+ .cmd = l2_spm_power_off_cmd_sequence,
+ },
+};
+
+
+static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
+ [0] = {
+ .reg_base_addr = MSM_SAW_L2_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
+ .modes = msm_spm_l2_seq_list,
+ .num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
+ },
+};
+
+static struct msm_spm_platform_data msm_spm_data[] __initdata = {
+ [0] = {
+ .reg_base_addr = MSM_SAW0_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
+ .reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
+#if defined(CONFIG_MSM_AVS_HW)
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
+#endif
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .vctl_timeout_us = 50,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
+ },
+ [1] = {
+ .reg_base_addr = MSM_SAW1_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
+ .reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
+#if defined(CONFIG_MSM_AVS_HW)
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
+#endif
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .vctl_timeout_us = 50,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
+ },
+ [2] = {
+ .reg_base_addr = MSM_SAW2_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
+ .reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
+#if defined(CONFIG_MSM_AVS_HW)
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
+#endif
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .vctl_timeout_us = 50,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
+ },
+ [3] = {
+ .reg_base_addr = MSM_SAW3_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
+ .reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
+#if defined(CONFIG_MSM_AVS_HW)
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
+ .reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
+#endif
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
+ .reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
+ .vctl_timeout_us = 50,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
},
};
@@ -684,6 +1060,9 @@
&apq_pcm_afe,
&apq_cpudai_auxpcm_rx,
&apq_cpudai_auxpcm_tx,
+ &apq8064_rpm_device,
+ &apq8064_rpm_log_device,
+ &apq8064_rpm_stat_device,
&msm_bus_8064_apps_fabric,
&msm_bus_8064_sys_fabric,
&msm_bus_8064_mm_fabric,
@@ -779,6 +1158,8 @@
{
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
+ BUG_ON(msm_rpm_init(&apq8064_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
apq8064_clock_init();
apq8064_init_gpiomux();
apq8064_i2c_init();
@@ -793,6 +1174,13 @@
slim_register_board_info(apq8064_slim_devices,
ARRAY_SIZE(apq8064_slim_devices));
acpuclk_init(&acpuclk_8064_soc_data);
+ msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
+ msm_spm_l2_init(msm_spm_l2_data);
+ msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
+ msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
+ msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
+ msm_pm_data);
+ BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
}
static void __init apq8064_sim_init(void)
diff --git a/arch/arm/mach-msm/board-8930-camera.c b/arch/arm/mach-msm/board-8930-camera.c
index 6b5f917..a32699f 100644
--- a/arch/arm/mach-msm/board-8930-camera.c
+++ b/arch/arm/mach-msm/board-8930-camera.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -348,12 +348,20 @@
.ioclk.mclk_clk_rate = 24000000,
.ioclk.vfe_clk_rate = 228570000,
.csid_core = 0,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
{
.ioclk.mclk_clk_rate = 24000000,
.ioclk.vfe_clk_rate = 228570000,
.csid_core = 1,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
};
diff --git a/arch/arm/mach-msm/board-8930-regulator.c b/arch/arm/mach-msm/board-8930-regulator.c
index 765bd45..989fde3 100644
--- a/arch/arm/mach-msm/board-8930-regulator.c
+++ b/arch/arm/mach-msm/board-8930-regulator.c
@@ -257,6 +257,97 @@
.pin_ctrl = _pin_ctrl, \
}
+#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
+ _peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
+ _force_mode, _power_mode, _state, _sleep_selectable, \
+ _always_on, _supply_regulator, _system_uA) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_modes_mask = _modes, \
+ .valid_ops_mask = _ops, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .input_uV = _min_uV, \
+ .apply_uV = _apply_uV, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id), \
+ .consumer_supplies = vreg_consumers_##_id, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .default_uV = _default_uV, \
+ .peak_uA = _peak_uA, \
+ .avg_uA = _avg_uA, \
+ .pull_down_enable = _pull_down, \
+ .pin_ctrl = _pin_ctrl, \
+ .freq = RPM_VREG_FREQ_##_freq, \
+ .pin_fn = _pin_fn, \
+ .force_mode = _force_mode, \
+ .power_mode = _power_mode, \
+ .state = _state, \
+ .sleep_selectable = _sleep_selectable, \
+ .system_uA = _system_uA, \
+ }
+
+#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _init_peak_uA) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
+ RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+/* Pin control initialization */
+#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id##_PC), \
+ .consumer_supplies = vreg_consumers_##_id##_PC, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8038_##_id##_PC, \
+ .pin_fn = RPM_VREG_PIN_FN_8930_##_pin_fn, \
+ .pin_ctrl = _pin_ctrl, \
+ }
+
#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \
[MSM8930_GPIO_VREG_ID_##_id] = { \
.init_data = { \
@@ -307,60 +398,58 @@
* ID name always_on pd min_uV max_uV en_t supply
* system_uA reg_ID
*/
- PM8XXX_SMPS(S1, "8038_s1", 1, 1, 1150000, 1150000, 500, NULL, 100000,
- 26),
- PM8XXX_SMPS(S2, "8038_s2", 1, 1, 1400000, 1400000, 500, NULL, 100000,
- 27),
- PM8XXX_SMPS(S3, "8038_s3", 0, 1, 1150000, 1150000, 500, NULL, 0, 28),
- PM8XXX_SMPS(S4, "8038_s4", 1, 1, 2200000, 2200000, 500, NULL, 100000,
- 29),
-
- PM8XXX_NLDO1200(L1, "8038_l1", 0, 1, 1300000, 1300000, 200, "8038_s2",
- 0, 1),
- PM8XXX_LDO(L2, "8038_l2", 0, 1, 1200000, 1200000, 200, "8038_s2", 0,
- 2),
- PM8XXX_LDO(L3, "8038_l3", 0, 1, 3075000, 3075000, 200, NULL, 0, 3),
- PM8XXX_LDO(L4, "8038_l4", 1, 1, 1800000, 1800000, 200, NULL, 10000,
- 4),
- PM8XXX_LDO(L5, "8038_l5", 0, 1, 2950000, 2950000, 200, NULL, 0, 5),
- PM8XXX_LDO(L6, "8038_l6", 0, 1, 2950000, 2950000, 200, NULL, 0, 6),
- PM8XXX_LDO(L7, "8038_l7", 0, 1, 2050000, 2050000, 200, "8038_s4", 0,
- 7),
- PM8XXX_LDO(L8, "8038_l8", 0, 1, 2800000, 2800000, 200, NULL, 0, 8),
- PM8XXX_LDO(L9, "8038_l9", 0, 1, 2850000, 2850000, 200, NULL, 0, 9),
- PM8XXX_LDO(L10, "8038_l10", 0, 1, 2900000, 2900000, 200, NULL, 0, 10),
- PM8XXX_LDO(L11, "8038_l11", 1, 1, 1800000, 1800000, 200, "8038_s4",
- 10000, 11),
- PM8XXX_LDO(L12, "8038_l12", 0, 1, 1200000, 1200000, 200, "8038_s2", 0,
- 12),
- PM8XXX_LDO(L14, "8038_l14", 0, 1, 1800000, 1800000, 200, NULL, 0, 13),
- PM8XXX_LDO(L15, "8038_l15", 0, 1, 1800000, 2950000, 200, NULL, 0, 14),
PM8XXX_NLDO1200(L16, "8038_l16", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 15),
- PM8XXX_LDO(L17, "8038_l17", 0, 1, 1800000, 2950000, 200, NULL, 0, 16),
- PM8XXX_LDO(L18, "8038_l18", 0, 1, 1800000, 1800000, 200, NULL, 0, 17),
+ 0, 0),
PM8XXX_NLDO1200(L19, "8038_l19", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 18),
- PM8XXX_NLDO1200(L20, "8038_l20", 1, 1, 1200000, 1200000, 200, "8038_s2",
- 10000, 19),
- PM8XXX_LDO(L21, "8038_l21", 0, 1, 1900000, 1900000, 200, "8038_s4", 0,
- 20),
- PM8XXX_LDO(L22, "8038_l22", 1, 1, 2950000, 2950000, 200, NULL, 10000,
- 21),
- PM8XXX_LDO(L23, "8038_l23", 0, 1, 1800000, 1800000, 200, "8038_s4", 0,
- 22),
- PM8XXX_NLDO1200(L24, "8038_l24", 1, 1, 1150000, 1150000, 200, "8038_s2",
- 10000, 23),
- PM8XXX_LDO(L26, "8038_l26", 1, 1, 1050000, 1050000, 200, "8038_s2",
- 10000, 24),
+ 0, 1),
PM8XXX_NLDO1200(L27, "8038_l27", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 25),
+ 0, 2),
+};
- /* ID name always_on pd en_t supply reg_ID */
- PM8XXX_VS(LVS1, "8038_lvs1", 0, 1, 0, "8038_l11", 32),
- PM8XXX_VS(LVS2, "8038_lvs2", 0, 1, 0, "8038_l11", 33),
+static struct rpm_regulator_init_data
+msm8930_rpm_regulator_init_data[] __devinitdata = {
+ /* ID a_on pd ss min_uV max_uV supply sys_uA freq */
+ RPM_SMPS(S1, 1, 1, 1, 500000, 1150000, NULL, 100000, 4p80),
+ RPM_SMPS(S2, 1, 1, 0, 1400000, 1400000, NULL, 100000, 1p60),
+ RPM_SMPS(S3, 0, 1, 0, 1150000, 1150000, NULL, 100000, 3p20),
+ RPM_SMPS(S4, 1, 1, 0, 2200000, 2200000, NULL, 100000, 1p60),
+ /* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
+ RPM_LDO(L1, 0, 1, 0, 1300000, 1300000, "8038_s2", 0, 0),
+ RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
+ RPM_LDO(L3, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
+ RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 10000, 10000),
+ RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L7, 0, 1, 0, 2050000, 2050000, "8038_s4", 0, 0),
+ RPM_LDO(L8, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
+ RPM_LDO(L9, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+ RPM_LDO(L10, 0, 1, 0, 2900000, 2900000, NULL, 0, 0),
+ RPM_LDO(L11, 1, 1, 0, 1800000, 1800000, "8038_s4", 10000, 10000),
+ RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
+ RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L15, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
+ RPM_LDO(L17, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
+ RPM_LDO(L18, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L20, 1, 1, 0, 1200000, 1200000, "8038_s2", 10000, 10000),
+ RPM_LDO(L21, 0, 1, 0, 1900000, 1900000, "8038_s4", 0, 0),
+ RPM_LDO(L22, 1, 1, 0, 1850000, 2950000, NULL, 10000, 10000),
+ RPM_LDO(L23, 1, 1, 1, 1800000, 1800000, "8038_s4", 0, 0),
+ RPM_LDO(L24, 1, 1, 1, 500000, 1150000, "8038_s2", 10000, 10000),
+ RPM_LDO(L26, 1, 1, 0, 1050000, 1050000, "8038_s2", 10000, 10000),
+
+ /* ID a_on pd ss supply */
+ RPM_VS(LVS1, 0, 1, 0, "8038_l11"),
+ RPM_VS(LVS2, 0, 1, 0, "8038_l11"),
};
int msm8930_pm8038_regulator_pdata_len __devinitdata =
ARRAY_SIZE(msm8930_pm8038_regulator_pdata);
+
+struct rpm_regulator_platform_data msm8930_rpm_regulator_pdata __devinitdata = {
+ .init_data = msm8930_rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(msm8930_rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_8930,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8038_L24,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8038_S1,
+};
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index fe125e3..75d0fb2 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -87,7 +87,6 @@
#include "rpm_resources.h"
#include "mpm.h"
#include "acpuclock.h"
-#include "rpm_log.h"
#include "smd_private.h"
#include "pm-boot.h"
#include "msm_watchdog.h"
@@ -787,6 +786,102 @@
&mdm_device,
};
+#ifdef CONFIG_MSM_MPM
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
+ [1] = MSM_GPIO_TO_INT(46),
+ [2] = MSM_GPIO_TO_INT(150),
+ [4] = MSM_GPIO_TO_INT(103),
+ [5] = MSM_GPIO_TO_INT(104),
+ [6] = MSM_GPIO_TO_INT(105),
+ [7] = MSM_GPIO_TO_INT(106),
+ [8] = MSM_GPIO_TO_INT(107),
+ [9] = MSM_GPIO_TO_INT(7),
+ [10] = MSM_GPIO_TO_INT(11),
+ [11] = MSM_GPIO_TO_INT(15),
+ [12] = MSM_GPIO_TO_INT(19),
+ [13] = MSM_GPIO_TO_INT(23),
+ [14] = MSM_GPIO_TO_INT(27),
+ [15] = MSM_GPIO_TO_INT(31),
+ [16] = MSM_GPIO_TO_INT(35),
+ [19] = MSM_GPIO_TO_INT(90),
+ [20] = MSM_GPIO_TO_INT(92),
+ [23] = MSM_GPIO_TO_INT(85),
+ [24] = MSM_GPIO_TO_INT(83),
+ [25] = USB1_HS_IRQ,
+ [27] = HDMI_IRQ,
+ [29] = MSM_GPIO_TO_INT(10),
+ [30] = MSM_GPIO_TO_INT(102),
+ [31] = MSM_GPIO_TO_INT(81),
+ [32] = MSM_GPIO_TO_INT(78),
+ [33] = MSM_GPIO_TO_INT(94),
+ [34] = MSM_GPIO_TO_INT(72),
+ [35] = MSM_GPIO_TO_INT(39),
+ [36] = MSM_GPIO_TO_INT(43),
+ [37] = MSM_GPIO_TO_INT(61),
+ [38] = MSM_GPIO_TO_INT(50),
+ [39] = MSM_GPIO_TO_INT(42),
+ [41] = MSM_GPIO_TO_INT(62),
+ [42] = MSM_GPIO_TO_INT(76),
+ [43] = MSM_GPIO_TO_INT(75),
+ [44] = MSM_GPIO_TO_INT(70),
+ [45] = MSM_GPIO_TO_INT(69),
+ [46] = MSM_GPIO_TO_INT(67),
+ [47] = MSM_GPIO_TO_INT(65),
+ [48] = MSM_GPIO_TO_INT(58),
+ [49] = MSM_GPIO_TO_INT(54),
+ [50] = MSM_GPIO_TO_INT(52),
+ [51] = MSM_GPIO_TO_INT(49),
+ [52] = MSM_GPIO_TO_INT(40),
+ [53] = MSM_GPIO_TO_INT(37),
+ [54] = MSM_GPIO_TO_INT(24),
+ [55] = MSM_GPIO_TO_INT(14),
+};
+
+static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
+ TLMM_MSM_SUMMARY_IRQ,
+ RPM_APCC_CPU0_GP_HIGH_IRQ,
+ RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+ RPM_APCC_CPU0_GP_LOW_IRQ,
+ RPM_APCC_CPU0_WAKE_UP_IRQ,
+ RPM_APCC_CPU1_GP_HIGH_IRQ,
+ RPM_APCC_CPU1_GP_MEDIUM_IRQ,
+ RPM_APCC_CPU1_GP_LOW_IRQ,
+ RPM_APCC_CPU1_WAKE_UP_IRQ,
+ MSS_TO_APPS_IRQ_0,
+ MSS_TO_APPS_IRQ_1,
+ MSS_TO_APPS_IRQ_2,
+ MSS_TO_APPS_IRQ_3,
+ MSS_TO_APPS_IRQ_4,
+ MSS_TO_APPS_IRQ_5,
+ MSS_TO_APPS_IRQ_6,
+ MSS_TO_APPS_IRQ_7,
+ MSS_TO_APPS_IRQ_8,
+ MSS_TO_APPS_IRQ_9,
+ LPASS_SCSS_GP_LOW_IRQ,
+ LPASS_SCSS_GP_MEDIUM_IRQ,
+ LPASS_SCSS_GP_HIGH_IRQ,
+ SPS_MTI_30,
+ SPS_MTI_31,
+ RIVA_APSS_SPARE_IRQ,
+ RIVA_APPS_WLAN_SMSM_IRQ,
+ RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
+ RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
+};
+
+struct msm_mpm_device_data msm8930_mpm_dev_data __initdata = {
+ .irqs_m2a = msm_mpm_irqs_m2a,
+ .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
+ .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
+ .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
+ .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
+ .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
+ .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
+ .mpm_apps_ipc_val = BIT(1),
+ .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+
+};
+#endif
+
#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init msm8930_map_io(void)
@@ -800,7 +895,12 @@
static void __init msm8930_init_irq(void)
{
- msm_mpm_irq_extn_init();
+ struct msm_mpm_device_data *data = NULL;
+#ifdef CONFIG_MSM_MPM
+ data = &msm8930_mpm_dev_data;
+#endif
+
+ msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -918,21 +1018,21 @@
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
- 0x03, 0x0f,
+ 0x03, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
- 0x00, 0x24, 0x54, 0x10,
- 0x09, 0x03, 0x01,
- 0x10, 0x54, 0x30, 0x0C,
- 0x24, 0x30, 0x0f,
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x03, 0x01,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
- 0x00, 0x24, 0x54, 0x10,
- 0x09, 0x07, 0x01, 0x0B,
- 0x10, 0x54, 0x30, 0x0C,
- 0x24, 0x30, 0x0f,
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x07, 0x01, 0x0B,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
@@ -991,21 +1091,21 @@
};
static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
- 0x00, 0x20, 0x03, 0x20,
- 0x00, 0x0f,
+ 0x00, 0x20, 0x03, 0x20,
+ 0x00, 0x0f,
};
static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
- 0x00, 0x20, 0x34, 0x64,
- 0x48, 0x07, 0x48, 0x20,
- 0x50, 0x64, 0x04, 0x34,
- 0x50, 0x0f,
+ 0x00, 0x20, 0x34, 0x64,
+ 0x48, 0x07, 0x48, 0x20,
+ 0x50, 0x64, 0x04, 0x34,
+ 0x50, 0x0f,
};
static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
- 0x00, 0x10, 0x34, 0x64,
- 0x48, 0x07, 0x48, 0x10,
- 0x50, 0x64, 0x04, 0x34,
- 0x50, 0x0F,
+ 0x00, 0x10, 0x34, 0x64,
+ 0x48, 0x07, 0x48, 0x10,
+ 0x50, 0x64, 0x04, 0x34,
+ 0x50, 0x0F,
};
static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
@@ -1553,20 +1653,6 @@
.src_clk_rate = 24000000,
};
-static struct msm_rpm_platform_data msm_rpm_data = {
- .reg_base_addrs = {
- [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
- [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
- [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
- [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
- },
-
- .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
- .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
- .irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
- .msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
- .msm_apps_ipc_rpm_val = 4,
-};
static struct ks8851_pdata spi_eth_pdata = {
.irq_gpio = KS8851_IRQ_GPIO,
@@ -1675,37 +1761,14 @@
.name = "rpm-regulator",
.id = -1,
.dev = {
- /*
- * TODO: When physical 8930/PM8038 hardware becomes
- * available, replace msm_rpm_regulator_pdata
- * with 8930 rpm regulator object.
- */
-#if !defined(MSM8930_PHASE_2)
-
+#ifndef MSM8930_PHASE_2
.platform_data = &msm_rpm_regulator_pdata,
+#else
+ .platform_data = &msm8930_rpm_regulator_pdata,
#endif
},
};
-static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
- .phys_addr_base = 0x0010C000,
- .reg_offsets = {
- [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
- [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
- },
- .phys_size = SZ_8K,
- .log_len = 4096, /* log's buffer length in bytes */
- .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
-};
-
-static struct platform_device msm_rpm_log_device = {
- .name = "msm_rpm_log",
- .id = -1,
- .dev = {
- .platform_data = &msm_rpm_log_pdata,
- },
-};
-
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
@@ -1763,12 +1826,12 @@
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
- &msm_rpm_device,
+ &msm8930_rpm_device,
+ &msm8930_rpm_log_device,
+ &msm8930_rpm_stat_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
- &msm_rpm_log_device,
- &msm_rpm_stat_device,
&msm_device_tz_log,
#ifdef CONFIG_MSM_QDSS
@@ -1982,6 +2045,33 @@
},
};
+static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
+ .levels = &msm_rpmrs_levels[0],
+ .num_levels = ARRAY_SIZE(msm_rpmrs_levels),
+ .vdd_mem_levels = {
+ [MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
+ [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
+ [MSM_RPMRS_VDD_MEM_MAX] = 1150000,
+ },
+ .vdd_dig_levels = {
+ [MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
+ [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
+ [MSM_RPMRS_VDD_DIG_MAX] = 1150000,
+ },
+ .vdd_mask = 0x7FFFFF,
+ .rpmrs_target_id = {
+ [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
+ [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
+ [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8038_S1_0,
+ [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8038_S1_1,
+ [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8038_L24_0,
+ [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8038_L24_1,
+ [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
+ },
+};
+
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -2123,9 +2213,8 @@
if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
pr_err("meminfo_init() failed!\n");
- BUG_ON(msm_rpm_init(&msm_rpm_data));
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm8930_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
if (msm_xo_init())
diff --git a/arch/arm/mach-msm/board-8930.h b/arch/arm/mach-msm/board-8930.h
index 8e20903..1feb5b8 100644
--- a/arch/arm/mach-msm/board-8930.h
+++ b/arch/arm/mach-msm/board-8930.h
@@ -75,6 +75,9 @@
extern struct gpio_regulator_platform_data
msm8930_gpio_regulator_pdata[] __devinitdata;
+extern struct rpm_regulator_platform_data
+ msm8930_rpm_regulator_pdata __devinitdata;
+
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
enum {
GPIO_EXPANDER_IRQ_BASE = (PM8038_IRQ_BASE + PM8038_NR_IRQS),
diff --git a/arch/arm/mach-msm/board-8960-camera.c b/arch/arm/mach-msm/board-8960-camera.c
index 4466872..2ad92b3 100644
--- a/arch/arm/mach-msm/board-8960-camera.c
+++ b/arch/arm/mach-msm/board-8960-camera.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -353,12 +353,20 @@
.ioclk.mclk_clk_rate = 24000000,
.ioclk.vfe_clk_rate = 228570000,
.csid_core = 0,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
{
.ioclk.mclk_clk_rate = 24000000,
.ioclk.vfe_clk_rate = 228570000,
.csid_core = 1,
+ .is_csiphy = 1,
+ .is_csid = 1,
+ .is_ispif = 1,
+ .is_vpe = 1,
.cam_bus_scale_table = &cam_bus_client_pdata,
},
};
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index f7ff370..a0a540f 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -92,7 +92,6 @@
#include "rpm_resources.h"
#include "mpm.h"
#include "acpuclock.h"
-#include "rpm_log.h"
#include "smd_private.h"
#include "pm-boot.h"
#include "msm_watchdog.h"
@@ -890,7 +889,13 @@
static void __init msm8960_init_irq(void)
{
- msm_mpm_irq_extn_init();
+ struct msm_mpm_device_data *data = NULL;
+
+#ifdef CONFIG_MSM_MPM
+ data = &msm8960_mpm_dev_data;
+#endif
+
+ msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -1514,21 +1519,6 @@
.src_clk_rate = 24000000,
};
-static struct msm_rpm_platform_data msm_rpm_data = {
- .reg_base_addrs = {
- [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
- [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
- [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
- [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
- },
-
- .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
- .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
- .irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
- .msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
- .msm_apps_ipc_rpm_val = 4,
-};
-
static struct msm_pm_sleep_status_data msm_pm_slp_sts_data = {
.base_addr = MSM_ACC0_BASE + 0x08,
.cpu_offset = MSM_ACC1_BASE - MSM_ACC0_BASE,
@@ -1638,25 +1628,6 @@
},
};
-static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
- .phys_addr_base = 0x0010C000,
- .reg_offsets = {
- [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
- [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
- },
- .phys_size = SZ_8K,
- .log_len = 4096, /* log's buffer length in bytes */
- .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
-};
-
-static struct platform_device msm_rpm_log_device = {
- .name = "msm_rpm_log",
- .id = -1,
- .dev = {
- .platform_data = &msm_rpm_log_pdata,
- },
-};
-
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
@@ -1707,14 +1678,13 @@
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
- &msm_rpm_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
- &msm_rpm_log_device,
- &msm_rpm_stat_device,
+ &msm8960_rpm_device,
+ &msm8960_rpm_log_device,
+ &msm8960_rpm_stat_device,
&msm_device_tz_log,
-
#ifdef CONFIG_MSM_QDSS
&msm_etb_device,
&msm_tpiu_device,
@@ -1857,6 +1827,7 @@
}
static struct msm_cpuidle_state msm_cstates[] __initdata = {
+
{0, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
@@ -1981,6 +1952,33 @@
},
};
+static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
+ .levels = &msm_rpmrs_levels[0],
+ .num_levels = ARRAY_SIZE(msm_rpmrs_levels),
+ .vdd_mem_levels = {
+ [MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
+ [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
+ [MSM_RPMRS_VDD_MEM_MAX] = 1150000,
+ },
+ .vdd_dig_levels = {
+ [MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
+ [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
+ [MSM_RPMRS_VDD_DIG_MAX] = 1150000,
+ },
+ .vdd_mask = 0x7FFFFF,
+ .rpmrs_target_id = {
+ [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
+ [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
+ [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
+ [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
+ [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
+ [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
+ [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
+ },
+};
+
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -2179,9 +2177,8 @@
&msm8960_device_watchdog.dev.platform_data;
wdog_pdata->bark_time = 15000;
- BUG_ON(msm_rpm_init(&msm_rpm_data));
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm8960_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&msm8960_device_rpm_regulator);
msm_clock_init(&msm8960_clock_init_data);
@@ -2216,9 +2213,8 @@
static void __init msm8960_rumi3_init(void)
{
- BUG_ON(msm_rpm_init(&msm_rpm_data));
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm8960_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&msm8960_device_rpm_regulator);
msm_clock_init(&msm8960_dummy_clock_init_data);
@@ -2251,9 +2247,8 @@
if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
pr_err("meminfo_init() failed!\n");
- BUG_ON(msm_rpm_init(&msm_rpm_data));
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm8960_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
if (msm_xo_init())
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index bb90988..e1ff3dd 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -448,7 +448,7 @@
&msm9615_device_tsens,
&msm_device_nand,
&msm_device_bam_dmux,
- &msm_rpm_device,
+ &msm9615_rpm_device,
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
@@ -465,6 +465,8 @@
&msm9615_device_watchdog,
&msm_bus_9615_sys_fabric,
&msm_bus_def_fab,
+ &msm9615_rpm_log_device,
+ &msm9615_rpm_stat_device,
};
static void __init msm9615_i2c_init(void)
diff --git a/arch/arm/mach-msm/board-msm7627a-bt.c b/arch/arm/mach-msm/board-msm7627a-bt.c
index 8b3b606..c92a898 100644
--- a/arch/arm/mach-msm/board-msm7627a-bt.c
+++ b/arch/arm/mach-msm/board-msm7627a-bt.c
@@ -933,6 +933,9 @@
int i, rc = 0;
struct device *dev;
+ if (machine_is_msm7627a_evb())
+ return;
+
gpio_bt_config();
i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
diff --git a/arch/arm/mach-msm/board-msm7627a-camera.c b/arch/arm/mach-msm/board-msm7627a-camera.c
index a3c2da3..bde38c3 100644
--- a/arch/arm/mach-msm/board-msm7627a-camera.c
+++ b/arch/arm/mach-msm/board-msm7627a-camera.c
@@ -23,6 +23,289 @@
#include "devices-msm7x2xa.h"
#include "board-msm7627a.h"
+#ifdef CONFIG_MSM_CAMERA_V4L2
+static uint32_t camera_off_gpio_table[] = {
+ GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
+};
+
+static uint32_t camera_on_gpio_table[] = {
+ GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
+};
+
+#ifdef CONFIG_MSM_CAMERA_FLASH
+static struct msm_camera_sensor_flash_src msm_flash_src = {
+ .flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
+ ._fsrc.ext_driver_src.led_en = GPIO_CAM_GP_LED_EN1,
+ ._fsrc.ext_driver_src.led_flash_en = GPIO_CAM_GP_LED_EN2,
+};
+#endif
+
+static struct regulator_bulk_data regs_camera[] = {
+ { .supply = "msme1", .min_uV = 1800000, .max_uV = 1800000 },
+ { .supply = "gp2", .min_uV = 2850000, .max_uV = 2850000 },
+ { .supply = "usb2", .min_uV = 1800000, .max_uV = 1800000 },
+};
+
+static void msm_camera_vreg_config(int vreg_en)
+{
+ int rc = vreg_en ?
+ regulator_bulk_enable(ARRAY_SIZE(regs_camera), regs_camera) :
+ regulator_bulk_disable(ARRAY_SIZE(regs_camera), regs_camera);
+
+ if (rc)
+ pr_err("%s: could not %sable regulators: %d\n",
+ __func__, vreg_en ? "en" : "dis", rc);
+}
+
+static int config_gpio_table(uint32_t *table, int len)
+{
+ int rc = 0, i = 0;
+
+ for (i = 0; i < len; i++) {
+ rc = gpio_tlmm_config(table[i], GPIO_CFG_ENABLE);
+ if (rc) {
+ pr_err("%s not able to get gpio\n", __func__);
+ for (i--; i >= 0; i--)
+ gpio_tlmm_config(camera_off_gpio_table[i],
+ GPIO_CFG_ENABLE);
+ break;
+ }
+ }
+ return rc;
+}
+
+static struct msm_camera_sensor_info msm_camera_sensor_s5k4e1_data;
+/* TODO: static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data; */
+static int config_camera_on_gpios_rear(void)
+{
+ int rc = 0;
+
+ if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa())
+ msm_camera_vreg_config(1);
+
+ rc = config_gpio_table(camera_on_gpio_table,
+ ARRAY_SIZE(camera_on_gpio_table));
+ if (rc < 0) {
+ pr_err("%s: CAMSENSOR gpio table request"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return rc;
+}
+
+static void config_camera_off_gpios_rear(void)
+{
+ if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa())
+ msm_camera_vreg_config(0);
+
+ config_gpio_table(camera_off_gpio_table,
+ ARRAY_SIZE(camera_off_gpio_table));
+}
+
+static int config_camera_on_gpios_front(void)
+{
+ int rc = 0;
+
+ if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa())
+ msm_camera_vreg_config(1);
+
+ rc = config_gpio_table(camera_on_gpio_table,
+ ARRAY_SIZE(camera_on_gpio_table));
+ if (rc < 0) {
+ pr_err("%s: CAMSENSOR gpio table request"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return rc;
+}
+
+static void config_camera_off_gpios_front(void)
+{
+ if (machine_is_msm7x27a_ffa() || machine_is_msm7625a_ffa())
+ msm_camera_vreg_config(0);
+
+ config_gpio_table(camera_off_gpio_table,
+ ARRAY_SIZE(camera_off_gpio_table));
+}
+
+struct msm_camera_device_platform_data msm_camera_device_data_csi1 = {
+ .camera_gpio_on = config_camera_on_gpios_rear,
+ .camera_gpio_off = config_camera_off_gpios_rear,
+ .ioclk.mclk_clk_rate = 24000000,
+ .ioclk.vfe_clk_rate = 192000000,
+ .csid_core = 1,
+ .is_csic = 1,
+};
+
+struct msm_camera_device_platform_data msm_camera_device_data_csi0 = {
+ .camera_gpio_on = config_camera_on_gpios_front,
+ .camera_gpio_off = config_camera_off_gpios_front,
+ .ioclk.mclk_clk_rate = 24000000,
+ .ioclk.vfe_clk_rate = 192000000,
+ .csid_core = 0,
+};
+
+#ifdef CONFIG_DW9712_ACT
+static struct i2c_board_info s5k4e1_actuator_i2c_info = {
+ I2C_BOARD_INFO("dw9712_act", 0x8C >> 1),
+};
+
+static struct msm_actuator_info s5k4e1_actuator_info = {
+ .board_info = &s5k4e1_actuator_i2c_info,
+ .bus_id = MSM_GSBI0_QUP_I2C_BUS_ID,
+ .vcm_pwd = GPIO_CAM_GP_CAM_PWDN,
+ .vcm_enable = 1,
+};
+#endif
+
+#ifdef CONFIG_S5K4E1
+static struct msm_camera_sensor_flash_data flash_s5k4e1 = {
+ .flash_type = MSM_CAMERA_FLASH_LED,
+ .flash_src = &msm_flash_src
+};
+
+static struct msm_camera_sensor_platform_info sensor_board_info_s5k4e1 = {
+ .mount_angle = 90,
+ .sensor_reset = GPIO_CAM_GP_CAMIF_RESET_N,
+ .sensor_pwd = 85,
+ .vcm_pwd = GPIO_CAM_GP_CAM_PWDN,
+ .vcm_enable = 1,
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_s5k4e1_data = {
+ .sensor_name = "s5k4e1",
+ .sensor_reset_enable = 1,
+ .pdata = &msm_camera_device_data_csi1,
+ .flash_data = &flash_s5k4e1,
+ .sensor_platform_info = &sensor_board_info_s5k4e1,
+ .csi_if = 1,
+ .camera_type = BACK_CAMERA_2D,
+#ifdef CONFIG_DW9712_ACT
+ .actuator_info = &s5k4e1_actuator_info
+#endif
+};
+#endif
+
+#ifdef CONFIG_MT9E013
+static struct msm_camera_sensor_flash_data flash_mt9e013 = {
+ .flash_type = MSM_CAMERA_FLASH_LED,
+ .flash_src = &msm_flash_src
+};
+
+static struct msm_camera_sensor_platform_info sensor_board_info_mt9e013 = {
+ .mount_angle = 90,
+ .sensor_reset = 0,
+ .sensor_pwd = 85,
+ .vcm_pwd = 1,
+ .vcm_enable = 0,
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
+ .sensor_name = "mt9e013",
+ .sensor_reset_enable = 1,
+ .pdata = &msm_camera_device_data_csi1,
+ .flash_data = &flash_mt9e013,
+ .sensor_platform_info = &sensor_board_info_mt9e013,
+ .csi_if = 1,
+ .camera_type = BACK_CAMERA_2D,
+};
+#endif
+
+#ifdef CONFIG_IMX072
+static struct msm_camera_sensor_platform_info imx072_sensor_7627a_info = {
+ .mount_angle = 90
+};
+
+static struct msm_camera_sensor_flash_data flash_imx072 = {
+ .flash_type = MSM_CAMERA_FLASH_LED,
+ .flash_src = &msm_flash_src
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_imx072_data = {
+ .sensor_name = "imx072",
+ .sensor_reset_enable = 1,
+ .sensor_reset = GPIO_CAM_GP_CAMIF_RESET_N, /* TODO 106,*/
+ .sensor_pwd = 85,
+ .vcm_pwd = GPIO_CAM_GP_CAM_PWDN,
+ .vcm_enable = 1,
+ .pdata = &msm_camera_device_data_csi1,
+ .flash_data = &flash_imx072,
+ .sensor_platform_info = &imx072_sensor_7627a_info,
+ .csi_if = 1
+};
+
+static struct platform_device msm_camera_sensor_imx072 = {
+ .name = "msm_camera_imx072",
+ .dev = {
+ .platform_data = &msm_camera_sensor_imx072_data,
+ },
+};
+#endif
+
+#ifdef CONFIG_WEBCAM_OV9726
+static struct msm_camera_sensor_flash_data flash_ov9726 = {
+ .flash_type = MSM_CAMERA_FLASH_LED,
+ .flash_src = &msm_flash_src
+};
+
+static struct msm_camera_sensor_platform_info sensor_board_info_ov9726 = {
+ .mount_angle = 90,
+ .sensor_reset = GPIO_CAM_GP_CAM1MP_XCLR,
+ .sensor_pwd = 85,
+ .vcm_pwd = 1,
+ .vcm_enable = 0,
+};
+
+static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
+ .sensor_name = "ov9726",
+ .sensor_reset_enable = 0,
+ .pdata = &msm_camera_device_data_csi0,
+ .flash_data = &flash_ov9726,
+ .sensor_platform_info = &sensor_board_info_ov9726,
+ .csi_if = 1,
+ .camera_type = FRONT_CAMERA_2D,
+};
+#endif
+
+static void __init msm7x27a_init_cam(void)
+{
+ platform_device_register(&msm7x27a_device_csic0);
+ platform_device_register(&msm7x27a_device_csic1);
+ platform_device_register(&msm7x27a_device_clkctl);
+ platform_device_register(&msm7x27a_device_vfe);
+}
+
+static struct i2c_board_info i2c_camera_devices[] = {
+ #ifdef CONFIG_S5K4E1
+ {
+ I2C_BOARD_INFO("s5k4e1", 0x36),
+ .platform_data = &msm_camera_sensor_s5k4e1_data,
+ },
+ #endif
+ #ifdef CONFIG_WEBCAM_OV9726
+ {
+ I2C_BOARD_INFO("ov9726", 0x10),
+ .platform_data = &msm_camera_sensor_ov9726_data,
+ },
+ #endif
+ #ifdef CONFIG_IMX072
+ {
+ I2C_BOARD_INFO("imx072", 0x34),
+ },
+ #endif
+ #ifdef CONFIG_MT9E013
+ {
+ I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
+ .platform_data = &msm_camera_sensor_mt9e013_data,
+ },
+ #endif
+ {
+ I2C_BOARD_INFO("sc628a", 0x6E),
+ },
+};
+#else
static uint32_t camera_off_gpio_table[] = {
GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
};
@@ -406,28 +689,6 @@
};
#endif
-enum {
- SX150X_CAM,
-};
-
-static struct sx150x_platform_data sx150x_data[] __initdata = {
- [SX150X_CAM] = {
- .gpio_base = GPIO_CAM_EXPANDER_BASE,
- .oscio_is_gpo = false,
- .io_pullup_ena = 0,
- .io_pulldn_ena = 0,
- .io_open_drain_ena = 0x23,
- .irq_summary = -1,
- },
-};
-
-static struct i2c_board_info cam_exp_i2c_info[] __initdata = {
- {
- I2C_BOARD_INFO("sx1508q", 0x22),
- .platform_data = &sx150x_data[SX150X_CAM],
- },
-};
-
static struct i2c_board_info i2c_camera_devices[] = {
#ifdef CONFIG_S5K4E1
{
@@ -493,6 +754,29 @@
&msm_camera_sensor_ov7692,
#endif
};
+#endif
+
+enum {
+ SX150X_CAM,
+};
+
+static struct sx150x_platform_data sx150x_data[] __initdata = {
+ [SX150X_CAM] = {
+ .gpio_base = GPIO_CAM_EXPANDER_BASE,
+ .oscio_is_gpo = false,
+ .io_pullup_ena = 0,
+ .io_pulldn_ena = 0,
+ .io_open_drain_ena = 0x23,
+ .irq_summary = -1,
+ },
+};
+
+static struct i2c_board_info cam_exp_i2c_info[] __initdata = {
+ {
+ I2C_BOARD_INFO("sx1508q", 0x22),
+ .platform_data = &sx150x_data[SX150X_CAM],
+ },
+};
static void __init register_i2c_devices(void)
{
@@ -505,17 +789,19 @@
{
int rc;
+#ifndef CONFIG_MSM_CAMERA_V4L2
if (machine_is_msm7627a_qrd1()) {
qrd1_camera_gpio_cfg();
platform_add_devices(camera_devices_qrd,
ARRAY_SIZE(camera_devices_qrd));
- } else
+ } else if (machine_is_msm7627a_evb())
+ return;
+ else
platform_add_devices(camera_devices_msm,
ARRAY_SIZE(camera_devices_msm));
-
+#endif
if (!machine_is_msm7627a_qrd1())
register_i2c_devices();
-
rc = regulator_bulk_get(NULL, ARRAY_SIZE(regs_camera), regs_camera);
if (rc) {
@@ -530,11 +816,16 @@
return;
}
+#if defined(CONFIG_MSM_CAMERA_V4L2)
+ msm7x27a_init_cam();
+#endif
+#ifndef CONFIG_MSM_CAMERA_V4L2
if (machine_is_msm7627a_qrd1())
i2c_register_board_info(MSM_GSBI0_QUP_I2C_BUS_ID,
i2c_camera_devices_qrd,
ARRAY_SIZE(i2c_camera_devices_qrd));
else
+#endif
i2c_register_board_info(MSM_GSBI0_QUP_I2C_BUS_ID,
i2c_camera_devices,
ARRAY_SIZE(i2c_camera_devices));
diff --git a/arch/arm/mach-msm/board-msm7627a-display.c b/arch/arm/mach-msm/board-msm7627a-display.c
index 32d29b2..8c03d17 100644
--- a/arch/arm/mach-msm/board-msm7627a-display.c
+++ b/arch/arm/mach-msm/board-msm7627a-display.c
@@ -316,6 +316,10 @@
&mipi_dsi_truly_panel_device,
};
+static struct platform_device *evb_fb_devices[] __initdata = {
+
+};
+
void __init msm_msm7627a_allocate_memory_regions(void)
{
void *addr;
@@ -688,6 +692,9 @@
if (machine_is_msm7627a_qrd1())
platform_add_devices(qrd_fb_devices,
ARRAY_SIZE(qrd_fb_devices));
+ else if (machine_is_msm7627a_evb())
+ platform_add_devices(evb_fb_devices,
+ ARRAY_SIZE(evb_fb_devices));
else
platform_add_devices(msm_fb_devices,
ARRAY_SIZE(msm_fb_devices));
diff --git a/arch/arm/mach-msm/board-msm7627a-storage.c b/arch/arm/mach-msm/board-msm7627a-storage.c
index c3657b5..93a6178 100644
--- a/arch/arm/mach-msm/board-msm7627a-storage.c
+++ b/arch/arm/mach-msm/board-msm7627a-storage.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -148,7 +148,7 @@
static int gpio_sdc1_hw_det = 85;
static void gpio_sdc1_config(void)
{
- if (machine_is_msm7627a_qrd1())
+ if (machine_is_msm7627a_qrd1() || machine_is_msm7627a_evb())
gpio_sdc1_hw_det = 42;
}
@@ -248,7 +248,8 @@
} else {
status = gpio_direction_input(gpio_sdc1_hw_det);
if (!status) {
- if (machine_is_msm7627a_qrd1())
+ if (machine_is_msm7627a_qrd1() ||
+ machine_is_msm7627a_evb())
status = !gpio_get_value(gpio_sdc1_hw_det);
else
status = gpio_get_value(gpio_sdc1_hw_det);
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7699aa8..a4f1b32 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -918,6 +918,33 @@
},
};
+static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
+ .levels = &msm_rpmrs_levels[0],
+ .num_levels = ARRAY_SIZE(msm_rpmrs_levels),
+ .vdd_mem_levels = {
+ [MSM_RPMRS_VDD_MEM_RET_LOW] = 500,
+ [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750,
+ [MSM_RPMRS_VDD_MEM_ACTIVE] = 1000,
+ [MSM_RPMRS_VDD_MEM_MAX] = 1250,
+ },
+ .vdd_dig_levels = {
+ [MSM_RPMRS_VDD_DIG_RET_LOW] = 500,
+ [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750,
+ [MSM_RPMRS_VDD_DIG_ACTIVE] = 1000,
+ [MSM_RPMRS_VDD_DIG_MAX] = 1250,
+ },
+ .vdd_mask = 0xFFF,
+ .rpmrs_target_id = {
+ [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
+ [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_APPS_L2_CACHE_CTL,
+ [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_SMPS1_0,
+ [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_SMPS1_1,
+ [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_SMPS0_0,
+ [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_SMPS0_1,
+ [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_TRIGGER_SET_FROM,
+ },
+};
+
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -3727,28 +3754,6 @@
#endif
-#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
-
-static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
- .phys_addr_base = 0x00106000,
- .reg_offsets = {
- [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
- [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
- },
- .phys_size = SZ_8K,
- .log_len = 4096, /* log's buffer length in bytes */
- .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
-};
-
-static struct platform_device msm_rpm_log_device = {
- .name = "msm_rpm_log",
- .id = -1,
- .dev = {
- .platform_data = &msm_rpm_log_pdata,
- },
-};
-#endif
-
#ifdef CONFIG_BATTERY_MSM8X60
static struct msm_charger_platform_data msm_charger_data = {
.safety_time = 180,
@@ -5193,10 +5198,10 @@
#endif
#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
- &msm_rpm_log_device,
+ &msm8660_rpm_log_device,
#endif
#if defined(CONFIG_MSM_RPM_STATS_LOG)
- &msm_rpm_stat_device,
+ &msm8660_rpm_stat_device,
#endif
&msm_device_vidc,
#if (defined(CONFIG_MARIMBA_CORE)) && \
@@ -5232,7 +5237,7 @@
#endif
&msm_tsens_device,
- &msm_rpm_device,
+ &msm8660_rpm_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
@@ -10045,23 +10050,6 @@
PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
}
-#ifdef CONFIG_MSM_RPM
-static struct msm_rpm_platform_data msm_rpm_data = {
- .reg_base_addrs = {
- [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
- [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
- [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
- [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
- },
-
- .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
- .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
- .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
- .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
- .msm_apps_ipc_rpm_val = 4,
-};
-#endif
-
void msm_fusion_setup_pinctrl(void)
{
struct msm_xo_voter *a1;
@@ -10129,11 +10117,8 @@
* Initialize RPM first as other drivers and devices may need
* it for their initialization.
*/
-#ifdef CONFIG_MSM_RPM
- BUG_ON(msm_rpm_init(&msm_rpm_data));
-#endif
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm8660_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
if (msm_xo_init())
pr_err("Failed to initialize XO votes\n");
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index e3664a4..a21abb8 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -658,7 +658,7 @@
.dev.platform_data = &msm_psy_batt_data,
};
-static struct platform_device *qrd1_devices[] __initdata = {
+static struct platform_device *qrd_common_devices[] __initdata = {
&msm_device_dmov,
&msm_device_smd,
&msm_device_uart1,
@@ -793,8 +793,27 @@
__func__, rc);
}
+static void msm7627a_add_io_devices(void)
+{
+ if (machine_is_msm7627a_evb())
+ return;
+
+#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C) || \
+ defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C_MODULE)
+ i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
+ synaptic_i2c_clearpad3k,
+ ARRAY_SIZE(synaptic_i2c_clearpad3k));
+#endif
+ platform_device_register(&hs_pdev);
+
+#ifdef CONFIG_MSM_RPC_VIBRATOR
+ msm_init_pmic_vibrator();
+#endif
+
+}
+
#define UART1DM_RX_GPIO 45
-static void __init msm_qrd1_init(void)
+static void __init msm_qrd_init(void)
{
msm7x2x_misc_init();
msm7627a_init_regulators();
@@ -811,8 +830,10 @@
#endif
msm_device_gadget_peripheral.dev.platform_data =
&msm_gadget_pdata;
- platform_add_devices(qrd1_devices,
- ARRAY_SIZE(qrd1_devices));
+
+ platform_add_devices(qrd_common_devices,
+ ARRAY_SIZE(qrd_common_devices));
+
msm7627a_init_mmc();
#ifdef CONFIG_USB_EHCI_MSM_72K
@@ -830,17 +851,7 @@
msm7627a_camera_init();
-#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C) || \
- defined(CONFIG_TOUCHSCREEN_SYNAPTICS_RMI4_I2C_MODULE)
- i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
- synaptic_i2c_clearpad3k,
- ARRAY_SIZE(synaptic_i2c_clearpad3k));
-#endif
- platform_device_register(&hs_pdev);
-
-#ifdef CONFIG_MSM_RPC_VIBRATOR
- msm_init_pmic_vibrator();
-#endif
+ msm7627a_add_io_devices();
}
static void __init qrd7627a_init_early(void)
@@ -853,7 +864,17 @@
.map_io = msm_common_io_init,
.reserve = msm7627a_reserve,
.init_irq = msm_init_irq,
- .init_machine = msm_qrd1_init,
+ .init_machine = msm_qrd_init,
+ .timer = &msm_timer,
+ .init_early = qrd7627a_init_early,
+ .handle_irq = vic_handle_irq,
+MACHINE_END
+MACHINE_START(MSM7627A_EVB, "QRD MSM7627a EVB")
+ .boot_params = PHYS_OFFSET + 0x100,
+ .map_io = msm_common_io_init,
+ .reserve = msm7627a_reserve,
+ .init_irq = msm_init_irq,
+ .init_machine = msm_qrd_init,
.timer = &msm_timer,
.init_early = qrd7627a_init_early,
.handle_irq = vic_handle_irq,
diff --git a/arch/arm/mach-msm/clock-pcom-lookup.c b/arch/arm/mach-msm/clock-pcom-lookup.c
index 7a3f49e..a98e7f1 100644
--- a/arch/arm/mach-msm/clock-pcom-lookup.c
+++ b/arch/arm/mach-msm/clock-pcom-lookup.c
@@ -273,6 +273,12 @@
CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
CLK_LOOKUP("csi_pclk", csi1_p_clk.c, NULL),
CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, NULL),
+ CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csic.0"),
+ CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_csic.0"),
+ CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_csic.0"),
+ CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csic.1"),
+ CLK_LOOKUP("csi_pclk", csi1_p_clk.c, "msm_csic.1"),
+ CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, "msm_csic.1"),
CLK_LOOKUP("dsi_byte_clk", dsi_byte_clk.c, NULL),
CLK_LOOKUP("dsi_clk", dsi_clk.c, NULL),
CLK_LOOKUP("dsi_esc_clk", dsi_esc_clk.c, NULL),
@@ -324,6 +330,7 @@
CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
CLK_LOOKUP("core_clk", vdc_clk.c, "footswitch-pcom.7"),
CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
+ CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-pcom.8"),
CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 9c77f3d..f3ef2ce 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -25,9 +25,13 @@
#include <sound/msm-dai-q6.h>
#include <sound/apr_audio.h>
#include <mach/msm_bus_board.h>
+#include <mach/rpm.h>
#include "clock.h"
#include "devices.h"
#include "msm_watchdog.h"
+#include "rpm_stats.h"
+#include "rpm_log.h"
+#include "mpm.h"
/* Address of GSBI blocks */
#define MSM_GSBI1_PHYS 0x12440000
@@ -942,3 +946,386 @@
.table = msm_clocks_8064_dummy,
.size = ARRAY_SIZE(msm_clocks_8064_dummy),
};
+
+struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
+ .reg_base_addrs = {
+ [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
+ [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
+ [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
+ [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
+ },
+ .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
+ .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
+ .ipc_rpm_val = 4,
+ .target_id = {
+ MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8),
+ MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1),
+ MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1),
+ MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1),
+ MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1),
+ MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0,
+ APPS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0,
+ APPS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL,
+ APPS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
+ MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0,
+ SYS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0,
+ SYS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL,
+ SYS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30),
+ MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0,
+ MMSS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0,
+ MMSS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL,
+ MMSS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21),
+ MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2),
+ MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2),
+ MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2),
+ MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2),
+ MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2),
+ MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2),
+ MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2),
+ MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2),
+ MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2),
+ MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2),
+ MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2),
+ MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2),
+ MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2),
+ MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2),
+ MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2),
+ MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2),
+ MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2),
+ MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2),
+ MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2),
+ MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2),
+ MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2),
+ MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2),
+ MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2),
+ MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2),
+ MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2),
+ MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2),
+ MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2),
+ MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2),
+ MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2),
+ MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2),
+ MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2),
+ MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2),
+ MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2),
+ MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2),
+ MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2),
+ MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2),
+ MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2),
+ MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2),
+ MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2),
+ MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1),
+ MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1),
+ MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2),
+ MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2),
+ MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2),
+ MSM_RPM_MAP(8064, NCP_0, NCP, 2),
+ MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
+ MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1),
+ MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2),
+ MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1),
+ },
+ .target_status = {
+ MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR),
+ MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR),
+ MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD),
+ MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1),
+ MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2),
+ MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE),
+ MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL),
+ MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK),
+ MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7),
+ MSM_RPM_STATUS_ID_MAP(8064, NCP_0),
+ MSM_RPM_STATUS_ID_MAP(8064, NCP_1),
+ MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS),
+ MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0),
+ MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1),
+ MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE),
+ MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0),
+ MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1),
+ },
+ .target_ctrl_id = {
+ MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR),
+ MSM_RPM_CTRL_MAP(8064, VERSION_MINOR),
+ MSM_RPM_CTRL_MAP(8064, VERSION_BUILD),
+ MSM_RPM_CTRL_MAP(8064, REQ_CTX_0),
+ MSM_RPM_CTRL_MAP(8064, REQ_SEL_0),
+ MSM_RPM_CTRL_MAP(8064, ACK_CTX_0),
+ MSM_RPM_CTRL_MAP(8064, ACK_SEL_0),
+ },
+ .sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE,
+ .sel_notification = MSM_RPM_8064_SEL_NOTIFICATION,
+ .sel_last = MSM_RPM_8064_SEL_LAST,
+ .ver = {3, 0, 0},
+};
+
+struct platform_device apq8064_rpm_device = {
+ .name = "msm_rpm",
+ .id = -1,
+};
+
+static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
+ .phys_addr_base = 0x0010D204,
+ .phys_size = SZ_8K,
+};
+
+struct platform_device apq8064_rpm_stat_device = {
+ .name = "msm_rpm_stat",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_stat_pdata,
+ },
+};
+
+static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
+ .phys_addr_base = 0x0010C000,
+ .reg_offsets = {
+ [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
+ [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
+ },
+ .phys_size = SZ_8K,
+ .log_len = 4096, /* log's buffer length in bytes */
+ .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
+};
+
+struct platform_device apq8064_rpm_log_device = {
+ .name = "msm_rpm_log",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_log_pdata,
+ },
+};
+
+#ifdef CONFIG_MSM_MPM
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
+ [1] = MSM_GPIO_TO_INT(26),
+ [2] = MSM_GPIO_TO_INT(88),
+ [4] = MSM_GPIO_TO_INT(73),
+ [5] = MSM_GPIO_TO_INT(74),
+ [6] = MSM_GPIO_TO_INT(75),
+ [7] = MSM_GPIO_TO_INT(76),
+ [8] = MSM_GPIO_TO_INT(77),
+ [9] = MSM_GPIO_TO_INT(36),
+ [10] = MSM_GPIO_TO_INT(84),
+ [11] = MSM_GPIO_TO_INT(7),
+ [12] = MSM_GPIO_TO_INT(11),
+ [13] = MSM_GPIO_TO_INT(52),
+ [14] = MSM_GPIO_TO_INT(15),
+ [15] = MSM_GPIO_TO_INT(83),
+ [16] = USB3_HS_IRQ,
+ [19] = MSM_GPIO_TO_INT(61),
+ [20] = MSM_GPIO_TO_INT(58),
+ [23] = MSM_GPIO_TO_INT(65),
+ [24] = MSM_GPIO_TO_INT(63),
+ [25] = USB1_HS_IRQ,
+ [27] = HDMI_IRQ,
+ [29] = MSM_GPIO_TO_INT(22),
+ [30] = MSM_GPIO_TO_INT(72),
+ [31] = USB4_HS_IRQ,
+ [33] = MSM_GPIO_TO_INT(44),
+ [34] = MSM_GPIO_TO_INT(39),
+ [35] = MSM_GPIO_TO_INT(19),
+ [36] = MSM_GPIO_TO_INT(23),
+ [37] = MSM_GPIO_TO_INT(41),
+ [38] = MSM_GPIO_TO_INT(30),
+ [41] = MSM_GPIO_TO_INT(42),
+ [42] = MSM_GPIO_TO_INT(56),
+ [43] = MSM_GPIO_TO_INT(55),
+ [44] = MSM_GPIO_TO_INT(50),
+ [45] = MSM_GPIO_TO_INT(49),
+ [46] = MSM_GPIO_TO_INT(47),
+ [47] = MSM_GPIO_TO_INT(45),
+ [48] = MSM_GPIO_TO_INT(38),
+ [49] = MSM_GPIO_TO_INT(34),
+ [50] = MSM_GPIO_TO_INT(32),
+ [51] = MSM_GPIO_TO_INT(29),
+ [52] = MSM_GPIO_TO_INT(18),
+ [53] = MSM_GPIO_TO_INT(10),
+ [54] = MSM_GPIO_TO_INT(81),
+ [55] = MSM_GPIO_TO_INT(6),
+};
+
+static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
+ TLMM_MSM_SUMMARY_IRQ,
+ RPM_APCC_CPU0_GP_HIGH_IRQ,
+ RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+ RPM_APCC_CPU0_GP_LOW_IRQ,
+ RPM_APCC_CPU0_WAKE_UP_IRQ,
+ RPM_APCC_CPU1_GP_HIGH_IRQ,
+ RPM_APCC_CPU1_GP_MEDIUM_IRQ,
+ RPM_APCC_CPU1_GP_LOW_IRQ,
+ RPM_APCC_CPU1_WAKE_UP_IRQ,
+ MSS_TO_APPS_IRQ_0,
+ MSS_TO_APPS_IRQ_1,
+ MSS_TO_APPS_IRQ_2,
+ MSS_TO_APPS_IRQ_3,
+ MSS_TO_APPS_IRQ_4,
+ MSS_TO_APPS_IRQ_5,
+ MSS_TO_APPS_IRQ_6,
+ MSS_TO_APPS_IRQ_7,
+ MSS_TO_APPS_IRQ_8,
+ MSS_TO_APPS_IRQ_9,
+ LPASS_SCSS_GP_LOW_IRQ,
+ LPASS_SCSS_GP_MEDIUM_IRQ,
+ LPASS_SCSS_GP_HIGH_IRQ,
+ SPS_MTI_30,
+ SPS_MTI_31,
+ RIVA_APSS_SPARE_IRQ,
+ RIVA_APPS_WLAN_SMSM_IRQ,
+ RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
+ RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
+};
+
+struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = {
+ .irqs_m2a = msm_mpm_irqs_m2a,
+ .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
+ .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
+ .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
+ .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
+ .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
+ .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
+ .mpm_apps_ipc_val = BIT(1),
+ .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
+
+};
+#endif
diff --git a/arch/arm/mach-msm/devices-8930.c b/arch/arm/mach-msm/devices-8930.c
new file mode 100644
index 0000000..257f372
--- /dev/null
+++ b/arch/arm/mach-msm/devices-8930.c
@@ -0,0 +1,272 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <mach/msm_iomap.h>
+#include <mach/irqs-8930.h>
+#include <mach/rpm.h>
+
+#include "devices.h"
+#include "rpm_log.h"
+#include "rpm_stats.h"
+
+#ifdef CONFIG_MSM_MPM
+#include "mpm.h"
+#endif
+
+struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
+ .reg_base_addrs = {
+ [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
+ [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
+ [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
+ [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
+ },
+ .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
+ .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
+ .ipc_rpm_val = 4,
+ .target_id = {
+ MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
+ MSM_RPM_MAP(8930, TRIGGER_TIMED_0, TRIGGER_TIMED_0, 2),
+ MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
+ MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
+ MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
+ MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
+ MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
+ APPS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
+ APPS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
+ APPS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
+ MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
+ SYS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
+ SYS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
+ SYS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
+ SYSTEM_FABRIC_ARB, 20),
+ MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
+ MMSS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
+ MMSS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
+ MMSS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
+ MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
+ MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
+ MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
+ MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
+ MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
+ MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
+ MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
+ MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
+ MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
+ MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
+ MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
+ MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
+ MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
+ MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
+ MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
+ MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
+ MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
+ MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
+ MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
+ MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
+ MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
+ MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
+ MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
+ MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
+ MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
+ MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
+ MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
+ MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
+ MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
+ MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
+ MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
+ MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
+ MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
+ MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
+ MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
+ MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
+ MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
+ MSM_RPM_MAP(8930, NCP_0, NCP, 2),
+ MSM_RPM_MAP(8930, CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_MAP(8930, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
+ MSM_RPM_MAP(8930, HDMI_SWITCH, HDMI_SWITCH, 1),
+ MSM_RPM_MAP(8930, QDSS_CLK, QDSS_CLK, 1),
+ },
+ .target_status = {
+ MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
+ MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
+ MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
+ MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
+ MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
+ MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
+ MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
+ MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
+ MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
+ MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
+ MSM_RPM_STATUS_ID_MAP(8930, NCP_0),
+ MSM_RPM_STATUS_ID_MAP(8930, NCP_1),
+ MSM_RPM_STATUS_ID_MAP(8930, CXO_BUFFERS),
+ MSM_RPM_STATUS_ID_MAP(8930, USB_OTG_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(8930, HDMI_SWITCH),
+ },
+ .target_ctrl_id = {
+ MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
+ MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
+ MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
+ MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
+ MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
+ MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
+ MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
+ },
+ .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
+ .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
+ .sel_last = MSM_RPM_8930_SEL_LAST,
+ .ver = {3, 0, 0},
+};
+
+struct platform_device msm8930_rpm_device = {
+ .name = "msm_rpm",
+ .id = -1,
+};
+
+static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
+ .phys_addr_base = 0x0010C000,
+ .reg_offsets = {
+ [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
+ [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
+ },
+ .phys_size = SZ_8K,
+ .log_len = 4096, /* log's buffer length in bytes */
+ .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
+};
+
+struct platform_device msm8930_rpm_log_device = {
+ .name = "msm_rpm_log",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_log_pdata,
+ },
+};
+
+static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
+ .phys_addr_base = 0x0010D204,
+ .phys_size = SZ_8K,
+};
+
+struct platform_device msm8930_rpm_stat_device = {
+ .name = "msm_rpm_stat",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_stat_pdata,
+ },
+};
+
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 8fdcbdd..f5d066d 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -38,6 +38,7 @@
#include "devices-msm8x60.h"
#include "footswitch.h"
#include "msm_watchdog.h"
+#include "rpm_log.h"
#include "rpm_stats.h"
#include "pil-q6v4.h"
#include "scm-pas.h"
@@ -1714,7 +1715,7 @@
};
#ifdef CONFIG_MSM_MPM
-static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(46),
[2] = MSM_GPIO_TO_INT(150),
[4] = MSM_GPIO_TO_INT(103),
@@ -1764,7 +1765,7 @@
[55] = MSM_GPIO_TO_INT(14),
};
-static uint16_t msm_mpm_bypassed_apps_irqs[] = {
+static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
@@ -1795,7 +1796,7 @@
RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
};
-struct msm_mpm_device_data msm_mpm_dev_data = {
+struct msm_mpm_device_data msm8960_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -2414,105 +2415,280 @@
};
#endif
-struct msm_rpm_map_data rpm_map_data[] __initdata = {
- MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
- MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
-
- MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
-
- MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
- MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
- MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
- MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
- MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
- MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
- MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
- MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
- MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
- MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
-
- MSM_RPM_MAP(APPS_FABRIC_CFG_HALT_0, APPS_FABRIC_CFG_HALT, 2),
- MSM_RPM_MAP(APPS_FABRIC_CFG_CLKMOD_0, APPS_FABRIC_CFG_CLKMOD, 3),
- MSM_RPM_MAP(APPS_FABRIC_CFG_IOCTL, APPS_FABRIC_CFG_IOCTL, 1),
- MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
-
- MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
- MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
- MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
- MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 29),
-
- MSM_RPM_MAP(MMSS_FABRIC_CFG_HALT_0, MMSS_FABRIC_CFG_HALT, 2),
- MSM_RPM_MAP(MMSS_FABRIC_CFG_CLKMOD_0, MMSS_FABRIC_CFG_CLKMOD, 3),
- MSM_RPM_MAP(MMSS_FABRIC_CFG_IOCTL, MMSS_FABRIC_CFG_IOCTL, 1),
- MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
-
- MSM_RPM_MAP(PM8921_S1_0, PM8921_S1, 2),
- MSM_RPM_MAP(PM8921_S2_0, PM8921_S2, 2),
- MSM_RPM_MAP(PM8921_S3_0, PM8921_S3, 2),
- MSM_RPM_MAP(PM8921_S4_0, PM8921_S4, 2),
- MSM_RPM_MAP(PM8921_S5_0, PM8921_S5, 2),
- MSM_RPM_MAP(PM8921_S6_0, PM8921_S6, 2),
- MSM_RPM_MAP(PM8921_S7_0, PM8921_S7, 2),
- MSM_RPM_MAP(PM8921_S8_0, PM8921_S8, 2),
- MSM_RPM_MAP(PM8921_L1_0, PM8921_L1, 2),
- MSM_RPM_MAP(PM8921_L2_0, PM8921_L2, 2),
- MSM_RPM_MAP(PM8921_L3_0, PM8921_L3, 2),
- MSM_RPM_MAP(PM8921_L4_0, PM8921_L4, 2),
- MSM_RPM_MAP(PM8921_L5_0, PM8921_L5, 2),
- MSM_RPM_MAP(PM8921_L6_0, PM8921_L6, 2),
- MSM_RPM_MAP(PM8921_L7_0, PM8921_L7, 2),
- MSM_RPM_MAP(PM8921_L8_0, PM8921_L8, 2),
- MSM_RPM_MAP(PM8921_L9_0, PM8921_L9, 2),
- MSM_RPM_MAP(PM8921_L10_0, PM8921_L10, 2),
- MSM_RPM_MAP(PM8921_L11_0, PM8921_L11, 2),
- MSM_RPM_MAP(PM8921_L12_0, PM8921_L12, 2),
- MSM_RPM_MAP(PM8921_L13_0, PM8921_L13, 2),
- MSM_RPM_MAP(PM8921_L14_0, PM8921_L14, 2),
- MSM_RPM_MAP(PM8921_L15_0, PM8921_L15, 2),
- MSM_RPM_MAP(PM8921_L16_0, PM8921_L16, 2),
- MSM_RPM_MAP(PM8921_L17_0, PM8921_L17, 2),
- MSM_RPM_MAP(PM8921_L18_0, PM8921_L18, 2),
- MSM_RPM_MAP(PM8921_L19_0, PM8921_L19, 2),
- MSM_RPM_MAP(PM8921_L20_0, PM8921_L20, 2),
- MSM_RPM_MAP(PM8921_L21_0, PM8921_L21, 2),
- MSM_RPM_MAP(PM8921_L22_0, PM8921_L22, 2),
- MSM_RPM_MAP(PM8921_L23_0, PM8921_L23, 2),
- MSM_RPM_MAP(PM8921_L24_0, PM8921_L24, 2),
- MSM_RPM_MAP(PM8921_L25_0, PM8921_L25, 2),
- MSM_RPM_MAP(PM8921_L26_0, PM8921_L26, 2),
- MSM_RPM_MAP(PM8921_L27_0, PM8921_L27, 2),
- MSM_RPM_MAP(PM8921_L28_0, PM8921_L28, 2),
- MSM_RPM_MAP(PM8921_L29_0, PM8921_L29, 2),
- MSM_RPM_MAP(PM8921_CLK1_0, PM8921_CLK1, 2),
- MSM_RPM_MAP(PM8921_CLK2_0, PM8921_CLK2, 2),
- MSM_RPM_MAP(PM8921_LVS1, PM8921_LVS1, 1),
- MSM_RPM_MAP(PM8921_LVS2, PM8921_LVS2, 1),
- MSM_RPM_MAP(PM8921_LVS3, PM8921_LVS3, 1),
- MSM_RPM_MAP(PM8921_LVS4, PM8921_LVS4, 1),
- MSM_RPM_MAP(PM8921_LVS5, PM8921_LVS5, 1),
- MSM_RPM_MAP(PM8921_LVS6, PM8921_LVS6, 1),
- MSM_RPM_MAP(PM8921_LVS7, PM8921_LVS7, 1),
- MSM_RPM_MAP(NCP_0, NCP, 2),
- MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
- MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
- MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
- MSM_RPM_MAP(DDR_DMM_0, DDR_DMM, 2),
- MSM_RPM_MAP(QDSS_CLK, QDSS_CLK, 1),
+struct msm_rpm_platform_data msm8960_rpm_data __initdata = {
+ .reg_base_addrs = {
+ [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
+ [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
+ [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
+ [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
+ },
+ .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
+ .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
+ .ipc_rpm_val = 4,
+ .target_id = {
+ MSM_RPM_MAP(8960, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8960, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(8960, INVALIDATE_0, INVALIDATE, 8),
+ MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8960, RPM_CTL, RPM_CTL, 1),
+ MSM_RPM_MAP(8960, CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(8960, PXO_CLK, PXO_CLK, 1),
+ MSM_RPM_MAP(8960, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8960, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8960, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8960, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8960, SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(8960, CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(8960, MMFPB_CLK, MMFPB_CLK, 1),
+ MSM_RPM_MAP(8960, EBI1_CLK, EBI1_CLK, 1),
+ MSM_RPM_MAP(8960, APPS_FABRIC_CFG_HALT_0,
+ APPS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8960, APPS_FABRIC_CFG_CLKMOD_0,
+ APPS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8960, APPS_FABRIC_CFG_IOCTL,
+ APPS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8960, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
+ MSM_RPM_MAP(8960, SYS_FABRIC_CFG_HALT_0,
+ SYS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8960, SYS_FABRIC_CFG_CLKMOD_0,
+ SYS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8960, SYS_FABRIC_CFG_IOCTL,
+ SYS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8960, SYSTEM_FABRIC_ARB_0,
+ SYSTEM_FABRIC_ARB, 29),
+ MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_HALT_0,
+ MMSS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_CLKMOD_0,
+ MMSS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_IOCTL,
+ MMSS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(8960, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
+ MSM_RPM_MAP(8960, PM8921_S1_0, PM8921_S1, 2),
+ MSM_RPM_MAP(8960, PM8921_S2_0, PM8921_S2, 2),
+ MSM_RPM_MAP(8960, PM8921_S3_0, PM8921_S3, 2),
+ MSM_RPM_MAP(8960, PM8921_S4_0, PM8921_S4, 2),
+ MSM_RPM_MAP(8960, PM8921_S5_0, PM8921_S5, 2),
+ MSM_RPM_MAP(8960, PM8921_S6_0, PM8921_S6, 2),
+ MSM_RPM_MAP(8960, PM8921_S7_0, PM8921_S7, 2),
+ MSM_RPM_MAP(8960, PM8921_S8_0, PM8921_S8, 2),
+ MSM_RPM_MAP(8960, PM8921_L1_0, PM8921_L1, 2),
+ MSM_RPM_MAP(8960, PM8921_L2_0, PM8921_L2, 2),
+ MSM_RPM_MAP(8960, PM8921_L3_0, PM8921_L3, 2),
+ MSM_RPM_MAP(8960, PM8921_L4_0, PM8921_L4, 2),
+ MSM_RPM_MAP(8960, PM8921_L5_0, PM8921_L5, 2),
+ MSM_RPM_MAP(8960, PM8921_L6_0, PM8921_L6, 2),
+ MSM_RPM_MAP(8960, PM8921_L7_0, PM8921_L7, 2),
+ MSM_RPM_MAP(8960, PM8921_L8_0, PM8921_L8, 2),
+ MSM_RPM_MAP(8960, PM8921_L9_0, PM8921_L9, 2),
+ MSM_RPM_MAP(8960, PM8921_L10_0, PM8921_L10, 2),
+ MSM_RPM_MAP(8960, PM8921_L11_0, PM8921_L11, 2),
+ MSM_RPM_MAP(8960, PM8921_L12_0, PM8921_L12, 2),
+ MSM_RPM_MAP(8960, PM8921_L13_0, PM8921_L13, 2),
+ MSM_RPM_MAP(8960, PM8921_L14_0, PM8921_L14, 2),
+ MSM_RPM_MAP(8960, PM8921_L15_0, PM8921_L15, 2),
+ MSM_RPM_MAP(8960, PM8921_L16_0, PM8921_L16, 2),
+ MSM_RPM_MAP(8960, PM8921_L17_0, PM8921_L17, 2),
+ MSM_RPM_MAP(8960, PM8921_L18_0, PM8921_L18, 2),
+ MSM_RPM_MAP(8960, PM8921_L19_0, PM8921_L19, 2),
+ MSM_RPM_MAP(8960, PM8921_L20_0, PM8921_L20, 2),
+ MSM_RPM_MAP(8960, PM8921_L21_0, PM8921_L21, 2),
+ MSM_RPM_MAP(8960, PM8921_L22_0, PM8921_L22, 2),
+ MSM_RPM_MAP(8960, PM8921_L23_0, PM8921_L23, 2),
+ MSM_RPM_MAP(8960, PM8921_L24_0, PM8921_L24, 2),
+ MSM_RPM_MAP(8960, PM8921_L25_0, PM8921_L25, 2),
+ MSM_RPM_MAP(8960, PM8921_L26_0, PM8921_L26, 2),
+ MSM_RPM_MAP(8960, PM8921_L27_0, PM8921_L27, 2),
+ MSM_RPM_MAP(8960, PM8921_L28_0, PM8921_L28, 2),
+ MSM_RPM_MAP(8960, PM8921_L29_0, PM8921_L29, 2),
+ MSM_RPM_MAP(8960, PM8921_CLK1_0, PM8921_CLK1, 2),
+ MSM_RPM_MAP(8960, PM8921_CLK2_0, PM8921_CLK2, 2),
+ MSM_RPM_MAP(8960, PM8921_LVS1, PM8921_LVS1, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS2, PM8921_LVS2, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS3, PM8921_LVS3, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS4, PM8921_LVS4, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS5, PM8921_LVS5, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS6, PM8921_LVS6, 1),
+ MSM_RPM_MAP(8960, PM8921_LVS7, PM8921_LVS7, 1),
+ MSM_RPM_MAP(8960, NCP_0, NCP, 2),
+ MSM_RPM_MAP(8960, CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_MAP(8960, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
+ MSM_RPM_MAP(8960, HDMI_SWITCH, HDMI_SWITCH, 1),
+ MSM_RPM_MAP(8960, DDR_DMM_0, DDR_DMM, 2),
+ MSM_RPM_MAP(8960, QDSS_CLK, QDSS_CLK, 1),
+ },
+ .target_status = {
+ MSM_RPM_STATUS_ID_MAP(8960, VERSION_MAJOR),
+ MSM_RPM_STATUS_ID_MAP(8960, VERSION_MINOR),
+ MSM_RPM_STATUS_ID_MAP(8960, VERSION_BUILD),
+ MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_1),
+ MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_2),
+ MSM_RPM_STATUS_ID_MAP(8960, RESERVED_SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8960, SEQUENCE),
+ MSM_RPM_STATUS_ID_MAP(8960, RPM_CTL),
+ MSM_RPM_STATUS_ID_MAP(8960, CXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, PXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, SYSTEM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, MM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, DAYTONA_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, SFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, CFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, MMFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, EBI1_CLK),
+ MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8960, SYSTEM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(8960, MM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S1_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S1_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S2_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S2_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S3_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S3_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S4_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S4_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S5_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S5_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S6_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S6_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S7_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S7_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S8_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_S8_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L1_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L1_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L2_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L2_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L3_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L3_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L4_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L4_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L5_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L5_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L6_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L6_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L7_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L7_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L8_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L8_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L9_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L9_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L10_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L10_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L11_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L11_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L12_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L12_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L13_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L13_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L14_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L14_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L15_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L15_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L16_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L16_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L17_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L17_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L18_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L18_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L19_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L19_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L20_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L20_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L21_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L21_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L22_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L22_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L23_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L23_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L24_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L24_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L25_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L25_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L26_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L26_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L27_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L27_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L28_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L28_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L29_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_L29_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK1_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK1_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK2_0),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK2_1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS1),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS2),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS3),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS4),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS5),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS6),
+ MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS7),
+ MSM_RPM_STATUS_ID_MAP(8960, NCP_0),
+ MSM_RPM_STATUS_ID_MAP(8960, NCP_1),
+ MSM_RPM_STATUS_ID_MAP(8960, CXO_BUFFERS),
+ MSM_RPM_STATUS_ID_MAP(8960, USB_OTG_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(8960, HDMI_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(8960, DDR_DMM_0),
+ MSM_RPM_STATUS_ID_MAP(8960, DDR_DMM_1),
+ MSM_RPM_STATUS_ID_MAP(8960, EBI1_CH0_RANGE),
+ MSM_RPM_STATUS_ID_MAP(8960, EBI1_CH1_RANGE),
+ },
+ .target_ctrl_id = {
+ MSM_RPM_CTRL_MAP(8960, VERSION_MAJOR),
+ MSM_RPM_CTRL_MAP(8960, VERSION_MINOR),
+ MSM_RPM_CTRL_MAP(8960, VERSION_BUILD),
+ MSM_RPM_CTRL_MAP(8960, REQ_CTX_0),
+ MSM_RPM_CTRL_MAP(8960, REQ_SEL_0),
+ MSM_RPM_CTRL_MAP(8960, ACK_CTX_0),
+ MSM_RPM_CTRL_MAP(8960, ACK_SEL_0),
+ },
+ .sel_invalidate = MSM_RPM_8960_SEL_INVALIDATE,
+ .sel_notification = MSM_RPM_8960_SEL_NOTIFICATION,
+ .sel_last = MSM_RPM_8960_SEL_LAST,
+ .ver = {3, 0, 0},
};
-unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
-
-struct platform_device msm_rpm_device = {
+struct platform_device msm8960_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
+static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
+ .phys_addr_base = 0x0010C000,
+ .reg_offsets = {
+ [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
+ [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
+ },
+ .phys_size = SZ_8K,
+ .log_len = 4096, /* log's buffer length in bytes */
+ .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
+};
+
+struct platform_device msm8960_rpm_log_device = {
+ .name = "msm_rpm_log",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_log_pdata,
+ },
+};
+
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x0010D204,
.phys_size = SZ_8K,
};
-struct platform_device msm_rpm_stat_device = {
+struct platform_device msm8960_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index 314d064..8b0c9bd 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -30,12 +30,14 @@
#include <asm/hardware/cache-l2x0.h>
#include <mach/msm_sps.h>
#include <mach/dma.h>
+#include <mach/pm.h>
#include "devices.h"
#include "mpm.h"
#include "spm.h"
-#include <mach/pm.h>
#include "rpm_resources.h"
#include "msm_watchdog.h"
+#include "rpm_stats.h"
+#include "rpm_log.h"
/* Address of GSBI blocks */
#define MSM_GSBI1_PHYS 0x16000000
@@ -724,72 +726,148 @@
static int __init l2x0_cache_init(void){ return 0; }
#endif
-struct msm_rpm_map_data rpm_map_data[] __initdata = {
- MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
- MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
-
- MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
-
- MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
- MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
- MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
- MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
- MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
- MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
-
- MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
- MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
- MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
- MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 27),
-
- MSM_RPM_MAP(PM8018_S1_0, PM8018_S1, 2),
- MSM_RPM_MAP(PM8018_S2_0, PM8018_S2, 2),
- MSM_RPM_MAP(PM8018_S3_0, PM8018_S3, 2),
- MSM_RPM_MAP(PM8018_S4_0, PM8018_S4, 2),
- MSM_RPM_MAP(PM8018_S5_0, PM8018_S5, 2),
- MSM_RPM_MAP(PM8018_L1_0, PM8018_L1, 2),
- MSM_RPM_MAP(PM8018_L2_0, PM8018_L2, 2),
- MSM_RPM_MAP(PM8018_L3_0, PM8018_L3, 2),
- MSM_RPM_MAP(PM8018_L4_0, PM8018_L4, 2),
- MSM_RPM_MAP(PM8018_L5_0, PM8018_L5, 2),
- MSM_RPM_MAP(PM8018_L6_0, PM8018_L6, 2),
- MSM_RPM_MAP(PM8018_L7_0, PM8018_L7, 2),
- MSM_RPM_MAP(PM8018_L8_0, PM8018_L8, 2),
- MSM_RPM_MAP(PM8018_L9_0, PM8018_L9, 2),
- MSM_RPM_MAP(PM8018_L10_0, PM8018_L10, 2),
- MSM_RPM_MAP(PM8018_L11_0, PM8018_L11, 2),
- MSM_RPM_MAP(PM8018_L12_0, PM8018_L12, 2),
- MSM_RPM_MAP(PM8018_L13_0, PM8018_L13, 2),
- MSM_RPM_MAP(PM8018_L14_0, PM8018_L14, 2),
- MSM_RPM_MAP(PM8018_LVS1, PM8018_LVS1, 1),
- MSM_RPM_MAP(NCP_0, NCP, 2),
- MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
- MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
- MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
-};
-unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
-
-static struct msm_rpm_platform_data msm_rpm_data = {
+struct msm_rpm_platform_data msm9615_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
-
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
- .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
- .irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
- .msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
- .msm_apps_ipc_rpm_val = 4,
+ .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
+ .ipc_rpm_val = 4,
+ .target_id = {
+ MSM_RPM_MAP(9615, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(9615, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
+ MSM_RPM_MAP(9615, INVALIDATE_0, INVALIDATE, 8),
+ MSM_RPM_MAP(9615, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(9615, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(9615, RPM_CTL, RPM_CTL, 1),
+ MSM_RPM_MAP(9615, CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(9615, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(9615, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(9615, SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(9615, CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(9615, EBI1_CLK, EBI1_CLK, 1),
+ MSM_RPM_MAP(9615, SYS_FABRIC_CFG_HALT_0,
+ SYS_FABRIC_CFG_HALT, 2),
+ MSM_RPM_MAP(9615, SYS_FABRIC_CFG_CLKMOD_0,
+ SYS_FABRIC_CFG_CLKMOD, 3),
+ MSM_RPM_MAP(9615, SYS_FABRIC_CFG_IOCTL,
+ SYS_FABRIC_CFG_IOCTL, 1),
+ MSM_RPM_MAP(9615, SYSTEM_FABRIC_ARB_0,
+ SYSTEM_FABRIC_ARB, 27),
+ MSM_RPM_MAP(9615, PM8018_S1_0, PM8018_S1, 2),
+ MSM_RPM_MAP(9615, PM8018_S2_0, PM8018_S2, 2),
+ MSM_RPM_MAP(9615, PM8018_S3_0, PM8018_S3, 2),
+ MSM_RPM_MAP(9615, PM8018_S4_0, PM8018_S4, 2),
+ MSM_RPM_MAP(9615, PM8018_S5_0, PM8018_S5, 2),
+ MSM_RPM_MAP(9615, PM8018_L1_0, PM8018_L1, 2),
+ MSM_RPM_MAP(9615, PM8018_L2_0, PM8018_L2, 2),
+ MSM_RPM_MAP(9615, PM8018_L3_0, PM8018_L3, 2),
+ MSM_RPM_MAP(9615, PM8018_L4_0, PM8018_L4, 2),
+ MSM_RPM_MAP(9615, PM8018_L5_0, PM8018_L5, 2),
+ MSM_RPM_MAP(9615, PM8018_L6_0, PM8018_L6, 2),
+ MSM_RPM_MAP(9615, PM8018_L7_0, PM8018_L7, 2),
+ MSM_RPM_MAP(9615, PM8018_L8_0, PM8018_L8, 2),
+ MSM_RPM_MAP(9615, PM8018_L9_0, PM8018_L9, 2),
+ MSM_RPM_MAP(9615, PM8018_L10_0, PM8018_L10, 2),
+ MSM_RPM_MAP(9615, PM8018_L11_0, PM8018_L11, 2),
+ MSM_RPM_MAP(9615, PM8018_L12_0, PM8018_L12, 2),
+ MSM_RPM_MAP(9615, PM8018_L13_0, PM8018_L13, 2),
+ MSM_RPM_MAP(9615, PM8018_L14_0, PM8018_L14, 2),
+ MSM_RPM_MAP(9615, PM8018_LVS1, PM8018_LVS1, 1),
+ MSM_RPM_MAP(9615, NCP_0, NCP, 2),
+ MSM_RPM_MAP(9615, CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_MAP(9615, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
+ MSM_RPM_MAP(9615, HDMI_SWITCH, HDMI_SWITCH, 1),
+ },
+ .target_status = {
+ MSM_RPM_STATUS_ID_MAP(9615, VERSION_MAJOR),
+ MSM_RPM_STATUS_ID_MAP(9615, VERSION_MINOR),
+ MSM_RPM_STATUS_ID_MAP(9615, VERSION_BUILD),
+ MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_1),
+ MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_2),
+ MSM_RPM_STATUS_ID_MAP(9615, RESERVED_SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(9615, SEQUENCE),
+ MSM_RPM_STATUS_ID_MAP(9615, RPM_CTL),
+ MSM_RPM_STATUS_ID_MAP(9615, CXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, SYSTEM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, DAYTONA_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, SFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, CFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, EBI1_CLK),
+ MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_HALT),
+ MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_CLKMOD),
+ MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_IOCTL),
+ MSM_RPM_STATUS_ID_MAP(9615, SYSTEM_FABRIC_ARB),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S1_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S1_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S2_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S2_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S3_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S3_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S4_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S4_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S5_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_S5_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L1_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L1_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L2_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L2_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L3_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L3_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L4_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L4_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L5_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L5_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L6_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L6_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L7_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L7_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L8_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L8_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L9_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L9_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L10_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L10_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L11_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L11_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L12_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L12_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L13_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L13_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L14_0),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_L14_1),
+ MSM_RPM_STATUS_ID_MAP(9615, PM8018_LVS1),
+ MSM_RPM_STATUS_ID_MAP(9615, NCP_0),
+ MSM_RPM_STATUS_ID_MAP(9615, NCP_1),
+ MSM_RPM_STATUS_ID_MAP(9615, CXO_BUFFERS),
+ MSM_RPM_STATUS_ID_MAP(9615, USB_OTG_SWITCH),
+ MSM_RPM_STATUS_ID_MAP(9615, HDMI_SWITCH),
+ },
+ .target_ctrl_id = {
+ MSM_RPM_CTRL_MAP(9615, VERSION_MAJOR),
+ MSM_RPM_CTRL_MAP(9615, VERSION_MINOR),
+ MSM_RPM_CTRL_MAP(9615, VERSION_BUILD),
+ MSM_RPM_CTRL_MAP(9615, REQ_CTX_0),
+ MSM_RPM_CTRL_MAP(9615, REQ_SEL_0),
+ MSM_RPM_CTRL_MAP(9615, ACK_CTX_0),
+ MSM_RPM_CTRL_MAP(9615, ACK_SEL_0),
+ },
+ .sel_invalidate = MSM_RPM_9615_SEL_INVALIDATE,
+ .sel_notification = MSM_RPM_9615_SEL_NOTIFICATION,
+ .sel_last = MSM_RPM_9615_SEL_LAST,
+ .ver = {3, 0, 0},
};
-struct platform_device msm_rpm_device = {
+struct platform_device msm9615_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
-static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[4] = MSM_GPIO_TO_INT(30),
[5] = MSM_GPIO_TO_INT(59),
[6] = MSM_GPIO_TO_INT(81),
@@ -833,7 +911,7 @@
[55] = MSM_GPIO_TO_INT(27),
};
-static uint16_t msm_mpm_bypassed_apps_irqs[] = {
+static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
@@ -848,7 +926,7 @@
A2_BAM_IRQ,
};
-struct msm_mpm_device_data msm_mpm_dev_data = {
+struct msm_mpm_device_data msm9615_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -911,7 +989,6 @@
true,
100, 8000, 100000, 1,
},
-
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
@@ -938,12 +1015,70 @@
},
};
+static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
+ .levels = &msm_rpmrs_levels[0],
+ .num_levels = ARRAY_SIZE(msm_rpmrs_levels),
+ .vdd_mem_levels = {
+ [MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
+ [MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
+ [MSM_RPMRS_VDD_MEM_MAX] = 1150000,
+ },
+ .vdd_dig_levels = {
+ [MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
+ [MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
+ [MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
+ [MSM_RPMRS_VDD_DIG_MAX] = 1150000,
+ },
+ .vdd_mask = 0x7FFFFF,
+ .rpmrs_target_id = {
+ [MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_CXO_CLK,
+ [MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
+ [MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8018_S1_0,
+ [MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8018_S1_1,
+ [MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8018_L9_0,
+ [MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8018_L9_1,
+ [MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
+ },
+};
+
+static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
+ .phys_addr_base = 0x0010D204,
+ .phys_size = SZ_8K,
+};
+
+struct platform_device msm9615_rpm_stat_device = {
+ .name = "msm_rpm_stat",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_stat_pdata,
+ },
+};
+
+static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
+ .phys_addr_base = 0x0010AC00,
+ .reg_offsets = {
+ [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
+ [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
+ },
+ .phys_size = SZ_8K,
+ .log_len = 4096, /* log's buffer length in bytes */
+ .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
+};
+
+struct platform_device msm9615_rpm_log_device = {
+ .name = "msm_rpm_log",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_log_pdata,
+ },
+};
+
void __init msm9615_device_init(void)
{
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
- BUG_ON(msm_rpm_init(&msm_rpm_data));
- BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
- ARRAY_SIZE(msm_rpmrs_levels)));
+ BUG_ON(msm_rpm_init(&msm9615_rpm_data));
+ BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
}
#define MSM_SHARED_RAM_PHYS 0x40000000
@@ -958,7 +1093,13 @@
void __init msm9615_init_irq(void)
{
- msm_mpm_irq_extn_init();
+ struct msm_mpm_device_data *data = NULL;
+
+#ifdef CONFIG_MSM_MPM
+ data = &msm9615_mpm_dev_data;
+#endif
+
+ msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 97cb263..104b2e0 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -523,6 +523,73 @@
return platform_device_register(pdev);
}
+#ifdef CONFIG_MSM_CAMERA_V4L2
+static struct resource msm_csic0_resources[] = {
+ {
+ .name = "csic",
+ .start = 0xA0F00000,
+ .end = 0xA0F00000 + 0x00100000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "csic",
+ .start = INT_CSI_IRQ_0,
+ .end = INT_CSI_IRQ_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource msm_csic1_resources[] = {
+ {
+ .name = "csic",
+ .start = 0xA1000000,
+ .end = 0xA1000000 + 0x00100000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "csic",
+ .start = INT_CSI_IRQ_1,
+ .end = INT_CSI_IRQ_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm7x27a_device_csic0 = {
+ .name = "msm_csic",
+ .id = 0,
+ .resource = msm_csic0_resources,
+ .num_resources = ARRAY_SIZE(msm_csic0_resources),
+};
+
+struct platform_device msm7x27a_device_csic1 = {
+ .name = "msm_csic",
+ .id = 1,
+ .resource = msm_csic1_resources,
+ .num_resources = ARRAY_SIZE(msm_csic1_resources),
+};
+
+static struct resource msm_clkctl_resources[] = {
+ {
+ .name = "clk_ctl",
+ .start = MSM_CLK_CTL_PHYS,
+ .end = MSM_CLK_CTL_PHYS + MSM_CLK_CTL_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+struct platform_device msm7x27a_device_clkctl = {
+ .name = "msm_clk_ctl",
+ .id = 0,
+ .resource = msm_clkctl_resources,
+ .num_resources = ARRAY_SIZE(msm_clkctl_resources),
+};
+
+struct platform_device msm7x27a_device_vfe = {
+ .name = "msm_vfe",
+ .id = 0,
+};
+
+#endif
+
#define MDP_BASE 0xAA200000
#define MIPI_DSI_HW_BASE 0xA1100000
diff --git a/arch/arm/mach-msm/devices-msm7x2xa.h b/arch/arm/mach-msm/devices-msm7x2xa.h
index d04dfe0..a9c87ba 100644
--- a/arch/arm/mach-msm/devices-msm7x2xa.h
+++ b/arch/arm/mach-msm/devices-msm7x2xa.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -19,4 +19,8 @@
void __init msm_init_pmic_vibrator(void);
void __init msm7x25a_kgsl_3d0_init(void);
int __init msm7x2x_misc_init(void);
+extern struct platform_device msm7x27a_device_vfe;
+extern struct platform_device msm7x27a_device_csic0;
+extern struct platform_device msm7x27a_device_csic1;
+extern struct platform_device msm7x27a_device_clkctl;
#endif
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 4196462..a433a89 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -52,6 +52,7 @@
#include <mach/rpm.h>
#include <mach/board.h>
#include <sound/apr_audio.h>
+#include "rpm_log.h"
#include "rpm_stats.h"
#include "mpm.h"
#include "msm_watchdog.h"
@@ -170,7 +171,13 @@
void __init msm8x60_init_irq(void)
{
- msm_mpm_irq_extn_init();
+ struct msm_mpm_device_data *data = NULL;
+
+#ifdef CONFIG_MSM_MPM
+ data = &msm8660_mpm_dev_data;
+#endif
+
+ msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
@@ -2175,13 +2182,34 @@
},
};
+#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
+static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
+ .phys_addr_base = 0x00106000,
+ .reg_offsets = {
+ [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
+ [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
+ },
+ .phys_size = SZ_8K,
+ .log_len = 4096, /* log's buffer length in bytes */
+ .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
+};
+
+struct platform_device msm8660_rpm_log_device = {
+ .name = "msm_rpm_log",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_log_pdata,
+ },
+};
+#endif
+
#if defined(CONFIG_MSM_RPM_STATS_LOG)
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x00107E04,
.phys_size = SZ_8K,
};
-struct platform_device msm_rpm_stat_device = {
+struct platform_device msm8660_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
@@ -2191,7 +2219,7 @@
#endif
#ifdef CONFIG_MSM_MPM
-static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
+static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(61),
[4] = MSM_GPIO_TO_INT(87),
[5] = MSM_GPIO_TO_INT(88),
@@ -2246,7 +2274,7 @@
[59] = MSM_GPIO_TO_INT(129),
};
-static uint16_t msm_mpm_bypassed_apps_irqs[] = {
+static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_SCSS_CPU0_GP_HIGH_IRQ,
RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
@@ -2273,7 +2301,7 @@
SPS_MTI_31,
};
-struct msm_mpm_device_data msm_mpm_dev_data = {
+struct msm_mpm_device_data msm8660_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -2433,104 +2461,265 @@
};
unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
-#ifdef CONFIG_MSM_RPM
-struct msm_rpm_map_data rpm_map_data[] __initdata = {
- MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
- MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
- MSM_RPM_MAP(TRIGGER_SET_FROM, TRIGGER_SET, 1),
- MSM_RPM_MAP(TRIGGER_SET_TO, TRIGGER_SET, 1),
- MSM_RPM_MAP(TRIGGER_SET_TRIGGER, TRIGGER_SET, 1),
- MSM_RPM_MAP(TRIGGER_CLEAR_FROM, TRIGGER_CLEAR, 1),
- MSM_RPM_MAP(TRIGGER_CLEAR_TO, TRIGGER_CLEAR, 1),
- MSM_RPM_MAP(TRIGGER_CLEAR_TRIGGER, TRIGGER_CLEAR, 1),
+struct msm_rpm_platform_data msm8660_rpm_data __initdata = {
+ .reg_base_addrs = {
+ [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
+ [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
+ [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
+ [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
+ },
+ .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
+ .ipc_rpm_reg = MSM_GCC_BASE + 0x008,
+ .ipc_rpm_val = 4,
+ .target_id = {
+ MSM_RPM_MAP(8660, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 8),
+ MSM_RPM_MAP(8660, NOTIFICATION_REGISTERED_0, NOTIFICATION, 8),
+ MSM_RPM_MAP(8660, INVALIDATE_0, INVALIDATE, 8),
+ MSM_RPM_MAP(8660, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8660, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
+ MSM_RPM_MAP(8660, TRIGGER_SET_FROM, TRIGGER_SET, 1),
+ MSM_RPM_MAP(8660, TRIGGER_SET_TO, TRIGGER_SET, 1),
+ MSM_RPM_MAP(8660, TRIGGER_SET_TRIGGER, TRIGGER_SET, 1),
+ MSM_RPM_MAP(8660, TRIGGER_CLEAR_FROM, TRIGGER_CLEAR, 1),
+ MSM_RPM_MAP(8660, TRIGGER_CLEAR_TO, TRIGGER_CLEAR, 1),
+ MSM_RPM_MAP(8660, TRIGGER_CLEAR_TRIGGER, TRIGGER_CLEAR, 1),
- MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
- MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
- MSM_RPM_MAP(PLL_4, PLL_4, 1),
- MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
- MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
- MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
- MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
- MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
- MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
- MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
- MSM_RPM_MAP(SMI_CLK, SMI_CLK, 1),
- MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
+ MSM_RPM_MAP(8660, CXO_CLK, CXO_CLK, 1),
+ MSM_RPM_MAP(8660, PXO_CLK, PXO_CLK, 1),
+ MSM_RPM_MAP(8660, PLL_4, PLL_4, 1),
+ MSM_RPM_MAP(8660, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8660, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8660, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8660, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
+ MSM_RPM_MAP(8660, SFPB_CLK, SFPB_CLK, 1),
+ MSM_RPM_MAP(8660, CFPB_CLK, CFPB_CLK, 1),
+ MSM_RPM_MAP(8660, MMFPB_CLK, MMFPB_CLK, 1),
+ MSM_RPM_MAP(8660, SMI_CLK, SMI_CLK, 1),
+ MSM_RPM_MAP(8660, EBI1_CLK, EBI1_CLK, 1),
- MSM_RPM_MAP(APPS_L2_CACHE_CTL, APPS_L2_CACHE_CTL, 1),
+ MSM_RPM_MAP(8660, APPS_L2_CACHE_CTL, APPS_L2_CACHE_CTL, 1),
- MSM_RPM_MAP(APPS_FABRIC_HALT_0, APPS_FABRIC_HALT, 2),
- MSM_RPM_MAP(APPS_FABRIC_CLOCK_MODE_0, APPS_FABRIC_CLOCK_MODE, 3),
- MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
+ MSM_RPM_MAP(8660, APPS_FABRIC_HALT_0, APPS_FABRIC_HALT, 2),
+ MSM_RPM_MAP(8660, APPS_FABRIC_CLOCK_MODE_0,
+ APPS_FABRIC_CLOCK_MODE, 3),
+ MSM_RPM_MAP(8660, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
- MSM_RPM_MAP(SYSTEM_FABRIC_HALT_0, SYSTEM_FABRIC_HALT, 2),
- MSM_RPM_MAP(SYSTEM_FABRIC_CLOCK_MODE_0, SYSTEM_FABRIC_CLOCK_MODE, 3),
- MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 22),
+ MSM_RPM_MAP(8660, SYSTEM_FABRIC_HALT_0, SYSTEM_FABRIC_HALT, 2),
+ MSM_RPM_MAP(8660, SYSTEM_FABRIC_CLOCK_MODE_0,
+ SYSTEM_FABRIC_CLOCK_MODE, 3),
+ MSM_RPM_MAP(8660, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 22),
- MSM_RPM_MAP(MM_FABRIC_HALT_0, MM_FABRIC_HALT, 2),
- MSM_RPM_MAP(MM_FABRIC_CLOCK_MODE_0, MM_FABRIC_CLOCK_MODE, 3),
- MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
+ MSM_RPM_MAP(8660, MM_FABRIC_HALT_0, MM_FABRIC_HALT, 2),
+ MSM_RPM_MAP(8660, MM_FABRIC_CLOCK_MODE_0,
+ MM_FABRIC_CLOCK_MODE, 3),
+ MSM_RPM_MAP(8660, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
- MSM_RPM_MAP(SMPS0B_0, SMPS0B, 2),
- MSM_RPM_MAP(SMPS1B_0, SMPS1B, 2),
- MSM_RPM_MAP(SMPS2B_0, SMPS2B, 2),
- MSM_RPM_MAP(SMPS3B_0, SMPS3B, 2),
- MSM_RPM_MAP(SMPS4B_0, SMPS4B, 2),
- MSM_RPM_MAP(LDO0B_0, LDO0B, 2),
- MSM_RPM_MAP(LDO1B_0, LDO1B, 2),
- MSM_RPM_MAP(LDO2B_0, LDO2B, 2),
- MSM_RPM_MAP(LDO3B_0, LDO3B, 2),
- MSM_RPM_MAP(LDO4B_0, LDO4B, 2),
- MSM_RPM_MAP(LDO5B_0, LDO5B, 2),
- MSM_RPM_MAP(LDO6B_0, LDO6B, 2),
- MSM_RPM_MAP(LVS0B, LVS0B, 1),
- MSM_RPM_MAP(LVS1B, LVS1B, 1),
- MSM_RPM_MAP(LVS2B, LVS2B, 1),
- MSM_RPM_MAP(LVS3B, LVS3B, 1),
- MSM_RPM_MAP(MVS, MVS, 1),
+ MSM_RPM_MAP(8660, SMPS0B_0, SMPS0B, 2),
+ MSM_RPM_MAP(8660, SMPS1B_0, SMPS1B, 2),
+ MSM_RPM_MAP(8660, SMPS2B_0, SMPS2B, 2),
+ MSM_RPM_MAP(8660, SMPS3B_0, SMPS3B, 2),
+ MSM_RPM_MAP(8660, SMPS4B_0, SMPS4B, 2),
+ MSM_RPM_MAP(8660, LDO0B_0, LDO0B, 2),
+ MSM_RPM_MAP(8660, LDO1B_0, LDO1B, 2),
+ MSM_RPM_MAP(8660, LDO2B_0, LDO2B, 2),
+ MSM_RPM_MAP(8660, LDO3B_0, LDO3B, 2),
+ MSM_RPM_MAP(8660, LDO4B_0, LDO4B, 2),
+ MSM_RPM_MAP(8660, LDO5B_0, LDO5B, 2),
+ MSM_RPM_MAP(8660, LDO6B_0, LDO6B, 2),
+ MSM_RPM_MAP(8660, LVS0B, LVS0B, 1),
+ MSM_RPM_MAP(8660, LVS1B, LVS1B, 1),
+ MSM_RPM_MAP(8660, LVS2B, LVS2B, 1),
+ MSM_RPM_MAP(8660, LVS3B, LVS3B, 1),
+ MSM_RPM_MAP(8660, MVS, MVS, 1),
- MSM_RPM_MAP(SMPS0_0, SMPS0, 2),
- MSM_RPM_MAP(SMPS1_0, SMPS1, 2),
- MSM_RPM_MAP(SMPS2_0, SMPS2, 2),
- MSM_RPM_MAP(SMPS3_0, SMPS3, 2),
- MSM_RPM_MAP(SMPS4_0, SMPS4, 2),
- MSM_RPM_MAP(LDO0_0, LDO0, 2),
- MSM_RPM_MAP(LDO1_0, LDO1, 2),
- MSM_RPM_MAP(LDO2_0, LDO2, 2),
- MSM_RPM_MAP(LDO3_0, LDO3, 2),
- MSM_RPM_MAP(LDO4_0, LDO4, 2),
- MSM_RPM_MAP(LDO5_0, LDO5, 2),
- MSM_RPM_MAP(LDO6_0, LDO6, 2),
- MSM_RPM_MAP(LDO7_0, LDO7, 2),
- MSM_RPM_MAP(LDO8_0, LDO8, 2),
- MSM_RPM_MAP(LDO9_0, LDO9, 2),
- MSM_RPM_MAP(LDO10_0, LDO10, 2),
- MSM_RPM_MAP(LDO11_0, LDO11, 2),
- MSM_RPM_MAP(LDO12_0, LDO12, 2),
- MSM_RPM_MAP(LDO13_0, LDO13, 2),
- MSM_RPM_MAP(LDO14_0, LDO14, 2),
- MSM_RPM_MAP(LDO15_0, LDO15, 2),
- MSM_RPM_MAP(LDO16_0, LDO16, 2),
- MSM_RPM_MAP(LDO17_0, LDO17, 2),
- MSM_RPM_MAP(LDO18_0, LDO18, 2),
- MSM_RPM_MAP(LDO19_0, LDO19, 2),
- MSM_RPM_MAP(LDO20_0, LDO20, 2),
- MSM_RPM_MAP(LDO21_0, LDO21, 2),
- MSM_RPM_MAP(LDO22_0, LDO22, 2),
- MSM_RPM_MAP(LDO23_0, LDO23, 2),
- MSM_RPM_MAP(LDO24_0, LDO24, 2),
- MSM_RPM_MAP(LDO25_0, LDO25, 2),
- MSM_RPM_MAP(LVS0, LVS0, 1),
- MSM_RPM_MAP(LVS1, LVS1, 1),
- MSM_RPM_MAP(NCP_0, NCP, 2),
+ MSM_RPM_MAP(8660, SMPS0_0, SMPS0, 2),
+ MSM_RPM_MAP(8660, SMPS1_0, SMPS1, 2),
+ MSM_RPM_MAP(8660, SMPS2_0, SMPS2, 2),
+ MSM_RPM_MAP(8660, SMPS3_0, SMPS3, 2),
+ MSM_RPM_MAP(8660, SMPS4_0, SMPS4, 2),
+ MSM_RPM_MAP(8660, LDO0_0, LDO0, 2),
+ MSM_RPM_MAP(8660, LDO1_0, LDO1, 2),
+ MSM_RPM_MAP(8660, LDO2_0, LDO2, 2),
+ MSM_RPM_MAP(8660, LDO3_0, LDO3, 2),
+ MSM_RPM_MAP(8660, LDO4_0, LDO4, 2),
+ MSM_RPM_MAP(8660, LDO5_0, LDO5, 2),
+ MSM_RPM_MAP(8660, LDO6_0, LDO6, 2),
+ MSM_RPM_MAP(8660, LDO7_0, LDO7, 2),
+ MSM_RPM_MAP(8660, LDO8_0, LDO8, 2),
+ MSM_RPM_MAP(8660, LDO9_0, LDO9, 2),
+ MSM_RPM_MAP(8660, LDO10_0, LDO10, 2),
+ MSM_RPM_MAP(8660, LDO11_0, LDO11, 2),
+ MSM_RPM_MAP(8660, LDO12_0, LDO12, 2),
+ MSM_RPM_MAP(8660, LDO13_0, LDO13, 2),
+ MSM_RPM_MAP(8660, LDO14_0, LDO14, 2),
+ MSM_RPM_MAP(8660, LDO15_0, LDO15, 2),
+ MSM_RPM_MAP(8660, LDO16_0, LDO16, 2),
+ MSM_RPM_MAP(8660, LDO17_0, LDO17, 2),
+ MSM_RPM_MAP(8660, LDO18_0, LDO18, 2),
+ MSM_RPM_MAP(8660, LDO19_0, LDO19, 2),
+ MSM_RPM_MAP(8660, LDO20_0, LDO20, 2),
+ MSM_RPM_MAP(8660, LDO21_0, LDO21, 2),
+ MSM_RPM_MAP(8660, LDO22_0, LDO22, 2),
+ MSM_RPM_MAP(8660, LDO23_0, LDO23, 2),
+ MSM_RPM_MAP(8660, LDO24_0, LDO24, 2),
+ MSM_RPM_MAP(8660, LDO25_0, LDO25, 2),
+ MSM_RPM_MAP(8660, LVS0, LVS0, 1),
+ MSM_RPM_MAP(8660, LVS1, LVS1, 1),
+ MSM_RPM_MAP(8660, NCP_0, NCP, 2),
+ MSM_RPM_MAP(8660, CXO_BUFFERS, CXO_BUFFERS, 1),
+ },
+ .target_status = {
+ MSM_RPM_STATUS_ID_MAP(8660, VERSION_MAJOR),
+ MSM_RPM_STATUS_ID_MAP(8660, VERSION_MINOR),
+ MSM_RPM_STATUS_ID_MAP(8660, VERSION_BUILD),
+ MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_2),
+ MSM_RPM_STATUS_ID_MAP(8660, SEQUENCE),
- MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
+ MSM_RPM_STATUS_ID_MAP(8660, CXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, PXO_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, PLL_4),
+ MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, DAYTONA_FABRIC_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, SFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, CFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, MMFPB_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, SMI_CLK),
+ MSM_RPM_STATUS_ID_MAP(8660, EBI1_CLK),
+
+ MSM_RPM_STATUS_ID_MAP(8660, APPS_L2_CACHE_CTL),
+
+ MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_HALT),
+ MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_CLOCK_MODE),
+ MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_ARB),
+
+ MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_HALT),
+ MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_CLOCK_MODE),
+ MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_ARB),
+
+ MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_HALT),
+ MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_CLOCK_MODE),
+ MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_ARB),
+
+
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS0B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS0B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS1B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS1B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS2B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS2B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS3B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS3B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS4B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS4B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO0B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO0B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO1B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO1B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO2B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO2B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO3B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO3B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO4B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO4B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO5B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO5B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO6B_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO6B_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS0B),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS1B),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS2B),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS3B),
+ MSM_RPM_STATUS_ID_MAP(8660, MVS),
+
+
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS0_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS0_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS1_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS1_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS2_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS2_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS3_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS3_1),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS4_0),
+ MSM_RPM_STATUS_ID_MAP(8660, SMPS4_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO0_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO0_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO1_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO1_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO2_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO2_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO3_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO3_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO4_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO4_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO5_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO5_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO6_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO6_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO7_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO7_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO8_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO8_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO9_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO9_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO10_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO10_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO11_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO11_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO12_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO12_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO13_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO13_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO14_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO14_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO15_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO15_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO16_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO16_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO17_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO17_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO18_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO18_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO19_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO19_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO20_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO20_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO21_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO21_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO22_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO22_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO23_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO23_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO24_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO24_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO25_0),
+ MSM_RPM_STATUS_ID_MAP(8660, LDO25_1),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS0),
+ MSM_RPM_STATUS_ID_MAP(8660, LVS1),
+ MSM_RPM_STATUS_ID_MAP(8660, NCP_0),
+ MSM_RPM_STATUS_ID_MAP(8660, NCP_1),
+ MSM_RPM_STATUS_ID_MAP(8660, CXO_BUFFERS),
+ },
+ .target_ctrl_id = {
+ MSM_RPM_CTRL_MAP(8660, VERSION_MAJOR),
+ MSM_RPM_CTRL_MAP(8660, VERSION_MINOR),
+ MSM_RPM_CTRL_MAP(8660, VERSION_BUILD),
+ MSM_RPM_CTRL_MAP(8660, REQ_CTX_0),
+ MSM_RPM_CTRL_MAP(8660, REQ_SEL_0),
+ MSM_RPM_CTRL_MAP(8660, ACK_CTX_0),
+ MSM_RPM_CTRL_MAP(8660, ACK_SEL_0),
+ },
+ .sel_invalidate = MSM_RPM_8660_SEL_INVALIDATE,
+ .sel_notification = MSM_RPM_8660_SEL_NOTIFICATION,
+ .sel_last = MSM_RPM_8660_SEL_LAST,
+ .ver = {2, 0, 0},
};
-unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
-struct platform_device msm_rpm_device = {
+struct platform_device msm8660_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
-
-#endif
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 5d28fa9..bbb815e 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -240,8 +240,26 @@
extern struct platform_device led_pdev;
-extern struct platform_device msm_rpm_device;
-extern struct platform_device msm_rpm_stat_device;
+extern struct platform_device msm8960_rpm_device;
+extern struct platform_device msm8960_rpm_stat_device;
+extern struct platform_device msm8960_rpm_log_device;
+
+extern struct platform_device msm8930_rpm_device;
+extern struct platform_device msm8930_rpm_stat_device;
+extern struct platform_device msm8930_rpm_log_device;
+
+extern struct platform_device msm8660_rpm_device;
+extern struct platform_device msm8660_rpm_stat_device;
+extern struct platform_device msm8660_rpm_log_device;
+
+extern struct platform_device msm9615_rpm_device;
+extern struct platform_device msm9615_rpm_stat_device;
+extern struct platform_device msm9615_rpm_log_device;
+
+extern struct platform_device apq8064_rpm_device;
+extern struct platform_device apq8064_rpm_stat_device;
+extern struct platform_device apq8064_rpm_log_device;
+
extern struct platform_device msm_device_rng;
extern struct platform_device apq8064_device_rng;
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 22d5bbc..0eee135 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -61,6 +61,11 @@
struct msm_camera_io_ext ioext;
struct msm_camera_io_clk ioclk;
uint8_t csid_core;
+ uint8_t is_csiphy;
+ uint8_t is_csic;
+ uint8_t is_csid;
+ uint8_t is_ispif;
+ uint8_t is_vpe;
struct msm_bus_scale_pdata *cam_bus_scale_table;
};
enum msm_camera_csi_data_format {
diff --git a/arch/arm/mach-msm/include/mach/rpm-8064.h b/arch/arm/mach-msm/include/mach/rpm-8064.h
new file mode 100644
index 0000000..c4c6b0a
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-8064.h
@@ -0,0 +1,432 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_RPM_8064_H
+#define __ARCH_ARM_MACH_MSM_RPM_8064_H
+
+/* RPM control message RAM enums */
+enum {
+ MSM_RPM_8064_CTRL_VERSION_MAJOR,
+ MSM_RPM_8064_CTRL_VERSION_MINOR,
+ MSM_RPM_8064_CTRL_VERSION_BUILD,
+
+ MSM_RPM_8064_CTRL_REQ_CTX_0,
+ MSM_RPM_8064_CTRL_REQ_CTX_7 = MSM_RPM_8064_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_8064_CTRL_REQ_SEL_0,
+ MSM_RPM_8064_CTRL_REQ_SEL_3 = MSM_RPM_8064_CTRL_REQ_SEL_0 + 3,
+ MSM_RPM_8064_CTRL_ACK_CTX_0,
+ MSM_RPM_8064_CTRL_ACK_CTX_7 = MSM_RPM_8064_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_8064_CTRL_ACK_SEL_0,
+ MSM_RPM_8064_CTRL_ACK_SEL_7 = MSM_RPM_8064_CTRL_ACK_SEL_0 + 7,
+};
+
+/* RPM resource select enums defined for RPM core
+ NOT IN SEQUENTIAL ORDER */
+enum {
+ MSM_RPM_8064_SEL_NOTIFICATION = 0,
+ MSM_RPM_8064_SEL_INVALIDATE = 1,
+ MSM_RPM_8064_SEL_TRIGGER_TIMED = 2,
+ MSM_RPM_8064_SEL_RPM_CTL = 3,
+
+ MSM_RPM_8064_SEL_CXO_CLK = 5,
+ MSM_RPM_8064_SEL_PXO_CLK = 6,
+ MSM_RPM_8064_SEL_QDSS_CLK = 7,
+ MSM_RPM_8064_SEL_APPS_FABRIC_CLK = 8,
+ MSM_RPM_8064_SEL_SYSTEM_FABRIC_CLK = 9,
+ MSM_RPM_8064_SEL_MM_FABRIC_CLK = 10,
+ MSM_RPM_8064_SEL_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_8064_SEL_SFPB_CLK = 12,
+ MSM_RPM_8064_SEL_CFPB_CLK = 13,
+ MSM_RPM_8064_SEL_MMFPB_CLK = 14,
+ MSM_RPM_8064_SEL_EBI1_CLK = 16,
+
+ MSM_RPM_8064_SEL_APPS_FABRIC_CFG_HALT = 18,
+ MSM_RPM_8064_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
+ MSM_RPM_8064_SEL_APPS_FABRIC_CFG_IOCTL = 20,
+ MSM_RPM_8064_SEL_APPS_FABRIC_ARB = 21,
+
+ MSM_RPM_8064_SEL_SYS_FABRIC_CFG_HALT = 22,
+ MSM_RPM_8064_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
+ MSM_RPM_8064_SEL_SYS_FABRIC_CFG_IOCTL = 24,
+ MSM_RPM_8064_SEL_SYSTEM_FABRIC_ARB = 25,
+
+ MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_HALT = 26,
+ MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
+ MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
+ MSM_RPM_8064_SEL_MM_FABRIC_ARB = 29,
+
+ MSM_RPM_8064_SEL_PM8921_S1 = 30,
+ MSM_RPM_8064_SEL_PM8921_S2 = 31,
+ MSM_RPM_8064_SEL_PM8921_S3 = 32,
+ MSM_RPM_8064_SEL_PM8921_S4 = 33,
+ MSM_RPM_8064_SEL_PM8921_S5 = 34,
+ MSM_RPM_8064_SEL_PM8921_S6 = 35,
+ MSM_RPM_8064_SEL_PM8921_S7 = 36,
+ MSM_RPM_8064_SEL_PM8921_S8 = 37,
+ MSM_RPM_8064_SEL_PM8921_L1 = 38,
+ MSM_RPM_8064_SEL_PM8921_L2 = 39,
+ MSM_RPM_8064_SEL_PM8921_L3 = 40,
+ MSM_RPM_8064_SEL_PM8921_L4 = 41,
+ MSM_RPM_8064_SEL_PM8921_L5 = 42,
+ MSM_RPM_8064_SEL_PM8921_L6 = 43,
+ MSM_RPM_8064_SEL_PM8921_L7 = 44,
+ MSM_RPM_8064_SEL_PM8921_L8 = 45,
+ MSM_RPM_8064_SEL_PM8921_L9 = 46,
+ MSM_RPM_8064_SEL_PM8921_L10 = 47,
+ MSM_RPM_8064_SEL_PM8921_L11 = 48,
+ MSM_RPM_8064_SEL_PM8921_L12 = 49,
+ MSM_RPM_8064_SEL_PM8921_L13 = 50,
+ MSM_RPM_8064_SEL_PM8921_L14 = 51,
+ MSM_RPM_8064_SEL_PM8921_L15 = 52,
+ MSM_RPM_8064_SEL_PM8921_L16 = 53,
+ MSM_RPM_8064_SEL_PM8921_L17 = 54,
+ MSM_RPM_8064_SEL_PM8921_L18 = 55,
+ MSM_RPM_8064_SEL_PM8921_L19 = 56,
+ MSM_RPM_8064_SEL_PM8921_L20 = 57,
+ MSM_RPM_8064_SEL_PM8921_L21 = 58,
+ MSM_RPM_8064_SEL_PM8921_L22 = 59,
+ MSM_RPM_8064_SEL_PM8921_L23 = 60,
+ MSM_RPM_8064_SEL_PM8921_L24 = 61,
+ MSM_RPM_8064_SEL_PM8921_L25 = 62,
+ MSM_RPM_8064_SEL_PM8921_L26 = 63,
+ MSM_RPM_8064_SEL_PM8921_L27 = 64,
+ MSM_RPM_8064_SEL_PM8921_L28 = 65,
+ MSM_RPM_8064_SEL_PM8921_L29 = 66,
+ MSM_RPM_8064_SEL_PM8921_CLK1 = 67,
+ MSM_RPM_8064_SEL_PM8921_CLK2 = 68,
+ MSM_RPM_8064_SEL_PM8921_LVS1 = 69,
+ MSM_RPM_8064_SEL_PM8921_LVS2 = 70,
+ MSM_RPM_8064_SEL_PM8921_LVS3 = 71,
+ MSM_RPM_8064_SEL_PM8921_LVS4 = 72,
+ MSM_RPM_8064_SEL_PM8921_LVS5 = 73,
+ MSM_RPM_8064_SEL_PM8921_LVS6 = 74,
+ MSM_RPM_8064_SEL_PM8921_LVS7 = 75,
+ MSM_RPM_8064_SEL_PM8821_S1 = 76,
+ MSM_RPM_8064_SEL_PM8821_S2 = 77,
+ MSM_RPM_8064_SEL_PM8821_L1 = 78,
+
+ MSM_RPM_8064_SEL_NCP = 80,
+ MSM_RPM_8064_SEL_CXO_BUFFERS = 81,
+ MSM_RPM_8064_SEL_USB_OTG_SWITCH = 82,
+ MSM_RPM_8064_SEL_HDMI_SWITCH = 83,
+ MSM_RPM_8064_SEL_DDR_DMM = 84,
+
+ MSM_RPM_8064_SEL_LAST = MSM_RPM_8064_SEL_DDR_DMM,
+};
+
+/* RPM resource (4 byte) word ID enum */
+enum {
+ MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_3 =
+ MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_0 + 3,
+
+ MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_0 = 4,
+ MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_3 =
+ MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_0 + 3,
+
+ MSM_RPM_8064_ID_INVALIDATE_0 = 8,
+ MSM_RPM_8064_ID_INVALIDATE_7 =
+ MSM_RPM_8064_ID_INVALIDATE_0 + 7,
+
+ MSM_RPM_8064_ID_TRIGGER_TIMED_TO = 16,
+ MSM_RPM_8064_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
+
+ MSM_RPM_8064_ID_RPM_CTL = 18,
+
+ /* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
+ MSM_RPM_8064_ID_RESERVED_0 = 19,
+ MSM_RPM_8064_ID_RESERVED_5 =
+ MSM_RPM_8064_ID_RESERVED_0 + 5,
+
+ MSM_RPM_8064_ID_CXO_CLK = 25,
+ MSM_RPM_8064_ID_PXO_CLK = 26,
+ MSM_RPM_8064_ID_APPS_FABRIC_CLK = 27,
+ MSM_RPM_8064_ID_SYSTEM_FABRIC_CLK = 28,
+ MSM_RPM_8064_ID_MM_FABRIC_CLK = 29,
+ MSM_RPM_8064_ID_DAYTONA_FABRIC_CLK = 30,
+ MSM_RPM_8064_ID_SFPB_CLK = 31,
+ MSM_RPM_8064_ID_CFPB_CLK = 32,
+ MSM_RPM_8064_ID_MMFPB_CLK = 33,
+ MSM_RPM_8064_ID_EBI1_CLK = 34,
+
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_HALT_0 = 35,
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_HALT_1 = 36,
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
+ MSM_RPM_8064_ID_APPS_FABRIC_CFG_IOCTL = 40,
+ MSM_RPM_8064_ID_APPS_FABRIC_ARB_0 = 41,
+ MSM_RPM_8064_ID_APPS_FABRIC_ARB_11 =
+ MSM_RPM_8064_ID_APPS_FABRIC_ARB_0 + 11,
+
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_HALT_0 = 53,
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_HALT_1 = 54,
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
+ MSM_RPM_8064_ID_SYS_FABRIC_CFG_IOCTL = 58,
+ MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_0 = 59,
+ MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_29 =
+ MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_0 + 29,
+
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_HALT_0 = 89,
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_HALT_1 = 90,
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 91,
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 92,
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 93,
+ MSM_RPM_8064_ID_MMSS_FABRIC_CFG_IOCTL = 94,
+ MSM_RPM_8064_ID_MM_FABRIC_ARB_0 = 95,
+ MSM_RPM_8064_ID_MM_FABRIC_ARB_20 =
+ MSM_RPM_8064_ID_MM_FABRIC_ARB_0 + 20,
+
+ MSM_RPM_8064_ID_PM8921_S1_0 = 116,
+ MSM_RPM_8064_ID_PM8921_S1_1 = 117,
+ MSM_RPM_8064_ID_PM8921_S2_0 = 118,
+ MSM_RPM_8064_ID_PM8921_S2_1 = 119,
+ MSM_RPM_8064_ID_PM8921_S3_0 = 120,
+ MSM_RPM_8064_ID_PM8921_S3_1 = 121,
+ MSM_RPM_8064_ID_PM8921_S4_0 = 122,
+ MSM_RPM_8064_ID_PM8921_S4_1 = 123,
+ MSM_RPM_8064_ID_PM8921_S5_0 = 124,
+ MSM_RPM_8064_ID_PM8921_S5_1 = 125,
+ MSM_RPM_8064_ID_PM8921_S6_0 = 126,
+ MSM_RPM_8064_ID_PM8921_S6_1 = 127,
+ MSM_RPM_8064_ID_PM8921_S7_0 = 128,
+ MSM_RPM_8064_ID_PM8921_S7_1 = 129,
+ MSM_RPM_8064_ID_PM8921_S8_0 = 130,
+ MSM_RPM_8064_ID_PM8921_S8_1 = 131,
+ MSM_RPM_8064_ID_PM8921_L1_0 = 132,
+ MSM_RPM_8064_ID_PM8921_L1_1 = 133,
+ MSM_RPM_8064_ID_PM8921_L2_0 = 134,
+ MSM_RPM_8064_ID_PM8921_L2_1 = 135,
+ MSM_RPM_8064_ID_PM8921_L3_0 = 136,
+ MSM_RPM_8064_ID_PM8921_L3_1 = 137,
+ MSM_RPM_8064_ID_PM8921_L4_0 = 138,
+ MSM_RPM_8064_ID_PM8921_L4_1 = 139,
+ MSM_RPM_8064_ID_PM8921_L5_0 = 140,
+ MSM_RPM_8064_ID_PM8921_L5_1 = 141,
+ MSM_RPM_8064_ID_PM8921_L6_0 = 142,
+ MSM_RPM_8064_ID_PM8921_L6_1 = 143,
+ MSM_RPM_8064_ID_PM8921_L7_0 = 144,
+ MSM_RPM_8064_ID_PM8921_L7_1 = 145,
+ MSM_RPM_8064_ID_PM8921_L8_0 = 146,
+ MSM_RPM_8064_ID_PM8921_L8_1 = 147,
+ MSM_RPM_8064_ID_PM8921_L9_0 = 148,
+ MSM_RPM_8064_ID_PM8921_L9_1 = 149,
+ MSM_RPM_8064_ID_PM8921_L10_0 = 150,
+ MSM_RPM_8064_ID_PM8921_L10_1 = 151,
+ MSM_RPM_8064_ID_PM8921_L11_0 = 152,
+ MSM_RPM_8064_ID_PM8921_L11_1 = 153,
+ MSM_RPM_8064_ID_PM8921_L12_0 = 154,
+ MSM_RPM_8064_ID_PM8921_L12_1 = 155,
+ MSM_RPM_8064_ID_PM8921_L13_0 = 156,
+ MSM_RPM_8064_ID_PM8921_L13_1 = 157,
+ MSM_RPM_8064_ID_PM8921_L14_0 = 158,
+ MSM_RPM_8064_ID_PM8921_L14_1 = 159,
+ MSM_RPM_8064_ID_PM8921_L15_0 = 160,
+ MSM_RPM_8064_ID_PM8921_L15_1 = 161,
+ MSM_RPM_8064_ID_PM8921_L16_0 = 162,
+ MSM_RPM_8064_ID_PM8921_L16_1 = 163,
+ MSM_RPM_8064_ID_PM8921_L17_0 = 164,
+ MSM_RPM_8064_ID_PM8921_L17_1 = 165,
+ MSM_RPM_8064_ID_PM8921_L18_0 = 166,
+ MSM_RPM_8064_ID_PM8921_L18_1 = 167,
+ MSM_RPM_8064_ID_PM8921_L19_0 = 168,
+ MSM_RPM_8064_ID_PM8921_L19_1 = 169,
+ MSM_RPM_8064_ID_PM8921_L20_0 = 170,
+ MSM_RPM_8064_ID_PM8921_L20_1 = 171,
+ MSM_RPM_8064_ID_PM8921_L21_0 = 172,
+ MSM_RPM_8064_ID_PM8921_L21_1 = 173,
+ MSM_RPM_8064_ID_PM8921_L22_0 = 174,
+ MSM_RPM_8064_ID_PM8921_L22_1 = 175,
+ MSM_RPM_8064_ID_PM8921_L23_0 = 176,
+ MSM_RPM_8064_ID_PM8921_L23_1 = 177,
+ MSM_RPM_8064_ID_PM8921_L24_0 = 178,
+ MSM_RPM_8064_ID_PM8921_L24_1 = 179,
+ MSM_RPM_8064_ID_PM8921_L25_0 = 180,
+ MSM_RPM_8064_ID_PM8921_L25_1 = 181,
+ MSM_RPM_8064_ID_PM8921_L26_0 = 182,
+ MSM_RPM_8064_ID_PM8921_L26_1 = 183,
+ MSM_RPM_8064_ID_PM8921_L27_0 = 184,
+ MSM_RPM_8064_ID_PM8921_L27_1 = 185,
+ MSM_RPM_8064_ID_PM8921_L28_0 = 186,
+ MSM_RPM_8064_ID_PM8921_L28_1 = 187,
+ MSM_RPM_8064_ID_PM8921_L29_0 = 188,
+ MSM_RPM_8064_ID_PM8921_L29_1 = 189,
+ MSM_RPM_8064_ID_PM8921_CLK1_0 = 190,
+ MSM_RPM_8064_ID_PM8921_CLK1_1 = 191,
+ MSM_RPM_8064_ID_PM8921_CLK2_0 = 192,
+ MSM_RPM_8064_ID_PM8921_CLK2_1 = 193,
+ MSM_RPM_8064_ID_PM8921_LVS1 = 194,
+ MSM_RPM_8064_ID_PM8921_LVS2 = 195,
+ MSM_RPM_8064_ID_PM8921_LVS3 = 196,
+ MSM_RPM_8064_ID_PM8921_LVS4 = 197,
+ MSM_RPM_8064_ID_PM8921_LVS5 = 198,
+ MSM_RPM_8064_ID_PM8921_LVS6 = 199,
+ MSM_RPM_8064_ID_PM8921_LVS7 = 200,
+ MSM_RPM_8064_ID_PM8821_S1_0 = 201,
+ MSM_RPM_8064_ID_PM8821_S1_1 = 202,
+ MSM_RPM_8064_ID_PM8821_S2_0 = 203,
+ MSM_RPM_8064_ID_PM8821_S2_1 = 204,
+ MSM_RPM_8064_ID_PM8821_L1_0 = 205,
+ MSM_RPM_8064_ID_PM8821_L1_1 = 206,
+ MSM_RPM_8064_ID_NCP_0 = 207,
+ MSM_RPM_8064_ID_NCP_1 = 208,
+ MSM_RPM_8064_ID_CXO_BUFFERS = 209,
+ MSM_RPM_8064_ID_USB_OTG_SWITCH = 210,
+ MSM_RPM_8064_ID_HDMI_SWITCH = 211,
+ MSM_RPM_8064_ID_DDR_DMM_0 = 212,
+ MSM_RPM_8064_ID_DDR_DMM_1 = 213,
+ MSM_RPM_8064_ID_QDSS_CLK = 214,
+
+ MSM_RPM_8064_ID_LAST = MSM_RPM_8064_ID_QDSS_CLK,
+};
+
+
+/* RPM status ID enum */
+enum {
+ MSM_RPM_8064_STATUS_ID_VERSION_MAJOR = 0,
+ MSM_RPM_8064_STATUS_ID_VERSION_MINOR = 1,
+ MSM_RPM_8064_STATUS_ID_VERSION_BUILD = 2,
+ MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
+ MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
+ MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
+ MSM_RPM_8064_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
+ MSM_RPM_8064_STATUS_ID_SEQUENCE = 7,
+ MSM_RPM_8064_STATUS_ID_RPM_CTL = 8,
+ MSM_RPM_8064_STATUS_ID_CXO_CLK = 9,
+ MSM_RPM_8064_STATUS_ID_PXO_CLK = 10,
+ MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CLK = 11,
+ MSM_RPM_8064_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
+ MSM_RPM_8064_STATUS_ID_MM_FABRIC_CLK = 13,
+ MSM_RPM_8064_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
+ MSM_RPM_8064_STATUS_ID_SFPB_CLK = 15,
+ MSM_RPM_8064_STATUS_ID_CFPB_CLK = 16,
+ MSM_RPM_8064_STATUS_ID_MMFPB_CLK = 17,
+ MSM_RPM_8064_STATUS_ID_EBI1_CLK = 18,
+ MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
+ MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
+ MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
+ MSM_RPM_8064_STATUS_ID_APPS_FABRIC_ARB = 22,
+ MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
+ MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
+ MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
+ MSM_RPM_8064_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
+ MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
+ MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
+ MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
+ MSM_RPM_8064_STATUS_ID_MM_FABRIC_ARB = 30,
+ MSM_RPM_8064_STATUS_ID_PM8921_S1_0 = 31,
+ MSM_RPM_8064_STATUS_ID_PM8921_S1_1 = 32,
+ MSM_RPM_8064_STATUS_ID_PM8921_S2_0 = 33,
+ MSM_RPM_8064_STATUS_ID_PM8921_S2_1 = 34,
+ MSM_RPM_8064_STATUS_ID_PM8921_S3_0 = 35,
+ MSM_RPM_8064_STATUS_ID_PM8921_S3_1 = 36,
+ MSM_RPM_8064_STATUS_ID_PM8921_S4_0 = 37,
+ MSM_RPM_8064_STATUS_ID_PM8921_S4_1 = 38,
+ MSM_RPM_8064_STATUS_ID_PM8921_S5_0 = 39,
+ MSM_RPM_8064_STATUS_ID_PM8921_S5_1 = 40,
+ MSM_RPM_8064_STATUS_ID_PM8921_S6_0 = 41,
+ MSM_RPM_8064_STATUS_ID_PM8921_S6_1 = 42,
+ MSM_RPM_8064_STATUS_ID_PM8921_S7_0 = 43,
+ MSM_RPM_8064_STATUS_ID_PM8921_S7_1 = 44,
+ MSM_RPM_8064_STATUS_ID_PM8921_S8_0 = 45,
+ MSM_RPM_8064_STATUS_ID_PM8921_S8_1 = 46,
+ MSM_RPM_8064_STATUS_ID_PM8921_L1_0 = 47,
+ MSM_RPM_8064_STATUS_ID_PM8921_L1_1 = 48,
+ MSM_RPM_8064_STATUS_ID_PM8921_L2_0 = 49,
+ MSM_RPM_8064_STATUS_ID_PM8921_L2_1 = 50,
+ MSM_RPM_8064_STATUS_ID_PM8921_L3_0 = 51,
+ MSM_RPM_8064_STATUS_ID_PM8921_L3_1 = 52,
+ MSM_RPM_8064_STATUS_ID_PM8921_L4_0 = 53,
+ MSM_RPM_8064_STATUS_ID_PM8921_L4_1 = 54,
+ MSM_RPM_8064_STATUS_ID_PM8921_L5_0 = 55,
+ MSM_RPM_8064_STATUS_ID_PM8921_L5_1 = 56,
+ MSM_RPM_8064_STATUS_ID_PM8921_L6_0 = 57,
+ MSM_RPM_8064_STATUS_ID_PM8921_L6_1 = 58,
+ MSM_RPM_8064_STATUS_ID_PM8921_L7_0 = 59,
+ MSM_RPM_8064_STATUS_ID_PM8921_L7_1 = 60,
+ MSM_RPM_8064_STATUS_ID_PM8921_L8_0 = 61,
+ MSM_RPM_8064_STATUS_ID_PM8921_L8_1 = 62,
+ MSM_RPM_8064_STATUS_ID_PM8921_L9_0 = 63,
+ MSM_RPM_8064_STATUS_ID_PM8921_L9_1 = 64,
+ MSM_RPM_8064_STATUS_ID_PM8921_L10_0 = 65,
+ MSM_RPM_8064_STATUS_ID_PM8921_L10_1 = 66,
+ MSM_RPM_8064_STATUS_ID_PM8921_L11_0 = 67,
+ MSM_RPM_8064_STATUS_ID_PM8921_L11_1 = 68,
+ MSM_RPM_8064_STATUS_ID_PM8921_L12_0 = 69,
+ MSM_RPM_8064_STATUS_ID_PM8921_L12_1 = 70,
+ MSM_RPM_8064_STATUS_ID_PM8921_L13_0 = 71,
+ MSM_RPM_8064_STATUS_ID_PM8921_L13_1 = 72,
+ MSM_RPM_8064_STATUS_ID_PM8921_L14_0 = 73,
+ MSM_RPM_8064_STATUS_ID_PM8921_L14_1 = 74,
+ MSM_RPM_8064_STATUS_ID_PM8921_L15_0 = 75,
+ MSM_RPM_8064_STATUS_ID_PM8921_L15_1 = 76,
+ MSM_RPM_8064_STATUS_ID_PM8921_L16_0 = 77,
+ MSM_RPM_8064_STATUS_ID_PM8921_L16_1 = 78,
+ MSM_RPM_8064_STATUS_ID_PM8921_L17_0 = 79,
+ MSM_RPM_8064_STATUS_ID_PM8921_L17_1 = 80,
+ MSM_RPM_8064_STATUS_ID_PM8921_L18_0 = 81,
+ MSM_RPM_8064_STATUS_ID_PM8921_L18_1 = 82,
+ MSM_RPM_8064_STATUS_ID_PM8921_L19_0 = 83,
+ MSM_RPM_8064_STATUS_ID_PM8921_L19_1 = 84,
+ MSM_RPM_8064_STATUS_ID_PM8921_L20_0 = 85,
+ MSM_RPM_8064_STATUS_ID_PM8921_L20_1 = 86,
+ MSM_RPM_8064_STATUS_ID_PM8921_L21_0 = 87,
+ MSM_RPM_8064_STATUS_ID_PM8921_L21_1 = 88,
+ MSM_RPM_8064_STATUS_ID_PM8921_L22_0 = 89,
+ MSM_RPM_8064_STATUS_ID_PM8921_L22_1 = 90,
+ MSM_RPM_8064_STATUS_ID_PM8921_L23_0 = 91,
+ MSM_RPM_8064_STATUS_ID_PM8921_L23_1 = 92,
+ MSM_RPM_8064_STATUS_ID_PM8921_L24_0 = 93,
+ MSM_RPM_8064_STATUS_ID_PM8921_L24_1 = 94,
+ MSM_RPM_8064_STATUS_ID_PM8921_L25_0 = 95,
+ MSM_RPM_8064_STATUS_ID_PM8921_L25_1 = 96,
+ MSM_RPM_8064_STATUS_ID_PM8921_L26_0 = 97,
+ MSM_RPM_8064_STATUS_ID_PM8921_L26_1 = 98,
+ MSM_RPM_8064_STATUS_ID_PM8921_L27_0 = 99,
+ MSM_RPM_8064_STATUS_ID_PM8921_L27_1 = 100,
+ MSM_RPM_8064_STATUS_ID_PM8921_L28_0 = 101,
+ MSM_RPM_8064_STATUS_ID_PM8921_L28_1 = 102,
+ MSM_RPM_8064_STATUS_ID_PM8921_L29_0 = 103,
+ MSM_RPM_8064_STATUS_ID_PM8921_L29_1 = 104,
+ MSM_RPM_8064_STATUS_ID_PM8921_CLK1_0 = 105,
+ MSM_RPM_8064_STATUS_ID_PM8921_CLK1_1 = 106,
+ MSM_RPM_8064_STATUS_ID_PM8921_CLK2_0 = 107,
+ MSM_RPM_8064_STATUS_ID_PM8921_CLK2_1 = 108,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS1 = 109,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS2 = 110,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS3 = 111,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS4 = 112,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS5 = 113,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS6 = 114,
+ MSM_RPM_8064_STATUS_ID_PM8921_LVS7 = 115,
+ MSM_RPM_8064_STATUS_ID_PM8821_S1_0 = 116,
+ MSM_RPM_8064_STATUS_ID_PM8821_S1_1 = 117,
+ MSM_RPM_8064_STATUS_ID_PM8821_S2_0 = 118,
+ MSM_RPM_8064_STATUS_ID_PM8821_S2_1 = 119,
+ MSM_RPM_8064_STATUS_ID_PM8821_L1_0 = 120,
+ MSM_RPM_8064_STATUS_ID_PM8821_L1_1 = 121,
+ MSM_RPM_8064_STATUS_ID_NCP_0 = 122,
+ MSM_RPM_8064_STATUS_ID_NCP_1 = 123,
+ MSM_RPM_8064_STATUS_ID_CXO_BUFFERS = 124,
+ MSM_RPM_8064_STATUS_ID_USB_OTG_SWITCH = 125,
+ MSM_RPM_8064_STATUS_ID_HDMI_SWITCH = 126,
+ MSM_RPM_8064_STATUS_ID_DDR_DMM_0 = 127,
+ MSM_RPM_8064_STATUS_ID_DDR_DMM_1 = 128,
+ MSM_RPM_8064_STATUS_ID_EBI1_CH0_RANGE = 129,
+ MSM_RPM_8064_STATUS_ID_EBI1_CH1_RANGE = 130,
+
+ MSM_RPM_8064_STATUS_ID_LAST = MSM_RPM_8064_STATUS_ID_EBI1_CH1_RANGE,
+};
+
+#endif /* __ARCH_ARM_MACH_MSM_RPM_8064_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-8660.h b/arch/arm/mach-msm/include/mach/rpm-8660.h
index 23ffc5d..5e3b404 100644
--- a/arch/arm/mach-msm/include/mach/rpm-8660.h
+++ b/arch/arm/mach-msm/include/mach/rpm-8660.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,469 +13,443 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_8660_H
#define __ARCH_ARM_MACH_MSM_RPM_8660_H
-#define RPM_MAJOR_VER 2
-#define RPM_MINOR_VER 0
-#define RPM_BUILD_VER 0
-
-
/* RPM control message RAM enums */
enum {
- MSM_RPM_CTRL_VERSION_MAJOR,
- MSM_RPM_CTRL_VERSION_MINOR,
- MSM_RPM_CTRL_VERSION_BUILD,
+ MSM_RPM_8660_CTRL_VERSION_MAJOR,
+ MSM_RPM_8660_CTRL_VERSION_MINOR,
+ MSM_RPM_8660_CTRL_VERSION_BUILD,
- MSM_RPM_CTRL_REQ_CTX_0,
- MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
- MSM_RPM_CTRL_REQ_SEL_0,
- MSM_RPM_CTRL_REQ_SEL_7 = MSM_RPM_CTRL_REQ_SEL_0 + 7,
- MSM_RPM_CTRL_ACK_CTX_0,
- MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
- MSM_RPM_CTRL_ACK_SEL_0,
- MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
+ MSM_RPM_8660_CTRL_REQ_CTX_0,
+ MSM_RPM_8660_CTRL_REQ_CTX_7 = MSM_RPM_8660_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_8660_CTRL_REQ_SEL_0,
+ MSM_RPM_8660_CTRL_REQ_SEL_7 = MSM_RPM_8660_CTRL_REQ_SEL_0 + 7,
+ MSM_RPM_8660_CTRL_ACK_CTX_0,
+ MSM_RPM_8660_CTRL_ACK_CTX_7 = MSM_RPM_8660_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_8660_CTRL_ACK_SEL_0,
+ MSM_RPM_8660_CTRL_ACK_SEL_7 = MSM_RPM_8660_CTRL_ACK_SEL_0 + 7,
};
enum {
- MSM_RPM_SEL_NOTIFICATION,
- MSM_RPM_SEL_INVALIDATE,
- MSM_RPM_SEL_TRIGGER_TIMED,
- MSM_RPM_SEL_TRIGGER_SET,
- MSM_RPM_SEL_TRIGGER_CLEAR,
+ MSM_RPM_8660_SEL_NOTIFICATION,
+ MSM_RPM_8660_SEL_INVALIDATE,
+ MSM_RPM_8660_SEL_TRIGGER_TIMED,
+ MSM_RPM_8660_SEL_TRIGGER_SET,
+ MSM_RPM_8660_SEL_TRIGGER_CLEAR,
- MSM_RPM_SEL_CXO_CLK,
- MSM_RPM_SEL_PXO_CLK,
- MSM_RPM_SEL_PLL_4,
- MSM_RPM_SEL_APPS_FABRIC_CLK,
- MSM_RPM_SEL_SYSTEM_FABRIC_CLK,
- MSM_RPM_SEL_MM_FABRIC_CLK,
- MSM_RPM_SEL_DAYTONA_FABRIC_CLK,
- MSM_RPM_SEL_SFPB_CLK,
- MSM_RPM_SEL_CFPB_CLK,
- MSM_RPM_SEL_MMFPB_CLK,
- MSM_RPM_SEL_SMI_CLK,
- MSM_RPM_SEL_EBI1_CLK,
+ MSM_RPM_8660_SEL_CXO_CLK,
+ MSM_RPM_8660_SEL_PXO_CLK,
+ MSM_RPM_8660_SEL_PLL_4,
+ MSM_RPM_8660_SEL_APPS_FABRIC_CLK,
+ MSM_RPM_8660_SEL_SYSTEM_FABRIC_CLK,
+ MSM_RPM_8660_SEL_MM_FABRIC_CLK,
+ MSM_RPM_8660_SEL_DAYTONA_FABRIC_CLK,
+ MSM_RPM_8660_SEL_SFPB_CLK,
+ MSM_RPM_8660_SEL_CFPB_CLK,
+ MSM_RPM_8660_SEL_MMFPB_CLK,
+ MSM_RPM_8660_SEL_SMI_CLK,
+ MSM_RPM_8660_SEL_EBI1_CLK,
- MSM_RPM_SEL_APPS_L2_CACHE_CTL,
+ MSM_RPM_8660_SEL_APPS_L2_CACHE_CTL,
- MSM_RPM_SEL_APPS_FABRIC_HALT,
- MSM_RPM_SEL_APPS_FABRIC_CLOCK_MODE,
- MSM_RPM_SEL_APPS_FABRIC_IOCTL,
- MSM_RPM_SEL_APPS_FABRIC_ARB,
+ MSM_RPM_8660_SEL_APPS_FABRIC_HALT,
+ MSM_RPM_8660_SEL_APPS_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_SEL_APPS_FABRIC_IOCTL,
+ MSM_RPM_8660_SEL_APPS_FABRIC_ARB,
- MSM_RPM_SEL_SYSTEM_FABRIC_HALT,
- MSM_RPM_SEL_SYSTEM_FABRIC_CLOCK_MODE,
- MSM_RPM_SEL_SYSTEM_FABRIC_IOCTL,
- MSM_RPM_SEL_SYSTEM_FABRIC_ARB,
+ MSM_RPM_8660_SEL_SYSTEM_FABRIC_HALT,
+ MSM_RPM_8660_SEL_SYSTEM_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_SEL_SYSTEM_FABRIC_IOCTL,
+ MSM_RPM_8660_SEL_SYSTEM_FABRIC_ARB,
- MSM_RPM_SEL_MM_FABRIC_HALT,
- MSM_RPM_SEL_MM_FABRIC_CLOCK_MODE,
- MSM_RPM_SEL_MM_FABRIC_IOCTL,
- MSM_RPM_SEL_MM_FABRIC_ARB,
+ MSM_RPM_8660_SEL_MM_FABRIC_HALT,
+ MSM_RPM_8660_SEL_MM_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_SEL_MM_FABRIC_IOCTL,
+ MSM_RPM_8660_SEL_MM_FABRIC_ARB,
- MSM_RPM_SEL_SMPS0B,
- MSM_RPM_SEL_SMPS1B,
- MSM_RPM_SEL_SMPS2B,
- MSM_RPM_SEL_SMPS3B,
- MSM_RPM_SEL_SMPS4B,
- MSM_RPM_SEL_LDO0B,
- MSM_RPM_SEL_LDO1B,
- MSM_RPM_SEL_LDO2B,
- MSM_RPM_SEL_LDO3B,
- MSM_RPM_SEL_LDO4B,
- MSM_RPM_SEL_LDO5B,
- MSM_RPM_SEL_LDO6B,
- MSM_RPM_SEL_LVS0B,
- MSM_RPM_SEL_LVS1B,
- MSM_RPM_SEL_LVS2B,
- MSM_RPM_SEL_LVS3B,
- MSM_RPM_SEL_MVS,
+ MSM_RPM_8660_SEL_SMPS0B,
+ MSM_RPM_8660_SEL_SMPS1B,
+ MSM_RPM_8660_SEL_SMPS2B,
+ MSM_RPM_8660_SEL_SMPS3B,
+ MSM_RPM_8660_SEL_SMPS4B,
+ MSM_RPM_8660_SEL_LDO0B,
+ MSM_RPM_8660_SEL_LDO1B,
+ MSM_RPM_8660_SEL_LDO2B,
+ MSM_RPM_8660_SEL_LDO3B,
+ MSM_RPM_8660_SEL_LDO4B,
+ MSM_RPM_8660_SEL_LDO5B,
+ MSM_RPM_8660_SEL_LDO6B,
+ MSM_RPM_8660_SEL_LVS0B,
+ MSM_RPM_8660_SEL_LVS1B,
+ MSM_RPM_8660_SEL_LVS2B,
+ MSM_RPM_8660_SEL_LVS3B,
+ MSM_RPM_8660_SEL_MVS,
- MSM_RPM_SEL_SMPS0,
- MSM_RPM_SEL_SMPS1,
- MSM_RPM_SEL_SMPS2,
- MSM_RPM_SEL_SMPS3,
- MSM_RPM_SEL_SMPS4,
+ MSM_RPM_8660_SEL_SMPS0,
+ MSM_RPM_8660_SEL_SMPS1,
+ MSM_RPM_8660_SEL_SMPS2,
+ MSM_RPM_8660_SEL_SMPS3,
+ MSM_RPM_8660_SEL_SMPS4,
- MSM_RPM_SEL_LDO0,
- MSM_RPM_SEL_LDO1,
- MSM_RPM_SEL_LDO2,
- MSM_RPM_SEL_LDO3,
- MSM_RPM_SEL_LDO4,
- MSM_RPM_SEL_LDO5,
- MSM_RPM_SEL_LDO6,
- MSM_RPM_SEL_LDO7,
- MSM_RPM_SEL_LDO8,
- MSM_RPM_SEL_LDO9,
- MSM_RPM_SEL_LDO10,
- MSM_RPM_SEL_LDO11,
- MSM_RPM_SEL_LDO12,
- MSM_RPM_SEL_LDO13,
- MSM_RPM_SEL_LDO14,
- MSM_RPM_SEL_LDO15,
- MSM_RPM_SEL_LDO16,
- MSM_RPM_SEL_LDO17,
- MSM_RPM_SEL_LDO18,
- MSM_RPM_SEL_LDO19,
- MSM_RPM_SEL_LDO20,
- MSM_RPM_SEL_LDO21,
- MSM_RPM_SEL_LDO22,
- MSM_RPM_SEL_LDO23,
- MSM_RPM_SEL_LDO24,
- MSM_RPM_SEL_LDO25,
- MSM_RPM_SEL_LVS0,
- MSM_RPM_SEL_LVS1,
- MSM_RPM_SEL_NCP,
+ MSM_RPM_8660_SEL_LDO0,
+ MSM_RPM_8660_SEL_LDO1,
+ MSM_RPM_8660_SEL_LDO2,
+ MSM_RPM_8660_SEL_LDO3,
+ MSM_RPM_8660_SEL_LDO4,
+ MSM_RPM_8660_SEL_LDO5,
+ MSM_RPM_8660_SEL_LDO6,
+ MSM_RPM_8660_SEL_LDO7,
+ MSM_RPM_8660_SEL_LDO8,
+ MSM_RPM_8660_SEL_LDO9,
+ MSM_RPM_8660_SEL_LDO10,
+ MSM_RPM_8660_SEL_LDO11,
+ MSM_RPM_8660_SEL_LDO12,
+ MSM_RPM_8660_SEL_LDO13,
+ MSM_RPM_8660_SEL_LDO14,
+ MSM_RPM_8660_SEL_LDO15,
+ MSM_RPM_8660_SEL_LDO16,
+ MSM_RPM_8660_SEL_LDO17,
+ MSM_RPM_8660_SEL_LDO18,
+ MSM_RPM_8660_SEL_LDO19,
+ MSM_RPM_8660_SEL_LDO20,
+ MSM_RPM_8660_SEL_LDO21,
+ MSM_RPM_8660_SEL_LDO22,
+ MSM_RPM_8660_SEL_LDO23,
+ MSM_RPM_8660_SEL_LDO24,
+ MSM_RPM_8660_SEL_LDO25,
+ MSM_RPM_8660_SEL_LVS0,
+ MSM_RPM_8660_SEL_LVS1,
+ MSM_RPM_8660_SEL_NCP,
- MSM_RPM_SEL_CXO_BUFFERS,
+ MSM_RPM_8660_SEL_CXO_BUFFERS,
- MSM_RPM_SEL_LAST = MSM_RPM_SEL_CXO_BUFFERS,
+ MSM_RPM_8660_SEL_LAST = MSM_RPM_8660_SEL_CXO_BUFFERS,
};
enum {
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0,
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_7 =
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 7,
+ MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_0,
+ MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_7 =
+ MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_0 + 7,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_7 =
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 7,
+ MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_0,
+ MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_7 =
+ MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_0 + 7,
- MSM_RPM_ID_INVALIDATE_0,
- MSM_RPM_ID_INVALIDATE_7 = MSM_RPM_ID_INVALIDATE_0 + 7,
+ MSM_RPM_8660_ID_INVALIDATE_0,
+ MSM_RPM_8660_ID_INVALIDATE_7 =
+ MSM_RPM_8660_ID_INVALIDATE_0 + 7,
- MSM_RPM_ID_TRIGGER_TIMED_TO,
- MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT,
+ MSM_RPM_8660_ID_TRIGGER_TIMED_TO,
+ MSM_RPM_8660_ID_TRIGGER_TIMED_SCLK_COUNT,
- MSM_RPM_ID_TRIGGER_SET_FROM,
- MSM_RPM_ID_TRIGGER_SET_TO,
- MSM_RPM_ID_TRIGGER_SET_TRIGGER,
+ MSM_RPM_8660_ID_TRIGGER_SET_FROM,
+ MSM_RPM_8660_ID_TRIGGER_SET_TO,
+ MSM_RPM_8660_ID_TRIGGER_SET_TRIGGER,
- MSM_RPM_ID_TRIGGER_CLEAR_FROM,
- MSM_RPM_ID_TRIGGER_CLEAR_TO,
- MSM_RPM_ID_TRIGGER_CLEAR_TRIGGER,
+ MSM_RPM_8660_ID_TRIGGER_CLEAR_FROM,
+ MSM_RPM_8660_ID_TRIGGER_CLEAR_TO,
+ MSM_RPM_8660_ID_TRIGGER_CLEAR_TRIGGER,
- MSM_RPM_ID_CXO_CLK,
- MSM_RPM_ID_PXO_CLK,
- MSM_RPM_ID_PLL_4,
- MSM_RPM_ID_APPS_FABRIC_CLK,
- MSM_RPM_ID_SYSTEM_FABRIC_CLK,
- MSM_RPM_ID_MM_FABRIC_CLK,
- MSM_RPM_ID_DAYTONA_FABRIC_CLK,
- MSM_RPM_ID_SFPB_CLK,
- MSM_RPM_ID_CFPB_CLK,
- MSM_RPM_ID_MMFPB_CLK,
- MSM_RPM_ID_SMI_CLK,
- MSM_RPM_ID_EBI1_CLK,
+ MSM_RPM_8660_ID_CXO_CLK,
+ MSM_RPM_8660_ID_PXO_CLK,
+ MSM_RPM_8660_ID_PLL_4,
+ MSM_RPM_8660_ID_APPS_FABRIC_CLK,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_CLK,
+ MSM_RPM_8660_ID_MM_FABRIC_CLK,
+ MSM_RPM_8660_ID_DAYTONA_FABRIC_CLK,
+ MSM_RPM_8660_ID_SFPB_CLK,
+ MSM_RPM_8660_ID_CFPB_CLK,
+ MSM_RPM_8660_ID_MMFPB_CLK,
+ MSM_RPM_8660_ID_SMI_CLK,
+ MSM_RPM_8660_ID_EBI1_CLK,
- MSM_RPM_ID_APPS_L2_CACHE_CTL,
+ MSM_RPM_8660_ID_APPS_L2_CACHE_CTL,
- MSM_RPM_ID_APPS_FABRIC_HALT_0,
- MSM_RPM_ID_APPS_FABRIC_HALT_1,
- MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_0,
- MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_1,
- MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_2,
- MSM_RPM_ID_APPS_FABRIC_RESERVED_A,
- MSM_RPM_ID_APPS_FABRIC_ARB_0,
- MSM_RPM_ID_APPS_FABRIC_ARB_5 = MSM_RPM_ID_APPS_FABRIC_ARB_0 + 5,
- MSM_RPM_ID_APPS_FABRIC_RESERVED_B_0,
- MSM_RPM_ID_APPS_FABRIC_RESERVED_B_5 =
- MSM_RPM_ID_APPS_FABRIC_RESERVED_B_0 + 5,
+ MSM_RPM_8660_ID_APPS_FABRIC_HALT_0,
+ MSM_RPM_8660_ID_APPS_FABRIC_HALT_1,
+ MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_0,
+ MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_1,
+ MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_2,
+ MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_A,
+ MSM_RPM_8660_ID_APPS_FABRIC_ARB_0,
+ MSM_RPM_8660_ID_APPS_FABRIC_ARB_5 =
+ MSM_RPM_8660_ID_APPS_FABRIC_ARB_0 + 5,
+ MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_0,
+ MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_5 =
+ MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_0 + 5,
- MSM_RPM_ID_SYSTEM_FABRIC_HALT_0,
- MSM_RPM_ID_SYSTEM_FABRIC_HALT_1,
- MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_0,
- MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_1,
- MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_2,
- MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_A,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_21 = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 21,
- MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_0,
- MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_13 =
- MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_0 + 13,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_HALT_0,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_HALT_1,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_0,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_1,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_2,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_A,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_0,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_21 =
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_0 + 21,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_0,
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_13 =
+ MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_0 + 13,
- MSM_RPM_ID_MM_FABRIC_HALT_0,
- MSM_RPM_ID_MM_FABRIC_HALT_1,
- MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_0,
- MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_1,
- MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_2,
- MSM_RPM_ID_MM_FABRIC_RESERVED_A,
- MSM_RPM_ID_MM_FABRIC_ARB_0,
- MSM_RPM_ID_MM_FABRIC_ARB_22 = MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
+ MSM_RPM_8660_ID_MM_FABRIC_HALT_0,
+ MSM_RPM_8660_ID_MM_FABRIC_HALT_1,
+ MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_0,
+ MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_1,
+ MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_2,
+ MSM_RPM_8660_ID_MM_FABRIC_RESERVED_A,
+ MSM_RPM_8660_ID_MM_FABRIC_ARB_0,
+ MSM_RPM_8660_ID_MM_FABRIC_ARB_22 =
+ MSM_RPM_8660_ID_MM_FABRIC_ARB_0 + 22,
/* pmic 8901 */
- MSM_RPM_ID_SMPS0B_0,
- MSM_RPM_ID_SMPS0B_1,
- MSM_RPM_ID_SMPS1B_0,
- MSM_RPM_ID_SMPS1B_1,
- MSM_RPM_ID_SMPS2B_0,
- MSM_RPM_ID_SMPS2B_1,
- MSM_RPM_ID_SMPS3B_0,
- MSM_RPM_ID_SMPS3B_1,
- MSM_RPM_ID_SMPS4B_0,
- MSM_RPM_ID_SMPS4B_1,
- MSM_RPM_ID_LDO0B_0,
- MSM_RPM_ID_LDO0B_1,
- MSM_RPM_ID_LDO1B_0,
- MSM_RPM_ID_LDO1B_1,
- MSM_RPM_ID_LDO2B_0,
- MSM_RPM_ID_LDO2B_1,
- MSM_RPM_ID_LDO3B_0,
- MSM_RPM_ID_LDO3B_1,
- MSM_RPM_ID_LDO4B_0,
- MSM_RPM_ID_LDO4B_1,
- MSM_RPM_ID_LDO5B_0,
- MSM_RPM_ID_LDO5B_1,
- MSM_RPM_ID_LDO6B_0,
- MSM_RPM_ID_LDO6B_1,
- MSM_RPM_ID_LVS0B,
- MSM_RPM_ID_LVS1B,
- MSM_RPM_ID_LVS2B,
- MSM_RPM_ID_LVS3B,
- MSM_RPM_ID_MVS,
+ MSM_RPM_8660_ID_SMPS0B_0,
+ MSM_RPM_8660_ID_SMPS0B_1,
+ MSM_RPM_8660_ID_SMPS1B_0,
+ MSM_RPM_8660_ID_SMPS1B_1,
+ MSM_RPM_8660_ID_SMPS2B_0,
+ MSM_RPM_8660_ID_SMPS2B_1,
+ MSM_RPM_8660_ID_SMPS3B_0,
+ MSM_RPM_8660_ID_SMPS3B_1,
+ MSM_RPM_8660_ID_SMPS4B_0,
+ MSM_RPM_8660_ID_SMPS4B_1,
+ MSM_RPM_8660_ID_LDO0B_0,
+ MSM_RPM_8660_ID_LDO0B_1,
+ MSM_RPM_8660_ID_LDO1B_0,
+ MSM_RPM_8660_ID_LDO1B_1,
+ MSM_RPM_8660_ID_LDO2B_0,
+ MSM_RPM_8660_ID_LDO2B_1,
+ MSM_RPM_8660_ID_LDO3B_0,
+ MSM_RPM_8660_ID_LDO3B_1,
+ MSM_RPM_8660_ID_LDO4B_0,
+ MSM_RPM_8660_ID_LDO4B_1,
+ MSM_RPM_8660_ID_LDO5B_0,
+ MSM_RPM_8660_ID_LDO5B_1,
+ MSM_RPM_8660_ID_LDO6B_0,
+ MSM_RPM_8660_ID_LDO6B_1,
+ MSM_RPM_8660_ID_LVS0B,
+ MSM_RPM_8660_ID_LVS1B,
+ MSM_RPM_8660_ID_LVS2B,
+ MSM_RPM_8660_ID_LVS3B,
+ MSM_RPM_8660_ID_MVS,
/* pmic 8058 */
- MSM_RPM_ID_SMPS0_0,
- MSM_RPM_ID_SMPS0_1,
- MSM_RPM_ID_SMPS1_0,
- MSM_RPM_ID_SMPS1_1,
- MSM_RPM_ID_SMPS2_0,
- MSM_RPM_ID_SMPS2_1,
- MSM_RPM_ID_SMPS3_0,
- MSM_RPM_ID_SMPS3_1,
- MSM_RPM_ID_SMPS4_0,
- MSM_RPM_ID_SMPS4_1,
- MSM_RPM_ID_LDO0_0,
- MSM_RPM_ID_LDO0_1,
- MSM_RPM_ID_LDO1_0,
- MSM_RPM_ID_LDO1_1,
- MSM_RPM_ID_LDO2_0,
- MSM_RPM_ID_LDO2_1,
- MSM_RPM_ID_LDO3_0,
- MSM_RPM_ID_LDO3_1,
- MSM_RPM_ID_LDO4_0,
- MSM_RPM_ID_LDO4_1,
- MSM_RPM_ID_LDO5_0,
- MSM_RPM_ID_LDO5_1,
- MSM_RPM_ID_LDO6_0,
- MSM_RPM_ID_LDO6_1,
- MSM_RPM_ID_LDO7_0,
- MSM_RPM_ID_LDO7_1,
- MSM_RPM_ID_LDO8_0,
- MSM_RPM_ID_LDO8_1,
- MSM_RPM_ID_LDO9_0,
- MSM_RPM_ID_LDO9_1,
- MSM_RPM_ID_LDO10_0,
- MSM_RPM_ID_LDO10_1,
- MSM_RPM_ID_LDO11_0,
- MSM_RPM_ID_LDO11_1,
- MSM_RPM_ID_LDO12_0,
- MSM_RPM_ID_LDO12_1,
- MSM_RPM_ID_LDO13_0,
- MSM_RPM_ID_LDO13_1,
- MSM_RPM_ID_LDO14_0,
- MSM_RPM_ID_LDO14_1,
- MSM_RPM_ID_LDO15_0,
- MSM_RPM_ID_LDO15_1,
- MSM_RPM_ID_LDO16_0,
- MSM_RPM_ID_LDO16_1,
- MSM_RPM_ID_LDO17_0,
- MSM_RPM_ID_LDO17_1,
- MSM_RPM_ID_LDO18_0,
- MSM_RPM_ID_LDO18_1,
- MSM_RPM_ID_LDO19_0,
- MSM_RPM_ID_LDO19_1,
- MSM_RPM_ID_LDO20_0,
- MSM_RPM_ID_LDO20_1,
- MSM_RPM_ID_LDO21_0,
- MSM_RPM_ID_LDO21_1,
- MSM_RPM_ID_LDO22_0,
- MSM_RPM_ID_LDO22_1,
- MSM_RPM_ID_LDO23_0,
- MSM_RPM_ID_LDO23_1,
- MSM_RPM_ID_LDO24_0,
- MSM_RPM_ID_LDO24_1,
- MSM_RPM_ID_LDO25_0,
- MSM_RPM_ID_LDO25_1,
- MSM_RPM_ID_LVS0,
- MSM_RPM_ID_LVS1,
- MSM_RPM_ID_NCP_0,
- MSM_RPM_ID_NCP_1,
+ MSM_RPM_8660_ID_SMPS0_0,
+ MSM_RPM_8660_ID_SMPS0_1,
+ MSM_RPM_8660_ID_SMPS1_0,
+ MSM_RPM_8660_ID_SMPS1_1,
+ MSM_RPM_8660_ID_SMPS2_0,
+ MSM_RPM_8660_ID_SMPS2_1,
+ MSM_RPM_8660_ID_SMPS3_0,
+ MSM_RPM_8660_ID_SMPS3_1,
+ MSM_RPM_8660_ID_SMPS4_0,
+ MSM_RPM_8660_ID_SMPS4_1,
+ MSM_RPM_8660_ID_LDO0_0,
+ MSM_RPM_8660_ID_LDO0_1,
+ MSM_RPM_8660_ID_LDO1_0,
+ MSM_RPM_8660_ID_LDO1_1,
+ MSM_RPM_8660_ID_LDO2_0,
+ MSM_RPM_8660_ID_LDO2_1,
+ MSM_RPM_8660_ID_LDO3_0,
+ MSM_RPM_8660_ID_LDO3_1,
+ MSM_RPM_8660_ID_LDO4_0,
+ MSM_RPM_8660_ID_LDO4_1,
+ MSM_RPM_8660_ID_LDO5_0,
+ MSM_RPM_8660_ID_LDO5_1,
+ MSM_RPM_8660_ID_LDO6_0,
+ MSM_RPM_8660_ID_LDO6_1,
+ MSM_RPM_8660_ID_LDO7_0,
+ MSM_RPM_8660_ID_LDO7_1,
+ MSM_RPM_8660_ID_LDO8_0,
+ MSM_RPM_8660_ID_LDO8_1,
+ MSM_RPM_8660_ID_LDO9_0,
+ MSM_RPM_8660_ID_LDO9_1,
+ MSM_RPM_8660_ID_LDO10_0,
+ MSM_RPM_8660_ID_LDO10_1,
+ MSM_RPM_8660_ID_LDO11_0,
+ MSM_RPM_8660_ID_LDO11_1,
+ MSM_RPM_8660_ID_LDO12_0,
+ MSM_RPM_8660_ID_LDO12_1,
+ MSM_RPM_8660_ID_LDO13_0,
+ MSM_RPM_8660_ID_LDO13_1,
+ MSM_RPM_8660_ID_LDO14_0,
+ MSM_RPM_8660_ID_LDO14_1,
+ MSM_RPM_8660_ID_LDO15_0,
+ MSM_RPM_8660_ID_LDO15_1,
+ MSM_RPM_8660_ID_LDO16_0,
+ MSM_RPM_8660_ID_LDO16_1,
+ MSM_RPM_8660_ID_LDO17_0,
+ MSM_RPM_8660_ID_LDO17_1,
+ MSM_RPM_8660_ID_LDO18_0,
+ MSM_RPM_8660_ID_LDO18_1,
+ MSM_RPM_8660_ID_LDO19_0,
+ MSM_RPM_8660_ID_LDO19_1,
+ MSM_RPM_8660_ID_LDO20_0,
+ MSM_RPM_8660_ID_LDO20_1,
+ MSM_RPM_8660_ID_LDO21_0,
+ MSM_RPM_8660_ID_LDO21_1,
+ MSM_RPM_8660_ID_LDO22_0,
+ MSM_RPM_8660_ID_LDO22_1,
+ MSM_RPM_8660_ID_LDO23_0,
+ MSM_RPM_8660_ID_LDO23_1,
+ MSM_RPM_8660_ID_LDO24_0,
+ MSM_RPM_8660_ID_LDO24_1,
+ MSM_RPM_8660_ID_LDO25_0,
+ MSM_RPM_8660_ID_LDO25_1,
+ MSM_RPM_8660_ID_LVS0,
+ MSM_RPM_8660_ID_LVS1,
+ MSM_RPM_8660_ID_NCP_0,
+ MSM_RPM_8660_ID_NCP_1,
- MSM_RPM_ID_CXO_BUFFERS,
+ MSM_RPM_8660_ID_CXO_BUFFERS,
- MSM_RPM_ID_LAST = MSM_RPM_ID_CXO_BUFFERS
-};
-
-/* RPM resources RPM_ID aliases */
-enum {
- MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_TRIGGER_SET_FROM,
- MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_PXO_CLK,
- MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_APPS_L2_CACHE_CTL,
- MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_SMPS0_0,
- MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_SMPS0_1,
- MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_SMPS1_0,
- MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_SMPS1_1
-};
-
-/* VDD values are in millivolts */
-#define MSM_RPMRS_VDD_MASK 0xfff
-enum {
- MSM_RPMRS_VDD_MEM_RET_LOW = 500,
- MSM_RPMRS_VDD_MEM_RET_HIGH = 750,
- MSM_RPMRS_VDD_MEM_ACTIVE = 1000,
- MSM_RPMRS_VDD_MEM_MAX = 1250,
+ MSM_RPM_8660_ID_LAST = MSM_RPM_8660_ID_CXO_BUFFERS
};
enum {
- MSM_RPMRS_VDD_DIG_RET_LOW = 500,
- MSM_RPMRS_VDD_DIG_RET_HIGH = 750,
- MSM_RPMRS_VDD_DIG_ACTIVE = 1000,
- MSM_RPMRS_VDD_DIG_MAX = 1250,
-};
+ MSM_RPM_8660_STATUS_ID_VERSION_MAJOR,
+ MSM_RPM_8660_STATUS_ID_VERSION_MINOR,
+ MSM_RPM_8660_STATUS_ID_VERSION_BUILD,
+ MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_0,
+ MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_1,
+ MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_2,
+ MSM_RPM_8660_STATUS_ID_RESERVED_0,
+ MSM_RPM_8660_STATUS_ID_RESERVED_4 =
+ MSM_RPM_8660_STATUS_ID_RESERVED_0 + 4,
+ MSM_RPM_8660_STATUS_ID_SEQUENCE,
-enum {
- MSM_RPM_STATUS_ID_VERSION_MAJOR,
- MSM_RPM_STATUS_ID_VERSION_MINOR,
- MSM_RPM_STATUS_ID_VERSION_BUILD,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2,
- MSM_RPM_STATUS_ID_RESERVED_0,
- MSM_RPM_STATUS_ID_RESERVED_4 = MSM_RPM_STATUS_ID_RESERVED_0 + 4,
- MSM_RPM_STATUS_ID_SEQUENCE,
+ MSM_RPM_8660_STATUS_ID_CXO_CLK,
+ MSM_RPM_8660_STATUS_ID_PXO_CLK,
+ MSM_RPM_8660_STATUS_ID_PLL_4,
+ MSM_RPM_8660_STATUS_ID_APPS_FABRIC_CLK,
+ MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_CLK,
+ MSM_RPM_8660_STATUS_ID_MM_FABRIC_CLK,
+ MSM_RPM_8660_STATUS_ID_DAYTONA_FABRIC_CLK,
+ MSM_RPM_8660_STATUS_ID_SFPB_CLK,
+ MSM_RPM_8660_STATUS_ID_CFPB_CLK,
+ MSM_RPM_8660_STATUS_ID_MMFPB_CLK,
+ MSM_RPM_8660_STATUS_ID_SMI_CLK,
+ MSM_RPM_8660_STATUS_ID_EBI1_CLK,
- MSM_RPM_STATUS_ID_CXO_CLK,
- MSM_RPM_STATUS_ID_PXO_CLK,
- MSM_RPM_STATUS_ID_PLL_4,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CLK,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK,
- MSM_RPM_STATUS_ID_MM_FABRIC_CLK,
- MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK,
- MSM_RPM_STATUS_ID_SFPB_CLK,
- MSM_RPM_STATUS_ID_CFPB_CLK,
- MSM_RPM_STATUS_ID_MMFPB_CLK,
- MSM_RPM_STATUS_ID_SMI_CLK,
- MSM_RPM_STATUS_ID_EBI1_CLK,
+ MSM_RPM_8660_STATUS_ID_APPS_L2_CACHE_CTL,
- MSM_RPM_STATUS_ID_APPS_L2_CACHE_CTL,
+ MSM_RPM_8660_STATUS_ID_APPS_FABRIC_HALT,
+ MSM_RPM_8660_STATUS_ID_APPS_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_STATUS_ID_APPS_FABRIC_RESERVED,
+ MSM_RPM_8660_STATUS_ID_APPS_FABRIC_ARB,
- MSM_RPM_STATUS_ID_APPS_FABRIC_HALT,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CLOCK_MODE,
- MSM_RPM_STATUS_ID_APPS_FABRIC_RESERVED,
- MSM_RPM_STATUS_ID_APPS_FABRIC_ARB,
+ MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_HALT,
+ MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_RESERVED,
+ MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_ARB,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_HALT,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_RESERVED,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB,
-
- MSM_RPM_STATUS_ID_MM_FABRIC_HALT,
- MSM_RPM_STATUS_ID_MM_FABRIC_CLOCK_MODE,
- MSM_RPM_STATUS_ID_MM_FABRIC_RESERVED,
- MSM_RPM_STATUS_ID_MM_FABRIC_ARB,
+ MSM_RPM_8660_STATUS_ID_MM_FABRIC_HALT,
+ MSM_RPM_8660_STATUS_ID_MM_FABRIC_CLOCK_MODE,
+ MSM_RPM_8660_STATUS_ID_MM_FABRIC_RESERVED,
+ MSM_RPM_8660_STATUS_ID_MM_FABRIC_ARB,
/* pmic 8901 */
- MSM_RPM_STATUS_ID_SMPS0B_0,
- MSM_RPM_STATUS_ID_SMPS0B_1,
- MSM_RPM_STATUS_ID_SMPS1B_0,
- MSM_RPM_STATUS_ID_SMPS1B_1,
- MSM_RPM_STATUS_ID_SMPS2B_0,
- MSM_RPM_STATUS_ID_SMPS2B_1,
- MSM_RPM_STATUS_ID_SMPS3B_0,
- MSM_RPM_STATUS_ID_SMPS3B_1,
- MSM_RPM_STATUS_ID_SMPS4B_0,
- MSM_RPM_STATUS_ID_SMPS4B_1,
- MSM_RPM_STATUS_ID_LDO0B_0,
- MSM_RPM_STATUS_ID_LDO0B_1,
- MSM_RPM_STATUS_ID_LDO1B_0,
- MSM_RPM_STATUS_ID_LDO1B_1,
- MSM_RPM_STATUS_ID_LDO2B_0,
- MSM_RPM_STATUS_ID_LDO2B_1,
- MSM_RPM_STATUS_ID_LDO3B_0,
- MSM_RPM_STATUS_ID_LDO3B_1,
- MSM_RPM_STATUS_ID_LDO4B_0,
- MSM_RPM_STATUS_ID_LDO4B_1,
- MSM_RPM_STATUS_ID_LDO5B_0,
- MSM_RPM_STATUS_ID_LDO5B_1,
- MSM_RPM_STATUS_ID_LDO6B_0,
- MSM_RPM_STATUS_ID_LDO6B_1,
- MSM_RPM_STATUS_ID_LVS0B,
- MSM_RPM_STATUS_ID_LVS1B,
- MSM_RPM_STATUS_ID_LVS2B,
- MSM_RPM_STATUS_ID_LVS3B,
- MSM_RPM_STATUS_ID_MVS,
+ MSM_RPM_8660_STATUS_ID_SMPS0B_0,
+ MSM_RPM_8660_STATUS_ID_SMPS0B_1,
+ MSM_RPM_8660_STATUS_ID_SMPS1B_0,
+ MSM_RPM_8660_STATUS_ID_SMPS1B_1,
+ MSM_RPM_8660_STATUS_ID_SMPS2B_0,
+ MSM_RPM_8660_STATUS_ID_SMPS2B_1,
+ MSM_RPM_8660_STATUS_ID_SMPS3B_0,
+ MSM_RPM_8660_STATUS_ID_SMPS3B_1,
+ MSM_RPM_8660_STATUS_ID_SMPS4B_0,
+ MSM_RPM_8660_STATUS_ID_SMPS4B_1,
+ MSM_RPM_8660_STATUS_ID_LDO0B_0,
+ MSM_RPM_8660_STATUS_ID_LDO0B_1,
+ MSM_RPM_8660_STATUS_ID_LDO1B_0,
+ MSM_RPM_8660_STATUS_ID_LDO1B_1,
+ MSM_RPM_8660_STATUS_ID_LDO2B_0,
+ MSM_RPM_8660_STATUS_ID_LDO2B_1,
+ MSM_RPM_8660_STATUS_ID_LDO3B_0,
+ MSM_RPM_8660_STATUS_ID_LDO3B_1,
+ MSM_RPM_8660_STATUS_ID_LDO4B_0,
+ MSM_RPM_8660_STATUS_ID_LDO4B_1,
+ MSM_RPM_8660_STATUS_ID_LDO5B_0,
+ MSM_RPM_8660_STATUS_ID_LDO5B_1,
+ MSM_RPM_8660_STATUS_ID_LDO6B_0,
+ MSM_RPM_8660_STATUS_ID_LDO6B_1,
+ MSM_RPM_8660_STATUS_ID_LVS0B,
+ MSM_RPM_8660_STATUS_ID_LVS1B,
+ MSM_RPM_8660_STATUS_ID_LVS2B,
+ MSM_RPM_8660_STATUS_ID_LVS3B,
+ MSM_RPM_8660_STATUS_ID_MVS,
/* pmic 8058 */
- MSM_RPM_STATUS_ID_SMPS0_0,
- MSM_RPM_STATUS_ID_SMPS0_1,
- MSM_RPM_STATUS_ID_SMPS1_0,
- MSM_RPM_STATUS_ID_SMPS1_1,
- MSM_RPM_STATUS_ID_SMPS2_0,
- MSM_RPM_STATUS_ID_SMPS2_1,
- MSM_RPM_STATUS_ID_SMPS3_0,
- MSM_RPM_STATUS_ID_SMPS3_1,
- MSM_RPM_STATUS_ID_SMPS4_0,
- MSM_RPM_STATUS_ID_SMPS4_1,
- MSM_RPM_STATUS_ID_LDO0_0,
- MSM_RPM_STATUS_ID_LDO0_1,
- MSM_RPM_STATUS_ID_LDO1_0,
- MSM_RPM_STATUS_ID_LDO1_1,
- MSM_RPM_STATUS_ID_LDO2_0,
- MSM_RPM_STATUS_ID_LDO2_1,
- MSM_RPM_STATUS_ID_LDO3_0,
- MSM_RPM_STATUS_ID_LDO3_1,
- MSM_RPM_STATUS_ID_LDO4_0,
- MSM_RPM_STATUS_ID_LDO4_1,
- MSM_RPM_STATUS_ID_LDO5_0,
- MSM_RPM_STATUS_ID_LDO5_1,
- MSM_RPM_STATUS_ID_LDO6_0,
- MSM_RPM_STATUS_ID_LDO6_1,
- MSM_RPM_STATUS_ID_LDO7_0,
- MSM_RPM_STATUS_ID_LDO7_1,
- MSM_RPM_STATUS_ID_LDO8_0,
- MSM_RPM_STATUS_ID_LDO8_1,
- MSM_RPM_STATUS_ID_LDO9_0,
- MSM_RPM_STATUS_ID_LDO9_1,
- MSM_RPM_STATUS_ID_LDO10_0,
- MSM_RPM_STATUS_ID_LDO10_1,
- MSM_RPM_STATUS_ID_LDO11_0,
- MSM_RPM_STATUS_ID_LDO11_1,
- MSM_RPM_STATUS_ID_LDO12_0,
- MSM_RPM_STATUS_ID_LDO12_1,
- MSM_RPM_STATUS_ID_LDO13_0,
- MSM_RPM_STATUS_ID_LDO13_1,
- MSM_RPM_STATUS_ID_LDO14_0,
- MSM_RPM_STATUS_ID_LDO14_1,
- MSM_RPM_STATUS_ID_LDO15_0,
- MSM_RPM_STATUS_ID_LDO15_1,
- MSM_RPM_STATUS_ID_LDO16_0,
- MSM_RPM_STATUS_ID_LDO16_1,
- MSM_RPM_STATUS_ID_LDO17_0,
- MSM_RPM_STATUS_ID_LDO17_1,
- MSM_RPM_STATUS_ID_LDO18_0,
- MSM_RPM_STATUS_ID_LDO18_1,
- MSM_RPM_STATUS_ID_LDO19_0,
- MSM_RPM_STATUS_ID_LDO19_1,
- MSM_RPM_STATUS_ID_LDO20_0,
- MSM_RPM_STATUS_ID_LDO20_1,
- MSM_RPM_STATUS_ID_LDO21_0,
- MSM_RPM_STATUS_ID_LDO21_1,
- MSM_RPM_STATUS_ID_LDO22_0,
- MSM_RPM_STATUS_ID_LDO22_1,
- MSM_RPM_STATUS_ID_LDO23_0,
- MSM_RPM_STATUS_ID_LDO23_1,
- MSM_RPM_STATUS_ID_LDO24_0,
- MSM_RPM_STATUS_ID_LDO24_1,
- MSM_RPM_STATUS_ID_LDO25_0,
- MSM_RPM_STATUS_ID_LDO25_1,
- MSM_RPM_STATUS_ID_LVS0,
- MSM_RPM_STATUS_ID_LVS1,
- MSM_RPM_STATUS_ID_NCP_0,
- MSM_RPM_STATUS_ID_NCP_1,
+ MSM_RPM_8660_STATUS_ID_SMPS0_0,
+ MSM_RPM_8660_STATUS_ID_SMPS0_1,
+ MSM_RPM_8660_STATUS_ID_SMPS1_0,
+ MSM_RPM_8660_STATUS_ID_SMPS1_1,
+ MSM_RPM_8660_STATUS_ID_SMPS2_0,
+ MSM_RPM_8660_STATUS_ID_SMPS2_1,
+ MSM_RPM_8660_STATUS_ID_SMPS3_0,
+ MSM_RPM_8660_STATUS_ID_SMPS3_1,
+ MSM_RPM_8660_STATUS_ID_SMPS4_0,
+ MSM_RPM_8660_STATUS_ID_SMPS4_1,
+ MSM_RPM_8660_STATUS_ID_LDO0_0,
+ MSM_RPM_8660_STATUS_ID_LDO0_1,
+ MSM_RPM_8660_STATUS_ID_LDO1_0,
+ MSM_RPM_8660_STATUS_ID_LDO1_1,
+ MSM_RPM_8660_STATUS_ID_LDO2_0,
+ MSM_RPM_8660_STATUS_ID_LDO2_1,
+ MSM_RPM_8660_STATUS_ID_LDO3_0,
+ MSM_RPM_8660_STATUS_ID_LDO3_1,
+ MSM_RPM_8660_STATUS_ID_LDO4_0,
+ MSM_RPM_8660_STATUS_ID_LDO4_1,
+ MSM_RPM_8660_STATUS_ID_LDO5_0,
+ MSM_RPM_8660_STATUS_ID_LDO5_1,
+ MSM_RPM_8660_STATUS_ID_LDO6_0,
+ MSM_RPM_8660_STATUS_ID_LDO6_1,
+ MSM_RPM_8660_STATUS_ID_LDO7_0,
+ MSM_RPM_8660_STATUS_ID_LDO7_1,
+ MSM_RPM_8660_STATUS_ID_LDO8_0,
+ MSM_RPM_8660_STATUS_ID_LDO8_1,
+ MSM_RPM_8660_STATUS_ID_LDO9_0,
+ MSM_RPM_8660_STATUS_ID_LDO9_1,
+ MSM_RPM_8660_STATUS_ID_LDO10_0,
+ MSM_RPM_8660_STATUS_ID_LDO10_1,
+ MSM_RPM_8660_STATUS_ID_LDO11_0,
+ MSM_RPM_8660_STATUS_ID_LDO11_1,
+ MSM_RPM_8660_STATUS_ID_LDO12_0,
+ MSM_RPM_8660_STATUS_ID_LDO12_1,
+ MSM_RPM_8660_STATUS_ID_LDO13_0,
+ MSM_RPM_8660_STATUS_ID_LDO13_1,
+ MSM_RPM_8660_STATUS_ID_LDO14_0,
+ MSM_RPM_8660_STATUS_ID_LDO14_1,
+ MSM_RPM_8660_STATUS_ID_LDO15_0,
+ MSM_RPM_8660_STATUS_ID_LDO15_1,
+ MSM_RPM_8660_STATUS_ID_LDO16_0,
+ MSM_RPM_8660_STATUS_ID_LDO16_1,
+ MSM_RPM_8660_STATUS_ID_LDO17_0,
+ MSM_RPM_8660_STATUS_ID_LDO17_1,
+ MSM_RPM_8660_STATUS_ID_LDO18_0,
+ MSM_RPM_8660_STATUS_ID_LDO18_1,
+ MSM_RPM_8660_STATUS_ID_LDO19_0,
+ MSM_RPM_8660_STATUS_ID_LDO19_1,
+ MSM_RPM_8660_STATUS_ID_LDO20_0,
+ MSM_RPM_8660_STATUS_ID_LDO20_1,
+ MSM_RPM_8660_STATUS_ID_LDO21_0,
+ MSM_RPM_8660_STATUS_ID_LDO21_1,
+ MSM_RPM_8660_STATUS_ID_LDO22_0,
+ MSM_RPM_8660_STATUS_ID_LDO22_1,
+ MSM_RPM_8660_STATUS_ID_LDO23_0,
+ MSM_RPM_8660_STATUS_ID_LDO23_1,
+ MSM_RPM_8660_STATUS_ID_LDO24_0,
+ MSM_RPM_8660_STATUS_ID_LDO24_1,
+ MSM_RPM_8660_STATUS_ID_LDO25_0,
+ MSM_RPM_8660_STATUS_ID_LDO25_1,
+ MSM_RPM_8660_STATUS_ID_LVS0,
+ MSM_RPM_8660_STATUS_ID_LVS1,
+ MSM_RPM_8660_STATUS_ID_NCP_0,
+ MSM_RPM_8660_STATUS_ID_NCP_1,
- MSM_RPM_STATUS_ID_CXO_BUFFERS,
+ MSM_RPM_8660_STATUS_ID_CXO_BUFFERS,
- MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_CXO_BUFFERS
+ MSM_RPM_8660_STATUS_ID_LAST =
+ MSM_RPM_8660_STATUS_ID_CXO_BUFFERS
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8660_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-8930.h b/arch/arm/mach-msm/include/mach/rpm-8930.h
new file mode 100644
index 0000000..304a185
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-8930.h
@@ -0,0 +1,359 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_RPM_8930_H
+#define __ARCH_ARM_MACH_MSM_RPM_8930_H
+
+/* RPM control message RAM enums */
+enum {
+ MSM_RPM_8930_CTRL_VERSION_MAJOR,
+ MSM_RPM_8930_CTRL_VERSION_MINOR,
+ MSM_RPM_8930_CTRL_VERSION_BUILD,
+
+ MSM_RPM_8930_CTRL_REQ_CTX_0,
+ MSM_RPM_8930_CTRL_REQ_CTX_7 = MSM_RPM_8930_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_8930_CTRL_REQ_SEL_0,
+ MSM_RPM_8930_CTRL_REQ_SEL_3 = MSM_RPM_8930_CTRL_REQ_SEL_0 + 3,
+ MSM_RPM_8930_CTRL_ACK_CTX_0,
+ MSM_RPM_8930_CTRL_ACK_CTX_7 = MSM_RPM_8930_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_8930_CTRL_ACK_SEL_0,
+ MSM_RPM_8930_CTRL_ACK_SEL_7 = MSM_RPM_8930_CTRL_ACK_SEL_0 + 7,
+};
+
+/* RPM resource select enums defined for RPM core
+ NOT IN SEQUENTIAL ORDER */
+enum {
+ MSM_RPM_8930_SEL_NOTIFICATION = 0,
+ MSM_RPM_8930_SEL_INVALIDATE = 1,
+ MSM_RPM_8930_SEL_TRIGGER_TIMED_0 = 2,
+ MSM_RPM_8930_SEL_RPM_CTL = 3,
+ MSM_RPM_8930_SEL_CXO_CLK = 5,
+ MSM_RPM_8930_SEL_PXO_CLK = 6,
+ MSM_RPM_8930_SEL_QDSS_CLK = 7,
+ MSM_RPM_8930_SEL_APPS_FABRIC_CLK = 8,
+ MSM_RPM_8930_SEL_SYSTEM_FABRIC_CLK = 9,
+ MSM_RPM_8930_SEL_MM_FABRIC_CLK = 10,
+ MSM_RPM_8930_SEL_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_8930_SEL_SFPB_CLK = 12,
+ MSM_RPM_8930_SEL_CFPB_CLK = 13,
+ MSM_RPM_8930_SEL_MMFPB_CLK = 14,
+ MSM_RPM_8930_SEL_EBI1_CLK = 16,
+ MSM_RPM_8930_SEL_APPS_FABRIC_CFG_HALT = 18,
+ MSM_RPM_8930_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
+ MSM_RPM_8930_SEL_APPS_FABRIC_CFG_IOCTL = 20,
+ MSM_RPM_8930_SEL_APPS_FABRIC_ARB = 21,
+ MSM_RPM_8930_SEL_SYS_FABRIC_CFG_HALT = 22,
+ MSM_RPM_8930_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
+ MSM_RPM_8930_SEL_SYS_FABRIC_CFG_IOCTL = 24,
+ MSM_RPM_8930_SEL_SYSTEM_FABRIC_ARB = 25,
+ MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_HALT = 26,
+ MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
+ MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
+ MSM_RPM_8930_SEL_MM_FABRIC_ARB = 29,
+ MSM_RPM_8930_SEL_PM8038_S1 = 30,
+ MSM_RPM_8930_SEL_PM8038_S2 = 31,
+ MSM_RPM_8930_SEL_PM8038_S3 = 32,
+ MSM_RPM_8930_SEL_PM8038_S4 = 33,
+ MSM_RPM_8930_SEL_PM8038_S5 = 34,
+ MSM_RPM_8930_SEL_PM8038_S6 = 35,
+ MSM_RPM_8930_SEL_PM8038_L1 = 36,
+ MSM_RPM_8930_SEL_PM8038_L2 = 37,
+ MSM_RPM_8930_SEL_PM8038_L3 = 38,
+ MSM_RPM_8930_SEL_PM8038_L4 = 39,
+ MSM_RPM_8930_SEL_PM8038_L5 = 40,
+ MSM_RPM_8930_SEL_PM8038_L6 = 41,
+ MSM_RPM_8930_SEL_PM8038_L7 = 42,
+ MSM_RPM_8930_SEL_PM8038_L8 = 43,
+ MSM_RPM_8930_SEL_PM8038_L9 = 44,
+ MSM_RPM_8930_SEL_PM8038_L10 = 45,
+ MSM_RPM_8930_SEL_PM8038_L11 = 46,
+ MSM_RPM_8930_SEL_PM8038_L12 = 47,
+ MSM_RPM_8930_SEL_PM8038_L13 = 48,
+ MSM_RPM_8930_SEL_PM8038_L14 = 49,
+ MSM_RPM_8930_SEL_PM8038_L15 = 50,
+ MSM_RPM_8930_SEL_PM8038_L16 = 51,
+ MSM_RPM_8930_SEL_PM8038_L17 = 52,
+ MSM_RPM_8930_SEL_PM8038_L18 = 53,
+ MSM_RPM_8930_SEL_PM8038_L19 = 54,
+ MSM_RPM_8930_SEL_PM8038_L20 = 55,
+ MSM_RPM_8930_SEL_PM8038_L21 = 56,
+ MSM_RPM_8930_SEL_PM8038_L22 = 57,
+ MSM_RPM_8930_SEL_PM8038_L23 = 58,
+ MSM_RPM_8930_SEL_PM8038_L24 = 59,
+ MSM_RPM_8930_SEL_PM8038_L25 = 60,
+ MSM_RPM_8930_SEL_PM8038_L26 = 61,
+ MSM_RPM_8930_SEL_PM8038_L27 = 62,
+ MSM_RPM_8930_SEL_PM8038_CLK1 = 63,
+ MSM_RPM_8930_SEL_PM8038_CLK2 = 64,
+ MSM_RPM_8930_SEL_PM8038_LVS1 = 65,
+ MSM_RPM_8930_SEL_PM8038_LVS2 = 66,
+ MSM_RPM_8930_SEL_NCP = 80,
+ MSM_RPM_8930_SEL_CXO_BUFFERS = 81,
+ MSM_RPM_8930_SEL_USB_OTG_SWITCH = 82,
+ MSM_RPM_8930_SEL_HDMI_SWITCH = 83,
+ MSM_RPM_8930_SEL_LAST = MSM_RPM_8930_SEL_HDMI_SWITCH,
+};
+
+/* RPM resource (4 byte) word ID enum */
+enum {
+ MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_3 =
+ MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_0 + 3,
+
+ MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_0 = 4,
+ MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_3 =
+ MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_0 + 3,
+
+ MSM_RPM_8930_ID_INVALIDATE_0 = 8,
+ MSM_RPM_8930_ID_INVALIDATE_7 =
+ MSM_RPM_8930_ID_INVALIDATE_0 + 7,
+
+ MSM_RPM_8930_ID_TRIGGER_TIMED_0 = 16,
+ MSM_RPM_8930_ID_TRIGGER_TIMED_1 = 17,
+ MSM_RPM_8930_ID_RPM_CTL = 18,
+ MSM_RPM_8930_ID_RESERVED_0 = 19,
+ MSM_RPM_8930_ID_RESERVED_5 =
+ MSM_RPM_8930_ID_RESERVED_0 + 5,
+ MSM_RPM_8930_ID_CXO_CLK = 25,
+ MSM_RPM_8930_ID_PXO_CLK = 26,
+ MSM_RPM_8930_ID_APPS_FABRIC_CLK = 27,
+ MSM_RPM_8930_ID_SYSTEM_FABRIC_CLK = 28,
+ MSM_RPM_8930_ID_MM_FABRIC_CLK = 29,
+ MSM_RPM_8930_ID_DAYTONA_FABRIC_CLK = 30,
+ MSM_RPM_8930_ID_SFPB_CLK = 31,
+ MSM_RPM_8930_ID_CFPB_CLK = 32,
+ MSM_RPM_8930_ID_MMFPB_CLK = 33,
+ MSM_RPM_8930_ID_EBI1_CLK = 34,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_HALT_0 = 35,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_HALT_1 = 36,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
+ MSM_RPM_8930_ID_APPS_FABRIC_CFG_IOCTL = 40,
+ MSM_RPM_8930_ID_APPS_FABRIC_ARB_0 = 41,
+ MSM_RPM_8930_ID_APPS_FABRIC_ARB_5 =
+ MSM_RPM_8930_ID_APPS_FABRIC_ARB_0 + 5,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_HALT_0 = 47,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_HALT_1 = 48,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_0 = 49,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_1 = 50,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_2 = 51,
+ MSM_RPM_8930_ID_SYS_FABRIC_CFG_IOCTL = 52,
+ MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_0 = 53,
+ MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_19 =
+ MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_0 + 19,
+
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_HALT_0 = 73,
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_HALT_1 = 74,
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 75,
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 76,
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 77,
+ MSM_RPM_8930_ID_MMSS_FABRIC_CFG_IOCTL = 78,
+ MSM_RPM_8930_ID_MM_FABRIC_ARB_0 = 79,
+ MSM_RPM_8930_ID_MM_FABRIC_ARB_10 =
+ MSM_RPM_8930_ID_MM_FABRIC_ARB_0 + 10,
+
+ MSM_RPM_8930_ID_PM8038_S1_0 = 90,
+ MSM_RPM_8930_ID_PM8038_S1_1 = 91,
+ MSM_RPM_8930_ID_PM8038_S2_0 = 92,
+ MSM_RPM_8930_ID_PM8038_S2_1 = 93,
+ MSM_RPM_8930_ID_PM8038_S3_0 = 94,
+ MSM_RPM_8930_ID_PM8038_S3_1 = 95,
+ MSM_RPM_8930_ID_PM8038_S4_0 = 96,
+ MSM_RPM_8930_ID_PM8038_S4_1 = 97,
+ MSM_RPM_8930_ID_PM8038_S5_0 = 98,
+ MSM_RPM_8930_ID_PM8038_S5_1 = 99,
+ MSM_RPM_8930_ID_PM8038_S6_0 = 100,
+ MSM_RPM_8930_ID_PM8038_S6_1 = 101,
+ MSM_RPM_8930_ID_PM8038_L1_0 = 102,
+ MSM_RPM_8930_ID_PM8038_L1_1 = 103,
+ MSM_RPM_8930_ID_PM8038_L2_0 = 104,
+ MSM_RPM_8930_ID_PM8038_L2_1 = 105,
+ MSM_RPM_8930_ID_PM8038_L3_0 = 106,
+ MSM_RPM_8930_ID_PM8038_L3_1 = 107,
+ MSM_RPM_8930_ID_PM8038_L4_0 = 108,
+ MSM_RPM_8930_ID_PM8038_L4_1 = 109,
+ MSM_RPM_8930_ID_PM8038_L5_0 = 110,
+ MSM_RPM_8930_ID_PM8038_L5_1 = 111,
+ MSM_RPM_8930_ID_PM8038_L6_0 = 112,
+ MSM_RPM_8930_ID_PM8038_L6_1 = 113,
+ MSM_RPM_8930_ID_PM8038_L7_0 = 114,
+ MSM_RPM_8930_ID_PM8038_L7_1 = 115,
+ MSM_RPM_8930_ID_PM8038_L8_0 = 116,
+ MSM_RPM_8930_ID_PM8038_L8_1 = 117,
+ MSM_RPM_8930_ID_PM8038_L9_0 = 118,
+ MSM_RPM_8930_ID_PM8038_L9_1 = 119,
+ MSM_RPM_8930_ID_PM8038_L10_0 = 120,
+ MSM_RPM_8930_ID_PM8038_L10_1 = 121,
+ MSM_RPM_8930_ID_PM8038_L11_0 = 122,
+ MSM_RPM_8930_ID_PM8038_L11_1 = 123,
+ MSM_RPM_8930_ID_PM8038_L12_0 = 124,
+ MSM_RPM_8930_ID_PM8038_L12_1 = 125,
+ MSM_RPM_8930_ID_PM8038_L13_0 = 126,
+ MSM_RPM_8930_ID_PM8038_L13_1 = 127,
+ MSM_RPM_8930_ID_PM8038_L14_0 = 128,
+ MSM_RPM_8930_ID_PM8038_L14_1 = 129,
+ MSM_RPM_8930_ID_PM8038_L15_0 = 130,
+ MSM_RPM_8930_ID_PM8038_L15_1 = 131,
+ MSM_RPM_8930_ID_PM8038_L16_0 = 132,
+ MSM_RPM_8930_ID_PM8038_L16_1 = 133,
+ MSM_RPM_8930_ID_PM8038_L17_0 = 134,
+ MSM_RPM_8930_ID_PM8038_L17_1 = 135,
+ MSM_RPM_8930_ID_PM8038_L18_0 = 136,
+ MSM_RPM_8930_ID_PM8038_L18_1 = 137,
+ MSM_RPM_8930_ID_PM8038_L19_0 = 138,
+ MSM_RPM_8930_ID_PM8038_L19_1 = 139,
+ MSM_RPM_8930_ID_PM8038_L20_0 = 140,
+ MSM_RPM_8930_ID_PM8038_L20_1 = 141,
+ MSM_RPM_8930_ID_PM8038_L21_0 = 142,
+ MSM_RPM_8930_ID_PM8038_L21_1 = 143,
+ MSM_RPM_8930_ID_PM8038_L22_0 = 144,
+ MSM_RPM_8930_ID_PM8038_L22_1 = 145,
+ MSM_RPM_8930_ID_PM8038_L23_0 = 146,
+ MSM_RPM_8930_ID_PM8038_L23_1 = 147,
+ MSM_RPM_8930_ID_PM8038_L24_0 = 148,
+ MSM_RPM_8930_ID_PM8038_L24_1 = 149,
+ MSM_RPM_8930_ID_PM8038_L25_0 = 150,
+ MSM_RPM_8930_ID_PM8038_L25_1 = 151,
+ MSM_RPM_8930_ID_PM8038_L26_0 = 152,
+ MSM_RPM_8930_ID_PM8038_L26_1 = 153,
+ MSM_RPM_8930_ID_PM8038_L27_0 = 154,
+ MSM_RPM_8930_ID_PM8038_L27_1 = 155,
+ MSM_RPM_8930_ID_PM8038_CLK1_0 = 156,
+ MSM_RPM_8930_ID_PM8038_CLK1_1 = 157,
+ MSM_RPM_8930_ID_PM8038_CLK2_0 = 158,
+ MSM_RPM_8930_ID_PM8038_CLK2_1 = 159,
+ MSM_RPM_8930_ID_PM8038_LVS1 = 160,
+ MSM_RPM_8930_ID_PM8038_LVS2 = 161,
+ MSM_RPM_8930_ID_NCP_0 = 162,
+ MSM_RPM_8930_ID_NCP_1 = 163,
+ MSM_RPM_8930_ID_CXO_BUFFERS = 164,
+ MSM_RPM_8930_ID_USB_OTG_SWITCH = 165,
+ MSM_RPM_8930_ID_HDMI_SWITCH = 166,
+ MSM_RPM_8930_ID_QDSS_CLK = 167,
+ MSM_RPM_8930_ID_LAST = MSM_RPM_8930_ID_QDSS_CLK,
+};
+
+/* RPM status ID enum */
+enum {
+ MSM_RPM_8930_STATUS_ID_VERSION_MAJOR = 0,
+ MSM_RPM_8930_STATUS_ID_VERSION_MINOR = 1,
+ MSM_RPM_8930_STATUS_ID_VERSION_BUILD = 2,
+ MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
+ MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
+ MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
+ MSM_RPM_8930_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
+ MSM_RPM_8930_STATUS_ID_SEQUENCE = 7,
+ MSM_RPM_8930_STATUS_ID_RPM_CTL = 8,
+ MSM_RPM_8930_STATUS_ID_CXO_CLK = 9,
+ MSM_RPM_8930_STATUS_ID_PXO_CLK = 10,
+ MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CLK = 11,
+ MSM_RPM_8930_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
+ MSM_RPM_8930_STATUS_ID_MM_FABRIC_CLK = 13,
+ MSM_RPM_8930_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
+ MSM_RPM_8930_STATUS_ID_SFPB_CLK = 15,
+ MSM_RPM_8930_STATUS_ID_CFPB_CLK = 16,
+ MSM_RPM_8930_STATUS_ID_MMFPB_CLK = 17,
+ MSM_RPM_8930_STATUS_ID_EBI1_CLK = 18,
+ MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
+ MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
+ MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
+ MSM_RPM_8930_STATUS_ID_APPS_FABRIC_ARB = 22,
+ MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
+ MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
+ MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
+ MSM_RPM_8930_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
+ MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
+ MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
+ MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
+ MSM_RPM_8930_STATUS_ID_MM_FABRIC_ARB = 30,
+ MSM_RPM_8930_STATUS_ID_PM8038_S1_0 = 31,
+ MSM_RPM_8930_STATUS_ID_PM8038_S1_1 = 32,
+ MSM_RPM_8930_STATUS_ID_PM8038_S2_0 = 33,
+ MSM_RPM_8930_STATUS_ID_PM8038_S2_1 = 34,
+ MSM_RPM_8930_STATUS_ID_PM8038_S3_0 = 35,
+ MSM_RPM_8930_STATUS_ID_PM8038_S3_1 = 36,
+ MSM_RPM_8930_STATUS_ID_PM8038_S4_0 = 37,
+ MSM_RPM_8930_STATUS_ID_PM8038_S4_1 = 38,
+ MSM_RPM_8930_STATUS_ID_PM8038_S5_0 = 39,
+ MSM_RPM_8930_STATUS_ID_PM8038_S5_1 = 40,
+ MSM_RPM_8930_STATUS_ID_PM8038_S6_0 = 41,
+ MSM_RPM_8930_STATUS_ID_PM8038_S6_1 = 42,
+ MSM_RPM_8930_STATUS_ID_PM8038_L1_0 = 43,
+ MSM_RPM_8930_STATUS_ID_PM8038_L1_1 = 44,
+ MSM_RPM_8930_STATUS_ID_PM8038_L2_0 = 45,
+ MSM_RPM_8930_STATUS_ID_PM8038_L2_1 = 46,
+ MSM_RPM_8930_STATUS_ID_PM8038_L3_0 = 47,
+ MSM_RPM_8930_STATUS_ID_PM8038_L3_1 = 48,
+ MSM_RPM_8930_STATUS_ID_PM8038_L4_0 = 49,
+ MSM_RPM_8930_STATUS_ID_PM8038_L4_1 = 50,
+ MSM_RPM_8930_STATUS_ID_PM8038_L5_0 = 51,
+ MSM_RPM_8930_STATUS_ID_PM8038_L5_1 = 52,
+ MSM_RPM_8930_STATUS_ID_PM8038_L6_0 = 53,
+ MSM_RPM_8930_STATUS_ID_PM8038_L6_1 = 54,
+ MSM_RPM_8930_STATUS_ID_PM8038_L7_0 = 55,
+ MSM_RPM_8930_STATUS_ID_PM8038_L7_1 = 56,
+ MSM_RPM_8930_STATUS_ID_PM8038_L8_0 = 57,
+ MSM_RPM_8930_STATUS_ID_PM8038_L8_1 = 58,
+ MSM_RPM_8930_STATUS_ID_PM8038_L9_0 = 59,
+ MSM_RPM_8930_STATUS_ID_PM8038_L9_1 = 60,
+ MSM_RPM_8930_STATUS_ID_PM8038_L10_0 = 61,
+ MSM_RPM_8930_STATUS_ID_PM8038_L10_1 = 62,
+ MSM_RPM_8930_STATUS_ID_PM8038_L11_0 = 63,
+ MSM_RPM_8930_STATUS_ID_PM8038_L11_1 = 64,
+ MSM_RPM_8930_STATUS_ID_PM8038_L12_0 = 65,
+ MSM_RPM_8930_STATUS_ID_PM8038_L12_1 = 66,
+ MSM_RPM_8930_STATUS_ID_PM8038_L13_0 = 67,
+ MSM_RPM_8930_STATUS_ID_PM8038_L13_1 = 68,
+ MSM_RPM_8930_STATUS_ID_PM8038_L14_0 = 69,
+ MSM_RPM_8930_STATUS_ID_PM8038_L14_1 = 70,
+ MSM_RPM_8930_STATUS_ID_PM8038_L15_0 = 71,
+ MSM_RPM_8930_STATUS_ID_PM8038_L15_1 = 72,
+ MSM_RPM_8930_STATUS_ID_PM8038_L16_0 = 73,
+ MSM_RPM_8930_STATUS_ID_PM8038_L16_1 = 74,
+ MSM_RPM_8930_STATUS_ID_PM8038_L17_0 = 75,
+ MSM_RPM_8930_STATUS_ID_PM8038_L17_1 = 76,
+ MSM_RPM_8930_STATUS_ID_PM8038_L18_0 = 77,
+ MSM_RPM_8930_STATUS_ID_PM8038_L18_1 = 78,
+ MSM_RPM_8930_STATUS_ID_PM8038_L19_0 = 79,
+ MSM_RPM_8930_STATUS_ID_PM8038_L19_1 = 80,
+ MSM_RPM_8930_STATUS_ID_PM8038_L20_0 = 81,
+ MSM_RPM_8930_STATUS_ID_PM8038_L20_1 = 82,
+ MSM_RPM_8930_STATUS_ID_PM8038_L21_0 = 83,
+ MSM_RPM_8930_STATUS_ID_PM8038_L21_1 = 84,
+ MSM_RPM_8930_STATUS_ID_PM8038_L22_0 = 85,
+ MSM_RPM_8930_STATUS_ID_PM8038_L22_1 = 86,
+ MSM_RPM_8930_STATUS_ID_PM8038_L23_0 = 87,
+ MSM_RPM_8930_STATUS_ID_PM8038_L23_1 = 88,
+ MSM_RPM_8930_STATUS_ID_PM8038_L24_0 = 89,
+ MSM_RPM_8930_STATUS_ID_PM8038_L24_1 = 90,
+ MSM_RPM_8930_STATUS_ID_PM8038_L25_0 = 91,
+ MSM_RPM_8930_STATUS_ID_PM8038_L25_1 = 92,
+ MSM_RPM_8930_STATUS_ID_PM8038_L26_0 = 93,
+ MSM_RPM_8930_STATUS_ID_PM8038_L26_1 = 94,
+ MSM_RPM_8930_STATUS_ID_PM8038_L27_0 = 95,
+ MSM_RPM_8930_STATUS_ID_PM8038_L27_1 = 96,
+ MSM_RPM_8930_STATUS_ID_PM8038_CLK1_0 = 97,
+ MSM_RPM_8930_STATUS_ID_PM8038_CLK1_1 = 98,
+ MSM_RPM_8930_STATUS_ID_PM8038_CLK2_0 = 99,
+ MSM_RPM_8930_STATUS_ID_PM8038_CLK2_1 = 100,
+ MSM_RPM_8930_STATUS_ID_PM8038_LVS1 = 101,
+ MSM_RPM_8930_STATUS_ID_PM8038_LVS2 = 102,
+ MSM_RPM_8930_STATUS_ID_NCP_0 = 103,
+ MSM_RPM_8930_STATUS_ID_NCP_1 = 104,
+ MSM_RPM_8930_STATUS_ID_CXO_BUFFERS = 105,
+ MSM_RPM_8930_STATUS_ID_USB_OTG_SWITCH = 106,
+ MSM_RPM_8930_STATUS_ID_HDMI_SWITCH = 107,
+ MSM_RPM_8930_STATUS_ID_LAST = MSM_RPM_8930_STATUS_ID_HDMI_SWITCH,
+};
+
+#endif /* __ARCH_ARM_MACH_MSM_RPM_8930_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-8960.h b/arch/arm/mach-msm/include/mach/rpm-8960.h
index 41b94ae..6fe8832 100644
--- a/arch/arm/mach-msm/include/mach/rpm-8960.h
+++ b/arch/arm/mach-msm/include/mach/rpm-8960.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,439 +13,404 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_8960_H
#define __ARCH_ARM_MACH_MSM_RPM_8960_H
-#define RPM_MAJOR_VER 3
-#define RPM_MINOR_VER 0
-#define RPM_BUILD_VER 0
-
/* RPM control message RAM enums */
enum {
- MSM_RPM_CTRL_VERSION_MAJOR,
- MSM_RPM_CTRL_VERSION_MINOR,
- MSM_RPM_CTRL_VERSION_BUILD,
+ MSM_RPM_8960_CTRL_VERSION_MAJOR,
+ MSM_RPM_8960_CTRL_VERSION_MINOR,
+ MSM_RPM_8960_CTRL_VERSION_BUILD,
- MSM_RPM_CTRL_REQ_CTX_0,
- MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
- MSM_RPM_CTRL_REQ_SEL_0,
- MSM_RPM_CTRL_REQ_SEL_3 = MSM_RPM_CTRL_REQ_SEL_0 + 3,
- MSM_RPM_CTRL_ACK_CTX_0,
- MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
- MSM_RPM_CTRL_ACK_SEL_0,
- MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
+ MSM_RPM_8960_CTRL_REQ_CTX_0,
+ MSM_RPM_8960_CTRL_REQ_CTX_7 = MSM_RPM_8960_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_8960_CTRL_REQ_SEL_0,
+ MSM_RPM_8960_CTRL_REQ_SEL_3 = MSM_RPM_8960_CTRL_REQ_SEL_0 + 3,
+ MSM_RPM_8960_CTRL_ACK_CTX_0,
+ MSM_RPM_8960_CTRL_ACK_CTX_7 = MSM_RPM_8960_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_8960_CTRL_ACK_SEL_0,
+ MSM_RPM_8960_CTRL_ACK_SEL_7 = MSM_RPM_8960_CTRL_ACK_SEL_0 + 7,
};
-
/* RPM resource select enums defined for RPM core
NOT IN SEQUENTIAL ORDER */
enum {
- MSM_RPM_SEL_NOTIFICATION = 0,
- MSM_RPM_SEL_INVALIDATE = 1,
- MSM_RPM_SEL_TRIGGER_TIMED = 2,
- MSM_RPM_SEL_RPM_CTL = 3,
+ MSM_RPM_8960_SEL_NOTIFICATION = 0,
+ MSM_RPM_8960_SEL_INVALIDATE = 1,
+ MSM_RPM_8960_SEL_TRIGGER_TIMED = 2,
+ MSM_RPM_8960_SEL_RPM_CTL = 3,
- MSM_RPM_SEL_CXO_CLK = 5,
- MSM_RPM_SEL_PXO_CLK = 6,
- MSM_RPM_SEL_QDSS_CLK = 7,
- MSM_RPM_SEL_APPS_FABRIC_CLK = 8,
- MSM_RPM_SEL_SYSTEM_FABRIC_CLK = 9,
- MSM_RPM_SEL_MM_FABRIC_CLK = 10,
- MSM_RPM_SEL_DAYTONA_FABRIC_CLK = 11,
- MSM_RPM_SEL_SFPB_CLK = 12,
- MSM_RPM_SEL_CFPB_CLK = 13,
- MSM_RPM_SEL_MMFPB_CLK = 14,
- MSM_RPM_SEL_EBI1_CLK = 16,
+ MSM_RPM_8960_SEL_CXO_CLK = 5,
+ MSM_RPM_8960_SEL_PXO_CLK = 6,
+ MSM_RPM_8960_SEL_QDSS_CLK = 7,
+ MSM_RPM_8960_SEL_APPS_FABRIC_CLK = 8,
+ MSM_RPM_8960_SEL_SYSTEM_FABRIC_CLK = 9,
+ MSM_RPM_8960_SEL_MM_FABRIC_CLK = 10,
+ MSM_RPM_8960_SEL_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_8960_SEL_SFPB_CLK = 12,
+ MSM_RPM_8960_SEL_CFPB_CLK = 13,
+ MSM_RPM_8960_SEL_MMFPB_CLK = 14,
+ MSM_RPM_8960_SEL_EBI1_CLK = 16,
- MSM_RPM_SEL_APPS_FABRIC_CFG_HALT = 18,
- MSM_RPM_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
- MSM_RPM_SEL_APPS_FABRIC_CFG_IOCTL = 20,
- MSM_RPM_SEL_APPS_FABRIC_ARB = 21,
+ MSM_RPM_8960_SEL_APPS_FABRIC_CFG_HALT = 18,
+ MSM_RPM_8960_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
+ MSM_RPM_8960_SEL_APPS_FABRIC_CFG_IOCTL = 20,
+ MSM_RPM_8960_SEL_APPS_FABRIC_ARB = 21,
- MSM_RPM_SEL_SYS_FABRIC_CFG_HALT = 22,
- MSM_RPM_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
- MSM_RPM_SEL_SYS_FABRIC_CFG_IOCTL = 24,
- MSM_RPM_SEL_SYSTEM_FABRIC_ARB = 25,
+ MSM_RPM_8960_SEL_SYS_FABRIC_CFG_HALT = 22,
+ MSM_RPM_8960_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
+ MSM_RPM_8960_SEL_SYS_FABRIC_CFG_IOCTL = 24,
+ MSM_RPM_8960_SEL_SYSTEM_FABRIC_ARB = 25,
- MSM_RPM_SEL_MMSS_FABRIC_CFG_HALT = 26,
- MSM_RPM_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
- MSM_RPM_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
- MSM_RPM_SEL_MM_FABRIC_ARB = 29,
+ MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_HALT = 26,
+ MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
+ MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
+ MSM_RPM_8960_SEL_MM_FABRIC_ARB = 29,
- MSM_RPM_SEL_PM8921_S1 = 30,
- MSM_RPM_SEL_PM8921_S2 = 31,
- MSM_RPM_SEL_PM8921_S3 = 32,
- MSM_RPM_SEL_PM8921_S4 = 33,
- MSM_RPM_SEL_PM8921_S5 = 34,
- MSM_RPM_SEL_PM8921_S6 = 35,
- MSM_RPM_SEL_PM8921_S7 = 36,
- MSM_RPM_SEL_PM8921_S8 = 37,
- MSM_RPM_SEL_PM8921_L1 = 38,
- MSM_RPM_SEL_PM8921_L2 = 39,
- MSM_RPM_SEL_PM8921_L3 = 40,
- MSM_RPM_SEL_PM8921_L4 = 41,
- MSM_RPM_SEL_PM8921_L5 = 42,
- MSM_RPM_SEL_PM8921_L6 = 43,
- MSM_RPM_SEL_PM8921_L7 = 44,
- MSM_RPM_SEL_PM8921_L8 = 45,
- MSM_RPM_SEL_PM8921_L9 = 46,
- MSM_RPM_SEL_PM8921_L10 = 47,
- MSM_RPM_SEL_PM8921_L11 = 48,
- MSM_RPM_SEL_PM8921_L12 = 49,
- MSM_RPM_SEL_PM8921_L13 = 50,
- MSM_RPM_SEL_PM8921_L14 = 51,
- MSM_RPM_SEL_PM8921_L15 = 52,
- MSM_RPM_SEL_PM8921_L16 = 53,
- MSM_RPM_SEL_PM8921_L17 = 54,
- MSM_RPM_SEL_PM8921_L18 = 55,
- MSM_RPM_SEL_PM8921_L19 = 56,
- MSM_RPM_SEL_PM8921_L20 = 57,
- MSM_RPM_SEL_PM8921_L21 = 58,
- MSM_RPM_SEL_PM8921_L22 = 59,
- MSM_RPM_SEL_PM8921_L23 = 60,
- MSM_RPM_SEL_PM8921_L24 = 61,
- MSM_RPM_SEL_PM8921_L25 = 62,
- MSM_RPM_SEL_PM8921_L26 = 63,
- MSM_RPM_SEL_PM8921_L27 = 64,
- MSM_RPM_SEL_PM8921_L28 = 65,
- MSM_RPM_SEL_PM8921_L29 = 66,
- MSM_RPM_SEL_PM8921_CLK1 = 67,
- MSM_RPM_SEL_PM8921_CLK2 = 68,
- MSM_RPM_SEL_PM8921_LVS1 = 69,
- MSM_RPM_SEL_PM8921_LVS2 = 70,
- MSM_RPM_SEL_PM8921_LVS3 = 71,
- MSM_RPM_SEL_PM8921_LVS4 = 72,
- MSM_RPM_SEL_PM8921_LVS5 = 73,
- MSM_RPM_SEL_PM8921_LVS6 = 74,
- MSM_RPM_SEL_PM8921_LVS7 = 75,
+ MSM_RPM_8960_SEL_PM8921_S1 = 30,
+ MSM_RPM_8960_SEL_PM8921_S2 = 31,
+ MSM_RPM_8960_SEL_PM8921_S3 = 32,
+ MSM_RPM_8960_SEL_PM8921_S4 = 33,
+ MSM_RPM_8960_SEL_PM8921_S5 = 34,
+ MSM_RPM_8960_SEL_PM8921_S6 = 35,
+ MSM_RPM_8960_SEL_PM8921_S7 = 36,
+ MSM_RPM_8960_SEL_PM8921_S8 = 37,
+ MSM_RPM_8960_SEL_PM8921_L1 = 38,
+ MSM_RPM_8960_SEL_PM8921_L2 = 39,
+ MSM_RPM_8960_SEL_PM8921_L3 = 40,
+ MSM_RPM_8960_SEL_PM8921_L4 = 41,
+ MSM_RPM_8960_SEL_PM8921_L5 = 42,
+ MSM_RPM_8960_SEL_PM8921_L6 = 43,
+ MSM_RPM_8960_SEL_PM8921_L7 = 44,
+ MSM_RPM_8960_SEL_PM8921_L8 = 45,
+ MSM_RPM_8960_SEL_PM8921_L9 = 46,
+ MSM_RPM_8960_SEL_PM8921_L10 = 47,
+ MSM_RPM_8960_SEL_PM8921_L11 = 48,
+ MSM_RPM_8960_SEL_PM8921_L12 = 49,
+ MSM_RPM_8960_SEL_PM8921_L13 = 50,
+ MSM_RPM_8960_SEL_PM8921_L14 = 51,
+ MSM_RPM_8960_SEL_PM8921_L15 = 52,
+ MSM_RPM_8960_SEL_PM8921_L16 = 53,
+ MSM_RPM_8960_SEL_PM8921_L17 = 54,
+ MSM_RPM_8960_SEL_PM8921_L18 = 55,
+ MSM_RPM_8960_SEL_PM8921_L19 = 56,
+ MSM_RPM_8960_SEL_PM8921_L20 = 57,
+ MSM_RPM_8960_SEL_PM8921_L21 = 58,
+ MSM_RPM_8960_SEL_PM8921_L22 = 59,
+ MSM_RPM_8960_SEL_PM8921_L23 = 60,
+ MSM_RPM_8960_SEL_PM8921_L24 = 61,
+ MSM_RPM_8960_SEL_PM8921_L25 = 62,
+ MSM_RPM_8960_SEL_PM8921_L26 = 63,
+ MSM_RPM_8960_SEL_PM8921_L27 = 64,
+ MSM_RPM_8960_SEL_PM8921_L28 = 65,
+ MSM_RPM_8960_SEL_PM8921_L29 = 66,
+ MSM_RPM_8960_SEL_PM8921_CLK1 = 67,
+ MSM_RPM_8960_SEL_PM8921_CLK2 = 68,
+ MSM_RPM_8960_SEL_PM8921_LVS1 = 69,
+ MSM_RPM_8960_SEL_PM8921_LVS2 = 70,
+ MSM_RPM_8960_SEL_PM8921_LVS3 = 71,
+ MSM_RPM_8960_SEL_PM8921_LVS4 = 72,
+ MSM_RPM_8960_SEL_PM8921_LVS5 = 73,
+ MSM_RPM_8960_SEL_PM8921_LVS6 = 74,
+ MSM_RPM_8960_SEL_PM8921_LVS7 = 75,
- MSM_RPM_SEL_NCP = 80,
- MSM_RPM_SEL_CXO_BUFFERS = 81,
- MSM_RPM_SEL_USB_OTG_SWITCH = 82,
- MSM_RPM_SEL_HDMI_SWITCH = 83,
- MSM_RPM_SEL_DDR_DMM = 84,
+ MSM_RPM_8960_SEL_NCP = 80,
+ MSM_RPM_8960_SEL_CXO_BUFFERS = 81,
+ MSM_RPM_8960_SEL_USB_OTG_SWITCH = 82,
+ MSM_RPM_8960_SEL_HDMI_SWITCH = 83,
+ MSM_RPM_8960_SEL_DDR_DMM = 84,
- MSM_RPM_SEL_LAST = MSM_RPM_SEL_DDR_DMM,
+ MSM_RPM_8960_SEL_LAST = MSM_RPM_8960_SEL_DDR_DMM,
};
/* RPM resource (4 byte) word ID enum */
enum {
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_3 =
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 3,
+ MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_3 =
+ MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_0 + 3,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0 = 4,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_3 =
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 3,
+ MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_0 = 4,
+ MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_3 =
+ MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_0 + 3,
- MSM_RPM_ID_INVALIDATE_0 = 8,
- MSM_RPM_ID_INVALIDATE_7 =
- MSM_RPM_ID_INVALIDATE_0 + 7,
+ MSM_RPM_8960_ID_INVALIDATE_0 = 8,
+ MSM_RPM_8960_ID_INVALIDATE_7 =
+ MSM_RPM_8960_ID_INVALIDATE_0 + 7,
- MSM_RPM_ID_TRIGGER_TIMED_TO = 16,
- MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
+ MSM_RPM_8960_ID_TRIGGER_TIMED_TO = 16,
+ MSM_RPM_8960_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
- MSM_RPM_ID_RPM_CTL = 18,
+ MSM_RPM_8960_ID_RPM_CTL = 18,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
- MSM_RPM_ID_RESERVED_0 = 19,
- MSM_RPM_ID_RESERVED_5 =
- MSM_RPM_ID_RESERVED_0 + 5,
+ MSM_RPM_8960_ID_RESERVED_0 = 19,
+ MSM_RPM_8960_ID_RESERVED_5 =
+ MSM_RPM_8960_ID_RESERVED_0 + 5,
- MSM_RPM_ID_CXO_CLK = 25,
- MSM_RPM_ID_PXO_CLK = 26,
- MSM_RPM_ID_APPS_FABRIC_CLK = 27,
- MSM_RPM_ID_SYSTEM_FABRIC_CLK = 28,
- MSM_RPM_ID_MM_FABRIC_CLK = 29,
- MSM_RPM_ID_DAYTONA_FABRIC_CLK = 30,
- MSM_RPM_ID_SFPB_CLK = 31,
- MSM_RPM_ID_CFPB_CLK = 32,
- MSM_RPM_ID_MMFPB_CLK = 33,
- MSM_RPM_ID_EBI1_CLK = 34,
+ MSM_RPM_8960_ID_CXO_CLK = 25,
+ MSM_RPM_8960_ID_PXO_CLK = 26,
+ MSM_RPM_8960_ID_APPS_FABRIC_CLK = 27,
+ MSM_RPM_8960_ID_SYSTEM_FABRIC_CLK = 28,
+ MSM_RPM_8960_ID_MM_FABRIC_CLK = 29,
+ MSM_RPM_8960_ID_DAYTONA_FABRIC_CLK = 30,
+ MSM_RPM_8960_ID_SFPB_CLK = 31,
+ MSM_RPM_8960_ID_CFPB_CLK = 32,
+ MSM_RPM_8960_ID_MMFPB_CLK = 33,
+ MSM_RPM_8960_ID_EBI1_CLK = 34,
- MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0 = 35,
- MSM_RPM_ID_APPS_FABRIC_CFG_HALT_1 = 36,
- MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
- MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
- MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
- MSM_RPM_ID_APPS_FABRIC_CFG_IOCTL = 40,
- MSM_RPM_ID_APPS_FABRIC_ARB_0 = 41,
- MSM_RPM_ID_APPS_FABRIC_ARB_11 =
- MSM_RPM_ID_APPS_FABRIC_ARB_0 + 11,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_HALT_0 = 35,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_HALT_1 = 36,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
+ MSM_RPM_8960_ID_APPS_FABRIC_CFG_IOCTL = 40,
+ MSM_RPM_8960_ID_APPS_FABRIC_ARB_0 = 41,
+ MSM_RPM_8960_ID_APPS_FABRIC_ARB_11 =
+ MSM_RPM_8960_ID_APPS_FABRIC_ARB_0 + 11,
- MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0 = 53,
- MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1 = 54,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
- MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL = 58,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 = 59,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_28 =
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 28,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_HALT_0 = 53,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_HALT_1 = 54,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
+ MSM_RPM_8960_ID_SYS_FABRIC_CFG_IOCTL = 58,
+ MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_0 = 59,
+ MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_28 =
+ MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_0 + 28,
- MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0 = 88,
- MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_1 = 89,
- MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 90,
- MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 91,
- MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 92,
- MSM_RPM_ID_MMSS_FABRIC_CFG_IOCTL = 93,
- MSM_RPM_ID_MM_FABRIC_ARB_0 = 94,
- MSM_RPM_ID_MM_FABRIC_ARB_22 =
- MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_HALT_0 = 88,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_HALT_1 = 89,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 90,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 91,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 92,
+ MSM_RPM_8960_ID_MMSS_FABRIC_CFG_IOCTL = 93,
+ MSM_RPM_8960_ID_MM_FABRIC_ARB_0 = 94,
+ MSM_RPM_8960_ID_MM_FABRIC_ARB_22 =
+ MSM_RPM_8960_ID_MM_FABRIC_ARB_0 + 22,
- MSM_RPM_ID_PM8921_S1_0 = 117,
- MSM_RPM_ID_PM8921_S1_1 = 118,
- MSM_RPM_ID_PM8921_S2_0 = 119,
- MSM_RPM_ID_PM8921_S2_1 = 120,
- MSM_RPM_ID_PM8921_S3_0 = 121,
- MSM_RPM_ID_PM8921_S3_1 = 122,
- MSM_RPM_ID_PM8921_S4_0 = 123,
- MSM_RPM_ID_PM8921_S4_1 = 124,
- MSM_RPM_ID_PM8921_S5_0 = 125,
- MSM_RPM_ID_PM8921_S5_1 = 126,
- MSM_RPM_ID_PM8921_S6_0 = 127,
- MSM_RPM_ID_PM8921_S6_1 = 128,
- MSM_RPM_ID_PM8921_S7_0 = 129,
- MSM_RPM_ID_PM8921_S7_1 = 130,
- MSM_RPM_ID_PM8921_S8_0 = 131,
- MSM_RPM_ID_PM8921_S8_1 = 132,
- MSM_RPM_ID_PM8921_L1_0 = 133,
- MSM_RPM_ID_PM8921_L1_1 = 134,
- MSM_RPM_ID_PM8921_L2_0 = 135,
- MSM_RPM_ID_PM8921_L2_1 = 136,
- MSM_RPM_ID_PM8921_L3_0 = 137,
- MSM_RPM_ID_PM8921_L3_1 = 138,
- MSM_RPM_ID_PM8921_L4_0 = 139,
- MSM_RPM_ID_PM8921_L4_1 = 140,
- MSM_RPM_ID_PM8921_L5_0 = 141,
- MSM_RPM_ID_PM8921_L5_1 = 142,
- MSM_RPM_ID_PM8921_L6_0 = 143,
- MSM_RPM_ID_PM8921_L6_1 = 144,
- MSM_RPM_ID_PM8921_L7_0 = 145,
- MSM_RPM_ID_PM8921_L7_1 = 146,
- MSM_RPM_ID_PM8921_L8_0 = 147,
- MSM_RPM_ID_PM8921_L8_1 = 148,
- MSM_RPM_ID_PM8921_L9_0 = 149,
- MSM_RPM_ID_PM8921_L9_1 = 150,
- MSM_RPM_ID_PM8921_L10_0 = 151,
- MSM_RPM_ID_PM8921_L10_1 = 152,
- MSM_RPM_ID_PM8921_L11_0 = 153,
- MSM_RPM_ID_PM8921_L11_1 = 154,
- MSM_RPM_ID_PM8921_L12_0 = 155,
- MSM_RPM_ID_PM8921_L12_1 = 156,
- MSM_RPM_ID_PM8921_L13_0 = 157,
- MSM_RPM_ID_PM8921_L13_1 = 158,
- MSM_RPM_ID_PM8921_L14_0 = 159,
- MSM_RPM_ID_PM8921_L14_1 = 160,
- MSM_RPM_ID_PM8921_L15_0 = 161,
- MSM_RPM_ID_PM8921_L15_1 = 162,
- MSM_RPM_ID_PM8921_L16_0 = 163,
- MSM_RPM_ID_PM8921_L16_1 = 164,
- MSM_RPM_ID_PM8921_L17_0 = 165,
- MSM_RPM_ID_PM8921_L17_1 = 166,
- MSM_RPM_ID_PM8921_L18_0 = 167,
- MSM_RPM_ID_PM8921_L18_1 = 168,
- MSM_RPM_ID_PM8921_L19_0 = 169,
- MSM_RPM_ID_PM8921_L19_1 = 170,
- MSM_RPM_ID_PM8921_L20_0 = 171,
- MSM_RPM_ID_PM8921_L20_1 = 172,
- MSM_RPM_ID_PM8921_L21_0 = 173,
- MSM_RPM_ID_PM8921_L21_1 = 174,
- MSM_RPM_ID_PM8921_L22_0 = 175,
- MSM_RPM_ID_PM8921_L22_1 = 176,
- MSM_RPM_ID_PM8921_L23_0 = 177,
- MSM_RPM_ID_PM8921_L23_1 = 178,
- MSM_RPM_ID_PM8921_L24_0 = 179,
- MSM_RPM_ID_PM8921_L24_1 = 180,
- MSM_RPM_ID_PM8921_L25_0 = 181,
- MSM_RPM_ID_PM8921_L25_1 = 182,
- MSM_RPM_ID_PM8921_L26_0 = 183,
- MSM_RPM_ID_PM8921_L26_1 = 184,
- MSM_RPM_ID_PM8921_L27_0 = 185,
- MSM_RPM_ID_PM8921_L27_1 = 186,
- MSM_RPM_ID_PM8921_L28_0 = 187,
- MSM_RPM_ID_PM8921_L28_1 = 188,
- MSM_RPM_ID_PM8921_L29_0 = 189,
- MSM_RPM_ID_PM8921_L29_1 = 190,
- MSM_RPM_ID_PM8921_CLK1_0 = 191,
- MSM_RPM_ID_PM8921_CLK1_1 = 192,
- MSM_RPM_ID_PM8921_CLK2_0 = 193,
- MSM_RPM_ID_PM8921_CLK2_1 = 194,
- MSM_RPM_ID_PM8921_LVS1 = 195,
- MSM_RPM_ID_PM8921_LVS2 = 196,
- MSM_RPM_ID_PM8921_LVS3 = 197,
- MSM_RPM_ID_PM8921_LVS4 = 198,
- MSM_RPM_ID_PM8921_LVS5 = 199,
- MSM_RPM_ID_PM8921_LVS6 = 200,
- MSM_RPM_ID_PM8921_LVS7 = 201,
- MSM_RPM_ID_NCP_0 = 202,
- MSM_RPM_ID_NCP_1 = 203,
- MSM_RPM_ID_CXO_BUFFERS = 204,
- MSM_RPM_ID_USB_OTG_SWITCH = 205,
- MSM_RPM_ID_HDMI_SWITCH = 206,
- MSM_RPM_ID_DDR_DMM_0 = 207,
- MSM_RPM_ID_DDR_DMM_1 = 208,
- MSM_RPM_ID_QDSS_CLK = 209,
+ MSM_RPM_8960_ID_PM8921_S1_0 = 117,
+ MSM_RPM_8960_ID_PM8921_S1_1 = 118,
+ MSM_RPM_8960_ID_PM8921_S2_0 = 119,
+ MSM_RPM_8960_ID_PM8921_S2_1 = 120,
+ MSM_RPM_8960_ID_PM8921_S3_0 = 121,
+ MSM_RPM_8960_ID_PM8921_S3_1 = 122,
+ MSM_RPM_8960_ID_PM8921_S4_0 = 123,
+ MSM_RPM_8960_ID_PM8921_S4_1 = 124,
+ MSM_RPM_8960_ID_PM8921_S5_0 = 125,
+ MSM_RPM_8960_ID_PM8921_S5_1 = 126,
+ MSM_RPM_8960_ID_PM8921_S6_0 = 127,
+ MSM_RPM_8960_ID_PM8921_S6_1 = 128,
+ MSM_RPM_8960_ID_PM8921_S7_0 = 129,
+ MSM_RPM_8960_ID_PM8921_S7_1 = 130,
+ MSM_RPM_8960_ID_PM8921_S8_0 = 131,
+ MSM_RPM_8960_ID_PM8921_S8_1 = 132,
+ MSM_RPM_8960_ID_PM8921_L1_0 = 133,
+ MSM_RPM_8960_ID_PM8921_L1_1 = 134,
+ MSM_RPM_8960_ID_PM8921_L2_0 = 135,
+ MSM_RPM_8960_ID_PM8921_L2_1 = 136,
+ MSM_RPM_8960_ID_PM8921_L3_0 = 137,
+ MSM_RPM_8960_ID_PM8921_L3_1 = 138,
+ MSM_RPM_8960_ID_PM8921_L4_0 = 139,
+ MSM_RPM_8960_ID_PM8921_L4_1 = 140,
+ MSM_RPM_8960_ID_PM8921_L5_0 = 141,
+ MSM_RPM_8960_ID_PM8921_L5_1 = 142,
+ MSM_RPM_8960_ID_PM8921_L6_0 = 143,
+ MSM_RPM_8960_ID_PM8921_L6_1 = 144,
+ MSM_RPM_8960_ID_PM8921_L7_0 = 145,
+ MSM_RPM_8960_ID_PM8921_L7_1 = 146,
+ MSM_RPM_8960_ID_PM8921_L8_0 = 147,
+ MSM_RPM_8960_ID_PM8921_L8_1 = 148,
+ MSM_RPM_8960_ID_PM8921_L9_0 = 149,
+ MSM_RPM_8960_ID_PM8921_L9_1 = 150,
+ MSM_RPM_8960_ID_PM8921_L10_0 = 151,
+ MSM_RPM_8960_ID_PM8921_L10_1 = 152,
+ MSM_RPM_8960_ID_PM8921_L11_0 = 153,
+ MSM_RPM_8960_ID_PM8921_L11_1 = 154,
+ MSM_RPM_8960_ID_PM8921_L12_0 = 155,
+ MSM_RPM_8960_ID_PM8921_L12_1 = 156,
+ MSM_RPM_8960_ID_PM8921_L13_0 = 157,
+ MSM_RPM_8960_ID_PM8921_L13_1 = 158,
+ MSM_RPM_8960_ID_PM8921_L14_0 = 159,
+ MSM_RPM_8960_ID_PM8921_L14_1 = 160,
+ MSM_RPM_8960_ID_PM8921_L15_0 = 161,
+ MSM_RPM_8960_ID_PM8921_L15_1 = 162,
+ MSM_RPM_8960_ID_PM8921_L16_0 = 163,
+ MSM_RPM_8960_ID_PM8921_L16_1 = 164,
+ MSM_RPM_8960_ID_PM8921_L17_0 = 165,
+ MSM_RPM_8960_ID_PM8921_L17_1 = 166,
+ MSM_RPM_8960_ID_PM8921_L18_0 = 167,
+ MSM_RPM_8960_ID_PM8921_L18_1 = 168,
+ MSM_RPM_8960_ID_PM8921_L19_0 = 169,
+ MSM_RPM_8960_ID_PM8921_L19_1 = 170,
+ MSM_RPM_8960_ID_PM8921_L20_0 = 171,
+ MSM_RPM_8960_ID_PM8921_L20_1 = 172,
+ MSM_RPM_8960_ID_PM8921_L21_0 = 173,
+ MSM_RPM_8960_ID_PM8921_L21_1 = 174,
+ MSM_RPM_8960_ID_PM8921_L22_0 = 175,
+ MSM_RPM_8960_ID_PM8921_L22_1 = 176,
+ MSM_RPM_8960_ID_PM8921_L23_0 = 177,
+ MSM_RPM_8960_ID_PM8921_L23_1 = 178,
+ MSM_RPM_8960_ID_PM8921_L24_0 = 179,
+ MSM_RPM_8960_ID_PM8921_L24_1 = 180,
+ MSM_RPM_8960_ID_PM8921_L25_0 = 181,
+ MSM_RPM_8960_ID_PM8921_L25_1 = 182,
+ MSM_RPM_8960_ID_PM8921_L26_0 = 183,
+ MSM_RPM_8960_ID_PM8921_L26_1 = 184,
+ MSM_RPM_8960_ID_PM8921_L27_0 = 185,
+ MSM_RPM_8960_ID_PM8921_L27_1 = 186,
+ MSM_RPM_8960_ID_PM8921_L28_0 = 187,
+ MSM_RPM_8960_ID_PM8921_L28_1 = 188,
+ MSM_RPM_8960_ID_PM8921_L29_0 = 189,
+ MSM_RPM_8960_ID_PM8921_L29_1 = 190,
+ MSM_RPM_8960_ID_PM8921_CLK1_0 = 191,
+ MSM_RPM_8960_ID_PM8921_CLK1_1 = 192,
+ MSM_RPM_8960_ID_PM8921_CLK2_0 = 193,
+ MSM_RPM_8960_ID_PM8921_CLK2_1 = 194,
+ MSM_RPM_8960_ID_PM8921_LVS1 = 195,
+ MSM_RPM_8960_ID_PM8921_LVS2 = 196,
+ MSM_RPM_8960_ID_PM8921_LVS3 = 197,
+ MSM_RPM_8960_ID_PM8921_LVS4 = 198,
+ MSM_RPM_8960_ID_PM8921_LVS5 = 199,
+ MSM_RPM_8960_ID_PM8921_LVS6 = 200,
+ MSM_RPM_8960_ID_PM8921_LVS7 = 201,
+ MSM_RPM_8960_ID_NCP_0 = 202,
+ MSM_RPM_8960_ID_NCP_1 = 203,
+ MSM_RPM_8960_ID_CXO_BUFFERS = 204,
+ MSM_RPM_8960_ID_USB_OTG_SWITCH = 205,
+ MSM_RPM_8960_ID_HDMI_SWITCH = 206,
+ MSM_RPM_8960_ID_DDR_DMM_0 = 207,
+ MSM_RPM_8960_ID_DDR_DMM_1 = 208,
+ MSM_RPM_8960_ID_QDSS_CLK = 209,
- MSM_RPM_ID_LAST = MSM_RPM_ID_QDSS_CLK,
-};
-
-/* RPM resources RPM_ID aliases */
-enum {
- MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_RPM_CTL,
- MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_PXO_CLK,
- MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_PM8921_S3_0,
- MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_PM8921_S3_1,
- MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_PM8921_L24_0,
- MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_PM8921_L24_1,
-
- /* MSM8960 L2 cache power control not via RPM
- * MSM_RPM_ID_LAST + 1 indicates invalid */
- MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_LAST + 1
-};
-
-/* VDD values are in microvolts */
-#define MSM_RPMRS_VDD_MASK 0x7fffff
-enum {
- MSM_RPMRS_VDD_MEM_RET_LOW = 750000,
- MSM_RPMRS_VDD_MEM_RET_HIGH = 750000,
- MSM_RPMRS_VDD_MEM_ACTIVE = 1050000,
- MSM_RPMRS_VDD_MEM_MAX = 1150000,
-};
-
-enum {
- MSM_RPMRS_VDD_DIG_RET_LOW = 500000,
- MSM_RPMRS_VDD_DIG_RET_HIGH = 750000,
- MSM_RPMRS_VDD_DIG_ACTIVE = 950000,
- MSM_RPMRS_VDD_DIG_MAX = 1150000,
+ MSM_RPM_8960_ID_LAST = MSM_RPM_8960_ID_QDSS_CLK,
};
/* RPM status ID enum */
enum {
- MSM_RPM_STATUS_ID_VERSION_MAJOR = 0,
- MSM_RPM_STATUS_ID_VERSION_MINOR = 1,
- MSM_RPM_STATUS_ID_VERSION_BUILD = 2,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
- MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
- MSM_RPM_STATUS_ID_SEQUENCE = 7,
- MSM_RPM_STATUS_ID_RPM_CTL = 8,
- MSM_RPM_STATUS_ID_CXO_CLK = 9,
- MSM_RPM_STATUS_ID_PXO_CLK = 10,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CLK = 11,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
- MSM_RPM_STATUS_ID_MM_FABRIC_CLK = 13,
- MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
- MSM_RPM_STATUS_ID_SFPB_CLK = 15,
- MSM_RPM_STATUS_ID_CFPB_CLK = 16,
- MSM_RPM_STATUS_ID_MMFPB_CLK = 17,
- MSM_RPM_STATUS_ID_EBI1_CLK = 18,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
- MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
- MSM_RPM_STATUS_ID_APPS_FABRIC_ARB = 22,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
- MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
- MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
- MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
- MSM_RPM_STATUS_ID_MM_FABRIC_ARB = 30,
- MSM_RPM_STATUS_ID_PM8921_S1_0 = 31,
- MSM_RPM_STATUS_ID_PM8921_S1_1 = 32,
- MSM_RPM_STATUS_ID_PM8921_S2_0 = 33,
- MSM_RPM_STATUS_ID_PM8921_S2_1 = 34,
- MSM_RPM_STATUS_ID_PM8921_S3_0 = 35,
- MSM_RPM_STATUS_ID_PM8921_S3_1 = 36,
- MSM_RPM_STATUS_ID_PM8921_S4_0 = 37,
- MSM_RPM_STATUS_ID_PM8921_S4_1 = 38,
- MSM_RPM_STATUS_ID_PM8921_S5_0 = 39,
- MSM_RPM_STATUS_ID_PM8921_S5_1 = 40,
- MSM_RPM_STATUS_ID_PM8921_S6_0 = 41,
- MSM_RPM_STATUS_ID_PM8921_S6_1 = 42,
- MSM_RPM_STATUS_ID_PM8921_S7_0 = 43,
- MSM_RPM_STATUS_ID_PM8921_S7_1 = 44,
- MSM_RPM_STATUS_ID_PM8921_S8_0 = 45,
- MSM_RPM_STATUS_ID_PM8921_S8_1 = 46,
- MSM_RPM_STATUS_ID_PM8921_L1_0 = 47,
- MSM_RPM_STATUS_ID_PM8921_L1_1 = 48,
- MSM_RPM_STATUS_ID_PM8921_L2_0 = 49,
- MSM_RPM_STATUS_ID_PM8921_L2_1 = 50,
- MSM_RPM_STATUS_ID_PM8921_L3_0 = 51,
- MSM_RPM_STATUS_ID_PM8921_L3_1 = 52,
- MSM_RPM_STATUS_ID_PM8921_L4_0 = 53,
- MSM_RPM_STATUS_ID_PM8921_L4_1 = 54,
- MSM_RPM_STATUS_ID_PM8921_L5_0 = 55,
- MSM_RPM_STATUS_ID_PM8921_L5_1 = 56,
- MSM_RPM_STATUS_ID_PM8921_L6_0 = 57,
- MSM_RPM_STATUS_ID_PM8921_L6_1 = 58,
- MSM_RPM_STATUS_ID_PM8921_L7_0 = 59,
- MSM_RPM_STATUS_ID_PM8921_L7_1 = 60,
- MSM_RPM_STATUS_ID_PM8921_L8_0 = 61,
- MSM_RPM_STATUS_ID_PM8921_L8_1 = 62,
- MSM_RPM_STATUS_ID_PM8921_L9_0 = 63,
- MSM_RPM_STATUS_ID_PM8921_L9_1 = 64,
- MSM_RPM_STATUS_ID_PM8921_L10_0 = 65,
- MSM_RPM_STATUS_ID_PM8921_L10_1 = 66,
- MSM_RPM_STATUS_ID_PM8921_L11_0 = 67,
- MSM_RPM_STATUS_ID_PM8921_L11_1 = 68,
- MSM_RPM_STATUS_ID_PM8921_L12_0 = 69,
- MSM_RPM_STATUS_ID_PM8921_L12_1 = 70,
- MSM_RPM_STATUS_ID_PM8921_L13_0 = 71,
- MSM_RPM_STATUS_ID_PM8921_L13_1 = 72,
- MSM_RPM_STATUS_ID_PM8921_L14_0 = 73,
- MSM_RPM_STATUS_ID_PM8921_L14_1 = 74,
- MSM_RPM_STATUS_ID_PM8921_L15_0 = 75,
- MSM_RPM_STATUS_ID_PM8921_L15_1 = 76,
- MSM_RPM_STATUS_ID_PM8921_L16_0 = 77,
- MSM_RPM_STATUS_ID_PM8921_L16_1 = 78,
- MSM_RPM_STATUS_ID_PM8921_L17_0 = 79,
- MSM_RPM_STATUS_ID_PM8921_L17_1 = 80,
- MSM_RPM_STATUS_ID_PM8921_L18_0 = 81,
- MSM_RPM_STATUS_ID_PM8921_L18_1 = 82,
- MSM_RPM_STATUS_ID_PM8921_L19_0 = 83,
- MSM_RPM_STATUS_ID_PM8921_L19_1 = 84,
- MSM_RPM_STATUS_ID_PM8921_L20_0 = 85,
- MSM_RPM_STATUS_ID_PM8921_L20_1 = 86,
- MSM_RPM_STATUS_ID_PM8921_L21_0 = 87,
- MSM_RPM_STATUS_ID_PM8921_L21_1 = 88,
- MSM_RPM_STATUS_ID_PM8921_L22_0 = 89,
- MSM_RPM_STATUS_ID_PM8921_L22_1 = 90,
- MSM_RPM_STATUS_ID_PM8921_L23_0 = 91,
- MSM_RPM_STATUS_ID_PM8921_L23_1 = 92,
- MSM_RPM_STATUS_ID_PM8921_L24_0 = 93,
- MSM_RPM_STATUS_ID_PM8921_L24_1 = 94,
- MSM_RPM_STATUS_ID_PM8921_L25_0 = 95,
- MSM_RPM_STATUS_ID_PM8921_L25_1 = 96,
- MSM_RPM_STATUS_ID_PM8921_L26_0 = 97,
- MSM_RPM_STATUS_ID_PM8921_L26_1 = 98,
- MSM_RPM_STATUS_ID_PM8921_L27_0 = 99,
- MSM_RPM_STATUS_ID_PM8921_L27_1 = 100,
- MSM_RPM_STATUS_ID_PM8921_L28_0 = 101,
- MSM_RPM_STATUS_ID_PM8921_L28_1 = 102,
- MSM_RPM_STATUS_ID_PM8921_L29_0 = 103,
- MSM_RPM_STATUS_ID_PM8921_L29_1 = 104,
- MSM_RPM_STATUS_ID_PM8921_CLK1_0 = 105,
- MSM_RPM_STATUS_ID_PM8921_CLK1_1 = 106,
- MSM_RPM_STATUS_ID_PM8921_CLK2_0 = 107,
- MSM_RPM_STATUS_ID_PM8921_CLK2_1 = 108,
- MSM_RPM_STATUS_ID_PM8921_LVS1 = 109,
- MSM_RPM_STATUS_ID_PM8921_LVS2 = 110,
- MSM_RPM_STATUS_ID_PM8921_LVS3 = 111,
- MSM_RPM_STATUS_ID_PM8921_LVS4 = 112,
- MSM_RPM_STATUS_ID_PM8921_LVS5 = 113,
- MSM_RPM_STATUS_ID_PM8921_LVS6 = 114,
- MSM_RPM_STATUS_ID_PM8921_LVS7 = 115,
- MSM_RPM_STATUS_ID_NCP_0 = 116,
- MSM_RPM_STATUS_ID_NCP_1 = 117,
- MSM_RPM_STATUS_ID_CXO_BUFFERS = 118,
- MSM_RPM_STATUS_ID_USB_OTG_SWITCH = 119,
- MSM_RPM_STATUS_ID_HDMI_SWITCH = 120,
- MSM_RPM_STATUS_ID_DDR_DMM_0 = 121,
- MSM_RPM_STATUS_ID_DDR_DMM_1 = 122,
- MSM_RPM_STATUS_ID_EBI1_CH0_RANGE = 123,
- MSM_RPM_STATUS_ID_EBI1_CH1_RANGE = 124,
+ MSM_RPM_8960_STATUS_ID_VERSION_MAJOR = 0,
+ MSM_RPM_8960_STATUS_ID_VERSION_MINOR = 1,
+ MSM_RPM_8960_STATUS_ID_VERSION_BUILD = 2,
+ MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
+ MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
+ MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
+ MSM_RPM_8960_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
+ MSM_RPM_8960_STATUS_ID_SEQUENCE = 7,
+ MSM_RPM_8960_STATUS_ID_RPM_CTL = 8,
+ MSM_RPM_8960_STATUS_ID_CXO_CLK = 9,
+ MSM_RPM_8960_STATUS_ID_PXO_CLK = 10,
+ MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CLK = 11,
+ MSM_RPM_8960_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
+ MSM_RPM_8960_STATUS_ID_MM_FABRIC_CLK = 13,
+ MSM_RPM_8960_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
+ MSM_RPM_8960_STATUS_ID_SFPB_CLK = 15,
+ MSM_RPM_8960_STATUS_ID_CFPB_CLK = 16,
+ MSM_RPM_8960_STATUS_ID_MMFPB_CLK = 17,
+ MSM_RPM_8960_STATUS_ID_EBI1_CLK = 18,
+ MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
+ MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
+ MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
+ MSM_RPM_8960_STATUS_ID_APPS_FABRIC_ARB = 22,
+ MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
+ MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
+ MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
+ MSM_RPM_8960_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
+ MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
+ MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
+ MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
+ MSM_RPM_8960_STATUS_ID_MM_FABRIC_ARB = 30,
+ MSM_RPM_8960_STATUS_ID_PM8921_S1_0 = 31,
+ MSM_RPM_8960_STATUS_ID_PM8921_S1_1 = 32,
+ MSM_RPM_8960_STATUS_ID_PM8921_S2_0 = 33,
+ MSM_RPM_8960_STATUS_ID_PM8921_S2_1 = 34,
+ MSM_RPM_8960_STATUS_ID_PM8921_S3_0 = 35,
+ MSM_RPM_8960_STATUS_ID_PM8921_S3_1 = 36,
+ MSM_RPM_8960_STATUS_ID_PM8921_S4_0 = 37,
+ MSM_RPM_8960_STATUS_ID_PM8921_S4_1 = 38,
+ MSM_RPM_8960_STATUS_ID_PM8921_S5_0 = 39,
+ MSM_RPM_8960_STATUS_ID_PM8921_S5_1 = 40,
+ MSM_RPM_8960_STATUS_ID_PM8921_S6_0 = 41,
+ MSM_RPM_8960_STATUS_ID_PM8921_S6_1 = 42,
+ MSM_RPM_8960_STATUS_ID_PM8921_S7_0 = 43,
+ MSM_RPM_8960_STATUS_ID_PM8921_S7_1 = 44,
+ MSM_RPM_8960_STATUS_ID_PM8921_S8_0 = 45,
+ MSM_RPM_8960_STATUS_ID_PM8921_S8_1 = 46,
+ MSM_RPM_8960_STATUS_ID_PM8921_L1_0 = 47,
+ MSM_RPM_8960_STATUS_ID_PM8921_L1_1 = 48,
+ MSM_RPM_8960_STATUS_ID_PM8921_L2_0 = 49,
+ MSM_RPM_8960_STATUS_ID_PM8921_L2_1 = 50,
+ MSM_RPM_8960_STATUS_ID_PM8921_L3_0 = 51,
+ MSM_RPM_8960_STATUS_ID_PM8921_L3_1 = 52,
+ MSM_RPM_8960_STATUS_ID_PM8921_L4_0 = 53,
+ MSM_RPM_8960_STATUS_ID_PM8921_L4_1 = 54,
+ MSM_RPM_8960_STATUS_ID_PM8921_L5_0 = 55,
+ MSM_RPM_8960_STATUS_ID_PM8921_L5_1 = 56,
+ MSM_RPM_8960_STATUS_ID_PM8921_L6_0 = 57,
+ MSM_RPM_8960_STATUS_ID_PM8921_L6_1 = 58,
+ MSM_RPM_8960_STATUS_ID_PM8921_L7_0 = 59,
+ MSM_RPM_8960_STATUS_ID_PM8921_L7_1 = 60,
+ MSM_RPM_8960_STATUS_ID_PM8921_L8_0 = 61,
+ MSM_RPM_8960_STATUS_ID_PM8921_L8_1 = 62,
+ MSM_RPM_8960_STATUS_ID_PM8921_L9_0 = 63,
+ MSM_RPM_8960_STATUS_ID_PM8921_L9_1 = 64,
+ MSM_RPM_8960_STATUS_ID_PM8921_L10_0 = 65,
+ MSM_RPM_8960_STATUS_ID_PM8921_L10_1 = 66,
+ MSM_RPM_8960_STATUS_ID_PM8921_L11_0 = 67,
+ MSM_RPM_8960_STATUS_ID_PM8921_L11_1 = 68,
+ MSM_RPM_8960_STATUS_ID_PM8921_L12_0 = 69,
+ MSM_RPM_8960_STATUS_ID_PM8921_L12_1 = 70,
+ MSM_RPM_8960_STATUS_ID_PM8921_L13_0 = 71,
+ MSM_RPM_8960_STATUS_ID_PM8921_L13_1 = 72,
+ MSM_RPM_8960_STATUS_ID_PM8921_L14_0 = 73,
+ MSM_RPM_8960_STATUS_ID_PM8921_L14_1 = 74,
+ MSM_RPM_8960_STATUS_ID_PM8921_L15_0 = 75,
+ MSM_RPM_8960_STATUS_ID_PM8921_L15_1 = 76,
+ MSM_RPM_8960_STATUS_ID_PM8921_L16_0 = 77,
+ MSM_RPM_8960_STATUS_ID_PM8921_L16_1 = 78,
+ MSM_RPM_8960_STATUS_ID_PM8921_L17_0 = 79,
+ MSM_RPM_8960_STATUS_ID_PM8921_L17_1 = 80,
+ MSM_RPM_8960_STATUS_ID_PM8921_L18_0 = 81,
+ MSM_RPM_8960_STATUS_ID_PM8921_L18_1 = 82,
+ MSM_RPM_8960_STATUS_ID_PM8921_L19_0 = 83,
+ MSM_RPM_8960_STATUS_ID_PM8921_L19_1 = 84,
+ MSM_RPM_8960_STATUS_ID_PM8921_L20_0 = 85,
+ MSM_RPM_8960_STATUS_ID_PM8921_L20_1 = 86,
+ MSM_RPM_8960_STATUS_ID_PM8921_L21_0 = 87,
+ MSM_RPM_8960_STATUS_ID_PM8921_L21_1 = 88,
+ MSM_RPM_8960_STATUS_ID_PM8921_L22_0 = 89,
+ MSM_RPM_8960_STATUS_ID_PM8921_L22_1 = 90,
+ MSM_RPM_8960_STATUS_ID_PM8921_L23_0 = 91,
+ MSM_RPM_8960_STATUS_ID_PM8921_L23_1 = 92,
+ MSM_RPM_8960_STATUS_ID_PM8921_L24_0 = 93,
+ MSM_RPM_8960_STATUS_ID_PM8921_L24_1 = 94,
+ MSM_RPM_8960_STATUS_ID_PM8921_L25_0 = 95,
+ MSM_RPM_8960_STATUS_ID_PM8921_L25_1 = 96,
+ MSM_RPM_8960_STATUS_ID_PM8921_L26_0 = 97,
+ MSM_RPM_8960_STATUS_ID_PM8921_L26_1 = 98,
+ MSM_RPM_8960_STATUS_ID_PM8921_L27_0 = 99,
+ MSM_RPM_8960_STATUS_ID_PM8921_L27_1 = 100,
+ MSM_RPM_8960_STATUS_ID_PM8921_L28_0 = 101,
+ MSM_RPM_8960_STATUS_ID_PM8921_L28_1 = 102,
+ MSM_RPM_8960_STATUS_ID_PM8921_L29_0 = 103,
+ MSM_RPM_8960_STATUS_ID_PM8921_L29_1 = 104,
+ MSM_RPM_8960_STATUS_ID_PM8921_CLK1_0 = 105,
+ MSM_RPM_8960_STATUS_ID_PM8921_CLK1_1 = 106,
+ MSM_RPM_8960_STATUS_ID_PM8921_CLK2_0 = 107,
+ MSM_RPM_8960_STATUS_ID_PM8921_CLK2_1 = 108,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS1 = 109,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS2 = 110,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS3 = 111,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS4 = 112,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS5 = 113,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS6 = 114,
+ MSM_RPM_8960_STATUS_ID_PM8921_LVS7 = 115,
+ MSM_RPM_8960_STATUS_ID_NCP_0 = 116,
+ MSM_RPM_8960_STATUS_ID_NCP_1 = 117,
+ MSM_RPM_8960_STATUS_ID_CXO_BUFFERS = 118,
+ MSM_RPM_8960_STATUS_ID_USB_OTG_SWITCH = 119,
+ MSM_RPM_8960_STATUS_ID_HDMI_SWITCH = 120,
+ MSM_RPM_8960_STATUS_ID_DDR_DMM_0 = 121,
+ MSM_RPM_8960_STATUS_ID_DDR_DMM_1 = 122,
+ MSM_RPM_8960_STATUS_ID_EBI1_CH0_RANGE = 123,
+ MSM_RPM_8960_STATUS_ID_EBI1_CH1_RANGE = 124,
- MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_EBI1_CH1_RANGE,
+ MSM_RPM_8960_STATUS_ID_LAST = MSM_RPM_8960_STATUS_ID_EBI1_CH1_RANGE,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8960_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-9615.h b/arch/arm/mach-msm/include/mach/rpm-9615.h
index 68fd6ce..6ae7bae 100644
--- a/arch/arm/mach-msm/include/mach/rpm-9615.h
+++ b/arch/arm/mach-msm/include/mach/rpm-9615.h
@@ -13,264 +13,226 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_9615_H
#define __ARCH_ARM_MACH_MSM_RPM_9615_H
-#define RPM_MAJOR_VER 3
-#define RPM_MINOR_VER 0
-#define RPM_BUILD_VER 0
-
/* RPM control message RAM enums */
enum {
- MSM_RPM_CTRL_VERSION_MAJOR,
- MSM_RPM_CTRL_VERSION_MINOR,
- MSM_RPM_CTRL_VERSION_BUILD,
+ MSM_RPM_9615_CTRL_VERSION_MAJOR,
+ MSM_RPM_9615_CTRL_VERSION_MINOR,
+ MSM_RPM_9615_CTRL_VERSION_BUILD,
- MSM_RPM_CTRL_REQ_CTX_0,
- MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
- MSM_RPM_CTRL_REQ_SEL_0,
- MSM_RPM_CTRL_REQ_SEL_3 = MSM_RPM_CTRL_REQ_SEL_0 + 3,
- MSM_RPM_CTRL_ACK_CTX_0,
- MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
- MSM_RPM_CTRL_ACK_SEL_0,
- MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
+ MSM_RPM_9615_CTRL_REQ_CTX_0,
+ MSM_RPM_9615_CTRL_REQ_CTX_7 = MSM_RPM_9615_CTRL_REQ_CTX_0 + 7,
+ MSM_RPM_9615_CTRL_REQ_SEL_0,
+ MSM_RPM_9615_CTRL_REQ_SEL_3 = MSM_RPM_9615_CTRL_REQ_SEL_0 + 3,
+ MSM_RPM_9615_CTRL_ACK_CTX_0,
+ MSM_RPM_9615_CTRL_ACK_CTX_7 = MSM_RPM_9615_CTRL_ACK_CTX_0 + 7,
+ MSM_RPM_9615_CTRL_ACK_SEL_0,
+ MSM_RPM_9615_CTRL_ACK_SEL_7 = MSM_RPM_9615_CTRL_ACK_SEL_0 + 7,
};
-
-/* RPM resource select enums defined for RPM core
- NOT IN SEQUENTIAL ORDER */
enum {
- MSM_RPM_SEL_NOTIFICATION = 0,
- MSM_RPM_SEL_INVALIDATE = 1,
- MSM_RPM_SEL_TRIGGER_TIMED = 2,
- MSM_RPM_SEL_RPM_CTL = 3,
+ MSM_RPM_9615_SEL_NOTIFICATION = 0,
+ MSM_RPM_9615_SEL_INVALIDATE = 1,
+ MSM_RPM_9615_SEL_TRIGGER_TIMED = 2,
+ MSM_RPM_9615_SEL_RPM_CTL = 3,
- MSM_RPM_SEL_CXO_CLK = 5,
- MSM_RPM_SEL_SYSTEM_FABRIC_CLK = 9,
- MSM_RPM_SEL_DAYTONA_FABRIC_CLK = 11,
- MSM_RPM_SEL_SFPB_CLK = 12,
- MSM_RPM_SEL_CFPB_CLK = 13,
- MSM_RPM_SEL_EBI1_CLK = 16,
+ MSM_RPM_9615_SEL_CXO_CLK = 5,
+ MSM_RPM_9615_SEL_SYSTEM_FABRIC_CLK = 9,
+ MSM_RPM_9615_SEL_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_9615_SEL_SFPB_CLK = 12,
+ MSM_RPM_9615_SEL_CFPB_CLK = 13,
+ MSM_RPM_9615_SEL_EBI1_CLK = 16,
- MSM_RPM_SEL_SYS_FABRIC_CFG_HALT = 22,
- MSM_RPM_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
- MSM_RPM_SEL_SYS_FABRIC_CFG_IOCTL = 24,
- MSM_RPM_SEL_SYSTEM_FABRIC_ARB = 25,
+ MSM_RPM_9615_SEL_SYS_FABRIC_CFG_HALT = 22,
+ MSM_RPM_9615_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
+ MSM_RPM_9615_SEL_SYS_FABRIC_CFG_IOCTL = 24,
+ MSM_RPM_9615_SEL_SYSTEM_FABRIC_ARB = 25,
- MSM_RPM_SEL_PM8018_S1 = 30,
- MSM_RPM_SEL_PM8018_S2 = 31,
- MSM_RPM_SEL_PM8018_S3 = 32,
- MSM_RPM_SEL_PM8018_S4 = 33,
- MSM_RPM_SEL_PM8018_S5 = 34,
- MSM_RPM_SEL_PM8018_L1 = 35,
- MSM_RPM_SEL_PM8018_L2 = 36,
- MSM_RPM_SEL_PM8018_L3 = 37,
- MSM_RPM_SEL_PM8018_L4 = 38,
- MSM_RPM_SEL_PM8018_L5 = 39,
- MSM_RPM_SEL_PM8018_L6 = 40,
- MSM_RPM_SEL_PM8018_L7 = 41,
- MSM_RPM_SEL_PM8018_L8 = 42,
- MSM_RPM_SEL_PM8018_L9 = 43,
- MSM_RPM_SEL_PM8018_L10 = 44,
- MSM_RPM_SEL_PM8018_L11 = 45,
- MSM_RPM_SEL_PM8018_L12 = 46,
- MSM_RPM_SEL_PM8018_L13 = 47,
- MSM_RPM_SEL_PM8018_L14 = 48,
- MSM_RPM_SEL_PM8018_LVS1 = 49,
+ MSM_RPM_9615_SEL_PM8018_S1 = 30,
+ MSM_RPM_9615_SEL_PM8018_S2 = 31,
+ MSM_RPM_9615_SEL_PM8018_S3 = 32,
+ MSM_RPM_9615_SEL_PM8018_S4 = 33,
+ MSM_RPM_9615_SEL_PM8018_S5 = 34,
+ MSM_RPM_9615_SEL_PM8018_L1 = 35,
+ MSM_RPM_9615_SEL_PM8018_L2 = 36,
+ MSM_RPM_9615_SEL_PM8018_L3 = 37,
+ MSM_RPM_9615_SEL_PM8018_L4 = 38,
+ MSM_RPM_9615_SEL_PM8018_L5 = 39,
+ MSM_RPM_9615_SEL_PM8018_L6 = 40,
+ MSM_RPM_9615_SEL_PM8018_L7 = 41,
+ MSM_RPM_9615_SEL_PM8018_L8 = 42,
+ MSM_RPM_9615_SEL_PM8018_L9 = 43,
+ MSM_RPM_9615_SEL_PM8018_L10 = 44,
+ MSM_RPM_9615_SEL_PM8018_L11 = 45,
+ MSM_RPM_9615_SEL_PM8018_L12 = 46,
+ MSM_RPM_9615_SEL_PM8018_L13 = 47,
+ MSM_RPM_9615_SEL_PM8018_L14 = 48,
+ MSM_RPM_9615_SEL_PM8018_LVS1 = 49,
- MSM_RPM_SEL_NCP = 80,
- MSM_RPM_SEL_CXO_BUFFERS = 81,
- MSM_RPM_SEL_USB_OTG_SWITCH = 82,
- MSM_RPM_SEL_HDMI_SWITCH = 83,
+ MSM_RPM_9615_SEL_NCP = 80,
+ MSM_RPM_9615_SEL_CXO_BUFFERS = 81,
+ MSM_RPM_9615_SEL_USB_OTG_SWITCH = 82,
+ MSM_RPM_9615_SEL_HDMI_SWITCH = 83,
- MSM_RPM_SEL_LAST = MSM_RPM_SEL_HDMI_SWITCH,
+ MSM_RPM_9615_SEL_LAST = MSM_RPM_9615_SEL_HDMI_SWITCH,
};
/* RPM resource (4 byte) word ID enum */
enum {
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_3 =
- MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 3,
+ MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_3 =
+ MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_0 + 3,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0 = 4,
- MSM_RPM_ID_NOTIFICATION_REGISTERED_3 =
- MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 3,
+ MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_0 = 4,
+ MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_3 =
+ MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_0 + 3,
- MSM_RPM_ID_INVALIDATE_0 = 8,
- MSM_RPM_ID_INVALIDATE_7 =
- MSM_RPM_ID_INVALIDATE_0 + 7,
+ MSM_RPM_9615_ID_INVALIDATE_0 = 8,
+ MSM_RPM_9615_ID_INVALIDATE_7 =
+ MSM_RPM_9615_ID_INVALIDATE_0 + 7,
- MSM_RPM_ID_TRIGGER_TIMED_TO = 16,
- MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
+ MSM_RPM_9615_ID_TRIGGER_TIMED_TO = 16,
+ MSM_RPM_9615_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
- MSM_RPM_ID_RPM_CTL = 18,
+ MSM_RPM_9615_ID_RPM_CTL = 18,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
- MSM_RPM_ID_RESERVED_0 = 19,
- MSM_RPM_ID_RESERVED_5 =
- MSM_RPM_ID_RESERVED_0 + 5,
+ MSM_RPM_9615_ID_RESERVED_0 = 19,
+ MSM_RPM_9615_ID_RESERVED_5 =
+ MSM_RPM_9615_ID_RESERVED_0 + 5,
- MSM_RPM_ID_CXO_CLK = 25,
- MSM_RPM_ID_SYSTEM_FABRIC_CLK = 26,
- MSM_RPM_ID_DAYTONA_FABRIC_CLK = 27,
- MSM_RPM_ID_SFPB_CLK = 28,
- MSM_RPM_ID_CFPB_CLK = 29,
- MSM_RPM_ID_EBI1_CLK = 30,
+ MSM_RPM_9615_ID_CXO_CLK = 25,
+ MSM_RPM_9615_ID_SYSTEM_FABRIC_CLK = 26,
+ MSM_RPM_9615_ID_DAYTONA_FABRIC_CLK = 27,
+ MSM_RPM_9615_ID_SFPB_CLK = 28,
+ MSM_RPM_9615_ID_CFPB_CLK = 29,
+ MSM_RPM_9615_ID_EBI1_CLK = 30,
- MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0 = 31,
- MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1 = 32,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0 = 33,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1 = 34,
- MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2 = 35,
- MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL = 36,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 = 37,
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_26 =
- MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 26,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_HALT_0 = 31,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_HALT_1 = 32,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_0 = 33,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_1 = 34,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_2 = 35,
+ MSM_RPM_9615_ID_SYS_FABRIC_CFG_IOCTL = 36,
+ MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_0 = 37,
+ MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_26 =
+ MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_0 + 26,
- MSM_RPM_ID_PM8018_S1_0 = 64,
- MSM_RPM_ID_PM8018_S1_1 = 65,
- MSM_RPM_ID_PM8018_S2_0 = 66,
- MSM_RPM_ID_PM8018_S2_1 = 67,
- MSM_RPM_ID_PM8018_S3_0 = 68,
- MSM_RPM_ID_PM8018_S3_1 = 69,
- MSM_RPM_ID_PM8018_S4_0 = 70,
- MSM_RPM_ID_PM8018_S4_1 = 71,
- MSM_RPM_ID_PM8018_S5_0 = 72,
- MSM_RPM_ID_PM8018_S5_1 = 73,
- MSM_RPM_ID_PM8018_L1_0 = 74,
- MSM_RPM_ID_PM8018_L1_1 = 75,
- MSM_RPM_ID_PM8018_L2_0 = 76,
- MSM_RPM_ID_PM8018_L2_1 = 77,
- MSM_RPM_ID_PM8018_L3_0 = 78,
- MSM_RPM_ID_PM8018_L3_1 = 79,
- MSM_RPM_ID_PM8018_L4_0 = 80,
- MSM_RPM_ID_PM8018_L4_1 = 81,
- MSM_RPM_ID_PM8018_L5_0 = 82,
- MSM_RPM_ID_PM8018_L5_1 = 83,
- MSM_RPM_ID_PM8018_L6_0 = 84,
- MSM_RPM_ID_PM8018_L6_1 = 85,
- MSM_RPM_ID_PM8018_L7_0 = 86,
- MSM_RPM_ID_PM8018_L7_1 = 87,
- MSM_RPM_ID_PM8018_L8_0 = 88,
- MSM_RPM_ID_PM8018_L8_1 = 89,
- MSM_RPM_ID_PM8018_L9_0 = 90,
- MSM_RPM_ID_PM8018_L9_1 = 91,
- MSM_RPM_ID_PM8018_L10_0 = 92,
- MSM_RPM_ID_PM8018_L10_1 = 93,
- MSM_RPM_ID_PM8018_L11_0 = 94,
- MSM_RPM_ID_PM8018_L11_1 = 95,
- MSM_RPM_ID_PM8018_L12_0 = 96,
- MSM_RPM_ID_PM8018_L12_1 = 97,
- MSM_RPM_ID_PM8018_L13_0 = 98,
- MSM_RPM_ID_PM8018_L13_1 = 99,
- MSM_RPM_ID_PM8018_L14_0 = 100,
- MSM_RPM_ID_PM8018_L14_1 = 101,
- MSM_RPM_ID_PM8018_LVS1 = 102,
+ MSM_RPM_9615_ID_PM8018_S1_0 = 64,
+ MSM_RPM_9615_ID_PM8018_S1_1 = 65,
+ MSM_RPM_9615_ID_PM8018_S2_0 = 66,
+ MSM_RPM_9615_ID_PM8018_S2_1 = 67,
+ MSM_RPM_9615_ID_PM8018_S3_0 = 68,
+ MSM_RPM_9615_ID_PM8018_S3_1 = 69,
+ MSM_RPM_9615_ID_PM8018_S4_0 = 70,
+ MSM_RPM_9615_ID_PM8018_S4_1 = 71,
+ MSM_RPM_9615_ID_PM8018_S5_0 = 72,
+ MSM_RPM_9615_ID_PM8018_S5_1 = 73,
+ MSM_RPM_9615_ID_PM8018_L1_0 = 74,
+ MSM_RPM_9615_ID_PM8018_L1_1 = 75,
+ MSM_RPM_9615_ID_PM8018_L2_0 = 76,
+ MSM_RPM_9615_ID_PM8018_L2_1 = 77,
+ MSM_RPM_9615_ID_PM8018_L3_0 = 78,
+ MSM_RPM_9615_ID_PM8018_L3_1 = 79,
+ MSM_RPM_9615_ID_PM8018_L4_0 = 80,
+ MSM_RPM_9615_ID_PM8018_L4_1 = 81,
+ MSM_RPM_9615_ID_PM8018_L5_0 = 82,
+ MSM_RPM_9615_ID_PM8018_L5_1 = 83,
+ MSM_RPM_9615_ID_PM8018_L6_0 = 84,
+ MSM_RPM_9615_ID_PM8018_L6_1 = 85,
+ MSM_RPM_9615_ID_PM8018_L7_0 = 86,
+ MSM_RPM_9615_ID_PM8018_L7_1 = 87,
+ MSM_RPM_9615_ID_PM8018_L8_0 = 88,
+ MSM_RPM_9615_ID_PM8018_L8_1 = 89,
+ MSM_RPM_9615_ID_PM8018_L9_0 = 90,
+ MSM_RPM_9615_ID_PM8018_L9_1 = 91,
+ MSM_RPM_9615_ID_PM8018_L10_0 = 92,
+ MSM_RPM_9615_ID_PM8018_L10_1 = 93,
+ MSM_RPM_9615_ID_PM8018_L11_0 = 94,
+ MSM_RPM_9615_ID_PM8018_L11_1 = 95,
+ MSM_RPM_9615_ID_PM8018_L12_0 = 96,
+ MSM_RPM_9615_ID_PM8018_L12_1 = 97,
+ MSM_RPM_9615_ID_PM8018_L13_0 = 98,
+ MSM_RPM_9615_ID_PM8018_L13_1 = 99,
+ MSM_RPM_9615_ID_PM8018_L14_0 = 100,
+ MSM_RPM_9615_ID_PM8018_L14_1 = 101,
+ MSM_RPM_9615_ID_PM8018_LVS1 = 102,
- MSM_RPM_ID_NCP_0 = 103,
- MSM_RPM_ID_NCP_1 = 104,
- MSM_RPM_ID_CXO_BUFFERS = 105,
- MSM_RPM_ID_USB_OTG_SWITCH = 106,
- MSM_RPM_ID_HDMI_SWITCH = 107,
+ MSM_RPM_9615_ID_NCP_0 = 103,
+ MSM_RPM_9615_ID_NCP_1 = 104,
+ MSM_RPM_9615_ID_CXO_BUFFERS = 105,
+ MSM_RPM_9615_ID_USB_OTG_SWITCH = 106,
+ MSM_RPM_9615_ID_HDMI_SWITCH = 107,
- MSM_RPM_ID_LAST = MSM_RPM_ID_HDMI_SWITCH,
-};
-
-/* RPM resources RPM_ID aliases */
-enum {
- MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_RPM_CTL,
- /* XO clock for this target is CXO */
- MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_CXO_CLK,
- MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_PM8018_S1_0,
- MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_PM8018_S1_1,
- MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_PM8018_L9_0,
- MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_PM8018_L9_1,
-
- /* MSM9615 L2 cache power control not via RPM
- * MSM_RPM_ID_LAST + 1 indicates invalid */
- MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_LAST + 1
-};
-
-/* VDD values are in microvolts */
-#define MSM_RPMRS_VDD_MASK 0x7fffff
-enum {
- MSM_RPMRS_VDD_MEM_RET_LOW = 750000,
- MSM_RPMRS_VDD_MEM_RET_HIGH = 750000,
- MSM_RPMRS_VDD_MEM_ACTIVE = 1050000,
- MSM_RPMRS_VDD_MEM_MAX = 1150000,
-};
-
-enum {
- MSM_RPMRS_VDD_DIG_RET_LOW = 500000,
- MSM_RPMRS_VDD_DIG_RET_HIGH = 750000,
- MSM_RPMRS_VDD_DIG_ACTIVE = 950000,
- MSM_RPMRS_VDD_DIG_MAX = 1150000,
+ MSM_RPM_9615_ID_LAST = MSM_RPM_9615_ID_HDMI_SWITCH,
};
/* RPM status ID enum */
enum {
- MSM_RPM_STATUS_ID_VERSION_MAJOR = 0,
- MSM_RPM_STATUS_ID_VERSION_MINOR = 1,
- MSM_RPM_STATUS_ID_VERSION_BUILD = 2,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
- MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
- MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
- MSM_RPM_STATUS_ID_SEQUENCE = 7,
- MSM_RPM_STATUS_ID_RPM_CTL = 8,
- MSM_RPM_STATUS_ID_CXO_CLK = 9,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK = 10,
- MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK = 11,
- MSM_RPM_STATUS_ID_SFPB_CLK = 12,
- MSM_RPM_STATUS_ID_CFPB_CLK = 13,
- MSM_RPM_STATUS_ID_EBI1_CLK = 14,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT = 15,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 16,
- MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 17,
- MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB = 18,
- MSM_RPM_STATUS_ID_PM8018_S1_0 = 19,
- MSM_RPM_STATUS_ID_PM8018_S1_1 = 20,
- MSM_RPM_STATUS_ID_PM8018_S2_0 = 21,
- MSM_RPM_STATUS_ID_PM8018_S2_1 = 22,
- MSM_RPM_STATUS_ID_PM8018_S3_0 = 23,
- MSM_RPM_STATUS_ID_PM8018_S3_1 = 24,
- MSM_RPM_STATUS_ID_PM8018_S4_0 = 25,
- MSM_RPM_STATUS_ID_PM8018_S4_1 = 26,
- MSM_RPM_STATUS_ID_PM8018_S5_0 = 27,
- MSM_RPM_STATUS_ID_PM8018_S5_1 = 28,
- MSM_RPM_STATUS_ID_PM8018_L1_0 = 29,
- MSM_RPM_STATUS_ID_PM8018_L1_1 = 30,
- MSM_RPM_STATUS_ID_PM8018_L2_0 = 31,
- MSM_RPM_STATUS_ID_PM8018_L2_1 = 32,
- MSM_RPM_STATUS_ID_PM8018_L3_0 = 33,
- MSM_RPM_STATUS_ID_PM8018_L3_1 = 34,
- MSM_RPM_STATUS_ID_PM8018_L4_0 = 35,
- MSM_RPM_STATUS_ID_PM8018_L4_1 = 36,
- MSM_RPM_STATUS_ID_PM8018_L5_0 = 37,
- MSM_RPM_STATUS_ID_PM8018_L5_1 = 38,
- MSM_RPM_STATUS_ID_PM8018_L6_0 = 39,
- MSM_RPM_STATUS_ID_PM8018_L6_1 = 40,
- MSM_RPM_STATUS_ID_PM8018_L7_0 = 41,
- MSM_RPM_STATUS_ID_PM8018_L7_1 = 42,
- MSM_RPM_STATUS_ID_PM8018_L8_0 = 43,
- MSM_RPM_STATUS_ID_PM8018_L8_1 = 44,
- MSM_RPM_STATUS_ID_PM8018_L9_0 = 45,
- MSM_RPM_STATUS_ID_PM8018_L9_1 = 46,
- MSM_RPM_STATUS_ID_PM8018_L10_0 = 47,
- MSM_RPM_STATUS_ID_PM8018_L10_1 = 48,
- MSM_RPM_STATUS_ID_PM8018_L11_0 = 49,
- MSM_RPM_STATUS_ID_PM8018_L11_1 = 50,
- MSM_RPM_STATUS_ID_PM8018_L12_0 = 51,
- MSM_RPM_STATUS_ID_PM8018_L12_1 = 52,
- MSM_RPM_STATUS_ID_PM8018_L13_0 = 53,
- MSM_RPM_STATUS_ID_PM8018_L13_1 = 54,
- MSM_RPM_STATUS_ID_PM8018_L14_0 = 55,
- MSM_RPM_STATUS_ID_PM8018_L14_1 = 56,
- MSM_RPM_STATUS_ID_PM8018_LVS1 = 57,
- MSM_RPM_STATUS_ID_NCP_0 = 58,
- MSM_RPM_STATUS_ID_NCP_1 = 59,
- MSM_RPM_STATUS_ID_CXO_BUFFERS = 60,
- MSM_RPM_STATUS_ID_USB_OTG_SWITCH = 61,
- MSM_RPM_STATUS_ID_HDMI_SWITCH = 62,
+ MSM_RPM_9615_STATUS_ID_VERSION_MAJOR = 0,
+ MSM_RPM_9615_STATUS_ID_VERSION_MINOR = 1,
+ MSM_RPM_9615_STATUS_ID_VERSION_BUILD = 2,
+ MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
+ MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
+ MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
+ MSM_RPM_9615_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
+ MSM_RPM_9615_STATUS_ID_SEQUENCE = 7,
+ MSM_RPM_9615_STATUS_ID_RPM_CTL = 8,
+ MSM_RPM_9615_STATUS_ID_CXO_CLK = 9,
+ MSM_RPM_9615_STATUS_ID_SYSTEM_FABRIC_CLK = 10,
+ MSM_RPM_9615_STATUS_ID_DAYTONA_FABRIC_CLK = 11,
+ MSM_RPM_9615_STATUS_ID_SFPB_CLK = 12,
+ MSM_RPM_9615_STATUS_ID_CFPB_CLK = 13,
+ MSM_RPM_9615_STATUS_ID_EBI1_CLK = 14,
+ MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_HALT = 15,
+ MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 16,
+ MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 17,
+ MSM_RPM_9615_STATUS_ID_SYSTEM_FABRIC_ARB = 18,
+ MSM_RPM_9615_STATUS_ID_PM8018_S1_0 = 19,
+ MSM_RPM_9615_STATUS_ID_PM8018_S1_1 = 20,
+ MSM_RPM_9615_STATUS_ID_PM8018_S2_0 = 21,
+ MSM_RPM_9615_STATUS_ID_PM8018_S2_1 = 22,
+ MSM_RPM_9615_STATUS_ID_PM8018_S3_0 = 23,
+ MSM_RPM_9615_STATUS_ID_PM8018_S3_1 = 24,
+ MSM_RPM_9615_STATUS_ID_PM8018_S4_0 = 25,
+ MSM_RPM_9615_STATUS_ID_PM8018_S4_1 = 26,
+ MSM_RPM_9615_STATUS_ID_PM8018_S5_0 = 27,
+ MSM_RPM_9615_STATUS_ID_PM8018_S5_1 = 28,
+ MSM_RPM_9615_STATUS_ID_PM8018_L1_0 = 29,
+ MSM_RPM_9615_STATUS_ID_PM8018_L1_1 = 30,
+ MSM_RPM_9615_STATUS_ID_PM8018_L2_0 = 31,
+ MSM_RPM_9615_STATUS_ID_PM8018_L2_1 = 32,
+ MSM_RPM_9615_STATUS_ID_PM8018_L3_0 = 33,
+ MSM_RPM_9615_STATUS_ID_PM8018_L3_1 = 34,
+ MSM_RPM_9615_STATUS_ID_PM8018_L4_0 = 35,
+ MSM_RPM_9615_STATUS_ID_PM8018_L4_1 = 36,
+ MSM_RPM_9615_STATUS_ID_PM8018_L5_0 = 37,
+ MSM_RPM_9615_STATUS_ID_PM8018_L5_1 = 38,
+ MSM_RPM_9615_STATUS_ID_PM8018_L6_0 = 39,
+ MSM_RPM_9615_STATUS_ID_PM8018_L6_1 = 40,
+ MSM_RPM_9615_STATUS_ID_PM8018_L7_0 = 41,
+ MSM_RPM_9615_STATUS_ID_PM8018_L7_1 = 42,
+ MSM_RPM_9615_STATUS_ID_PM8018_L8_0 = 43,
+ MSM_RPM_9615_STATUS_ID_PM8018_L8_1 = 44,
+ MSM_RPM_9615_STATUS_ID_PM8018_L9_0 = 45,
+ MSM_RPM_9615_STATUS_ID_PM8018_L9_1 = 46,
+ MSM_RPM_9615_STATUS_ID_PM8018_L10_0 = 47,
+ MSM_RPM_9615_STATUS_ID_PM8018_L10_1 = 48,
+ MSM_RPM_9615_STATUS_ID_PM8018_L11_0 = 49,
+ MSM_RPM_9615_STATUS_ID_PM8018_L11_1 = 50,
+ MSM_RPM_9615_STATUS_ID_PM8018_L12_0 = 51,
+ MSM_RPM_9615_STATUS_ID_PM8018_L12_1 = 52,
+ MSM_RPM_9615_STATUS_ID_PM8018_L13_0 = 53,
+ MSM_RPM_9615_STATUS_ID_PM8018_L13_1 = 54,
+ MSM_RPM_9615_STATUS_ID_PM8018_L14_0 = 55,
+ MSM_RPM_9615_STATUS_ID_PM8018_L14_1 = 56,
+ MSM_RPM_9615_STATUS_ID_PM8018_LVS1 = 57,
+ MSM_RPM_9615_STATUS_ID_NCP_0 = 58,
+ MSM_RPM_9615_STATUS_ID_NCP_1 = 59,
+ MSM_RPM_9615_STATUS_ID_CXO_BUFFERS = 60,
+ MSM_RPM_9615_STATUS_ID_USB_OTG_SWITCH = 61,
+ MSM_RPM_9615_STATUS_ID_HDMI_SWITCH = 62,
- MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_HDMI_SWITCH,
+ MSM_RPM_9615_STATUS_ID_LAST = MSM_RPM_9615_STATUS_ID_HDMI_SWITCH,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_9615_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h b/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h
new file mode 100644
index 0000000..9e654ed
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8930_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8930_H
+
+/* Pin control input signals. */
+#define RPM_VREG_PIN_CTRL_PM8038_D1 0x01
+#define RPM_VREG_PIN_CTRL_PM8038_A0 0x02
+#define RPM_VREG_PIN_CTRL_PM8038_A1 0x04
+#define RPM_VREG_PIN_CTRL_PM8038_A2 0x08
+
+/**
+ * enum rpm_vreg_pin_fn_8930 - RPM regulator pin function choices
+ * %RPM_VREG_PIN_FN_8930_DONT_CARE: do not care about pin control state of
+ * the regulator; allow another master
+ * processor to specify pin control
+ * %RPM_VREG_PIN_FN_8930_ENABLE: pin control switches between disable and
+ * enable
+ * %RPM_VREG_PIN_FN_8930_MODE: pin control switches between LPM and HPM
+ * %RPM_VREG_PIN_FN_8930_SLEEP_B: regulator is forced into LPM when
+ * sleep_b signal is asserted
+ * %RPM_VREG_PIN_FN_8930_NONE: do not use pin control for the regulator
+ * and do not allow another master to
+ * request pin control
+ *
+ * The pin function specified in platform data corresponds to the active state
+ * pin function value. Pin function will be NONE until a consumer requests
+ * pin control to be enabled.
+ */
+enum rpm_vreg_pin_fn_8930 {
+ RPM_VREG_PIN_FN_8930_DONT_CARE,
+ RPM_VREG_PIN_FN_8930_ENABLE,
+ RPM_VREG_PIN_FN_8930_MODE,
+ RPM_VREG_PIN_FN_8930_SLEEP_B,
+ RPM_VREG_PIN_FN_8930_NONE,
+};
+
+/**
+ * enum rpm_vreg_force_mode_8930 - RPM regulator force mode choices
+ * %RPM_VREG_FORCE_MODE_8930_PIN_CTRL: allow pin control usage
+ * %RPM_VREG_FORCE_MODE_8930_NONE: do not force any mode
+ * %RPM_VREG_FORCE_MODE_8930_LPM: force into low power mode
+ * %RPM_VREG_FORCE_MODE_8930_AUTO: allow regulator to automatically select
+ * its own mode based on realtime current
+ * draw (only available for SMPS
+ * regulators)
+ * %RPM_VREG_FORCE_MODE_8930_HPM: force into high power mode
+ * %RPM_VREG_FORCE_MODE_8930_BYPASS: set regulator to use bypass mode, i.e.
+ * to act as a switch and not regulate
+ * (only available for LDO regulators)
+ *
+ * Force mode is used to override aggregation with other masters and to set
+ * special operating modes.
+ */
+enum rpm_vreg_force_mode_8930 {
+ RPM_VREG_FORCE_MODE_8930_PIN_CTRL = 0,
+ RPM_VREG_FORCE_MODE_8930_NONE = 0,
+ RPM_VREG_FORCE_MODE_8930_LPM,
+ RPM_VREG_FORCE_MODE_8930_AUTO, /* SMPS only */
+ RPM_VREG_FORCE_MODE_8930_HPM,
+ RPM_VREG_FORCE_MODE_8930_BYPASS, /* LDO only */
+};
+
+/**
+ * enum rpm_vreg_power_mode_8930 - power mode for SMPS regulators
+ * %RPM_VREG_POWER_MODE_8930_HYSTERETIC: Use hysteretic mode for HPM and when
+ * usage goes high in AUTO
+ * %RPM_VREG_POWER_MODE_8930_PWM: Use PWM mode for HPM and when usage
+ * goes high in AUTO
+ */
+enum rpm_vreg_power_mode_8930 {
+ RPM_VREG_POWER_MODE_8930_HYSTERETIC,
+ RPM_VREG_POWER_MODE_8930_PWM,
+};
+
+/**
+ * enum rpm_vreg_id - RPM regulator ID numbers (both real and pin control)
+ */
+enum rpm_vreg_id_8930 {
+ RPM_VREG_ID_PM8038_L1,
+ RPM_VREG_ID_PM8038_L2,
+ RPM_VREG_ID_PM8038_L3,
+ RPM_VREG_ID_PM8038_L4,
+ RPM_VREG_ID_PM8038_L5,
+ RPM_VREG_ID_PM8038_L6,
+ RPM_VREG_ID_PM8038_L7,
+ RPM_VREG_ID_PM8038_L8,
+ RPM_VREG_ID_PM8038_L9,
+ RPM_VREG_ID_PM8038_L10,
+ RPM_VREG_ID_PM8038_L11,
+ RPM_VREG_ID_PM8038_L12,
+ RPM_VREG_ID_PM8038_L14,
+ RPM_VREG_ID_PM8038_L15,
+ RPM_VREG_ID_PM8038_L16,
+ RPM_VREG_ID_PM8038_L17,
+ RPM_VREG_ID_PM8038_L18,
+ RPM_VREG_ID_PM8038_L19,
+ RPM_VREG_ID_PM8038_L20,
+ RPM_VREG_ID_PM8038_L21,
+ RPM_VREG_ID_PM8038_L22,
+ RPM_VREG_ID_PM8038_L23,
+ RPM_VREG_ID_PM8038_L24,
+ RPM_VREG_ID_PM8038_L26,
+ RPM_VREG_ID_PM8038_L27,
+ RPM_VREG_ID_PM8038_S1,
+ RPM_VREG_ID_PM8038_S2,
+ RPM_VREG_ID_PM8038_S3,
+ RPM_VREG_ID_PM8038_S4,
+ RPM_VREG_ID_PM8038_S5,
+ RPM_VREG_ID_PM8038_S6,
+ RPM_VREG_ID_PM8038_LVS1,
+ RPM_VREG_ID_PM8038_LVS2,
+ RPM_VREG_ID_PM8038_MAX_REAL = RPM_VREG_ID_PM8038_LVS2,
+
+ /* The following are IDs for regulator devices to enable pin control. */
+ RPM_VREG_ID_PM8038_L2_PC,
+ RPM_VREG_ID_PM8038_L3_PC,
+ RPM_VREG_ID_PM8038_L4_PC,
+ RPM_VREG_ID_PM8038_L5_PC,
+ RPM_VREG_ID_PM8038_L6_PC,
+ RPM_VREG_ID_PM8038_L7_PC,
+ RPM_VREG_ID_PM8038_L8_PC,
+ RPM_VREG_ID_PM8038_L9_PC,
+ RPM_VREG_ID_PM8038_L10_PC,
+ RPM_VREG_ID_PM8038_L11_PC,
+ RPM_VREG_ID_PM8038_L12_PC,
+ RPM_VREG_ID_PM8038_L14_PC,
+ RPM_VREG_ID_PM8038_L15_PC,
+ RPM_VREG_ID_PM8038_L17_PC,
+ RPM_VREG_ID_PM8038_L18_PC,
+ RPM_VREG_ID_PM8038_L21_PC,
+ RPM_VREG_ID_PM8038_L22_PC,
+ RPM_VREG_ID_PM8038_L23_PC,
+ RPM_VREG_ID_PM8038_L26_PC,
+ RPM_VREG_ID_PM8038_S1_PC,
+ RPM_VREG_ID_PM8038_S2_PC,
+ RPM_VREG_ID_PM8038_S3_PC,
+ RPM_VREG_ID_PM8038_S4_PC,
+ RPM_VREG_ID_PM8038_LVS1_PC,
+ RPM_VREG_ID_PM8038_LVS2_PC,
+ RPM_VREG_ID_PM8038_MAX = RPM_VREG_ID_PM8038_LVS2_PC,
+};
+
+/* Minimum high power mode loads in uA. */
+#define RPM_VREG_8930_LDO_50_HPM_MIN_LOAD 5000
+#define RPM_VREG_8930_LDO_150_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_300_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_600_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_1200_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_SMPS_1500_HPM_MIN_LOAD 100000
+#define RPM_VREG_8930_SMPS_2000_HPM_MIN_LOAD 100000
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator.h b/arch/arm/mach-msm/include/mach/rpm-regulator.h
index 1095078..0d113ac 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -21,6 +21,7 @@
#include <mach/rpm-regulator-8960.h>
#include <mach/rpm-regulator-9615.h>
#include <mach/rpm-regulator-copper.h>
+#include <mach/rpm-regulator-8930.h>
/**
* enum rpm_vreg_version - supported RPM regulator versions
@@ -29,7 +30,8 @@
RPM_VREG_VERSION_8660,
RPM_VREG_VERSION_8960,
RPM_VREG_VERSION_9615,
- RPM_VREG_VERSION_MAX = RPM_VREG_VERSION_9615,
+ RPM_VREG_VERSION_8930,
+ RPM_VREG_VERSION_MAX = RPM_VREG_VERSION_8930,
};
#define RPM_VREG_PIN_CTRL_NONE 0x00
diff --git a/arch/arm/mach-msm/include/mach/rpm.h b/arch/arm/mach-msm/include/mach/rpm.h
index dda9954..40a8c9b 100644
--- a/arch/arm/mach-msm/include/mach/rpm.h
+++ b/arch/arm/mach-msm/include/mach/rpm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -18,14 +18,13 @@
#include <linux/list.h>
#include <linux/semaphore.h>
-#if defined(CONFIG_ARCH_MSM8X60)
#include <mach/rpm-8660.h>
-#elif defined(CONFIG_ARCH_MSM9615)
#include <mach/rpm-9615.h>
-#elif defined(CONFIG_ARCH_MSM8960)
#include <mach/rpm-8960.h>
-#endif
+#include <mach/rpm-8930.h>
+#include <mach/rpm-8064.h>
+#define SEL_MASK_SIZE (5)
enum {
MSM_RPM_PAGE_STATUS,
@@ -44,13 +43,794 @@
MSM_RPM_CTX_REJECTED = 31,
};
+/* RPM control message RAM enums */
+enum {
+ MSM_RPM_CTRL_VERSION_MAJOR,
+ MSM_RPM_CTRL_VERSION_MINOR,
+ MSM_RPM_CTRL_VERSION_BUILD,
+
+ MSM_RPM_CTRL_REQ_CTX_0,
+ MSM_RPM_CTRL_REQ_SEL_0,
+ MSM_RPM_CTRL_ACK_CTX_0,
+ MSM_RPM_CTRL_ACK_SEL_0,
+
+ MSM_RPM_CTRL_LAST,
+};
+
+enum {
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_7 =
+ MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 7,
+
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_0,
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_7 =
+ MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 7,
+
+ MSM_RPM_ID_INVALIDATE_0,
+ MSM_RPM_ID_INVALIDATE_7 =
+ MSM_RPM_ID_INVALIDATE_0 + 7,
+
+ MSM_RPM_ID_TRIGGER_TIMED_TO,
+ MSM_RPM_ID_TRIGGER_TIMED_0,
+ MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT,
+
+ MSM_RPM_ID_RPM_CTL,
+
+ /* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
+ MSM_RPM_ID_RESERVED_0,
+ MSM_RPM_ID_RESERVED_5 =
+ MSM_RPM_ID_RESERVED_0 + 5,
+
+ MSM_RPM_ID_CXO_CLK,
+ MSM_RPM_ID_PXO_CLK,
+ MSM_RPM_ID_APPS_FABRIC_CLK,
+ MSM_RPM_ID_SYSTEM_FABRIC_CLK,
+ MSM_RPM_ID_MM_FABRIC_CLK,
+ MSM_RPM_ID_DAYTONA_FABRIC_CLK,
+ MSM_RPM_ID_SFPB_CLK,
+ MSM_RPM_ID_CFPB_CLK,
+ MSM_RPM_ID_MMFPB_CLK,
+ MSM_RPM_ID_EBI1_CLK,
+
+ MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_APPS_FABRIC_HALT_0 =
+ MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_APPS_FABRIC_CFG_HALT_1,
+ MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_0 =
+ MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_1,
+ MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_2,
+ MSM_RPM_ID_APPS_FABRIC_CFG_IOCTL,
+ MSM_RPM_ID_APPS_FABRIC_ARB_0,
+ MSM_RPM_ID_APPS_FABRIC_ARB_11 =
+ MSM_RPM_ID_APPS_FABRIC_ARB_0 + 11,
+
+ MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_SYSTEM_FABRIC_HALT_0 =
+ MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_0 =
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1,
+ MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2,
+ MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL,
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_28 =
+ MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 28,
+
+ MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_MM_FABRIC_HALT_0 =
+ MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
+ MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_1,
+ MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_0 =
+ MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0,
+ MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_1,
+ MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_2,
+ MSM_RPM_ID_MMSS_FABRIC_CFG_IOCTL,
+ MSM_RPM_ID_MM_FABRIC_ARB_0,
+ MSM_RPM_ID_MM_FABRIC_ARB_22 =
+ MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
+
+ MSM_RPM_ID_PM8921_S1_0,
+ MSM_RPM_ID_PM8921_S1_1,
+ MSM_RPM_ID_PM8921_S2_0,
+ MSM_RPM_ID_PM8921_S2_1,
+ MSM_RPM_ID_PM8921_S3_0,
+ MSM_RPM_ID_PM8921_S3_1,
+ MSM_RPM_ID_PM8921_S4_0,
+ MSM_RPM_ID_PM8921_S4_1,
+ MSM_RPM_ID_PM8921_S5_0,
+ MSM_RPM_ID_PM8921_S5_1,
+ MSM_RPM_ID_PM8921_S6_0,
+ MSM_RPM_ID_PM8921_S6_1,
+ MSM_RPM_ID_PM8921_S7_0,
+ MSM_RPM_ID_PM8921_S7_1,
+ MSM_RPM_ID_PM8921_S8_0,
+ MSM_RPM_ID_PM8921_S8_1,
+ MSM_RPM_ID_PM8921_L1_0,
+ MSM_RPM_ID_PM8921_L1_1,
+ MSM_RPM_ID_PM8921_L2_0,
+ MSM_RPM_ID_PM8921_L2_1,
+ MSM_RPM_ID_PM8921_L3_0,
+ MSM_RPM_ID_PM8921_L3_1,
+ MSM_RPM_ID_PM8921_L4_0,
+ MSM_RPM_ID_PM8921_L4_1,
+ MSM_RPM_ID_PM8921_L5_0,
+ MSM_RPM_ID_PM8921_L5_1,
+ MSM_RPM_ID_PM8921_L6_0,
+ MSM_RPM_ID_PM8921_L6_1,
+ MSM_RPM_ID_PM8921_L7_0,
+ MSM_RPM_ID_PM8921_L7_1,
+ MSM_RPM_ID_PM8921_L8_0,
+ MSM_RPM_ID_PM8921_L8_1,
+ MSM_RPM_ID_PM8921_L9_0,
+ MSM_RPM_ID_PM8921_L9_1,
+ MSM_RPM_ID_PM8921_L10_0,
+ MSM_RPM_ID_PM8921_L10_1,
+ MSM_RPM_ID_PM8921_L11_0,
+ MSM_RPM_ID_PM8921_L11_1,
+ MSM_RPM_ID_PM8921_L12_0,
+ MSM_RPM_ID_PM8921_L12_1,
+ MSM_RPM_ID_PM8921_L13_0,
+ MSM_RPM_ID_PM8921_L13_1,
+ MSM_RPM_ID_PM8921_L14_0,
+ MSM_RPM_ID_PM8921_L14_1,
+ MSM_RPM_ID_PM8921_L15_0,
+ MSM_RPM_ID_PM8921_L15_1,
+ MSM_RPM_ID_PM8921_L16_0,
+ MSM_RPM_ID_PM8921_L16_1,
+ MSM_RPM_ID_PM8921_L17_0,
+ MSM_RPM_ID_PM8921_L17_1,
+ MSM_RPM_ID_PM8921_L18_0,
+ MSM_RPM_ID_PM8921_L18_1,
+ MSM_RPM_ID_PM8921_L19_0,
+ MSM_RPM_ID_PM8921_L19_1,
+ MSM_RPM_ID_PM8921_L20_0,
+ MSM_RPM_ID_PM8921_L20_1,
+ MSM_RPM_ID_PM8921_L21_0,
+ MSM_RPM_ID_PM8921_L21_1,
+ MSM_RPM_ID_PM8921_L22_0,
+ MSM_RPM_ID_PM8921_L22_1,
+ MSM_RPM_ID_PM8921_L23_0,
+ MSM_RPM_ID_PM8921_L23_1,
+ MSM_RPM_ID_PM8921_L24_0,
+ MSM_RPM_ID_PM8921_L24_1,
+ MSM_RPM_ID_PM8921_L25_0,
+ MSM_RPM_ID_PM8921_L25_1,
+ MSM_RPM_ID_PM8921_L26_0,
+ MSM_RPM_ID_PM8921_L26_1,
+ MSM_RPM_ID_PM8921_L27_0,
+ MSM_RPM_ID_PM8921_L27_1,
+ MSM_RPM_ID_PM8921_L28_0,
+ MSM_RPM_ID_PM8921_L28_1,
+ MSM_RPM_ID_PM8921_L29_0,
+ MSM_RPM_ID_PM8921_L29_1,
+ MSM_RPM_ID_PM8921_CLK1_0,
+ MSM_RPM_ID_PM8921_CLK1_1,
+ MSM_RPM_ID_PM8921_CLK2_0,
+ MSM_RPM_ID_PM8921_CLK2_1,
+ MSM_RPM_ID_PM8921_LVS1,
+ MSM_RPM_ID_PM8921_LVS2,
+ MSM_RPM_ID_PM8921_LVS3,
+ MSM_RPM_ID_PM8921_LVS4,
+ MSM_RPM_ID_PM8921_LVS5,
+ MSM_RPM_ID_PM8921_LVS6,
+ MSM_RPM_ID_PM8921_LVS7,
+ MSM_RPM_ID_NCP_0,
+ MSM_RPM_ID_NCP_1,
+ MSM_RPM_ID_CXO_BUFFERS,
+ MSM_RPM_ID_USB_OTG_SWITCH,
+ MSM_RPM_ID_HDMI_SWITCH,
+ MSM_RPM_ID_DDR_DMM_0,
+ MSM_RPM_ID_DDR_DMM_1,
+ MSM_RPM_ID_QDSS_CLK,
+
+ /* 8660 specific ids */
+ MSM_RPM_ID_TRIGGER_SET_FROM,
+ MSM_RPM_ID_TRIGGER_SET_TO,
+ MSM_RPM_ID_TRIGGER_SET_TRIGGER,
+
+ MSM_RPM_ID_TRIGGER_CLEAR_FROM,
+ MSM_RPM_ID_TRIGGER_CLEAR_TO,
+ MSM_RPM_ID_TRIGGER_CLEAR_TRIGGER,
+ MSM_RPM_ID_PLL_4,
+ MSM_RPM_ID_SMI_CLK,
+ MSM_RPM_ID_APPS_L2_CACHE_CTL,
+
+ /* pmic 8901 */
+ MSM_RPM_ID_SMPS0B_0,
+ MSM_RPM_ID_SMPS0B_1,
+ MSM_RPM_ID_SMPS1B_0,
+ MSM_RPM_ID_SMPS1B_1,
+ MSM_RPM_ID_SMPS2B_0,
+ MSM_RPM_ID_SMPS2B_1,
+ MSM_RPM_ID_SMPS3B_0,
+ MSM_RPM_ID_SMPS3B_1,
+ MSM_RPM_ID_SMPS4B_0,
+ MSM_RPM_ID_SMPS4B_1,
+ MSM_RPM_ID_LDO0B_0,
+ MSM_RPM_ID_LDO0B_1,
+ MSM_RPM_ID_LDO1B_0,
+ MSM_RPM_ID_LDO1B_1,
+ MSM_RPM_ID_LDO2B_0,
+ MSM_RPM_ID_LDO2B_1,
+ MSM_RPM_ID_LDO3B_0,
+ MSM_RPM_ID_LDO3B_1,
+ MSM_RPM_ID_LDO4B_0,
+ MSM_RPM_ID_LDO4B_1,
+ MSM_RPM_ID_LDO5B_0,
+ MSM_RPM_ID_LDO5B_1,
+ MSM_RPM_ID_LDO6B_0,
+ MSM_RPM_ID_LDO6B_1,
+ MSM_RPM_ID_LVS0B,
+ MSM_RPM_ID_LVS1B,
+ MSM_RPM_ID_LVS2B,
+ MSM_RPM_ID_LVS3B,
+ MSM_RPM_ID_MVS,
+
+ /* pmic 8058 */
+ MSM_RPM_ID_SMPS0_0,
+ MSM_RPM_ID_SMPS0_1,
+ MSM_RPM_ID_SMPS1_0,
+ MSM_RPM_ID_SMPS1_1,
+ MSM_RPM_ID_SMPS2_0,
+ MSM_RPM_ID_SMPS2_1,
+ MSM_RPM_ID_SMPS3_0,
+ MSM_RPM_ID_SMPS3_1,
+ MSM_RPM_ID_SMPS4_0,
+ MSM_RPM_ID_SMPS4_1,
+ MSM_RPM_ID_LDO0_0,
+ MSM_RPM_ID_LDO0_1,
+ MSM_RPM_ID_LDO1_0,
+ MSM_RPM_ID_LDO1_1,
+ MSM_RPM_ID_LDO2_0,
+ MSM_RPM_ID_LDO2_1,
+ MSM_RPM_ID_LDO3_0,
+ MSM_RPM_ID_LDO3_1,
+ MSM_RPM_ID_LDO4_0,
+ MSM_RPM_ID_LDO4_1,
+ MSM_RPM_ID_LDO5_0,
+ MSM_RPM_ID_LDO5_1,
+ MSM_RPM_ID_LDO6_0,
+ MSM_RPM_ID_LDO6_1,
+ MSM_RPM_ID_LDO7_0,
+ MSM_RPM_ID_LDO7_1,
+ MSM_RPM_ID_LDO8_0,
+ MSM_RPM_ID_LDO8_1,
+ MSM_RPM_ID_LDO9_0,
+ MSM_RPM_ID_LDO9_1,
+ MSM_RPM_ID_LDO10_0,
+ MSM_RPM_ID_LDO10_1,
+ MSM_RPM_ID_LDO11_0,
+ MSM_RPM_ID_LDO11_1,
+ MSM_RPM_ID_LDO12_0,
+ MSM_RPM_ID_LDO12_1,
+ MSM_RPM_ID_LDO13_0,
+ MSM_RPM_ID_LDO13_1,
+ MSM_RPM_ID_LDO14_0,
+ MSM_RPM_ID_LDO14_1,
+ MSM_RPM_ID_LDO15_0,
+ MSM_RPM_ID_LDO15_1,
+ MSM_RPM_ID_LDO16_0,
+ MSM_RPM_ID_LDO16_1,
+ MSM_RPM_ID_LDO17_0,
+ MSM_RPM_ID_LDO17_1,
+ MSM_RPM_ID_LDO18_0,
+ MSM_RPM_ID_LDO18_1,
+ MSM_RPM_ID_LDO19_0,
+ MSM_RPM_ID_LDO19_1,
+ MSM_RPM_ID_LDO20_0,
+ MSM_RPM_ID_LDO20_1,
+ MSM_RPM_ID_LDO21_0,
+ MSM_RPM_ID_LDO21_1,
+ MSM_RPM_ID_LDO22_0,
+ MSM_RPM_ID_LDO22_1,
+ MSM_RPM_ID_LDO23_0,
+ MSM_RPM_ID_LDO23_1,
+ MSM_RPM_ID_LDO24_0,
+ MSM_RPM_ID_LDO24_1,
+ MSM_RPM_ID_LDO25_0,
+ MSM_RPM_ID_LDO25_1,
+ MSM_RPM_ID_LVS0,
+ MSM_RPM_ID_LVS1,
+
+ /* 9615 specific */
+ MSM_RPM_ID_PM8018_S1_0,
+ MSM_RPM_ID_PM8018_S1_1,
+ MSM_RPM_ID_PM8018_S2_0,
+ MSM_RPM_ID_PM8018_S2_1,
+ MSM_RPM_ID_PM8018_S3_0,
+ MSM_RPM_ID_PM8018_S3_1,
+ MSM_RPM_ID_PM8018_S4_0,
+ MSM_RPM_ID_PM8018_S4_1,
+ MSM_RPM_ID_PM8018_S5_0,
+ MSM_RPM_ID_PM8018_S5_1,
+ MSM_RPM_ID_PM8018_L1_0,
+ MSM_RPM_ID_PM8018_L1_1,
+ MSM_RPM_ID_PM8018_L2_0,
+ MSM_RPM_ID_PM8018_L2_1,
+ MSM_RPM_ID_PM8018_L3_0,
+ MSM_RPM_ID_PM8018_L3_1,
+ MSM_RPM_ID_PM8018_L4_0,
+ MSM_RPM_ID_PM8018_L4_1,
+ MSM_RPM_ID_PM8018_L5_0,
+ MSM_RPM_ID_PM8018_L5_1,
+ MSM_RPM_ID_PM8018_L6_0,
+ MSM_RPM_ID_PM8018_L6_1,
+ MSM_RPM_ID_PM8018_L7_0,
+ MSM_RPM_ID_PM8018_L7_1,
+ MSM_RPM_ID_PM8018_L8_0,
+ MSM_RPM_ID_PM8018_L8_1,
+ MSM_RPM_ID_PM8018_L9_0,
+ MSM_RPM_ID_PM8018_L9_1,
+ MSM_RPM_ID_PM8018_L10_0,
+ MSM_RPM_ID_PM8018_L10_1,
+ MSM_RPM_ID_PM8018_L11_0,
+ MSM_RPM_ID_PM8018_L11_1,
+ MSM_RPM_ID_PM8018_L12_0,
+ MSM_RPM_ID_PM8018_L12_1,
+ MSM_RPM_ID_PM8018_L13_0,
+ MSM_RPM_ID_PM8018_L13_1,
+ MSM_RPM_ID_PM8018_L14_0,
+ MSM_RPM_ID_PM8018_L14_1,
+ MSM_RPM_ID_PM8018_LVS1,
+
+ /* 8930 specific */
+ MSM_RPM_ID_PM8038_S1_0,
+ MSM_RPM_ID_PM8038_S1_1,
+ MSM_RPM_ID_PM8038_S2_0,
+ MSM_RPM_ID_PM8038_S2_1,
+ MSM_RPM_ID_PM8038_S3_0,
+ MSM_RPM_ID_PM8038_S3_1,
+ MSM_RPM_ID_PM8038_S4_0,
+ MSM_RPM_ID_PM8038_S4_1,
+ MSM_RPM_ID_PM8038_S5_0,
+ MSM_RPM_ID_PM8038_S5_1,
+ MSM_RPM_ID_PM8038_S6_0,
+ MSM_RPM_ID_PM8038_S6_1,
+ MSM_RPM_ID_PM8038_L1_0,
+ MSM_RPM_ID_PM8038_L1_1,
+ MSM_RPM_ID_PM8038_L2_0,
+ MSM_RPM_ID_PM8038_L2_1,
+ MSM_RPM_ID_PM8038_L3_0,
+ MSM_RPM_ID_PM8038_L3_1,
+ MSM_RPM_ID_PM8038_L4_0,
+ MSM_RPM_ID_PM8038_L4_1,
+ MSM_RPM_ID_PM8038_L5_0,
+ MSM_RPM_ID_PM8038_L5_1,
+ MSM_RPM_ID_PM8038_L6_0,
+ MSM_RPM_ID_PM8038_L6_1,
+ MSM_RPM_ID_PM8038_L7_0,
+ MSM_RPM_ID_PM8038_L7_1,
+ MSM_RPM_ID_PM8038_L8_0,
+ MSM_RPM_ID_PM8038_L8_1,
+ MSM_RPM_ID_PM8038_L9_0,
+ MSM_RPM_ID_PM8038_L9_1,
+ MSM_RPM_ID_PM8038_L10_0,
+ MSM_RPM_ID_PM8038_L10_1,
+ MSM_RPM_ID_PM8038_L11_0,
+ MSM_RPM_ID_PM8038_L11_1,
+ MSM_RPM_ID_PM8038_L12_0,
+ MSM_RPM_ID_PM8038_L12_1,
+ MSM_RPM_ID_PM8038_L13_0,
+ MSM_RPM_ID_PM8038_L13_1,
+ MSM_RPM_ID_PM8038_L14_0,
+ MSM_RPM_ID_PM8038_L14_1,
+ MSM_RPM_ID_PM8038_L15_0,
+ MSM_RPM_ID_PM8038_L15_1,
+ MSM_RPM_ID_PM8038_L16_0,
+ MSM_RPM_ID_PM8038_L16_1,
+ MSM_RPM_ID_PM8038_L17_0,
+ MSM_RPM_ID_PM8038_L17_1,
+ MSM_RPM_ID_PM8038_L18_0,
+ MSM_RPM_ID_PM8038_L18_1,
+ MSM_RPM_ID_PM8038_L19_0,
+ MSM_RPM_ID_PM8038_L19_1,
+ MSM_RPM_ID_PM8038_L20_0,
+ MSM_RPM_ID_PM8038_L20_1,
+ MSM_RPM_ID_PM8038_L21_0,
+ MSM_RPM_ID_PM8038_L21_1,
+ MSM_RPM_ID_PM8038_L22_0,
+ MSM_RPM_ID_PM8038_L22_1,
+ MSM_RPM_ID_PM8038_L23_0,
+ MSM_RPM_ID_PM8038_L23_1,
+ MSM_RPM_ID_PM8038_L24_0,
+ MSM_RPM_ID_PM8038_L24_1,
+ MSM_RPM_ID_PM8038_L25_0,
+ MSM_RPM_ID_PM8038_L25_1,
+ MSM_RPM_ID_PM8038_L26_0,
+ MSM_RPM_ID_PM8038_L26_1,
+ MSM_RPM_ID_PM8038_L27_0,
+ MSM_RPM_ID_PM8038_L27_1,
+ MSM_RPM_ID_PM8038_CLK1_0,
+ MSM_RPM_ID_PM8038_CLK1_1,
+ MSM_RPM_ID_PM8038_CLK2_0,
+ MSM_RPM_ID_PM8038_CLK2_1,
+ MSM_RPM_ID_PM8038_LVS1,
+ MSM_RPM_ID_PM8038_LVS2,
+
+ /* 8064 specific */
+ MSM_RPM_ID_PM8821_S1_0,
+ MSM_RPM_ID_PM8821_S1_1,
+ MSM_RPM_ID_PM8821_S2_0,
+ MSM_RPM_ID_PM8821_S2_1,
+ MSM_RPM_ID_PM8821_L1_0,
+ MSM_RPM_ID_PM8821_L1_1,
+
+ MSM_RPM_ID_LAST,
+};
+
+enum {
+ MSM_RPM_STATUS_ID_VERSION_MAJOR,
+ MSM_RPM_STATUS_ID_VERSION_MINOR,
+ MSM_RPM_STATUS_ID_VERSION_BUILD,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1,
+ MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2,
+ MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0,
+ MSM_RPM_STATUS_ID_SEQUENCE,
+ MSM_RPM_STATUS_ID_RPM_CTL,
+ MSM_RPM_STATUS_ID_CXO_CLK,
+ MSM_RPM_STATUS_ID_PXO_CLK,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CLK,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK,
+ MSM_RPM_STATUS_ID_MM_FABRIC_CLK,
+ MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK,
+ MSM_RPM_STATUS_ID_SFPB_CLK,
+ MSM_RPM_STATUS_ID_CFPB_CLK,
+ MSM_RPM_STATUS_ID_MMFPB_CLK,
+ MSM_RPM_STATUS_ID_EBI1_CLK,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_HALT =
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CLOCK_MODE =
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_IOCTL,
+ MSM_RPM_STATUS_ID_APPS_FABRIC_ARB,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_HALT =
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE =
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL,
+ MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB,
+ MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_MM_FABRIC_HALT =
+ MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT,
+ MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_MM_FABRIC_CLOCK_MODE =
+ MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD,
+ MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_IOCTL,
+ MSM_RPM_STATUS_ID_MM_FABRIC_ARB,
+ MSM_RPM_STATUS_ID_PM8921_S1_0,
+ MSM_RPM_STATUS_ID_PM8921_S1_1,
+ MSM_RPM_STATUS_ID_PM8921_S2_0,
+ MSM_RPM_STATUS_ID_PM8921_S2_1,
+ MSM_RPM_STATUS_ID_PM8921_S3_0,
+ MSM_RPM_STATUS_ID_PM8921_S3_1,
+ MSM_RPM_STATUS_ID_PM8921_S4_0,
+ MSM_RPM_STATUS_ID_PM8921_S4_1,
+ MSM_RPM_STATUS_ID_PM8921_S5_0,
+ MSM_RPM_STATUS_ID_PM8921_S5_1,
+ MSM_RPM_STATUS_ID_PM8921_S6_0,
+ MSM_RPM_STATUS_ID_PM8921_S6_1,
+ MSM_RPM_STATUS_ID_PM8921_S7_0,
+ MSM_RPM_STATUS_ID_PM8921_S7_1,
+ MSM_RPM_STATUS_ID_PM8921_S8_0,
+ MSM_RPM_STATUS_ID_PM8921_S8_1,
+ MSM_RPM_STATUS_ID_PM8921_L1_0,
+ MSM_RPM_STATUS_ID_PM8921_L1_1,
+ MSM_RPM_STATUS_ID_PM8921_L2_0,
+ MSM_RPM_STATUS_ID_PM8921_L2_1,
+ MSM_RPM_STATUS_ID_PM8921_L3_0,
+ MSM_RPM_STATUS_ID_PM8921_L3_1,
+ MSM_RPM_STATUS_ID_PM8921_L4_0,
+ MSM_RPM_STATUS_ID_PM8921_L4_1,
+ MSM_RPM_STATUS_ID_PM8921_L5_0,
+ MSM_RPM_STATUS_ID_PM8921_L5_1,
+ MSM_RPM_STATUS_ID_PM8921_L6_0,
+ MSM_RPM_STATUS_ID_PM8921_L6_1,
+ MSM_RPM_STATUS_ID_PM8921_L7_0,
+ MSM_RPM_STATUS_ID_PM8921_L7_1,
+ MSM_RPM_STATUS_ID_PM8921_L8_0,
+ MSM_RPM_STATUS_ID_PM8921_L8_1,
+ MSM_RPM_STATUS_ID_PM8921_L9_0,
+ MSM_RPM_STATUS_ID_PM8921_L9_1,
+ MSM_RPM_STATUS_ID_PM8921_L10_0,
+ MSM_RPM_STATUS_ID_PM8921_L10_1,
+ MSM_RPM_STATUS_ID_PM8921_L11_0,
+ MSM_RPM_STATUS_ID_PM8921_L11_1,
+ MSM_RPM_STATUS_ID_PM8921_L12_0,
+ MSM_RPM_STATUS_ID_PM8921_L12_1,
+ MSM_RPM_STATUS_ID_PM8921_L13_0,
+ MSM_RPM_STATUS_ID_PM8921_L13_1,
+ MSM_RPM_STATUS_ID_PM8921_L14_0,
+ MSM_RPM_STATUS_ID_PM8921_L14_1,
+ MSM_RPM_STATUS_ID_PM8921_L15_0,
+ MSM_RPM_STATUS_ID_PM8921_L15_1,
+ MSM_RPM_STATUS_ID_PM8921_L16_0,
+ MSM_RPM_STATUS_ID_PM8921_L16_1,
+ MSM_RPM_STATUS_ID_PM8921_L17_0,
+ MSM_RPM_STATUS_ID_PM8921_L17_1,
+ MSM_RPM_STATUS_ID_PM8921_L18_0,
+ MSM_RPM_STATUS_ID_PM8921_L18_1,
+ MSM_RPM_STATUS_ID_PM8921_L19_0,
+ MSM_RPM_STATUS_ID_PM8921_L19_1,
+ MSM_RPM_STATUS_ID_PM8921_L20_0,
+ MSM_RPM_STATUS_ID_PM8921_L20_1,
+ MSM_RPM_STATUS_ID_PM8921_L21_0,
+ MSM_RPM_STATUS_ID_PM8921_L21_1,
+ MSM_RPM_STATUS_ID_PM8921_L22_0,
+ MSM_RPM_STATUS_ID_PM8921_L22_1,
+ MSM_RPM_STATUS_ID_PM8921_L23_0,
+ MSM_RPM_STATUS_ID_PM8921_L23_1,
+ MSM_RPM_STATUS_ID_PM8921_L24_0,
+ MSM_RPM_STATUS_ID_PM8921_L24_1,
+ MSM_RPM_STATUS_ID_PM8921_L25_0,
+ MSM_RPM_STATUS_ID_PM8921_L25_1,
+ MSM_RPM_STATUS_ID_PM8921_L26_0,
+ MSM_RPM_STATUS_ID_PM8921_L26_1,
+ MSM_RPM_STATUS_ID_PM8921_L27_0,
+ MSM_RPM_STATUS_ID_PM8921_L27_1,
+ MSM_RPM_STATUS_ID_PM8921_L28_0,
+ MSM_RPM_STATUS_ID_PM8921_L28_1,
+ MSM_RPM_STATUS_ID_PM8921_L29_0,
+ MSM_RPM_STATUS_ID_PM8921_L29_1,
+ MSM_RPM_STATUS_ID_PM8921_CLK1_0,
+ MSM_RPM_STATUS_ID_PM8921_CLK1_1,
+ MSM_RPM_STATUS_ID_PM8921_CLK2_0,
+ MSM_RPM_STATUS_ID_PM8921_CLK2_1,
+ MSM_RPM_STATUS_ID_PM8921_LVS1,
+ MSM_RPM_STATUS_ID_PM8921_LVS2,
+ MSM_RPM_STATUS_ID_PM8921_LVS3,
+ MSM_RPM_STATUS_ID_PM8921_LVS4,
+ MSM_RPM_STATUS_ID_PM8921_LVS5,
+ MSM_RPM_STATUS_ID_PM8921_LVS6,
+ MSM_RPM_STATUS_ID_PM8921_LVS7,
+ MSM_RPM_STATUS_ID_NCP_0,
+ MSM_RPM_STATUS_ID_NCP_1,
+ MSM_RPM_STATUS_ID_CXO_BUFFERS,
+ MSM_RPM_STATUS_ID_USB_OTG_SWITCH,
+ MSM_RPM_STATUS_ID_HDMI_SWITCH,
+ MSM_RPM_STATUS_ID_DDR_DMM_0,
+ MSM_RPM_STATUS_ID_DDR_DMM_1,
+ MSM_RPM_STATUS_ID_EBI1_CH0_RANGE,
+ MSM_RPM_STATUS_ID_EBI1_CH1_RANGE,
+
+ /* 8660 Specific */
+ MSM_RPM_STATUS_ID_PLL_4,
+ MSM_RPM_STATUS_ID_SMI_CLK,
+ MSM_RPM_STATUS_ID_APPS_L2_CACHE_CTL,
+ MSM_RPM_STATUS_ID_SMPS0B_0,
+ MSM_RPM_STATUS_ID_SMPS0B_1,
+ MSM_RPM_STATUS_ID_SMPS1B_0,
+ MSM_RPM_STATUS_ID_SMPS1B_1,
+ MSM_RPM_STATUS_ID_SMPS2B_0,
+ MSM_RPM_STATUS_ID_SMPS2B_1,
+ MSM_RPM_STATUS_ID_SMPS3B_0,
+ MSM_RPM_STATUS_ID_SMPS3B_1,
+ MSM_RPM_STATUS_ID_SMPS4B_0,
+ MSM_RPM_STATUS_ID_SMPS4B_1,
+ MSM_RPM_STATUS_ID_LDO0B_0,
+ MSM_RPM_STATUS_ID_LDO0B_1,
+ MSM_RPM_STATUS_ID_LDO1B_0,
+ MSM_RPM_STATUS_ID_LDO1B_1,
+ MSM_RPM_STATUS_ID_LDO2B_0,
+ MSM_RPM_STATUS_ID_LDO2B_1,
+ MSM_RPM_STATUS_ID_LDO3B_0,
+ MSM_RPM_STATUS_ID_LDO3B_1,
+ MSM_RPM_STATUS_ID_LDO4B_0,
+ MSM_RPM_STATUS_ID_LDO4B_1,
+ MSM_RPM_STATUS_ID_LDO5B_0,
+ MSM_RPM_STATUS_ID_LDO5B_1,
+ MSM_RPM_STATUS_ID_LDO6B_0,
+ MSM_RPM_STATUS_ID_LDO6B_1,
+ MSM_RPM_STATUS_ID_LVS0B,
+ MSM_RPM_STATUS_ID_LVS1B,
+ MSM_RPM_STATUS_ID_LVS2B,
+ MSM_RPM_STATUS_ID_LVS3B,
+ MSM_RPM_STATUS_ID_MVS,
+ MSM_RPM_STATUS_ID_SMPS0_0,
+ MSM_RPM_STATUS_ID_SMPS0_1,
+ MSM_RPM_STATUS_ID_SMPS1_0,
+ MSM_RPM_STATUS_ID_SMPS1_1,
+ MSM_RPM_STATUS_ID_SMPS2_0,
+ MSM_RPM_STATUS_ID_SMPS2_1,
+ MSM_RPM_STATUS_ID_SMPS3_0,
+ MSM_RPM_STATUS_ID_SMPS3_1,
+ MSM_RPM_STATUS_ID_SMPS4_0,
+ MSM_RPM_STATUS_ID_SMPS4_1,
+ MSM_RPM_STATUS_ID_LDO0_0,
+ MSM_RPM_STATUS_ID_LDO0_1,
+ MSM_RPM_STATUS_ID_LDO1_0,
+ MSM_RPM_STATUS_ID_LDO1_1,
+ MSM_RPM_STATUS_ID_LDO2_0,
+ MSM_RPM_STATUS_ID_LDO2_1,
+ MSM_RPM_STATUS_ID_LDO3_0,
+ MSM_RPM_STATUS_ID_LDO3_1,
+ MSM_RPM_STATUS_ID_LDO4_0,
+ MSM_RPM_STATUS_ID_LDO4_1,
+ MSM_RPM_STATUS_ID_LDO5_0,
+ MSM_RPM_STATUS_ID_LDO5_1,
+ MSM_RPM_STATUS_ID_LDO6_0,
+ MSM_RPM_STATUS_ID_LDO6_1,
+ MSM_RPM_STATUS_ID_LDO7_0,
+ MSM_RPM_STATUS_ID_LDO7_1,
+ MSM_RPM_STATUS_ID_LDO8_0,
+ MSM_RPM_STATUS_ID_LDO8_1,
+ MSM_RPM_STATUS_ID_LDO9_0,
+ MSM_RPM_STATUS_ID_LDO9_1,
+ MSM_RPM_STATUS_ID_LDO10_0,
+ MSM_RPM_STATUS_ID_LDO10_1,
+ MSM_RPM_STATUS_ID_LDO11_0,
+ MSM_RPM_STATUS_ID_LDO11_1,
+ MSM_RPM_STATUS_ID_LDO12_0,
+ MSM_RPM_STATUS_ID_LDO12_1,
+ MSM_RPM_STATUS_ID_LDO13_0,
+ MSM_RPM_STATUS_ID_LDO13_1,
+ MSM_RPM_STATUS_ID_LDO14_0,
+ MSM_RPM_STATUS_ID_LDO14_1,
+ MSM_RPM_STATUS_ID_LDO15_0,
+ MSM_RPM_STATUS_ID_LDO15_1,
+ MSM_RPM_STATUS_ID_LDO16_0,
+ MSM_RPM_STATUS_ID_LDO16_1,
+ MSM_RPM_STATUS_ID_LDO17_0,
+ MSM_RPM_STATUS_ID_LDO17_1,
+ MSM_RPM_STATUS_ID_LDO18_0,
+ MSM_RPM_STATUS_ID_LDO18_1,
+ MSM_RPM_STATUS_ID_LDO19_0,
+ MSM_RPM_STATUS_ID_LDO19_1,
+ MSM_RPM_STATUS_ID_LDO20_0,
+ MSM_RPM_STATUS_ID_LDO20_1,
+ MSM_RPM_STATUS_ID_LDO21_0,
+ MSM_RPM_STATUS_ID_LDO21_1,
+ MSM_RPM_STATUS_ID_LDO22_0,
+ MSM_RPM_STATUS_ID_LDO22_1,
+ MSM_RPM_STATUS_ID_LDO23_0,
+ MSM_RPM_STATUS_ID_LDO23_1,
+ MSM_RPM_STATUS_ID_LDO24_0,
+ MSM_RPM_STATUS_ID_LDO24_1,
+ MSM_RPM_STATUS_ID_LDO25_0,
+ MSM_RPM_STATUS_ID_LDO25_1,
+ MSM_RPM_STATUS_ID_LVS0,
+ MSM_RPM_STATUS_ID_LVS1,
+
+ /* 9615 Specific */
+ MSM_RPM_STATUS_ID_PM8018_S1_0,
+ MSM_RPM_STATUS_ID_PM8018_S1_1,
+ MSM_RPM_STATUS_ID_PM8018_S2_0,
+ MSM_RPM_STATUS_ID_PM8018_S2_1,
+ MSM_RPM_STATUS_ID_PM8018_S3_0,
+ MSM_RPM_STATUS_ID_PM8018_S3_1,
+ MSM_RPM_STATUS_ID_PM8018_S4_0,
+ MSM_RPM_STATUS_ID_PM8018_S4_1,
+ MSM_RPM_STATUS_ID_PM8018_S5_0,
+ MSM_RPM_STATUS_ID_PM8018_S5_1,
+ MSM_RPM_STATUS_ID_PM8018_L1_0,
+ MSM_RPM_STATUS_ID_PM8018_L1_1,
+ MSM_RPM_STATUS_ID_PM8018_L2_0,
+ MSM_RPM_STATUS_ID_PM8018_L2_1,
+ MSM_RPM_STATUS_ID_PM8018_L3_0,
+ MSM_RPM_STATUS_ID_PM8018_L3_1,
+ MSM_RPM_STATUS_ID_PM8018_L4_0,
+ MSM_RPM_STATUS_ID_PM8018_L4_1,
+ MSM_RPM_STATUS_ID_PM8018_L5_0,
+ MSM_RPM_STATUS_ID_PM8018_L5_1,
+ MSM_RPM_STATUS_ID_PM8018_L6_0,
+ MSM_RPM_STATUS_ID_PM8018_L6_1,
+ MSM_RPM_STATUS_ID_PM8018_L7_0,
+ MSM_RPM_STATUS_ID_PM8018_L7_1,
+ MSM_RPM_STATUS_ID_PM8018_L8_0,
+ MSM_RPM_STATUS_ID_PM8018_L8_1,
+ MSM_RPM_STATUS_ID_PM8018_L9_0,
+ MSM_RPM_STATUS_ID_PM8018_L9_1,
+ MSM_RPM_STATUS_ID_PM8018_L10_0,
+ MSM_RPM_STATUS_ID_PM8018_L10_1,
+ MSM_RPM_STATUS_ID_PM8018_L11_0,
+ MSM_RPM_STATUS_ID_PM8018_L11_1,
+ MSM_RPM_STATUS_ID_PM8018_L12_0,
+ MSM_RPM_STATUS_ID_PM8018_L12_1,
+ MSM_RPM_STATUS_ID_PM8018_L13_0,
+ MSM_RPM_STATUS_ID_PM8018_L13_1,
+ MSM_RPM_STATUS_ID_PM8018_L14_0,
+ MSM_RPM_STATUS_ID_PM8018_L14_1,
+ MSM_RPM_STATUS_ID_PM8018_LVS1,
+
+ /* 8930 specific */
+ MSM_RPM_STATUS_ID_PM8038_S1_0,
+ MSM_RPM_STATUS_ID_PM8038_S1_1,
+ MSM_RPM_STATUS_ID_PM8038_S2_0,
+ MSM_RPM_STATUS_ID_PM8038_S2_1,
+ MSM_RPM_STATUS_ID_PM8038_S3_0,
+ MSM_RPM_STATUS_ID_PM8038_S3_1,
+ MSM_RPM_STATUS_ID_PM8038_S4_0,
+ MSM_RPM_STATUS_ID_PM8038_S4_1,
+ MSM_RPM_STATUS_ID_PM8038_S5_0,
+ MSM_RPM_STATUS_ID_PM8038_S5_1,
+ MSM_RPM_STATUS_ID_PM8038_S6_0,
+ MSM_RPM_STATUS_ID_PM8038_S6_1,
+ MSM_RPM_STATUS_ID_PM8038_L1_0,
+ MSM_RPM_STATUS_ID_PM8038_L1_1,
+ MSM_RPM_STATUS_ID_PM8038_L2_0,
+ MSM_RPM_STATUS_ID_PM8038_L2_1,
+ MSM_RPM_STATUS_ID_PM8038_L3_0,
+ MSM_RPM_STATUS_ID_PM8038_L3_1,
+ MSM_RPM_STATUS_ID_PM8038_L4_0,
+ MSM_RPM_STATUS_ID_PM8038_L4_1,
+ MSM_RPM_STATUS_ID_PM8038_L5_0,
+ MSM_RPM_STATUS_ID_PM8038_L5_1,
+ MSM_RPM_STATUS_ID_PM8038_L6_0,
+ MSM_RPM_STATUS_ID_PM8038_L6_1,
+ MSM_RPM_STATUS_ID_PM8038_L7_0,
+ MSM_RPM_STATUS_ID_PM8038_L7_1,
+ MSM_RPM_STATUS_ID_PM8038_L8_0,
+ MSM_RPM_STATUS_ID_PM8038_L8_1,
+ MSM_RPM_STATUS_ID_PM8038_L9_0,
+ MSM_RPM_STATUS_ID_PM8038_L9_1,
+ MSM_RPM_STATUS_ID_PM8038_L10_0,
+ MSM_RPM_STATUS_ID_PM8038_L10_1,
+ MSM_RPM_STATUS_ID_PM8038_L11_0,
+ MSM_RPM_STATUS_ID_PM8038_L11_1,
+ MSM_RPM_STATUS_ID_PM8038_L12_0,
+ MSM_RPM_STATUS_ID_PM8038_L12_1,
+ MSM_RPM_STATUS_ID_PM8038_L13_0,
+ MSM_RPM_STATUS_ID_PM8038_L13_1,
+ MSM_RPM_STATUS_ID_PM8038_L14_0,
+ MSM_RPM_STATUS_ID_PM8038_L14_1,
+ MSM_RPM_STATUS_ID_PM8038_L15_0,
+ MSM_RPM_STATUS_ID_PM8038_L15_1,
+ MSM_RPM_STATUS_ID_PM8038_L16_0,
+ MSM_RPM_STATUS_ID_PM8038_L16_1,
+ MSM_RPM_STATUS_ID_PM8038_L17_0,
+ MSM_RPM_STATUS_ID_PM8038_L17_1,
+ MSM_RPM_STATUS_ID_PM8038_L18_0,
+ MSM_RPM_STATUS_ID_PM8038_L18_1,
+ MSM_RPM_STATUS_ID_PM8038_L19_0,
+ MSM_RPM_STATUS_ID_PM8038_L19_1,
+ MSM_RPM_STATUS_ID_PM8038_L20_0,
+ MSM_RPM_STATUS_ID_PM8038_L20_1,
+ MSM_RPM_STATUS_ID_PM8038_L21_0,
+ MSM_RPM_STATUS_ID_PM8038_L21_1,
+ MSM_RPM_STATUS_ID_PM8038_L22_0,
+ MSM_RPM_STATUS_ID_PM8038_L22_1,
+ MSM_RPM_STATUS_ID_PM8038_L23_0,
+ MSM_RPM_STATUS_ID_PM8038_L23_1,
+ MSM_RPM_STATUS_ID_PM8038_L24_0,
+ MSM_RPM_STATUS_ID_PM8038_L24_1,
+ MSM_RPM_STATUS_ID_PM8038_L25_0,
+ MSM_RPM_STATUS_ID_PM8038_L25_1,
+ MSM_RPM_STATUS_ID_PM8038_L26_0,
+ MSM_RPM_STATUS_ID_PM8038_L26_1,
+ MSM_RPM_STATUS_ID_PM8038_L27_0,
+ MSM_RPM_STATUS_ID_PM8038_L27_1,
+ MSM_RPM_STATUS_ID_PM8038_CLK1_0,
+ MSM_RPM_STATUS_ID_PM8038_CLK1_1,
+ MSM_RPM_STATUS_ID_PM8038_CLK2_0,
+ MSM_RPM_STATUS_ID_PM8038_CLK2_1,
+ MSM_RPM_STATUS_ID_PM8038_LVS1,
+ MSM_RPM_STATUS_ID_PM8038_LVS2,
+
+ /* 8064 specific */
+ MSM_RPM_STATUS_ID_PM8821_S1_0,
+ MSM_RPM_STATUS_ID_PM8821_S1_1,
+ MSM_RPM_STATUS_ID_PM8821_S2_0,
+ MSM_RPM_STATUS_ID_PM8821_S2_1,
+ MSM_RPM_STATUS_ID_PM8821_L1_0,
+ MSM_RPM_STATUS_ID_PM8821_L1_1,
+
+ MSM_RPM_STATUS_ID_LAST,
+};
+
static inline uint32_t msm_rpm_get_ctx_mask(unsigned int ctx)
{
return 1UL << ctx;
}
-#define MSM_RPM_SEL_MASK_SIZE (MSM_RPM_SEL_LAST / 32 + 1)
-
static inline unsigned int msm_rpm_get_sel_mask_reg(unsigned int sel)
{
return sel / 32;
@@ -69,7 +849,7 @@
struct msm_rpm_notification {
struct list_head list; /* reserved for RPM use */
struct semaphore sem;
- uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE]; /* reserved for RPM use */
+ uint32_t sel_masks[SEL_MASK_SIZE]; /* reserved for RPM use */
};
struct msm_rpm_map_data {
@@ -78,22 +858,41 @@
uint32_t count;
};
-#define MSM_RPM_MAP(i, s, c) { \
- .id = MSM_RPM_ID_##i, .sel = MSM_RPM_SEL_##s, .count = c }
+#define MSM_RPM_MAP(t, i, s, c) \
+ [MSM_RPM_ID_##i] = \
+ {\
+ .id = MSM_RPM_##t##_ID_##i, \
+ .sel = MSM_RPM_##t##_SEL_##s, \
+ .count = c, \
+ }
+
+#define MSM_RPM_STATUS_ID_VALID BIT(31)
+
+#define MSM_RPM_STATUS_ID_MAP(t, i) \
+ [MSM_RPM_STATUS_ID_## i] = (MSM_RPM_##t##_STATUS_ID_##i \
+ | MSM_RPM_STATUS_ID_VALID)
+
+#define MSM_RPM_CTRL_MAP(t, i) \
+ [MSM_RPM_CTRL_##i] = MSM_RPM_##t##_CTRL_##i
struct msm_rpm_platform_data {
void __iomem *reg_base_addrs[MSM_RPM_PAGE_COUNT];
-
unsigned int irq_ack;
- unsigned int irq_err;
- unsigned int irq_vmpm;
- void *msm_apps_ipc_rpm_reg;
- unsigned int msm_apps_ipc_rpm_val;
+ void *ipc_rpm_reg;
+ unsigned int ipc_rpm_val;
+ struct msm_rpm_map_data target_id[MSM_RPM_ID_LAST];
+ unsigned int target_status[MSM_RPM_STATUS_ID_LAST];
+ unsigned int target_ctrl_id[MSM_RPM_CTRL_LAST];
+ unsigned int sel_invalidate, sel_notification, sel_last;
+ unsigned int ver[3];
};
-extern struct msm_rpm_map_data rpm_map_data[];
-extern unsigned int rpm_map_data_size;
+extern struct msm_rpm_platform_data msm8660_rpm_data;
+extern struct msm_rpm_platform_data msm8960_rpm_data;
+extern struct msm_rpm_platform_data msm9615_rpm_data;
+extern struct msm_rpm_platform_data msm8930_rpm_data;
+extern struct msm_rpm_platform_data apq8064_rpm_data;
int msm_rpm_local_request_is_outstanding(void);
int msm_rpm_get_status(struct msm_rpm_iv_pair *status, int count);
diff --git a/arch/arm/mach-msm/mpm.c b/arch/arm/mach-msm/mpm.c
index 70ee39b..746c0f8 100644
--- a/arch/arm/mach-msm/mpm.c
+++ b/arch/arm/mach-msm/mpm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -20,8 +20,9 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
-#include <asm/hardware/gic.h>
+#include <linux/slab.h>
#include <linux/spinlock.h>
+#include <asm/hardware/gic.h>
#include <mach/msm_iomap.h>
#include <mach/gpio.h>
@@ -68,6 +69,7 @@
#define MSM_MPM_IRQ_INDEX(irq) (irq / 32)
#define MSM_MPM_IRQ_MASK(irq) BIT(irq % 32)
+static struct msm_mpm_device_data msm_mpm_dev_data;
static uint8_t msm_mpm_irqs_a2m[MSM_MPM_NR_APPS_IRQS];
static DEFINE_SPINLOCK(msm_mpm_lock);
@@ -472,7 +474,7 @@
}
core_initcall(msm_mpm_early_init);
-void msm_mpm_irq_extn_init(void)
+void __init msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data)
{
gic_arch_extn.irq_mask = msm_mpm_disable_irq;
gic_arch_extn.irq_unmask = msm_mpm_enable_irq;
@@ -487,6 +489,29 @@
msm_gpio_irq_extn.irq_set_wake = msm_mpm_set_irq_wake;
bitmap_set(msm_mpm_gpio_irqs_mask, NR_MSM_IRQS, NR_GPIO_IRQS);
+
+ if (!mpm_data) {
+#ifdef CONFIG_MSM_MPM
+ BUG();
+#endif
+ return;
+ }
+
+ memcpy(&msm_mpm_dev_data, mpm_data, sizeof(struct msm_mpm_device_data));
+
+ msm_mpm_dev_data.irqs_m2a =
+ kzalloc(msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t),
+ GFP_KERNEL);
+ BUG_ON(!msm_mpm_dev_data.irqs_m2a);
+ memcpy(msm_mpm_dev_data.irqs_m2a, mpm_data->irqs_m2a,
+ msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t));
+ msm_mpm_dev_data.bypassed_apps_irqs =
+ kzalloc(msm_mpm_dev_data.bypassed_apps_irqs_size *
+ sizeof(uint16_t), GFP_KERNEL);
+ BUG_ON(!msm_mpm_dev_data.bypassed_apps_irqs);
+ memcpy(msm_mpm_dev_data.bypassed_apps_irqs,
+ mpm_data->bypassed_apps_irqs,
+ msm_mpm_dev_data.bypassed_apps_irqs_size * sizeof(uint16_t));
}
static int __init msm_mpm_init(void)
diff --git a/arch/arm/mach-msm/mpm.h b/arch/arm/mach-msm/mpm.h
index 88e369c..85761bc 100644
--- a/arch/arm/mach-msm/mpm.h
+++ b/arch/arm/mach-msm/mpm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -38,9 +38,14 @@
unsigned int mpm_ipc_irq;
};
-#ifdef CONFIG_MSM_MPM
-extern struct msm_mpm_device_data msm_mpm_dev_data;
+extern struct msm_mpm_device_data msm8660_mpm_dev_data;
+extern struct msm_mpm_device_data msm8960_mpm_dev_data;
+extern struct msm_mpm_device_data msm9615_mpm_dev_data;
+extern struct msm_mpm_device_data apq8064_mpm_dev_data;
+void msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data);
+
+#ifdef CONFIG_MSM_MPM
int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable);
int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on);
int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type);
@@ -48,9 +53,7 @@
bool msm_mpm_gpio_irqs_detectable(bool from_idle);
void msm_mpm_enter_sleep(bool from_idle);
void msm_mpm_exit_sleep(bool from_idle);
-void msm_mpm_irq_extn_init(void);
#else
-
int msm_mpm_enable_irq(unsigned int irq, unsigned int enable)
{ return -ENODEV; }
int msm_mpm_set_irq_wake(unsigned int irq, unsigned int on)
@@ -69,7 +72,6 @@
{ return false; }
void msm_mpm_enter_sleep(bool from_idle) {}
void msm_mpm_exit_sleep(bool from_idle) {}
-void msm_mpm_irq_extn_init(void) {}
#endif
diff --git a/arch/arm/mach-msm/rpm-regulator-8930.c b/arch/arm/mach-msm/rpm-regulator-8930.c
new file mode 100644
index 0000000..22595ec
--- /dev/null
+++ b/arch/arm/mach-msm/rpm-regulator-8930.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include "rpm-regulator-private.h"
+
+/* RPM regulator request formats */
+static struct rpm_vreg_parts ldo_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+};
+
+static struct rpm_vreg_parts smps_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+ .pm = REQUEST_MEMBER(1, 0x00800000, 23),
+ .freq = REQUEST_MEMBER(1, 0x1F000000, 24),
+ .freq_clk_src = REQUEST_MEMBER(1, 0x60000000, 29),
+};
+
+static struct rpm_vreg_parts switch_parts = {
+ .request_len = 1,
+ .enable_state = REQUEST_MEMBER(0, 0x00000001, 0),
+ .pd = REQUEST_MEMBER(0, 0x00000002, 1),
+ .pc = REQUEST_MEMBER(0, 0x0000003C, 2),
+ .pf = REQUEST_MEMBER(0, 0x000003C0, 6),
+ .hpm = REQUEST_MEMBER(0, 0x00000C00, 10),
+};
+
+/* Physically available PMIC regulator voltage setpoint ranges */
+static struct vreg_range pldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+ VOLTAGE_RANGE(3100000, 4900000, 50000),
+};
+
+static struct vreg_range nldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range nldo1200_ranges[] = {
+ VOLTAGE_RANGE( 375000, 743750, 6250),
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range smps_ranges[] = {
+ VOLTAGE_RANGE( 375000, 737500, 12500),
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+};
+
+static struct vreg_range ftsmps_ranges[] = {
+ VOLTAGE_RANGE( 350000, 650000, 50000),
+ VOLTAGE_RANGE( 700000, 1400000, 12500),
+ VOLTAGE_RANGE(1500000, 3300000, 50000),
+};
+
+static struct vreg_set_points pldo_set_points = SET_POINTS(pldo_ranges);
+static struct vreg_set_points nldo_set_points = SET_POINTS(nldo_ranges);
+static struct vreg_set_points nldo1200_set_points = SET_POINTS(nldo1200_ranges);
+static struct vreg_set_points smps_set_points = SET_POINTS(smps_ranges);
+static struct vreg_set_points ftsmps_set_points = SET_POINTS(ftsmps_ranges);
+
+static struct vreg_set_points *all_set_points[] = {
+ &pldo_set_points,
+ &nldo_set_points,
+ &nldo1200_set_points,
+ &smps_set_points,
+ &ftsmps_set_points,
+};
+
+#define LDO(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8038_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8930_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_LDO, \
+ .set_points = &_ranges##_set_points, \
+ .part = &ldo_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define SMPS(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8038_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8930_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_SMPS, \
+ .set_points = &_ranges##_set_points, \
+ .part = &smps_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define LVS(_id, _name, _name_pc) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id, }, \
+ [1] = { .id = -1, }, \
+ }, \
+ .type = RPM_REGULATOR_TYPE_VS, \
+ .part = &switch_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+static struct vreg vregs[] = {
+ LDO(L1, "8038_l1", NULL, nldo1200, LDO_1200),
+ LDO(L2, "8038_l2", "8038_l2_pc", nldo, LDO_150),
+ LDO(L3, "8038_l3", "8038_l3_pc", pldo, LDO_50),
+ LDO(L4, "8038_l4", "8038_l4_pc", pldo, LDO_50),
+ LDO(L5, "8038_l5", "8038_l5_pc", pldo, LDO_600),
+ LDO(L6, "8038_l6", "8038_l6_pc", pldo, LDO_600),
+ LDO(L7, "8038_l7", "8038_l7_pc", pldo, LDO_600),
+ LDO(L8, "8038_l8", "8038_l8_pc", pldo, LDO_300),
+ LDO(L9, "8038_l9", "8038_l9_pc", pldo, LDO_300),
+ LDO(L10, "8038_l10", "8038_l10_pc", pldo, LDO_600),
+ LDO(L11, "8038_l11", "8038_l11_pc", pldo, LDO_600),
+ LDO(L12, "8038_l12", "8038_l12_pc", nldo, LDO_300),
+ LDO(L14, "8038_l14", "8038_l14_pc", pldo, LDO_50),
+ LDO(L15, "8038_l15", "8038_l15_pc", pldo, LDO_150),
+ LDO(L16, "8038_l16", NULL, nldo1200, LDO_1200),
+ LDO(L17, "8038_l17", "8038_l17_pc", pldo, LDO_150),
+ LDO(L18, "8038_l18", "8038_l18_pc", pldo, LDO_50),
+ LDO(L19, "8038_l19", NULL, nldo1200, LDO_1200),
+ LDO(L20, "8038_l20", NULL, nldo1200, LDO_1200),
+ LDO(L21, "8038_l21", "8038_l21_pc", pldo, LDO_150),
+ LDO(L22, "8038_l22", "8038_l22_pc", pldo, LDO_50),
+ LDO(L23, "8038_l23", "8038_l23_pc", pldo, LDO_50),
+ LDO(L24, "8038_l24", NULL, nldo1200, LDO_1200),
+ LDO(L26, "8038_l26", "8038_l26_pc", nldo, LDO_150),
+ LDO(L27, "8038_l27", NULL, nldo1200, LDO_1200),
+
+ SMPS(S1, "8038_s1", "8038_s1_pc", smps, SMPS_1500),
+ SMPS(S2, "8038_s2", "8038_s2_pc", smps, SMPS_1500),
+ SMPS(S3, "8038_s3", "8038_s3_pc", smps, SMPS_1500),
+ SMPS(S4, "8038_s4", "8038_s4_pc", smps, SMPS_1500),
+ SMPS(S5, "8038_s5", NULL, ftsmps, SMPS_2000),
+ SMPS(S6, "8038_s6", NULL, ftsmps, SMPS_2000),
+
+ LVS(LVS1, "8038_lvs1", "8038_lvs1_pc"),
+ LVS(LVS2, "8038_lvs2", "8038_lvs2_pc"),
+};
+
+static const char *pin_func_label[] = {
+ [RPM_VREG_PIN_FN_8930_DONT_CARE] = "don't care",
+ [RPM_VREG_PIN_FN_8930_ENABLE] = "on/off",
+ [RPM_VREG_PIN_FN_8930_MODE] = "HPM/LPM",
+ [RPM_VREG_PIN_FN_8930_SLEEP_B] = "sleep_b",
+ [RPM_VREG_PIN_FN_8930_NONE] = "none",
+};
+
+static const char *force_mode_label[] = {
+ [RPM_VREG_FORCE_MODE_8930_NONE] = "none",
+ [RPM_VREG_FORCE_MODE_8930_LPM] = "LPM",
+ [RPM_VREG_FORCE_MODE_8930_AUTO] = "auto",
+ [RPM_VREG_FORCE_MODE_8930_HPM] = "HPM",
+ [RPM_VREG_FORCE_MODE_8930_BYPASS] = "BYP",
+};
+
+static const char *power_mode_label[] = {
+ [RPM_VREG_POWER_MODE_8930_HYSTERETIC] = "HYS",
+ [RPM_VREG_POWER_MODE_8930_PWM] = "PWM",
+};
+
+static const char *pin_control_label[] = {
+ " D1",
+ " A0",
+ " A1",
+ " A2",
+};
+
+static int is_real_id(int id)
+{
+ return (id >= 0) && (id <= RPM_VREG_ID_PM8038_MAX_REAL);
+}
+
+static int pc_id_to_real_id(int id)
+{
+ int real_id = 0;
+
+ if (id >= RPM_VREG_ID_PM8038_L2_PC && id <= RPM_VREG_ID_PM8038_L15_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L2_PC;
+ else if (id >= RPM_VREG_ID_PM8038_L17_PC
+ && id <= RPM_VREG_ID_PM8038_L18_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L17_PC
+ + RPM_VREG_ID_PM8038_L17;
+ else if (id >= RPM_VREG_ID_PM8038_L21_PC
+ && id <= RPM_VREG_ID_PM8038_L23_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L21_PC
+ + RPM_VREG_ID_PM8038_L21;
+ else if (id == RPM_VREG_ID_PM8038_L26_PC)
+ real_id = RPM_VREG_ID_PM8038_L26;
+ else if (id >= RPM_VREG_ID_PM8038_S1_PC
+ && id <= RPM_VREG_ID_PM8038_S4_PC)
+ real_id = id - RPM_VREG_ID_PM8038_S1_PC
+ + RPM_VREG_ID_PM8038_S1;
+ else if (id >= RPM_VREG_ID_PM8038_LVS1_PC
+ && id <= RPM_VREG_ID_PM8038_LVS2_PC)
+ real_id = id - RPM_VREG_ID_PM8038_LVS1_PC
+ + RPM_VREG_ID_PM8038_LVS1;
+
+ return real_id;
+}
+
+static struct vreg_config config = {
+ .vregs = vregs,
+ .vregs_len = ARRAY_SIZE(vregs),
+
+ .vreg_id_min = RPM_VREG_ID_PM8038_L1,
+ .vreg_id_max = RPM_VREG_ID_PM8038_MAX,
+
+ .pin_func_none = RPM_VREG_PIN_FN_8930_NONE,
+ .pin_func_sleep_b = RPM_VREG_PIN_FN_8930_SLEEP_B,
+
+ .mode_lpm = REGULATOR_MODE_IDLE,
+ .mode_hpm = REGULATOR_MODE_NORMAL,
+
+ .set_points = all_set_points,
+ .set_points_len = ARRAY_SIZE(all_set_points),
+
+ .label_pin_ctrl = pin_control_label,
+ .label_pin_ctrl_len = ARRAY_SIZE(pin_control_label),
+ .label_pin_func = pin_func_label,
+ .label_pin_func_len = ARRAY_SIZE(pin_func_label),
+ .label_force_mode = force_mode_label,
+ .label_force_mode_len = ARRAY_SIZE(force_mode_label),
+ .label_power_mode = power_mode_label,
+ .label_power_mode_len = ARRAY_SIZE(power_mode_label),
+
+ .is_real_id = is_real_id,
+ .pc_id_to_real_id = pc_id_to_real_id,
+};
+
+struct vreg_config *get_config_8930(void)
+{
+ return &config;
+}
diff --git a/arch/arm/mach-msm/rpm-regulator-private.h b/arch/arm/mach-msm/rpm-regulator-private.h
index ff127d9..88b52ea 100644
--- a/arch/arm/mach-msm/rpm-regulator-private.h
+++ b/arch/arm/mach-msm/rpm-regulator-private.h
@@ -144,7 +144,7 @@
#define MICRO_TO_MILLI(uV) ((uV) / 1000)
#define MILLI_TO_MICRO(mV) ((mV) * 1000)
-#if defined(CONFIG_ARCH_MSM8X60)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM8X60)
struct vreg_config *get_config_8660(void);
#else
static inline struct vreg_config *get_config_8660(void)
@@ -153,7 +153,8 @@
}
#endif
-#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && \
+ (defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064))
struct vreg_config *get_config_8960(void);
#else
static inline struct vreg_config *get_config_8960(void)
@@ -162,7 +163,7 @@
}
#endif
-#if defined(CONFIG_ARCH_MSM9615)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM9615)
struct vreg_config *get_config_9615(void);
#else
static inline struct vreg_config *get_config_9615(void)
@@ -171,4 +172,13 @@
}
#endif
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM8930)
+struct vreg_config *get_config_8930(void);
+#else
+static inline struct vreg_config *get_config_8930(void)
+{
+ return NULL;
+}
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/rpm-regulator.c b/arch/arm/mach-msm/rpm-regulator.c
index e2ebbd4..946d31b 100644
--- a/arch/arm/mach-msm/rpm-regulator.c
+++ b/arch/arm/mach-msm/rpm-regulator.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -46,6 +46,7 @@
[RPM_VREG_VERSION_8660] = get_config_8660,
[RPM_VREG_VERSION_8960] = get_config_8960,
[RPM_VREG_VERSION_9615] = get_config_9615,
+ [RPM_VREG_VERSION_8930] = get_config_8930,
};
#define SET_PART(_vreg, _part, _val) \
diff --git a/arch/arm/mach-msm/rpm.c b/arch/arm/mach-msm/rpm.c
index a8d787a..fb9d295 100644
--- a/arch/arm/mach-msm/rpm.c
+++ b/arch/arm/mach-msm/rpm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include <asm/hardware/gic.h>
#include <mach/msm_iomap.h>
#include <mach/rpm.h>
@@ -45,14 +46,15 @@
};
struct msm_rpm_notif_config {
- struct msm_rpm_iv_pair iv[MSM_RPM_SEL_MASK_SIZE * 2];
+ struct msm_rpm_iv_pair iv[SEL_MASK_SIZE * 2];
};
#define configured_iv(notif_cfg) ((notif_cfg)->iv)
-#define registered_iv(notif_cfg) ((notif_cfg)->iv + MSM_RPM_SEL_MASK_SIZE)
+#define registered_iv(notif_cfg) ((notif_cfg)->iv + msm_rpm_sel_mask_size)
-static struct msm_rpm_platform_data *msm_rpm_platform;
-static uint32_t msm_rpm_map[MSM_RPM_ID_LAST + 1];
+static uint32_t msm_rpm_sel_mask_size;
+static struct msm_rpm_platform_data msm_rpm_data;
+
static DEFINE_MUTEX(msm_rpm_mutex);
static DEFINE_SPINLOCK(msm_rpm_lock);
@@ -69,15 +71,34 @@
* Internal functions
*****************************************************************************/
+static inline unsigned int target_enum(unsigned int id)
+{
+ BUG_ON(id >= MSM_RPM_ID_LAST);
+ return msm_rpm_data.target_id[id].id;
+}
+
+static inline unsigned int target_status(unsigned int id)
+{
+ BUG_ON(id >= MSM_RPM_STATUS_ID_LAST);
+ return msm_rpm_data.target_status[id];
+}
+
+static inline unsigned int target_ctrl(unsigned int id)
+{
+ BUG_ON(id >= MSM_RPM_CTRL_LAST);
+ return msm_rpm_data.target_ctrl_id[id];
+}
+
static inline uint32_t msm_rpm_read(unsigned int page, unsigned int reg)
{
- return __raw_readl(msm_rpm_platform->reg_base_addrs[page] + reg * 4);
+ return __raw_readl(msm_rpm_data.reg_base_addrs[page] + reg * 4);
}
static inline void msm_rpm_write(
unsigned int page, unsigned int reg, uint32_t value)
{
- __raw_writel(value, msm_rpm_platform->reg_base_addrs[page] + reg * 4);
+ __raw_writel(value,
+ msm_rpm_data.reg_base_addrs[page] + reg * 4);
}
static inline void msm_rpm_read_contiguous(
@@ -109,7 +130,8 @@
static inline uint32_t msm_rpm_map_id_to_sel(uint32_t id)
{
- return (id > MSM_RPM_ID_LAST) ? MSM_RPM_SEL_LAST + 1 : msm_rpm_map[id];
+ return (id >= MSM_RPM_ID_LAST) ? msm_rpm_data.sel_last + 1 :
+ msm_rpm_data.target_id[id].sel;
}
/*
@@ -128,8 +150,11 @@
for (i = 0; i < count; i++) {
sel = msm_rpm_map_id_to_sel(req[i].id);
- if (sel > MSM_RPM_SEL_LAST)
+ if (sel > msm_rpm_data.sel_last) {
+ pr_err("%s(): RPM ID %d not defined for target\n",
+ __func__, req[i].id);
return -EINVAL;
+ }
sel_masks[msm_rpm_get_sel_mask_reg(sel)] |=
msm_rpm_get_sel_mask(sel);
@@ -140,8 +165,8 @@
static inline void msm_rpm_send_req_interrupt(void)
{
- __raw_writel(msm_rpm_platform->msm_apps_ipc_rpm_val,
- msm_rpm_platform->msm_apps_ipc_rpm_reg);
+ __raw_writel(msm_rpm_data.ipc_rpm_val,
+ msm_rpm_data.ipc_rpm_reg);
}
/*
@@ -155,26 +180,30 @@
static int msm_rpm_process_ack_interrupt(void)
{
uint32_t ctx_mask_ack;
- uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
+ uint32_t sel_masks_ack[SEL_MASK_SIZE] = {0};
- ctx_mask_ack = msm_rpm_read(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0);
+ ctx_mask_ack = msm_rpm_read(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_ACK_CTX_0));
msm_rpm_read_contiguous(MSM_RPM_PAGE_CTRL,
- MSM_RPM_CTRL_ACK_SEL_0, sel_masks_ack, MSM_RPM_SEL_MASK_SIZE);
+ target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
+ sel_masks_ack, msm_rpm_sel_mask_size);
if (ctx_mask_ack & msm_rpm_get_ctx_mask(MSM_RPM_CTX_NOTIFICATION)) {
struct msm_rpm_notification *n;
int i;
list_for_each_entry(n, &msm_rpm_notifications, list)
- for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
+ for (i = 0; i < msm_rpm_sel_mask_size; i++)
if (sel_masks_ack[i] & n->sel_masks[i]) {
up(&n->sem);
break;
}
msm_rpm_write_contiguous_zeros(MSM_RPM_PAGE_CTRL,
- MSM_RPM_CTRL_ACK_SEL_0, MSM_RPM_SEL_MASK_SIZE);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0, 0);
+ target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
+ msm_rpm_sel_mask_size);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_ACK_CTX_0), 0);
/* Ensure the write is complete before return */
mb();
@@ -191,11 +220,13 @@
for (i = 0; i < msm_rpm_request->count; i++)
msm_rpm_request->req[i].value =
msm_rpm_read(MSM_RPM_PAGE_ACK,
- msm_rpm_request->req[i].id);
+ target_enum(msm_rpm_request->req[i].id));
msm_rpm_write_contiguous_zeros(MSM_RPM_PAGE_CTRL,
- MSM_RPM_CTRL_ACK_SEL_0, MSM_RPM_SEL_MASK_SIZE);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0, 0);
+ target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
+ msm_rpm_sel_mask_size);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_ACK_CTX_0), 0);
/* Ensure the write is complete before return */
mb();
@@ -233,7 +264,7 @@
int rc;
do {
- while (!gic_is_spi_pending(msm_rpm_platform->irq_ack) &&
+ while (!gic_is_spi_pending(msm_rpm_data.irq_ack) &&
msm_rpm_request) {
if (allow_async_completion)
spin_unlock(&msm_rpm_irq_lock);
@@ -246,7 +277,7 @@
break;
rc = msm_rpm_process_ack_interrupt();
- gic_clear_spi_pending(msm_rpm_platform->irq_ack);
+ gic_clear_spi_pending(msm_rpm_data.irq_ack);
} while (rc);
}
@@ -265,7 +296,7 @@
unsigned long flags;
uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
uint32_t ctx_mask_ack = 0;
- uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
+ uint32_t sel_masks_ack[SEL_MASK_SIZE];
int i;
msm_rpm_request_irq_mode.req = req;
@@ -281,13 +312,16 @@
msm_rpm_request = &msm_rpm_request_irq_mode;
for (i = 0; i < count; i++) {
- BUG_ON(req[i].id > MSM_RPM_ID_LAST);
- msm_rpm_write(MSM_RPM_PAGE_REQ, req[i].id, req[i].value);
+ BUG_ON(target_enum(req[i].id) >= MSM_RPM_ID_LAST);
+ msm_rpm_write(MSM_RPM_PAGE_REQ,
+ target_enum(req[i].id), req[i].value);
}
msm_rpm_write_contiguous(MSM_RPM_PAGE_CTRL,
- MSM_RPM_CTRL_REQ_SEL_0, sel_masks, MSM_RPM_SEL_MASK_SIZE);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_REQ_CTX_0, ctx_mask);
+ target_ctrl(MSM_RPM_CTRL_REQ_SEL_0),
+ sel_masks, msm_rpm_sel_mask_size);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_REQ_CTX_0), ctx_mask);
/* Ensure RPM data is written before sending the interrupt */
mb();
@@ -317,11 +351,11 @@
static int msm_rpm_set_exclusive_noirq(int ctx,
uint32_t *sel_masks, struct msm_rpm_iv_pair *req, int count)
{
- unsigned int irq = msm_rpm_platform->irq_ack;
+ unsigned int irq = msm_rpm_data.irq_ack;
unsigned long flags;
uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
uint32_t ctx_mask_ack = 0;
- uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
+ uint32_t sel_masks_ack[SEL_MASK_SIZE];
struct irq_chip *irq_chip = NULL;
int i;
@@ -347,13 +381,16 @@
msm_rpm_request = &msm_rpm_request_poll_mode;
for (i = 0; i < count; i++) {
- BUG_ON(req[i].id > MSM_RPM_ID_LAST);
- msm_rpm_write(MSM_RPM_PAGE_REQ, req[i].id, req[i].value);
+ BUG_ON(target_enum(req[i].id) >= MSM_RPM_ID_LAST);
+ msm_rpm_write(MSM_RPM_PAGE_REQ,
+ target_enum(req[i].id), req[i].value);
}
msm_rpm_write_contiguous(MSM_RPM_PAGE_CTRL,
- MSM_RPM_CTRL_REQ_SEL_0, sel_masks, MSM_RPM_SEL_MASK_SIZE);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_REQ_CTX_0, ctx_mask);
+ target_ctrl(MSM_RPM_CTRL_REQ_SEL_0),
+ sel_masks, msm_rpm_sel_mask_size);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_REQ_CTX_0), ctx_mask);
/* Ensure RPM data is written before sending the interrupt */
mb();
@@ -385,15 +422,11 @@
static int msm_rpm_set_common(
int ctx, struct msm_rpm_iv_pair *req, int count, bool noirq)
{
- uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
+ uint32_t sel_masks[SEL_MASK_SIZE] = {};
int rc;
- if (!msm_rpm_platform) {
- if (cpu_is_apq8064())
- return 0;
- else
- return -ENODEV;
- }
+ if (cpu_is_apq8064())
+ return 0;
if (ctx >= MSM_RPM_CTX_SET_COUNT) {
rc = -EINVAL;
@@ -433,17 +466,13 @@
static int msm_rpm_clear_common(
int ctx, struct msm_rpm_iv_pair *req, int count, bool noirq)
{
- uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
- struct msm_rpm_iv_pair r[MSM_RPM_SEL_MASK_SIZE];
+ uint32_t sel_masks[SEL_MASK_SIZE] = {};
+ struct msm_rpm_iv_pair r[SEL_MASK_SIZE];
int rc;
int i;
- if (!msm_rpm_platform) {
- if (cpu_is_apq8064())
- return 0;
- else
- return -ENODEV;
- }
+ if (cpu_is_apq8064())
+ return 0;
if (ctx >= MSM_RPM_CTX_SET_COUNT) {
rc = -EINVAL;
@@ -460,8 +489,8 @@
}
memset(sel_masks, 0, sizeof(sel_masks));
- sel_masks[msm_rpm_get_sel_mask_reg(MSM_RPM_SEL_INVALIDATE)] |=
- msm_rpm_get_sel_mask(MSM_RPM_SEL_INVALIDATE);
+ sel_masks[msm_rpm_get_sel_mask_reg(msm_rpm_data.sel_invalidate)] |=
+ msm_rpm_get_sel_mask(msm_rpm_data.sel_invalidate);
if (noirq) {
unsigned long flags;
@@ -492,12 +521,14 @@
struct msm_rpm_notif_config *curr_cfg,
struct msm_rpm_notif_config *new_cfg)
{
+ unsigned int sel_notif = msm_rpm_data.sel_notification;
+
if (memcmp(curr_cfg, new_cfg, sizeof(*new_cfg))) {
- uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
+ uint32_t sel_masks[SEL_MASK_SIZE] = {};
int rc;
- sel_masks[msm_rpm_get_sel_mask_reg(MSM_RPM_SEL_NOTIFICATION)]
- |= msm_rpm_get_sel_mask(MSM_RPM_SEL_NOTIFICATION);
+ sel_masks[msm_rpm_get_sel_mask_reg(sel_notif)]
+ |= msm_rpm_get_sel_mask(sel_notif);
rc = msm_rpm_set_exclusive(ctx,
sel_masks, new_cfg->iv, ARRAY_SIZE(new_cfg->iv));
@@ -519,7 +550,7 @@
for (ctx = MSM_RPM_CTX_SET_0; ctx <= MSM_RPM_CTX_SET_SLEEP; ctx++) {
cfg = msm_rpm_notif_cfgs[ctx];
- for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++) {
+ for (i = 0; i < msm_rpm_sel_mask_size; i++) {
configured_iv(&cfg)[i].id =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + i;
configured_iv(&cfg)[i].value = ~0UL;
@@ -581,28 +612,36 @@
int rc;
int i;
- if (!msm_rpm_platform) {
- if (cpu_is_apq8064())
- return 0;
- else
- return -ENODEV;
- }
+ if (cpu_is_apq8064())
+ return 0;
seq_begin = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- MSM_RPM_STATUS_ID_SEQUENCE);
+ target_status(MSM_RPM_STATUS_ID_SEQUENCE));
for (i = 0; i < count; i++) {
- if (status[i].id > MSM_RPM_STATUS_ID_LAST) {
+ int target_status_id;
+
+ if (status[i].id >= MSM_RPM_STATUS_ID_LAST) {
+ pr_err("%s(): Status ID beyond limits\n", __func__);
+ rc = -EINVAL;
+ goto get_status_exit;
+ }
+
+ target_status_id = target_status(status[i].id);
+ if (target_status_id >= MSM_RPM_STATUS_ID_LAST) {
+ pr_err("%s(): Status id %d not defined for target\n",
+ __func__,
+ target_status_id);
rc = -EINVAL;
goto get_status_exit;
}
status[i].value = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- status[i].id);
+ target_status_id);
}
seq_end = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- MSM_RPM_STATUS_ID_SEQUENCE);
+ target_status(MSM_RPM_STATUS_ID_SEQUENCE));
rc = (seq_begin != seq_end || (seq_begin & 0x01)) ? -EBUSY : 0;
@@ -729,12 +768,8 @@
int rc;
int i;
- if (!msm_rpm_platform) {
- if (cpu_is_apq8064())
- return 0;
- else
- return -ENODEV;
- }
+ if (cpu_is_apq8064())
+ return 0;
INIT_LIST_HEAD(&n->list);
rc = msm_rpm_fill_sel_masks(n->sel_masks, req, count);
@@ -757,7 +792,7 @@
ctx = MSM_RPM_CTX_SET_0;
cfg = msm_rpm_notif_cfgs[ctx];
- for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
+ for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value |= n->sel_masks[i];
msm_rpm_update_notification(ctx, &msm_rpm_notif_cfgs[ctx], &cfg);
@@ -788,12 +823,8 @@
int rc;
int i;
- if (!msm_rpm_platform) {
- if (cpu_is_apq8064())
- return 0;
- else
- return -ENODEV;
- }
+ if (cpu_is_apq8064())
+ return 0;
rc = mutex_lock_interruptible(&msm_rpm_mutex);
if (rc)
@@ -802,13 +833,13 @@
ctx = MSM_RPM_CTX_SET_0;
cfg = msm_rpm_notif_cfgs[ctx];
- for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
+ for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value = 0;
spin_lock_irqsave(&msm_rpm_irq_lock, flags);
list_del(&n->list);
list_for_each_entry(n, &msm_rpm_notifications, list)
- for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
+ for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value |= n->sel_masks[i];
spin_unlock_irqrestore(&msm_rpm_irq_lock, flags);
@@ -826,7 +857,7 @@
struct kobj_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%u.%u.%u\n",
- RPM_MAJOR_VER, RPM_MINOR_VER, RPM_BUILD_VER);
+ msm_rpm_data.ver[0], msm_rpm_data.ver[1], msm_rpm_data.ver[2]);
}
static ssize_t fw_version_show(struct kobject *kobj,
@@ -869,18 +900,49 @@
},
};
-static void __init msm_rpm_populate_map(void)
+static void __init msm_rpm_populate_map(struct msm_rpm_platform_data *data)
{
- int i, k;
+ int i, j;
+ struct msm_rpm_map_data *src = NULL;
+ struct msm_rpm_map_data *dst = NULL;
- for (i = 0; i < ARRAY_SIZE(msm_rpm_map); i++)
- msm_rpm_map[i] = MSM_RPM_SEL_LAST + 1;
+ for (i = 0; i < MSM_RPM_ID_LAST;) {
+ src = &data->target_id[i];
+ dst = &msm_rpm_data.target_id[i];
- for (i = 0; i < rpm_map_data_size; i++) {
- struct msm_rpm_map_data *raw_data = &rpm_map_data[i];
+ dst->id = MSM_RPM_ID_LAST;
+ dst->sel = msm_rpm_data.sel_last + 1;
- for (k = 0; k < raw_data->count; k++)
- msm_rpm_map[raw_data->id + k] = raw_data->sel;
+ /*
+ * copy the target specific id of the current and also of
+ * all the #count id's that follow the current.
+ * [MSM_RPM_ID_PM8921_S1_0] = { MSM_RPM_8960_ID_PM8921_S1_0,
+ * MSM_RPM_8960_SEL_PM8921_S1,
+ * 2},
+ * [MSM_RPM_ID_PM8921_S1_1] = { 0, 0, 0 },
+ * should translate to
+ * [MSM_RPM_ID_PM8921_S1_0] = { MSM_RPM_8960_ID_PM8921_S1_0,
+ * MSM_RPM_8960_SEL_PM8921,
+ * 2 },
+ * [MSM_RPM_ID_PM8921_S1_1] = { MSM_RPM_8960_ID_PM8921_S1_0 + 1,
+ * MSM_RPM_8960_SEL_PM8921,
+ * 0 },
+ */
+ for (j = 0; j < src->count; j++) {
+ dst = &msm_rpm_data.target_id[i + j];
+ dst->id = src->id + j;
+ dst->sel = src->sel;
+ }
+
+ i += (src->count) ? src->count : 1;
+ }
+
+ for (i = 0; i < MSM_RPM_STATUS_ID_LAST; i++) {
+ if (data->target_status[i] & MSM_RPM_STATUS_ID_VALID)
+ msm_rpm_data.target_status[i] &=
+ ~MSM_RPM_STATUS_ID_VALID;
+ else
+ msm_rpm_data.target_status[i] = MSM_RPM_STATUS_ID_LAST;
}
}
@@ -892,33 +954,37 @@
if (cpu_is_apq8064())
return 0;
- msm_rpm_platform = data;
+ memcpy(&msm_rpm_data, data, sizeof(struct msm_rpm_platform_data));
+ msm_rpm_sel_mask_size = msm_rpm_data.sel_last / 32 + 1;
+ BUG_ON(SEL_MASK_SIZE < msm_rpm_sel_mask_size);
fw_major = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- MSM_RPM_STATUS_ID_VERSION_MAJOR);
+ target_status(MSM_RPM_STATUS_ID_VERSION_MAJOR));
fw_minor = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- MSM_RPM_STATUS_ID_VERSION_MINOR);
+ target_status(MSM_RPM_STATUS_ID_VERSION_MINOR));
fw_build = msm_rpm_read(MSM_RPM_PAGE_STATUS,
- MSM_RPM_STATUS_ID_VERSION_BUILD);
+ target_status(MSM_RPM_STATUS_ID_VERSION_BUILD));
pr_info("%s: RPM firmware %u.%u.%u\n", __func__,
fw_major, fw_minor, fw_build);
- if (fw_major != RPM_MAJOR_VER) {
+ if (fw_major != msm_rpm_data.ver[0]) {
pr_err("%s: RPM version %u.%u.%u incompatible with "
"this driver version %u.%u.%u\n", __func__,
fw_major, fw_minor, fw_build,
- RPM_MAJOR_VER, RPM_MINOR_VER, RPM_BUILD_VER);
+ msm_rpm_data.ver[0],
+ msm_rpm_data.ver[1],
+ msm_rpm_data.ver[2]);
return -EFAULT;
}
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_MAJOR,
- RPM_MAJOR_VER);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_MINOR,
- RPM_MINOR_VER);
- msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_BUILD,
- RPM_BUILD_VER);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_VERSION_MAJOR), msm_rpm_data.ver[0]);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_VERSION_MINOR), msm_rpm_data.ver[1]);
+ msm_rpm_write(MSM_RPM_PAGE_CTRL,
+ target_ctrl(MSM_RPM_CTRL_VERSION_BUILD), msm_rpm_data.ver[2]);
- irq = msm_rpm_platform->irq_ack;
+ irq = data->irq_ack;
rc = request_irq(irq, msm_rpm_ack_interrupt,
IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
@@ -936,7 +1002,7 @@
return rc;
}
- msm_rpm_populate_map();
+ msm_rpm_populate_map(data);
return platform_driver_register(&msm_rpm_platform_driver);
}
diff --git a/arch/arm/mach-msm/rpm_resources.c b/arch/arm/mach-msm/rpm_resources.c
index 3568070..609528c 100644
--- a/arch/arm/mach-msm/rpm_resources.c
+++ b/arch/arm/mach-msm/rpm_resources.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -65,6 +65,10 @@
static ssize_t msm_rpmrs_resource_attr_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count);
+static int vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_LAST];
+static int vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_LAST];
+static int vdd_mask;
+
#define MSM_RPMRS_MAX_RS_REGISTER_COUNT 2
#define RPMRS_ATTR(_name) \
@@ -86,7 +90,6 @@
};
static struct msm_rpmrs_resource msm_rpmrs_pxo = {
- .rs[0].id = MSM_RPMRS_ID_PXO_CLK,
.size = 1,
.name = "pxo",
.beyond_limits = msm_rpmrs_pxo_beyond_limits,
@@ -96,7 +99,6 @@
};
static struct msm_rpmrs_resource msm_rpmrs_l2_cache = {
- .rs[0].id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL,
.size = 1,
.name = "L2_cache",
.beyond_limits = msm_rpmrs_l2_cache_beyond_limits,
@@ -106,8 +108,6 @@
};
static struct msm_rpmrs_resource msm_rpmrs_vdd_mem = {
- .rs[0].id = MSM_RPMRS_ID_VDD_MEM_0,
- .rs[1].id = MSM_RPMRS_ID_VDD_MEM_1,
.size = 2,
.name = "vdd_mem",
.beyond_limits = msm_rpmrs_vdd_mem_beyond_limits,
@@ -117,8 +117,6 @@
};
static struct msm_rpmrs_resource msm_rpmrs_vdd_dig = {
- .rs[0].id = MSM_RPMRS_ID_VDD_DIG_0,
- .rs[1].id = MSM_RPMRS_ID_VDD_DIG_1,
.size = 2,
.name = "vdd_dig",
.beyond_limits = msm_rpmrs_vdd_dig_beyond_limits,
@@ -128,7 +126,6 @@
};
static struct msm_rpmrs_resource msm_rpmrs_rpm_ctl = {
- .rs[0].id = MSM_RPMRS_ID_RPM_CTL,
.size = 1,
.name = "rpm_ctl",
.beyond_limits = NULL,
@@ -145,12 +142,12 @@
&msm_rpmrs_rpm_ctl,
};
-static uint32_t msm_rpmrs_buffer[MSM_RPM_ID_LAST + 1];
-static DECLARE_BITMAP(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
-static DECLARE_BITMAP(msm_rpmrs_listed, MSM_RPM_ID_LAST + 1);
+static uint32_t msm_rpmrs_buffer[MSM_RPM_ID_LAST];
+static DECLARE_BITMAP(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
+static DECLARE_BITMAP(msm_rpmrs_listed, MSM_RPM_ID_LAST);
static DEFINE_SPINLOCK(msm_rpmrs_lock);
-#define MSM_RPMRS_VDD(v) ((v) & (MSM_RPMRS_VDD_MASK))
+#define MSM_RPMRS_VDD(v) ((v) & (vdd_mask))
/******************************************************************************
* Attribute Definitions
@@ -290,20 +287,19 @@
uint32_t buffered_value = msm_rpmrs_buffer[rs->rs[0].id];
if (rs->enable_low_power == 0)
- vdd_mem = MSM_RPMRS_VDD_MEM_ACTIVE;
+ vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_ACTIVE];
else if (rs->enable_low_power == 1)
- vdd_mem = MSM_RPMRS_VDD_MEM_RET_HIGH;
+ vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_RET_HIGH];
else
- vdd_mem = MSM_RPMRS_VDD_MEM_RET_LOW;
+ vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_RET_LOW];
if (MSM_RPMRS_VDD(buffered_value) > MSM_RPMRS_VDD(vdd_mem))
- vdd_mem = buffered_value;
+ vdd_mem = MSM_RPMRS_VDD(buffered_value);
} else {
- vdd_mem = MSM_RPMRS_VDD_MEM_ACTIVE;
+ vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_ACTIVE];
}
- return MSM_RPMRS_VDD(vdd_mem) >
- MSM_RPMRS_VDD(limits->vdd_mem_upper_bound);
+ return vdd_mem > vdd_mem_vlevels[limits->vdd_mem_upper_bound];
}
static void msm_rpmrs_aggregate_vdd_mem(struct msm_rpmrs_limits *limits)
@@ -313,9 +309,9 @@
if (test_bit(rs->rs[0].id, msm_rpmrs_buffered)) {
rs->rs[0].value = *buf;
- if (MSM_RPMRS_VDD(limits->vdd_mem) > MSM_RPMRS_VDD(*buf)) {
- *buf &= ~MSM_RPMRS_VDD_MASK;
- *buf |= MSM_RPMRS_VDD(limits->vdd_mem);
+ if (vdd_mem_vlevels[limits->vdd_mem] > MSM_RPMRS_VDD(*buf)) {
+ *buf &= ~vdd_mask;
+ *buf |= vdd_mem_vlevels[limits->vdd_mem];
}
if (MSM_RPMRS_DEBUG_OUTPUT & msm_rpmrs_debug_mask)
@@ -341,20 +337,19 @@
uint32_t buffered_value = msm_rpmrs_buffer[rs->rs[0].id];
if (rs->enable_low_power == 0)
- vdd_dig = MSM_RPMRS_VDD_DIG_ACTIVE;
+ vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_ACTIVE];
else if (rs->enable_low_power == 1)
- vdd_dig = MSM_RPMRS_VDD_DIG_RET_HIGH;
+ vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH];
else
- vdd_dig = MSM_RPMRS_VDD_DIG_RET_LOW;
+ vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_LOW];
if (MSM_RPMRS_VDD(buffered_value) > MSM_RPMRS_VDD(vdd_dig))
- vdd_dig = buffered_value;
+ vdd_dig = MSM_RPMRS_VDD(buffered_value);
} else {
- vdd_dig = MSM_RPMRS_VDD_DIG_ACTIVE;
+ vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_ACTIVE];
}
- return MSM_RPMRS_VDD(vdd_dig) >
- MSM_RPMRS_VDD(limits->vdd_dig_upper_bound);
+ return vdd_dig > vdd_dig_vlevels[limits->vdd_dig_upper_bound];
}
static void msm_rpmrs_aggregate_vdd_dig(struct msm_rpmrs_limits *limits)
@@ -364,9 +359,9 @@
if (test_bit(rs->rs[0].id, msm_rpmrs_buffered)) {
rs->rs[0].value = *buf;
- if (MSM_RPMRS_VDD(limits->vdd_dig) > MSM_RPMRS_VDD(*buf)) {
- *buf &= ~MSM_RPMRS_VDD_MASK;
- *buf |= MSM_RPMRS_VDD(limits->vdd_dig);
+ if (vdd_dig_vlevels[limits->vdd_dig] > MSM_RPMRS_VDD(*buf)) {
+ *buf &= ~vdd_mask;
+ *buf |= vdd_dig_vlevels[limits->vdd_dig];
}
@@ -392,7 +387,8 @@
bool irqs_detect, bool gpio_detect)
{
- if (limits->vdd_dig_upper_bound <= MSM_RPMRS_VDD_DIG_RET_HIGH)
+ if (vdd_dig_vlevels[limits->vdd_dig_upper_bound] <=
+ vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH])
return irqs_detect;
if (limits->pxo == MSM_RPMRS_PXO_OFF)
@@ -404,7 +400,8 @@
static bool msm_rpmrs_use_mpm(struct msm_rpmrs_limits *limits)
{
return (limits->pxo == MSM_RPMRS_PXO_OFF) ||
- (limits->vdd_dig <= MSM_RPMRS_VDD_DIG_RET_HIGH);
+ (vdd_dig_vlevels[limits->vdd_dig] <=
+ vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH]);
}
static void msm_rpmrs_update_levels(void)
@@ -428,6 +425,7 @@
break;
}
}
+
}
}
@@ -443,7 +441,7 @@
int i;
for (i = 0; i < count; i++)
- if (req[i].id > MSM_RPM_ID_LAST)
+ if (req[i].id >= MSM_RPM_ID_LAST)
return -EINVAL;
for (i = 0, listed = false; i < count; i++) {
@@ -476,7 +474,7 @@
int i;
for (i = 0; i < count; i++)
- if (req[i].id > MSM_RPM_ID_LAST)
+ if (req[i].id >= MSM_RPM_ID_LAST)
return -EINVAL;
for (i = 0, listed = false; i < count; i++) {
@@ -557,7 +555,7 @@
msm_rpmrs_resources[i]->aggregate(limits);
}
- count = bitmap_weight(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
+ count = bitmap_weight(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
req = kmalloc(sizeof(*req) * count, GFP_ATOMIC);
if (!req) {
@@ -566,9 +564,9 @@
}
count = 0;
- i = find_first_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
+ i = find_first_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
- while (i < MSM_RPM_ID_LAST + 1) {
+ while (i < MSM_RPM_ID_LAST) {
if (MSM_RPMRS_DEBUG_OUTPUT & msm_rpmrs_debug_mask)
pr_info("%s: reg %d: 0x%x\n",
__func__, i, msm_rpmrs_buffer[i]);
@@ -577,7 +575,7 @@
req[count].value = msm_rpmrs_buffer[i];
count++;
- i = find_next_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST+1, i+1);
+ i = find_next_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST, i + 1);
}
rc = msm_rpm_set_noirq(MSM_RPM_CTX_SET_SLEEP, req, count);
@@ -587,7 +585,7 @@
goto flush_buffer_restore;
bitmap_and(msm_rpmrs_buffered,
- msm_rpmrs_buffered, msm_rpmrs_listed, MSM_RPM_ID_LAST + 1);
+ msm_rpmrs_buffered, msm_rpmrs_listed, MSM_RPM_ID_LAST);
flush_buffer_restore:
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
@@ -664,7 +662,8 @@
spin_lock_irqsave(&msm_rpmrs_lock, flags);
/* special case active-set signal for MSM_RPMRS_ID_RPM_CTL */
- if (GET_RS_FROM_ATTR(attr)->rs[0].id == MSM_RPMRS_ID_RPM_CTL)
+ if (GET_RS_FROM_ATTR(attr)->rs[0].id ==
+ msm_rpmrs_rpm_ctl.rs[0].id)
temp = GET_RS_FROM_ATTR(attr)->rs[0].value;
else
temp = GET_RS_FROM_ATTR(attr)->enable_low_power;
@@ -698,9 +697,10 @@
GET_RS_FROM_ATTR(attr)->enable_low_power = temp;
/* special case active-set signal for MSM_RPMRS_ID_RPM_CTL */
- if (GET_RS_FROM_ATTR(attr)->rs[0].id == MSM_RPMRS_ID_RPM_CTL) {
+ if (GET_RS_FROM_ATTR(attr)->rs[0].id ==
+ msm_rpmrs_rpm_ctl.rs[0].id) {
struct msm_rpm_iv_pair req;
- req.id = MSM_RPMRS_ID_RPM_CTL;
+ req.id = msm_rpmrs_rpm_ctl.rs[0].id;
req.value = GET_RS_FROM_ATTR(attr)->enable_low_power;
GET_RS_FROM_ATTR(attr)->rs[0].value = req.value;
@@ -855,7 +855,7 @@
spin_lock_irqsave(&msm_rpmrs_lock, flags);
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
rs = msm_rpmrs_resources[i];
- if (rs->rs[0].id < MSM_RPM_ID_LAST + 1)
+ if (rs->rs[0].id < MSM_RPM_ID_LAST)
pr_info("%s: resource %s: buffered %d, value 0x%x\n",
__func__, rs->name,
test_bit(rs->rs[0].id, msm_rpmrs_buffered),
@@ -978,14 +978,51 @@
.notifier_call = rpmrs_cpu_callback,
};
-int __init msm_rpmrs_levels_init(struct msm_rpmrs_level *levels, int size)
+int __init msm_rpmrs_levels_init(struct msm_rpmrs_platform_data *data)
{
- msm_rpmrs_levels = kzalloc(sizeof(struct msm_rpmrs_level) * size,
- GFP_KERNEL);
+ int i, k;
+ struct msm_rpmrs_level *levels = data->levels;
+
+ msm_rpmrs_level_count = data->num_levels;
+
+ msm_rpmrs_levels = kzalloc(sizeof(struct msm_rpmrs_level) *
+ msm_rpmrs_level_count, GFP_KERNEL);
if (!msm_rpmrs_levels)
return -ENOMEM;
- msm_rpmrs_level_count = size;
- memcpy(msm_rpmrs_levels, levels, size * sizeof(struct msm_rpmrs_level));
+
+ memcpy(msm_rpmrs_levels, levels,
+ msm_rpmrs_level_count * sizeof(struct msm_rpmrs_level));
+
+ memcpy(vdd_dig_vlevels, data->vdd_dig_levels,
+ (MSM_RPMRS_VDD_DIG_MAX + 1) * sizeof(vdd_dig_vlevels[0]));
+
+ memcpy(vdd_mem_vlevels, data->vdd_mem_levels,
+ (MSM_RPMRS_VDD_MEM_MAX + 1) * sizeof(vdd_mem_vlevels[0]));
+ vdd_mask = data->vdd_mask;
+
+ msm_rpmrs_pxo.rs[0].id = data->rpmrs_target_id[MSM_RPMRS_ID_PXO_CLK];
+ msm_rpmrs_l2_cache.rs[0].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_L2_CACHE_CTL];
+ msm_rpmrs_vdd_mem.rs[0].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_VDD_MEM_0];
+ msm_rpmrs_vdd_mem.rs[1].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_VDD_MEM_1];
+ msm_rpmrs_vdd_dig.rs[0].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_VDD_DIG_0];
+ msm_rpmrs_vdd_dig.rs[1].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_VDD_DIG_1];
+ msm_rpmrs_rpm_ctl.rs[0].id =
+ data->rpmrs_target_id[MSM_RPMRS_ID_RPM_CTL];
+
+ /* Initialize listed bitmap for valid resource IDs */
+ for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
+ for (k = 0; k < msm_rpmrs_resources[i]->size; k++)
+ if (msm_rpmrs_resources[i]->rs[k].id >=
+ MSM_RPM_ID_LAST)
+ continue;
+ set_bit(msm_rpmrs_resources[i]->rs[k].id,
+ msm_rpmrs_listed);
+ }
return 0;
}
@@ -1001,7 +1038,7 @@
BUG_ON(!msm_rpmrs_levels);
if (cpu_is_msm8x60()) {
- req.id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL;
+ req.id = msm_rpmrs_l2_cache.rs[0].id;
req.value = 1;
rc = msm_rpm_set(MSM_RPM_CTX_SET_0, &req, 1);
@@ -1011,7 +1048,7 @@
goto init_exit;
}
- req.id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL;
+ req.id = msm_rpmrs_l2_cache.rs[0].id;
req.value = 0;
rc = msm_rpmrs_set(MSM_RPM_CTX_SET_SLEEP, &req, 1);
@@ -1029,21 +1066,6 @@
}
device_initcall(msm_rpmrs_init);
-static int __init msm_rpmrs_early_init(void)
-{
- int i, k;
-
- /* Initialize listed bitmap for valid resource IDs */
- for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
- for (k = 0; k < msm_rpmrs_resources[i]->size; k++)
- set_bit(msm_rpmrs_resources[i]->rs[k].id,
- msm_rpmrs_listed);
- }
-
- return 0;
-}
-early_initcall(msm_rpmrs_early_init);
-
static int __init msm_rpmrs_l2_init(void)
{
if (cpu_is_msm8960() || cpu_is_msm8930()) {
diff --git a/arch/arm/mach-msm/rpm_resources.h b/arch/arm/mach-msm/rpm_resources.h
index e849208..da9d3ff 100644
--- a/arch/arm/mach-msm/rpm_resources.h
+++ b/arch/arm/mach-msm/rpm_resources.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -17,17 +17,15 @@
#include <mach/rpm.h>
#include <mach/pm.h>
-
-struct msm_rpmrs_limits {
- uint32_t pxo;
- uint32_t l2_cache;
- uint32_t vdd_mem_upper_bound;
- uint32_t vdd_mem;
- uint32_t vdd_dig_upper_bound;
- uint32_t vdd_dig;
-
- uint32_t latency_us[NR_CPUS];
- uint32_t power[NR_CPUS];
+enum {
+ MSM_RPMRS_ID_PXO_CLK = 0,
+ MSM_RPMRS_ID_L2_CACHE_CTL = 1,
+ MSM_RPMRS_ID_VDD_DIG_0 = 2,
+ MSM_RPMRS_ID_VDD_DIG_1 = 3,
+ MSM_RPMRS_ID_VDD_MEM_0 = 4,
+ MSM_RPMRS_ID_VDD_MEM_1 = 5,
+ MSM_RPMRS_ID_RPM_CTL = 6,
+ MSM_RPMRS_ID_LAST,
};
enum {
@@ -47,6 +45,22 @@
MSM_RPMRS_MASK_RPM_CTL_MULTI_TIER = 2,
};
+enum {
+ MSM_RPMRS_VDD_MEM_RET_LOW = 0,
+ MSM_RPMRS_VDD_MEM_RET_HIGH = 1,
+ MSM_RPMRS_VDD_MEM_ACTIVE = 2,
+ MSM_RPMRS_VDD_MEM_MAX = 3,
+ MSM_RPMRS_VDD_MEM_LAST,
+};
+
+enum {
+ MSM_RPMRS_VDD_DIG_RET_LOW = 0,
+ MSM_RPMRS_VDD_DIG_RET_HIGH = 1,
+ MSM_RPMRS_VDD_DIG_ACTIVE = 2,
+ MSM_RPMRS_VDD_DIG_MAX = 3,
+ MSM_RPMRS_VDD_DIG_LAST,
+};
+
#define MSM_RPMRS_LIMITS(_pxo, _l2, _vdd_upper_b, _vdd) { \
MSM_RPMRS_PXO_##_pxo, \
MSM_RPMRS_L2_CACHE_##_l2, \
@@ -57,6 +71,18 @@
{0}, {0}, \
}
+struct msm_rpmrs_limits {
+ uint32_t pxo;
+ uint32_t l2_cache;
+ uint32_t vdd_mem_upper_bound;
+ uint32_t vdd_mem;
+ uint32_t vdd_dig_upper_bound;
+ uint32_t vdd_dig;
+
+ uint32_t latency_us[NR_CPUS];
+ uint32_t power[NR_CPUS];
+};
+
struct msm_rpmrs_level {
enum msm_pm_sleep_mode sleep_mode;
struct msm_rpmrs_limits rs_limits;
@@ -67,6 +93,15 @@
uint32_t time_overhead_us;
};
+struct msm_rpmrs_platform_data {
+ struct msm_rpmrs_level *levels;
+ unsigned int num_levels;
+ unsigned int vdd_mem_levels[MSM_RPMRS_VDD_MEM_LAST];
+ unsigned int vdd_dig_levels[MSM_RPMRS_VDD_DIG_LAST];
+ unsigned int vdd_mask;
+ unsigned int rpmrs_target_id[MSM_RPMRS_ID_LAST];
+};
+
int msm_rpmrs_set(int ctx, struct msm_rpm_iv_pair *req, int count);
int msm_rpmrs_set_noirq(int ctx, struct msm_rpm_iv_pair *req, int count);
int msm_rpmrs_set_bits_noirq(int ctx, struct msm_rpm_iv_pair *req, int count,
@@ -112,6 +147,6 @@
void msm_rpmrs_exit_sleep(struct msm_rpmrs_limits *limits, bool from_idle,
bool notify_rpm, bool collapsed);
-int msm_rpmrs_levels_init(struct msm_rpmrs_level *levels, int size);
+int msm_rpmrs_levels_init(struct msm_rpmrs_platform_data *data);
#endif /* __ARCH_ARM_MACH_MSM_RPM_RESOURCES_H */
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 514f817..0bc3b0e 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -1459,18 +1459,16 @@
struct smd_channel *ch;
struct smd_channel *index;
+ mutex_lock(&smd_creation_mutex);
spin_lock_irqsave(&smd_lock, flags);
list_for_each_entry_safe(ch, index, &smd_ch_to_close_list, ch_list) {
list_del(&ch->ch_list);
- spin_unlock_irqrestore(&smd_lock, flags);
- mutex_lock(&smd_creation_mutex);
list_add(&ch->ch_list, &smd_ch_closed_list);
- mutex_unlock(&smd_creation_mutex);
ch->notify(ch->priv, SMD_EVENT_REOPEN_READY);
ch->notify = do_nothing_notify;
- spin_lock_irqsave(&smd_lock, flags);
}
spin_unlock_irqrestore(&smd_lock, flags);
+ mutex_unlock(&smd_creation_mutex);
}
struct smd_channel *smd_get_channel(const char *name, uint32_t type)
@@ -1506,8 +1504,37 @@
SMD_DBG("smd_open('%s', %p, %p)\n", name, priv, notify);
ch = smd_get_channel(name, edge);
- if (!ch)
- return -ENODEV;
+ if (!ch) {
+ unsigned long flags;
+ struct smd_channel *ch;
+
+ /* check closing list for port */
+ spin_lock_irqsave(&smd_lock, flags);
+ list_for_each_entry(ch, &smd_ch_closing_list, ch_list) {
+ if (!strncmp(name, ch->name, 20) &&
+ (edge == ch->type)) {
+ /* channel exists, but is being closed */
+ spin_unlock_irqrestore(&smd_lock, flags);
+ return -EAGAIN;
+ }
+ }
+
+ /* check closing workqueue list for port */
+ list_for_each_entry(ch, &smd_ch_to_close_list, ch_list) {
+ if (!strncmp(name, ch->name, 20) &&
+ (edge == ch->type)) {
+ /* channel exists, but is being closed */
+ spin_unlock_irqrestore(&smd_lock, flags);
+ return -EAGAIN;
+ }
+ }
+ spin_unlock_irqrestore(&smd_lock, flags);
+
+ /* one final check to handle closing->closed race condition */
+ ch = smd_get_channel(name, edge);
+ if (!ch)
+ return -ENODEV;
+ }
if (notify == 0)
notify = do_nothing_notify;
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 4e78152..dbd1bd4 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -33,7 +33,12 @@
#define EVENT_CHANNEL "APPS_RIVA_BT_CMD"
#define DATA_CHANNEL "APPS_RIVA_BT_ACL"
-#define RX_Q_MONITOR (1) /* 1 milli second */
+/* release wakelock in 500ms, not immediately, because higher layers
+ * don't always take wakelocks when they should
+ * This is derived from the implementation for UART transport
+ */
+
+#define RX_Q_MONITOR (500) /* 500 milli second */
static int hcismd_set;
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 60bd232..1ef71a4 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -621,7 +621,7 @@
struct kgsl_device *device = (struct kgsl_device *) data;
KGSL_PWR_INFO(device, "idle timer expired device %d\n", device->id);
- if (device->requested_state == KGSL_STATE_NONE) {
+ if (device->requested_state != KGSL_STATE_SUSPEND) {
if (device->pwrctrl.restore_slumber)
kgsl_pwrctrl_request_state(device, KGSL_STATE_SLUMBER);
else
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index ff0e00d..46e03b9 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -98,6 +98,7 @@
struct hci_fm_ssbi_req ssbi_data_accs;
struct hci_fm_ssbi_peek ssbi_peek_reg;
struct hci_fm_sig_threshold_rsp sig_th;
+ struct hci_fm_ch_det_threshold ch_det_threshold;
};
static struct video_device *priv_videodev;
@@ -427,6 +428,38 @@
.minimum = -128,
.maximum = 127,
},
+ {
+ .id = V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Intf High Threshold",
+ .minimum = 0,
+ .maximum = 0xFF,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Intf low Threshold",
+ .minimum = 0,
+ .maximum = 0xFF,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_PRIVATE_SINR_THRESHOLD,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "SINR Threshold",
+ .minimum = -128,
+ .maximum = 127,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_PRIVATE_SINR_SAMPLES,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "SINR samples",
+ .minimum = 1,
+ .maximum = 0xFF,
+ .default_value = 0,
+ },
};
static void iris_q_event(struct iris_device *radio,
@@ -1046,6 +1079,25 @@
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
+static int hci_fm_set_ch_det_th(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ struct hci_fm_ch_det_threshold *ch_det_th =
+ (struct hci_fm_ch_det_threshold *) param;
+ u16 opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ HCI_OCF_FM_SET_CH_DET_THRESHOLD);
+ return radio_hci_send_cmd(hdev, opcode, sizeof((*ch_det_th)),
+ ch_det_th);
+}
+
+static int hci_fm_get_ch_det_th(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ u16 opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ HCI_OCF_FM_GET_CH_DET_THRESHOLD);
+ return radio_hci_send_cmd(hdev, opcode, 0, NULL);
+}
+
static int radio_hci_err(__u16 code)
{
switch (code) {
@@ -1369,6 +1421,16 @@
return ret;
}
+static int hci_set_ch_det_thresholds_req(struct hci_fm_ch_det_threshold *arg,
+ struct radio_hci_dev *hdev)
+{
+ int ret = 0;
+ struct hci_fm_ch_det_threshold *ch_det_threshold = arg;
+ ret = radio_hci_request(hdev, hci_fm_set_ch_det_th,
+ (unsigned long)ch_det_threshold, RADIO_HCI_TIMEOUT);
+ return ret;
+}
+
static int hci_fm_set_cal_req_proc(struct radio_hci_dev *hdev,
unsigned long param)
{
@@ -1482,6 +1544,10 @@
ret = radio_hci_request(hdev, hci_get_fm_trans_conf_req, arg,
msecs_to_jiffies(RADIO_HCI_TIMEOUT));
break;
+ case HCI_FM_GET_DET_CH_TH_CMD:
+ ret = radio_hci_request(hdev, hci_fm_get_ch_det_th, arg,
+ msecs_to_jiffies(RADIO_HCI_TIMEOUT));
+ break;
default:
ret = -EINVAL;
break;
@@ -1786,6 +1852,21 @@
radio_hci_req_complete(hdev, rsp.status);
}
+
+static void hci_cc_get_ch_det_threshold_rsp(struct radio_hci_dev *hdev,
+ struct sk_buff *skb)
+{
+ struct iris_device *radio = video_get_drvdata(video_get_dev());
+ u8 status = skb->data[0];
+ if (status) {
+ FMDERR("status = %d", status);
+ return;
+ }
+ memcpy(&radio->ch_det_threshold, &skb->data[1],
+ sizeof(struct hci_fm_ch_det_threshold));
+ radio_hci_req_complete(hdev, status);
+}
+
static inline void hci_cmd_complete_event(struct radio_hci_dev *hdev,
struct sk_buff *skb)
{
@@ -1818,6 +1899,7 @@
case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_GRP_PROCESS):
case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_EN_WAN_AVD_CTRL):
case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_EN_NOTCH_CTRL):
+ case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_SET_CH_DET_THRESHOLD):
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_ENABLE_TRANS_REQ):
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_DISABLE_TRANS_REQ):
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_RT_REQ):
@@ -1886,6 +1968,9 @@
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_GET_TRANS_CONF_REQ):
hci_cc_fm_trans_get_conf_rsp(hdev, skb);
break;
+ case hci_recv_ctrl_cmd_op_pack(HCI_OCF_FM_GET_CH_DET_THRESHOLD):
+ hci_cc_get_ch_det_threshold_rsp(hdev, skb);
+ break;
default:
FMDERR("%s opcode 0x%x", hdev->name, opcode);
break;
@@ -2522,6 +2607,38 @@
} else
retval = -EINVAL;
+ case V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Get High det threshold failed %x", retval);
+ return retval;
+ }
+ ctrl->value = radio->ch_det_threshold.high_th;
+ break;
+ case V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Get Low det threshold failed %x", retval);
+ return retval;
+ }
+ ctrl->value = radio->ch_det_threshold.low_th;
+ break;
+ case V4L2_CID_PRIVATE_SINR_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Get SINR threshold failed %x", retval);
+ return retval;
+ }
+ ctrl->value = radio->ch_det_threshold.sinr;
+ break;
+ case V4L2_CID_PRIVATE_SINR_SAMPLES:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Get SINR samples failed %x", retval);
+ return retval;
+ }
+
+ ctrl->value = radio->ch_det_threshold.sinr_samples;
break;
default:
retval = -EINVAL;
@@ -2983,6 +3100,66 @@
temp_val = ctrl->value;
retval = hci_set_notch_filter(&temp_val, radio->fm_hdev);
break;
+ case V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to get chnl det thresholds %d", retval);
+ return retval;
+ }
+ radio->ch_det_threshold.high_th = ctrl->value;
+ retval = hci_set_ch_det_thresholds_req(&radio->ch_det_threshold,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to set High det threshold %d ", retval);
+ return retval;
+ }
+ break;
+
+ case V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to get chnl det thresholds %d", retval);
+ return retval;
+ }
+ radio->ch_det_threshold.low_th = ctrl->value;
+ retval = hci_set_ch_det_thresholds_req(&radio->ch_det_threshold,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to Set Low det threshold %d", retval);
+ return retval;
+ }
+ break;
+
+ case V4L2_CID_PRIVATE_SINR_THRESHOLD:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to get chnl det thresholds %d", retval);
+ return retval;
+ }
+ radio->ch_det_threshold.sinr = ctrl->value;
+ retval = hci_set_ch_det_thresholds_req(&radio->ch_det_threshold,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to set SINR threshold %d", retval);
+ return retval;
+ }
+ break;
+
+ case V4L2_CID_PRIVATE_SINR_SAMPLES:
+ retval = hci_cmd(HCI_FM_GET_DET_CH_TH_CMD, radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to get chnl det thresholds %d", retval);
+ return retval;
+ }
+ radio->ch_det_threshold.sinr_samples = ctrl->value;
+ retval = hci_set_ch_det_thresholds_req(&radio->ch_det_threshold,
+ radio->fm_hdev);
+ if (retval < 0) {
+ FMDERR("Failed to set SINR samples %d", retval);
+ return retval;
+ }
+ break;
+
case V4L2_CID_PRIVATE_IRIS_SRCH_ALGORITHM:
case V4L2_CID_PRIVATE_IRIS_SET_AUDIO_PATH:
/*
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index 8f09b6a..1c4f616 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -3966,6 +3966,9 @@
if (i == TAVARUA_BUF_RAW_RDS)
kfifo_alloc_rc = kfifo_alloc(&radio->data_buf[i],
rds_buf*3, GFP_KERNEL);
+ else if (i == TAVARUA_BUF_RT_RDS)
+ kfifo_alloc_rc = kfifo_alloc(&radio->data_buf[i],
+ STD_BUF_SIZE * 2, GFP_KERNEL);
else
kfifo_alloc_rc = kfifo_alloc(&radio->data_buf[i],
STD_BUF_SIZE, GFP_KERNEL);
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 22d53e9..c0c398b 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -2541,12 +2541,98 @@
return -EINVAL;
}
+static void pm8921_chg_force_19p2mhz_clk(struct pm8921_chg_chip *chip)
+{
+ int err;
+ u8 temp;
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD3;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD5;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ udelay(183);
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD0;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+ udelay(32);
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD3;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+}
+
+static void pm8921_chg_set_hw_clk_switching(struct pm8921_chg_chip *chip)
+{
+ int err;
+ u8 temp;
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD0;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+}
+
#define ENUM_TIMER_STOP_BIT BIT(1)
#define BOOT_DONE_BIT BIT(6)
#define CHG_BATFET_ON_BIT BIT(3)
#define CHG_VCP_EN BIT(0)
#define CHG_BAT_TEMP_DIS_BIT BIT(2)
#define SAFE_CURRENT_MA 1500
+#define VREF_BATT_THERM_FORCE_ON BIT(7)
static int __devinit pm8921_chg_hw_init(struct pm8921_chg_chip *chip)
{
int rc;
@@ -2736,6 +2822,13 @@
/* Disable EOC FSM processing */
pm8xxx_writeb(chip->dev->parent, CHG_BUCK_CTRL_TEST3, 0x91);
+ pm8921_chg_force_19p2mhz_clk(chip);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON,
+ VREF_BATT_THERM_FORCE_ON);
+ if (rc)
+ pr_err("Failed to Force Vref therm rc=%d\n", rc);
+
rc = pm_chg_charge_dis(chip, charging_disabled);
if (rc) {
pr_err("Failed to disable CHG_CHARGE_DIS bit rc=%d\n", rc);
@@ -2918,6 +3011,32 @@
}
}
+static int pm8921_charger_suspend_noirq(struct device *dev)
+{
+ int rc;
+ struct pm8921_chg_chip *chip = dev_get_drvdata(dev);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON, 0);
+ if (rc)
+ pr_err("Failed to Force Vref therm off rc=%d\n", rc);
+ pm8921_chg_set_hw_clk_switching(chip);
+ return 0;
+}
+
+static int pm8921_charger_resume_noirq(struct device *dev)
+{
+ int rc;
+ struct pm8921_chg_chip *chip = dev_get_drvdata(dev);
+
+ pm8921_chg_force_19p2mhz_clk(chip);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON,
+ VREF_BATT_THERM_FORCE_ON);
+ if (rc)
+ pr_err("Failed to Force Vref therm on rc=%d\n", rc);
+ return 0;
+}
+
static int pm8921_charger_resume(struct device *dev)
{
int rc;
@@ -2956,6 +3075,7 @@
pm8921_chg_enable_irq(chip, LOOP_CHANGE_IRQ);
enable_irq_wake(chip->pmic_chg_irq[LOOP_CHANGE_IRQ]);
}
+
return 0;
}
static int __devinit pm8921_charger_probe(struct platform_device *pdev)
@@ -3116,6 +3236,8 @@
}
static const struct dev_pm_ops pm8921_pm_ops = {
.suspend = pm8921_charger_suspend,
+ .suspend_noirq = pm8921_charger_suspend_noirq,
+ .resume_noirq = pm8921_charger_resume_noirq,
.resume = pm8921_charger_resume,
};
static struct platform_driver pm8921_charger_driver = {
diff --git a/drivers/usb/gadget/u_data_hsic.c b/drivers/usb/gadget/u_data_hsic.c
index 61458ea..46109f2 100644
--- a/drivers/usb/gadget/u_data_hsic.c
+++ b/drivers/usb/gadget/u_data_hsic.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -37,6 +37,7 @@
#define GHSIC_DATA_SERIAL_RX_Q_SIZE 2
#define GHSIC_DATA_SERIAL_TX_Q_SIZE 2
#define GHSIC_DATA_RX_REQ_SIZE 2048
+#define GHSIC_DATA_TX_INTR_THRESHOLD 20
static unsigned int ghsic_data_rmnet_tx_q_size = GHSIC_DATA_RMNET_TX_Q_SIZE;
module_param(ghsic_data_rmnet_tx_q_size, uint, S_IRUGO | S_IWUSR);
@@ -53,6 +54,9 @@
static unsigned int ghsic_data_rx_req_size = GHSIC_DATA_RX_REQ_SIZE;
module_param(ghsic_data_rx_req_size, uint, S_IRUGO | S_IWUSR);
+unsigned int ghsic_data_tx_intr_thld = GHSIC_DATA_TX_INTR_THRESHOLD;
+module_param(ghsic_data_tx_intr_thld, uint, S_IRUGO | S_IWUSR);
+
/*flow ctrl*/
#define GHSIC_DATA_FLOW_CTRL_EN_THRESHOLD 500
#define GHSIC_DATA_FLOW_CTRL_DISABLE 300
@@ -109,6 +113,8 @@
/*bridge status*/
unsigned long bridge_sts;
+ unsigned int n_tx_req_queued;
+
/*counters*/
unsigned long to_modem;
unsigned long to_host;
@@ -210,6 +216,14 @@
req->buf = skb->data;
req->length = skb->len;
+ port->n_tx_req_queued++;
+ if (port->n_tx_req_queued == ghsic_data_tx_intr_thld) {
+ req->no_interrupt = 0;
+ port->n_tx_req_queued = 0;
+ } else {
+ req->no_interrupt = 1;
+ }
+
list_del(&req->list);
spin_unlock_irqrestore(&port->port_lock, flags);
@@ -698,6 +712,7 @@
port->port_usb = 0;
port->in = NULL;
port->out = NULL;
+ port->n_tx_req_queued = 0;
clear_bit(TX_THROTTLED, &port->brdg.flags);
clear_bit(RX_THROTTLED, &port->brdg.flags);
spin_unlock_irqrestore(&port->port_lock, flags);
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
index 7c3325a..522ff16 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
@@ -92,17 +92,17 @@
goto bail_out;
}
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
goto bail_out;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
goto disable_pclk;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n");
goto disable_hclk;
}
@@ -120,9 +120,9 @@
}
msleep(20);
- clk_disable(resource_context.pclk);
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
clk_put(resource_context.hclk_div2);
clk_put(resource_context.hclk);
@@ -144,9 +144,9 @@
return true;
disable_hclk:
- clk_disable(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk);
disable_pclk:
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.pclk);
bail_out:
if (resource_context.pclk) {
clk_put(resource_context.pclk);
@@ -175,7 +175,7 @@
VCDRES_MSG_LOW("%s(): Enabling the clocks ...\n", __func__);
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
clk_put(resource_context.hclk);
@@ -184,7 +184,7 @@
return false;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
clk_put(resource_context.pclk);
clk_put(resource_context.hclk_div2);
@@ -192,7 +192,7 @@
return false;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
clk_put(resource_context.hclk);
clk_put(resource_context.pclk);
@@ -253,9 +253,9 @@
VCDRES_MSG_LOW("%s(): Disabling the clocks ...\n", __func__);
resource_context.clock_enabled = 0;
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
mutex_unlock(&resource_context.lock);
return true;
@@ -311,17 +311,17 @@
goto release_all_clks;
}
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
goto release_all_clks;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
goto disable_pclk;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n");
goto disable_hclk_pclk;
}
@@ -333,9 +333,9 @@
}
msleep(20);
- clk_disable(resource_context.pclk);
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
}
resource_context.rail_enabled = 1;
@@ -343,11 +343,11 @@
return true;
disable_and_release_all_clks:
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.hclk_div2);
disable_hclk_pclk:
- clk_disable(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk);
disable_pclk:
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.pclk);
release_all_clks:
clk_put(resource_context.hclk_div2);
resource_context.hclk_div2 = NULL;
@@ -412,7 +412,7 @@
VCDRES_MSG_ERROR("Request AXI bus QOS fails.");
return false;
}
- clk_enable(ebi1_clk);
+ clk_prepare_enable(ebi1_clk);
}
#endif
@@ -427,7 +427,7 @@
#ifdef AXI_CLK_SCALING
VCDRES_MSG_MED("\n res_trk_power_down()::"
"Calling AXI remove requirement\n");
- clk_disable(ebi1_clk);
+ clk_disable_unprepare(ebi1_clk);
clk_put(ebi1_clk);
#endif
VCDRES_MSG_MED("\n res_trk_power_down():: Calling "
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index 1f898b0..5e37c02 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -51,6 +51,7 @@
KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
KGSL_USER_MEM_TYPE_ADDR = 0x00000002,
KGSL_USER_MEM_TYPE_ION = 0x00000003,
+ KGSL_USER_MEM_TYPE_MAX = 0x00000004,
};
struct kgsl_devinfo {
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index 8b753bd..36139ba 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -129,7 +129,8 @@
#define HCI_OCF_FM_EN_WAN_AVD_CTRL 0x0014
#define HCI_OCF_FM_EN_NOTCH_CTRL 0x0015
#define HCI_OCF_FM_SET_EVENT_MASK 0x0016
-
+#define HCI_OCF_FM_SET_CH_DET_THRESHOLD 0x0017
+#define HCI_OCF_FM_GET_CH_DET_THRESHOLD 0x0018
/* HCI trans control commans opcode*/
#define HCI_OCF_FM_ENABLE_TRANS_REQ 0x0001
#define HCI_OCF_FM_DISABLE_TRANS_REQ 0x0002
@@ -199,7 +200,7 @@
#define HCI_FM_ENABLE_TRANS_CMD 13
#define HCI_FM_DISABLE_TRANS_CMD 14
#define HCI_FM_GET_TX_CONFIG 15
-
+#define HCI_FM_GET_DET_CH_TH_CMD 16
/* Defines for FM TX*/
#define TX_PS_DATA_LENGTH 96
@@ -319,6 +320,14 @@
__u16 start_address;
} __packed;
+struct hci_fm_ch_det_threshold {
+ char sinr;
+ __u8 sinr_samples;
+ __u8 low_th;
+ __u8 high_th;
+
+} __packed;
+
/*HCI events*/
#define HCI_EV_TUNE_STATUS 0x01
#define HCI_EV_RDS_LOCK_STATUS 0x02
@@ -551,6 +560,10 @@
V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION,
V4L2_CID_PRIVATE_IRIS_SRCH_ALGORITHM, /* TAVARUA specific command */
V4L2_CID_PRIVATE_IRIS_GET_SINR,
+ V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD,
+ V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD,
+ V4L2_CID_PRIVATE_SINR_THRESHOLD,
+ V4L2_CID_PRIVATE_SINR_SAMPLES,
/*using private CIDs under userclass*/
V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 70ea0df..f8cf37d 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -466,6 +466,7 @@
zone->present_pages += onlined_pages;
zone->zone_pgdat->node_present_pages += onlined_pages;
+ drain_all_pages();
if (need_zonelists_rebuild)
build_all_zonelists(zone);
else