Merge "mmc: msm_sdcc: enable SDCC test bus debugging"
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 00dc5bf..b5408cb 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -5104,6 +5104,31 @@
}
}
+/*
+ * This function prints the testbus debug output for all the
+ * available SDCC controller test bus.
+ *
+ * Note: This function should only be called if the SDCC is clocked.
+ */
+static void msmsdcc_print_testbus_info(struct msmsdcc_host *host)
+{
+ int testbus_num;
+
+ if (!is_testbus_debug(host))
+ return;
+
+ pr_err("== SDCC Test Bus Debug ==");
+ for (testbus_num = 0; testbus_num < MAX_TESTBUS; testbus_num++) {
+ writel_relaxed(((testbus_num & MCI_TESTBUS_SEL_MASK)
+ | MCI_TESTBUS_ENA),
+ host->base + MCI_TESTBUS_CONFIG);
+ pr_err("TestBus(%d) = 0x%.8x\n", testbus_num,
+ (u32)readl_relaxed(host->base + MCI_SDCC_DEBUG_REG));
+ }
+ /* Disable the test bus output */
+ writel_relaxed(~MCI_TESTBUS_ENA, host->base + MCI_TESTBUS_CONFIG);
+}
+
static void msmsdcc_dump_sdcc_state(struct msmsdcc_host *host)
{
/* Dump current state of SDCC clocks, power and irq */
@@ -5123,6 +5148,7 @@
pr_err("%s: MCI_TEST_INPUT = 0x%.8x\n",
mmc_hostname(host->mmc),
readl_relaxed(host->base + MCI_TEST_INPUT));
+ msmsdcc_print_testbus_info(host);
}
if (host->curr.data) {
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 500b5fb..7469c8e 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -193,6 +193,13 @@
#define MCI_TEST_INPUT 0x0D4
+#define MCI_TESTBUS_CONFIG 0x0CC
+#define MCI_TESTBUS_SEL_MASK (0x7)
+#define MAX_TESTBUS 8
+#define MCI_TESTBUS_ENA (1 << 3)
+
+#define MCI_SDCC_DEBUG_REG 0x124
+
#define MCI_IRQENABLE \
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
@@ -449,6 +456,7 @@
#define MSMSDCC_AUTO_CMD21 (1 << 10)
#define MSMSDCC_SW_RST_CFG_BROKEN (1 << 11)
#define MSMSDCC_DATA_PEND_FOR_CMD53 (1 << 12)
+#define MSMSDCC_TESTBUS_DEBUG (1 << 13)
#define set_hw_caps(h, val) ((h)->hw_caps |= val)
#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
@@ -465,6 +473,7 @@
#define is_sw_reset_save_config_broken(h) \
((h)->hw_caps & MSMSDCC_SW_RST_CFG_BROKEN)
#define is_data_pend_for_cmd53(h) ((h)->hw_caps & MSMSDCC_DATA_PEND_FOR_CMD53)
+#define is_testbus_debug(h) ((h)->hw_caps & MSMSDCC_TESTBUS_DEBUG)
/* Set controller capabilities based on version */
static inline void set_default_hw_caps(struct msmsdcc_host *host)
@@ -498,7 +507,8 @@
if (step >= 0x2b) /* SDCC v4 2.1.0 and greater */
host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG |
MSMSDCC_AUTO_CMD21 |
- MSMSDCC_DATA_PEND_FOR_CMD53;
+ MSMSDCC_DATA_PEND_FOR_CMD53 |
+ MSMSDCC_TESTBUS_DEBUG;
if (step == 0x2b)
host->hw_caps |= MSMSDCC_SW_RST_CFG_BROKEN;