| commit | 39d5b2c83ca8904b6826a0713263a4e5a9c0730a | [log] [tgz] |
|---|---|---|
| author | Bruno Randolf <br1@einfach.org> | Mon Jun 07 13:11:25 2010 +0900 |
| committer | John W. Linville <linville@tuxdriver.com> | Tue Jun 08 09:31:20 2010 -0400 |
| tree | f808861ade19d3f138d358a77261285f95684ae3 | |
| parent | 84efa0e7aab9f41451bdf4bff5e2414bb59c6a93 [diff] |
ath5k: update AR5K_PHY_RESTART_DIV_GC values to match masks #define AR5K_PHY_RESTART_DIV_GC 0x001c0000 is 3 bit wide. The previous values of 0xc and 0x8 are 4bit wide and bigger than the mask. Writing 0 and 1 to AR5K_PHY_RESTART_DIV_GC is consistent with the comments and initvals we have in the HAL. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>