coresight: use fixed clock rate for tpiu sdc use case
Vote for a fixed clock frequency for TPIU output to SD to
workaround trace data corruption issues across XO shutdown.
Change-Id: Iaa7e822899685c3b5d0cc01dea1090e817e9b129
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
diff --git a/drivers/coresight/coresight-tpiu.c b/drivers/coresight/coresight-tpiu.c
index de6574a..95cdddba 100644
--- a/drivers/coresight/coresight-tpiu.c
+++ b/drivers/coresight/coresight-tpiu.c
@@ -269,6 +269,10 @@
if (ret)
goto err4;
+ ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_FIXED);
+ if (ret)
+ goto err5;
+
msm_tlmm_misc_reg_write(TLMM_SDC2_HDRV_PULL_CTL, 0x16D);
msm_tlmm_misc_reg_write(TLMM_ETM_MODE_REG, 1);
@@ -280,6 +284,8 @@
TPIU_LOCK(drvdata);
return 0;
+err5:
+ regulator_disable(drvdata->reg_io);
err4:
tpiu_reg_set_voltage(drvdata->reg_io, 0, drvdata->reg_high_io);
err3:
@@ -363,6 +369,8 @@
msm_tlmm_misc_reg_write(TLMM_ETM_MODE_REG, 0);
+ clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
+
regulator_disable(drvdata->reg);
tpiu_reg_set_optimum_mode(drvdata->reg, 0);
tpiu_reg_set_voltage(drvdata->reg, 0, drvdata->reg_high);
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 5b69884..fbd5fb0 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -41,6 +41,7 @@
CORESIGHT_CLK_RATE_OFF,
CORESIGHT_CLK_RATE_TRACE = 1000,
CORESIGHT_CLK_RATE_HSTRACE = 2000,
+ CORESIGHT_CLK_RATE_FIXED = 3000,
};
enum coresight_dev_type {