Merge "msm: timer: correct timer0 base setting" into msm-3.0
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 1df3c23..d9488ec 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -49,6 +49,10 @@
 	#define DG_TIMER_RATING 300
 #endif
 
+#ifndef MSM_TMR0_BASE
+#define MSM_TMR0_BASE MSM_TMR_BASE
+#endif
+
 #define MSM_DGT_SHIFT (5)
 
 #define TIMER_MATCH_VAL         0x0000
@@ -393,7 +397,6 @@
 	local_irq_restore(irq_flags);
 }
 
-/* Call this after SMP init */
 void __iomem *msm_timer_get_timer0_base(void)
 {
 	return MSM_TMR_BASE + global_timer_offset;
@@ -993,10 +996,17 @@
 	else if (cpu_is_msm7x30() || cpu_is_msm8x55())
 		dgt->freq = 6144000;
 	else if (cpu_is_msm8x60()) {
+		global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
 		dgt->freq = 6750000;
 		__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-	} else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930()
-		|| cpu_is_msm9615()) {
+	} else if (cpu_is_msm9615()) {
+		dgt->freq = 6750000;
+		__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+		gpt->freq = 32765;
+		gpt_hz = 32765;
+		sclk_hz = 32765;
+	} else if (cpu_is_msm8960() || cpu_is_apq8064() || cpu_is_msm8930()) {
+		global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
 		dgt->freq = 6750000;
 		__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 		gpt->freq = 32765;
@@ -1081,7 +1091,6 @@
 	if (!smp_processor_id())
 		return 0;
 
-	global_timer_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
 	if (cpu_is_msm8x60() || cpu_is_msm8960() || cpu_is_apq8064()
 			|| cpu_is_msm8930())
 		__raw_writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);