msm: Perf: Add PL310 support for the 8625 and 7627A
Enable perf events support for the PL310 L2CC. Include
single kernel image support for both targets.
Change-Id: Iaad714b538782638a6a299e11dbb1d989b38a563
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
diff --git a/arch/arm/mach-msm/perf_event_msm_pl310.c b/arch/arm/mach-msm/perf_event_msm_pl310.c
index 40a2f98..e2a580f 100644
--- a/arch/arm/mach-msm/perf_event_msm_pl310.c
+++ b/arch/arm/mach-msm/perf_event_msm_pl310.c
@@ -22,6 +22,9 @@
#include <asm/pmu.h>
#include <asm/hardware/cache-l2x0.h>
+#include <mach/socinfo.h>
+
+static u32 rev1;
/*
* Store dynamic PMU type after registration,
@@ -110,6 +113,30 @@
#define COUNTER_ADDR(idx) (l2x0_base + L2X0_EVENT_CNT0_VAL - 4*idx)
+static u32 l2x0_read_intr_mask(void)
+{
+ return readl_relaxed(l2x0_base + L2X0_INTR_MASK);
+}
+
+static void l2x0_write_intr_mask(u32 val)
+{
+ writel_relaxed(val, l2x0_base + L2X0_INTR_MASK);
+}
+
+static void l2x0_enable_counter_interrupt(void)
+{
+ u32 intr_mask = l2x0_read_intr_mask();
+ intr_mask |= L2X0_INTR_MASK_ECNTR;
+ l2x0_write_intr_mask(intr_mask);
+}
+
+static void l2x0_disable_counter_interrupt(void)
+{
+ u32 intr_mask = l2x0_read_intr_mask();
+ intr_mask &= ~L2X0_INTR_MASK_ECNTR;
+ l2x0_write_intr_mask(intr_mask);
+}
+
static void l2x0_clear_interrupts(u32 flags)
{
writel_relaxed(flags, l2x0_base + L2X0_INTR_CLEAR);
@@ -190,10 +217,8 @@
raw_spin_lock_irqsave(&l2x0pmu_hw_events.pmu_lock, flags);
- /*
- * TODO: Enable counter interrupt,
- * once we know it works on this chip.
- */
+ if (!rev1)
+ l2x0_enable_counter_interrupt();
val = l2x0pmu_read_ctrl();
@@ -214,10 +239,8 @@
val &= ~L2X0_EVENT_CNT_ENABLE_MASK;
l2x0pmu_write_ctrl(val);
- /*
- * TODO: Disable counter interrupt,
- * once we know it works on this chip.
- */
+ if (!rev1)
+ l2x0_disable_counter_interrupt();
raw_spin_unlock_irqrestore(&l2x0pmu_hw_events.pmu_lock, flags);
}
@@ -401,6 +424,9 @@
static int __init register_pmu_driver(void)
{
+ if (machine_is_msm9625())
+ rev1 = 1;
+
return platform_driver_register(&l2x0pmu_driver);
}
device_initcall(register_pmu_driver);