Initial Contribution
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..de4d85a 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -1,6 +1,7 @@
/* linux/include/asm-arm/arch-msm/dma.h
*
* Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -14,10 +15,15 @@
*/
#ifndef __ASM_ARCH_MSM_DMA_H
+#define __ASM_ARCH_MSM_DMA_H
#include <linux/list.h>
#include <mach/msm_iomap.h>
+#if defined(CONFIG_ARCH_FSM9XXX)
+#include <mach/dma-fsm9xxx.h>
+#endif
+
struct msm_dmov_errdata {
uint32_t flush[6];
};
@@ -25,74 +31,203 @@
struct msm_dmov_cmd {
struct list_head list;
unsigned int cmdptr;
+ unsigned int crci_mask;
void (*complete_func)(struct msm_dmov_cmd *cmd,
unsigned int result,
struct msm_dmov_errdata *err);
- void (*execute_func)(struct msm_dmov_cmd *cmd);
- void *data;
+ void (*exec_func)(struct msm_dmov_cmd *cmd);
+ void *user; /* Pointer for caller's reference */
};
-#ifndef CONFIG_ARCH_MSM8X60
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-#else
-static inline
-void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
-static inline
-void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
-static inline
-int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
-#endif
+void msm_dmov_flush(unsigned int id);
+int msm_dmov_exec_cmd(unsigned id, unsigned int crci_mask, unsigned int cmdptr);
+unsigned int msm_dmov_build_crci_mask(int n, ...);
+#define DMOV_CRCIS_PER_CONF 10
-#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
-#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
-#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
-#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+#define DMOV_ADDR(off, ch, sd) ((DMOV_SD_SIZE*(sd)) + (off) + ((ch) << 2))
+#define DMOV_SD0(off, ch) DMOV_ADDR(off, ch, 0)
+#define DMOV_SD1(off, ch) DMOV_ADDR(off, ch, 1)
+#define DMOV_SD2(off, ch) DMOV_ADDR(off, ch, 2)
+#define DMOV_SD3(off, ch) DMOV_ADDR(off, ch, 3)
#if defined(CONFIG_ARCH_MSM7X30)
-#define DMOV_SD_AARM DMOV_SD2
+#define DMOV_SD_SIZE 0x400
+#define DMOV_SD_AARM 2
+#elif defined(CONFIG_ARCH_MSM8960)
+#define DMOV_SD_SIZE 0x800
+#define DMOV_SD_AARM 1
+#elif defined(CONFIG_MSM_ADM3)
+#define DMOV_SD_SIZE 0x800
+#define DMOV_SD_MASTER 1
+#define DMOV_SD_AARM 1
+#define DMOV_SD_MASTER_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_MASTER)
+#elif defined(CONFIG_ARCH_FSM9XXX)
+/* defined in dma-fsm9xxx.h */
#else
-#define DMOV_SD_AARM DMOV_SD3
+#define DMOV_SD_SIZE 0x400
+#define DMOV_SD_AARM 3
#endif
-#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
+#define DMOV_SD_AARM_ADDR(off, ch) DMOV_ADDR(off, ch, DMOV_SD_AARM)
+
+#define DMOV_CMD_PTR(ch) DMOV_SD_AARM_ADDR(0x000, ch)
#define DMOV_CMD_LIST (0 << 29) /* does not work */
#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
-#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
+#define DMOV_RSLT(ch) DMOV_SD_AARM_ADDR(0x040, ch)
#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
#define DMOV_RSLT_ERROR (1 << 3)
#define DMOV_RSLT_FLUSH (1 << 2)
#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
-#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
-#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
-#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
-#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
-#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
-#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
+#define DMOV_FLUSH0(ch) DMOV_SD_AARM_ADDR(0x080, ch)
+#define DMOV_FLUSH1(ch) DMOV_SD_AARM_ADDR(0x0C0, ch)
+#define DMOV_FLUSH2(ch) DMOV_SD_AARM_ADDR(0x100, ch)
+#define DMOV_FLUSH3(ch) DMOV_SD_AARM_ADDR(0x140, ch)
+#define DMOV_FLUSH4(ch) DMOV_SD_AARM_ADDR(0x180, ch)
+#define DMOV_FLUSH5(ch) DMOV_SD_AARM_ADDR(0x1C0, ch)
+#define DMOV_FLUSH_TYPE (1 << 31)
-#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
+#define DMOV_STATUS(ch) DMOV_SD_AARM_ADDR(0x200, ch)
#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
#define DMOV_STATUS_RSLT_VALID (1 << 1)
#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
-#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
-
-#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
-#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
-#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
-#define DMOV_CONFIG_IRQ_EN (1 << 0)
+#define DMOV_CONF(ch) DMOV_SD_MASTER_ADDR(0x240, ch)
+#define DMOV_CONF_SD(sd) (((sd & 4) << 11) | ((sd & 3) << 4))
+#define DMOV_CONF_IRQ_EN (1 << 6)
+#define DMOV_CONF_FORCE_RSLT_EN (1 << 7)
+#define DMOV_CONF_SHADOW_EN (1 << 12)
+#define DMOV_CONF_MPU_DISABLE (1 << 11)
+#define DMOV_CONF_PRIORITY(n) (n << 0)
+
+#define DMOV_DBG_ERR(ci) DMOV_SD_MASTER_ADDR(0x280, ci)
+
+#define DMOV_RSLT_CONF(ch) DMOV_SD_AARM_ADDR(0x300, ch)
+#define DMOV_RSLT_CONF_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_RSLT_CONF_FORCE_FLUSH_RSLT (1 << 1)
+#define DMOV_RSLT_CONF_IRQ_EN (1 << 0)
+
+#define DMOV_ISR DMOV_SD_AARM_ADDR(0x380, 0)
+
+#define DMOV_CI_CONF(ci) DMOV_SD_MASTER_ADDR(0x390, ci)
+#define DMOV_CI_CONF_RANGE_END(n) ((n) << 24)
+#define DMOV_CI_CONF_RANGE_START(n) ((n) << 16)
+#define DMOV_CI_CONF_MAX_BURST(n) ((n) << 0)
+
+#define DMOV_CI_DBG_ERR(ci) DMOV_SD_MASTER_ADDR(0x3B0, ci)
+
+#define DMOV_CRCI_CONF0 DMOV_SD_MASTER_ADDR(0x3D0, 0)
+#define DMOV_CRCI_CONF1 DMOV_SD_MASTER_ADDR(0x3D4, 0)
+#define DMOV_CRCI_CONF0_SD(crci, sd) (sd << (crci*3))
+#define DMOV_CRCI_CONF1_SD(crci, sd) (sd << ((crci-DMOV_CRCIS_PER_CONF)*3))
+
+#define DMOV_CRCI_CTL(crci) DMOV_SD_AARM_ADDR(0x400, crci)
+#define DMOV_CRCI_CTL_BLK_SZ(n) ((n) << 0)
+#define DMOV_CRCI_CTL_RST (1 << 17)
+#define DMOV_CRCI_MUX (1 << 18)
/* channel assignments */
+/*
+ * Format of CRCI numbers: crci number + (muxsel << 4)
+ */
+
+#if defined(CONFIG_ARCH_MSM8X60)
+#define DMOV_GP_CHAN 15
+
+#define DMOV_NAND_CHAN 17
+#define DMOV_NAND_CHAN_MODEM 26
+#define DMOV_NAND_CHAN_Q6 27
+#define DMOV_NAND_CRCI_CMD 15
+#define DMOV_NAND_CRCI_DATA 3
+
+#define DMOV_CE_IN_CHAN 2
+#define DMOV_CE_IN_CRCI 4
+
+#define DMOV_CE_OUT_CHAN 3
+#define DMOV_CE_OUT_CRCI 5
+
+#define DMOV_CE_HASH_CRCI 15
+
+#define DMOV_SDC1_CHAN 18
+#define DMOV_SDC1_CRCI 1
+
+#define DMOV_SDC2_CHAN 19
+#define DMOV_SDC2_CRCI 4
+
+#define DMOV_SDC3_CHAN 20
+#define DMOV_SDC3_CRCI 2
+
+#define DMOV_SDC4_CHAN 21
+#define DMOV_SDC4_CRCI 5
+
+#define DMOV_SDC5_CHAN 21
+#define DMOV_SDC5_CRCI 14
+
+#define DMOV_TSIF_CHAN 4
+#define DMOV_TSIF_CRCI 6
+
+#define DMOV_HSUART1_TX_CHAN 22
+#define DMOV_HSUART1_TX_CRCI 8
+
+#define DMOV_HSUART1_RX_CHAN 23
+#define DMOV_HSUART1_RX_CRCI 9
+
+#define DMOV_HSUART2_TX_CHAN 8
+#define DMOV_HSUART2_TX_CRCI 13
+
+#define DMOV_HSUART2_RX_CHAN 8
+#define DMOV_HSUART2_RX_CRCI 14
+
+#elif defined(CONFIG_ARCH_MSM8960)
+#define DMOV_GP_CHAN 13
+
+#define DMOV_CE_IN_CHAN 0
+#define DMOV_CE_IN_CRCI 2
+
+#define DMOV_CE_OUT_CHAN 1
+#define DMOV_CE_OUT_CRCI 3
+
+/* SDC doesn't use ADM on 8960. Need these to compile */
+#define DMOV_SDC1_CHAN 13
+#define DMOV_SDC1_CRCI 0
+
+#define DMOV_SDC2_CHAN 13
+#define DMOV_SDC2_CRCI 0
+
+#define DMOV_SDC3_CHAN 13
+#define DMOV_SDC3_CRCI 0
+
+#define DMOV_SDC4_CHAN 13
+#define DMOV_SDC4_CRCI 0
+
+#define DMOV_SDC5_CHAN 13
+#define DMOV_SDC5_CRCI 0
+
+#elif defined(CONFIG_ARCH_FSM9XXX)
+/* defined in dma-fsm9xxx.h */
+
+#else
+#define DMOV_GP_CHAN 4
+
+#define DMOV_CE_IN_CHAN 5
+#define DMOV_CE_IN_CRCI 1
+
+#define DMOV_CE_OUT_CHAN 6
+#define DMOV_CE_OUT_CRCI 2
+
+#define DMOV_CE_HASH_CRCI 3
+
#define DMOV_NAND_CHAN 7
#define DMOV_NAND_CRCI_CMD 5
#define DMOV_NAND_CRCI_DATA 4
@@ -103,11 +238,31 @@
#define DMOV_SDC2_CHAN 8
#define DMOV_SDC2_CRCI 7
+#define DMOV_SDC3_CHAN 8
+#define DMOV_SDC3_CRCI 12
+
+#define DMOV_SDC4_CHAN 8
+#define DMOV_SDC4_CRCI 13
+
#define DMOV_TSIF_CHAN 10
#define DMOV_TSIF_CRCI 10
#define DMOV_USB_CHAN 11
+#define DMOV_HSUART1_TX_CHAN 4
+#define DMOV_HSUART1_TX_CRCI 8
+
+#define DMOV_HSUART1_RX_CHAN 9
+#define DMOV_HSUART1_RX_CRCI 9
+
+#define DMOV_HSUART2_TX_CHAN 4
+#define DMOV_HSUART2_TX_CRCI 14
+
+#define DMOV_HSUART2_RX_CHAN 11
+#define DMOV_HSUART2_RX_CRCI 15
+#endif
+
+
/* no client rate control ifc (eg, ram) */
#define DMOV_NONE_CRCI 0