perf, x86: Fix key indexing in Pentium-4 PMU
Index 0-6 in p4_templates are reserved for common hardware
events. So p4_templates is arranged as below:
0 - 6: common hardware events
7 - N: cache events
N+1 - ...: other raw events
Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Acked-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268983738.13901.142.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 2a1a57f..facf961 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -709,7 +709,7 @@
};
enum {
- KEY_P4_L1D_OP_READ_RESULT_MISS,
+ KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX,
KEY_P4_LL_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_WRITE_RESULT_MISS,