| commit | 2022c1f136067f673964dcaffa1cae1008ddcd74 | [log] [tgz] |
|---|---|---|
| author | Russ Anderson <rja@sgi.com> | Thu Jan 03 10:23:49 2008 -0600 |
| committer | Tony Luck <tony.luck@intel.com> | Thu Jan 03 13:22:54 2008 -0800 |
| tree | e62db392a3d730156fe8ca62d9e7d507f3e1a8de | |
| parent | 4ca8ad7e4c38cd7f32b11e60418d06fa912a1a37 [diff] |
[IA64] Update Altix nofault code Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>