| commit | 44131dff361d7c1e1ecc24504d3ae7145104f6c9 | [log] [tgz] |
|---|---|---|
| author | Matt Wagantall <mattw@codeaurora.org> | Fri Aug 03 18:29:47 2012 -0700 |
| committer | Matt Wagantall <mattw@codeaurora.org> | Fri Aug 03 18:31:38 2012 -0700 |
| tree | 75e4c07c50007547eade6c6dd1d3363efee96549 | |
| parent | b782abd7fd95306b0b63ad31958b1c9fed95c69c [diff] |
msm: pil-pronto: Add delay after de-assertion of CLK_CTL_WCNSS_RESTART_BIT A previous change introduced a udelay after de-asserting this bit in another place in this driver, but this second de-assertion was missed. Add it for similar reasons: the subsystem cannot be accessed until the reset de-assertion has finished propagating. Change-Id: I97abe8b81cd599ab3187f989429501d35f50aec6 Signed-off-by: Matt Wagantall <mattw@codeaurora.org>