msm: clock-8610: Rename camera mux clocks temporarily
To allow the generic mux code to co-exist with the camera
mux code, rename the camera mux clocks temporarily. These
clocks will use the generic code soon allowing the camera
specific mux code to go away.
Change-Id: Ic7ddfd9809df3f98782dbfe8187b8b82fa95e91b
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8610.c b/arch/arm/mach-msm/clock-8610.c
index 478f77f..b778662 100644
--- a/arch/arm/mach-msm/clock-8610.c
+++ b/arch/arm/mach-msm/clock-8610.c
@@ -2017,7 +2017,7 @@
},
};
-static struct mux_clk csi0phy_mux_clk = {
+static struct cam_mux_clk csi0phy_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(11),
.select_reg = MMSS_CAMSS_MISC,
@@ -2029,13 +2029,13 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "csi0phy_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(csi0phy_mux_clk.c),
+ .dbg_name = "csi0phy_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(csi0phy_cam_mux_clk.c),
},
};
-static struct mux_clk csi1phy_mux_clk = {
+static struct cam_mux_clk csi1phy_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(10),
.select_reg = MMSS_CAMSS_MISC,
@@ -2047,13 +2047,13 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "csi1phy_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(csi1phy_mux_clk.c),
+ .dbg_name = "csi1phy_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(csi1phy_cam_mux_clk.c),
},
};
-static struct mux_clk csi0pix_mux_clk = {
+static struct cam_mux_clk csi0pix_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(7),
.select_reg = MMSS_CAMSS_MISC,
@@ -2065,14 +2065,14 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "csi0pix_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(csi0pix_mux_clk.c),
+ .dbg_name = "csi0pix_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(csi0pix_cam_mux_clk.c),
},
};
-static struct mux_clk rdi2_mux_clk = {
+static struct cam_mux_clk rdi2_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(6),
.select_reg = MMSS_CAMSS_MISC,
@@ -2084,13 +2084,13 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "rdi2_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(rdi2_mux_clk.c),
+ .dbg_name = "rdi2_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(rdi2_cam_mux_clk.c),
},
};
-static struct mux_clk rdi1_mux_clk = {
+static struct cam_mux_clk rdi1_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(5),
.select_reg = MMSS_CAMSS_MISC,
@@ -2102,13 +2102,13 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "rdi1_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(rdi1_mux_clk.c),
+ .dbg_name = "rdi1_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(rdi1_cam_mux_clk.c),
},
};
-static struct mux_clk rdi0_mux_clk = {
+static struct cam_mux_clk rdi0_cam_mux_clk = {
.enable_reg = MMSS_CAMSS_MISC,
.enable_mask = BIT(4),
.select_reg = MMSS_CAMSS_MISC,
@@ -2120,9 +2120,9 @@
},
.base = &virt_bases[MMSS_BASE],
.c = {
- .dbg_name = "rdi0_mux_clk",
- .ops = &clk_ops_mux,
- CLK_INIT(rdi0_mux_clk.c),
+ .dbg_name = "rdi0_cam_mux_clk",
+ .ops = &clk_ops_cam_mux,
+ CLK_INIT(rdi0_cam_mux_clk.c),
},
};
@@ -2967,12 +2967,12 @@
CLK_LOOKUP("core_clk", vfe_ahb_clk.c, ""),
CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
- CLK_LOOKUP("core_clk", csi0pix_mux_clk.c, ""),
- CLK_LOOKUP("core_clk", csi0phy_mux_clk.c, ""),
- CLK_LOOKUP("core_clk", csi1phy_mux_clk.c, ""),
- CLK_LOOKUP("core_clk", rdi2_mux_clk.c, ""),
- CLK_LOOKUP("core_clk", rdi1_mux_clk.c, ""),
- CLK_LOOKUP("core_clk", rdi0_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", csi0pix_cam_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", csi0phy_cam_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", csi1phy_cam_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", rdi2_cam_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", rdi1_cam_mux_clk.c, ""),
+ CLK_LOOKUP("core_clk", rdi0_cam_mux_clk.c, ""),
CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdc00000.qcom,kgsl-3d0"),
CLK_LOOKUP("iface_clk", oxili_ahb_clk.c, "fdc00000.qcom,kgsl-3d0"),