| commit | 4c020a961a812ffae9846b917304cea504c3a733 | [log] [tgz] |
|---|---|---|
| author | David Dillow <dave@thedillows.org> | Wed Mar 03 16:33:10 2010 +0000 |
| committer | David S. Miller <davem@davemloft.net> | Thu Mar 04 00:53:53 2010 -0800 |
| tree | c2cae6ab8a1d9b62452b26ea865fdf51573464f3 | |
| parent | d0021b252eaf65ca07ed14f0d66425dd9ccab9a6 [diff] |
r8169: use correct barrier between cacheable and non-cacheable memory r8169 needs certain writes to be visible to other CPUs or the NIC before touching the hardware, but was using smp_wmb() which is only required to order cacheable memory access. Switch to wmb() which is required to order both cacheable and non-cacheable memory. Noticed by Catalin Marinas and Paul Mackerras. Signed-off-by: David Dillow <dave@thedillows.org> Signed-off-by: David S. Miller <davem@davemloft.net>