Merge "msm: camera2: cpp: Support queue and timer clean up."
diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp.txt b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
index 749c594..1aca300 100644
--- a/Documentation/devicetree/bindings/leds/leds-qpnp.txt
+++ b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
@@ -52,13 +52,15 @@
RGB Led is a tri-colored led, Red, Blue & Green.
Required properties for RGB led:
-- qcom,mode: mode the led should operate in, options "pwm" and "lpg"
-- qcom,pwm-channel: pwm channel the led will operate on
+- qcom,mode: mode the led should operate in, options "pwm" and "lpg". "manual" mode is not supported for RGB led.
Required properties for PWM mode only:
+- qcom,pwm-channel: pwm channel the led will operate on
- qcom,pwm-us: time the pwm device will modulate at (us)
Required properties for LPG mode only:
+- qcom,pwm-channel: pwm channel the led will operate on
+- qcom,pwm-us: time the pwm device will modulate at (us)
- qcom,duty-pcts: array of values for duty cycle to go through
- qcom,start-idx: starting point duty-pcts array
@@ -93,6 +95,7 @@
Required properties for LPG mode only:
- qcom,pwm-channel: pwm channel the led will operate on
+- qcom,pwm-us: time the pwm device will modulate at (us)
- qcom,duty-pcts: array of values for duty cycle to go through
- qcom,start-idx: starting point duty-pcts array
@@ -106,9 +109,7 @@
and the required rows are enabled by specifying values in the properties.
Required properties for keypad backlight:
-- qcom,mode: mode the led should operate in, options "pwm" and "lpg"
-- qcom,pwm-channel: pwm channel the led will operate on
-- qcom,pwm-us: time the pwm device will modulate at (us)
+- qcom,mode: mode the led should operate in, options "pwm" and "lpg". "manual" mode is not supported for keypad backlight.
- qcom,row-id: specify the id of the row. Supported values are 0 to 3.
Optional properties for keypad backlight:
@@ -118,9 +119,12 @@
- qcom,always-on: specify if the module has to be always on
Required properties for PWM mode only:
+- qcom,pwm-channel: pwm channel the led will operate on
- qcom,pwm-us: time the pwm device will modulate at (us)
Required properties for LPG mode only:
+- qcom,pwm-channel: pwm channel the led will operate on
+- qcom,pwm-us: time the pwm device will modulate at (us)
- qcom,duty-pcts: array of values for duty cycle to go through
- qcom,start-idx: starting point duty-pcts array
@@ -201,6 +205,7 @@
linux,name = "led:rgb_green";
qcom,mode = "lpg";
qcom,pwm-channel = <5>;
+ qcom,pwm-us = <1000>;
qcom,duty-ms = <20>;
qcom,start-idx = <1>;
qcom,idx-len = <10>;
diff --git a/Documentation/devicetree/bindings/memory.txt b/Documentation/devicetree/bindings/memory.txt
index 32f6a24..3ee245e 100644
--- a/Documentation/devicetree/bindings/memory.txt
+++ b/Documentation/devicetree/bindings/memory.txt
@@ -36,6 +36,7 @@
reg = <(baseaddr) (size)>;
(linux,contiguous-region);
(linux,default-contiguous-region);
+ (linux,reserve-region);
(linux,memory-limit);
label = (unique_name);
};
@@ -49,6 +50,9 @@
linux,default-contiguous-region: property indicating that the region
is the default region for all contiguous memory
allocations, Linux specific (optional)
+linux,reserve-region: property indicating that the contiguous memory will
+ not be given back to the system allocator. The memory be
+ always be available for contiguous use.
linux,memory-limit: property specifying an upper bound on the physical address
of the region if the region is placed dynamically. If no limit
is specificed, the region may be placed anywhere in the physical
diff --git a/Documentation/devicetree/bindings/sound/voice-svc.txt b/Documentation/devicetree/bindings/sound/voice-svc.txt
index deca7f5..bb8649f 100644
--- a/Documentation/devicetree/bindings/sound/voice-svc.txt
+++ b/Documentation/devicetree/bindings/sound/voice-svc.txt
@@ -1,4 +1,6 @@
* Voice Service binding
+Provides an interface to access voice services
+exposed by DSP over APR interface.
Required properties:
- compatible : "qcom,msm-voice-svc"
diff --git a/arch/arm/boot/dts/msm8226-mdss.dtsi b/arch/arm/boot/dts/msm8226-mdss.dtsi
index 5776926..cedec5f 100644
--- a/arch/arm/boot/dts/msm8226-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8226-mdss.dtsi
@@ -76,7 +76,13 @@
<0x0D8 0x00000707>,
<0x124 0x00000003>;
qcom,mdp-settings = <0x02E0 0x000000A5>,
- <0x02E4 0x00000055>;
+ <0x02E4 0x00000055>,
+ <0x03AC 0xC0000CCC>,
+ <0x03B4 0xC0000000>,
+ <0x03BC 0x00C00C00>,
+ <0x04A8 0x0CCCC000>,
+ <0x04B0 0xC0000000>,
+ <0x04B8 0xC0000000>;
/* buffer parameters to calculate prefill bandwidth */
qcom,mdss-prefill-outstanding-buffer-bytes = <1024>;
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index d83a235..3fef47a 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -35,6 +35,7 @@
qcom,mdss-ab-factor = <2 1>; /* 2 times */
qcom,mdss-ib-factor = <6 5>; /* 1.2 times */
qcom,mdss-clk-factor = <5 4>; /* 1.25 times */
+ qcom,mdss-ib-factor-overlap = <7 4>; /* 1.75 times */
qcom,max-clk-rate = <320000000>;
qcom,mdss-pipe-vig-off = <0x00001200 0x00001600
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index e0f2ef2..4eb26a2 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -335,7 +335,7 @@
qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
qcom,msm-bus,name = "sdcc1";
- qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
<78 512 1600 3200>, /* 400 KB/s*/
@@ -344,8 +344,11 @@
<78 512 200000 400000>, /* 50 MB/s */
<78 512 400000 800000>, /* 100 MB/s */
<78 512 800000 1600000>, /* 200 MB/s */
+ <78 512 800000 1600000>, /* 400 MB/s */
<78 512 2048000 4096000>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 400000000
+ 4294967295>;
qcom,dat1-mpm-int = <42>;
status = "disable";
};
@@ -498,7 +501,7 @@
qcom,cpu-dma-latency-us = <200>;
qcom,msm-bus,name = "sdhc1";
- qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
<78 512 1600 3200>, /* 400 KB/s*/
@@ -507,8 +510,11 @@
<78 512 200000 400000>, /* 50 MB/s */
<78 512 400000 800000>, /* 100 MB/s */
<78 512 800000 1600000>, /* 200 MB/s */
+ <78 512 800000 1600000>, /* 400 MB/s */
<78 512 2048000 4096000>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 400000000
+ 4294967295>;
qcom,dat1-mpm-int = <42>;
status = "disable";
};
@@ -1732,6 +1738,10 @@
compatible = "qti,msm-pcm-loopback";
};
+ qcom,msm-voice-svc {
+ compatible = "qcom,msm-voice-svc";
+ };
+
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
qcom,msm-dai-q6-sb-0-rx {
diff --git a/arch/arm/kernel/perf_event_msm_krait.c b/arch/arm/kernel/perf_event_msm_krait.c
index 1fb5fd3..1c338f7 100644
--- a/arch/arm/kernel/perf_event_msm_krait.c
+++ b/arch/arm/kernel/perf_event_msm_krait.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2012, 2014 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -454,37 +454,29 @@
/* Disable counter */
armv7_pmnc_disable_counter(idx);
- /*
- * Set event (if destined for PMNx counters)
- * We don't need to set the event if it's a cycle count
- */
- if (idx != ARMV7_IDX_CYCLE_COUNTER) {
- val = hwc->config_base;
- val &= KRAIT_EVENT_MASK;
+ val = hwc->config_base;
+ val &= KRAIT_EVENT_MASK;
- if (val < 0x40) {
- armv7_pmnc_write_evtsel(idx, hwc->config_base);
- } else {
- event = get_krait_evtinfo(val, &evtinfo);
+ /* set event for ARM-architected events, and filter for CC */
+ if ((val < 0x40) || (idx == ARMV7_IDX_CYCLE_COUNTER)) {
+ armv7_pmnc_write_evtsel(idx, hwc->config_base);
+ } else {
+ event = get_krait_evtinfo(val, &evtinfo);
- if (event == -EINVAL)
- goto krait_out;
+ if (event == -EINVAL)
+ goto krait_out;
- /* Restore Mode-exclusion bits */
- event |= (hwc->config_base & KRAIT_MODE_EXCL_MASK);
+ /* Restore Mode-exclusion bits */
+ event |= (hwc->config_base & KRAIT_MODE_EXCL_MASK);
- /*
- * Set event (if destined for PMNx counters)
- * We don't need to set the event if it's a cycle count
- */
- armv7_pmnc_write_evtsel(idx, event);
- val = 0x0;
- asm volatile("mcr p15, 0, %0, c9, c15, 0" : :
- "r" (val));
- val = evtinfo.group_setval;
- gr = evtinfo.groupcode;
- krait_evt_setup(gr, val, evtinfo.armv7_evt_type);
- }
+ /* Set event (if destined for PMNx counters) */
+ armv7_pmnc_write_evtsel(idx, event);
+ val = 0x0;
+ asm volatile("mcr p15, 0, %0, c9, c15, 0" : :
+ "r" (val));
+ val = evtinfo.group_setval;
+ gr = evtinfo.groupcode;
+ krait_evt_setup(gr, val, evtinfo.armv7_evt_type);
}
/* Enable interrupt for this counter */
diff --git a/arch/arm/mach-msm/clock-8226.c b/arch/arm/mach-msm/clock-8226.c
index 7a7c008..e16bcb1 100644
--- a/arch/arm/mach-msm/clock-8226.c
+++ b/arch/arm/mach-msm/clock-8226.c
@@ -3497,8 +3497,36 @@
"fda08400.qcom,csid"),
/* ISPIF clocks */
+
CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
- "fda0a000.qcom,ispif"),
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_clk", camss_csi0_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c,
+ "fda0a000.qcom,ispif"),
+
+ CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_clk", camss_csi1_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c,
+ "fda0a000.qcom,ispif"),
+ CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c,
+ "fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
"fda0a000.qcom,ispif"),
CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index c81720e..a5240cc 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -329,24 +329,40 @@
* before the CPU is brought up.
*/
case CPU_DEAD:
- case CPU_UP_CANCELED:
if (is_clk) {
clk_disable_unprepare(cpu_clk[cpu]);
clk_disable_unprepare(l2_clk);
update_l2_bw(NULL);
}
break;
+ case CPU_UP_CANCELED:
+ if (is_clk) {
+ clk_unprepare(cpu_clk[cpu]);
+ clk_unprepare(l2_clk);
+ update_l2_bw(NULL);
+ }
+ break;
case CPU_UP_PREPARE:
if (is_clk) {
- rc = clk_prepare_enable(l2_clk);
+ rc = clk_prepare(l2_clk);
if (rc < 0)
return NOTIFY_BAD;
- rc = clk_prepare_enable(cpu_clk[cpu]);
+ rc = clk_prepare(cpu_clk[cpu]);
if (rc < 0)
return NOTIFY_BAD;
update_l2_bw(&cpu);
}
break;
+ case CPU_STARTING:
+ if (is_clk) {
+ rc = clk_enable(l2_clk);
+ if (rc < 0)
+ return NOTIFY_BAD;
+ rc = clk_enable(cpu_clk[cpu]);
+ if (rc < 0)
+ return NOTIFY_BAD;
+ }
+ break;
default:
break;
}
diff --git a/arch/arm/mach-msm/include/mach/ocmem_priv.h b/arch/arm/mach-msm/include/mach/ocmem_priv.h
index 00aedb6..c94fa0e 100644
--- a/arch/arm/mach-msm/include/mach/ocmem_priv.h
+++ b/arch/arm/mach-msm/include/mach/ocmem_priv.h
@@ -206,7 +206,7 @@
int check_notifier(int);
const char *get_name(int);
int get_tz_id(int);
-int ocmem_enable_sec_program(int);
+int ocmem_restore_sec_program(int);
int ocmem_enable_dump(enum ocmem_client, unsigned long, unsigned long);
int ocmem_disable_dump(enum ocmem_client, unsigned long, unsigned long);
int check_id(int);
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/apr_us.h b/arch/arm/mach-msm/include/mach/qdsp6v2/apr_us.h
index 661d496..8de3d60 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/apr_us.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/apr_us.h
@@ -45,6 +45,28 @@
#define USM_STREAM_CMD_CLOSE 0x0001230A
+#define USM_STREAM_CMD_SET_PARAM 0x00012731
+struct usm_stream_cmd_set_param {
+ struct apr_hdr hdr;
+ u32 buf_addr_lsw;
+ u32 buf_addr_msw;
+ u32 mem_map_handle;
+ u32 buf_size;
+ u32 module_id;
+ u32 param_id;
+} __packed;
+
+#define USM_STREAM_CMD_GET_PARAM 0x00012732
+struct usm_stream_cmd_get_param {
+ struct apr_hdr hdr;
+ u32 buf_addr_lsw;
+ u32 buf_addr_msw;
+ u32 mem_map_handle;
+ u32 buf_size;
+ u32 module_id;
+ u32 param_id;
+} __packed;
+
/* Encoder configuration definitions */
#define USM_STREAM_CMD_SET_ENC_PARAM 0x0001230B
/* Decoder configuration definitions */
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h b/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
index faf50d2..9944353 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
@@ -39,6 +39,15 @@
#define US_GET_VERSION _IOWR(USF_IOCTL_MAGIC, 9, \
struct us_version_info_type)
+#define US_SET_TX_STREAM_PARAM _IOW(USF_IOCTL_MAGIC, 10, \
+ struct us_stream_param_type)
+#define US_GET_TX_STREAM_PARAM _IOWR(USF_IOCTL_MAGIC, 11, \
+ struct us_stream_param_type)
+#define US_SET_RX_STREAM_PARAM _IOW(USF_IOCTL_MAGIC, 12, \
+ struct us_stream_param_type)
+#define US_GET_RX_STREAM_PARAM _IOWR(USF_IOCTL_MAGIC, 13, \
+ struct us_stream_param_type)
+
/* Special timeout values */
#define USF_NO_WAIT_TIMEOUT 0x00000000
/* Infinitive */
@@ -130,6 +139,8 @@
uint16_t params_data_size;
/* Pointer to the parameters */
uint8_t *params_data;
+/* Max size of buffer for get and set parameter */
+ uint32_t max_get_set_param_buf_size;
};
struct us_input_info_type {
@@ -273,4 +284,15 @@
char *pbuf;
};
+struct us_stream_param_type {
+/* Id of module */
+ uint32_t module_id;
+/* Id of parameter */
+ uint32_t param_id;
+/* Size of memory of the parameter buffer */
+ uint32_t buf_size;
+/* Pointer to the memory of the parameter buffer */
+ uint8_t __user *pbuf;
+};
+
#endif /* __USF_H__ */
diff --git a/arch/arm/mach-msm/ocmem.c b/arch/arm/mach-msm/ocmem.c
index 99e54b7..4a8cc39 100644
--- a/arch/arm/mach-msm/ocmem.c
+++ b/arch/arm/mach-msm/ocmem.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -788,6 +788,7 @@
struct device *dev = &pdev->dev;
struct clk *ocmem_core_clk = NULL;
struct clk *ocmem_iface_clk = NULL;
+ int rc;
if (!pdev->dev.of_node) {
dev_info(dev, "Missing Configuration in Device Tree\n");
@@ -830,10 +831,23 @@
platform_set_drvdata(pdev, ocmem_pdata);
+ rc = ocmem_enable_core_clock();
+ if (rc < 0)
+ goto core_clk_fail;
+
+ rc = ocmem_enable_iface_clock();
+ if (rc < 0)
+ goto iface_clk_fail;
+
/* Parameter to be updated based on TZ */
/* Allow the OCMEM CSR to be programmed */
- if (ocmem_enable_sec_program(OCMEM_SECURE_DEV_ID))
+ if (ocmem_restore_sec_program(OCMEM_SECURE_DEV_ID)) {
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
return -EBUSY;
+ }
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
if (ocmem_debugfs_init(pdev))
dev_err(dev, "ocmem: No debugfs node available\n");
@@ -860,6 +874,11 @@
dev_dbg(dev, "initialized successfully\n");
return 0;
+
+iface_clk_fail:
+ ocmem_disable_core_clock();
+core_clk_fail:
+ return rc;
}
static int __devexit msm_ocmem_remove(struct platform_device *pdev)
diff --git a/arch/arm/mach-msm/ocmem_core.c b/arch/arm/mach-msm/ocmem_core.c
index f753391..9c2afb9 100644
--- a/arch/arm/mach-msm/ocmem_core.c
+++ b/arch/arm/mach-msm/ocmem_core.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -583,7 +583,7 @@
return 0;
}
-int ocmem_enable_sec_program(int sec_id)
+int ocmem_restore_sec_program(int sec_id)
{
return 0;
}
@@ -702,7 +702,7 @@
return rc;
}
-int ocmem_enable_sec_program(int sec_id)
+int ocmem_restore_sec_program(int sec_id)
{
int rc, scm_ret = 0;
struct msm_scm_sec_cfg {
@@ -953,7 +953,6 @@
unsigned end_m = num_banks;
unsigned long region_offset = 0;
struct ocmem_hw_region *region;
- int rc = 0;
if (offset < 0)
return -EINVAL;
@@ -974,14 +973,6 @@
(region_end >= num_regions))
return -EINVAL;
- rc = ocmem_enable_core_clock();
-
- if (rc < 0) {
- pr_err("ocmem: Power transistion request for client %s (id: %d) failed\n",
- get_name(id), id);
- return rc;
- }
-
mutex_lock(®ion_ctrl_lock);
for (i = region_start; i <= region_end; i++) {
@@ -1035,11 +1026,10 @@
}
mutex_unlock(®ion_ctrl_lock);
- ocmem_disable_core_clock();
+
return 0;
invalid_transition:
mutex_unlock(®ion_ctrl_lock);
- ocmem_disable_core_clock();
pr_err("ocmem_core: Invalid state transition detected for %d\n", id);
pr_err("ocmem_core: Offset %lx Len %lx curr_state %x new_state %x\n",
offset, len, curr_state, new_state);
@@ -1122,9 +1112,37 @@
static int ocmem_power_show(struct seq_file *f, void *dummy)
{
+ int rc = 0;
+
+ rc = ocmem_enable_core_clock();
+
+ if (rc < 0)
+ goto core_clock_fail;
+
+ rc = ocmem_enable_iface_clock();
+
+ if (rc < 0)
+ goto iface_clock_fail;
+
+ rc = ocmem_restore_sec_program(OCMEM_SECURE_DEV_ID);
+ if (rc < 0) {
+ pr_err("ocmem: Failed to restore security programming\n");
+ goto restore_config_fail;
+ }
ocmem_power_show_sw_state(f, dummy);
ocmem_power_show_hw_state(f, dummy);
+
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
+
return 0;
+
+restore_config_fail:
+ ocmem_disable_iface_clock();
+iface_clock_fail:
+ ocmem_disable_core_clock();
+core_clock_fail:
+ return -EINVAL;
}
static int ocmem_power_open(struct inode *inode, struct file *file)
diff --git a/arch/arm/mach-msm/ocmem_sched.c b/arch/arm/mach-msm/ocmem_sched.c
index 8e25bb2..78279ed 100644
--- a/arch/arm/mach-msm/ocmem_sched.c
+++ b/arch/arm/mach-msm/ocmem_sched.c
@@ -634,17 +634,11 @@
{
int rc = 0;
- rc = ocmem_enable_core_clock();
+ rc = ocmem_restore_sec_program(OCMEM_SECURE_DEV_ID);
- if (rc < 0)
- goto core_clock_fail;
-
-
- if (is_iface_access(req->owner)) {
- rc = ocmem_enable_iface_clock();
-
- if (rc < 0)
- goto iface_clock_fail;
+ if (rc < 0) {
+ pr_err("ocmem: Failed to restore security programming\n");
+ goto lock_failed;
}
rc = ocmem_lock(req->owner, phys_to_offset(req->req_start), req->req_sz,
@@ -670,11 +664,6 @@
process_map_fail:
ocmem_unlock(req->owner, phys_to_offset(req->req_start), req->req_sz);
lock_failed:
- if (is_iface_access(req->owner))
- ocmem_disable_iface_clock();
-iface_clock_fail:
- ocmem_disable_core_clock();
-core_clock_fail:
pr_err("ocmem: Failed to map ocmem request\n");
return rc;
}
@@ -698,9 +687,6 @@
goto unlock_failed;
}
- if (is_iface_access(req->owner))
- ocmem_disable_iface_clock();
- ocmem_disable_core_clock();
pr_debug("ocmem: Unmapped request %p\n", req);
return 0;
@@ -1345,9 +1331,21 @@
if (rc < 0)
return -EINVAL;
+ rc = ocmem_enable_core_clock();
+
+ if (rc < 0)
+ goto core_clock_fail;
+
+ if (is_iface_access(req->owner)) {
+ rc = ocmem_enable_iface_clock();
+
+ if (rc < 0)
+ goto iface_clock_fail;
+ }
+
rc = process_map(req, req->req_start, req->req_end);
if (rc < 0)
- return -EINVAL;
+ goto map_error;
offset = phys_to_offset(req->req_start);
@@ -1366,7 +1364,14 @@
BUG();
}
return 0;
+
power_ctl_error:
+map_error:
+if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+iface_clock_fail:
+ ocmem_disable_core_clock();
+core_clock_fail:
return -EINVAL;
}
@@ -1536,6 +1541,10 @@
}
}
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
+
rc = do_free(req);
if (rc < 0) {
pr_err("ocmem: Failed to free %p\n", req);
@@ -1556,6 +1565,9 @@
pr_err("Failed to switch OFF memory macros\n");
goto free_fail;
}
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
}
/* free the allocation */
@@ -1658,6 +1670,10 @@
rc = process_unmap(req, req->req_start, req->req_end);
if (rc < 0)
return -EINVAL;
+
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
} else
return -EINVAL;
@@ -1768,6 +1784,9 @@
rc = process_unmap(req, req->req_start, req->req_end);
if (rc < 0)
goto shrink_fail;
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+ ocmem_disable_core_clock();
}
rc = do_free(req);
if (rc < 0)
@@ -2254,6 +2273,17 @@
if (req->req_sz != 0) {
+ rc = ocmem_enable_core_clock();
+
+ if (rc < 0)
+ goto core_clock_fail;
+
+ if (is_iface_access(req->owner)) {
+ rc = ocmem_enable_iface_clock();
+
+ if (rc < 0)
+ goto iface_clock_fail;
+ }
rc = process_map(req, req->req_start, req->req_end);
if (rc < 0)
goto map_error;
@@ -2275,6 +2305,11 @@
map_error:
handle->req = NULL;
do_free(req);
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+iface_clock_fail:
+ ocmem_disable_core_clock();
+core_clock_fail:
do_allocate_error:
ocmem_destroy_req(req);
return -EINVAL;
@@ -2303,6 +2338,17 @@
inc_ocmem_stat(zone_of(req), NR_ASYNC_ALLOCATIONS);
if (req->req_sz != 0) {
+ rc = ocmem_enable_core_clock();
+
+ if (rc < 0)
+ goto core_clock_fail;
+
+ if (is_iface_access(req->owner)) {
+ rc = ocmem_enable_iface_clock();
+
+ if (rc < 0)
+ goto iface_clock_fail;
+ }
rc = process_map(req, req->req_start, req->req_end);
if (rc < 0)
@@ -2333,6 +2379,11 @@
map_error:
handle->req = NULL;
do_free(req);
+ if (is_iface_access(req->owner))
+ ocmem_disable_iface_clock();
+iface_clock_fail:
+ ocmem_disable_core_clock();
+core_clock_fail:
do_allocate_error:
ocmem_destroy_req(req);
return -EINVAL;
diff --git a/arch/arm/mach-msm/perf_debug.c b/arch/arm/mach-msm/perf_debug.c
index 3a87c78..c4f7d45 100644
--- a/arch/arm/mach-msm/perf_debug.c
+++ b/arch/arm/mach-msm/perf_debug.c
@@ -48,6 +48,7 @@
"23 msm: perf: Fix cpu id logic in tracectr notifier\n"
"24 msm: perf: tracectr: Initialize cnts after hotplug\n"
"25 Perf: Reset pmu after hotplug\n"
+ "26 msm: perf: set filter bits for cycle counter on krait\n"
;
static ssize_t desc_read(struct file *fp, char __user *buf,
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h b/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
index 7ab4ec3..58a6431 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
@@ -65,6 +65,14 @@
spinlock_t dsp_lock;
/* extended parameters, related to q6 variants */
void *ext;
+ /* physical address of parameter buffer */
+ dma_addr_t param_phys;
+ /* buffer which stores the parameter data */
+ u8 *param_buf;
+ /* size of parameter buffer */
+ uint32_t param_buf_size;
+ /* parameter buffer memory handle */
+ void *param_buf_mem_handle;
};
struct us_client {
@@ -88,6 +96,8 @@
int q6usm_cmd(struct us_client *usc, int cmd);
int q6usm_us_client_buf_alloc(unsigned int dir, struct us_client *usc,
unsigned int bufsz, unsigned int bufcnt);
+int q6usm_us_param_buf_alloc(unsigned int dir, struct us_client *usc,
+ unsigned int bufsz);
int q6usm_enc_cfg_blk(struct us_client *usc, struct us_encdec_cfg *us_cfg);
int q6usm_dec_cfg_blk(struct us_client *usc, struct us_encdec_cfg *us_cfg);
int q6usm_read(struct us_client *usc, uint32_t read_ind);
@@ -104,5 +114,9 @@
int q6usm_set_us_detection(struct us_client *usc,
struct usm_session_cmd_detect_info *detect_info,
uint16_t detect_info_size);
+int q6usm_set_us_stream_param(int dir, struct us_client *usc,
+ uint32_t module_id, uint32_t param_id, uint32_t buf_size);
+int q6usm_get_us_stream_param(int dir, struct us_client *usc,
+ uint32_t module_id, uint32_t param_id, uint32_t buf_size);
#endif /* __Q6_USM_H__ */
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c b/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
index 192aaf9..1c42020 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
@@ -27,8 +27,8 @@
#include "usfcdev.h"
/* The driver version*/
-#define DRV_VERSION "1.6.1"
-#define USF_VERSION_ID 0x0161
+#define DRV_VERSION "1.7.1"
+#define USF_VERSION_ID 0x0171
/* Standard timeout in the asynchronous ops */
#define USF_TIMEOUT_JIFFIES (1*HZ) /* 1 sec */
@@ -36,6 +36,8 @@
/* Undefined USF device */
#define USF_UNDEF_DEV_ID 0xffff
+/* TX memory mapping flag */
+#define USF_VM_READ 1
/* RX memory mapping flag */
#define USF_VM_WRITE 2
@@ -973,6 +975,13 @@
return rc;
}
+ rc = q6usm_us_param_buf_alloc(OUT, usf_xx->usc,
+ config_tx.us_xx_info.max_get_set_param_buf_size);
+ if (rc) {
+ (void)q6usm_cmd(usf_xx->usc, CMD_CLOSE);
+ return rc;
+ }
+
rc = q6usm_enc_cfg_blk(usf_xx->usc,
&usf_xx->encdec_cfg);
if (!rc &&
@@ -1027,6 +1036,13 @@
return rc;
}
+ rc = q6usm_us_param_buf_alloc(IN, usf_xx->usc,
+ config_rx.us_xx_info.max_get_set_param_buf_size);
+ if (rc) {
+ (void)q6usm_cmd(usf_xx->usc, CMD_CLOSE);
+ return rc;
+ }
+
rc = q6usm_dec_cfg_blk(usf_xx->usc,
&usf_xx->encdec_cfg);
if (rc)
@@ -1270,6 +1286,120 @@
return rc;
} /* usf_get_version */
+static int usf_set_stream_param(struct usf_xx_type *usf_xx,
+ unsigned long arg, int dir)
+{
+ struct us_stream_param_type set_stream_param;
+ struct us_client *usc = usf_xx->usc;
+ struct us_port_data *port = &usc->port[dir];
+ int rc = 0;
+
+ if (port->param_buf == NULL) {
+ pr_err("%s: parameter buffer is null\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ rc = copy_from_user(&set_stream_param,
+ (struct us_stream_param_type __user *) arg,
+ sizeof(set_stream_param));
+
+ if (rc) {
+ pr_err("%s: copy set_stream_param from user; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ if (set_stream_param.buf_size > port->param_buf_size) {
+ pr_err("%s: buf_size (%d) > maximum buf size (%d)\n",
+ __func__, set_stream_param.buf_size,
+ port->param_buf_size);
+ return -EINVAL;
+ }
+
+ if (set_stream_param.buf_size == 0) {
+ pr_err("%s: buf_size is 0\n", __func__);
+ return -EINVAL;
+ }
+
+ rc = copy_from_user(port->param_buf,
+ (uint8_t __user *) set_stream_param.pbuf,
+ set_stream_param.buf_size);
+ if (rc) {
+ pr_err("%s: copy param buf from user; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ rc = q6usm_set_us_stream_param(dir, usc, set_stream_param.module_id,
+ set_stream_param.param_id,
+ set_stream_param.buf_size);
+ if (rc) {
+ pr_err("%s: q6usm_set_us_stream_param failed; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ return rc;
+} /* usf_set_stream_param */
+
+static int usf_get_stream_param(struct usf_xx_type *usf_xx,
+ unsigned long arg, int dir)
+{
+ struct us_stream_param_type get_stream_param;
+ struct us_client *usc = usf_xx->usc;
+ struct us_port_data *port = &usc->port[dir];
+ int rc = 0;
+
+ if (port->param_buf == NULL) {
+ pr_err("%s: parameter buffer is null\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ rc = copy_from_user(&get_stream_param,
+ (struct us_stream_param_type __user *) arg,
+ sizeof(get_stream_param));
+
+ if (rc) {
+ pr_err("%s: copy get_stream_param from user; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ if (get_stream_param.buf_size > port->param_buf_size) {
+ pr_err("%s: buf_size (%d) > maximum buf size (%d)\n",
+ __func__, get_stream_param.buf_size,
+ port->param_buf_size);
+ return -EINVAL;
+ }
+
+ if (get_stream_param.buf_size == 0) {
+ pr_err("%s: buf_size is 0\n", __func__);
+ return -EINVAL;
+ }
+
+ rc = q6usm_get_us_stream_param(dir, usc, get_stream_param.module_id,
+ get_stream_param.param_id,
+ get_stream_param.buf_size);
+ if (rc) {
+ pr_err("%s: q6usm_get_us_stream_param failed; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ rc = copy_to_user((uint8_t __user *) get_stream_param.pbuf,
+ port->param_buf,
+ get_stream_param.buf_size);
+ if (rc) {
+ pr_err("%s: copy param buf to user; rc=%d\n",
+ __func__, rc);
+ return -EFAULT;
+ }
+
+ return rc;
+} /* usf_get_stream_param */
+
static long usf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int rc = 0;
@@ -1402,6 +1532,26 @@
break;
} /* US_GET_VERSION */
+ case US_SET_TX_STREAM_PARAM: {
+ rc = usf_set_stream_param(&usf->usf_tx, arg, OUT);
+ break;
+ } /* US_SET_TX_STREAM_PARAM */
+
+ case US_GET_TX_STREAM_PARAM: {
+ rc = usf_get_stream_param(&usf->usf_tx, arg, OUT);
+ break;
+ } /* US_GET_TX_STREAM_PARAM */
+
+ case US_SET_RX_STREAM_PARAM: {
+ rc = usf_set_stream_param(&usf->usf_rx, arg, IN);
+ break;
+ } /* US_SET_RX_STREAM_PARAM */
+
+ case US_GET_RX_STREAM_PARAM: {
+ rc = usf_get_stream_param(&usf->usf_rx, arg, IN);
+ break;
+ } /* US_GET_RX_STREAM_PARAM */
+
default:
pr_err("%s: unsupported IOCTL command [%d]\n",
__func__,
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c b/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
index af3c1f5..1a1d587 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
@@ -53,7 +53,7 @@
static struct usm_mmap this_mmap;
-static void q6usm_add_mmaphdr(struct us_client *usc, struct apr_hdr *hdr,
+static void q6usm_add_mmaphdr(struct apr_hdr *hdr,
uint32_t pkt_size, bool cmd_flg, u32 token)
{
hdr->hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, \
@@ -68,20 +68,20 @@
return;
}
-static int q6usm_memory_map(struct us_client *usc, uint32_t buf_add, int dir,
- uint32_t bufsz, uint32_t bufcnt)
+static int q6usm_memory_map(uint32_t buf_add, int dir, uint32_t bufsz,
+ uint32_t bufcnt, uint32_t session, uint32_t *mem_handle)
{
struct usm_cmd_memory_map_region mem_region_map;
int rc = 0;
- if ((usc == NULL) || (usc->apr == NULL) || (this_mmap.apr == NULL)) {
+ if (this_mmap.apr == NULL) {
pr_err("%s: APR handle NULL\n", __func__);
return -EINVAL;
}
- q6usm_add_mmaphdr(usc, &mem_region_map.hdr,
+ q6usm_add_mmaphdr(&mem_region_map.hdr,
sizeof(struct usm_cmd_memory_map_region), true,
- ((usc->session << 8) | dir));
+ ((session << 8) | dir));
mem_region_map.hdr.opcode = USM_CMD_SHARED_MEM_MAP_REGION;
mem_region_map.mempool_id = ADSP_MEMORY_MAP_SHMEM8_4K_POOL;
@@ -108,32 +108,29 @@
rc = -ETIME;
pr_err("%s: timeout. waited for memory_map\n", __func__);
} else {
- struct us_port_data *port = &usc->port[dir];
-
- *((uint32_t *)(port->ext)) = this_mmap.mem_handle;
+ *mem_handle = this_mmap.mem_handle;
rc = 0;
}
fail_cmd:
return rc;
}
-int q6usm_memory_unmap(struct us_client *usc, uint32_t buf_add, int dir)
+int q6usm_memory_unmap(uint32_t buf_add, int dir, uint32_t session,
+ uint32_t mem_handle)
{
struct usm_cmd_memory_unmap_region mem_unmap;
- struct us_port_data *port = &usc->port[dir];
int rc = 0;
- if ((usc == NULL) || (usc->apr == NULL) || (this_mmap.apr == NULL)) {
+ if (this_mmap.apr == NULL) {
pr_err("%s: APR handle NULL\n", __func__);
return -EINVAL;
}
- port = &usc->port[dir];
- q6usm_add_mmaphdr(usc, &mem_unmap.hdr,
+ q6usm_add_mmaphdr(&mem_unmap.hdr,
sizeof(struct usm_cmd_memory_unmap_region), true,
- ((usc->session << 8) | dir));
+ ((session << 8) | dir));
mem_unmap.hdr.opcode = USM_CMD_SHARED_MEM_UNMAP_REGION;
- mem_unmap.mem_map_handle = *((uint32_t *)(port->ext));
+ mem_unmap.mem_map_handle = mem_handle;
rc = apr_send_pkt(this_mmap.apr, (uint32_t *) &mem_unmap);
if (rc < 0) {
@@ -209,7 +206,8 @@
return 0;
}
- rc = q6usm_memory_unmap(usc, port->phys, dir);
+ rc = q6usm_memory_unmap(port->phys, dir, usc->session,
+ *((uint32_t *)port->ext));
pr_debug("%s: data[%p]phys[%p][%p]\n", __func__,
(void *)port->data, (void *)port->phys, (void *)&port->phys);
/* 4K boundary is required by the API with QDSP6 */
@@ -224,6 +222,45 @@
return rc;
}
+int q6usm_us_param_buf_free(unsigned int dir,
+ struct us_client *usc)
+{
+ struct us_port_data *port;
+ int rc = 0;
+ uint32_t size = 0;
+
+ if ((usc == NULL) ||
+ ((dir != IN) && (dir != OUT)))
+ return -EINVAL;
+
+ mutex_lock(&usc->cmd_lock);
+ port = &usc->port[dir];
+ if (port == NULL) {
+ mutex_unlock(&usc->cmd_lock);
+ return -EINVAL;
+ }
+
+ if (port->param_buf == NULL) {
+ mutex_unlock(&usc->cmd_lock);
+ return 0;
+ }
+
+ rc = q6usm_memory_unmap(port->param_phys, dir, usc->session,
+ *((uint32_t *)port->param_buf_mem_handle));
+ pr_debug("%s: data[%p]phys[%p][%p]\n", __func__,
+ (void *)port->param_buf, (void *)port->param_phys,
+ (void *)&port->param_phys);
+ /* 4K boundary is required by the API with QDSP6 */
+ size = (port->param_buf_size + MEM_4K_OFFSET) & MEM_4K_MASK;
+ dma_free_coherent(NULL, size, port->param_buf, port->param_phys);
+ port->param_buf = NULL;
+ port->param_phys = 0;
+ port->param_buf_size = 0;
+
+ mutex_unlock(&usc->cmd_lock);
+ return rc;
+}
+
void q6usm_us_client_free(struct us_client *usc)
{
int loopcnt = 0;
@@ -240,6 +277,7 @@
continue;
pr_debug("%s: loopcnt = %d\n", __func__, loopcnt);
q6usm_us_client_buf_free(loopcnt, usc);
+ q6usm_us_param_buf_free(loopcnt, usc);
}
q6usm_session_free(usc);
apr_deregister(usc->apr);
@@ -279,7 +317,7 @@
pr_err("%s: us_client allocation failed\n", __func__);
return NULL;
}
- p_mem_handle = kzalloc(sizeof(uint32_t) * 2, GFP_KERNEL);
+ p_mem_handle = kzalloc(sizeof(uint32_t) * 4, GFP_KERNEL);
if (p_mem_handle == NULL) {
pr_err("%s: p_mem_handle allocation failed\n", __func__);
kfree(usc);
@@ -320,6 +358,7 @@
mutex_init(&usc->port[lcnt].lock);
spin_lock_init(&usc->port[lcnt].dsp_lock);
usc->port[lcnt].ext = (void *)p_mem_handle++;
+ usc->port[lcnt].param_buf_mem_handle = (void *)p_mem_handle++;
pr_err("%s: usc->port[%d].ext=%p;\n",
__func__, lcnt, usc->port[lcnt].ext);
}
@@ -372,11 +411,71 @@
(void *)&port->phys);
size = (size + MEM_4K_OFFSET) & MEM_4K_MASK;
- rc = q6usm_memory_map(usc, port->phys, dir, size, 1);
+ rc = q6usm_memory_map(port->phys, dir, size, 1, usc->session,
+ (uint32_t *)port->ext);
if (rc < 0) {
pr_err("%s: CMD Memory_map failed\n", __func__);
mutex_unlock(&usc->cmd_lock);
q6usm_us_client_buf_free(dir, usc);
+ q6usm_us_param_buf_free(dir, usc);
+ } else {
+ mutex_unlock(&usc->cmd_lock);
+ rc = 0;
+ }
+
+ return rc;
+}
+
+int q6usm_us_param_buf_alloc(unsigned int dir,
+ struct us_client *usc,
+ unsigned int bufsz)
+{
+ int rc = 0;
+ struct us_port_data *port = NULL;
+ unsigned int size = 0;
+
+ if ((usc == NULL) ||
+ ((dir != IN) && (dir != OUT)) ||
+ (usc->session <= 0 || usc->session > SESSION_MAX)) {
+ pr_err("%s: wrong parameters: direction=%d, bufsz=%d\n",
+ __func__, dir, bufsz);
+ return -EINVAL;
+ }
+
+ mutex_lock(&usc->cmd_lock);
+
+ port = &usc->port[dir];
+
+ if (bufsz == 0) {
+ pr_debug("%s: bufsz=0, get/set param commands are forbidden\n",
+ __func__);
+ port->param_buf = NULL;
+ mutex_unlock(&usc->cmd_lock);
+ return rc;
+ }
+
+ port->param_buf = dma_alloc_coherent(NULL, bufsz,
+ &(port->param_phys), GFP_KERNEL);
+ if (port->param_buf == NULL) {
+ pr_err("%s: Parameter buffer allocation failed\n", __func__);
+ mutex_unlock(&usc->cmd_lock);
+ return -ENOMEM;
+ }
+
+ port->param_buf_size = bufsz;
+ pr_debug("%s: param_buf[%p]; param_phys[%p]; [%p]\n", __func__,
+ (void *)port->param_buf,
+ (void *)port->param_phys,
+ (void *)&port->param_phys);
+
+ size = (bufsz + MEM_4K_OFFSET) & MEM_4K_MASK;
+ rc = q6usm_memory_map(port->param_phys, (IN | OUT), size, 1,
+ usc->session, (uint32_t *)port->param_buf_mem_handle);
+ if (rc < 0) {
+ pr_err("%s: CMD Memory_map failed\n", __func__);
+ mutex_unlock(&usc->cmd_lock);
+ q6usm_us_client_buf_free(dir, usc);
+ q6usm_us_param_buf_free(dir, usc);
} else {
mutex_unlock(&usc->cmd_lock);
rc = 0;
@@ -471,6 +570,8 @@
case USM_STREAM_CMD_SET_ENC_PARAM:
case USM_DATA_CMD_MEDIA_FORMAT_UPDATE:
case USM_SESSION_CMD_SIGNAL_DETECT_MODE:
+ case USM_STREAM_CMD_SET_PARAM:
+ case USM_STREAM_CMD_GET_PARAM:
if (atomic_read(&usc->cmd_state)) {
atomic_set(&usc->cmd_state, 0);
wake_up(&usc->cmd_wait);
@@ -1230,6 +1331,98 @@
return rc;
}
+int q6usm_set_us_stream_param(int dir, struct us_client *usc,
+ uint32_t module_id, uint32_t param_id, uint32_t buf_size)
+{
+ int rc = 0;
+ struct usm_stream_cmd_set_param cmd_set_param;
+ struct us_port_data *port = NULL;
+
+ if ((usc == NULL) || (usc->apr == NULL)) {
+ pr_err("%s: APR handle NULL\n", __func__);
+ return -EINVAL;
+ }
+ port = &usc->port[dir];
+
+ q6usm_add_hdr(usc, &cmd_set_param.hdr,
+ (sizeof(cmd_set_param) - APR_HDR_SIZE), true);
+
+ cmd_set_param.hdr.opcode = USM_STREAM_CMD_SET_PARAM;
+ cmd_set_param.buf_size = buf_size;
+ cmd_set_param.buf_addr_msw = upper_32_bits(port->param_phys);
+ cmd_set_param.buf_addr_lsw = lower_32_bits(port->param_phys);
+ cmd_set_param.mem_map_handle =
+ *((uint32_t *)(port->param_buf_mem_handle));
+ cmd_set_param.module_id = module_id;
+ cmd_set_param.param_id = param_id;
+ cmd_set_param.hdr.token = 0;
+
+ rc = apr_send_pkt(usc->apr, (uint32_t *) &cmd_set_param);
+
+ if (rc < 0) {
+ pr_err("%s:write op[0x%x];rc[%d]\n",
+ __func__, cmd_set_param.hdr.opcode, rc);
+ }
+
+ rc = wait_event_timeout(usc->cmd_wait,
+ (atomic_read(&usc->cmd_state) == 0),
+ Q6USM_TIMEOUT_JIFFIES);
+ if (!rc) {
+ rc = -ETIME;
+ pr_err("%s: CMD_SET_PARAM: timeout=%d\n",
+ __func__, Q6USM_TIMEOUT_JIFFIES);
+ } else
+ rc = 0;
+
+ return rc;
+}
+
+int q6usm_get_us_stream_param(int dir, struct us_client *usc,
+ uint32_t module_id, uint32_t param_id, uint32_t buf_size)
+{
+ int rc = 0;
+ struct usm_stream_cmd_get_param cmd_get_param;
+ struct us_port_data *port = NULL;
+
+ if ((usc == NULL) || (usc->apr == NULL)) {
+ pr_err("%s: APR handle NULL\n", __func__);
+ return -EINVAL;
+ }
+ port = &usc->port[dir];
+
+ q6usm_add_hdr(usc, &cmd_get_param.hdr,
+ (sizeof(cmd_get_param) - APR_HDR_SIZE), true);
+
+ cmd_get_param.hdr.opcode = USM_STREAM_CMD_GET_PARAM;
+ cmd_get_param.buf_size = buf_size;
+ cmd_get_param.buf_addr_msw = upper_32_bits(port->param_phys);
+ cmd_get_param.buf_addr_lsw = lower_32_bits(port->param_phys);
+ cmd_get_param.mem_map_handle =
+ *((uint32_t *)(port->param_buf_mem_handle));
+ cmd_get_param.module_id = module_id;
+ cmd_get_param.param_id = param_id;
+ cmd_get_param.hdr.token = 0;
+
+ rc = apr_send_pkt(usc->apr, (uint32_t *) &cmd_get_param);
+
+ if (rc < 0) {
+ pr_err("%s:write op[0x%x];rc[%d]\n",
+ __func__, cmd_get_param.hdr.opcode, rc);
+ }
+
+ rc = wait_event_timeout(usc->cmd_wait,
+ (atomic_read(&usc->cmd_state) == 0),
+ Q6USM_TIMEOUT_JIFFIES);
+ if (!rc) {
+ rc = -ETIME;
+ pr_err("%s: CMD_GET_PARAM: timeout=%d\n",
+ __func__, Q6USM_TIMEOUT_JIFFIES);
+ } else
+ rc = 0;
+
+ return rc;
+}
+
static int __init q6usm_init(void)
{
pr_debug("%s\n", __func__);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 935bb9a..7ad6401 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -280,7 +280,8 @@
static void *__alloc_from_contiguous(struct device *dev, size_t size,
pgprot_t prot, struct page **ret_page,
- bool no_kernel_mapping, const void *caller);
+ const void *caller,
+ struct dma_attrs *attrs);
struct dma_pool {
size_t size;
@@ -321,7 +322,7 @@
if (IS_ENABLED(CONFIG_CMA))
ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
- false, atomic_pool_init);
+ atomic_pool_init, NULL);
else
ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
&page, NULL);
@@ -508,19 +509,22 @@
#define NO_KERNEL_MAPPING_DUMMY 0x2222
static void *__alloc_from_contiguous(struct device *dev, size_t size,
pgprot_t prot, struct page **ret_page,
- bool no_kernel_mapping,
- const void *caller)
+ const void *caller,
+ struct dma_attrs *attrs)
{
unsigned long order = get_order(size);
size_t count = size >> PAGE_SHIFT;
struct page *page;
void *ptr;
+ bool no_kernel_mapping = dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING,
+ attrs);
page = dma_alloc_from_contiguous(dev, count, order);
if (!page)
return NULL;
- __dma_clear_buffer(page, size);
+ if (!dma_get_attr(DMA_ATTR_SKIP_ZEROING, attrs))
+ __dma_clear_buffer(page, size);
if (!PageHighMem(page)) {
__dma_remap(page, size, prot, no_kernel_mapping);
@@ -601,7 +605,7 @@
static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
gfp_t gfp, pgprot_t prot, const void *caller,
- bool no_kernel_mapping)
+ struct dma_attrs *attrs)
{
u64 mask = get_coherent_dma_mask(dev);
struct page *page;
@@ -642,7 +646,7 @@
addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
else
addr = __alloc_from_contiguous(dev, size, prot, &page,
- no_kernel_mapping, caller);
+ caller, attrs);
if (addr)
*handle = pfn_to_dma(dev, page_to_pfn(page));
@@ -659,14 +663,12 @@
{
pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
void *memory;
- bool no_kernel_mapping = dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING,
- attrs);
if (dma_alloc_from_coherent(dev, size, handle, &memory))
return memory;
return __dma_alloc(dev, size, handle, gfp, prot,
- __builtin_return_address(0), no_kernel_mapping);
+ __builtin_return_address(0), attrs);
}
/*
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3d52735..947e229 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1519,8 +1519,25 @@
const struct mem_type *type)
{
pte_t *pte, *start_pte;
+ pmd_t *base_pmd;
- start_pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
+ base_pmd = pmd_offset(
+ pud_offset(pgd_offset(&init_mm, addr), addr), addr);
+
+ if (pmd_none(*base_pmd) || pmd_bad(*base_pmd)) {
+ start_pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
+#ifndef CONFIG_ARM_LPAE
+ /*
+ * Following is needed when new pte is allocated for pmd[1]
+ * cases, which may happen when base (start) address falls
+ * under pmd[1].
+ */
+ if (addr & SECTION_SIZE)
+ start_pte += pte_index(addr);
+#endif
+ } else {
+ start_pte = pte_offset_kernel(base_pmd, addr);
+ }
pte = start_pte;
diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
index 2adcbbc..4745406 100644
--- a/drivers/base/dma-contiguous.c
+++ b/drivers/base/dma-contiguous.c
@@ -47,6 +47,7 @@
unsigned long base_pfn;
unsigned long count;
unsigned long *bitmap;
+ bool in_system;
struct mutex lock;
};
@@ -60,6 +61,7 @@
unsigned long size;
struct cma *cma;
const char *name;
+ bool to_system;
} cma_areas[MAX_CMA_AREAS];
static unsigned cma_area_count;
@@ -170,7 +172,7 @@
}
static __init struct cma *cma_create_area(unsigned long base_pfn,
- unsigned long count)
+ unsigned long count, bool system)
{
int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
struct cma *cma;
@@ -184,14 +186,17 @@
cma->base_pfn = base_pfn;
cma->count = count;
+ cma->in_system = system;
cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
if (!cma->bitmap)
goto no_mem;
- ret = cma_activate_area(base_pfn, count);
- if (ret)
- goto error;
+ if (cma->in_system) {
+ ret = cma_activate_area(base_pfn, count);
+ if (ret)
+ goto error;
+ }
mutex_init(&cma->lock);
pr_debug("%s: returned %p\n", __func__, (void *)cma);
@@ -214,6 +219,7 @@
unsigned long len;
__be32 *prop;
char *name;
+ bool in_system;
phys_addr_t limit = MEMBLOCK_ALLOC_ANYWHERE;
if (!of_get_flat_dt_prop(node, "linux,contiguous-region", NULL))
@@ -227,6 +233,8 @@
size = be32_to_cpu(prop[1]);
name = of_get_flat_dt_prop(node, "label", NULL);
+ in_system =
+ of_get_flat_dt_prop(node, "linux,reserve-region", NULL) ? 0 : 1;
prop = of_get_flat_dt_prop(node, "linux,memory-limit", NULL);
if (prop)
@@ -234,7 +242,8 @@
pr_info("Found %s, memory base %lx, size %ld MiB, limit %pa\n", uname,
(unsigned long)base, (unsigned long)size / SZ_1M, &limit);
- dma_contiguous_reserve_area(size, &base, limit, name);
+ dma_contiguous_reserve_area(size, &base, limit, name,
+ in_system);
return 0;
}
@@ -275,8 +284,8 @@
pr_debug("%s: reserving %ld MiB for global area\n", __func__,
(unsigned long)sel_size / SZ_1M);
- if (dma_contiguous_reserve_area(sel_size, &base, limit, NULL)
- == 0)
+ if (dma_contiguous_reserve_area(sel_size, &base, limit, NULL,
+ true) == 0)
dma_contiguous_def_base = base;
}
#ifdef CONFIG_OF
@@ -299,7 +308,8 @@
* devices.
*/
int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t *res_base,
- phys_addr_t limit, const char *name)
+ phys_addr_t limit, const char *name,
+ bool to_system)
{
phys_addr_t base = *res_base;
phys_addr_t alignment;
@@ -352,6 +362,7 @@
cma_areas[cma_area_count].base = base;
cma_areas[cma_area_count].size = size;
cma_areas[cma_area_count].name = name;
+ cma_areas[cma_area_count].to_system = to_system;
cma_area_count++;
*res_base = base;
@@ -434,8 +445,9 @@
for (i = 0; i < cma_area_count; i++) {
phys_addr_t base = PFN_DOWN(cma_areas[i].base);
unsigned int count = cma_areas[i].size >> PAGE_SHIFT;
+ bool system = cma_areas[i].to_system;
- cma = cma_create_area(base, count);
+ cma = cma_create_area(base, count, system);
if (!IS_ERR(cma))
cma_areas[i].cma = cma;
}
@@ -485,7 +497,7 @@
unsigned long mask, pfn, pageno, start = 0;
struct cma *cma = dev_get_cma_area(dev);
struct page *page = NULL;
- int ret;
+ int ret = 0;
int tries = 0;
if (!cma || !cma->count)
@@ -521,7 +533,8 @@
pfn = cma->base_pfn + pageno;
mutex_lock(&cma_mutex);
- ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
+ if (cma->in_system)
+ ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
mutex_unlock(&cma_mutex);
if (ret == 0) {
page = pfn_to_page(pfn);
@@ -573,7 +586,8 @@
VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
- free_contig_range(pfn, count);
+ if (cma->in_system)
+ free_contig_range(pfn, count);
clear_cma_bitmap(cma, pfn, count);
return true;
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index ba13ec1..93e932a 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -1508,8 +1508,7 @@
return err;
}
if (pkt_type == CALLBACK_DATA_TYPE) {
- if (payload_size > driver->itemsize ||
- payload_size <= MIN_SIZ_ALLOW) {
+ if (payload_size > driver->itemsize) {
pr_err("diag: Dropping packet, invalid packet size. Current payload size %d\n",
payload_size);
driver->dropped_count++;
@@ -1541,6 +1540,11 @@
return ret;
}
/* The packet is for the remote processor */
+ if (payload_size <= MIN_SIZ_ALLOW) {
+ pr_err("diag: Integer underflow in %s, payload size: %d",
+ __func__, payload_size);
+ return -EBADMSG;
+ }
token_offset = 4;
payload_size -= 4;
buf += 4;
diff --git a/drivers/coresight/coresight-tmc.c b/drivers/coresight/coresight-tmc.c
index 0c7c9e0..936541f 100644
--- a/drivers/coresight/coresight-tmc.c
+++ b/drivers/coresight/coresight-tmc.c
@@ -640,7 +640,6 @@
char *hdr;
char *bufp;
uint32_t read_data;
- int i;
memwidth = BMVAL(tmc_readl(drvdata, CORESIGHT_DEVID), 8, 10);
if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
@@ -654,16 +653,22 @@
bufp = drvdata->buf;
while (1) {
- for (i = 0; i < memwords; i++) {
- read_data = tmc_readl_no_log(drvdata, TMC_RRD);
- if (read_data == 0xFFFFFFFF)
- goto out;
- memcpy(bufp, &read_data, BYTES_PER_WORD);
- bufp += BYTES_PER_WORD;
+ read_data = tmc_readl_no_log(drvdata, TMC_RRD);
+ if (read_data == 0xFFFFFFFF)
+ goto out;
+ if ((bufp - drvdata->buf) >= drvdata->size) {
+ dev_err(drvdata->dev, "ETF-ETB end marker missing\n");
+ goto out;
}
+ memcpy(bufp, &read_data, BYTES_PER_WORD);
+ bufp += BYTES_PER_WORD;
}
out:
+ if ((bufp - drvdata->buf) % (memwords * BYTES_PER_WORD))
+ dev_dbg(drvdata->dev, "ETF-ETB data is not %lx bytes aligned\n",
+ (unsigned long) memwords * BYTES_PER_WORD);
+
if (drvdata->aborting) {
hdr = drvdata->buf - PAGE_SIZE;
*(uint32_t *)(hdr + TMC_ETFETB_DUMP_MAGIC_OFF) =
diff --git a/drivers/crypto/msm/qce.c b/drivers/crypto/msm/qce.c
index 8037187..d11a831 100644
--- a/drivers/crypto/msm/qce.c
+++ b/drivers/crypto/msm/qce.c
@@ -1,6 +1,6 @@
/* Qualcomm Crypto Engine driver.
*
- * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -422,7 +422,7 @@
{
unsigned n;
- n = len / sizeof(uint32_t) ;
+ n = len / sizeof(uint32_t);
for (; n > 0; n--) {
*iv = ((*b << 24) & 0xff000000) |
(((*(b+1)) << 16) & 0xff0000) |
@@ -436,12 +436,12 @@
if (n == 3) {
*iv = ((*b << 24) & 0xff000000) |
(((*(b+1)) << 16) & 0xff0000) |
- (((*(b+2)) << 8) & 0xff00) ;
+ (((*(b+2)) << 8) & 0xff00);
} else if (n == 2) {
*iv = ((*b << 24) & 0xff000000) |
- (((*(b+1)) << 16) & 0xff0000) ;
+ (((*(b+1)) << 16) & 0xff0000);
} else if (n == 1) {
- *iv = ((*b << 24) & 0xff000000) ;
+ *iv = ((*b << 24) & 0xff000000);
}
}
@@ -1819,7 +1819,7 @@
}
};
-static int _ce_f9_setup(struct qce_device *pce_dev, struct qce_f9_req * req)
+static int _ce_f9_setup(struct qce_device *pce_dev, struct qce_f9_req *req)
{
uint32_t cfg;
uint32_t ikey[OTA_KEY_SIZE/sizeof(uint32_t)];
@@ -1846,7 +1846,7 @@
if (req->algorithm == QCE_OTA_ALGO_KASUMI)
cfg |= (CRYPTO_AUTH_SIZE_UIA1 << CRYPTO_AUTH_SIZE);
else
- cfg |= (CRYPTO_AUTH_SIZE_UIA2 << CRYPTO_AUTH_SIZE) ;
+ cfg |= (CRYPTO_AUTH_SIZE_UIA2 << CRYPTO_AUTH_SIZE);
if (req->direction == QCE_OTA_DIR_DOWNLINK)
cfg |= 1 << CRYPTO_F9_DIRECTION;
@@ -1885,7 +1885,7 @@
if (req->algorithm == QCE_OTA_ALGO_KASUMI)
cfg |= (CRYPTO_ENCR_KEY_SZ_UEA1 << CRYPTO_ENCR_KEY_SZ);
else
- cfg |= (CRYPTO_ENCR_KEY_SZ_UEA2 << CRYPTO_ENCR_KEY_SZ) ;
+ cfg |= (CRYPTO_ENCR_KEY_SZ_UEA2 << CRYPTO_ENCR_KEY_SZ);
if (key_stream_mode)
cfg |= 1 << CRYPTO_F8_KEYSTREAM_ENABLE;
if (req->direction == QCE_OTA_DIR_DOWNLINK)
@@ -1932,6 +1932,9 @@
return 0;
};
+struct qce_pm_table qce_pm_table = {NULL, NULL};
+EXPORT_SYMBOL(qce_pm_table);
+
int qce_aead_req(void *handle, struct qce_req *q_req)
{
struct qce_device *pce_dev = (struct qce_device *) handle;
@@ -2555,7 +2558,7 @@
rc = _ce_f8_setup(pce_dev, req, false, num_pkt, cipher_start,
cipher_size);
if (rc)
- goto bad ;
+ goto bad;
/* setup for callback, and issue command to adm */
pce_dev->areq = cookie;
diff --git a/drivers/crypto/msm/qce.h b/drivers/crypto/msm/qce.h
index ff90db7..6ba5063 100644
--- a/drivers/crypto/msm/qce.h
+++ b/drivers/crypto/msm/qce.h
@@ -166,6 +166,13 @@
unsigned int flags;
};
+struct qce_pm_table {
+ int (*suspend)(void *handle);
+ int (*resume)(void *handle);
+};
+
+extern struct qce_pm_table qce_pm_table;
+
void *qce_open(struct platform_device *pdev, int *rc);
int qce_close(void *handle);
int qce_aead_req(void *handle, struct qce_req *req);
diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c
index f9f6646..ad7dd31 100644
--- a/drivers/crypto/msm/qce50.c
+++ b/drivers/crypto/msm/qce50.c
@@ -127,7 +127,7 @@
{
unsigned n;
- n = len / sizeof(uint32_t) ;
+ n = len / sizeof(uint32_t);
for (; n > 0; n--) {
*iv = ((*b << 24) & 0xff000000) |
(((*(b+1)) << 16) & 0xff0000) |
@@ -141,12 +141,12 @@
if (n == 3) {
*iv = ((*b << 24) & 0xff000000) |
(((*(b+1)) << 16) & 0xff0000) |
- (((*(b+2)) << 8) & 0xff00) ;
+ (((*(b+2)) << 8) & 0xff00);
} else if (n == 2) {
*iv = ((*b << 24) & 0xff000000) |
- (((*(b+1)) << 16) & 0xff0000) ;
+ (((*(b+1)) << 16) & 0xff0000);
} else if (n == 1) {
- *iv = ((*b << 24) & 0xff000000) ;
+ *iv = ((*b << 24) & 0xff000000);
}
}
@@ -2645,7 +2645,7 @@
struct sps_bam_props bam = {0};
struct bam_registration_info *pbam = NULL;
struct bam_registration_info *p;
- uint32_t bam_cfg = 0 ;
+ uint32_t bam_cfg = 0;
mutex_lock(&bam_register_lock);
@@ -2955,7 +2955,7 @@
(*cmd_ptr)->mask = 0xFFFFFFFF;
if (populate != NULL)
*populate = *cmd_ptr;
- (*cmd_ptr)++ ;
+ (*cmd_ptr)++;
}
static int _setup_cipher_aes_cmdlistptrs(struct qce_device *pdev,
@@ -4405,6 +4405,65 @@
return rc;
}
+static int _qce_suspend(void *handle)
+{
+ struct qce_device *pce_dev = (struct qce_device *)handle;
+ struct sps_pipe *sps_pipe_info;
+
+ if (handle == NULL)
+ return -ENODEV;
+
+ qce_enable_clk(pce_dev);
+
+ sps_pipe_info = pce_dev->ce_sps.consumer.pipe;
+ sps_disconnect(sps_pipe_info);
+
+ sps_pipe_info = pce_dev->ce_sps.producer.pipe;
+ sps_disconnect(sps_pipe_info);
+
+ qce_disable_clk(pce_dev);
+ return 0;
+}
+
+static int _qce_resume(void *handle)
+{
+ struct qce_device *pce_dev = (struct qce_device *)handle;
+ struct sps_pipe *sps_pipe_info;
+ struct sps_connect *sps_connect_info;
+ int rc;
+
+ if (handle == NULL)
+ return -ENODEV;
+
+ qce_enable_clk(pce_dev);
+
+ sps_pipe_info = pce_dev->ce_sps.consumer.pipe;
+ sps_connect_info = &pce_dev->ce_sps.consumer.connect;
+ memset(sps_connect_info->desc.base, 0x00, sps_connect_info->desc.size);
+ rc = sps_connect(sps_pipe_info, sps_connect_info);
+ if (rc) {
+ pr_err("sps_connect() fail pipe_handle=0x%x, rc = %d\n",
+ (u32)sps_pipe_info, rc);
+ return rc;
+ }
+ sps_pipe_info = pce_dev->ce_sps.producer.pipe;
+ sps_connect_info = &pce_dev->ce_sps.producer.connect;
+ memset(sps_connect_info->desc.base, 0x00, sps_connect_info->desc.size);
+ rc = sps_connect(sps_pipe_info, sps_connect_info);
+ if (rc)
+ pr_err("sps_connect() fail pipe_handle=0x%x, rc = %d\n",
+ (u32)sps_pipe_info, rc);
+
+ pce_dev->ce_sps.out_transfer.user = pce_dev->ce_sps.producer.pipe;
+ pce_dev->ce_sps.in_transfer.user = pce_dev->ce_sps.consumer.pipe;
+
+ qce_disable_clk(pce_dev);
+ return rc;
+}
+
+struct qce_pm_table qce_pm_table = {_qce_suspend, _qce_resume};
+EXPORT_SYMBOL(qce_pm_table);
+
int qce_aead_req(void *handle, struct qce_req *q_req)
{
struct qce_device *pce_dev;
@@ -5469,5 +5528,6 @@
}
EXPORT_SYMBOL(qce_hw_support);
+
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Crypto Engine driver");
diff --git a/drivers/crypto/msm/qcrypto.c b/drivers/crypto/msm/qcrypto.c
index d7f0bcb..c247189 100644
--- a/drivers/crypto/msm/qcrypto.c
+++ b/drivers/crypto/msm/qcrypto.c
@@ -58,6 +58,14 @@
#define QCRYPTO_HIGH_BANDWIDTH_TIMEOUT 1000
+enum qcrypto_bus_state {
+ BUS_NO_BANDWIDTH = 0,
+ BUS_HAS_BANDWIDTH,
+ BUS_BANDWIDTH_RELEASING,
+ BUS_BANDWIDTH_ALLOCATING,
+ BUS_SUSPENDED,
+};
+
struct crypto_stat {
u64 aead_sha1_aes_enc;
u64 aead_sha1_aes_dec;
@@ -114,10 +122,19 @@
u32 unit;
u32 ce_device;
unsigned int signature;
- uint32_t high_bw_req_count;
- bool high_bw_req;
- struct timer_list bw_scale_down_timer;
- struct work_struct low_bw_req_ws;
+
+ enum qcrypto_bus_state bw_state;
+ bool high_bw_req;
+ struct timer_list bw_reaper_timer;
+ struct work_struct bw_reaper_ws;
+ struct work_struct bw_allocate_ws;
+
+ /* engine execution sequence number */
+ u32 active_seq;
+ /* last QCRYPTO_HIGH_BANDWIDTH_TIMEOUT active_seq */
+ u32 last_active_seq;
+
+ bool check_flag;
};
struct crypto_priv {
@@ -127,7 +144,7 @@
/* CE features/algorithms supported by HW engine*/
struct ce_hw_support ce_support;
- /* the lock protects queue and req*/
+ /* the lock protects crypto queue and req */
spinlock_t lock;
/* list of registered algorithms */
@@ -141,13 +158,13 @@
struct list_head engine_list; /* list of qcrypto engines */
int32_t total_units; /* total units of engines */
struct mutex engine_lock;
+
struct crypto_engine *next_engine; /* next assign engine */
struct crypto_queue req_queue; /*
* request queue for those requests
* that waiting for an available
* engine.
*/
-
};
static struct crypto_priv qcrypto_dev;
static struct crypto_engine *_qcrypto_static_assign_engine(
@@ -433,11 +450,12 @@
{
int ret = 0;
- if (high_bw_req && pengine->high_bw_req == false) {
+ if (high_bw_req) {
+ pm_stay_awake(&pengine->pdev->dev);
ret = qce_enable_clk(pengine->qce);
if (ret) {
pr_err("%s Unable enable clk\n", __func__);
- return;
+ goto clk_err;
}
ret = msm_bus_scale_client_update_request(
pengine->bus_scale_handle, 1);
@@ -445,16 +463,18 @@
pr_err("%s Unable to set to high bandwidth\n",
__func__);
qce_disable_clk(pengine->qce);
- return;
+ goto clk_err;
}
- pengine->high_bw_req = true;
- } else if (high_bw_req == false && pengine->high_bw_req == true) {
+
+
+ } else {
+
ret = msm_bus_scale_client_update_request(
pengine->bus_scale_handle, 0);
if (ret) {
pr_err("%s Unable to set to low bandwidth\n",
__func__);
- return;
+ goto clk_err;
}
ret = qce_disable_clk(pengine->qce);
if (ret) {
@@ -464,67 +484,119 @@
if (ret)
pr_err("%s Unable to set to high bandwidth\n",
__func__);
- return;
+ goto clk_err;
}
- pengine->high_bw_req = false;
+ pm_relax(&pengine->pdev->dev);
}
+ return;
+clk_err:
+ pm_relax(&pengine->pdev->dev);
+ return;
+
}
-static void qcrypto_bw_scale_down_timer_callback(unsigned long data)
+static void qcrypto_bw_reaper_timer_callback(unsigned long data)
{
struct crypto_engine *pengine = (struct crypto_engine *)data;
- schedule_work(&pengine->low_bw_req_ws);
+ schedule_work(&pengine->bw_reaper_ws);
return;
}
static void qcrypto_bw_set_timeout(struct crypto_engine *pengine)
{
- del_timer_sync(&(pengine->bw_scale_down_timer));
- pengine->bw_scale_down_timer.data =
+ pengine->bw_reaper_timer.data =
(unsigned long)(pengine);
- pengine->bw_scale_down_timer.expires = jiffies +
+ pengine->bw_reaper_timer.expires = jiffies +
msecs_to_jiffies(QCRYPTO_HIGH_BANDWIDTH_TIMEOUT);
- add_timer(&(pengine->bw_scale_down_timer));
+ add_timer(&(pengine->bw_reaper_timer));
}
-static void qcrypto_ce_bw_scaling_req(struct crypto_priv *cp,
- bool high_bw_req)
+static void qcrypto_ce_bw_allocate_req(struct crypto_engine *pengine)
{
- struct crypto_engine *pengine;
-
- if (cp->platform_support.bus_scale_table == NULL)
- return;
- mutex_lock(&cp->engine_lock);
- list_for_each_entry(pengine, &cp->engine_list, elist) {
- if (high_bw_req) {
- if (pengine->high_bw_req_count == 0)
- qcrypto_ce_set_bus(pengine, true);
- pengine->high_bw_req_count++;
- } else {
- pengine->high_bw_req_count--;
- if (pengine->high_bw_req_count == 0)
- qcrypto_bw_set_timeout(pengine);
- }
- }
- mutex_unlock(&cp->engine_lock);
-}
-
-static void qcrypto_low_bw_req_work(struct work_struct *work)
-{
- struct crypto_engine *pengine = container_of(work,
- struct crypto_engine, low_bw_req_ws);
-
- mutex_lock(&pengine->pcp->engine_lock);
- if (pengine->high_bw_req_count == 0)
- qcrypto_ce_set_bus(pengine, false);
- mutex_unlock(&pengine->pcp->engine_lock);
+ schedule_work(&pengine->bw_allocate_ws);
}
static int _start_qcrypto_process(struct crypto_priv *cp,
struct crypto_engine *pengine);
+static void qcrypto_bw_allocate_work(struct work_struct *work)
+{
+ struct crypto_engine *pengine = container_of(work,
+ struct crypto_engine, bw_allocate_ws);
+ unsigned long flags;
+ struct crypto_priv *cp = pengine->pcp;
+
+ spin_lock_irqsave(&cp->lock, flags);
+ pengine->bw_state = BUS_BANDWIDTH_ALLOCATING;
+ spin_unlock_irqrestore(&cp->lock, flags);
+
+ qcrypto_ce_set_bus(pengine, true);
+
+ spin_lock_irqsave(&cp->lock, flags);
+ pengine->bw_state = BUS_HAS_BANDWIDTH;
+ pengine->high_bw_req = false;
+ pengine->active_seq++;
+ pengine->check_flag = true;
+ spin_unlock_irqrestore(&cp->lock, flags);
+ _start_qcrypto_process(cp, pengine);
+};
+
+static void qcrypto_bw_reaper_work(struct work_struct *work)
+{
+ struct crypto_engine *pengine = container_of(work,
+ struct crypto_engine, bw_reaper_ws);
+ struct crypto_priv *cp = pengine->pcp;
+ unsigned long flags;
+ u32 active_seq;
+ bool restart = false;
+
+ spin_lock_irqsave(&cp->lock, flags);
+ active_seq = pengine->active_seq;
+ if (pengine->bw_state == BUS_HAS_BANDWIDTH &&
+ (active_seq == pengine->last_active_seq)) {
+
+ /* check if engine is stuck */
+ if (pengine->req) {
+ if (pengine->check_flag)
+ dev_err(&pengine->pdev->dev,
+ "The engine appears to be stuck seq %d req %p.\n",
+ active_seq, pengine->req);
+ pengine->check_flag = false;
+ goto ret;
+ }
+ if (cp->platform_support.bus_scale_table == NULL)
+ goto ret;
+ pengine->bw_state = BUS_BANDWIDTH_RELEASING;
+ spin_unlock_irqrestore(&cp->lock, flags);
+
+ qcrypto_ce_set_bus(pengine, false);
+
+ spin_lock_irqsave(&cp->lock, flags);
+
+ if (pengine->high_bw_req == true) {
+ /* we got request while we are disabling clock */
+ pengine->bw_state = BUS_BANDWIDTH_ALLOCATING;
+ spin_unlock_irqrestore(&cp->lock, flags);
+
+ qcrypto_ce_set_bus(pengine, true);
+
+ spin_lock_irqsave(&cp->lock, flags);
+ pengine->bw_state = BUS_HAS_BANDWIDTH;
+ pengine->high_bw_req = false;
+ restart = true;
+ } else
+ pengine->bw_state = BUS_NO_BANDWIDTH;
+ }
+ret:
+ pengine->last_active_seq = active_seq;
+ spin_unlock_irqrestore(&cp->lock, flags);
+ if (restart)
+ _start_qcrypto_process(cp, pengine);
+ qcrypto_bw_set_timeout(pengine);
+}
+
static int qcrypto_count_sg(struct scatterlist *sg, int nbytes)
{
int i;
@@ -625,7 +697,6 @@
return -ENODEV;
} else
ctx->pengine = NULL;
- qcrypto_ce_bw_scaling_req(ctx->cp, true);
INIT_LIST_HEAD(&ctx->rsp_queue);
return 0;
};
@@ -650,7 +721,6 @@
return -ENODEV;
} else
sha_ctx->pengine = NULL;
- qcrypto_ce_bw_scaling_req(sha_ctx->cp, true);
INIT_LIST_HEAD(&sha_ctx->rsp_queue);
return 0;
};
@@ -665,7 +735,6 @@
ahash_request_free(sha_ctx->ahash_req);
sha_ctx->ahash_req = NULL;
}
- qcrypto_ce_bw_scaling_req(sha_ctx->cp, false);
};
@@ -716,7 +785,6 @@
if (!list_empty(&ctx->rsp_queue))
pr_err("_qcrypto__cra_ablkcipher_exit: requests still outstanding");
- qcrypto_ce_bw_scaling_req(ctx->cp, false);
};
static void _qcrypto_cra_aead_exit(struct crypto_tfm *tfm)
@@ -725,7 +793,6 @@
if (!list_empty(&ctx->rsp_queue))
pr_err("_qcrypto__cra_aead_exit: requests still outstanding");
- qcrypto_ce_bw_scaling_req(ctx->cp, false);
};
static int _disp_stats(int id)
@@ -875,8 +942,9 @@
cp->total_units--;
tasklet_kill(&pengine->done_tasklet);
- cancel_work_sync(&pengine->low_bw_req_ws);
- del_timer_sync(&pengine->bw_scale_down_timer);
+ cancel_work_sync(&pengine->bw_reaper_ws);
+ cancel_work_sync(&pengine->bw_allocate_ws);
+ del_timer_sync(&pengine->bw_reaper_timer);
if (pengine->bus_scale_handle != 0)
msm_bus_scale_unregister_client(pengine->bus_scale_handle);
@@ -1856,6 +1924,8 @@
arsp->async_req = async_req;
pengine->req = async_req;
pengine->arsp = arsp;
+ pengine->active_seq++;
+ pengine->check_flag = true;
spin_unlock_irqrestore(&cp->lock, flags);
if (backlog_eng)
@@ -1923,16 +1993,40 @@
}
spin_lock_irqsave(&cp->lock, flags);
+
if (pengine) {
ret = crypto_enqueue_request(&pengine->req_queue, req);
} else {
ret = crypto_enqueue_request(&cp->req_queue, req);
pengine = _avail_eng(cp);
}
+ if (pengine) {
+ switch (pengine->bw_state) {
+ case BUS_NO_BANDWIDTH:
+ if (pengine->high_bw_req == false) {
+ qcrypto_ce_bw_allocate_req(pengine);
+ pengine->high_bw_req = true;
+ }
+ pengine = NULL;
+ break;
+ case BUS_HAS_BANDWIDTH:
+ break;
+ case BUS_BANDWIDTH_RELEASING:
+ pengine->high_bw_req = true;
+ pengine = NULL;
+ break;
+ case BUS_BANDWIDTH_ALLOCATING:
+ pengine = NULL;
+ break;
+ case BUS_SUSPENDED:
+ default:
+ pengine = NULL;
+ break;
+ }
+ }
spin_unlock_irqrestore(&cp->lock, flags);
if (pengine)
_start_qcrypto_process(cp, pengine);
-
return ret;
}
@@ -4163,12 +4257,17 @@
pengine->req = NULL;
pengine->signature = 0xdeadbeef;
- pengine->high_bw_req_count = 0;
+ init_timer(&(pengine->bw_reaper_timer));
+ INIT_WORK(&pengine->bw_reaper_ws, qcrypto_bw_reaper_work);
+ pengine->bw_reaper_timer.function =
+ qcrypto_bw_reaper_timer_callback;
+ INIT_WORK(&pengine->bw_allocate_ws, qcrypto_bw_allocate_work);
pengine->high_bw_req = false;
- init_timer(&(pengine->bw_scale_down_timer));
- INIT_WORK(&pengine->low_bw_req_ws, qcrypto_low_bw_req_work);
- pengine->bw_scale_down_timer.function =
- qcrypto_bw_scale_down_timer_callback;
+ pengine->active_seq = 0;
+ pengine->last_active_seq = 0;
+ pengine->check_flag = false;
+ qcrypto_bw_set_timeout(pengine);
+
tasklet_init(&pengine->done_tasklet, req_done, (unsigned long)pengine);
crypto_init_queue(&pengine->req_queue, MSM_QCRYPTO_REQ_QUEUE_LENGTH);
@@ -4208,7 +4307,9 @@
platform_support->bus_scale_table;
cp->platform_support.sha_hmac = platform_support->sha_hmac;
}
+
pengine->bus_scale_handle = 0;
+
if (cp->platform_support.bus_scale_table != NULL) {
pengine->bus_scale_handle =
msm_bus_scale_register_client(
@@ -4220,6 +4321,9 @@
rc = -ENOMEM;
goto err;
}
+ pengine->bw_state = BUS_NO_BANDWIDTH;
+ } else {
+ pengine->bw_state = BUS_HAS_BANDWIDTH;
}
if (cp->total_units != 1) {
@@ -4486,12 +4590,12 @@
return rc;
};
-
static int _qcrypto_suspend(struct platform_device *pdev, pm_message_t state)
{
int ret = 0;
struct crypto_engine *pengine;
struct crypto_priv *cp;
+ unsigned long flags;
pengine = platform_get_drvdata(pdev);
if (!pengine)
@@ -4504,42 +4608,39 @@
cp = pengine->pcp;
if (!cp->ce_support.clk_mgmt_sus_res)
return 0;
-
- mutex_lock(&cp->engine_lock);
-
- if (pengine->high_bw_req) {
- del_timer_sync(&(pengine->bw_scale_down_timer));
- ret = msm_bus_scale_client_update_request(
- pengine->bus_scale_handle, 0);
- if (ret) {
- dev_err(&pdev->dev, "%s Unable to set to low bandwidth\n",
- __func__);
- mutex_unlock(&cp->engine_lock);
- return ret;
- }
- ret = qce_disable_clk(pengine->qce);
- if (ret) {
- pr_err("%s Unable disable clk\n", __func__);
- ret = msm_bus_scale_client_update_request(
- pengine->bus_scale_handle, 1);
- if (ret)
- dev_err(&pdev->dev,
- "%s Unable to set to high bandwidth\n",
- __func__);
- mutex_unlock(&cp->engine_lock);
- return ret;
- }
+ spin_lock_irqsave(&cp->lock, flags);
+ switch (pengine->bw_state) {
+ case BUS_NO_BANDWIDTH:
+ if (pengine->high_bw_req == false)
+ pengine->bw_state = BUS_SUSPENDED;
+ else
+ ret = -EBUSY;
+ break;
+ case BUS_HAS_BANDWIDTH:
+ case BUS_BANDWIDTH_RELEASING:
+ case BUS_BANDWIDTH_ALLOCATING:
+ case BUS_SUSPENDED:
+ default:
+ ret = -EBUSY;
+ break;
}
- mutex_unlock(&cp->engine_lock);
- return 0;
+ spin_unlock_irqrestore(&cp->lock, flags);
+ if (ret)
+ return ret;
+ else {
+ if (qce_pm_table.suspend)
+ qce_pm_table.suspend(pengine->qce);
+ return 0;
+ }
}
static int _qcrypto_resume(struct platform_device *pdev)
{
- int ret = 0;
struct crypto_engine *pengine;
struct crypto_priv *cp;
+ unsigned long flags;
+ bool restart = false;
pengine = platform_get_drvdata(pdev);
@@ -4550,33 +4651,26 @@
if (!cp->ce_support.clk_mgmt_sus_res)
return 0;
- mutex_lock(&cp->engine_lock);
- if (pengine->high_bw_req) {
- ret = qce_enable_clk(pengine->qce);
- if (ret) {
- dev_err(&pdev->dev, "%s Unable to enable clk\n",
- __func__);
- mutex_unlock(&cp->engine_lock);
- return ret;
- }
- ret = msm_bus_scale_client_update_request(
- pengine->bus_scale_handle, 1);
- if (ret) {
- dev_err(&pdev->dev,
- "%s Unable to set to high bandwidth\n",
- __func__);
- qce_disable_clk(pengine->qce);
- mutex_unlock(&cp->engine_lock);
- return ret;
- }
- pengine->bw_scale_down_timer.data =
- (unsigned long)(pengine);
- pengine->bw_scale_down_timer.expires = jiffies +
- msecs_to_jiffies(QCRYPTO_HIGH_BANDWIDTH_TIMEOUT);
- add_timer(&(pengine->bw_scale_down_timer));
- }
+ spin_lock_irqsave(&cp->lock, flags);
+ if (pengine->bw_state == BUS_SUSPENDED) {
+ pengine->bw_state = BUS_BANDWIDTH_ALLOCATING;
+ spin_unlock_irqrestore(&cp->lock, flags);
- mutex_unlock(&cp->engine_lock);
+ if (qce_pm_table.resume)
+ qce_pm_table.resume(pengine->qce);
+
+ qcrypto_ce_set_bus(pengine, true);
+
+ spin_lock_irqsave(&cp->lock, flags);
+ pengine->bw_state = BUS_HAS_BANDWIDTH;
+ pengine->high_bw_req = false;
+ restart = true;
+ pengine->active_seq++;
+ pengine->check_flag = true;
+ }
+ spin_unlock_irqrestore(&cp->lock, flags);
+ if (restart)
+ _start_qcrypto_process(cp, pengine);
return 0;
}
diff --git a/drivers/gpu/ion/ion_cma_secure_heap.c b/drivers/gpu/ion/ion_cma_secure_heap.c
index da68d05..048dc56 100644
--- a/drivers/gpu/ion/ion_cma_secure_heap.c
+++ b/drivers/gpu/ion/ion_cma_secure_heap.c
@@ -136,6 +136,7 @@
}
dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+ dma_set_attr(DMA_ATTR_SKIP_ZEROING, &attrs);
cpu_addr = dma_alloc_attrs(sheap->dev, len, &handle, GFP_KERNEL,
&attrs);
diff --git a/drivers/hwmon/qpnp-adc-common.c b/drivers/hwmon/qpnp-adc-common.c
index 37a11d2..96b058b 100644
--- a/drivers/hwmon/qpnp-adc-common.c
+++ b/drivers/hwmon/qpnp-adc-common.c
@@ -814,17 +814,22 @@
return -EINVAL;
scale_voltage = (adc_code -
- chan_properties->adc_graph[CALIB_ABSOLUTE].adc_gnd)
- * chan_properties->adc_graph[CALIB_ABSOLUTE].dx;
+ chan_properties->adc_graph[chan_properties->calib_type].adc_gnd)
+ * chan_properties->adc_graph[chan_properties->calib_type].dx;
if (scale_voltage < 0) {
negative_offset = 1;
scale_voltage = -scale_voltage;
}
do_div(scale_voltage,
- chan_properties->adc_graph[CALIB_ABSOLUTE].dy);
+ chan_properties->adc_graph[chan_properties->calib_type].dy);
if (negative_offset)
scale_voltage = -scale_voltage;
- scale_voltage += chan_properties->adc_graph[CALIB_ABSOLUTE].dx;
+
+ if (chan_properties->calib_type == CALIB_ABSOLUTE)
+ scale_voltage +=
+ chan_properties->adc_graph[chan_properties->calib_type].dx;
+ else
+ scale_voltage *= 1000;
if (scale_voltage < 0) {
if (adc_properties->bipolar) {
@@ -1190,6 +1195,7 @@
adc_channel_list[i].adc_scale_fn = post_scaling;
adc_channel_list[i].hw_settle_time = hw_settle_time;
adc_channel_list[i].fast_avg_setup = fast_avg_setup;
+ adc_channel_list[i].calib_type = calib_type;
i++;
}
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index 346a72d..ee69840 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -600,6 +600,7 @@
QPNP_VBAT_COEFF_25;
break;
}
+ break;
case QPNP_REV_ID_8110_2_0:
switch (vadc->id) {
case COMP_ID_SMIC:
@@ -713,6 +714,7 @@
temp_var = 0;
break;
}
+ break;
case QPNP_REV_ID_8110_2_0:
switch (vadc->id) {
case COMP_ID_SMIC:
@@ -1173,6 +1175,8 @@
qpnp_vadc_amux_scaling_ratio[amux_prescaling].num;
vadc->adc->amux_prop->chan_prop->offset_gain_denominator =
qpnp_vadc_amux_scaling_ratio[amux_prescaling].den;
+ vadc->adc->amux_prop->chan_prop->calib_type =
+ vadc->adc->adc_channels[dt_index].calib_type;
scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn;
if (scale_type >= SCALE_NONE) {
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 0c22694..915f5e7 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -81,8 +81,6 @@
To compile this driver as a module, choose M here: the
module will be called hbtp_input.
-endif
-
config INPUT_PCSPKR
tristate "PC Speaker support"
depends on PCSPKR_PLATFORM
@@ -724,3 +722,5 @@
To compile this driver as a module, choose M here: the
module will be called CM36283.
+
+endif
diff --git a/drivers/leds/leds-qpnp.c b/drivers/leds/leds-qpnp.c
index 0659b77..0413472 100644
--- a/drivers/leds/leds-qpnp.c
+++ b/drivers/leds/leds-qpnp.c
@@ -1755,7 +1755,7 @@
return -EINVAL;
}
rc = pwm_lut_config(pwm_cfg->pwm_dev,
- PM_PWM_PERIOD_MIN, /* ignored by hardware */
+ pwm_cfg->pwm_period_us,
pwm_cfg->duty_cycles->duty_pcts,
pwm_cfg->lut_params);
if (rc < 0) {
@@ -2862,7 +2862,7 @@
else
return rc;
- if (pwm_cfg->mode == PWM_MODE) {
+ if (pwm_cfg->mode != MANUAL_MODE) {
rc = of_property_read_u32(node, "qcom,pwm-us", &val);
if (!rc)
pwm_cfg->pwm_period_us = val;
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
index 80a0073..d35869c 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
@@ -52,8 +52,82 @@
{}
};
+#define MAX_OVERFLOW_COUNTERS 15
+#define OVERFLOW_LENGTH 512
+#define OVERFLOW_BUFFER_LENGTH 32
static struct msm_isp_buf_mgr vfe_buf_mgr;
+static int msm_isp_enable_debugfs(struct msm_isp_statistics *stats);
+static char *stats_str[MAX_OVERFLOW_COUNTERS] = {
+ "imgmaster0_overflow_cnt",
+ "imgmaster1_overflow_cnt",
+ "imgmaster2_overflow_cnt",
+ "imgmaster3_overflow_cnt",
+ "imgmaster4_overflow_cnt",
+ "imgmaster5_overflow_cnt",
+ "imgmaster6_overflow_cnt",
+ "be_overflow_cnt",
+ "bg_overflow_cnt",
+ "bf_overflow_cnt",
+ "awb_overflow_cnt",
+ "rs_overflow_cnt",
+ "cs_overflow_cnt",
+ "ihist_overflow_cnt",
+ "skinbhist_overflow_cnt",
+};
+static int vfe_debugfs_statistics_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+static ssize_t vfe_debugfs_statistics_read(struct file *t_file, char *t_char,
+ size_t t_size_t, loff_t *t_loff_t)
+{
+ int i;
+ char name[OVERFLOW_LENGTH] = {0};
+ int *ptr;
+ char buffer[OVERFLOW_BUFFER_LENGTH] = {0};
+ struct msm_isp_statistics *stats = (struct msm_isp_statistics *)
+ t_file->private_data;
+ ptr = (int *)(stats);
+ for (i = 0; i < MAX_OVERFLOW_COUNTERS; i++) {
+ strlcat(name, stats_str[i], sizeof(name));
+ strlcat(name, " ", sizeof(name));
+ snprintf(buffer, sizeof(buffer), "%d", ptr[i]);
+ strlcat(name, buffer, sizeof(name));
+ strlcat(name, "\r\n", sizeof(name));
+ }
+ return simple_read_from_buffer(t_char, t_size_t,
+ t_loff_t, name, strlen(name));
+}
+
+static ssize_t vfe_debugfs_statistics_write(struct file *t_file,
+ const char *t_char, size_t t_size_t, loff_t *t_loff_t)
+{
+ struct msm_isp_statistics *stats = (struct msm_isp_statistics *)
+ t_file->private_data;
+ memset(stats, 0, sizeof(struct msm_isp_statistics));
+
+ return sizeof(struct msm_isp_statistics);
+}
+
+static const struct file_operations vfe_debugfs_error = {
+ .open = vfe_debugfs_statistics_open,
+ .read = vfe_debugfs_statistics_read,
+ .write = vfe_debugfs_statistics_write,
+};
+
+static int msm_isp_enable_debugfs(struct msm_isp_statistics *stats)
+{
+ struct dentry *debugfs_base;
+ debugfs_base = debugfs_create_dir("msm_isp", NULL);
+ if (!debugfs_base)
+ return -ENOMEM;
+ if (!debugfs_create_file("stats", S_IRUGO | S_IWUSR, debugfs_base,
+ stats, &vfe_debugfs_error))
+ return -ENOMEM;
+ return 0;
+}
static int __devinit vfe_probe(struct platform_device *pdev)
{
struct vfe_device *vfe_dev;
@@ -73,6 +147,7 @@
};
vfe_dev = kzalloc(sizeof(struct vfe_device), GFP_KERNEL);
+ vfe_dev->stats = kzalloc(sizeof(struct msm_isp_statistics), GFP_KERNEL);
if (!vfe_dev) {
pr_err("%s: no enough memory\n", __func__);
return -ENOMEM;
@@ -144,6 +219,7 @@
kfree(vfe_dev);
return -EINVAL;
}
+ msm_isp_enable_debugfs(vfe_dev->stats);
vfe_dev->buf_mgr->ops->register_ctx(vfe_dev->buf_mgr,
&vfe_dev->iommu_ctx[0], vfe_dev->hw_info->num_iommu_ctx);
vfe_dev->vfe_open_cnt = 0;
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h
index 334a293..805ff0a 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h
@@ -24,7 +24,6 @@
#include <media/msmb_isp.h>
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
-
#include "msm_buf_mgr.h"
#define MAX_IOMMU_CTX 2
@@ -148,13 +147,13 @@
uint32_t (*get_wm_mask) (uint32_t irq_status0, uint32_t irq_status1);
uint32_t (*get_comp_mask) (uint32_t irq_status0, uint32_t irq_status1);
uint32_t (*get_pingpong_status) (struct vfe_device *vfe_dev);
- long (*halt) (struct vfe_device *vfe_dev);
+ long (*halt) (struct vfe_device *vfe_dev, uint32_t blocking);
};
struct msm_vfe_core_ops {
void (*reg_update) (struct vfe_device *vfe_dev);
long (*reset_hw) (struct vfe_device *vfe_dev,
- enum msm_isp_reset_type reset_type);
+ enum msm_isp_reset_type reset_type, uint32_t blocking);
int (*init_hw) (struct vfe_device *vfe_dev);
void (*init_hw_reg) (struct vfe_device *vfe_dev);
void (*release_hw) (struct vfe_device *vfe_dev);
@@ -168,6 +167,12 @@
int (*get_platform_data) (struct vfe_device *vfe_dev);
void (*get_error_mask) (uint32_t *error_mask0, uint32_t *error_mask1);
void (*process_error_status) (struct vfe_device *vfe_dev);
+ void (*get_overflow_mask) (uint32_t *overflow_mask);
+ void (*get_irq_mask) (struct vfe_device *vfe_dev,
+ uint32_t *irq0_mask, uint32_t *irq1_mask);
+ void (*restore_irq_mask) (struct vfe_device *vfe_dev);
+ void (*get_halt_restart_mask) (uint32_t *irq0_mask,
+ uint32_t *irq1_mask);
};
struct msm_vfe_stats_ops {
int (*get_stats_idx) (enum msm_isp_stats_type stats_type);
@@ -299,6 +304,15 @@
uint32_t runtime_num_burst_capture;
uint8_t runtime_framedrop_update;
uint32_t runtime_output_format;
+ enum msm_vfe_frame_skip_pattern frame_skip_pattern;
+
+};
+
+enum msm_vfe_overflow_state {
+ NO_OVERFLOW,
+ OVERFLOW_DETECTED,
+ HALT_REQUESTED,
+ RESTART_REQUESTED,
};
struct msm_vfe_axi_composite_info {
@@ -315,6 +329,7 @@
uint32_t width;
long pixel_clock;
uint32_t input_format;/*V4L2 pix format with bayer pattern*/
+ uint32_t last_updt_frm_id;
};
enum msm_wm_ub_cfg_type {
@@ -394,6 +409,9 @@
#define MSM_VFE_TASKLETQ_SIZE 200
struct msm_vfe_error_info {
+ atomic_t overflow_state;
+ uint32_t overflow_recover_irq_mask0;
+ uint32_t overflow_recover_irq_mask1;
uint32_t error_mask0;
uint32_t error_mask1;
uint32_t violation_status;
@@ -409,6 +427,24 @@
uint32_t frame_id;
};
+struct msm_isp_statistics {
+ int32_t imagemaster0_overflow;
+ int32_t imagemaster1_overflow;
+ int32_t imagemaster2_overflow;
+ int32_t imagemaster3_overflow;
+ int32_t imagemaster4_overflow;
+ int32_t imagemaster5_overflow;
+ int32_t imagemaster6_overflow;
+ int32_t be_overflow;
+ int32_t bg_overflow;
+ int32_t bf_overflow;
+ int32_t awb_overflow;
+ int32_t rs_overflow;
+ int32_t cs_overflow;
+ int32_t ihist_overflow;
+ int32_t skinbhist_overflow;
+};
+
struct vfe_device {
struct platform_device *pdev;
struct msm_sd_subdev subdev;
@@ -460,6 +496,7 @@
void __iomem *p_avtimer_msw;
void __iomem *p_avtimer_lsw;
uint8_t ignore_error;
+ struct msm_isp_statistics *stats;
};
#endif
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
index 4beb3c3..ba1e58c 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
@@ -255,7 +255,6 @@
static void msm_vfe32_process_error_status(struct vfe_device *vfe_dev)
{
uint32_t error_status1 = vfe_dev->error_info.error_mask1;
-
if (error_status1 & BIT(0))
pr_err("%s: camif error status: 0x%x\n",
__func__, vfe_dev->error_info.camif_status);
@@ -275,34 +274,62 @@
pr_err("%s: violation\n", __func__);
msm_vfe32_process_violation_status(vfe_dev);
}
- if (error_status1 & BIT(8))
+ if (error_status1 & BIT(8)) {
+ vfe_dev->stats->imagemaster0_overflow++;
pr_err("%s: image master 0 bus overflow\n", __func__);
- if (error_status1 & BIT(9))
+ }
+ if (error_status1 & BIT(9)) {
+ vfe_dev->stats->imagemaster1_overflow++;
pr_err("%s: image master 1 bus overflow\n", __func__);
- if (error_status1 & BIT(10))
+ }
+ if (error_status1 & BIT(10)) {
+ vfe_dev->stats->imagemaster2_overflow++;
pr_err("%s: image master 2 bus overflow\n", __func__);
- if (error_status1 & BIT(11))
+ }
+ if (error_status1 & BIT(11)) {
+ vfe_dev->stats->imagemaster3_overflow++;
pr_err("%s: image master 3 bus overflow\n", __func__);
- if (error_status1 & BIT(12))
+ }
+ if (error_status1 & BIT(12)) {
+ vfe_dev->stats->imagemaster4_overflow++;
pr_err("%s: image master 4 bus overflow\n", __func__);
- if (error_status1 & BIT(13))
+ }
+ if (error_status1 & BIT(13)) {
+ vfe_dev->stats->imagemaster5_overflow++;
pr_err("%s: image master 5 bus overflow\n", __func__);
- if (error_status1 & BIT(14))
+ }
+ if (error_status1 & BIT(14)) {
+ vfe_dev->stats->imagemaster6_overflow++;
pr_err("%s: image master 6 bus overflow\n", __func__);
- if (error_status1 & BIT(15))
+ }
+ if (error_status1 & BIT(15)) {
+ vfe_dev->stats->bg_overflow++;
pr_err("%s: status ae/bg bus overflow\n", __func__);
- if (error_status1 & BIT(16))
+ }
+ if (error_status1 & BIT(16)) {
+ vfe_dev->stats->bf_overflow++;
pr_err("%s: status af/bf bus overflow\n", __func__);
- if (error_status1 & BIT(17))
+ }
+ if (error_status1 & BIT(17)) {
+ vfe_dev->stats->awb_overflow++;
pr_err("%s: status awb bus overflow\n", __func__);
- if (error_status1 & BIT(18))
+ }
+ if (error_status1 & BIT(18)) {
+ vfe_dev->stats->rs_overflow++;
pr_err("%s: status rs bus overflow\n", __func__);
- if (error_status1 & BIT(19))
+ }
+ if (error_status1 & BIT(19)) {
+ vfe_dev->stats->cs_overflow++;
pr_err("%s: status cs bus overflow\n", __func__);
- if (error_status1 & BIT(20))
+ }
+ if (error_status1 & BIT(20)) {
+ vfe_dev->stats->ihist_overflow++;
pr_err("%s: status ihist bus overflow\n", __func__);
- if (error_status1 & BIT(21))
+ }
+ if (error_status1 & BIT(21)) {
+ vfe_dev->stats->skinbhist_overflow++;
pr_err("%s: status skin bhist bus overflow\n", __func__);
+ }
if (error_status1 & BIT(22))
pr_err("%s: axi error\n", __func__);
}
@@ -366,19 +393,25 @@
};
static long msm_vfe32_reset_hardware(struct vfe_device *vfe_dev ,
- enum msm_isp_reset_type reset_type)
+ enum msm_isp_reset_type reset_type, uint32_t blocking)
{
uint32_t rst_val;
+ long rc = 0;
if (reset_type >= ISP_RST_MAX) {
pr_err("%s: Error Invalid parameter\n", __func__);
reset_type = ISP_RST_HARD;
}
rst_val = msm_vfe32_reset_values[reset_type];
init_completion(&vfe_dev->reset_complete);
- msm_camera_io_w_mb(rst_val, vfe_dev->vfe_base + 0x4);
- return wait_for_completion_timeout(
- &vfe_dev->reset_complete, msecs_to_jiffies(50));
+ if (blocking) {
+ msm_camera_io_w_mb(rst_val, vfe_dev->vfe_base + 0x4);
+ rc = wait_for_completion_timeout(
+ &vfe_dev->reset_complete, msecs_to_jiffies(50));
+ } else {
+ msm_camera_io_w_mb(0x3EF, vfe_dev->vfe_base + 0x4);
+ }
+ return rc;
}
static void msm_vfe32_axi_reload_wm(
@@ -632,6 +665,7 @@
val &= 0xFFFFFF3F;
val = val | bus_en << 7 | vfe_en << 6;
msm_camera_io_w(val, vfe_dev->vfe_base + 0x1E4);
+ msm_camera_io_w_mb(0x4, vfe_dev->vfe_base + 0x1E0);
msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x1E0);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 1;
} else if (update_state == DISABLE_CAMIF) {
@@ -864,12 +898,15 @@
VFE32_PING_PONG_BASE(wm_idx, pingpong_status));
}
-static long msm_vfe32_axi_halt(struct vfe_device *vfe_dev)
+static long msm_vfe32_axi_halt(struct vfe_device *vfe_dev,
+ uint32_t blocking)
{
uint32_t halt_mask;
- uint32_t axi_busy_flag = true;
-
+ uint32_t axi_busy_flag = false;
msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x1D8);
+ if (blocking) {
+ axi_busy_flag = true;
+ }
while (axi_busy_flag) {
if (msm_camera_io_r(
vfe_dev->vfe_base + 0x1DC) & 0x1)
@@ -1040,6 +1077,33 @@
return (irq_status0 >> 13) & 0x7F;
}
+static void msm_vfe32_get_overflow_mask(uint32_t *overflow_mask)
+{
+ *overflow_mask = 0x002FFF7E;
+}
+
+static void msm_vfe32_get_irq_mask(struct vfe_device *vfe_dev,
+ uint32_t *irq0_mask, uint32_t *irq1_mask)
+{
+ *irq0_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x1C);
+ *irq1_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x20);
+}
+
+static void msm_vfe32_restore_irq_mask(struct vfe_device *vfe_dev)
+{
+ msm_camera_io_w(vfe_dev->error_info.overflow_recover_irq_mask0,
+ vfe_dev->vfe_base + 0x1C);
+ msm_camera_io_w(vfe_dev->error_info.overflow_recover_irq_mask1,
+ vfe_dev->vfe_base + 0x20);
+}
+
+static void msm_vfe32_get_halt_restart_mask(uint32_t *irq0_mask,
+ uint32_t *irq1_mask)
+{
+ *irq0_mask = 0x0;
+ *irq1_mask = 0x01800000;
+}
+
static uint32_t msm_vfe32_stats_get_comp_mask(uint32_t irq_status0,
uint32_t irq_status1)
{
@@ -1193,6 +1257,11 @@
.release_hw = msm_vfe32_release_hardware,
.get_platform_data = msm_vfe32_get_platform_data,
.get_error_mask = msm_vfe32_get_error_mask,
+ .get_overflow_mask = msm_vfe32_get_overflow_mask,
+ .get_irq_mask = msm_vfe32_get_irq_mask,
+ .restore_irq_mask = msm_vfe32_restore_irq_mask,
+ .get_halt_restart_mask =
+ msm_vfe32_get_halt_restart_mask,
.process_error_status = msm_vfe32_process_error_status,
},
.stats_ops = {
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
index 827dbb0..81e9c74 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
@@ -480,44 +480,74 @@
pr_err_ratelimited("%s: violation\n", __func__);
msm_vfe40_process_violation_status(vfe_dev);
}
- if (error_status1 & (1 << 9))
+ if (error_status1 & (1 << 9)) {
+ vfe_dev->stats->imagemaster0_overflow++;
pr_err_ratelimited("%s: image master 0 bus overflow\n",
__func__);
- if (error_status1 & (1 << 10))
+ }
+ if (error_status1 & (1 << 10)) {
+ vfe_dev->stats->imagemaster1_overflow++;
pr_err_ratelimited("%s: image master 1 bus overflow\n",
__func__);
- if (error_status1 & (1 << 11))
+ }
+ if (error_status1 & (1 << 11)) {
+ vfe_dev->stats->imagemaster2_overflow++;
pr_err_ratelimited("%s: image master 2 bus overflow\n",
__func__);
- if (error_status1 & (1 << 12))
+ }
+ if (error_status1 & (1 << 12)) {
+ vfe_dev->stats->imagemaster3_overflow++;
pr_err_ratelimited("%s: image master 3 bus overflow\n",
__func__);
- if (error_status1 & (1 << 13))
+ }
+ if (error_status1 & (1 << 13)) {
+ vfe_dev->stats->imagemaster4_overflow++;
pr_err_ratelimited("%s: image master 4 bus overflow\n",
__func__);
- if (error_status1 & (1 << 14))
+ }
+ if (error_status1 & (1 << 14)) {
+ vfe_dev->stats->imagemaster5_overflow++;
pr_err_ratelimited("%s: image master 5 bus overflow\n",
__func__);
- if (error_status1 & (1 << 15))
+ }
+ if (error_status1 & (1 << 15)) {
+ vfe_dev->stats->imagemaster6_overflow++;
pr_err_ratelimited("%s: image master 6 bus overflow\n",
__func__);
- if (error_status1 & (1 << 16))
+ }
+ if (error_status1 & (1 << 16)) {
+ vfe_dev->stats->be_overflow++;
pr_err_ratelimited("%s: status be bus overflow\n", __func__);
- if (error_status1 & (1 << 17))
+ }
+ if (error_status1 & (1 << 17)) {
+ vfe_dev->stats->bg_overflow++;
pr_err_ratelimited("%s: status bg bus overflow\n", __func__);
- if (error_status1 & (1 << 18))
+ }
+ if (error_status1 & (1 << 18)) {
+ vfe_dev->stats->bf_overflow++;
pr_err_ratelimited("%s: status bf bus overflow\n", __func__);
- if (error_status1 & (1 << 19))
+ }
+ if (error_status1 & (1 << 19)) {
+ vfe_dev->stats->awb_overflow++;
pr_err_ratelimited("%s: status awb bus overflow\n", __func__);
- if (error_status1 & (1 << 20))
+ }
+ if (error_status1 & (1 << 20)) {
+ vfe_dev->stats->imagemaster0_overflow++;
pr_err_ratelimited("%s: status rs bus overflow\n", __func__);
- if (error_status1 & (1 << 21))
+ }
+ if (error_status1 & (1 << 21)) {
+ vfe_dev->stats->cs_overflow++;
pr_err_ratelimited("%s: status cs bus overflow\n", __func__);
- if (error_status1 & (1 << 22))
+ }
+ if (error_status1 & (1 << 22)) {
+ vfe_dev->stats->ihist_overflow++;
pr_err_ratelimited("%s: status ihist bus overflow\n", __func__);
- if (error_status1 & (1 << 23))
+ }
+ if (error_status1 & (1 << 23)) {
+ vfe_dev->stats->skinbhist_overflow++;
pr_err_ratelimited("%s: status skin bhist bus overflow\n",
__func__);
+ }
}
static void msm_vfe40_read_irq_status(struct vfe_device *vfe_dev,
@@ -590,18 +620,24 @@
static long msm_vfe40_reset_hardware(struct vfe_device *vfe_dev ,
- enum msm_isp_reset_type reset_type)
+ enum msm_isp_reset_type reset_type, uint32_t blocking)
{
uint32_t rst_val;
+ long rc = 0;
if (reset_type >= ISP_RST_MAX) {
pr_err("%s: Error Invalid parameter\n", __func__);
reset_type = ISP_RST_HARD;
}
rst_val = msm_vfe40_reset_values[reset_type];
init_completion(&vfe_dev->reset_complete);
- msm_camera_io_w_mb(rst_val, vfe_dev->vfe_base + 0xC);
- return wait_for_completion_timeout(
- &vfe_dev->reset_complete, msecs_to_jiffies(50));
+ if (blocking) {
+ msm_camera_io_w_mb(rst_val, vfe_dev->vfe_base + 0xC);
+ rc = wait_for_completion_timeout(
+ &vfe_dev->reset_complete, msecs_to_jiffies(50));
+ } else {
+ msm_camera_io_w_mb(0x1EF, vfe_dev->vfe_base + 0xC);
+ }
+ return rc;
}
static void msm_vfe40_axi_reload_wm(
@@ -894,6 +930,7 @@
val &= 0xFFFFFF3F;
val = val | bus_en << 7 | vfe_en << 6;
msm_camera_io_w(val, vfe_dev->vfe_base + 0x2F8);
+ msm_camera_io_w_mb(0x4, vfe_dev->vfe_base + 0x2F4);
msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x2F4);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 1;
} else if (update_state == DISABLE_CAMIF) {
@@ -1135,16 +1172,24 @@
VFE40_PING_PONG_BASE(wm_idx, pingpong_status));
}
-static long msm_vfe40_axi_halt(struct vfe_device *vfe_dev)
+static long msm_vfe40_axi_halt(struct vfe_device *vfe_dev,
+ uint32_t blocking)
{
- uint32_t halt_mask;
- halt_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x2C);
- halt_mask |= (1 << 8);
- msm_camera_io_w_mb(halt_mask, vfe_dev->vfe_base + 0x2C);
+ long rc = 0;
+ /* Keep only restart mask and halt mask*/
+ msm_camera_io_w(BIT(31), vfe_dev->vfe_base + 0x28);
+ msm_camera_io_w(BIT(8), vfe_dev->vfe_base + 0x2C);
+ /* Clear IRQ Status*/
+ msm_camera_io_w(0xFFFFFFFF, vfe_dev->vfe_base + 0x30);
+ msm_camera_io_w(0xFEFFFFFF, vfe_dev->vfe_base + 0x34);
init_completion(&vfe_dev->halt_complete);
msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x2C0);
- return wait_for_completion_interruptible_timeout(
- &vfe_dev->halt_complete, msecs_to_jiffies(500));
+ if (blocking) {
+ atomic_set(&vfe_dev->error_info.overflow_state, NO_OVERFLOW);
+ rc = wait_for_completion_interruptible_timeout(
+ &vfe_dev->halt_complete, msecs_to_jiffies(500));
+ }
+ return rc;
}
static uint32_t msm_vfe40_get_wm_mask(
@@ -1153,6 +1198,33 @@
return (irq_status0 >> 8) & 0x7F;
}
+static void msm_vfe40_get_overflow_mask(uint32_t *overflow_mask)
+{
+ *overflow_mask = 0x00FFFE7E;
+}
+
+static void msm_vfe40_get_irq_mask(struct vfe_device *vfe_dev,
+ uint32_t *irq0_mask, uint32_t *irq1_mask)
+{
+ *irq0_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x28);
+ *irq1_mask = msm_camera_io_r(vfe_dev->vfe_base + 0x2C);
+}
+
+static void msm_vfe40_restore_irq_mask(struct vfe_device *vfe_dev)
+{
+ msm_camera_io_w(vfe_dev->error_info.overflow_recover_irq_mask0,
+ vfe_dev->vfe_base + 0x28);
+ msm_camera_io_w(vfe_dev->error_info.overflow_recover_irq_mask1,
+ vfe_dev->vfe_base + 0x2C);
+}
+
+static void msm_vfe40_get_halt_restart_mask(uint32_t *irq0_mask,
+ uint32_t *irq1_mask)
+{
+ *irq0_mask = BIT(31);
+ *irq1_mask = BIT(8);
+}
+
static uint32_t msm_vfe40_get_comp_mask(
uint32_t irq_status0, uint32_t irq_status1)
{
@@ -1489,6 +1561,11 @@
.release_hw = msm_vfe40_release_hardware,
.get_platform_data = msm_vfe40_get_platform_data,
.get_error_mask = msm_vfe40_get_error_mask,
+ .get_overflow_mask = msm_vfe40_get_overflow_mask,
+ .get_irq_mask = msm_vfe40_get_irq_mask,
+ .restore_irq_mask = msm_vfe40_restore_irq_mask,
+ .get_halt_restart_mask =
+ msm_vfe40_get_halt_restart_mask,
.process_error_status = msm_vfe40_process_error_status,
},
.stats_ops = {
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
index 508bcec..4c3a3d5 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
@@ -20,6 +20,9 @@
#define HANDLE_TO_IDX(handle) (handle & 0xFF)
+#define MSM_ISP_MIN_AB 450000000
+#define MSM_ISP_MIN_IB 900000000
+
int msm_isp_axi_create_stream(
struct msm_vfe_axi_shared_data *axi_data,
struct msm_vfe_axi_stream_request_cmd *stream_cfg_cmd)
@@ -475,7 +478,8 @@
framedrop_period = msm_isp_get_framedrop_period(
stream_cfg_cmd->frame_skip_pattern);
-
+ stream_info->frame_skip_pattern =
+ stream_cfg_cmd->frame_skip_pattern;
if (stream_cfg_cmd->frame_skip_pattern == SKIP_ALL)
stream_info->framedrop_pattern = 0x0;
else
@@ -1069,6 +1073,8 @@
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
uint32_t total_pix_bandwidth = 0, total_rdi_bandwidth = 0;
uint32_t num_pix_streams = 0;
+ uint32_t num_rdi_streams = 0;
+ uint32_t total_streams = 0;
uint64_t total_bandwidth = 0;
for (i = 0; i < MAX_NUM_STREAM; i++) {
@@ -1080,6 +1086,7 @@
num_pix_streams++;
} else {
total_rdi_bandwidth += stream_info->bandwidth;
+ num_rdi_streams++;
}
}
}
@@ -1089,10 +1096,17 @@
((unsigned long)axi_data->src_info[VFE_PIX_0].
pixel_clock) * ISP_DEFAULT_FORMAT_FACTOR / ISP_Q2;
total_bandwidth = total_pix_bandwidth + total_rdi_bandwidth;
-
+ total_streams = num_pix_streams + num_rdi_streams;
+ if (total_streams == 1) {
+ rc = msm_isp_update_bandwidth(ISP_VFE0 + vfe_dev->pdev->id,
+ (total_bandwidth - MSM_ISP_MIN_AB) , (total_bandwidth *
+ ISP_BUS_UTILIZATION_FACTOR / ISP_Q2 - MSM_ISP_MIN_IB));
+ }
+ else {
rc = msm_isp_update_bandwidth(ISP_VFE0 + vfe_dev->pdev->id,
total_bandwidth, total_bandwidth *
ISP_BUS_UTILIZATION_FACTOR / ISP_Q2);
+ }
if (rc < 0)
pr_err("%s: update failed\n", __func__);
@@ -1318,9 +1332,9 @@
if (cur_stream_cnt == 0) {
vfe_dev->ignore_error = 1;
if (camif_update == DISABLE_CAMIF_IMMEDIATELY) {
- vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev, 1);
}
- vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev, ISP_RST_HARD);
+ vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev, ISP_RST_HARD, 1);
vfe_dev->hw_info->vfe_ops.core_ops.init_hw_reg(vfe_dev);
vfe_dev->ignore_error = 0;
}
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h
index 7d282bd..2314300 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.h
@@ -37,6 +37,10 @@
struct vfe_device *vfe_dev,
struct msm_vfe_axi_stream_cfg_cmd *stream_cfg_cmd);
+void msm_isp_calculate_framedrop(
+ struct msm_vfe_axi_shared_data *axi_data,
+ struct msm_vfe_axi_stream_request_cmd *stream_cfg_cmd);
+
int msm_isp_request_axi_stream(struct vfe_device *vfe_dev, void *arg);
int msm_isp_cfg_axi_stream(struct vfe_device *vfe_dev, void *arg);
int msm_isp_release_axi_stream(struct vfe_device *vfe_dev, void *arg);
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
index f148d53..b1521df 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
@@ -637,6 +637,33 @@
}
break;
}
+ case VFE_HW_UPDATE_LOCK: {
+ uint32_t update_id =
+ vfe_dev->axi_data.src_info[VFE_PIX_0].last_updt_frm_id;
+ if (vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id != *cfg_data
+ || update_id == *cfg_data) {
+ pr_err("hw update lock failed,acquire id %u\n",
+ *cfg_data);
+ pr_err("hw update lock failed,current id %lu\n",
+ vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id);
+ pr_err("hw update lock failed,last id %u\n",
+ update_id);
+ return -EINVAL;
+ }
+ break;
+ }
+ case VFE_HW_UPDATE_UNLOCK: {
+ if (vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id
+ != *cfg_data) {
+ pr_err("hw update across frame boundary,begin id %u\n",
+ *cfg_data);
+ pr_err("hw update across frame boundary,end id %lu\n",
+ vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id);
+ vfe_dev->axi_data.src_info[VFE_PIX_0].last_updt_frm_id =
+ vfe_dev->axi_data.src_info[VFE_PIX_0].frame_id;
+ }
+ break;
+ }
case VFE_READ: {
int i;
uint32_t *data_ptr = cfg_data +
@@ -726,7 +753,7 @@
}
for (i = 0; i < proc_cmd->num_cfg; i++)
- msm_isp_send_hw_cmd(vfe_dev, ®_cfg_cmd[i],
+ rc = msm_isp_send_hw_cmd(vfe_dev, ®_cfg_cmd[i],
cfg_data, proc_cmd->cmd_len);
if (copy_to_user(proc_cmd->cfg_data,
@@ -987,6 +1014,125 @@
vfe_dev->error_info.error_count++;
}
+static inline void msm_isp_process_overflow_irq(
+ struct vfe_device *vfe_dev,
+ uint32_t *irq_status0, uint32_t *irq_status1)
+{
+ uint32_t overflow_mask;
+ uint32_t halt_restart_mask0, halt_restart_mask1;
+ /*Mask out all other irqs if recovery is started*/
+ if (atomic_read(&vfe_dev->error_info.overflow_state) !=
+ NO_OVERFLOW) {
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ get_halt_restart_mask(&halt_restart_mask0,
+ &halt_restart_mask1);
+ *irq_status0 &= halt_restart_mask0;
+ *irq_status1 &= halt_restart_mask1;
+ return;
+ }
+
+ /*Check if any overflow bit is set*/
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ get_overflow_mask(&overflow_mask);
+ overflow_mask &= *irq_status1;
+ if (overflow_mask) {
+ pr_warning("%s: Bus overflow detected: 0x%x\n",
+ __func__, overflow_mask);
+ atomic_set(&vfe_dev->error_info.overflow_state,
+ OVERFLOW_DETECTED);
+ pr_warning("%s: Start bus overflow recovery\n", __func__);
+ /*Store current IRQ mask*/
+ vfe_dev->hw_info->vfe_ops.core_ops.get_irq_mask(vfe_dev,
+ &vfe_dev->error_info.overflow_recover_irq_mask0,
+ &vfe_dev->error_info.overflow_recover_irq_mask1);
+ /*Stop CAMIF Immediately*/
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ update_camif_state(vfe_dev, DISABLE_CAMIF_IMMEDIATELY);
+ /*Halt the hardware & Clear all other IRQ mask*/
+ vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev, 0);
+ /*Update overflow state*/
+ atomic_set(&vfe_dev->error_info.overflow_state, HALT_REQUESTED);
+ *irq_status0 = 0;
+ *irq_status1 = 0;
+ }
+}
+
+static inline void msm_isp_reset_burst_count(
+ struct vfe_device *vfe_dev)
+{
+ int i;
+ struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
+ struct msm_vfe_axi_stream *stream_info;
+ struct msm_vfe_axi_stream_request_cmd framedrop_info;
+ for (i = 0; i < MAX_NUM_STREAM; i++) {
+ stream_info = &axi_data->stream_info[i];
+ if (stream_info->state != ACTIVE)
+ continue;
+ if (stream_info->stream_type == BURST_STREAM &&
+ stream_info->num_burst_capture != 0) {
+ framedrop_info.burst_count =
+ stream_info->num_burst_capture;
+ framedrop_info.frame_skip_pattern =
+ stream_info->frame_skip_pattern;
+ framedrop_info.init_frame_drop = 0;
+ msm_isp_calculate_framedrop(&vfe_dev->axi_data,
+ &framedrop_info);
+ }
+ }
+}
+
+static void msm_isp_process_overflow_recovery(
+ struct vfe_device *vfe_dev,
+ uint32_t irq_status0, uint32_t irq_status1)
+{
+ uint32_t halt_restart_mask0, halt_restart_mask1;
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ get_halt_restart_mask(&halt_restart_mask0,
+ &halt_restart_mask1);
+ irq_status0 &= halt_restart_mask0;
+ irq_status1 &= halt_restart_mask1;
+ if (irq_status0 == 0 && irq_status1 == 0)
+ return;
+
+ switch (atomic_read(&vfe_dev->error_info.overflow_state)) {
+ case HALT_REQUESTED: {
+ pr_err("%s: Halt done, Restart Pending\n", __func__);
+ /*Reset the hardware*/
+ vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev,
+ ISP_RST_SOFT, 0);
+ /*Update overflow state*/
+ atomic_set(&vfe_dev->error_info.overflow_state,
+ RESTART_REQUESTED);
+ }
+ break;
+ case RESTART_REQUESTED: {
+ pr_err("%s: Restart done, Resuming\n", __func__);
+ /*Reset the burst stream frame drop pattern, in the
+ *case where bus overflow happens during the burstshot,
+ *the framedrop pattern might be updated after reg update
+ *to skip all the frames after the burst shot. The burst shot
+ *might not be completed due to the overflow, so the framedrop
+ *pattern need to change back to the original settings in order
+ *to recovr from overflow.
+ */
+ msm_isp_reset_burst_count(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.axi_ops.
+ reload_wm(vfe_dev, 0xFFFFFFFF);
+ vfe_dev->hw_info->vfe_ops.core_ops.restore_irq_mask(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
+ memset(&vfe_dev->error_info, 0, sizeof(vfe_dev->error_info));
+ atomic_set(&vfe_dev->error_info.overflow_state, NO_OVERFLOW);
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ update_camif_state(vfe_dev, ENABLE_CAMIF);
+ }
+ break;
+ case NO_OVERFLOW:
+ case OVERFLOW_DETECTED:
+ default:
+ break;
+ }
+}
+
irqreturn_t msm_isp_process_irq(int irq_num, void *data)
{
unsigned long flags;
@@ -997,6 +1143,8 @@
vfe_dev->hw_info->vfe_ops.irq_ops.
read_irq_status(vfe_dev, &irq_status0, &irq_status1);
+ msm_isp_process_overflow_irq(vfe_dev,
+ &irq_status0, &irq_status1);
vfe_dev->hw_info->vfe_ops.core_ops.
get_error_mask(&error_mask0, &error_mask1);
error_mask0 &= irq_status0;
@@ -1061,6 +1209,13 @@
irq_status1 = queue_cmd->vfeInterruptStatus1;
ts = queue_cmd->ts;
spin_unlock_irqrestore(&vfe_dev->tasklet_lock, flags);
+ if (atomic_read(&vfe_dev->error_info.overflow_state) !=
+ NO_OVERFLOW) {
+ pr_err("There is Overflow, kicking up recovery !!!!");
+ msm_isp_process_overflow_recovery(vfe_dev,
+ irq_status0, irq_status1);
+ continue;
+ }
ISP_DBG("%s: status0: 0x%x status1: 0x%x\n",
__func__, irq_status0, irq_status1);
irq_ops->process_reset_irq(vfe_dev,
@@ -1111,7 +1266,10 @@
return -EBUSY;
}
- rc = vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev, ISP_RST_HARD);
+ memset(&vfe_dev->error_info, 0, sizeof(vfe_dev->error_info));
+ atomic_set(&vfe_dev->error_info.overflow_state, NO_OVERFLOW);
+ rc = vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev,
+ ISP_RST_HARD, 1);
if (rc <= 0) {
pr_err("%s: reset timeout\n", __func__);
mutex_unlock(&vfe_dev->core_mutex);
@@ -1163,7 +1321,7 @@
return -ENODEV;
}
- rc = vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev);
+ rc = vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev, 1);
if (rc <= 0)
pr_err("%s: halt timeout rc=%ld\n", __func__, rc);
diff --git a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
index a08fad7..8f99ff6 100755
--- a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
+++ b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c
@@ -64,6 +64,25 @@
false : true;
}
+static struct msm_cam_clk_info ispif_8626_reset_clk_info[] = {
+ {"ispif_ahb_clk", NO_SET_RATE},
+ {"camss_top_ahb_clk", NO_SET_RATE},
+ {"csi0_ahb_clk", NO_SET_RATE},
+ {"csi0_src_clk", NO_SET_RATE},
+ {"csi0_phy_clk", NO_SET_RATE},
+ {"csi0_clk", NO_SET_RATE},
+ {"csi0_pix_clk", NO_SET_RATE},
+ {"csi0_rdi_clk", NO_SET_RATE},
+ {"csi1_ahb_clk", NO_SET_RATE},
+ {"csi1_src_clk", NO_SET_RATE},
+ {"csi1_phy_clk", NO_SET_RATE},
+ {"csi1_clk", NO_SET_RATE},
+ {"csi1_pix_clk", NO_SET_RATE},
+ {"csi1_rdi_clk", NO_SET_RATE},
+ {"camss_vfe_vfe_clk", NO_SET_RATE},
+ {"camss_csi_vfe_clk", NO_SET_RATE},
+};
+
static struct msm_cam_clk_info ispif_8974_ahb_clk_info[] = {
{"ispif_ahb_clk", -1},
};
@@ -98,13 +117,26 @@
int rc = 0;
long timeout = 0;
struct clk *reset_clk[ARRAY_SIZE(ispif_8974_reset_clk_info)];
+ struct clk *reset_clk1[ARRAY_SIZE(ispif_8626_reset_clk_info)];
+ ispif->clk_idx = 0;
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_8974_reset_clk_info, reset_clk,
ARRAY_SIZE(ispif_8974_reset_clk_info), 1);
if (rc < 0) {
- pr_err("%s: cannot enable clock, error = %d",
- __func__, rc);
+ rc = msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8626_reset_clk_info, reset_clk1,
+ ARRAY_SIZE(ispif_8626_reset_clk_info), 1);
+ if (rc < 0){
+ pr_err("%s: cannot enable clock, error = %d",
+ __func__, rc);
+ } else {
+ /* This is set if device is 8x26 */
+ ispif->clk_idx = 2;
+ }
+ } else {
+ /* This is set if device is 8974 */
+ ispif->clk_idx = 1;
}
init_completion(&ispif->reset_complete[VFE0]);
@@ -121,11 +153,19 @@
timeout = wait_for_completion_timeout(
&ispif->reset_complete[VFE0], msecs_to_jiffies(500));
CDBG("%s: VFE0 done\n", __func__);
+
if (timeout <= 0) {
pr_err("%s: VFE0 reset wait timeout\n", __func__);
- msm_cam_clk_enable(&ispif->pdev->dev,
+ rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_8974_reset_clk_info, reset_clk,
ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
+ if (rc < 0){
+ rc = msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8626_reset_clk_info, reset_clk1,
+ ARRAY_SIZE(ispif_8626_reset_clk_info), 0);
+ if (rc < 0)
+ pr_err("%s: VFE0 reset wait timeout\n", __func__);
+ }
return -ETIMEDOUT;
}
@@ -143,13 +183,26 @@
}
}
- rc = msm_cam_clk_enable(&ispif->pdev->dev,
- ispif_8974_reset_clk_info, reset_clk,
- ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
- if (rc < 0) {
- pr_err("%s: cannot disable clock, error = %d",
- __func__, rc);
+ if (ispif->clk_idx == 1){
+ rc = msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8974_reset_clk_info, reset_clk,
+ ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
+ if (rc < 0) {
+ pr_err("%s: cannot disable clock, error = %d",
+ __func__, rc);
+ }
}
+
+ if (ispif->clk_idx == 2){
+ rc = msm_cam_clk_enable(&ispif->pdev->dev,
+ ispif_8626_reset_clk_info, reset_clk1,
+ ARRAY_SIZE(ispif_8626_reset_clk_info), 0);
+ if (rc < 0) {
+ pr_err("%s: cannot disable clock, error = %d",
+ __func__, rc);
+ }
+ }
+
return rc;
}
@@ -941,11 +994,7 @@
goto error_ahb;
}
- if (of_device_is_compatible(ispif->pdev->dev.of_node,
- "qcom,ispif-v3.0")) {
- /* currently HW reset is implemented for 8974 only */
- msm_ispif_reset_hw(ispif);
- }
+ msm_ispif_reset_hw(ispif);
rc = msm_ispif_reset(ispif);
if (rc == 0) {
diff --git a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.h b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.h
index 45e7354..10dbfb6 100644
--- a/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.h
+++ b/drivers/media/platform/msm/camera_v2/ispif/msm_ispif.h
@@ -60,5 +60,6 @@
struct clk *ahb_clk;
struct completion reset_complete[VFE_MAX];
uint32_t hw_num_isps;
+ uint32_t clk_idx;
};
#endif
diff --git a/drivers/media/platform/msm/camera_v2/sensor/actuator/msm_actuator.c b/drivers/media/platform/msm/camera_v2/sensor/actuator/msm_actuator.c
index 7805930..50f37db 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/actuator/msm_actuator.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/actuator/msm_actuator.c
@@ -156,6 +156,7 @@
settings[i].i2c_operation);
break;
}
+ break;
}
case MSM_ACT_POLL: {
switch (settings[i].data_type) {
@@ -178,6 +179,7 @@
settings[i].i2c_operation);
break;
}
+ break;
}
}
@@ -302,6 +304,21 @@
if (dest_step_pos == a_ctrl->curr_step_pos)
return rc;
+ if ((sign_dir > MSM_ACTUATOR_MOVE_SIGNED_NEAR) ||
+ (sign_dir < MSM_ACTUATOR_MOVE_SIGNED_FAR)) {
+ pr_err("Invalid sign_dir = %d\n", sign_dir);
+ return -EFAULT;
+ }
+ if ((dir > MOVE_FAR) || (dir < MOVE_NEAR)) {
+ pr_err("Invalid direction = %d\n", dir);
+ return -EFAULT;
+ }
+ if (dest_step_pos > a_ctrl->total_steps) {
+ pr_err("Step pos greater than total steps = %d\n",
+ dest_step_pos);
+ return -EFAULT;
+ }
+ curr_lens_pos = a_ctrl->step_position_table[a_ctrl->curr_step_pos];
a_ctrl->i2c_tbl_index = 0;
CDBG("curr_step_pos =%d dest_step_pos =%d curr_lens_pos=%d\n",
a_ctrl->curr_step_pos, dest_step_pos, curr_lens_pos);
@@ -372,6 +389,12 @@
kfree(a_ctrl->step_position_table);
a_ctrl->step_position_table = NULL;
+ if (set_info->af_tuning_params.total_steps
+ > MAX_ACTUATOR_AF_TOTAL_STEPS) {
+ pr_err("Max actuator totalsteps exceeded = %d\n",
+ set_info->af_tuning_params.total_steps);
+ return -EFAULT;
+ }
/* Fill step position table */
a_ctrl->step_position_table =
kmalloc(sizeof(uint16_t) *
@@ -500,12 +523,19 @@
pr_err("Actuator function table not found\n");
return rc;
}
-
- a_ctrl->region_size = set_info->af_tuning_params.region_size;
- if (a_ctrl->region_size > MAX_ACTUATOR_REGION) {
+ if (set_info->af_tuning_params.total_steps
+ > MAX_ACTUATOR_AF_TOTAL_STEPS) {
+ pr_err("Max actuator totalsteps exceeded = %d\n",
+ set_info->af_tuning_params.total_steps);
+ return -EFAULT;
+ }
+ if (set_info->af_tuning_params.region_size
+ > MAX_ACTUATOR_REGION) {
pr_err("MAX_ACTUATOR_REGION is exceeded.\n");
return -EFAULT;
}
+
+ a_ctrl->region_size = set_info->af_tuning_params.region_size;
a_ctrl->pwd_step = set_info->af_tuning_params.pwd_step;
a_ctrl->total_steps = set_info->af_tuning_params.total_steps;
@@ -555,7 +585,9 @@
return -EFAULT;
}
- if (set_info->actuator_params.init_setting_size) {
+ if (set_info->actuator_params.init_setting_size &&
+ set_info->actuator_params.init_setting_size
+ <= MAX_ACTUATOR_REG_TBL_SIZE) {
if (a_ctrl->func_tbl->actuator_init_focus) {
init_settings = kmalloc(sizeof(struct reg_settings_t) *
(set_info->actuator_params.init_setting_size),
@@ -894,6 +926,7 @@
&pdev->id);
CDBG("cell-index %d, rc %d\n", pdev->id, rc);
if (rc < 0) {
+ kfree(msm_actuator_t);
pr_err("failed rc %d\n", rc);
return rc;
}
@@ -902,6 +935,7 @@
&msm_actuator_t->cci_master);
CDBG("qcom,cci-master %d, rc %d\n", msm_actuator_t->cci_master, rc);
if (rc < 0) {
+ kfree(msm_actuator_t);
pr_err("failed rc %d\n", rc);
return rc;
}
@@ -918,6 +952,7 @@
msm_actuator_t->i2c_client.cci_client = kzalloc(sizeof(
struct msm_camera_cci_client), GFP_KERNEL);
if (!msm_actuator_t->i2c_client.cci_client) {
+ kfree(msm_actuator_t);
pr_err("failed no memory\n");
return -ENOMEM;
}
diff --git a/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c b/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
index 176c612..c638415 100644
--- a/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
@@ -319,7 +319,6 @@
}
INIT_LIST_HEAD(&core->instances);
- mutex_init(&core->sync_lock);
mutex_init(&core->lock);
core->state = VIDC_CORE_UNINIT;
diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c
index 7d27cea..f84a806 100644
--- a/drivers/media/platform/msm/vidc/msm_vdec.c
+++ b/drivers/media/platform/msm/vidc/msm_vdec.c
@@ -870,9 +870,8 @@
dprintk(VIDC_PROF, "reported fps changed for %p: %d->%d\n",
inst, inst->prop.fps, fps);
inst->prop.fps = fps;
- mutex_lock(&inst->core->sync_lock);
+
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
}
exit:
return rc;
@@ -1228,9 +1227,8 @@
goto fail_start;
}
}
- mutex_lock(&inst->core->sync_lock);
+
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
rc = msm_comm_try_state(inst, MSM_VIDC_START_DONE);
if (rc) {
@@ -1337,9 +1335,7 @@
break;
}
- mutex_lock(&inst->core->sync_lock);
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
if (rc)
dprintk(VIDC_ERR,
@@ -1889,6 +1885,11 @@
int msm_vdec_ctrl_deinit(struct msm_vidc_inst *inst)
{
+ if (!inst) {
+ dprintk(VIDC_ERR, "%s invalid parameters\n", __func__);
+ return -EINVAL;
+ }
+
kfree(inst->ctrls);
kfree(inst->cluster);
v4l2_ctrl_handler_free(&inst->ctrl_handler);
diff --git a/drivers/media/platform/msm/vidc/msm_venc.c b/drivers/media/platform/msm/vidc/msm_venc.c
index 9504817..810357e 100644
--- a/drivers/media/platform/msm/vidc/msm_venc.c
+++ b/drivers/media/platform/msm/vidc/msm_venc.c
@@ -907,9 +907,23 @@
}
hdev = inst->core->device;
+ rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to open instance\n");
+ return rc;
+ }
+
+ rc = msm_comm_try_get_bufreqs(inst);
+ if (rc) {
+ dprintk(VIDC_ERR,
+ "Failed to get buffer requirements: %d\n", rc);
+ return rc;
+ }
+
switch (q->type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
*num_planes = 1;
+
buff_req = get_buff_req_buffer(inst, HAL_BUFFER_OUTPUT);
if (buff_req) {
*num_buffers = buff_req->buffer_count_actual =
@@ -937,9 +951,18 @@
inst->fmts[CAPTURE_PORT]->num_planes = *num_planes;
for (i = 0; i < *num_planes; i++) {
+ int extra_idx = EXTRADATA_IDX(*num_planes);
+
sizes[i] = inst->fmts[CAPTURE_PORT]->get_frame_size(
i, inst->prop.height[CAPTURE_PORT],
inst->prop.width[CAPTURE_PORT]);
+
+ if (extra_idx && i == extra_idx &&
+ extra_idx < VIDEO_MAX_PLANES) {
+ buff_req = get_buff_req_buffer(inst,
+ HAL_BUFFER_EXTRADATA_OUTPUT);
+ sizes[i] = buff_req->buffer_size;
+ }
}
property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
@@ -949,26 +972,18 @@
property_id, &new_buf_count);
break;
case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
- rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to open instance\n");
- break;
- }
- rc = msm_comm_try_get_bufreqs(inst);
- if (rc) {
- dprintk(VIDC_ERR,
- "Failed to get buffer requirements: %d\n", rc);
- break;
- }
*num_planes = 1;
+
mutex_lock(&inst->lock);
*num_buffers = inst->buff_req.buffer[0].buffer_count_actual =
max(*num_buffers, inst->buff_req.buffer[0].
buffer_count_actual);
mutex_unlock(&inst->lock);
+
property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
new_buf_count.buffer_type = HAL_BUFFER_INPUT;
new_buf_count.buffer_count_actual = *num_buffers;
+
rc = call_hfi_op(hdev, session_set_property, inst->session,
property_id, &new_buf_count);
dprintk(VIDC_DBG, "size = %d, alignment = %d, count = %d\n",
@@ -980,6 +995,7 @@
i, inst->prop.height[OUTPUT_PORT],
inst->prop.width[OUTPUT_PORT]);
}
+
break;
default:
dprintk(VIDC_ERR, "Invalid q type = %d\n", q->type);
@@ -1060,9 +1076,7 @@
goto fail_start;
}
- mutex_lock(&inst->core->sync_lock);
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
rc = msm_comm_try_state(inst, MSM_VIDC_START_DONE);
if (rc) {
@@ -1139,9 +1153,7 @@
break;
}
- mutex_lock(&inst->core->sync_lock);
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
if (rc)
dprintk(VIDC_ERR,
@@ -1277,7 +1289,7 @@
default:
goto unknown_value;
}
- /* H263 */
+ /* H263 */
case V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE:
switch (value) {
case V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE:
@@ -1370,6 +1382,17 @@
default:
goto unknown_value;
}
+ case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
+ switch (value) {
+ case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED:
+ return HAL_H264_DB_MODE_DISABLE;
+ case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED:
+ return HAL_H264_DB_MODE_ALL_BOUNDARY;
+ case L_MODE:
+ return HAL_H264_DB_MODE_SKIP_SLICE_BOUNDARY;
+ default:
+ goto unknown_value;
+ }
}
unknown_value:
@@ -1978,23 +2001,58 @@
break;
}
case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
- property_id =
- HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
- h264_db_control.mode = ctrl->val;
+ {
+ struct v4l2_ctrl *alpha, *beta;
+
+ alpha = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA);
+ beta = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA);
+
+ property_id = HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
+ h264_db_control.slice_alpha_offset = alpha->val;
+ h264_db_control.slice_beta_offset = beta->val;
+ h264_db_control.mode = venc_v4l2_to_hal(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
+ ctrl->val);
pdata = &h264_db_control;
break;
+ }
case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:
- property_id =
- HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
+ {
+ struct v4l2_ctrl *mode, *beta;
+
+ mode = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE);
+ beta = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA);
+
+ property_id = HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
h264_db_control.slice_alpha_offset = ctrl->val;
+ h264_db_control.slice_beta_offset = beta->val;
+ h264_db_control.mode = venc_v4l2_to_hal(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
+ mode->val);
pdata = &h264_db_control;
break;
+ }
case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:
- property_id =
- HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
+ {
+ struct v4l2_ctrl *mode, *alpha;
+
+ mode = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE);
+ alpha = TRY_GET_CTRL(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA);
+ property_id = HAL_PARAM_VENC_H264_DEBLOCK_CONTROL;
+ h264_db_control.slice_alpha_offset = alpha->val;
h264_db_control.slice_beta_offset = ctrl->val;
+ h264_db_control.mode = venc_v4l2_to_hal(
+ V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
+ mode->val);
pdata = &h264_db_control;
break;
+ }
case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
property_id =
HAL_PARAM_VENC_SYNC_FRAME_SEQUENCE_HEADER;
@@ -2496,9 +2554,8 @@
dprintk(VIDC_WARN,
"Failed to set frame rate %d\n", rc);
}
- mutex_lock(&inst->core->sync_lock);
+
msm_comm_scale_clocks_and_bus(inst);
- mutex_unlock(&inst->core->sync_lock);
}
exit:
return rc;
@@ -3040,6 +3097,11 @@
int msm_venc_ctrl_deinit(struct msm_vidc_inst *inst)
{
+ if (!inst) {
+ dprintk(VIDC_ERR, "%s invalid parameters\n", __func__);
+ return -EINVAL;
+ }
+
kfree(inst->ctrls);
kfree(inst->cluster);
v4l2_ctrl_handler_free(&inst->ctrl_handler);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index bfa9025..cfc2eb8 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -1276,9 +1276,9 @@
setup_event_queue(inst, &core->vdev[session_type].vdev);
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
list_add_tail(&inst->list, &core->instances);
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
return inst;
fail_init:
vb2_queue_release(&inst->bufq[OUTPUT_PORT].vb2_bufq);
@@ -1373,13 +1373,13 @@
}
core = inst->core;
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
list_for_each_safe(ptr, next, &core->instances) {
temp = list_entry(ptr, struct msm_vidc_inst, list);
if (temp == inst)
list_del(&inst->list);
}
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
if (inst->session_type == MSM_VIDC_DECODER)
msm_vdec_ctrl_deinit(inst);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index 7833500..7429466 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -51,9 +51,10 @@
enum session_type type)
{
struct msm_vidc_inst *inst = NULL;
+ bool wants_turbo = false;
+ mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list) {
- bool wants_turbo = false;
mutex_lock(&inst->lock);
if (inst->session_type == type &&
@@ -64,10 +65,12 @@
mutex_unlock(&inst->lock);
if (wants_turbo)
- return true;
+ break;
}
- return false;
+ mutex_unlock(&core->lock);
+
+ return wants_turbo;
}
static bool is_thumbnail_session(struct msm_vidc_inst *inst)
@@ -117,6 +120,7 @@
dprintk(VIDC_ERR, "Invalid args: %p\n", core);
return -EINVAL;
}
+ mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list) {
mutex_lock(&inst->lock);
if (inst->session_type == type &&
@@ -128,6 +132,7 @@
}
mutex_unlock(&inst->lock);
}
+ mutex_unlock(&core->lock);
return num_mbs_per_sec;
}
@@ -869,13 +874,12 @@
core = handler->core;
hdev = core->device;
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
/*
* Restart the firmware to bring out of bad state.
*/
if ((core->state == VIDC_CORE_INVALID) &&
hdev->resurrect_fw) {
- mutex_lock(&core->lock);
rc = call_hfi_op(hdev, resurrect_fw,
hdev->hfi_device_data);
if (rc) {
@@ -884,12 +888,11 @@
__func__, rc);
}
core->state = VIDC_CORE_LOADED;
- mutex_unlock(&core->lock);
} else {
dprintk(VIDC_DBG,
"fw unloaded after sys error, no need to resurrect\n");
}
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
exit:
/* free sys error handler, allocated in handle_sys_err */
@@ -922,13 +925,11 @@
dprintk(VIDC_WARN, "SYS_ERROR %d received for core %p\n", cmd, core);
mutex_lock(&core->lock);
core->state = VIDC_CORE_INVALID;
- mutex_unlock(&core->lock);
/*
* 1. Delete each instance session from hfi list
* 2. Notify all clients about hardware error.
*/
- mutex_lock(&core->sync_lock);
list_for_each_entry(inst, &core->instances,
list) {
mutex_lock(&inst->lock);
@@ -950,7 +951,7 @@
msm_vidc_queue_v4l2_event(inst,
V4L2_EVENT_MSM_VIDC_SYS_ERROR);
}
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
handler = kzalloc(sizeof(*handler), GFP_KERNEL);
@@ -1604,7 +1605,7 @@
{
struct msm_vidc_core *core = inst->core;
int rc = 0;
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
if (core->state >= VIDC_CORE_INIT_DONE) {
dprintk(VIDC_INFO, "Video core: %d is already in state: %d\n",
core->id, core->state);
@@ -1620,16 +1621,14 @@
rc = -EIO;
goto exit;
} else {
- mutex_lock(&core->lock);
core->state = VIDC_CORE_INIT_DONE;
- mutex_unlock(&core->lock);
}
dprintk(VIDC_DBG, "SYS_INIT_DONE!!!\n");
core_already_inited:
change_inst_state(inst, MSM_VIDC_CORE_INIT_DONE);
rc = 0;
exit:
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
return rc;
}
@@ -1643,12 +1642,13 @@
return -EINVAL;
hdev = core->device;
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
if (core->state >= VIDC_CORE_INIT) {
dprintk(VIDC_INFO, "Video core: %d is already in state: %d\n",
core->id, core->state);
goto core_already_inited;
}
+ mutex_unlock(&core->lock);
rc = msm_comm_scale_bus(core, inst->session_type, DDR_MEM);
if (rc) {
@@ -1656,13 +1656,16 @@
goto fail_scale_bus;
}
+ mutex_lock(&core->lock);
if (core->state < VIDC_CORE_LOADED) {
rc = call_hfi_op(hdev, load_fw, hdev->hfi_device_data);
if (rc) {
dprintk(VIDC_ERR, "Failed to load video firmware\n");
goto fail_load_fw;
}
+ core->state = VIDC_CORE_LOADED;
}
+ mutex_unlock(&core->lock);
rc = msm_comm_scale_clocks(core);
if (rc) {
@@ -1670,25 +1673,29 @@
goto fail_core_init;
}
- init_completion(&core->completions[SYS_MSG_INDEX(SYS_INIT_DONE)]);
- rc = call_hfi_op(hdev, core_init, hdev->hfi_device_data);
- if (rc) {
- dprintk(VIDC_ERR, "Failed to init core, id = %d\n", core->id);
- goto fail_core_init;
- }
mutex_lock(&core->lock);
- core->state = VIDC_CORE_INIT;
- mutex_unlock(&core->lock);
+ if (core->state == VIDC_CORE_LOADED) {
+ init_completion(&core->completions
+ [SYS_MSG_INDEX(SYS_INIT_DONE)]);
+ rc = call_hfi_op(hdev, core_init, hdev->hfi_device_data);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to init core, id = %d\n",
+ core->id);
+ goto fail_core_init;
+ }
+ core->state = VIDC_CORE_INIT;
+ }
+
core_already_inited:
change_inst_state(inst, MSM_VIDC_CORE_INIT);
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
return rc;
fail_core_init:
call_hfi_op(hdev, unload_fw, hdev->hfi_device_data);
fail_load_fw:
msm_comm_unvote_buses(core, DDR_MEM);
fail_scale_bus:
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
return rc;
}
@@ -1706,14 +1713,17 @@
core = inst->core;
hdev = core->device;
- mutex_lock(&core->sync_lock);
+ mutex_lock(&core->lock);
if (core->state == VIDC_CORE_UNINIT) {
dprintk(VIDC_INFO, "Video core: %d is already in state: %d\n",
core->id, core->state);
goto core_already_uninited;
}
+ mutex_unlock(&core->lock);
msm_comm_scale_clocks_and_bus(inst);
+
+ mutex_lock(&core->lock);
if (list_empty(&core->instances)) {
if (core->state > VIDC_CORE_INIT) {
if (core->resources.has_ocmem) {
@@ -1732,9 +1742,9 @@
goto exit;
}
}
- mutex_lock(&core->lock);
+
core->state = VIDC_CORE_UNINIT;
- mutex_unlock(&core->lock);
+
call_hfi_op(hdev, unload_fw, hdev->hfi_device_data);
if (core->resources.has_ocmem)
msm_comm_unvote_buses(core, DDR_MEM|OCMEM_MEM);
@@ -1745,7 +1755,7 @@
core_already_uninited:
change_inst_state(inst, MSM_VIDC_CORE_UNINIT);
exit:
- mutex_unlock(&core->sync_lock);
+ mutex_unlock(&core->lock);
return rc;
}
@@ -1874,6 +1884,8 @@
struct msm_vidc_inst *temp;
dprintk(VIDC_ERR, "Running instances:\n");
dprintk(VIDC_ERR, "%4s|%4s|%4s|%4s\n", "type", "w", "h", "fps");
+
+ mutex_lock(&core->lock);
list_for_each_entry(temp, &core->instances, list) {
mutex_lock(&temp->lock);
if (temp->state >= MSM_VIDC_OPEN_DONE &&
@@ -1886,6 +1898,7 @@
}
mutex_unlock(&temp->lock);
}
+ mutex_unlock(&core->lock);
}
static int msm_vidc_load_resources(int flipped_state,
@@ -1914,10 +1927,8 @@
return -EINVAL;
}
- mutex_lock(&inst->core->sync_lock);
num_mbs_per_sec = msm_comm_get_load(inst->core, MSM_VIDC_DECODER);
num_mbs_per_sec += msm_comm_get_load(inst->core, MSM_VIDC_ENCODER);
- mutex_unlock(&inst->core->sync_lock);
if (num_mbs_per_sec > inst->core->resources.max_load) {
dprintk(VIDC_ERR, "HW is overloaded, needed: %d max: %d\n",
@@ -1941,16 +1952,14 @@
inst->prop.width[OUTPUT_PORT]);
ocmem_sz = get_ocmem_requirement(
height, width);
- mutex_lock(&inst->core->sync_lock);
rc = msm_comm_scale_bus(inst->core, inst->session_type,
OCMEM_MEM);
- mutex_unlock(&inst->core->sync_lock);
if (!rc) {
- mutex_lock(&inst->core->sync_lock);
+ mutex_lock(&inst->core->lock);
rc = call_hfi_op(hdev, alloc_ocmem,
hdev->hfi_device_data,
ocmem_sz);
- mutex_unlock(&inst->core->sync_lock);
+ mutex_unlock(&inst->core->lock);
if (rc) {
dprintk(VIDC_WARN,
"Failed to allocate OCMEM. Performance will be impacted\n");
@@ -2562,13 +2571,6 @@
mutex_unlock(&inst->sync_lock);
} else {
int64_t time_usec = timeval_to_ns(&vb->v4l2_buf.timestamp);
-
- rc = msm_vidc_check_session_supported(inst);
- if (rc) {
- dprintk(VIDC_ERR,
- "%s: session not supported\n", __func__);
- goto err_no_mem;
- }
do_div(time_usec, NSEC_PER_USEC);
memset(&frame_data, 0 , sizeof(struct vidc_frame_data));
frame_data.alloc_len = vb->v4l2_planes[0].length;
@@ -3353,20 +3355,16 @@
int num_mbs_per_sec = 0;
if (inst->state == MSM_VIDC_OPEN_DONE) {
- mutex_lock(&inst->core->sync_lock);
num_mbs_per_sec = msm_comm_get_load(inst->core,
MSM_VIDC_DECODER);
num_mbs_per_sec += msm_comm_get_load(inst->core,
MSM_VIDC_ENCODER);
- mutex_unlock(&inst->core->sync_lock);
if (num_mbs_per_sec > inst->core->resources.max_load) {
dprintk(VIDC_ERR,
"H/w is overloaded. needed: %d max: %d\n",
num_mbs_per_sec,
inst->core->resources.max_load);
- mutex_lock(&inst->sync_lock);
msm_vidc_print_running_insts(inst->core);
- mutex_unlock(&inst->sync_lock);
return -EINVAL;
}
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
index e9bf91d..1677e57 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
@@ -199,7 +199,7 @@
struct msm_vidc_core {
struct list_head list;
- struct mutex sync_lock, lock;
+ struct mutex lock;
int id;
void *device;
struct msm_video_device vdev[MSM_VIDC_MAX_DEVICES];
diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c
index 37b1e72..448fe3b 100644
--- a/drivers/media/platform/msm/vidc/venus_hfi.c
+++ b/drivers/media/platform/msm/vidc/venus_hfi.c
@@ -3739,45 +3739,11 @@
int venus_hfi_get_core_capabilities(void)
{
- int i = 0, rc = 0, j = 0, venus_version_length = 0;
- u32 smem_block_size = 0;
- u8 *smem_table_ptr;
- char version[256];
- const u32 version_string_size = 128;
- char venus_version[] = "VIDEO.VE.1.4";
- u8 version_info[256];
- const u32 smem_image_index_venus = 14 * 128;
- /* Venus version is stored at 14th entry in smem table */
-
- smem_table_ptr = smem_get_entry(SMEM_IMAGE_VERSION_TABLE,
- &smem_block_size);
- if (smem_table_ptr &&
- ((smem_image_index_venus + version_string_size) <=
- smem_block_size)) {
- memcpy(version_info, smem_table_ptr + smem_image_index_venus,
- version_string_size);
- } else {
- dprintk(VIDC_ERR,
- "%s: failed to read version info from smem table\n",
- __func__);
- return -EINVAL;
- }
-
- while (version_info[i++] != 'V' && i < version_string_size)
- ;
-
- venus_version_length = strlen(venus_version);
- for (i--, j = 0; i < version_string_size && j < venus_version_length;
- i++)
- version[j++] = version_info[i];
- version[venus_version_length] = '\0';
- dprintk(VIDC_DBG, "F/W version retrieved : %s\n", version);
-
- if (strcmp((const char *)version, (const char *)venus_version) == 0)
- rc = HAL_VIDEO_ENCODER_ROTATION_CAPABILITY |
- HAL_VIDEO_ENCODER_SCALING_CAPABILITY |
- HAL_VIDEO_ENCODER_DEINTERLACE_CAPABILITY |
- HAL_VIDEO_DECODER_MULTI_STREAM_CAPABILITY;
+ int rc = 0;
+ rc = HAL_VIDEO_ENCODER_ROTATION_CAPABILITY |
+ HAL_VIDEO_ENCODER_SCALING_CAPABILITY |
+ HAL_VIDEO_ENCODER_DEINTERLACE_CAPABILITY |
+ HAL_VIDEO_DECODER_MULTI_STREAM_CAPABILITY;
return rc;
}
diff --git a/drivers/media/video/videobuf2-core.c b/drivers/media/video/videobuf2-core.c
index e5311ce..6cea218 100644
--- a/drivers/media/video/videobuf2-core.c
+++ b/drivers/media/video/videobuf2-core.c
@@ -513,13 +513,6 @@
return -EINVAL;
}
- /*
- * If the same number of buffers and memory access method is requested
- * then return immediately.
- */
- if (q->memory == req->memory && req->count == q->num_buffers)
- return 0;
-
if (req->count == 0 || q->num_buffers != 0 || q->memory != req->memory) {
/*
* We already have buffers allocated, so first check if they
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index dbc7d5c..36bf643 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -698,11 +698,11 @@
struct mmc_context_info *context_info = &host->context_info;
bool pending_is_urgent = false;
bool is_urgent = false;
- int err;
+ int err, ret;
unsigned long flags;
while (1) {
- wait_io_event_interruptible(context_info->wait,
+ ret = wait_io_event_interruptible(context_info->wait,
(context_info->is_done_rcv ||
context_info->is_new_req ||
context_info->is_urgent));
@@ -755,7 +755,7 @@
err = MMC_BLK_NEW_REQUEST;
break; /* return err */
}
- } else {
+ } else if (context_info->is_urgent) {
/*
* The case when block layer sent next urgent
* notification before it receives end_io on
@@ -807,6 +807,11 @@
pending_is_urgent = true;
continue; /* wait for done/new/urgent event */
}
+ } else {
+ pr_warn("%s: mmc thread unblocked from waiting by signal, ret=%d\n",
+ mmc_hostname(host),
+ ret);
+ continue;
}
} /* while */
return err;
@@ -3234,7 +3239,8 @@
mmc_release_host(host);
mmc_rpm_release(host, &host->class_dev);
out:
- if (extend_wakelock)
+ /* only extend the wakelock, if suspend has not started yet */
+ if (extend_wakelock && !host->rescan_disable)
wake_lock_timeout(&host->detect_wake_lock, HZ / 2);
if (host->caps & MMC_CAP_NEEDS_POLL)
@@ -3619,16 +3625,15 @@
spin_unlock_irqrestore(&host->lock, flags);
break;
}
+
+ /* since its suspending anyway, disable rescan */
+ host->rescan_disable = 1;
spin_unlock_irqrestore(&host->lock, flags);
/* Wait for pending detect work to be completed */
if (!(host->caps & MMC_CAP_NEEDS_POLL))
flush_work(&host->detect.work);
- spin_lock_irqsave(&host->lock, flags);
- host->rescan_disable = 1;
- spin_unlock_irqrestore(&host->lock, flags);
-
/*
* In some cases, the detect work might be scheduled
* just before rescan_disable is set to true.
@@ -3636,6 +3641,13 @@
*/
cancel_delayed_work_sync(&host->detect);
+ /*
+ * It is possible that the wake-lock has been acquired, since
+ * its being suspended, release the wakelock
+ */
+ if (wake_lock_active(&host->detect_wake_lock))
+ wake_unlock(&host->detect_wake_lock);
+
if (!host->bus_ops || host->bus_ops->suspend)
break;
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 1e53c1e..c1f366e 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1264,8 +1264,7 @@
mmc_set_clock(host, (unsigned int) (*freq));
}
- if ((mmc_card_hs400(card) || mmc_card_hs200(card))
- && card->host->ops->execute_tuning) {
+ if (mmc_card_hs200(card) && card->host->ops->execute_tuning) {
/*
* We try to probe host driver for tuning for any
* frequency, it is host driver responsibility to
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 179632c..783f512 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -1399,7 +1399,11 @@
*/
#ifdef CONFIG_MMC_PARANOID_SD_INIT
retries = 5;
- while (retries) {
+ /*
+ * Some bad cards may take a long time to init, give preference to
+ * suspend in those cases.
+ */
+ while (retries && !host->rescan_disable) {
err = mmc_sd_init_card(host, host->ocr, NULL);
if (err) {
retries--;
@@ -1417,6 +1421,9 @@
mmc_hostname(host), err);
goto err;
}
+
+ if (host->rescan_disable)
+ goto err;
#else
err = mmc_sd_init_card(host, host->ocr, NULL);
if (err)
@@ -1440,9 +1447,9 @@
mmc_claim_host(host);
err:
mmc_detach_bus(host);
-
- pr_err("%s: error %d whilst initialising SD card\n",
- mmc_hostname(host), err);
+ if (err)
+ pr_err("%s: error %d whilst initialising SD card: rescan: %d\n",
+ mmc_hostname(host), err, host->rescan_disable);
return err;
}
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 074b6a8..2c96d3c 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -876,6 +876,14 @@
memset(data_buf, 0, size);
mmc_wait_for_req(mmc, &mrq);
+ /*
+ * wait for 146 MCLK cycles for the card to send out the data
+ * and thus move to TRANS state. As the MCLK would be minimum
+ * 200MHz when tuning is performed, we need maximum 0.73us
+ * delay. To be on safer side 1ms delay is given.
+ */
+ if (cmd.error)
+ usleep_range(1000, 1200);
if (!cmd.error && !data.error &&
!memcmp(data_buf, tuning_block_pattern, size)) {
/* tuning is successful at this tuning point */
@@ -2897,7 +2905,6 @@
host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK;
- host->quirks2 |= SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING;
host->quirks2 |= SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE;
host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD;
host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 32ff175..277aef5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2591,17 +2591,6 @@
host->cmd->error = -EILSEQ;
}
- if (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING) {
- if ((host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS400) ||
- (host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
- (host->cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
- if (intmask & SDHCI_INT_CRC) {
- sdhci_reset(host, SDHCI_RESET_CMD);
- host->cmd->error = 0;
- }
- }
- }
-
if (host->cmd->error) {
if (host->cmd->error == -EILSEQ)
host->flags |= SDHCI_NEEDS_RETUNING;
@@ -2631,17 +2620,6 @@
* fall through and take the SDHCI_INT_RESPONSE */
}
- if (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING) {
- if ((host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS400) ||
- (host->cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
- (host->cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
- if (intmask & SDHCI_INT_CRC) {
- sdhci_finish_command(host);
- return;
- }
- }
- }
-
if (intmask & SDHCI_INT_RESPONSE)
sdhci_finish_command(host);
}
@@ -2727,8 +2705,7 @@
host->data->error = -EIO;
}
if (host->data->error) {
- if ((intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT)) &&
- (host->quirks2 & SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING)) {
+ if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT)) {
command = SDHCI_GET_CMD(sdhci_readw(host,
SDHCI_COMMAND));
if ((command != MMC_SEND_TUNING_BLOCK_HS400) &&
diff --git a/drivers/net/wireless/wcnss/wcnss_vreg.c b/drivers/net/wireless/wcnss/wcnss_vreg.c
index 4713d29..c066acd 100644
--- a/drivers/net/wireless/wcnss/wcnss_vreg.c
+++ b/drivers/net/wireless/wcnss/wcnss_vreg.c
@@ -51,6 +51,8 @@
#define WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP BIT(5)
#define WCNSS_PMU_CFG_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
+#define WCNSS_PMU_CFG_IRIS_RESET BIT(7)
+#define WCNSS_PMU_CFG_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
#define WCNSS_PMU_CFG_IRIS_XO_READ BIT(9)
#define WCNSS_PMU_CFG_IRIS_XO_READ_STS BIT(10)
@@ -258,6 +260,19 @@
writel_relaxed(reg, pmu_conf_reg);
+ /* Reset IRIS */
+ reg |= WCNSS_PMU_CFG_IRIS_RESET;
+ writel_relaxed(reg, pmu_conf_reg);
+
+ /* Wait for PMU_CFG.iris_reg_reset_sts */
+ while (readl_relaxed(pmu_conf_reg) &
+ WCNSS_PMU_CFG_IRIS_RESET_STS)
+ cpu_relax();
+
+ /* Reset iris reset bit */
+ reg &= ~WCNSS_PMU_CFG_IRIS_RESET;
+ writel_relaxed(reg, pmu_conf_reg);
+
/* Start IRIS XO configuration */
reg |= WCNSS_PMU_CFG_IRIS_XO_CFG;
writel_relaxed(reg, pmu_conf_reg);
diff --git a/drivers/net/wireless/wcnss/wcnss_wlan.c b/drivers/net/wireless/wcnss/wcnss_wlan.c
index e03d5be..05264b4 100644
--- a/drivers/net/wireless/wcnss/wcnss_wlan.c
+++ b/drivers/net/wireless/wcnss/wcnss_wlan.c
@@ -129,10 +129,10 @@
#define WCNSS_TSTBUS_CTRL_WRFIFO (0x04 << 1)
#define WCNSS_TSTBUS_CTRL_RDFIFO (0x05 << 1)
#define WCNSS_TSTBUS_CTRL_CTRL (0x07 << 1)
-#define WCNSS_TSTBUS_CTRL_AXIM_CFG0 (0x00 << 6)
-#define WCNSS_TSTBUS_CTRL_AXIM_CFG1 (0x01 << 6)
-#define WCNSS_TSTBUS_CTRL_CTRL_CFG0 (0x00 << 12)
-#define WCNSS_TSTBUS_CTRL_CTRL_CFG1 (0x01 << 12)
+#define WCNSS_TSTBUS_CTRL_AXIM_CFG0 (0x00 << 8)
+#define WCNSS_TSTBUS_CTRL_AXIM_CFG1 (0x01 << 8)
+#define WCNSS_TSTBUS_CTRL_CTRL_CFG0 (0x00 << 28)
+#define WCNSS_TSTBUS_CTRL_CTRL_CFG1 (0x01 << 28)
#define MSM_PRONTO_CCPU_BASE 0xfb205050
#define CCU_PRONTO_INVALID_ADDR_OFFSET 0x08
diff --git a/drivers/nfc/nfc-nci.c b/drivers/nfc/nfc-nci.c
index 8cd4bd1..018c3a6 100644
--- a/drivers/nfc/nfc-nci.c
+++ b/drivers/nfc/nfc-nci.c
@@ -1169,10 +1169,7 @@
r = of_property_read_string(np, "qcom,clk-src", &pdata->clk_src_name);
if (strcmp(pdata->clk_src_name, "GPCLK2")) {
- r = of_property_read_u32(np, "qcom,clk-gpio",
- &pdata->clkreq_gpio);
- if (r)
- return -EINVAL;
+ pdata->clkreq_gpio = of_get_named_gpio(np, "qcom,clk-gpio", 0);
}
if ((!strcmp(pdata->clk_src_name, "GPCLK")) ||
@@ -1186,6 +1183,7 @@
if ((!gpio_is_valid(pdata->irq_gpio_clk_req)))
return -EINVAL;
}
+
if (r)
return -EINVAL;
return r;
@@ -1196,7 +1194,6 @@
{
int r = 0;
int irqn = 0;
- struct device_node *node = client->dev.of_node;
struct qca199x_platform_data *platform_data;
struct qca199x_dev *qca199x_dev;
@@ -1348,9 +1345,6 @@
}
if (strcmp(platform_data->clk_src_name, "GPCLK2")) {
- platform_data->clkreq_gpio =
- of_get_named_gpio(node, "qcom,clk-gpio", 0);
-
if (gpio_is_valid(platform_data->clkreq_gpio)) {
r = gpio_request(platform_data->clkreq_gpio,
"nfc_clkreq_gpio");
diff --git a/drivers/slimbus/slim-msm-ngd.c b/drivers/slimbus/slim-msm-ngd.c
index 0035349..b4c88cd 100644
--- a/drivers/slimbus/slim-msm-ngd.c
+++ b/drivers/slimbus/slim-msm-ngd.c
@@ -301,17 +301,9 @@
*/
ngd_slim_runtime_resume(dev->dev);
}
- if ((txn->mc == (SLIM_MSG_CLK_PAUSE_SEQ_FLG |
- SLIM_MSG_MC_RECONFIGURE_NOW)) &&
- dev->state <= MSM_CTRL_IDLE) {
- msm_slim_disconnect_endp(dev, &dev->rx_msgq,
- &dev->use_rx_msgqs);
- msm_slim_disconnect_endp(dev, &dev->tx_msgq,
- &dev->use_tx_msgqs);
- return msm_slim_qmi_power_request(dev, false);
- }
+
else if (txn->mc & SLIM_MSG_CLK_PAUSE_SEQ_FLG)
- return 0;
+ return -EPROTONOSUPPORT;
if (txn->mt == SLIM_MSG_MT_CORE &&
(txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
@@ -385,6 +377,7 @@
if (report_sat == false && dev->state != MSM_CTRL_AWAKE) {
SLIM_ERR(dev, "controller not ready\n");
mutex_unlock(&dev->tx_lock);
+ pm_runtime_set_suspended(dev->dev);
msm_slim_put_ctrl(dev);
return -EREMOTEIO;
}
@@ -1074,20 +1067,7 @@
ret = msm_slim_qmi_init(dev, false);
/* controller state should be in sync with framework state */
if (!ret) {
- ret = slim_ctrl_clk_pause(&dev->ctrl, false,
- SLIM_CLK_UNSPECIFIED);
complete(&dev->qmi.qmi_comp);
- /*
- * Power-up won't be called if clock pause failed.
- * This can happen if ADSP SSR happened when audio
- * session is in progress. Framework will think that
- * clock pause failed so no need to wakeup controller.
- * Call power-up explicitly in that case, since slimbus
- * HW needs to be powered-on to be in sync with
- * framework state
- */
- if (ret)
- ngd_slim_power_up(dev, false);
if (!pm_runtime_enabled(dev->dev) ||
!pm_runtime_suspended(dev->dev))
ngd_slim_runtime_resume(dev->dev);
@@ -1105,10 +1085,25 @@
return ret;
}
-static int ngd_clk_pause_wakeup(struct slim_controller *ctrl)
+static int ngd_slim_power_down(struct msm_slim_ctrl *dev)
{
- struct msm_slim_ctrl *dev = slim_get_ctrldata(ctrl);
- return ngd_slim_power_up(dev, false);
+ int i;
+ struct slim_controller *ctrl = &dev->ctrl;
+ mutex_lock(&ctrl->m_ctrl);
+ /* Pending response for a message */
+ for (i = 0; i < ctrl->last_tid; i++) {
+ if (ctrl->txnt[i]) {
+ SLIM_INFO(dev, "NGD down:txn-rsp for %d pending", i);
+ mutex_unlock(&ctrl->m_ctrl);
+ return -EBUSY;
+ }
+ }
+ mutex_unlock(&ctrl->m_ctrl);
+ msm_slim_disconnect_endp(dev, &dev->rx_msgq,
+ &dev->use_rx_msgqs);
+ msm_slim_disconnect_endp(dev, &dev->tx_msgq,
+ &dev->use_tx_msgqs);
+ return msm_slim_qmi_power_request(dev, false);
}
static int ngd_slim_rx_msgq_thread(void *data)
@@ -1365,7 +1360,7 @@
dev->ctrl.allocbw = ngd_allocbw;
dev->ctrl.xfer_msg = ngd_xfer_msg;
dev->ctrl.xfer_user_msg = ngd_user_msg;
- dev->ctrl.wakeup = ngd_clk_pause_wakeup;
+ dev->ctrl.wakeup = NULL;
dev->ctrl.alloc_port = msm_alloc_port;
dev->ctrl.dealloc_port = msm_dealloc_port;
dev->ctrl.port_xfer = msm_slim_port_xfer;
@@ -1528,9 +1523,9 @@
struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
int ret = 0;
if (dev->state >= MSM_CTRL_ASLEEP)
- ret = slim_ctrl_clk_pause(&dev->ctrl, true, 0);
+ ret = ngd_slim_power_up(dev, false);
if (ret) {
- /* Did SSR cause this clock pause failure */
+ /* Did SSR cause this power up failure */
if (dev->state != MSM_CTRL_DOWN)
dev->state = MSM_CTRL_ASLEEP;
else
@@ -1548,10 +1543,10 @@
struct platform_device *pdev = to_platform_device(device);
struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
int ret = 0;
- ret = slim_ctrl_clk_pause(&dev->ctrl, false, SLIM_CLK_UNSPECIFIED);
+ ret = ngd_slim_power_down(dev);
if (ret) {
if (ret != -EBUSY)
- SLIM_INFO(dev, "clk pause not entered:%d\n", ret);
+ SLIM_INFO(dev, "slim resource not idle:%d\n", ret);
dev->state = MSM_CTRL_AWAKE;
} else {
dev->state = MSM_CTRL_ASLEEP;
diff --git a/drivers/spi/spi_qsd.c b/drivers/spi/spi_qsd.c
index d670f8b..d8dc6f9 100644
--- a/drivers/spi/spi_qsd.c
+++ b/drivers/spi/spi_qsd.c
@@ -50,7 +50,7 @@
static int msm_spi_pm_resume_runtime(struct device *device);
static int msm_spi_pm_suspend_runtime(struct device *device);
-
+static inline void msm_spi_dma_unmap_buffers(struct msm_spi *dd);
static inline int msm_spi_configure_gsbi(struct msm_spi *dd,
struct platform_device *pdev)
@@ -135,6 +135,40 @@
}
}
+static inline int msm_spi_request_cs_gpio(struct msm_spi *dd)
+{
+ int cs_num;
+ int rc;
+
+ cs_num = dd->cur_msg->spi->chip_select;
+ if ((!(dd->cur_msg->spi->mode & SPI_LOOP)) &&
+ (!(dd->cs_gpios[cs_num].valid)) &&
+ (dd->cs_gpios[cs_num].gpio_num >= 0)) {
+ rc = gpio_request(dd->cs_gpios[cs_num].gpio_num,
+ spi_cs_rsrcs[cs_num]);
+ if (rc) {
+ dev_err(dd->dev,
+ "gpio_request for pin %d failed,error %d\n",
+ dd->cs_gpios[cs_num].gpio_num, rc);
+ return rc;
+ }
+ dd->cs_gpios[cs_num].valid = 1;
+ }
+ return 0;
+}
+
+static inline void msm_spi_free_cs_gpio(struct msm_spi *dd)
+{
+ int cs_num;
+
+ cs_num = dd->cur_msg->spi->chip_select;
+ if (dd->cs_gpios[cs_num].valid) {
+ gpio_free(dd->cs_gpios[cs_num].gpio_num);
+ dd->cs_gpios[cs_num].valid = 0;
+ }
+}
+
+
/**
* msm_spi_clk_max_rate: finds the nearest lower rate for a clk
* @clk the clock for which to find nearest lower rate
@@ -785,117 +819,190 @@
msm_spi_bam_pipe_flush(dd, SPI_BAM_PRODUCER_PIPE);
}
+static int
+msm_spi_bam_process_rx(struct msm_spi *dd, u32 *bytes_to_send, u32 desc_cnt)
+{
+ int ret = 0;
+ u32 data_xfr_size = 0, rem_bc = 0;
+ u32 prod_flags = 0;
+
+ rem_bc = dd->cur_rx_transfer->len - dd->bam.curr_rx_bytes_recvd;
+ data_xfr_size = (rem_bc < *bytes_to_send) ? rem_bc : *bytes_to_send;
+
+ /*
+ * set flags for last descriptor only
+ */
+ if ((desc_cnt == 1)
+ || (*bytes_to_send == data_xfr_size))
+ prod_flags = (dd->write_buf)
+ ? 0 : (SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_NWD);
+
+ /*
+ * enqueue read buffer in BAM
+ */
+ ret = sps_transfer_one(dd->bam.prod.handle,
+ dd->cur_rx_transfer->rx_dma
+ + dd->bam.curr_rx_bytes_recvd,
+ data_xfr_size, dd, prod_flags);
+ if (ret < 0) {
+ dev_err(dd->dev,
+ "%s: Failed to queue producer BAM transfer",
+ __func__);
+ return ret;
+ }
+
+ dd->bam.curr_rx_bytes_recvd += data_xfr_size;
+ *bytes_to_send -= data_xfr_size;
+ dd->bam.bam_rx_len -= data_xfr_size;
+
+ if (!(dd->cur_rx_transfer->len - dd->bam.curr_rx_bytes_recvd)) {
+ struct spi_transfer *t = dd->cur_rx_transfer;
+ struct spi_transfer *next;
+ if (t->transfer_list.next != &dd->cur_msg->transfers) {
+ next = list_entry(t->transfer_list.next,
+ struct spi_transfer,
+ transfer_list);
+ dd->read_buf = next->rx_buf;
+ dd->cur_rx_transfer = next;
+ dd->bam.curr_rx_bytes_recvd = 0;
+ }
+ }
+ return data_xfr_size;
+}
+
+static int
+msm_spi_bam_process_tx(struct msm_spi *dd, u32 *bytes_to_send, u32 desc_cnt)
+{
+ int ret = 0;
+ u32 data_xfr_size = 0, rem_bc = 0;
+ u32 cons_flags = 0;
+
+ rem_bc = dd->cur_tx_transfer->len - dd->bam.curr_tx_bytes_sent;
+ data_xfr_size = (rem_bc < *bytes_to_send) ? rem_bc : *bytes_to_send;
+
+ /*
+ * set flags for last descriptor only
+ */
+ if ((desc_cnt == 1)
+ || (*bytes_to_send == data_xfr_size))
+ cons_flags = SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_NWD;
+
+ /*
+ * enqueue write buffer in BAM
+ */
+ ret = sps_transfer_one(dd->bam.cons.handle,
+ dd->cur_tx_transfer->tx_dma
+ + dd->bam.curr_tx_bytes_sent,
+ data_xfr_size, dd, cons_flags);
+ if (ret < 0) {
+ dev_err(dd->dev,
+ "%s: Failed to queue consumer BAM transfer",
+ __func__);
+ return ret;
+ }
+
+ dd->bam.curr_tx_bytes_sent += data_xfr_size;
+ *bytes_to_send -= data_xfr_size;
+ dd->bam.bam_tx_len -= data_xfr_size;
+
+ if (!(dd->cur_tx_transfer->len - dd->bam.curr_tx_bytes_sent)) {
+ struct spi_transfer *t = dd->cur_tx_transfer;
+ struct spi_transfer *next;
+ if (t->transfer_list.next != &dd->cur_msg->transfers) {
+ next = list_entry(t->transfer_list.next,
+ struct spi_transfer,
+ transfer_list);
+ dd->write_buf = next->tx_buf;
+ dd->cur_tx_transfer = next;
+ dd->bam.curr_tx_bytes_sent = 0;
+ }
+ }
+ return data_xfr_size;
+}
+
+
/**
* msm_spi_bam_begin_transfer: transfer dd->tx_bytes_remaining bytes
* using BAM.
* @brief BAM can transfer SPI_MAX_TRFR_BTWN_RESETS byte at a single
* transfer. Between transfer QUP must change to reset state. A loop is
- * issuing a single BAM transfer at a time. If another tsranfer is
- * required, it waits for the trasfer to finish, then moving to reset
- * state, and back to run state to issue the next transfer.
- * The function dose not wait for the last transfer to end, or if only
- * a single transfer is required, the function dose not wait for it to
- * end.
- * @timeout max time in jiffies to wait for a transfer to finish.
+ * issuing a single BAM transfer at a time.
* @return zero on success
*/
static int
-msm_spi_bam_begin_transfer(struct msm_spi *dd, u32 timeout, u8 bpw)
+msm_spi_bam_begin_transfer(struct msm_spi *dd)
{
- u32 bytes_to_send, bytes_sent, n_words_xfr, cons_flags, prod_flags;
- int ret;
- /*
- * QUP must move to reset mode every 64K-1 bytes of transfer
- * (counter is 16 bit)
- */
- if (dd->tx_bytes_remaining > SPI_MAX_TRFR_BTWN_RESETS) {
- /* assert chip select unconditionally */
- u32 spi_ioc = readl_relaxed(dd->base + SPI_IO_CONTROL);
- if (!(spi_ioc & SPI_IO_C_FORCE_CS))
- writel_relaxed(spi_ioc | SPI_IO_C_FORCE_CS,
- dd->base + SPI_IO_CONTROL);
+ u32 tx_bytes_to_send = 0, rx_bytes_to_recv = 0;
+ u32 n_words_xfr;
+ s32 ret = 0;
+ u32 prod_desc_cnt = SPI_BAM_MAX_DESC_NUM - 1;
+ u32 cons_desc_cnt = SPI_BAM_MAX_DESC_NUM - 1;
+ u32 byte_count = 0;
+
+
+ rx_bytes_to_recv = min_t(u32, dd->bam.bam_rx_len,
+ SPI_MAX_TRFR_BTWN_RESETS);
+ tx_bytes_to_send = min_t(u32, dd->bam.bam_tx_len,
+ SPI_MAX_TRFR_BTWN_RESETS);
+ n_words_xfr = DIV_ROUND_UP(rx_bytes_to_recv,
+ dd->bytes_per_word);
+
+ msm_spi_set_mx_counts(dd, n_words_xfr);
+ ret = msm_spi_set_state(dd, SPI_OP_STATE_RUN);
+ if (ret < 0) {
+ dev_err(dd->dev,
+ "%s: Failed to set QUP state to run",
+ __func__);
+ goto xfr_err;
}
- /* Following flags are required since we are waiting on all transfers */
- cons_flags = SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_NWD;
- /*
- * on a balanced transaction, BAM will set the flags on the producer
- * pipe based on the flags set on the consumer pipe
- */
- prod_flags = (dd->write_buf) ? 0 : cons_flags;
-
- while (dd->tx_bytes_remaining > 0) {
- bytes_sent = dd->cur_transfer->len - dd->tx_bytes_remaining;
- bytes_to_send = min_t(u32, dd->tx_bytes_remaining
- , SPI_MAX_TRFR_BTWN_RESETS);
- n_words_xfr = DIV_ROUND_UP(bytes_to_send
- , dd->bytes_per_word);
-
- msm_spi_set_mx_counts(dd, n_words_xfr);
-
- ret = msm_spi_set_state(dd, SPI_OP_STATE_RUN);
- if (ret < 0) {
- dev_err(dd->dev,
- "%s: Failed to set QUP state to run",
- __func__);
- goto xfr_err;
+ while ((rx_bytes_to_recv + tx_bytes_to_send) &&
+ ((cons_desc_cnt + prod_desc_cnt) > 0)) {
+ if (dd->read_buf && (prod_desc_cnt > 0)) {
+ ret = msm_spi_bam_process_rx(dd, &rx_bytes_to_recv,
+ prod_desc_cnt);
+ if (ret < 0)
+ goto xfr_err;
+ prod_desc_cnt--;
}
- /* enqueue read buffer in BAM */
- if (dd->read_buf) {
- ret = sps_transfer_one(dd->bam.prod.handle,
- dd->cur_transfer->rx_dma + bytes_sent,
- bytes_to_send, dd, prod_flags);
- if (ret < 0) {
- dev_err(dd->dev,
- "%s: Failed to queue producer BAM transfer",
- __func__);
+ if (dd->write_buf && (cons_desc_cnt > 0)) {
+ ret = msm_spi_bam_process_tx(dd, &tx_bytes_to_send,
+ cons_desc_cnt);
+ if (ret < 0)
goto xfr_err;
- }
+ cons_desc_cnt--;
}
-
- /* enqueue write buffer in BAM */
- if (dd->write_buf) {
- ret = sps_transfer_one(dd->bam.cons.handle,
- dd->cur_transfer->tx_dma + bytes_sent,
- bytes_to_send, dd, cons_flags);
- if (ret < 0) {
- dev_err(dd->dev,
- "%s: Failed to queue consumer BAM transfer",
- __func__);
- goto xfr_err;
- }
- }
-
- dd->tx_bytes_remaining -= bytes_to_send;
-
- /* move to reset state after SPI_MAX_TRFR_BTWN_RESETS */
- if (dd->tx_bytes_remaining > 0) {
- if (!wait_for_completion_timeout(
- &dd->transfer_complete, timeout)) {
- dev_err(dd->dev,
- "%s: SPI transaction timeout",
- __func__);
- dd->cur_msg->status = -EIO;
- ret = -EIO;
- goto xfr_err;
- }
- ret = msm_spi_set_state(dd, SPI_OP_STATE_RESET);
- if (ret < 0) {
- dev_err(dd->dev,
- "%s: Failed to set QUP state to reset",
- __func__);
- goto xfr_err;
- }
- init_completion(&dd->transfer_complete);
- }
+ byte_count += ret;
}
+
+ dd->tx_bytes_remaining -= min_t(u32, byte_count,
+ SPI_MAX_TRFR_BTWN_RESETS);
return 0;
-
xfr_err:
return ret;
}
+static int
+msm_spi_bam_next_transfer(struct msm_spi *dd)
+{
+ if (dd->mode != SPI_BAM_MODE)
+ return 0;
+
+ if (dd->tx_bytes_remaining > 0) {
+ init_completion(&dd->transfer_complete);
+ if (msm_spi_set_state(dd, SPI_OP_STATE_RESET))
+ return 0;
+ if ((msm_spi_bam_begin_transfer(dd)) < 0) {
+ dev_err(dd->dev, "%s: BAM transfer setup failed\n",
+ __func__);
+ return 0;
+ }
+ return 1;
+ }
+ return 0;
+}
+
static void msm_spi_setup_dm_transfer(struct msm_spi *dd)
{
dmov_box *box;
@@ -1098,6 +1205,16 @@
return 0;
}
+static int msm_spi_dma_send_next(struct msm_spi *dd)
+{
+ int ret = 0;
+ if (dd->mode == SPI_DMOV_MODE)
+ ret = msm_spi_dm_send_next(dd);
+ if (dd->mode == SPI_BAM_MODE)
+ ret = msm_spi_bam_next_transfer(dd);
+ return ret;
+}
+
static inline void msm_spi_ack_transfer(struct msm_spi *dd)
{
writel_relaxed(SPI_OP_MAX_INPUT_DONE_FLAG |
@@ -1297,14 +1414,14 @@
}
/**
- * msm_spi_dma_map_buffers: prepares buffer for DMA transfer
+ * msm_spi_dmov_map_buffers: prepares buffer for DMA transfer
* @return zero on success or negative error code
*
* calls dma_map_single() on the read/write buffers, effectively invalidating
* their cash entries. for For WR-WR and WR-RD transfers, allocates temporary
* buffer and copy the data to/from the client buffers
*/
-static int msm_spi_dma_map_buffers(struct msm_spi *dd)
+static int msm_spi_dmov_map_buffers(struct msm_spi *dd)
{
struct device *dev;
struct spi_transfer *first_xfr;
@@ -1323,7 +1440,7 @@
* For WR-WR and WR-RD transfers, we allocate our own temporary
* buffer and copy the data to/from the client buffers.
*/
- if (dd->multi_xfr) {
+ if (!dd->qup_ver && dd->multi_xfr) {
dd->temp_buf = kzalloc(dd->cur_msg_len,
GFP_KERNEL | __GFP_DMA);
if (!dd->temp_buf)
@@ -1384,6 +1501,70 @@
return ret;
}
+static int msm_spi_bam_map_buffers(struct msm_spi *dd)
+{
+ int ret = -EINVAL;
+ struct device *dev;
+ struct spi_transfer *first_xfr;
+ struct spi_transfer *nxt_xfr;
+ void *tx_buf, *rx_buf;
+ u32 tx_len, rx_len;
+ int num_xfrs_grped = dd->num_xfrs_grped;
+
+ dev = &dd->cur_msg->spi->dev;
+ first_xfr = dd->cur_transfer;
+
+ do {
+ tx_buf = (void *)first_xfr->tx_buf;
+ rx_buf = first_xfr->rx_buf;
+ tx_len = rx_len = first_xfr->len;
+ if (tx_buf != NULL) {
+ first_xfr->tx_dma = dma_map_single(dev, tx_buf,
+ tx_len, DMA_TO_DEVICE);
+ if (dma_mapping_error(NULL, first_xfr->tx_dma)) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ }
+
+ if (rx_buf != NULL) {
+ first_xfr->rx_dma = dma_map_single(dev, rx_buf, rx_len,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(NULL, first_xfr->rx_dma)) {
+ if (tx_buf != NULL)
+ dma_unmap_single(NULL,
+ first_xfr->tx_dma,
+ tx_len, DMA_TO_DEVICE);
+ ret = -ENOMEM;
+ goto error;
+ }
+ }
+
+ nxt_xfr = list_entry(first_xfr->transfer_list.next,
+ struct spi_transfer, transfer_list);
+
+ if (nxt_xfr == NULL)
+ break;
+ num_xfrs_grped--;
+ first_xfr = nxt_xfr;
+ } while (num_xfrs_grped > 0);
+
+ return 0;
+error:
+ msm_spi_dma_unmap_buffers(dd);
+ return ret;
+}
+
+static int msm_spi_dma_map_buffers(struct msm_spi *dd)
+{
+ int ret = 0;
+ if (dd->mode == SPI_DMOV_MODE)
+ ret = msm_spi_dmov_map_buffers(dd);
+ else if (dd->mode == SPI_BAM_MODE)
+ ret = msm_spi_bam_map_buffers(dd);
+ return ret;
+}
+
static void msm_spi_dmov_unmap_buffers(struct msm_spi *dd)
{
struct device *dev;
@@ -1455,21 +1636,39 @@
static void msm_spi_bam_unmap_buffers(struct msm_spi *dd)
{
struct device *dev;
+ int num_xfrs_grped = dd->num_xfrs_grped;
+ struct spi_transfer *first_xfr;
+ struct spi_transfer *nxt_xfr;
+ void *tx_buf, *rx_buf;
+ u32 tx_len, rx_len;
+
+ dev = &dd->cur_msg->spi->dev;
+ first_xfr = dd->cur_transfer;
/* mapped by client */
if (dd->cur_msg->is_dma_mapped)
return;
- dev = &dd->cur_msg->spi->dev;
- if (dd->cur_transfer->rx_buf)
- dma_unmap_single(dev, dd->cur_transfer->rx_dma,
- dd->cur_transfer->len,
- DMA_FROM_DEVICE);
+ do {
+ tx_buf = (void *)first_xfr->tx_buf;
+ rx_buf = first_xfr->rx_buf;
+ tx_len = rx_len = first_xfr->len;
+ if (tx_buf != NULL)
+ dma_unmap_single(dev, first_xfr->tx_dma,
+ tx_len, DMA_TO_DEVICE);
- if (dd->cur_transfer->tx_buf)
- dma_unmap_single(dev, dd->cur_transfer->tx_dma,
- dd->cur_transfer->len,
- DMA_TO_DEVICE);
+ if (rx_buf != NULL)
+ dma_unmap_single(dev, first_xfr->rx_dma,
+ rx_len, DMA_FROM_DEVICE);
+
+ nxt_xfr = list_entry(first_xfr->transfer_list.next,
+ struct spi_transfer, transfer_list);
+
+ if (nxt_xfr == NULL)
+ break;
+ num_xfrs_grped--;
+ first_xfr = nxt_xfr;
+ } while (num_xfrs_grped > 0);
}
static inline void msm_spi_dma_unmap_buffers(struct msm_spi *dd)
@@ -1506,7 +1705,8 @@
if (dd->cur_msg_len < 3*dd->input_block_size)
return false;
- if (dd->multi_xfr && !dd->read_len && !dd->write_len)
+ if ((dd->qup_ver != SPI_QUP_VERSION_BFAM) &&
+ dd->multi_xfr && !dd->read_len && !dd->write_len)
return false;
if (dd->qup_ver == SPI_QUP_VERSION_NONE) {
@@ -1688,11 +1888,17 @@
msm_spi_set_transfer_mode(dd, bpw, read_count);
msm_spi_set_mx_counts(dd, read_count);
- if ((dd->mode == SPI_BAM_MODE) || (dd->mode == SPI_DMOV_MODE))
+ if (dd->mode == SPI_DMOV_MODE) {
if (msm_spi_dma_map_buffers(dd) < 0) {
pr_err("Mapping DMA buffers\n");
return;
+ }
+ } else if (dd->mode == SPI_BAM_MODE) {
+ if (msm_spi_dma_map_buffers(dd) < 0) {
+ pr_err("Mapping DMA buffers\n");
+ return;
}
+ }
msm_spi_set_qup_io_modes(dd);
msm_spi_set_spi_config(dd, bpw);
msm_spi_set_qup_config(dd, bpw);
@@ -1712,7 +1918,7 @@
goto transfer_end;
msm_spi_start_write(dd, read_count);
} else if (dd->mode == SPI_BAM_MODE) {
- if ((msm_spi_bam_begin_transfer(dd, timeout, bpw)) < 0)
+ if ((msm_spi_bam_begin_transfer(dd)) < 0)
dev_err(dd->dev, "%s: BAM transfer setup failed\n",
__func__);
}
@@ -1749,9 +1955,10 @@
msm_spi_bam_flush(dd);
break;
}
- } while (msm_spi_dm_send_next(dd));
+ } while (msm_spi_dma_send_next(dd));
- msm_spi_udelay(dd->cur_transfer->delay_usecs);
+ msm_spi_udelay(dd->xfrs_delay_usec);
+
transfer_end:
msm_spi_dma_unmap_buffers(dd);
dd->mode = SPI_MODE_NONE;
@@ -1803,26 +2010,6 @@
dd->multi_xfr = 1;
}
-static inline int combine_transfers(struct msm_spi *dd)
-{
- struct spi_transfer *t = dd->cur_transfer;
- struct spi_transfer *nxt;
- int xfrs_grped = 1;
-
- dd->cur_msg_len = dd->cur_transfer->len;
- while (t->transfer_list.next != &dd->cur_msg->transfers) {
- nxt = list_entry(t->transfer_list.next,
- struct spi_transfer,
- transfer_list);
- if (t->cs_change != nxt->cs_change)
- return xfrs_grped;
- dd->cur_msg_len += nxt->len;
- xfrs_grped++;
- t = nxt;
- }
- return xfrs_grped;
-}
-
static inline void write_force_cs(struct msm_spi *dd, bool set_flag)
{
u32 spi_ioc;
@@ -1839,122 +2026,124 @@
writel_relaxed(spi_ioc, dd->base + SPI_IO_CONTROL);
}
+static inline int combine_transfers(struct msm_spi *dd)
+{
+ struct spi_transfer *t = dd->cur_transfer;
+ struct spi_transfer *nxt;
+ int xfrs_grped = 1;
+ dd->xfrs_delay_usec = 0;
+
+ dd->bam.bam_rx_len = dd->bam.bam_tx_len = 0;
+
+ dd->cur_msg_len = dd->cur_transfer->len;
+
+ if (dd->cur_transfer->tx_buf)
+ dd->bam.bam_tx_len += dd->cur_transfer->len;
+ if (dd->cur_transfer->rx_buf)
+ dd->bam.bam_rx_len += dd->cur_transfer->len;
+
+ while (t->transfer_list.next != &dd->cur_msg->transfers) {
+ nxt = list_entry(t->transfer_list.next,
+ struct spi_transfer,
+ transfer_list);
+ if (t->cs_change != nxt->cs_change)
+ return xfrs_grped;
+ if (t->delay_usecs) {
+ dd->xfrs_delay_usec = t->delay_usecs;
+ dev_info(dd->dev, "SPI slave requests delay per txn :%d usecs",
+ t->delay_usecs);
+ return xfrs_grped;
+ }
+ if (nxt->tx_buf)
+ dd->bam.bam_tx_len += nxt->len;
+ if (nxt->rx_buf)
+ dd->bam.bam_rx_len += nxt->len;
+
+ dd->cur_msg_len += nxt->len;
+ xfrs_grped++;
+ t = nxt;
+ }
+
+ if (1 == xfrs_grped)
+ dd->xfrs_delay_usec = dd->cur_transfer->delay_usecs;
+
+ return xfrs_grped;
+}
+
static void msm_spi_process_message(struct msm_spi *dd)
{
int xfrs_grped = 0;
- int cs_num;
int rc;
- bool xfer_delay = false;
- struct spi_transfer *tr;
+ dd->num_xfrs_grped = 0;
+ dd->bam.curr_rx_bytes_recvd = dd->bam.curr_tx_bytes_sent = 0;
dd->write_xfr_cnt = dd->read_xfr_cnt = 0;
- cs_num = dd->cur_msg->spi->chip_select;
- if ((!(dd->cur_msg->spi->mode & SPI_LOOP)) &&
- (!(dd->cs_gpios[cs_num].valid)) &&
- (dd->cs_gpios[cs_num].gpio_num >= 0)) {
- rc = gpio_request(dd->cs_gpios[cs_num].gpio_num,
- spi_cs_rsrcs[cs_num]);
- if (rc) {
- dev_err(dd->dev, "gpio_request for pin %d failed with "
- "error %d\n", dd->cs_gpios[cs_num].gpio_num,
- rc);
- return;
- }
- dd->cs_gpios[cs_num].valid = 1;
- }
+ rc = msm_spi_request_cs_gpio(dd);
+ if (rc)
+ return;
- list_for_each_entry(tr,
- &dd->cur_msg->transfers,
- transfer_list) {
- if (tr->delay_usecs) {
- dev_info(dd->dev, "SPI slave requests delay per txn :%d",
- tr->delay_usecs);
- xfer_delay = true;
- break;
- }
- }
-
- /* Don't combine xfers if delay is needed after every xfer */
- if (dd->qup_ver || xfer_delay) {
- if (dd->qup_ver)
- write_force_cs(dd, 0);
- list_for_each_entry(dd->cur_transfer,
- &dd->cur_msg->transfers,
- transfer_list) {
- struct spi_transfer *t = dd->cur_transfer;
- struct spi_transfer *nxt;
-
- if (t->transfer_list.next != &dd->cur_msg->transfers) {
- nxt = list_entry(t->transfer_list.next,
+ dd->cur_transfer = list_first_entry(&dd->cur_msg->transfers,
struct spi_transfer,
transfer_list);
- if (dd->qup_ver &&
- t->cs_change == nxt->cs_change)
- write_force_cs(dd, 1);
- else if (dd->qup_ver)
- write_force_cs(dd, 0);
- }
+ get_transfer_length(dd);
+ if (dd->qup_ver || (dd->multi_xfr && !dd->read_len && !dd->write_len)) {
- dd->cur_msg_len = dd->cur_transfer->len;
- msm_spi_process_transfer(dd);
- }
- } else {
- dd->cur_transfer = list_first_entry(&dd->cur_msg->transfers,
- struct spi_transfer,
- transfer_list);
- get_transfer_length(dd);
- if (dd->multi_xfr && !dd->read_len && !dd->write_len) {
- /*
- * Handling of multi-transfers.
- * FIFO mode is used by default
- */
- list_for_each_entry(dd->cur_transfer,
- &dd->cur_msg->transfers,
- transfer_list) {
- if (!dd->cur_transfer->len)
- goto error;
- if (xfrs_grped) {
- xfrs_grped--;
- continue;
- } else {
- dd->read_len = dd->write_len = 0;
- xfrs_grped = combine_transfers(dd);
- }
+ if (dd->qup_ver)
+ write_force_cs(dd, 0);
- dd->cur_tx_transfer = dd->cur_transfer;
- dd->cur_rx_transfer = dd->cur_transfer;
- msm_spi_process_transfer(dd);
+ /*
+ * Handling of multi-transfers.
+ * FIFO mode is used by default
+ */
+ list_for_each_entry(dd->cur_transfer,
+ &dd->cur_msg->transfers,
+ transfer_list) {
+ if (!dd->cur_transfer->len)
+ goto error;
+ if (xfrs_grped) {
xfrs_grped--;
- }
- } else {
- /* Handling of a single transfer or
- * WR-WR or WR-RD transfers
- */
- if ((!dd->cur_msg->is_dma_mapped) &&
- (msm_spi_use_dma(dd, dd->cur_transfer,
- dd->cur_transfer->bits_per_word))) {
- /* Mapping of DMA buffers */
- int ret = msm_spi_dma_map_buffers(dd);
- if (ret < 0) {
- dd->cur_msg->status = ret;
- goto error;
- }
+ continue;
+ } else {
+ dd->read_len = dd->write_len = 0;
+ xfrs_grped = combine_transfers(dd);
+ dd->num_xfrs_grped = xfrs_grped;
+ if (dd->qup_ver)
+ write_force_cs(dd, 1);
}
dd->cur_tx_transfer = dd->cur_transfer;
dd->cur_rx_transfer = dd->cur_transfer;
msm_spi_process_transfer(dd);
+ if (dd->qup_ver && !dd->xfrs_delay_usec)
+ write_force_cs(dd, 0);
+ xfrs_grped--;
}
+ } else {
+ /* Handling of a single transfer or
+ * WR-WR or WR-RD transfers
+ */
+ if ((!dd->cur_msg->is_dma_mapped) &&
+ (msm_spi_use_dma(dd, dd->cur_transfer,
+ dd->cur_transfer->bits_per_word))) {
+ /* Mapping of DMA buffers */
+ int ret = msm_spi_dma_map_buffers(dd);
+ if (ret < 0) {
+ dd->cur_msg->status = ret;
+ goto error;
+ }
+ }
+
+ dd->cur_tx_transfer = dd->cur_transfer;
+ dd->cur_rx_transfer = dd->cur_transfer;
+ dd->num_xfrs_grped = 1;
+ msm_spi_process_transfer(dd);
}
return;
error:
- if (dd->cs_gpios[cs_num].valid) {
- gpio_free(dd->cs_gpios[cs_num].gpio_num);
- dd->cs_gpios[cs_num].valid = 0;
- }
+ msm_spi_free_cs_gpio(dd);
}
/**
diff --git a/drivers/spi/spi_qsd.h b/drivers/spi/spi_qsd.h
index d538076..a0c399b 100644
--- a/drivers/spi/spi_qsd.h
+++ b/drivers/spi/spi_qsd.h
@@ -291,6 +291,10 @@
struct msm_spi_bam_pipe prod;
struct msm_spi_bam_pipe cons;
bool deregister_required;
+ u32 curr_rx_bytes_recvd;
+ u32 curr_tx_bytes_sent;
+ u32 bam_rx_len;
+ u32 bam_tx_len;
};
struct msm_spi {
@@ -388,6 +392,8 @@
struct spi_cs_gpio cs_gpios[ARRAY_SIZE(spi_cs_rsrcs)];
enum msm_spi_qup_version qup_ver;
int max_trfr_len;
+ int num_xfrs_grped;
+ u16 xfrs_delay_usec;
};
/* Forward declaration */
diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c
index b4a56ec..7b623e4 100644
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -970,7 +970,9 @@
return -EINVAL;
while (!kthread_should_stop()) {
- wait_for_completion(&hotplug_notify_complete);
+ while (wait_for_completion_interruptible(
+ &hotplug_notify_complete) != 0)
+ ;
INIT_COMPLETION(hotplug_notify_complete);
mask = 0;
@@ -1404,7 +1406,9 @@
uint32_t cpu = 0, max_freq_req = 0, min_freq_req = 0;
while (!kthread_should_stop()) {
- wait_for_completion(&freq_mitigation_complete);
+ while (wait_for_completion_interruptible(
+ &freq_mitigation_complete) != 0)
+ ;
INIT_COMPLETION(freq_mitigation_complete);
get_online_cpus();
@@ -1641,7 +1645,9 @@
struct therm_threshold *sensor_list;
while (!kthread_should_stop()) {
- wait_for_completion(&thermal_monitor_complete);
+ while (wait_for_completion_interruptible(
+ &thermal_monitor_complete) != 0)
+ ;
INIT_COMPLETION(thermal_monitor_complete);
for (i = 0; i < MSM_LIST_MAX_NR; i++) {
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 6a92684..30a678b 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -841,9 +841,6 @@
/* ESS flushes only at end?!? */
hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
- /* clear setup token semaphores */
- hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
-
/* clear complete status */
hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 486d99d..ea724d6 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -2438,6 +2438,11 @@
* Notify the charger type to power supply
* owner as soon as we determine the charger.
*/
+ if (motg->chg_type == USB_DCP_CHARGER &&
+ motg->ext_chg_opened) {
+ init_completion(&motg->ext_chg_wait);
+ motg->ext_chg_active = DEFAULT;
+ }
msm_otg_notify_chg_type(motg);
msm_chg_block_off(motg);
msm_chg_enable_aca_det(motg);
@@ -2541,14 +2546,17 @@
* detection is completed.
*/
- if (motg->ext_chg_active) {
+ if (motg->ext_chg_active == ACTIVE) {
+do_wait:
pr_debug("before msm_otg ext chg wait\n");
t = wait_for_completion_timeout(&motg->ext_chg_wait,
msecs_to_jiffies(3000));
if (!t)
pr_err("msm_otg ext chg wait timeout\n");
+ else if (motg->ext_chg_active == ACTIVE)
+ goto do_wait;
else
pr_debug("msm_otg ext chg wait done\n");
}
@@ -2624,11 +2632,6 @@
case USB_DCP_CHARGER:
/* Enable VDP_SRC */
ulpi_write(otg->phy, 0x2, 0x85);
- if (motg->ext_chg_opened) {
- init_completion(
- &motg->ext_chg_wait);
- motg->ext_chg_active = true;
- }
/* fall through */
case USB_PROPRIETARY_CHARGER:
msm_otg_notify_charger(motg,
@@ -2698,6 +2701,8 @@
motg->chg_type = USB_INVALID_CHARGER;
msm_otg_notify_charger(motg, 0);
if (dcp) {
+ if (motg->ext_chg_active == DEFAULT)
+ motg->ext_chg_active = INACTIVE;
msm_otg_wait_for_ext_chg_done(motg);
/* Turn off VDP_SRC */
ulpi_write(otg->phy, 0x2, 0x86);
@@ -4051,6 +4056,7 @@
pr_debug("%s: LPM block request %d\n", __func__, val);
if (val) { /* block LPM */
if (motg->chg_type == USB_DCP_CHARGER) {
+ motg->ext_chg_active = ACTIVE;
/*
* If device is already suspended, resume it.
* The PM usage counter is incremented in
@@ -4063,14 +4069,23 @@
else
pm_runtime_get_sync(motg->phy.dev);
} else {
- motg->ext_chg_active = false;
+ motg->ext_chg_active = INACTIVE;
complete(&motg->ext_chg_wait);
ret = -ENODEV;
}
} else {
- motg->ext_chg_active = false;
+ motg->ext_chg_active = INACTIVE;
complete(&motg->ext_chg_wait);
- pm_runtime_put(motg->phy.dev);
+ /*
+ * If usb cable is disconnected and then userspace
+ * calls ioctl to unblock low power mode, make sure
+ * otg_sm work for usb disconnect is processed first
+ * followed by decrementing the PM usage counters.
+ */
+ flush_work(&motg->sm_work);
+ pm_runtime_put_noidle(motg->phy.dev);
+ motg->pm_done = 1;
+ pm_runtime_suspend(motg->phy.dev);
}
break;
case MSM_USB_EXT_CHG_VOLTAGE_INFO:
@@ -4897,7 +4912,7 @@
if (phy->state == OTG_STATE_UNDEFINED)
return -EAGAIN;
- if (motg->ext_chg_active) {
+ if (motg->ext_chg_active == DEFAULT) {
dev_dbg(dev, "Deferring LPM\n");
/*
* Charger detection may happen in user space.
diff --git a/drivers/video/msm/mdss/Makefile b/drivers/video/msm/mdss/Makefile
index ddea735..ae13322 100644
--- a/drivers/video/msm/mdss/Makefile
+++ b/drivers/video/msm/mdss/Makefile
@@ -9,6 +9,7 @@
mdss-mdp-objs += mdss_mdp_intf_writeback.o
mdss-mdp-objs += mdss_mdp_rotator.o
mdss-mdp-objs += mdss_mdp_overlay.o
+mdss-mdp-objs += mdss_mdp_splash_logo.o
mdss-mdp-objs += mdss_mdp_wb.o
obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o
diff --git a/drivers/video/msm/mdss/dsi_status_6g.c b/drivers/video/msm/mdss/dsi_status_6g.c
index 31c9022..4f7e4da 100644
--- a/drivers/video/msm/mdss/dsi_status_6g.c
+++ b/drivers/video/msm/mdss/dsi_status_6g.c
@@ -38,6 +38,10 @@
pstatus_data = container_of(to_delayed_work(work),
struct dsi_status_data, check_status);
+ if (!pstatus_data || !(pstatus_data->mfd)) {
+ pr_err("%s: mfd not available\n", __func__);
+ return;
+ }
pdata = dev_get_platdata(&pstatus_data->mfd->pdev->dev);
if (!pdata) {
@@ -56,6 +60,11 @@
mdp5_data = mfd_to_mdp5_data(pstatus_data->mfd);
ctl = mfd_to_ctl(pstatus_data->mfd);
+ if (!ctl) {
+ pr_err("%s: Display is off\n", __func__);
+ return;
+ }
+
if (ctl->shared_lock)
mutex_lock(ctl->shared_lock);
mutex_lock(&mdp5_data->ov_lock);
diff --git a/drivers/video/msm/mdss/dsi_status_v2.c b/drivers/video/msm/mdss/dsi_status_v2.c
index c8915e6..f0966cc 100644
--- a/drivers/video/msm/mdss/dsi_status_v2.c
+++ b/drivers/video/msm/mdss/dsi_status_v2.c
@@ -40,6 +40,11 @@
pdsi_status = container_of(to_delayed_work(work),
struct dsi_status_data, check_status);
+ if (!pdsi_status || !(pdsi_status->mfd)) {
+ pr_err("%s: mfd not available\n", __func__);
+ return;
+ }
+
pdata = dev_get_platdata(&pdsi_status->mfd->pdev->dev);
if (!pdata) {
pr_err("%s: Panel data not available\n", __func__);
@@ -56,6 +61,11 @@
}
mdp3_session = pdsi_status->mfd->mdp.private1;
+ if (!mdp3_session) {
+ pr_err("%s: Display is off\n", __func__);
+ return;
+ }
+
mutex_lock(&mdp3_session->lock);
if (!mdp3_session->status) {
pr_info("display off already\n");
diff --git a/drivers/video/msm/mdss/mdp3.c b/drivers/video/msm/mdss/mdp3.c
index 8e2ae4d..37134b4 100644
--- a/drivers/video/msm/mdss/mdp3.c
+++ b/drivers/video/msm/mdss/mdp3.c
@@ -738,9 +738,11 @@
if (context >= MDP3_IOMMU_CTX_MAX)
return -EINVAL;
+ mutex_lock(&mdp3_res->iommu_lock);
context_map = mdp3_res->iommu_contexts + context;
if (context_map->attached) {
pr_warn("mdp iommu already attached\n");
+ mutex_unlock(&mdp3_res->iommu_lock);
return 0;
}
@@ -749,6 +751,7 @@
iommu_attach_device(domain_map->domain, context_map->ctx);
context_map->attached = true;
+ mutex_unlock(&mdp3_res->iommu_lock);
return 0;
}
@@ -761,9 +764,11 @@
context >= MDP3_IOMMU_CTX_MAX)
return -EINVAL;
+ mutex_lock(&mdp3_res->iommu_lock);
context_map = mdp3_res->iommu_contexts + context;
if (!context_map->attached) {
pr_warn("mdp iommu not attached\n");
+ mutex_unlock(&mdp3_res->iommu_lock);
return 0;
}
@@ -771,6 +776,7 @@
iommu_detach_device(domain_map->domain, context_map->ctx);
context_map->attached = false;
+ mutex_unlock(&mdp3_res->iommu_lock);
return 0;
}
diff --git a/drivers/video/msm/mdss/mdp3_ctrl.c b/drivers/video/msm/mdss/mdp3_ctrl.c
index 9cbff71..8acb9b0 100644
--- a/drivers/video/msm/mdss/mdp3_ctrl.c
+++ b/drivers/video/msm/mdss/mdp3_ctrl.c
@@ -27,10 +27,7 @@
#define VSYNC_EXPIRE_TICK 4
-static void mdp3_ctrl_pan_display(struct msm_fb_data_type *mfd,
- struct mdp_overlay *req,
- int image_size,
- int *pipe_ndx);
+static void mdp3_ctrl_pan_display(struct msm_fb_data_type *mfd);
static int mdp3_overlay_unset(struct msm_fb_data_type *mfd, int ndx);
static int mdp3_histogram_stop(struct mdp3_session_data *session,
u32 block);
@@ -1071,10 +1068,7 @@
return 0;
}
-static void mdp3_ctrl_pan_display(struct msm_fb_data_type *mfd,
- struct mdp_overlay *req,
- int image_size,
- int *pipe_ndx)
+static void mdp3_ctrl_pan_display(struct msm_fb_data_type *mfd)
{
struct fb_info *fbi;
struct mdp3_session_data *mdp3_session;
diff --git a/drivers/video/msm/mdss/mdp3_ppp.h b/drivers/video/msm/mdss/mdp3_ppp.h
index 9753e94..a0ad3c3 100644
--- a/drivers/video/msm/mdss/mdp3_ppp.h
+++ b/drivers/video/msm/mdss/mdp3_ppp.h
@@ -391,7 +391,7 @@
uint32_t ppp_bpp(uint32_t type);
uint32_t ppp_src_config(uint32_t type);
uint32_t ppp_out_config(uint32_t type);
-uint32_t ppp_pack_pattern(uint32_t type);
+uint32_t ppp_pack_pattern(uint32_t type, uint32_t yuv2rgb);
uint32_t ppp_dst_op_reg(uint32_t type);
uint32_t ppp_src_op_reg(uint32_t type);
bool ppp_per_p_alpha(uint32_t type);
diff --git a/drivers/video/msm/mdss/mdp3_ppp_data.c b/drivers/video/msm/mdss/mdp3_ppp_data.c
index e562ad3..5748842 100644
--- a/drivers/video/msm/mdss/mdp3_ppp_data.c
+++ b/drivers/video/msm/mdss/mdp3_ppp_data.c
@@ -88,6 +88,35 @@
CLR_G, CLR_R, 8),
};
+const uint32_t swapped_pack_patt_lut[MDP_IMGTYPE_LIMIT] = {
+ [MDP_RGB_565] = PPP_GET_PACK_PATTERN(0, CLR_B, CLR_G, CLR_R, 8),
+ [MDP_BGR_565] = PPP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8),
+ [MDP_RGB_888] = PPP_GET_PACK_PATTERN(0, CLR_B, CLR_G, CLR_R, 8),
+ [MDP_BGR_888] = PPP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8),
+ [MDP_BGRA_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R,
+ CLR_G, CLR_B, 8),
+ [MDP_RGBA_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B,
+ CLR_G, CLR_R, 8),
+ [MDP_ARGB_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B,
+ CLR_G, CLR_R, 8),
+ [MDP_XRGB_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B,
+ CLR_G, CLR_R, 8),
+ [MDP_RGBX_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B,
+ CLR_G, CLR_R, 8),
+ [MDP_Y_CRCB_H2V2] = PPP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8),
+ [MDP_Y_CBCR_H2V2] = PPP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8),
+ [MDP_Y_CBCR_H2V2_ADRENO] = PPP_GET_PACK_PATTERN(0, 0, CLR_CR,
+ CLR_CB, 8),
+ [MDP_Y_CBCR_H2V2_VENUS] = PPP_GET_PACK_PATTERN(0, 0, CLR_CR,
+ CLR_CB, 8),
+ [MDP_YCRYCB_H2V1] = PPP_GET_PACK_PATTERN(CLR_Y,
+ CLR_CB, CLR_Y, CLR_CR, 8),
+ [MDP_Y_CBCR_H2V1] = PPP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8),
+ [MDP_Y_CRCB_H2V1] = PPP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8),
+ [MDP_BGRX_8888] = PPP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R,
+ CLR_G, CLR_B, 8),
+};
+
const uint32_t dst_op_reg[MDP_IMGTYPE_LIMIT] = {
[MDP_Y_CRCB_H2V2] = PPP_OP_DST_CHROMA_420,
[MDP_Y_CBCR_H2V2] = PPP_OP_DST_CHROMA_420,
@@ -1530,10 +1559,13 @@
return out_cfg_lut[type];
}
-uint32_t ppp_pack_pattern(uint32_t type)
+uint32_t ppp_pack_pattern(uint32_t type, uint32_t yuv2rgb)
{
if (MDP_IS_IMGTYPE_BAD(type))
return 0;
+ if (yuv2rgb)
+ return swapped_pack_patt_lut[type];
+
return pack_patt_lut[type];
}
diff --git a/drivers/video/msm/mdss/mdp3_ppp_hwio.c b/drivers/video/msm/mdss/mdp3_ppp_hwio.c
index eb01d00..a25c2c7 100644
--- a/drivers/video/msm/mdss/mdp3_ppp_hwio.c
+++ b/drivers/video/msm/mdss/mdp3_ppp_hwio.c
@@ -486,7 +486,7 @@
return load_secondary_matrix(csc);
}
-int config_ppp_src(struct ppp_img_desc *src)
+int config_ppp_src(struct ppp_img_desc *src, uint32_t yuv2rgb)
{
uint32_t val;
@@ -510,12 +510,12 @@
val |= (src->roi.x % 2) ? PPP_SRC_BPP_ROI_ODD_X : 0;
val |= (src->roi.y % 2) ? PPP_SRC_BPP_ROI_ODD_Y : 0;
PPP_WRITEL(val, MDP3_PPP_SRC_FORMAT);
- PPP_WRITEL(ppp_pack_pattern(src->color_fmt),
+ PPP_WRITEL(ppp_pack_pattern(src->color_fmt, yuv2rgb),
MDP3_PPP_SRC_UNPACK_PATTERN1);
return 0;
}
-int config_ppp_out(struct ppp_img_desc *dst)
+int config_ppp_out(struct ppp_img_desc *dst, uint32_t yuv2rgb)
{
uint32_t val;
bool pseudoplanr_output = false;
@@ -534,7 +534,7 @@
if (pseudoplanr_output)
val |= PPP_DST_PLANE_PSEUDOPLN;
PPP_WRITEL(val, MDP3_PPP_OUT_FORMAT);
- PPP_WRITEL(ppp_pack_pattern(dst->color_fmt),
+ PPP_WRITEL(ppp_pack_pattern(dst->color_fmt, yuv2rgb),
MDP3_PPP_OUT_PACK_PATTERN1);
val = ((dst->roi.height & MDP3_PPP_XY_MASK) << MDP3_PPP_XY_OFFSET) |
@@ -573,7 +573,7 @@
PPP_WRITEL(ppp_src_config(bg->color_fmt),
MDP3_PPP_BG_FORMAT);
- PPP_WRITEL(ppp_pack_pattern(bg->color_fmt),
+ PPP_WRITEL(ppp_pack_pattern(bg->color_fmt, 0),
MDP3_PPP_BG_UNPACK_PATTERN1);
return 0;
}
@@ -1108,6 +1108,7 @@
int config_ppp_op_mode(struct ppp_blit_op *blit_op)
{
+ uint32_t yuv2rgb;
uint32_t ppp_operation_reg = 0;
int sv_slice, sh_slice;
int dv_slice, dh_slice;
@@ -1153,6 +1154,7 @@
config_ppp_csc(blit_op->src.color_fmt,
blit_op->dst.color_fmt, &ppp_operation_reg);
+ yuv2rgb = ppp_operation_reg & PPP_OP_CONVERT_YCBCR2RGB;
if (blit_op->mdp_op & MDPOP_DITHER)
ppp_operation_reg |= PPP_OP_DITHER_EN;
@@ -1197,8 +1199,8 @@
config_ppp_blend(blit_op, &ppp_operation_reg);
- config_ppp_src(&blit_op->src);
- config_ppp_out(&blit_op->dst);
+ config_ppp_src(&blit_op->src, yuv2rgb);
+ config_ppp_out(&blit_op->dst, yuv2rgb);
PPP_WRITEL(ppp_operation_reg, MDP3_PPP_OP_MODE);
mb();
return 0;
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index dd8eec5..40a458c 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -1518,6 +1518,8 @@
if (!gpio_is_valid(ctrl_pdata->mode_gpio))
pr_info("%s:%d, mode gpio not specified\n",
__func__, __LINE__);
+ } else {
+ ctrl_pdata->mode_gpio = -EINVAL;
}
if (mdss_dsi_clk_init(ctrl_pdev, ctrl_pdata)) {
diff --git a/drivers/video/msm/mdss/mdss_dsi_status.c b/drivers/video/msm/mdss/mdss_dsi_status.c
index 116b778..c68155a 100644
--- a/drivers/video/msm/mdss/mdss_dsi_status.c
+++ b/drivers/video/msm/mdss/mdss_dsi_status.c
@@ -106,8 +106,14 @@
msecs_to_jiffies(interval));
break;
case FB_BLANK_POWERDOWN:
+ case FB_BLANK_HSYNC_SUSPEND:
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_NORMAL:
cancel_delayed_work(&pdata->check_status);
break;
+ default:
+ pr_err("Unknown case in FB_EVENT_BLANK event\n");
+ break;
}
}
return 0;
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 1927fe2..c14f936 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -52,6 +52,7 @@
#include <mach/msm_memtypes.h>
#include "mdss_fb.h"
+#include "mdss_mdp_splash_logo.h"
#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
#define MDSS_FB_NUM 3
@@ -191,47 +192,6 @@
return ret;
}
-static int mdss_fb_splash_thread(void *data)
-{
- struct msm_fb_data_type *mfd = data;
- int ret = -EINVAL;
- struct fb_info *fbi = NULL;
- int ov_index[2];
-
- if (!mfd || !mfd->fbi || !mfd->mdp.splash_fnc) {
- pr_err("Invalid input parameter\n");
- goto end;
- }
-
- fbi = mfd->fbi;
-
- ret = mdss_fb_open(fbi, current->tgid);
- if (ret) {
- pr_err("fb_open failed\n");
- goto end;
- }
-
- mfd->bl_updated = true;
- mdss_fb_set_backlight(mfd, mfd->panel_info->bl_max >> 1);
-
- ret = mfd->mdp.splash_fnc(mfd, ov_index, MDP_CREATE_SPLASH_OV);
- if (ret) {
- pr_err("Splash image failed\n");
- goto splash_err;
- }
-
- do {
- schedule_timeout_interruptible(SPLASH_THREAD_WAIT_TIMEOUT * HZ);
- } while (!kthread_should_stop());
-
- mfd->mdp.splash_fnc(mfd, ov_index, MDP_REMOVE_SPLASH_OV);
-
-splash_err:
- mdss_fb_release(fbi, current->tgid);
-end:
- return ret;
-}
-
static int lcd_backlight_registered;
static void mdss_fb_set_bl_brightness(struct led_classdev *led_cdev,
@@ -307,25 +267,30 @@
static void mdss_fb_parse_dt(struct msm_fb_data_type *mfd)
{
- u32 data[2];
+ u32 data[2] = {0};
+ u32 panel_xres;
struct platform_device *pdev = mfd->pdev;
- mfd->splash_logo_enabled = of_property_read_bool(pdev->dev.of_node,
- "qcom,mdss-fb-splash-logo-enabled");
+ of_property_read_u32_array(pdev->dev.of_node,
+ "qcom,mdss-fb-split", data, 2);
- if (of_property_read_u32_array(pdev->dev.of_node, "qcom,mdss-fb-split",
- data, 2))
- return;
- if (data[0] && data[1] &&
- (mfd->panel_info->xres == (data[0] + data[1]))) {
- mfd->split_fb_left = data[0];
- mfd->split_fb_right = data[1];
- pr_info("split framebuffer left=%d right=%d\n",
- mfd->split_fb_left, mfd->split_fb_right);
+ panel_xres = mfd->panel_info->xres;
+ if (data[0] && data[1]) {
+ if (mfd->split_display)
+ panel_xres *= 2;
+
+ if (panel_xres == data[0] + data[1]) {
+ mfd->split_fb_left = data[0];
+ mfd->split_fb_right = data[1];
+ }
} else {
- mfd->split_fb_left = 0;
- mfd->split_fb_right = 0;
+ if (mfd->split_display)
+ mfd->split_fb_left = mfd->split_fb_right = panel_xres;
+ else
+ mfd->split_fb_left = mfd->split_fb_right = 0;
}
+ pr_info("split framebuffer left=%d right=%d\n",
+ mfd->split_fb_left, mfd->split_fb_right);
}
static ssize_t mdss_fb_get_split(struct device *dev,
@@ -567,15 +532,8 @@
break;
}
- if (mfd->splash_logo_enabled) {
- mfd->splash_thread = kthread_run(mdss_fb_splash_thread, mfd,
- "mdss_fb_splash");
- if (IS_ERR(mfd->splash_thread)) {
- pr_err("unable to start splash thread %d\n",
- mfd->index);
- mfd->splash_thread = NULL;
- }
- }
+ if (mfd->mdp.splash_init_fnc)
+ mfd->mdp.splash_init_fnc(mfd);
INIT_DELAYED_WORK(&mfd->idle_notify_work, __mdss_fb_idle_notify_work);
@@ -857,17 +815,17 @@
{
struct mdss_panel_data *pdata;
+ mutex_lock(&mfd->bl_lock);
if (mfd->unset_bl_level && !mfd->bl_updated) {
pdata = dev_get_platdata(&mfd->pdev->dev);
if ((pdata) && (pdata->set_backlight)) {
- mutex_lock(&mfd->bl_lock);
mfd->bl_level = mfd->unset_bl_level;
pdata->set_backlight(pdata, mfd->bl_level);
mfd->bl_level_old = mfd->unset_bl_level;
- mutex_unlock(&mfd->bl_lock);
mfd->bl_updated = 1;
}
}
+ mutex_unlock(&mfd->bl_lock);
}
static int mdss_fb_blank_sub(int blank_mode, struct fb_info *info,
@@ -922,7 +880,9 @@
mfd->op_enable = false;
curr_pwr_state = mfd->panel_power_on;
mfd->panel_power_on = false;
+ mutex_lock(&mfd->bl_lock);
mfd->bl_updated = 0;
+ mutex_unlock(&mfd->bl_lock);
ret = mfd->mdp.off_fnc(mfd);
if (ret)
@@ -1383,12 +1343,6 @@
pinfo->ref_cnt++;
mfd->ref_cnt++;
- /* Stop the splash thread once userspace open the fb node */
- if (mfd->splash_thread && mfd->ref_cnt > 1) {
- kthread_stop(mfd->splash_thread);
- mfd->splash_thread = NULL;
- }
-
return 0;
blank_error:
@@ -1803,7 +1757,7 @@
(var->yoffset / info->fix.ypanstep) * info->fix.ypanstep;
if (mfd->mdp.dma_fnc)
- mfd->mdp.dma_fnc(mfd, NULL, 0, NULL);
+ mfd->mdp.dma_fnc(mfd);
else
pr_warn("dma function not set for panel type=%d\n",
mfd->panel.type);
diff --git a/drivers/video/msm/mdss/mdss_fb.h b/drivers/video/msm/mdss/mdss_fb.h
index 894dbbc..3416b9e 100644
--- a/drivers/video/msm/mdss/mdss_fb.h
+++ b/drivers/video/msm/mdss/mdss_fb.h
@@ -21,6 +21,7 @@
#include <linux/notifier.h>
#include "mdss_panel.h"
+#include "mdss_mdp_splash_logo.h"
#define MSM_FB_DEFAULT_PAGE_SIZE 2
#define MFD_KEY 0x11161126
@@ -33,8 +34,6 @@
#define WAIT_DISP_OP_TIMEOUT ((WAIT_FENCE_FIRST_TIMEOUT + \
WAIT_FENCE_FINAL_TIMEOUT) * MDP_MAX_FENCE_FD)
-#define SPLASH_THREAD_WAIT_TIMEOUT 3
-
#ifndef MAX
#define MAX(x, y) (((x) > (y)) ? (x) : (y))
#endif
@@ -69,11 +68,6 @@
MDP_NOTIFY_FRAME_TIMEOUT,
};
-enum mdp_splash_event {
- MDP_CREATE_SPLASH_OV = 0,
- MDP_REMOVE_SPLASH_OV,
-};
-
struct disp_info_type_suspend {
int op_enable;
int panel_power_on;
@@ -122,8 +116,7 @@
int (*kickoff_fnc)(struct msm_fb_data_type *mfd,
struct mdp_display_commit *data);
int (*ioctl_handler)(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
- void (*dma_fnc)(struct msm_fb_data_type *mfd, struct mdp_overlay *req,
- int image_len, int *pipe_ndx);
+ void (*dma_fnc)(struct msm_fb_data_type *mfd);
int (*cursor_update)(struct msm_fb_data_type *mfd,
struct fb_cursor *cursor);
int (*lut_update)(struct msm_fb_data_type *mfd, struct fb_cmap *cmap);
@@ -132,7 +125,7 @@
int (*update_ad_input)(struct msm_fb_data_type *mfd);
int (*panel_register_done)(struct mdss_panel_data *pdata);
u32 (*fb_stride)(u32 fb_index, u32 xres, int bpp);
- int (*splash_fnc) (struct msm_fb_data_type *mfd, int *index, int req);
+ int (*splash_init_fnc)(struct msm_fb_data_type *mfd);
struct msm_sync_pt_data *(*get_sync_fnc)(struct msm_fb_data_type *mfd,
const struct mdp_buf_sync *buf_sync);
void (*check_dsi_status)(struct work_struct *work, uint32_t interval);
@@ -221,8 +214,7 @@
wait_queue_head_t kickoff_wait_q;
bool shutdown_pending;
- struct task_struct *splash_thread;
- bool splash_logo_enabled;
+ struct msm_fb_splash_info splash_info;
wait_queue_head_t ioctl_q;
atomic_t ioctl_ref_cnt;
diff --git a/drivers/video/msm/mdss/mdss_mdp.c b/drivers/video/msm/mdss/mdss_mdp.c
index 97d4dc9..037a183 100644
--- a/drivers/video/msm/mdss/mdss_mdp.c
+++ b/drivers/video/msm/mdss/mdss_mdp.c
@@ -56,6 +56,9 @@
#include "mdss_panel.h"
#include "mdss_debug.h"
+#define CREATE_TRACE_POINTS
+#include "mdss_mdp_trace.h"
+
struct mdss_data_type *mdss_res;
static int mdss_fb_mem_get_iommu_domain(void)
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index ebdc2b8..33a0806 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -33,6 +33,7 @@
#define MDP_CLK_DEFAULT_RATE 200000000
#define PHASE_STEP_SHIFT 21
#define MAX_MIXER_WIDTH 2048
+#define MAX_LINE_BUFFER_WIDTH 2048
#define MAX_MIXER_HEIGHT 0xFFFF
#define MAX_IMG_WIDTH 0x3FFF
#define MAX_IMG_HEIGHT 0x3FFF
@@ -297,6 +298,7 @@
u32 hist_cnt_time;
u32 frame_cnt;
struct completion comp;
+ struct completion first_kick;
u32 data[HIST_V_SIZE];
struct mutex hist_mutex;
spinlock_t hist_lock;
@@ -505,6 +507,17 @@
return readl_relaxed(mixer->pingpong_base + reg);
}
+static inline int mdss_mdp_iommu_dyn_attach_supported(
+ struct mdss_data_type *mdata)
+{
+ return (mdata->mdp_rev >= MDSS_MDP_HW_REV_103);
+}
+
+static inline int mdss_mdp_line_buffer_width(void)
+{
+ return MAX_LINE_BUFFER_WIDTH;
+}
+
irqreturn_t mdss_mdp_isr(int irq, void *ptr);
int mdss_iommu_attach(struct mdss_data_type *mdata);
int mdss_iommu_dettach(struct mdss_data_type *mdata);
@@ -538,6 +551,12 @@
struct msmfb_data *planes,
int num_planes,
u32 flags);
+int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd,
+ struct mdp_overlay *req, struct mdss_mdp_pipe **ppipe);
+void mdss_mdp_handoff_cleanup_pipes(struct msm_fb_data_type *mfd,
+ u32 type);
+int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx);
+int mdss_mdp_overlay_start(struct msm_fb_data_type *mfd);
int mdss_mdp_video_addr_setup(struct mdss_data_type *mdata,
u32 *offsets, u32 count);
int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl);
@@ -670,7 +689,7 @@
int mdss_mdp_data_check(struct mdss_mdp_data *data,
struct mdss_mdp_plane_sizes *ps);
int mdss_mdp_get_plane_sizes(u32 format, u32 w, u32 h,
- struct mdss_mdp_plane_sizes *ps, u32 bwc_mode);
+ struct mdss_mdp_plane_sizes *ps, u32 bwc_mode, bool rotation);
int mdss_mdp_get_rau_strides(u32 w, u32 h, struct mdss_mdp_format_params *fmt,
struct mdss_mdp_plane_sizes *ps);
void mdss_mdp_data_calc_offset(struct mdss_mdp_data *data, u16 x, u16 y,
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index 65d28a0..3449308 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -23,6 +23,7 @@
#include "mdss_fb.h"
#include "mdss_mdp.h"
#include "mdss_debug.h"
+#include "mdss_mdp_trace.h"
static void mdss_mdp_xlog_mixer_reg(struct mdss_mdp_ctl *ctl);
static inline u64 fudge_factor(u64 val, u32 numer, u32 denom)
@@ -833,6 +834,7 @@
bus_ib_quota = bw_sum_of_intfs;
bus_ab_quota = apply_fudge_factor(bw_sum_of_intfs,
&mdss_res->ab_factor);
+ trace_mdp_perf_update_bus(bus_ab_quota, bus_ib_quota);
mdss_mdp_bus_scale_set_quota(bus_ab_quota, bus_ib_quota);
pr_debug("ab=%llu ib=%llu\n", bus_ab_quota, bus_ib_quota);
}
@@ -874,6 +876,7 @@
/*Release the bandwidth only if there are no transactions pending*/
if (!transaction_status) {
+ trace_mdp_cmd_release_bw(ctl->num);
ctl->cur_perf.bw_ctl = 0;
ctl->new_perf.bw_ctl = 0;
pr_debug("Release BW ctl=%d\n", ctl->num);
@@ -1966,6 +1969,7 @@
if (!mixer)
return -ENODEV;
+ trace_mdp_mixer_update(mixer->num);
pr_debug("setup mixer=%d\n", mixer->num);
outsize = (mixer->roi.h << 16) | mixer->roi.w;
@@ -2071,6 +2075,8 @@
mixercfg |= stage << (3 * pipe->num);
+ trace_mdp_sspp_change(pipe);
+
pr_debug("stg=%d op=%x fg_alpha=%x bg_alpha=%x\n", stage,
blend_op, fg_alpha, bg_alpha);
mdp_mixer_write(mixer, off + MDSS_MDP_REG_LM_OP_MODE, blend_op);
@@ -2486,6 +2492,8 @@
if (ctl->wait_fnc)
ret = ctl->wait_fnc(ctl, NULL);
+ trace_mdp_commit(ctl);
+
mdss_mdp_ctl_perf_update(ctl, 0);
mutex_unlock(&ctl->lock);
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
index e2a8d56..991eb06 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
@@ -16,6 +16,7 @@
#include "mdss_mdp.h"
#include "mdss_panel.h"
#include "mdss_debug.h"
+#include "mdss_mdp_trace.h"
#define VSYNC_EXPIRE_TICK 4
@@ -24,7 +25,7 @@
/* wait for at most 2 vsync for lowest refresh rate (24hz) */
#define KOFF_TIMEOUT msecs_to_jiffies(84)
-#define STOP_TIMEOUT msecs_to_jiffies(16 * (VSYNC_EXPIRE_TICK + 2))
+#define STOP_TIMEOUT(hz) msecs_to_jiffies((1000 / hz) * (VSYNC_EXPIRE_TICK + 2))
#define ULPS_ENTER_TIME msecs_to_jiffies(100)
struct mdss_mdp_cmd_ctx {
@@ -354,6 +355,7 @@
} else
pr_err("%s: should not have pingpong interrupt!\n", __func__);
+ trace_mdp_cmd_pingpong_done(ctl, ctx->pp_num, ctx->koff_cnt);
pr_debug("%s: ctl_num=%d intf_num=%d ctx=%d kcnt=%d\n", __func__,
ctl->num, ctl->intf_num, ctx->pp_num, ctx->koff_cnt);
@@ -531,6 +533,8 @@
rc = wait_for_completion_timeout(
&ctx->pp_comp, KOFF_TIMEOUT);
+ trace_mdp_cmd_wait_pingpong(ctl->num, ctx->koff_cnt);
+
if (rc <= 0) {
WARN(1, "cmd kickoff timed out (%d) ctl=%d\n",
rc, ctl->num);
@@ -596,6 +600,7 @@
spin_lock_irqsave(&ctx->clk_lock, flags);
ctx->koff_cnt++;
spin_unlock_irqrestore(&ctx->clk_lock, flags);
+ trace_mdp_cmd_kickoff(ctl->num, ctx->koff_cnt);
mdss_mdp_cmd_clk_on(ctx);
@@ -626,6 +631,7 @@
struct mdss_mdp_vsync_handler *tmp, *handle;
int need_wait = 0;
int ret = 0;
+ int hz;
ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
if (!ctx) {
@@ -645,8 +651,11 @@
}
spin_unlock_irqrestore(&ctx->clk_lock, flags);
+ hz = mdss_panel_get_framerate(&ctl->panel_data->panel_info);
+
if (need_wait)
- if (wait_for_completion_timeout(&ctx->stop_comp, STOP_TIMEOUT)
+ if (wait_for_completion_timeout(&ctx->stop_comp,
+ STOP_TIMEOUT(hz))
<= 0) {
WARN(1, "stop cmd time out\n");
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index e41bd49..92a4ae4 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -16,13 +16,13 @@
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
-#include <linux/bootmem.h>
#include <linux/memblock.h>
#include "mdss_fb.h"
#include "mdss_mdp.h"
#include "mdss_panel.h"
#include "mdss_debug.h"
+#include "mdss_mdp_trace.h"
/* wait for at least 2 vsyncs for lowest refresh rate (24hz) */
#define VSYNC_TIMEOUT_US 100000
@@ -494,6 +494,7 @@
ctl->underrun_cnt++;
MDSS_XLOG(ctl->num, ctl->underrun_cnt);
MDSS_XLOG_TOUT_HANDLER("mdp", "dsi0", "dsi1", "edp", "hdmi", "panic");
+ trace_mdp_video_underrun_done(ctl->num, ctl->underrun_cnt);
pr_debug("display underrun detected for ctl=%d count=%d\n", ctl->num,
ctl->underrun_cnt);
@@ -735,7 +736,6 @@
{
struct mdss_panel_data *pdata = ctl->panel_data;
int i, ret = 0;
- struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(ctl->mfd);
struct mdss_mdp_video_ctx *ctx;
struct mdss_data_type *mdata = ctl->mdata;
@@ -770,12 +770,6 @@
error:
pdata->panel_info.cont_splash_enabled = 0;
-
- /* Give back the reserved memory to the system */
- memblock_free(mdp5_data->splash_mem_addr, mdp5_data->splash_mem_size);
- free_bootmem_late(mdp5_data->splash_mem_addr,
- mdp5_data->splash_mem_size);
-
return ret;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c b/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
index 27a7707..02e7b75 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_writeback.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -131,13 +131,17 @@
struct mdss_mdp_format_params *fmt;
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
u32 opmode = ctx->opmode;
+ bool rotation = false;
struct mdss_data_type *mdata;
pr_debug("wb_num=%d format=%d\n", ctx->wb_num, format);
+ if (ctx->rot90)
+ rotation = true;
+
mdss_mdp_get_plane_sizes(format, ctx->width, ctx->height,
&ctx->dst_planes,
- ctx->opmode & MDSS_MDP_OP_BWC_EN);
+ ctx->opmode & MDSS_MDP_OP_BWC_EN, rotation);
fmt = mdss_mdp_get_format_params(format);
if (!fmt) {
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 4a5022e..faa60fe 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -35,8 +35,6 @@
#include "mdss_mdp.h"
#include "mdss_mdp_rotator.h"
-#include "splash.h"
-
#define VSYNC_PERIOD 16
#define BORDERFILL_NDX 0x0BF000BF
#define CHECK_BOUNDS(offset, size, max_size) \
@@ -47,7 +45,6 @@
#define MEM_PROTECT_SD_CTRL 0xF
-#define INVALID_PIPE_INDEX 0xFFFF
#define OVERLAY_MAX 10
struct sd_ctrl_req {
@@ -58,7 +55,6 @@
static int mdss_mdp_overlay_free_fb_pipe(struct msm_fb_data_type *mfd);
static int mdss_mdp_overlay_fb_parse_dt(struct msm_fb_data_type *mfd);
static int mdss_mdp_overlay_off(struct msm_fb_data_type *mfd);
-static int mdss_mdp_overlay_splash_parse_dt(struct msm_fb_data_type *mfd);
static void __overlay_kickoff_requeue(struct msm_fb_data_type *mfd);
static int mdss_mdp_overlay_sd_ctrl(struct msm_fb_data_type *mfd,
@@ -349,7 +345,7 @@
pipe->chroma_sample_v = 0;
}
-static int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd,
+int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd,
struct mdp_overlay *req,
struct mdss_mdp_pipe **ppipe)
{
@@ -823,7 +819,7 @@
mutex_unlock(&mfd->lock);
}
-static void __mdss_mdp_handoff_cleanup_pipes(struct msm_fb_data_type *mfd,
+void mdss_mdp_handoff_cleanup_pipes(struct msm_fb_data_type *mfd,
u32 type)
{
u32 i, npipes;
@@ -870,7 +866,7 @@
* from the the splash screen to the android boot animation when the
* continuous splash screen feature is enabled.
*/
-static int mdss_mdp_overlay_start(struct msm_fb_data_type *mfd)
+int mdss_mdp_overlay_start(struct msm_fb_data_type *mfd)
{
int rc;
struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
@@ -886,6 +882,7 @@
mdss_mdp_batfet_ctrl(mdp5_data->mdata, true);
if (!mfd->panel_info->cont_splash_enabled)
mdss_iommu_attach(mdp5_data->mdata);
+ mdss_mdp_release_splash_pipe(mfd);
return 0;
}
@@ -922,55 +919,7 @@
goto error;
}
- if (mfd->panel_info->cont_splash_enabled) {
- if (mdp5_data->handoff) {
- /*
- * Set up border-fill on the handed off pipes.
- * This is needed to ensure that there are no memory
- * accesses prior to attaching iommu during continuous
- * splash screen case. However, for command mode
- * displays, this is not necessary since the panels can
- * refresh from their internal memory if no data is sent
- * out on the dsi lanes.
- */
- if (ctl && ctl->is_video_mode) {
- rc = mdss_mdp_display_commit(ctl, NULL);
- if (!IS_ERR_VALUE(rc)) {
- mdss_mdp_display_wait4comp(ctl);
- } else {
- /*
- * Since border-fill setup failed, we
- * need to ensure that we turn off the
- * MDP timing generator before attaching
- * iommu
- */
- pr_err("failed to set BF at handoff\n");
- mdp5_data->handoff = false;
- rc = 0;
- }
- }
-
- /* Add all the handed off pipes to the cleanup list */
- __mdss_mdp_handoff_cleanup_pipes(mfd,
- MDSS_MDP_PIPE_TYPE_RGB);
- __mdss_mdp_handoff_cleanup_pipes(mfd,
- MDSS_MDP_PIPE_TYPE_VIG);
- __mdss_mdp_handoff_cleanup_pipes(mfd,
- MDSS_MDP_PIPE_TYPE_DMA);
- }
- rc = mdss_mdp_ctl_splash_finish(ctl, mdp5_data->handoff);
- /*
- * Remove the vote for footswitch even if above function
- * returned error
- */
- mdss_mdp_footswitch_ctrl_splash(0);
- if (rc)
- goto error;
-
- if (!is_mdss_iommu_attached())
- mdss_iommu_attach(mdss_res);
- }
-
+ rc = mdss_mdp_splash_cleanup(mfd, true);
error:
if (rc) {
mdss_mdp_ctl_destroy(ctl);
@@ -1098,6 +1047,7 @@
struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd);
int ret = 0;
int sd_in_pipe = 0;
+ bool need_cleanup = false;
if (ctl->shared_lock) {
mdss_mdp_ctl_notify(ctl, MDP_NOTIFY_FRAME_BEGIN);
@@ -1142,6 +1092,7 @@
list_for_each_entry(pipe, &mdp5_data->pipes_cleanup, cleanup_list) {
mdss_mdp_pipe_queue_data(pipe, NULL);
mdss_mdp_mixer_pipe_unstage(pipe);
+ need_cleanup = true;
}
ret = __overlay_queue_pipes(mfd);
@@ -1151,8 +1102,10 @@
else
ret = mdss_mdp_display_commit(mdp5_data->ctl, NULL);
- atomic_set(&mfd->kickoff_pending, 0);
- wake_up_all(&mfd->kickoff_wait_q);
+ if (!need_cleanup) {
+ atomic_set(&mfd->kickoff_pending, 0);
+ wake_up_all(&mfd->kickoff_wait_q);
+ }
mutex_unlock(&mfd->lock);
if (IS_ERR_VALUE(ret))
@@ -1179,7 +1132,10 @@
mdss_mdp_overlay_cleanup(mfd);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mdss_mdp_ctl_notify(ctl, MDP_NOTIFY_FRAME_FLUSHED);
-
+ if (need_cleanup) {
+ atomic_set(&mfd->kickoff_pending, 0);
+ wake_up_all(&mfd->kickoff_wait_q);
+ }
mutex_unlock(&mdp5_data->ov_lock);
if (ctl->shared_lock)
mutex_unlock(ctl->shared_lock);
@@ -1187,7 +1143,7 @@
return ret;
}
-static int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx)
+int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx)
{
struct mdss_mdp_pipe *pipe;
struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
@@ -1295,8 +1251,8 @@
}
}
- if (cnt == 0 && !list_empty(&mdp5_data->pipes_cleanup)) {
- pr_debug("overlay release on fb%d called without commit!",
+ if (!mfd->ref_cnt && !list_empty(&mdp5_data->pipes_cleanup)) {
+ pr_debug("fb%d:: free pipes present in cleanup list",
mfd->index);
cnt++;
}
@@ -1489,8 +1445,7 @@
static int mdss_mdp_overlay_get_fb_pipe(struct msm_fb_data_type *mfd,
struct mdss_mdp_pipe **ppipe,
- int mixer_mux,
- struct mdp_overlay *req_ov)
+ int mixer_mux)
{
struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
struct mdss_mdp_pipe *pipe;
@@ -1500,7 +1455,10 @@
MDSS_MDP_STAGE_BASE);
if (pipe == NULL) {
+ struct mdp_overlay req;
+ struct fb_info *fbi = mfd->fbi;
struct mdss_mdp_mixer *mixer;
+ int bpp;
mixer = mdss_mdp_mixer_get(mdp5_data->ctl,
MDSS_MDP_MIXER_MUX_LEFT);
@@ -1509,73 +1467,46 @@
return -ENODEV;
}
- if (req_ov == NULL) {
- struct mdp_overlay req;
- struct fb_info *fbi = mfd->fbi;
- int bpp;
+ memset(&req, 0, sizeof(req));
- memset(&req, 0, sizeof(req));
-
- bpp = fbi->var.bits_per_pixel / 8;
- req.id = MSMFB_NEW_REQUEST;
- req.src.format = mfd->fb_imgType;
- req.src.height = fbi->var.yres;
- req.src.width = fbi->fix.line_length / bpp;
- if (mixer_mux == MDSS_MDP_MIXER_MUX_RIGHT) {
- if (req.src.width <= mixer->width) {
- pr_warn("right fb pipe not needed\n");
- return -EINVAL;
- }
-
- req.flags |= MDSS_MDP_RIGHT_MIXER;
- req.src_rect.x = mixer->width;
- req.src_rect.w = fbi->var.xres - mixer->width;
- } else {
- req.src_rect.x = 0;
- req.src_rect.w = MIN(fbi->var.xres,
- mixer->width);
+ bpp = fbi->var.bits_per_pixel / 8;
+ req.id = MSMFB_NEW_REQUEST;
+ req.src.format = mfd->fb_imgType;
+ req.src.height = fbi->var.yres;
+ req.src.width = fbi->fix.line_length / bpp;
+ if (mixer_mux == MDSS_MDP_MIXER_MUX_RIGHT) {
+ if (req.src.width <= mixer->width) {
+ pr_warn("right fb pipe not needed\n");
+ return -EINVAL;
}
- req.src_rect.y = 0;
- req.src_rect.h = req.src.height;
- req.dst_rect.x = 0;
- req.dst_rect.y = 0;
- req.dst_rect.w = req.src_rect.w;
- req.dst_rect.h = req.src_rect.h;
- req.z_order = MDSS_MDP_STAGE_BASE;
-
- pr_debug("allocating base pipe mux=%d\n", mixer_mux);
-
- ret = mdss_mdp_overlay_pipe_setup(mfd, &req, &pipe);
- if (ret)
- return ret;
+ req.src_rect.x = mixer->width;
+ req.src_rect.w = fbi->var.xres - mixer->width;
} else {
- if (mixer_mux == MDSS_MDP_MIXER_MUX_RIGHT) {
- req_ov->id = MSMFB_NEW_REQUEST;
- req_ov->flags |= MDSS_MDP_RIGHT_MIXER;
- req_ov->src_rect.w = MIN(mixer->width,
- req_ov->src_rect.w >> 1);
- req_ov->dst_rect.w = req_ov->src_rect.w;
- req_ov->src_rect.x = req_ov->src_rect.w;
- req_ov->dst_rect.x = 0;
- }
-
- ret = mdss_mdp_overlay_pipe_setup(mfd, req_ov, &pipe);
- if (ret)
- return ret;
+ req.src_rect.x = 0;
+ req.src_rect.w = MIN(fbi->var.xres,
+ mixer->width);
}
- }
+ req.src_rect.y = 0;
+ req.src_rect.h = req.src.height;
+ req.dst_rect.w = req.src_rect.w;
+ req.dst_rect.h = req.src_rect.h;
+ req.z_order = MDSS_MDP_STAGE_BASE;
+
+ pr_debug("allocating base pipe mux=%d\n", mixer_mux);
+
+ ret = mdss_mdp_overlay_pipe_setup(mfd, &req, &pipe);
+ if (ret)
+ return ret;
+ }
pr_debug("ctl=%d pnum=%d\n", mdp5_data->ctl->num, pipe->num);
*ppipe = pipe;
return 0;
}
-static void mdss_mdp_overlay_pan_display(struct msm_fb_data_type *mfd,
- struct mdp_overlay *req,
- int image_size,
- int *pipe_ndx)
+static void mdss_mdp_overlay_pan_display(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_data *buf;
struct mdss_mdp_pipe *pipe;
@@ -1625,7 +1556,7 @@
}
ret = mdss_mdp_overlay_get_fb_pipe(mfd, &pipe,
- MDSS_MDP_MIXER_MUX_LEFT, req);
+ MDSS_MDP_MIXER_MUX_LEFT);
if (ret) {
pr_err("unable to allocate base pipe\n");
goto pan_display_error;
@@ -1635,14 +1566,13 @@
pr_err("unable to map base pipe\n");
goto pan_display_error;
}
- if (pipe_ndx)
- pipe_ndx[0] = pipe->ndx;
buf = &pipe->back_buf;
if (is_mdss_iommu_attached()) {
if (!mfd->iova) {
pr_err("mfd iova is zero\n");
- goto attach_err;
+ mdss_mdp_pipe_unmap(pipe);
+ goto pan_display_error;
}
buf->p[0].addr = mfd->iova;
} else {
@@ -1650,26 +1580,21 @@
}
buf->p[0].addr += offset;
- if (image_size)
- buf->p[0].len = image_size;
- else
- buf->p[0].len = fbi->fix.smem_len - offset;
+ buf->p[0].len = fbi->fix.smem_len - offset;
buf->num_planes = 1;
mdss_mdp_pipe_unmap(pipe);
if (fbi->var.xres > MAX_MIXER_WIDTH || mfd->split_display) {
ret = mdss_mdp_overlay_get_fb_pipe(mfd, &pipe,
- MDSS_MDP_MIXER_MUX_RIGHT, req);
+ MDSS_MDP_MIXER_MUX_RIGHT);
if (ret) {
pr_err("unable to allocate right base pipe\n");
- goto attach_err;
+ goto pan_display_error;
}
if (mdss_mdp_pipe_map(pipe)) {
pr_err("unable to map right base pipe\n");
- goto attach_err;
+ goto pan_display_error;
}
- if (pipe_ndx)
- pipe_ndx[1] = pipe->ndx;
pipe->back_buf = *buf;
mdss_mdp_pipe_unmap(pipe);
@@ -1683,13 +1608,6 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
return;
-attach_err:
- mutex_unlock(&mdp5_data->ov_lock);
- mdss_mdp_overlay_unset(mfd, pipe->ndx);
- if (pipe_ndx)
- pipe_ndx[0] = INVALID_PIPE_INDEX;
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
- return;
pan_display_error:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mutex_unlock(&mdp5_data->ov_lock);
@@ -2945,9 +2863,9 @@
error:
if (rc && ctl) {
- __mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_RGB);
- __mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_VIG);
- __mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_DMA);
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_RGB);
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_VIG);
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_DMA);
mdss_mdp_ctl_destroy(ctl);
mdp5_data->ctl = NULL;
mdp5_data->handoff = false;
@@ -2956,63 +2874,6 @@
return rc;
}
-static int mdss_mdp_overlay_splash_image(struct msm_fb_data_type *mfd,
- int *pipe_ndx, int splash_event)
-{
- struct mdp_overlay req;
- int rc = 0;
- struct fb_info *fbi = NULL;
- int image_len = 0;
-
- if (!mfd || !mfd->fbi || !mfd->fbi->screen_base || !pipe_ndx) {
- pr_err("Invalid input parameter\n");
- return -EINVAL;
- }
-
- fbi = mfd->fbi;
- image_len = SPLASH_IMAGE_WIDTH * SPLASH_IMAGE_HEIGHT * SPLASH_IMAGE_BPP;
-
- if (SPLASH_IMAGE_WIDTH > fbi->var.xres ||
- SPLASH_IMAGE_HEIGHT > fbi->var.yres ||
- SPLASH_IMAGE_BPP > fbi->var.bits_per_pixel / 8 ||
- image_len > fbi->fix.smem_len) {
- pr_err("Invalid splash parameter configuration\n");
- return -EINVAL;
- }
-
- if (splash_event == MDP_CREATE_SPLASH_OV) {
- pipe_ndx[0] = INVALID_PIPE_INDEX;
- pipe_ndx[1] = INVALID_PIPE_INDEX;
-
- memset(&req, 0, sizeof(struct mdp_overlay));
- req.src.width = req.dst_rect.w = req.src_rect.w =
- SPLASH_IMAGE_WIDTH;
- req.src.height = req.dst_rect.h = req.src_rect.h =
- SPLASH_IMAGE_HEIGHT;
- req.src.format = SPLASH_IMAGE_FORMAT;
- req.id = MSMFB_NEW_REQUEST;
- req.z_order = MDSS_MDP_STAGE_0;
- req.is_fg = 1;
- req.alpha = 0xff;
- req.transp_mask = MDP_TRANSP_NOP;
- req.dst_rect.x =
- (fbi->var.xres >> 1) - (SPLASH_IMAGE_WIDTH >> 1);
- req.dst_rect.y =
- (fbi->var.yres >> 1) - (SPLASH_IMAGE_HEIGHT >> 1);
-
- memcpy(fbi->screen_base, splash_bgr888_image, image_len);
- mdss_mdp_overlay_pan_display(mfd, &req, image_len, pipe_ndx);
-
- } else if (splash_event == MDP_REMOVE_SPLASH_OV) {
- if (pipe_ndx[0] != INVALID_PIPE_INDEX)
- mdss_mdp_overlay_unset(mfd, pipe_ndx[0]);
- if (pipe_ndx[1] != INVALID_PIPE_INDEX)
- mdss_mdp_overlay_unset(mfd, pipe_ndx[1]);
- }
-
- return rc;
-}
-
static void __vsync_retire_handle_vsync(struct mdss_mdp_ctl *ctl, ktime_t t)
{
struct msm_fb_data_type *mfd = ctl->mfd;
@@ -3131,7 +2992,7 @@
mdp5_interface->panel_register_done = mdss_panel_register_done;
mdp5_interface->kickoff_fnc = mdss_mdp_overlay_kickoff;
mdp5_interface->get_sync_fnc = mdss_mdp_rotator_sync_pt_get;
- mdp5_interface->splash_fnc = mdss_mdp_overlay_splash_image;
+ mdp5_interface->splash_init_fnc = mdss_mdp_splash_init;
mdp5_data = kmalloc(sizeof(struct mdss_overlay_private), GFP_KERNEL);
if (!mdp5_data) {
@@ -3225,45 +3086,6 @@
return rc;
}
-static __ref int mdss_mdp_overlay_splash_parse_dt(struct msm_fb_data_type *mfd)
-{
- struct platform_device *pdev = mfd->pdev;
- struct mdss_overlay_private *mdp5_mdata = mfd_to_mdp5_data(mfd);
- int len = 0, rc = 0;
- u32 offsets[2];
-
- of_find_property(pdev->dev.of_node, "qcom,memblock-reserve", &len);
-
- if (len < 1) {
- pr_debug("mem reservation for splash screen fb not present\n");
- rc = -EINVAL;
- goto error;
- }
-
- len = len/sizeof(u32);
-
- rc = of_property_read_u32_array(pdev->dev.of_node,
- "qcom,memblock-reserve", offsets, len);
- if (rc) {
- pr_debug("Error reading mem reserve settings for fb\n");
- goto error;
- }
-
- if (!memblock_is_reserved(offsets[0])) {
- pr_debug("failed to reserve memory for fb splash\n");
- rc = -EINVAL;
- goto error;
- }
-
- mdp5_mdata->splash_mem_addr = offsets[0];
- mdp5_mdata->splash_mem_size = offsets[1];
- pr_debug("memaddr=%x size=%x\n", mdp5_mdata->splash_mem_addr,
- mdp5_mdata->splash_mem_size);
-
-error:
- return rc;
-}
-
static int mdss_mdp_overlay_fb_parse_dt(struct msm_fb_data_type *mfd)
{
int rc = 0;
@@ -3277,13 +3099,5 @@
pdev->name);
}
- rc = mdss_mdp_overlay_splash_parse_dt(mfd);
- if (rc && mfd->panel_info->cont_splash_enabled) {
- pr_err("No rsvd mem found in DT for splash screen\n");
- } else {
- pr_debug("Mem reservation not reqd if cont splash diasbled\n");
- rc = 0;
- }
-
return rc;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_pipe.c b/drivers/video/msm/mdss/mdss_mdp_pipe.c
index c522857..32b8cbf 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pipe.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pipe.c
@@ -270,7 +270,7 @@
}
}
rc = mdss_mdp_get_plane_sizes(format, width, pipe->src.h,
- &ps, 0);
+ &ps, 0, 0);
if (rc)
return rc;
@@ -883,6 +883,7 @@
u32 decimation;
struct mdss_mdp_img_rect sci, dst, src;
int ret = 0;
+ bool rotation = false;
pr_debug("pnum=%d wh=%dx%d src={%d,%d,%d,%d} dst={%d,%d,%d,%d}\n",
pipe->num, pipe->img_width, pipe->img_height,
@@ -891,8 +892,12 @@
width = pipe->img_width;
height = pipe->img_height;
+
+ if (pipe->flags & MDP_SOURCE_ROTATED_90)
+ rotation = true;
+
mdss_mdp_get_plane_sizes(pipe->src_fmt->format, width, height,
- &pipe->src_planes, pipe->bwc_mode);
+ &pipe->src_planes, pipe->bwc_mode, rotation);
if (data != NULL) {
ret = mdss_mdp_data_check(data, &pipe->src_planes);
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index 6b497bb..42e7ed2 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -81,6 +81,8 @@
#define MDSS_BLOCK_DISP_NUM (MDP_BLOCK_MAX - MDP_LOGICAL_BLOCK_DISP_0)
#define HIST_WAIT_TIMEOUT(frame) ((75 * HZ * (frame)) / 1000)
+#define HIST_KICKOFF_WAIT_FRACTION 4
+
/* hist collect state */
enum {
HIST_UNKNOWN,
@@ -1351,6 +1353,7 @@
/* Kick off collection */
writel_relaxed(1, base + kick_base);
hist_info->col_state = HIST_START;
+ complete(&hist_info->first_kick);
}
}
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
@@ -1609,6 +1612,7 @@
u32 disp_num;
int i;
bool valid_mixers = true;
+ bool valid_ad_panel = true;
if ((!ctl->mfd) || (!mdss_pp_res))
return -EINVAL;
@@ -1629,7 +1633,13 @@
if (mixer_id[i] >= mdata->nad_cfgs)
valid_mixers = false;
}
- if (valid_mixers && (mixer_cnt <= mdata->nmax_concurrent_ad_hw)) {
+ valid_ad_panel = (ctl->mfd->panel_info->type != DTV_PANEL) &&
+ (((mdata->mdp_rev < MDSS_MDP_HW_REV_103) &&
+ (ctl->mfd->panel_info->type == WRITEBACK_PANEL)) ||
+ (ctl->mfd->panel_info->type != WRITEBACK_PANEL));
+
+ if (valid_mixers && (mixer_cnt <= mdata->nmax_concurrent_ad_hw) &&
+ valid_ad_panel) {
ret = mdss_mdp_ad_setup(ctl->mfd);
if (ret < 0)
pr_warn("ad_setup(disp%d) returns %d", disp_num, ret);
@@ -1788,6 +1798,8 @@
&mdss_pp_res->dspp_hist[i].hist_lock);
init_completion(
&mdss_pp_res->dspp_hist[i].comp);
+ init_completion(
+ &mdss_pp_res->dspp_hist[i].first_kick);
}
}
}
@@ -1797,6 +1809,7 @@
mutex_init(&vig[i].pp_res.hist.hist_mutex);
spin_lock_init(&vig[i].pp_res.hist.hist_lock);
init_completion(&vig[i].pp_res.hist.comp);
+ init_completion(&vig[i].pp_res.hist.first_kick);
}
if (!mdata->pp_bus_hdl) {
pp_bus_pdata = &mdp_pp_bus_scale_table;
@@ -3006,6 +3019,7 @@
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
hist_info->frame_cnt = req->frame_cnt;
INIT_COMPLETION(hist_info->comp);
+ INIT_COMPLETION(hist_info->first_kick);
hist_info->hist_cnt_read = 0;
hist_info->hist_cnt_sent = 0;
hist_info->hist_cnt_time = 0;
@@ -3131,6 +3145,7 @@
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
mdss_mdp_hist_intr_req(&mdata->hist_intr, done_bit, false);
complete_all(&hist_info->comp);
+ complete_all(&hist_info->first_kick);
writel_relaxed(BIT(1), ctl_base);/* cancel */
ret = 0;
exit:
@@ -3363,7 +3378,7 @@
struct pp_hist_col_info *hist_info,
char __iomem *ctl_base, u32 expect_sum)
{
- int wait_ret, ret = 0;
+ int kick_ret, wait_ret, ret = 0;
u32 timeout, sum;
char __iomem *v_base;
unsigned long flag;
@@ -3389,12 +3404,26 @@
pipe = container_of(res, struct mdss_mdp_pipe, pp_res);
pipe->params_changed++;
}
- wait_ret = wait_for_completion_killable_timeout(
+ kick_ret = wait_for_completion_killable_timeout(
+ &(hist_info->first_kick), timeout /
+ HIST_KICKOFF_WAIT_FRACTION);
+ if (kick_ret != 0)
+ wait_ret = wait_for_completion_killable_timeout(
&(hist_info->comp), timeout);
mutex_lock(&hist_info->hist_mutex);
spin_lock_irqsave(&hist_info->hist_lock, flag);
- if (wait_ret == 0) {
+ if (kick_ret == 0) {
+ ret = -ENODATA;
+ pr_debug("histogram kickoff not done yet");
+ spin_unlock_irqrestore(&hist_info->hist_lock, flag);
+ goto hist_collect_exit;
+ } else if (kick_ret < 0) {
+ ret = -EINTR;
+ pr_debug("histogram first kickoff interrupted");
+ spin_unlock_irqrestore(&hist_info->hist_lock, flag);
+ goto hist_collect_exit;
+ } else if (wait_ret == 0) {
ret = -ETIMEDOUT;
pr_debug("bin collection timedout, state %d",
hist_info->col_state);
diff --git a/drivers/video/msm/mdss/mdss_mdp_splash_logo.c b/drivers/video/msm/mdss/mdss_mdp_splash_logo.c
new file mode 100644
index 0000000..838f58f
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_mdp_splash_logo.c
@@ -0,0 +1,623 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/memblock.h>
+#include <linux/bootmem.h>
+#include <linux/iommu.h>
+#include <linux/fb.h>
+
+#include "mdss_fb.h"
+#include "mdss_mdp.h"
+#include "splash.h"
+#include "mdss_mdp_splash_logo.h"
+
+#define INVALID_PIPE_INDEX 0xFFFF
+#define MAX_FRAME_DONE_COUNT_WAIT 2
+
+static int mdss_mdp_splash_alloc_memory(struct msm_fb_data_type *mfd,
+ uint32_t size)
+{
+ int rc;
+ struct msm_fb_splash_info *sinfo;
+ unsigned long buf_size = size;
+ struct mdss_data_type *mdata;
+
+ if (!mfd || !size)
+ return -EINVAL;
+
+ mdata = mfd_to_mdata(mfd);
+ sinfo = &mfd->splash_info;
+
+ if (!mdata || !mdata->iclient || sinfo->splash_buffer)
+ return -EINVAL;
+
+ sinfo->ion_handle = ion_alloc(mdata->iclient, size, SZ_4K,
+ ION_HEAP(ION_SYSTEM_HEAP_ID), 0);
+ if (IS_ERR_OR_NULL(sinfo->ion_handle)) {
+ pr_err("ion memory allocation failed\n");
+ rc = PTR_RET(sinfo->ion_handle);
+ goto end;
+ }
+
+ rc = ion_map_iommu(mdata->iclient, sinfo->ion_handle,
+ mdss_get_iommu_domain(MDSS_IOMMU_DOMAIN_UNSECURE),
+ 0, SZ_4K, 0, (unsigned long *)&sinfo->iova,
+ (unsigned long *)&buf_size, 0, 0);
+ if (rc) {
+ pr_err("ion memory map failed\n");
+ goto imap_err;
+ }
+
+ sinfo->splash_buffer = ion_map_kernel(mdata->iclient,
+ sinfo->ion_handle);
+ if (IS_ERR_OR_NULL(sinfo->splash_buffer)) {
+ pr_err("ion kernel memory mapping failed\n");
+ rc = IS_ERR(sinfo->splash_buffer);
+ goto kmap_err;
+ }
+
+ return rc;
+
+kmap_err:
+ ion_unmap_iommu(mdata->iclient, sinfo->ion_handle,
+ mdss_get_iommu_domain(MDSS_IOMMU_DOMAIN_UNSECURE), 0);
+imap_err:
+ ion_free(mdata->iclient, sinfo->ion_handle);
+end:
+ return rc;
+}
+
+static void mdss_mdp_splash_free_memory(struct msm_fb_data_type *mfd)
+{
+ struct msm_fb_splash_info *sinfo;
+ struct mdss_data_type *mdata;
+
+ if (!mfd)
+ return;
+
+ sinfo = &mfd->splash_info;
+ mdata = mfd_to_mdata(mfd);
+
+ if (!mdata || !mdata->iclient || !sinfo->ion_handle)
+ return;
+
+ ion_unmap_kernel(mdata->iclient, sinfo->ion_handle);
+
+ ion_unmap_iommu(mdata->iclient, sinfo->ion_handle,
+ mdss_get_iommu_domain(MDSS_IOMMU_DOMAIN_UNSECURE), 0);
+
+ ion_free(mdata->iclient, sinfo->ion_handle);
+ sinfo->splash_buffer = NULL;
+}
+
+static int mdss_mdp_splash_iommu_attach(struct msm_fb_data_type *mfd)
+{
+ struct iommu_domain *domain;
+ struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
+ int rc;
+
+ /*
+ * iommu dynamic attach for following conditions.
+ * 1. it is still not attached
+ * 2. MDP hardware version supports the feature
+ * 3. configuration is with valid splash buffer
+ */
+ if (is_mdss_iommu_attached() ||
+ !mfd->panel_info->cont_splash_enabled ||
+ !mdss_mdp_iommu_dyn_attach_supported(mdp5_data->mdata) ||
+ !mdp5_data->splash_mem_addr ||
+ !mdp5_data->splash_mem_size) {
+ pr_debug("dynamic attach is not supported\n");
+ return -EPERM;
+ }
+
+ domain = msm_get_iommu_domain(mdss_get_iommu_domain(
+ MDSS_IOMMU_DOMAIN_UNSECURE));
+ if (!domain) {
+ pr_debug("mdss iommu domain get failed\n");
+ return -EINVAL;
+ }
+
+ rc = iommu_map(domain, mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_size, IOMMU_READ);
+ if (rc) {
+ pr_debug("iommu memory mapping failed rc=%d\n", rc);
+ } else {
+ rc = mdss_iommu_attach(mdss_res);
+ if (rc) {
+ pr_debug("mdss iommu attach failed\n");
+ iommu_unmap(domain, mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_size);
+ } else {
+ mfd->splash_info.iommu_dynamic_attached = true;
+ }
+ }
+
+ return rc;
+}
+
+static void mdss_mdp_splash_unmap_splash_mem(struct msm_fb_data_type *mfd)
+{
+ struct iommu_domain *domain;
+ struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
+
+ if (mfd->splash_info.iommu_dynamic_attached) {
+ domain = msm_get_iommu_domain(mdss_get_iommu_domain(
+ MDSS_IOMMU_DOMAIN_UNSECURE));
+ if (!domain) {
+ pr_err("mdss iommu domain get failed\n");
+ return;
+ }
+
+ iommu_unmap(domain, mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_size);
+ mfd->splash_info.iommu_dynamic_attached = false;
+ }
+}
+
+void mdss_mdp_release_splash_pipe(struct msm_fb_data_type *mfd)
+{
+ struct msm_fb_splash_info *sinfo;
+
+ if (!mfd || !mfd->splash_info.splash_pipe_allocated)
+ return;
+
+ sinfo = &mfd->splash_info;
+
+ if (sinfo->pipe_ndx[0] != INVALID_PIPE_INDEX)
+ mdss_mdp_overlay_release(mfd, sinfo->pipe_ndx[0]);
+ if (sinfo->pipe_ndx[1] != INVALID_PIPE_INDEX)
+ mdss_mdp_overlay_release(mfd, sinfo->pipe_ndx[1]);
+ sinfo->splash_pipe_allocated = false;
+}
+
+int mdss_mdp_splash_cleanup(struct msm_fb_data_type *mfd,
+ bool use_borderfill)
+{
+ struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
+ struct mdss_mdp_ctl *ctl = mdp5_data->ctl;
+ int rc = 0;
+
+ if (!mfd || !mdp5_data)
+ return -EINVAL;
+
+ if (mfd->splash_info.iommu_dynamic_attached ||
+ !mfd->panel_info->cont_splash_enabled)
+ goto end;
+
+ if (use_borderfill && mdp5_data->handoff) {
+ /*
+ * Set up border-fill on the handed off pipes.
+ * This is needed to ensure that there are no memory
+ * accesses prior to attaching iommu during continuous
+ * splash screen case. However, for command mode
+ * displays, this is not necessary since the panels can
+ * refresh from their internal memory if no data is sent
+ * out on the dsi lanes.
+ */
+ if (mdp5_data->handoff && ctl && ctl->is_video_mode) {
+ rc = mdss_mdp_display_commit(ctl, NULL);
+ if (!IS_ERR_VALUE(rc)) {
+ mdss_mdp_display_wait4comp(ctl);
+ } else {
+ /*
+ * Since border-fill setup failed, we
+ * need to ensure that we turn off the
+ * MDP timing generator before attaching
+ * iommu
+ */
+ pr_err("failed to set BF at handoff\n");
+ mdp5_data->handoff = false;
+ }
+ }
+ }
+
+ if (rc || mdp5_data->handoff) {
+ /* Add all the handed off pipes to the cleanup list */
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_RGB);
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_VIG);
+ mdss_mdp_handoff_cleanup_pipes(mfd, MDSS_MDP_PIPE_TYPE_DMA);
+ }
+
+ mdss_mdp_ctl_splash_finish(ctl, mdp5_data->handoff);
+
+ if (mdp5_data->splash_mem_addr) {
+ /* Give back the reserved memory to the system */
+ memblock_free(mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_size);
+ free_bootmem_late(mdp5_data->splash_mem_addr,
+ mdp5_data->splash_mem_size);
+ }
+
+ mdss_mdp_footswitch_ctrl_splash(0);
+ if (!is_mdss_iommu_attached()) {
+ rc = mdss_iommu_attach(mdss_res);
+ if (rc)
+ pr_err("iommu attach failed rc=%d\n", rc);
+ }
+
+end:
+ return rc;
+}
+
+static struct mdss_mdp_pipe *mdss_mdp_splash_get_pipe(
+ struct msm_fb_data_type *mfd,
+ struct mdp_overlay *req)
+{
+ struct mdss_mdp_pipe *pipe;
+ int ret;
+ struct mdss_mdp_data *buf;
+ uint32_t image_size = SPLASH_IMAGE_WIDTH * SPLASH_IMAGE_HEIGHT
+ * SPLASH_IMAGE_BPP;
+
+ ret = mdss_mdp_overlay_pipe_setup(mfd, req, &pipe);
+ if (ret)
+ return NULL;
+
+ if (mdss_mdp_pipe_map(pipe)) {
+ pr_err("unable to map base pipe\n");
+ return NULL;
+ }
+
+ buf = &pipe->back_buf;
+ buf->p[0].addr = mfd->splash_info.iova;
+ buf->p[0].len = image_size;
+ buf->num_planes = 1;
+ mdss_mdp_pipe_unmap(pipe);
+
+ return pipe;
+}
+
+static int mdss_mdp_splash_kickoff(struct msm_fb_data_type *mfd,
+ struct mdss_mdp_img_rect *src_rect,
+ struct mdss_mdp_img_rect *dest_rect)
+{
+ struct mdss_mdp_pipe *pipe;
+ struct fb_info *fbi;
+ struct mdp_overlay req;
+ struct mdss_overlay_private *mdp5_data;
+ struct mdss_data_type *mdata;
+ struct mdss_mdp_mixer *mixer;
+ int ret;
+ bool use_single_pipe = false;
+ struct msm_fb_splash_info *sinfo;
+
+ if (!mfd)
+ return -EINVAL;
+
+ fbi = mfd->fbi;
+ mdp5_data = mfd_to_mdp5_data(mfd);
+ mdata = mfd_to_mdata(mfd);
+ sinfo = &mfd->splash_info;
+
+ if (!mdp5_data || !mdp5_data->ctl)
+ return -EINVAL;
+
+ if (mutex_lock_interruptible(&mdp5_data->ov_lock))
+ return -EINVAL;
+
+ ret = mdss_mdp_overlay_start(mfd);
+ if (ret) {
+ pr_err("unable to start overlay %d (%d)\n", mfd->index, ret);
+ goto end;
+ }
+
+ mixer = mdss_mdp_mixer_get(mdp5_data->ctl, MDSS_MDP_MIXER_MUX_LEFT);
+ if (!mixer) {
+ pr_err("unable to retrieve mixer\n");
+ ret = -EINVAL;
+ goto end;
+ }
+
+ memset(&req, 0, sizeof(struct mdp_overlay));
+ /*
+ * use single pipe for
+ * 1. split display disabled
+ * 2. splash image is only on one side of panel
+ */
+ use_single_pipe =
+ !mfd->split_display ||
+ (mfd->split_display &&
+ ((dest_rect->x + dest_rect->w) < mfd->split_fb_left ||
+ dest_rect->x > mfd->split_fb_left));
+
+ req.src.width = src_rect->w;
+ if (use_single_pipe)
+ req.src_rect.w = src_rect->w;
+ else
+ req.src_rect.w = min_t(u16, mixer->width, src_rect->w >> 1);
+ req.dst_rect.w = req.src_rect.w;
+ req.src.height = req.dst_rect.h = req.src_rect.h =
+ src_rect->h;
+ req.src.format = SPLASH_IMAGE_FORMAT;
+ req.id = MSMFB_NEW_REQUEST;
+ req.z_order = MDSS_MDP_STAGE_0;
+ req.alpha = 0xff;
+ req.transp_mask = MDP_TRANSP_NOP;
+ req.dst_rect.x = dest_rect->x;
+ req.dst_rect.y = dest_rect->y;
+
+ pipe = mdss_mdp_splash_get_pipe(mfd, &req);
+ if (!pipe) {
+ pr_err("unable to allocate base pipe\n");
+ ret = -EINVAL;
+ goto end;
+ }
+
+ sinfo->pipe_ndx[0] = pipe->ndx;
+
+ if (!use_single_pipe) {
+ req.id = MSMFB_NEW_REQUEST;
+ req.src_rect.x = src_rect->x + min_t(u16, mixer->width,
+ src_rect->w - req.src_rect.w);
+ req.dst_rect.x = mixer->width;
+ pipe = mdss_mdp_splash_get_pipe(mfd, &req);
+ if (!pipe) {
+ pr_err("unable to allocate right base pipe\n");
+ mdss_mdp_overlay_release(mfd, sinfo->pipe_ndx[0]);
+ ret = -EINVAL;
+ goto end;
+ }
+ sinfo->pipe_ndx[1] = pipe->ndx;
+ }
+ mutex_unlock(&mdp5_data->ov_lock);
+
+ ret = mfd->mdp.kickoff_fnc(mfd, NULL);
+ if (ret) {
+ pr_err("error in displaying image\n");
+ mdss_mdp_overlay_release(mfd, sinfo->pipe_ndx[0] |
+ sinfo->pipe_ndx[1]);
+ }
+
+ return ret;
+end:
+ sinfo->pipe_ndx[0] = INVALID_PIPE_INDEX;
+ sinfo->pipe_ndx[1] = INVALID_PIPE_INDEX;
+ mutex_unlock(&mdp5_data->ov_lock);
+ return ret;
+}
+
+static int mdss_mdp_display_splash_image(struct msm_fb_data_type *mfd)
+{
+ int rc = 0;
+ struct fb_info *fbi;
+ uint32_t image_len = SPLASH_IMAGE_WIDTH * SPLASH_IMAGE_HEIGHT
+ * SPLASH_IMAGE_BPP;
+ struct mdss_mdp_img_rect src_rect, dest_rect;
+ struct msm_fb_splash_info *sinfo;
+
+ if (!mfd || !mfd->fbi) {
+ pr_err("invalid input parameter\n");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ fbi = mfd->fbi;
+ sinfo = &mfd->splash_info;
+
+ if (SPLASH_IMAGE_WIDTH > fbi->var.xres ||
+ SPLASH_IMAGE_HEIGHT > fbi->var.yres ||
+ SPLASH_IMAGE_BPP > (fbi->var.bits_per_pixel >> 3)) {
+ pr_err("invalid splash parameter configuration\n");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ sinfo->pipe_ndx[0] = INVALID_PIPE_INDEX;
+ sinfo->pipe_ndx[1] = INVALID_PIPE_INDEX;
+
+ src_rect.x = 0;
+ src_rect.y = 0;
+ dest_rect.w = src_rect.w = SPLASH_IMAGE_WIDTH;
+ dest_rect.h = src_rect.h = SPLASH_IMAGE_HEIGHT;
+ dest_rect.x = (fbi->var.xres >> 1) - (SPLASH_IMAGE_WIDTH >> 1);
+ dest_rect.y = (fbi->var.yres >> 1) - (SPLASH_IMAGE_HEIGHT >> 1);
+
+ rc = mdss_mdp_splash_alloc_memory(mfd, image_len);
+ if (rc) {
+ pr_err("splash buffer allocation failed\n");
+ goto end;
+ }
+
+ memcpy(sinfo->splash_buffer, splash_bgr888_image, image_len);
+
+ rc = mdss_mdp_splash_iommu_attach(mfd);
+ if (rc)
+ pr_debug("iommu dynamic attach failed\n");
+
+ rc = mdss_mdp_splash_kickoff(mfd, &src_rect, &dest_rect);
+ if (rc)
+ pr_err("splash image display failed\n");
+ else
+ sinfo->splash_pipe_allocated = true;
+end:
+ return rc;
+}
+
+static int mdss_mdp_splash_ctl_cb(struct notifier_block *self,
+ unsigned long event, void *data)
+{
+ struct msm_fb_splash_info *sinfo = container_of(self,
+ struct msm_fb_splash_info, notifier);
+ struct msm_fb_data_type *mfd;
+
+ if (!sinfo)
+ goto done;
+
+ mfd = container_of(sinfo, struct msm_fb_data_type, splash_info);
+
+ if (!mfd)
+ goto done;
+
+ if (event != MDP_NOTIFY_FRAME_DONE)
+ goto done;
+
+ if (!sinfo->frame_done_count) {
+ mdss_mdp_splash_unmap_splash_mem(mfd);
+ mdss_mdp_splash_cleanup(mfd, false);
+ /* wait for 2 frame done events before releasing memory */
+ } else if (sinfo->frame_done_count > MAX_FRAME_DONE_COUNT_WAIT &&
+ sinfo->splash_thread) {
+ complete(&sinfo->frame_done);
+ sinfo->splash_thread = NULL;
+ }
+
+ /* increase frame done count after pipes are staged from other client */
+ if (!sinfo->splash_pipe_allocated)
+ sinfo->frame_done_count++;
+done:
+ return NOTIFY_OK;
+}
+
+static int mdss_mdp_splash_thread(void *data)
+{
+ struct msm_fb_data_type *mfd = data;
+ struct mdss_overlay_private *mdp5_data = mfd_to_mdp5_data(mfd);
+ int ret = -EINVAL;
+
+ if (!mfd) {
+ pr_err("invalid input parameter\n");
+ goto end;
+ }
+
+ lock_fb_info(mfd->fbi);
+ ret = fb_blank(mfd->fbi, FB_BLANK_UNBLANK);
+ if (ret) {
+ pr_err("can't turn on fb!\n");
+ goto end;
+ }
+ unlock_fb_info(mfd->fbi);
+
+ mutex_lock(&mfd->bl_lock);
+ mfd->bl_updated = true;
+ mdss_fb_set_backlight(mfd, mfd->panel_info->bl_max >> 1);
+ mutex_unlock(&mfd->bl_lock);
+
+ init_completion(&mfd->splash_info.frame_done);
+
+ mfd->splash_info.notifier.notifier_call = mdss_mdp_splash_ctl_cb;
+ mdss_mdp_ctl_notifier_register(mdp5_data->ctl,
+ &mfd->splash_info.notifier);
+
+ ret = mdss_mdp_display_splash_image(mfd);
+ if (ret) {
+ /*
+ * keep thread alive to release dynamically allocated
+ * resources
+ */
+ pr_err("splash image display failed\n");
+ }
+
+ /* wait for second display complete to release splash resources */
+ ret = wait_for_completion_killable(&mfd->splash_info.frame_done);
+
+ mdss_mdp_splash_free_memory(mfd);
+
+ mdss_mdp_ctl_notifier_unregister(mdp5_data->ctl,
+ &mfd->splash_info.notifier);
+end:
+ return ret;
+}
+
+static __ref int mdss_mdp_splash_parse_dt(struct msm_fb_data_type *mfd)
+{
+ struct platform_device *pdev = mfd->pdev;
+ struct mdss_overlay_private *mdp5_mdata = mfd_to_mdp5_data(mfd);
+ int len = 0, rc = 0;
+ u32 offsets[2];
+
+ mfd->splash_info.splash_logo_enabled =
+ of_property_read_bool(pdev->dev.of_node,
+ "qcom,mdss-fb-splash-logo-enabled");
+
+ of_find_property(pdev->dev.of_node, "qcom,memblock-reserve", &len);
+ if (len < 1) {
+ pr_debug("mem reservation for splash screen fb not present\n");
+ rc = -EINVAL;
+ goto error;
+ }
+
+ len = len / sizeof(u32);
+
+ rc = of_property_read_u32_array(pdev->dev.of_node,
+ "qcom,memblock-reserve", offsets, len);
+ if (rc) {
+ pr_debug("error reading mem reserve settings for fb\n");
+ goto error;
+ }
+
+ if (!memblock_is_reserved(offsets[0])) {
+ pr_debug("failed to reserve memory for fb splash\n");
+ rc = -EINVAL;
+ goto error;
+ }
+
+ mdp5_mdata->splash_mem_addr = offsets[0];
+ mdp5_mdata->splash_mem_size = offsets[1];
+ pr_debug("memaddr=%x size=%x\n", mdp5_mdata->splash_mem_addr,
+ mdp5_mdata->splash_mem_size);
+
+error:
+ if (!rc && !mfd->panel_info->cont_splash_enabled &&
+ mdp5_mdata->splash_mem_addr) {
+ pr_debug("mem reservation not reqd if cont splash disabled\n");
+ memblock_free(mdp5_mdata->splash_mem_addr,
+ mdp5_mdata->splash_mem_size);
+ free_bootmem_late(mdp5_mdata->splash_mem_addr,
+ mdp5_mdata->splash_mem_size);
+ } else if (rc && mfd->panel_info->cont_splash_enabled) {
+ pr_err("no rsvd mem found in DT for splash screen\n");
+ } else {
+ rc = 0;
+ }
+
+ return rc;
+}
+
+int mdss_mdp_splash_init(struct msm_fb_data_type *mfd)
+{
+ int rc;
+
+ if (!mfd) {
+ rc = -EINVAL;
+ goto end;
+ }
+
+ rc = mdss_mdp_splash_parse_dt(mfd);
+ if (rc) {
+ pr_err("splash memory reserve failed\n");
+ goto end;
+ }
+
+ if (!mfd->splash_info.splash_logo_enabled) {
+ rc = -EINVAL;
+ goto end;
+ }
+
+ mfd->splash_info.splash_thread = kthread_run(mdss_mdp_splash_thread,
+ mfd, "mdss_fb_splash");
+
+ if (IS_ERR(mfd->splash_info.splash_thread)) {
+ pr_err("unable to start splash thread %d\n", mfd->index);
+ mfd->splash_info.splash_thread = NULL;
+ }
+
+end:
+ return rc;
+}
diff --git a/drivers/video/msm/mdss/mdss_mdp_splash_logo.h b/drivers/video/msm/mdss/mdss_mdp_splash_logo.h
new file mode 100644
index 0000000..0a4e83b
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_mdp_splash_logo.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef MDSS_MDP_SPLASH_LOGO
+#define MDSS_MDP_SPLASH_LOGO
+
+#include <linux/types.h>
+#include <linux/notifier.h>
+#include <linux/kthread.h>
+#include <linux/completion.h>
+
+struct msm_fb_splash_info {
+ struct task_struct *splash_thread;
+ bool splash_logo_enabled;
+ bool iommu_dynamic_attached;
+ struct notifier_block notifier;
+ uint32_t frame_done_count;
+ struct completion frame_done;
+
+ struct ion_handle *ion_handle;
+ dma_addr_t iova;
+ void *splash_buffer;
+ int pipe_ndx[2];
+ bool splash_pipe_allocated;
+};
+
+struct msm_fb_data_type;
+
+void mdss_mdp_release_splash_pipe(struct msm_fb_data_type *mfd);
+int mdss_mdp_splash_cleanup(struct msm_fb_data_type *mfd,
+ bool use_borderfill);
+int mdss_mdp_splash_init(struct msm_fb_data_type *mfd);
+
+#endif
diff --git a/drivers/video/msm/mdss/mdss_mdp_trace.h b/drivers/video/msm/mdss/mdss_mdp_trace.h
new file mode 100644
index 0000000..0e0c1e7
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_mdp_trace.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#if !defined(TRACE_MDSS_MDP_H) || defined(TRACE_HEADER_MULTI_READ)
+#define TRACE_MDSS_MDP_H
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM mdss
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE mdss_mdp_trace
+
+#include <linux/tracepoint.h>
+#include "mdss_mdp.h"
+
+DECLARE_EVENT_CLASS(mdp_sspp_template,
+ TP_PROTO(struct mdss_mdp_pipe *pipe),
+ TP_ARGS(pipe),
+ TP_STRUCT__entry(
+ __field(u32, num)
+ __field(u32, play_cnt)
+ __field(u32, mixer)
+ __field(u32, stage)
+ __field(u32, flags)
+ __field(u32, format)
+ __field(u16, img_w)
+ __field(u16, img_h)
+ __field(u16, src_x)
+ __field(u16, src_y)
+ __field(u16, src_w)
+ __field(u16, src_h)
+ __field(u16, dst_x)
+ __field(u16, dst_y)
+ __field(u16, dst_w)
+ __field(u16, dst_h)
+ ),
+ TP_fast_assign(
+ __entry->num = pipe->num;
+ __entry->play_cnt = pipe->play_cnt;
+ __entry->mixer = pipe->mixer->num;
+ __entry->stage = pipe->mixer_stage;
+ __entry->flags = pipe->flags;
+ __entry->format = pipe->src_fmt ?
+ pipe->src_fmt->format : -1;
+ __entry->img_w = pipe->img_width;
+ __entry->img_h = pipe->img_height;
+ __entry->src_x = pipe->src.x;
+ __entry->src_y = pipe->src.y;
+ __entry->src_w = pipe->src.w;
+ __entry->src_h = pipe->src.h;
+ __entry->dst_x = pipe->dst.x;
+ __entry->dst_y = pipe->dst.y;
+ __entry->dst_w = pipe->dst.w;
+ __entry->dst_h = pipe->dst.h;
+ ),
+
+ TP_printk("num=%d mixer=%d play_cnt=%d flags=0x%x stage=%d format=%d img=%dx%d src=[%d,%d,%d,%d] dst=[%d,%d,%d,%d]",
+ __entry->num, __entry->mixer, __entry->play_cnt,
+ __entry->flags, __entry->stage,
+ __entry->format, __entry->img_w, __entry->img_h,
+ __entry->src_x, __entry->src_y,
+ __entry->src_w, __entry->src_h,
+ __entry->dst_x, __entry->dst_y,
+ __entry->dst_w, __entry->dst_h)
+);
+
+DEFINE_EVENT(mdp_sspp_template, mdp_sspp_set,
+ TP_PROTO(struct mdss_mdp_pipe *pipe),
+ TP_ARGS(pipe)
+);
+
+DEFINE_EVENT(mdp_sspp_template, mdp_sspp_change,
+ TP_PROTO(struct mdss_mdp_pipe *pipe),
+ TP_ARGS(pipe)
+);
+
+TRACE_EVENT(mdp_mixer_update,
+ TP_PROTO(u32 mixer_num),
+ TP_ARGS(mixer_num),
+ TP_STRUCT__entry(
+ __field(u32, mixer_num)
+ ),
+ TP_fast_assign(
+ __entry->mixer_num = mixer_num;
+ ),
+ TP_printk("mixer=%d",
+ __entry->mixer_num)
+);
+
+TRACE_EVENT(mdp_commit,
+ TP_PROTO(struct mdss_mdp_ctl *ctl),
+ TP_ARGS(ctl),
+ TP_STRUCT__entry(
+ __field(u32, num)
+ __field(u32, play_cnt)
+ __field(u32, clk_rate)
+ __field(u64, bandwidth)
+ ),
+ TP_fast_assign(
+ __entry->num = ctl->num;
+ __entry->play_cnt = ctl->play_cnt;
+ __entry->clk_rate = ctl->new_perf.mdp_clk_rate;
+ __entry->bandwidth = ctl->new_perf.bw_ctl;
+ ),
+ TP_printk("num=%d play_cnt=%d bandwidth=%llu clk_rate=%u",
+ __entry->num,
+ __entry->play_cnt,
+ __entry->bandwidth,
+ __entry->clk_rate)
+);
+
+TRACE_EVENT(mdp_video_underrun_done,
+ TP_PROTO(u32 ctl_num, u32 underrun_cnt),
+ TP_ARGS(ctl_num, underrun_cnt),
+ TP_STRUCT__entry(
+ __field(u32, ctl_num)
+ __field(u32, underrun_cnt)
+ ),
+ TP_fast_assign(
+ __entry->ctl_num = ctl_num;
+ __entry->underrun_cnt = underrun_cnt;
+ ),
+ TP_printk("ctl=%d count=%d",
+ __entry->ctl_num, __entry->underrun_cnt)
+);
+
+TRACE_EVENT(mdp_perf_update_bus,
+ TP_PROTO(unsigned long long ab_quota, unsigned long long ib_quota),
+ TP_ARGS(ab_quota, ib_quota),
+ TP_STRUCT__entry(
+ __field(u64, ab_quota)
+ __field(u64, ib_quota)
+ ),
+ TP_fast_assign(
+ __entry->ab_quota = ab_quota;
+ __entry->ib_quota = ib_quota;
+ ),
+ TP_printk("ab=%llu ib=%llu",
+ __entry->ab_quota,
+ __entry->ib_quota)
+);
+
+TRACE_EVENT(mdp_cmd_pingpong_done,
+ TP_PROTO(struct mdss_mdp_ctl *ctl, u32 pp_num, int koff_cnt),
+ TP_ARGS(ctl, pp_num, koff_cnt),
+ TP_STRUCT__entry(
+ __field(u32, ctl_num)
+ __field(u32, intf_num)
+ __field(u32, pp_num)
+ __field(int, koff_cnt)
+ ),
+ TP_fast_assign(
+ __entry->ctl_num = ctl->num;
+ __entry->intf_num = ctl->intf_num;
+ __entry->pp_num = pp_num;
+ __entry->koff_cnt = koff_cnt;
+ ),
+ TP_printk("ctl num:%d intf_num:%d ctx:%d kickoff:%d",
+ __entry->ctl_num, __entry->intf_num, __entry->pp_num,
+ __entry->koff_cnt)
+);
+
+TRACE_EVENT(mdp_cmd_release_bw,
+ TP_PROTO(u32 ctl_num),
+ TP_ARGS(ctl_num),
+ TP_STRUCT__entry(
+ __field(u32, ctl_num)
+ ),
+ TP_fast_assign(
+ __entry->ctl_num = ctl_num;
+ ),
+ TP_printk("ctl num:%d", __entry->ctl_num)
+);
+
+TRACE_EVENT(mdp_cmd_kickoff,
+ TP_PROTO(u32 ctl_num, int kickoff_cnt),
+ TP_ARGS(ctl_num, kickoff_cnt),
+ TP_STRUCT__entry(
+ __field(u32, ctl_num)
+ __field(int, kickoff_cnt)
+ ),
+ TP_fast_assign(
+ __entry->ctl_num = ctl_num;
+ __entry->kickoff_cnt = kickoff_cnt;
+ ),
+ TP_printk("kickoff ctl=%d cnt=%d",
+ __entry->ctl_num,
+ __entry->kickoff_cnt)
+);
+
+TRACE_EVENT(mdp_cmd_wait_pingpong,
+ TP_PROTO(u32 ctl_num, int kickoff_cnt),
+ TP_ARGS(ctl_num, kickoff_cnt),
+ TP_STRUCT__entry(
+ __field(u32, ctl_num)
+ __field(int, kickoff_cnt)
+ ),
+ TP_fast_assign(
+ __entry->ctl_num = ctl_num;
+ __entry->kickoff_cnt = kickoff_cnt;
+ ),
+ TP_printk("pingpong ctl=%d cnt=%d",
+ __entry->ctl_num,
+ __entry->kickoff_cnt)
+);
+
+#endif /* if !defined(TRACE_MDSS_MDP_H) || defined(TRACE_HEADER_MULTI_READ) */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/drivers/video/msm/mdss/mdss_mdp_util.c b/drivers/video/msm/mdss/mdss_mdp_util.c
index 69506d4..9336582 100644
--- a/drivers/video/msm/mdss/mdss_mdp_util.c
+++ b/drivers/video/msm/mdss/mdss_mdp_util.c
@@ -320,7 +320,7 @@
}
int mdss_mdp_get_plane_sizes(u32 format, u32 w, u32 h,
- struct mdss_mdp_plane_sizes *ps, u32 bwc_mode)
+ struct mdss_mdp_plane_sizes *ps, u32 bwc_mode, bool rotation)
{
struct mdss_mdp_format_params *fmt;
int i, rc;
@@ -374,9 +374,19 @@
u8 hmap[] = { 1, 2, 1, 2 };
u8 vmap[] = { 1, 1, 2, 2 };
u8 horiz, vert, stride_align, height_align;
+ u32 chroma_samp;
- horiz = hmap[fmt->chroma_sample];
- vert = vmap[fmt->chroma_sample];
+ chroma_samp = fmt->chroma_sample;
+
+ if (rotation) {
+ if (chroma_samp == MDSS_MDP_CHROMA_H2V1)
+ chroma_samp = MDSS_MDP_CHROMA_H1V2;
+ else if (chroma_samp == MDSS_MDP_CHROMA_H1V2)
+ chroma_samp = MDSS_MDP_CHROMA_H2V1;
+ }
+
+ horiz = hmap[chroma_samp];
+ vert = vmap[chroma_samp];
switch (format) {
case MDP_Y_CR_CB_GH2V2:
diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h
index 18513e3..74f6714 100644
--- a/include/linux/dma-attrs.h
+++ b/include/linux/dma-attrs.h
@@ -17,6 +17,7 @@
DMA_ATTR_NON_CONSISTENT,
DMA_ATTR_NO_KERNEL_MAPPING,
DMA_ATTR_STRONGLY_ORDERED,
+ DMA_ATTR_SKIP_ZEROING,
DMA_ATTR_MAX,
};
diff --git a/include/linux/dma-contiguous.h b/include/linux/dma-contiguous.h
index 78e57cd..9975eef 100644
--- a/include/linux/dma-contiguous.h
+++ b/include/linux/dma-contiguous.h
@@ -73,7 +73,8 @@
void dma_contiguous_reserve(phys_addr_t addr_limit);
int dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t *res_base,
- phys_addr_t limit, const char *name);
+ phys_addr_t limit, const char *name,
+ bool in_system);
int dma_contiguous_add_device(struct device *dev, phys_addr_t base);
@@ -94,7 +95,19 @@
phys_addr_t base, phys_addr_t limit)
{
int ret;
- ret = dma_contiguous_reserve_area(size, &base, limit, NULL);
+ ret = dma_contiguous_reserve_area(size, &base, limit, NULL, true);
+ if (ret == 0)
+ ret = dma_contiguous_add_device(dev, base);
+ return ret;
+}
+
+static inline int dma_declare_contiguous_reserved(struct device *dev,
+ phys_addr_t size,
+ phys_addr_t base,
+ phys_addr_t limit)
+{
+ int ret;
+ ret = dma_contiguous_reserve_area(size, &base, limit, NULL, false);
if (ret == 0)
ret = dma_contiguous_add_device(dev, base);
return ret;
diff --git a/include/linux/mfd/wcd9xxx/core.h b/include/linux/mfd/wcd9xxx/core.h
index 85be7c3..a8e792b 100644
--- a/include/linux/mfd/wcd9xxx/core.h
+++ b/include/linux/mfd/wcd9xxx/core.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -133,6 +133,7 @@
u16 grph; /* slimbus group handle */
unsigned long ch_mask;
wait_queue_head_t dai_wait;
+ bool bus_down_in_recovery;
};
#define WCD9XXX_CH(xport, xshift) \
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 65a3fe1..9bdf508 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -113,39 +113,37 @@
* be called twice.
*/
#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<2)
-/* Ignore CMD CRC errors for tuning commands */
-#define SDHCI_QUIRK2_IGNORE_CMDCRC_FOR_TUNING (1<<3)
/*
* If the base clock can be scalable, then there should be no further
* clock dividing as the input clock itself will be scaled down to
* required frequency.
*/
-#define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK (1<<4)
+#define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK (1<<3)
/*
* Dont use the max_discard_to in sdhci driver so that the maximum discard
* unit gets picked by the mmc queue. Otherwise, it takes a long time for
* secure discard kind of operations to complete.
*/
-#define SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE (1<<5)
+#define SDHCI_QUIRK2_USE_MAX_DISCARD_SIZE (1<<4)
/*
* Ignore data timeout error for R1B commands as there will be no
* data associated and the busy timeout value for these commands
* could be lager than the maximum timeout value that controller
* can handle.
*/
-#define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD (1<<6)
+#define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD (1<<5)
/*
* The preset value registers are not properly initialized by
* some hardware and hence preset value must not be enabled for
* such controllers.
*/
-#define SDHCI_QUIRK2_BROKEN_PRESET_VALUE (1<<7)
+#define SDHCI_QUIRK2_BROKEN_PRESET_VALUE (1<<6)
/*
* Some controllers define the usage of 0xF in data timeout counter
* register (0x2E) which is actually a reserved bit as per
* specification.
*/
-#define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT (1<<8)
+#define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT (1<<7)
/*
* This is applicable for controllers that advertize timeout clock
* value in capabilities register (bit 5-0) as just 50MHz whereas the
@@ -158,7 +156,7 @@
* will be used in such cases to avoid controller mulplication when timeout is
* calculated based on the base clock.
*/
-#define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 (1 << 9)
+#define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 (1 << 8)
/*
* Some SDHC controllers are unable to handle data-end bit error in
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index 7ba4148..52195c1 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -840,6 +840,7 @@
enum qpnp_adc_meas_timer_2 meas_interval2;
enum qpnp_adc_tm_channel_select tm_channel_select;
enum qpnp_state_request state_request;
+ enum qpnp_adc_calib_type calib_type;
struct qpnp_vadc_linear_graph adc_graph[2];
};
@@ -883,6 +884,7 @@
enum qpnp_adc_scale_fn_type adc_scale_fn;
enum qpnp_adc_fast_avg_ctl fast_avg_setup;
enum qpnp_adc_hw_settle_time hw_settle_time;
+ enum qpnp_adc_calib_type calib_type;
};
/**
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 4ecacc7..44fe134 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -191,6 +191,20 @@
};
/**
+ * Maintain state for hvdcp external charger status
+ * DEFAULT This is used when DCP is detected
+ * ACTIVE This is used when ioctl is called to block LPM
+ * INACTIVE This is used when ioctl is called to unblock LPM
+ */
+
+enum usb_ext_chg_status {
+ DEFAULT = 1,
+ ACTIVE,
+ INACTIVE,
+};
+
+
+/**
* struct msm_otg_platform_data - platform device data
* for msm_otg driver.
* @phy_init_seq: PHY configuration sequence. val, reg pairs
@@ -463,7 +477,7 @@
struct class *ext_chg_class;
struct device *ext_chg_device;
bool ext_chg_opened;
- bool ext_chg_active;
+ enum usb_ext_chg_status ext_chg_active;
struct completion ext_chg_wait;
int ui_enabled;
bool pm_done;
diff --git a/include/media/msm_cam_sensor.h b/include/media/msm_cam_sensor.h
index 46cec76..b1b54cb 100644
--- a/include/media/msm_cam_sensor.h
+++ b/include/media/msm_cam_sensor.h
@@ -40,10 +40,14 @@
#define MAX_ACTUATOR_REGION 5
#define MAX_ACTUATOR_INIT_SET 12
#define MAX_ACTUATOR_REG_TBL_SIZE 8
+#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024
#define MOVE_NEAR 0
#define MOVE_FAR 1
+#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1
+#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1
+
#define MAX_EEPROM_NAME 32
#define MAX_AF_ITERATIONS 3
diff --git a/include/media/msm_media_info.h b/include/media/msm_media_info.h
index 663809e..d46b505 100644
--- a/include/media/msm_media_info.h
+++ b/include/media/msm_media_info.h
@@ -79,6 +79,18 @@
COLOR_FMT_NV21,
};
+static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height)
+{
+ (void)height;
+ (void)width;
+
+ /*
+ * In the future, calculate the size based on the w/h but just
+ * hardcode it for now since 8K satisfies all current usecases.
+ */
+ return 8 * 1024;
+}
+
static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width)
{
unsigned int alignment, stride = 0;
@@ -158,7 +170,7 @@
static inline unsigned int VENUS_BUFFER_SIZE(
int color_fmt, int width, int height)
{
- const unsigned int extra_size = 8*1024;
+ const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height);
unsigned int uv_alignment = 0, size = 0;
unsigned int y_plane, uv_plane, y_stride,
uv_stride, y_sclines, uv_sclines;
diff --git a/include/media/msmb_isp.h b/include/media/msmb_isp.h
index 3828221..30e7d06 100644
--- a/include/media/msmb_isp.h
+++ b/include/media/msmb_isp.h
@@ -240,6 +240,8 @@
VFE_READ_DMI_64BIT,
GET_SOC_HW_VER,
GET_MAX_CLK_RATE,
+ VFE_HW_UPDATE_LOCK,
+ VFE_HW_UPDATE_UNLOCK,
};
struct msm_vfe_cfg_cmd2 {
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index 2a89d01..61d82fb 100644
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
@@ -374,7 +374,7 @@
#endif
}
-static int unix_release_sock(struct sock *sk, int embrion)
+static void unix_release_sock(struct sock *sk, int embrion)
{
struct unix_sock *u = unix_sk(sk);
struct path path;
@@ -443,8 +443,6 @@
if (unix_tot_inflight)
unix_gc(); /* Garbage collect fds */
-
- return 0;
}
static void init_peercred(struct sock *sk)
@@ -694,9 +692,10 @@
if (!sk)
return 0;
+ unix_release_sock(sk, 0);
sock->sk = NULL;
- return unix_release_sock(sk, 0);
+ return 0;
}
static int unix_autobind(struct socket *sock)
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index c3adef8..cf82dbd 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -6780,9 +6780,11 @@
data = nla_data(info->attrs[NL80211_ATTR_VENDOR_DATA]);
len = nla_len(info->attrs[NL80211_ATTR_VENDOR_DATA]);
}
-
- return rdev->wiphy.vendor_commands[i].doit(&rdev->wiphy, wdev,
+ rdev->cur_cmd_info = info;
+ err = rdev->wiphy.vendor_commands[i].doit(&rdev->wiphy, wdev,
data, len);
+ rdev->cur_cmd_info = NULL;
+ return err;
}
return -EOPNOTSUPP;
diff --git a/sound/soc/codecs/msm_hdmi_codec_rx.c b/sound/soc/codecs/msm_hdmi_codec_rx.c
index 9cf37b4..5223070 100644
--- a/sound/soc/codecs/msm_hdmi_codec_rx.c
+++ b/sound/soc/codecs/msm_hdmi_codec_rx.c
@@ -84,7 +84,7 @@
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
- int rv;
+ int rv = 0;
struct msm_hdmi_audio_codec_rx_data *codec_data =
dev_get_drvdata(dai->codec->dev);
@@ -92,7 +92,13 @@
codec_data->hdmi_core_pdev, 1);
if (IS_ERR_VALUE(rv)) {
dev_err(dai->dev,
- "%s() HDMI core is not ready\n", __func__);
+ "%s() HDMI core is not ready (rv = %d)\n",
+ __func__, rv);
+ } else if (!rv) {
+ dev_err(dai->dev,
+ "%s() HDMI cable is not connected (ret val = %d)\n",
+ __func__, rv);
+ rv = -EAGAIN;
}
return rv;
@@ -116,8 +122,14 @@
codec_data->hdmi_core_pdev, 1);
if (IS_ERR_VALUE(rv)) {
dev_err(dai->dev,
- "%s() HDMI core is not ready\n", __func__);
+ "%s() HDMI core is not ready (rv = %d)\n",
+ __func__, rv);
return rv;
+ } else if (!rv) {
+ dev_err(dai->dev,
+ "%s() HDMI cable is not connected (rv = %d)\n",
+ __func__, rv);
+ return -EAGAIN;
}
switch (num_channels) {
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
index 61a0682..38d7901 100644
--- a/sound/soc/codecs/wcd9306.c
+++ b/sound/soc/codecs/wcd9306.c
@@ -4154,6 +4154,7 @@
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ dai->bus_down_in_recovery = false;
(void) tapan_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -4162,7 +4163,8 @@
case SND_SOC_DAPM_POST_PMD:
ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
dai->grph);
- ret = tapan_codec_enable_slim_chmask(dai, false);
+ if (!dai->bus_down_in_recovery)
+ ret = tapan_codec_enable_slim_chmask(dai, false);
if (ret < 0) {
ret = wcd9xxx_disconnect_port(core,
&dai->wcd9xxx_ch_list,
@@ -4177,6 +4179,7 @@
pm_runtime_put(core->dev->parent);
dev_dbg(codec->dev, "%s: unvote requested", __func__);
}
+ dai->bus_down_in_recovery = false;
break;
}
return ret;
@@ -4208,6 +4211,7 @@
dai = &tapan_p->dai[w->shift];
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ dai->bus_down_in_recovery = false;
(void) tapan_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -4216,7 +4220,8 @@
case SND_SOC_DAPM_POST_PMD:
ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->grph);
- ret = tapan_codec_enable_slim_chmask(dai, false);
+ if (!dai->bus_down_in_recovery)
+ ret = tapan_codec_enable_slim_chmask(dai, false);
if (ret < 0) {
ret = wcd9xxx_disconnect_port(core,
&dai->wcd9xxx_ch_list,
@@ -4231,6 +4236,7 @@
pm_runtime_put(core->dev->parent);
dev_dbg(codec->dev, "%s: unvote requested", __func__);
}
+ dai->bus_down_in_recovery = false;
break;
}
return ret;
@@ -5732,6 +5738,7 @@
int rco_clk_rate;
struct snd_soc_codec *codec;
struct tapan_priv *tapan;
+ int count;
codec = (struct snd_soc_codec *)(wcd9xxx->ssr_priv);
tapan = snd_soc_codec_get_drvdata(codec);
@@ -5788,6 +5795,9 @@
tapan->machine_codec_event_cb(codec, WCD9XXX_CODEC_EVENT_CODEC_UP);
+ for (count = 0; count < NUM_CODEC_DAIS; count++)
+ tapan->dai[count].bus_down_in_recovery = true;
+
mutex_unlock(&codec->mutex);
return ret;
}
diff --git a/sound/soc/codecs/wcd9320.c b/sound/soc/codecs/wcd9320.c
index 2b0c9d3..4c5d327 100644
--- a/sound/soc/codecs/wcd9320.c
+++ b/sound/soc/codecs/wcd9320.c
@@ -5144,6 +5144,7 @@
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ dai->bus_down_in_recovery = false;
taiko_codec_enable_int_port(dai, codec);
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
@@ -5153,7 +5154,9 @@
case SND_SOC_DAPM_POST_PMD:
ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
dai->grph);
- ret = taiko_codec_enable_slim_chmask(dai, false);
+ if (!dai->bus_down_in_recovery)
+ ret = taiko_codec_enable_slim_chmask(dai, false);
+
if (ret < 0) {
ret = wcd9xxx_disconnect_port(core,
&dai->wcd9xxx_ch_list,
@@ -5161,6 +5164,7 @@
pr_debug("%s: Disconnect RX port, ret = %d\n",
__func__, ret);
}
+ dai->bus_down_in_recovery = false;
break;
}
return ret;
@@ -5210,6 +5214,7 @@
snd_soc_update_bits(codec,
TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL, 0xC, 0xC);
taiko_codec_enable_int_port(dai, codec);
+ dai->bus_down_in_recovery = false;
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -5226,6 +5231,8 @@
/*Disable V&I sensing*/
snd_soc_update_bits(codec, TAIKO_A_SPKR_PROT_EN,
0x88, 0x00);
+
+ dai->bus_down_in_recovery = false;
break;
}
out_vi:
@@ -5255,9 +5262,11 @@
__func__, w->name, event, w->shift);
dai = &taiko_p->dai[w->shift];
+
switch (event) {
case SND_SOC_DAPM_POST_PMU:
taiko_codec_enable_int_port(dai, codec);
+ dai->bus_down_in_recovery = false;
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -5266,7 +5275,9 @@
case SND_SOC_DAPM_POST_PMD:
ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->grph);
- ret = taiko_codec_enable_slim_chmask(dai, false);
+ if (!dai->bus_down_in_recovery)
+ ret = taiko_codec_enable_slim_chmask(dai, false);
+
if (ret < 0) {
ret = wcd9xxx_disconnect_port(core,
&dai->wcd9xxx_ch_list,
@@ -5274,6 +5285,8 @@
pr_debug("%s: Disconnect RX port, ret = %d\n",
__func__, ret);
}
+
+ dai->bus_down_in_recovery = false;
break;
}
return ret;
@@ -6485,6 +6498,9 @@
/* set MAD input MIC to DMIC1 */
{TAIKO_A_CDC_CONN_MAD, 0x0F, 0x08},
+
+ /* set DMIC CLK drive strength to 4mA */
+ {TAIKO_A_HDRIVE_OVERRIDE, 0x07, 0x01},
};
static void taiko_codec_init_reg(struct snd_soc_codec *codec)
@@ -6807,6 +6823,7 @@
struct snd_soc_codec *codec;
struct taiko_priv *taiko;
int rco_clk_rate;
+ int count;
codec = (struct snd_soc_codec *)(wcd9xxx->ssr_priv);
taiko = snd_soc_codec_get_drvdata(codec);
@@ -6863,6 +6880,9 @@
if (ret)
pr_err("%s: Failed to setup irq: %d\n", __func__, ret);
+ for (count = 0; count < NUM_CODEC_DAIS; count++)
+ taiko->dai[count].bus_down_in_recovery = true;
+
mutex_unlock(&codec->mutex);
return ret;
}
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index 34cb21a..8a71891 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -884,7 +884,8 @@
0, WCD9XXX_JACK_MASK);
mbhc->hph_status &= ~(SND_JACK_HEADSET |
SND_JACK_LINEOUT |
- SND_JACK_ANC_HEADPHONE);
+ SND_JACK_ANC_HEADPHONE |
+ SND_JACK_UNSUPPORTED);
}
/* Report insertion */
@@ -3050,11 +3051,14 @@
if (!mbhc->mbhc_cfg->detect_extn_cable &&
retry == NUM_ATTEMPTS_TO_REPORT &&
mbhc->current_plug == PLUG_TYPE_NONE) {
+ WCD9XXX_BCL_LOCK(mbhc->resmgr);
wcd9xxx_report_plug(mbhc, 1,
SND_JACK_HEADPHONE);
+ WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
}
} else if (plug_type == PLUG_TYPE_HEADPHONE) {
pr_debug("Good headphone detected, continue polling\n");
+ WCD9XXX_BCL_LOCK(mbhc->resmgr);
if (mbhc->mbhc_cfg->detect_extn_cable) {
if (mbhc->current_plug != plug_type)
wcd9xxx_report_plug(mbhc, 1,
@@ -3063,9 +3067,11 @@
wcd9xxx_report_plug(mbhc, 1,
SND_JACK_HEADPHONE);
}
+ WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
} else if (plug_type == PLUG_TYPE_HIGH_HPH) {
pr_debug("%s: High HPH detected, continue polling\n",
__func__);
+ WCD9XXX_BCL_LOCK(mbhc->resmgr);
if (mbhc->mbhc_cfg->detect_extn_cable) {
if (mbhc->current_plug != plug_type)
wcd9xxx_report_plug(mbhc, 1,
@@ -3074,6 +3080,7 @@
wcd9xxx_report_plug(mbhc, 1,
SND_JACK_HEADPHONE);
}
+ WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
} else {
if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
pt_gnd_mic_swap_cnt++;
@@ -3499,6 +3506,7 @@
pr_debug("%s: enter\n", __func__);
WCD9XXX_BCL_LOCK(mbhc->resmgr);
+ mutex_lock(&mbhc->mbhc_lock);
mbhc_status = snd_soc_read(codec, WCD9XXX_A_CDC_MBHC_B1_STATUS) & 0x3E;
if (mbhc->mbhc_state == MBHC_STATE_POTENTIAL_RECOVERY) {
@@ -3671,6 +3679,7 @@
done:
pr_debug("%s: leave\n", __func__);
+ mutex_unlock(&mbhc->mbhc_lock);
WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
return IRQ_HANDLED;
}
@@ -4518,6 +4527,7 @@
pr_debug("%s: enter event %s(%d)\n", __func__,
wcd9xxx_get_event_string(event), event);
+ mutex_lock(&mbhc->mbhc_lock);
switch (event) {
/* MICBIAS usage change */
case WCD9XXX_EVENT_PRE_MICBIAS_1_ON:
@@ -4711,6 +4721,7 @@
WARN(1, "Unknown event %d\n", event);
ret = -EINVAL;
}
+ mutex_unlock(&mbhc->mbhc_lock);
pr_debug("%s: leave\n", __func__);
@@ -4920,17 +4931,19 @@
wcd9xxx_mbhc_insert_work);
}
+ mutex_init(&mbhc->mbhc_lock);
+
/* Register event notifier */
mbhc->nblock.notifier_call = wcd9xxx_event_notify;
ret = wcd9xxx_resmgr_register_notifier(mbhc->resmgr, &mbhc->nblock);
if (ret) {
pr_err("%s: Failed to register notifier %d\n", __func__, ret);
+ mutex_destroy(&mbhc->mbhc_lock);
return ret;
}
wcd9xxx_init_debugfs(mbhc);
-
/* Disable Impedance detection by default for certain codec types */
if (mbhc->mbhc_cb &&
mbhc->mbhc_cb->get_cdc_type() == WCD9XXX_CDC_TYPE_HELICON)
@@ -5015,6 +5028,8 @@
err_insert_irq:
wcd9xxx_resmgr_unregister_notifier(mbhc->resmgr, &mbhc->nblock);
+ mutex_destroy(&mbhc->mbhc_lock);
+
pr_debug("%s: leave ret %d\n", __func__, ret);
return ret;
}
@@ -5036,6 +5051,7 @@
wcd9xxx_free_irq(core_res, mbhc->intr_ids->hph_left_ocp, mbhc);
wcd9xxx_free_irq(core_res, mbhc->intr_ids->hph_right_ocp, mbhc);
+ mutex_destroy(&mbhc->mbhc_lock);
wcd9xxx_resmgr_unregister_notifier(mbhc->resmgr, &mbhc->nblock);
wcd9xxx_cleanup_debugfs(mbhc);
}
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.h b/sound/soc/codecs/wcd9xxx-mbhc.h
index cf25798..91edaca 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.h
+++ b/sound/soc/codecs/wcd9xxx-mbhc.h
@@ -368,6 +368,8 @@
struct dentry *debugfs_poke;
struct dentry *debugfs_mbhc;
#endif
+
+ struct mutex mbhc_lock;
};
#define WCD9XXX_MBHC_CAL_SIZE(buttons, rload) ( \
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index 9c01a08..23ed60a 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -46,6 +46,7 @@
#define BTSCO_RATE_16KHZ 16000
static int slim0_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE;
+static int slim0_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE;
static int hdmi_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE;
#define SAMPLING_RATE_48KHZ 48000
@@ -1318,7 +1319,7 @@
pr_debug("%s()\n", __func__);
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
- slim0_rx_bit_format);
+ slim0_tx_bit_format);
rate->min = rate->max = 48000;
channels->min = channels->max = msm_slim_0_tx_ch;
@@ -2412,6 +2413,21 @@
.ignore_pmdown_time = 1,
.be_id = MSM_FRONTEND_DAI_MULTIMEDIA9,
},
+ {
+ .name = "VoWLAN",
+ .stream_name = "VoWLAN",
+ .cpu_dai_name = "VoWLAN",
+ .platform_name = "msm-pcm-voice",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .be_id = MSM_FRONTEND_DAI_VOWLAN,
+ },
/* Backend BT/FM DAI Links */
{
.name = LPASS_BE_INT_BT_SCO_RX,
diff --git a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
index cdfd042..aa4d88d 100644
--- a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
@@ -545,12 +545,6 @@
int dir = IN, ret = 0;
struct audio_client *ac = prtd->audio_client;
uint32_t stream_index;
- struct asm_softpause_params softpause = {
- .enable = SOFT_PAUSE_ENABLE,
- .period = SOFT_PAUSE_PERIOD,
- .step = SOFT_PAUSE_STEP,
- .rampingcurve = SOFT_PAUSE_CURVE_LINEAR,
- };
struct asm_softvolume_params softvol = {
.period = SOFT_VOLUME_PERIOD,
.step = SOFT_VOLUME_STEP,
@@ -584,11 +578,6 @@
if (ret < 0)
pr_err("%s : Set Volume failed : %d", __func__, ret);
- ret = q6asm_set_softpause(ac, &softpause);
- if (ret < 0)
- pr_err("%s: Send SoftPause Param failed ret=%d\n",
- __func__, ret);
-
ret = q6asm_set_softvolume(ac, &softvol);
if (ret < 0)
pr_err("%s: Send SoftVolume Param failed ret=%d\n",
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
index 08448fe..b49ce46 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
@@ -31,6 +31,7 @@
#include <linux/msm_audio_ion.h>
#include <linux/of_device.h>
+#include <sound/tlv.h>
#include <sound/pcm_params.h>
#include "msm-pcm-q6-v2.h"
@@ -38,6 +39,10 @@
static struct audio_locks the_locks;
+#define PCM_MASTER_VOL_MAX_STEPS 0x2000
+static const DECLARE_TLV_DB_LINEAR(msm_pcm_vol_gain, 0,
+ PCM_MASTER_VOL_MAX_STEPS);
+
struct snd_msm {
struct snd_card *card;
struct snd_pcm *pcm;
@@ -819,6 +824,94 @@
.mmap = msm_pcm_mmap,
};
+static int msm_pcm_set_volume(struct msm_audio *prtd, uint32_t volume)
+{
+ int rc = 0;
+
+ if (prtd && prtd->audio_client) {
+ pr_debug("%s: channels %d volume 0x%x\n", __func__,
+ prtd->channel_mode, volume);
+ rc = q6asm_set_volume(prtd->audio_client, volume);
+ if (rc < 0) {
+ pr_err("%s: Send Volume command failed rc=%d\n",
+ __func__, rc);
+ }
+ }
+ return rc;
+}
+
+static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol);
+ struct snd_pcm_substream *substream =
+ vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+ struct msm_audio *prtd;
+
+ pr_debug("%s\n", __func__);
+ if (!substream) {
+ pr_err("%s substream not found\n", __func__);
+ return -ENODEV;
+ }
+ if (!substream->runtime) {
+ pr_err("%s substream runtime not found\n", __func__);
+ return 0;
+ }
+ prtd = substream->runtime->private_data;
+ if (prtd)
+ ucontrol->value.integer.value[0] = prtd->volume;
+ return 0;
+}
+
+static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int rc = 0;
+ struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol);
+ struct snd_pcm_substream *substream =
+ vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+ struct msm_audio *prtd;
+ int volume = ucontrol->value.integer.value[0];
+
+ pr_debug("%s: volume : 0x%x\n", __func__, volume);
+ if (!substream) {
+ pr_err("%s substream not found\n", __func__);
+ return -ENODEV;
+ }
+ if (!substream->runtime) {
+ pr_err("%s substream runtime not found\n", __func__);
+ return 0;
+ }
+ prtd = substream->runtime->private_data;
+ if (prtd) {
+ rc = msm_pcm_set_volume(prtd, volume);
+ prtd->volume = volume;
+ }
+ return rc;
+}
+
+static int msm_pcm_add_volume_control(struct snd_soc_pcm_runtime *rtd)
+{
+ int ret = 0;
+ struct snd_pcm *pcm = rtd->pcm;
+ struct snd_pcm_volume *volume_info;
+ struct snd_kcontrol *kctl;
+
+ dev_dbg(rtd->dev, "%s, Volume control add\n", __func__);
+ ret = snd_pcm_add_volume_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
+ NULL, 1, rtd->dai_link->be_id,
+ &volume_info);
+ if (ret < 0) {
+ pr_err("%s volume control failed ret %d\n", __func__, ret);
+ return ret;
+ }
+ kctl = volume_info->kctl;
+ kctl->put = msm_pcm_volume_ctl_put;
+ kctl->get = msm_pcm_volume_ctl_get;
+ kctl->tlv.p = msm_pcm_vol_gain;
+ return 0;
+}
+
static int msm_pcm_chmap_ctl_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
@@ -905,6 +998,10 @@
__func__, kctl->id.name);
kctl->put = msm_pcm_chmap_ctl_put;
kctl->get = msm_pcm_chmap_ctl_get;
+ ret = msm_pcm_add_volume_control(rtd);
+ if (ret)
+ pr_err("%s: Could not add pcm Volume Control %d\n",
+ __func__, ret);
return ret;
}
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
index a5c8f8d..4893990 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
@@ -1419,34 +1419,45 @@
struct snd_ctl_elem_value *ucontrol)
{
int ec_ref_port_id;
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ int mux = ucontrol->value.enumerated.item[0];
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+
mutex_lock(&routing_lock);
switch (ucontrol->value.integer.value[0]) {
case 0:
msm_route_ec_ref_rx = 0;
- ec_ref_port_id = SLIMBUS_0_RX;
+ ec_ref_port_id = AFE_PORT_INVALID;
break;
case 1:
msm_route_ec_ref_rx = 1;
- ec_ref_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
+ ec_ref_port_id = SLIMBUS_0_RX;
break;
case 2:
msm_route_ec_ref_rx = 2;
- ec_ref_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
+ ec_ref_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
break;
case 3:
msm_route_ec_ref_rx = 3;
- ec_ref_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
+ ec_ref_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
break;
case 4:
msm_route_ec_ref_rx = 4;
- ec_ref_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
+ ec_ref_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
break;
case 5:
msm_route_ec_ref_rx = 5;
+ ec_ref_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
+ break;
+ case 6:
+ msm_route_ec_ref_rx = 6;
ec_ref_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
break;
default:
- msm_route_ec_ref_rx = 6; /* NONE */
+ msm_route_ec_ref_rx = 0; /* NONE */
+ pr_err("%s EC ref rx %ld not valid\n",
+ __func__, ucontrol->value.integer.value[0]);
ec_ref_port_id = AFE_PORT_INVALID;
break;
}
@@ -1454,11 +1465,13 @@
pr_debug("%s: msm_route_ec_ref_rx = %d\n",
__func__, msm_route_ec_ref_rx);
mutex_unlock(&routing_lock);
+ snd_soc_dapm_mux_update_power(widget, kcontrol, 1, mux, e);
return 0;
}
-static const char *const ec_ref_rx[] = { "SLIM_RX", "I2S_RX", "PRI_MI2S_TX",
- "SEC_MI2S_TX", "TERT_MI2S_TX", "QUAT_MI2S_TX", "PROXY_RX", "NONE"};
+static const char *const ec_ref_rx[] = { "None", "SLIM_RX", "I2S_RX",
+ "PRI_MI2S_TX",
+ "SEC_MI2S_TX", "TERT_MI2S_TX", "QUAT_MI2S_TX", "PROXY_RX"};
static const struct soc_enum msm_route_ec_ref_rx_enum[] = {
SOC_ENUM_SINGLE_EXT(8, ec_ref_rx),
};