msm: clock: Use device names to distinguish between USB clocks
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name. Clock names
are updated to match the new naming convention.
CRs-Fixed: 327559
Change-Id: I78757806589e037a0655a63e7ee20c935214c99d
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index eb0b203..af7f2cf 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -1,6 +1,6 @@
/* ehci-msm-hsic.c - HSUSB Host Controller Driver Implementation
*
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* Partly derived from ehci-fsl.c and ehci-hcd.c
* Copyright (c) 2000-2004 by David Brownell
@@ -43,9 +43,9 @@
struct ehci_hcd ehci;
struct device *dev;
struct clk *ahb_clk;
- struct clk *sys_clk;
- struct clk *fs_xcvr_clk;
- struct clk *hsic_clk;
+ struct clk *core_clk;
+ struct clk *alt_core_clk;
+ struct clk *phy_clk;
struct clk *cal_clk;
struct regulator *hsic_vddcx;
bool async_int;
@@ -270,18 +270,18 @@
{
int ret;
- clk_enable(mehci->fs_xcvr_clk);
+ clk_enable(mehci->alt_core_clk);
- ret = clk_reset(mehci->sys_clk, CLK_RESET_ASSERT);
+ ret = clk_reset(mehci->core_clk, CLK_RESET_ASSERT);
if (ret) {
- clk_disable(mehci->fs_xcvr_clk);
+ clk_disable(mehci->alt_core_clk);
dev_err(mehci->dev, "usb phy clk assert failed\n");
return ret;
}
usleep_range(10000, 12000);
- clk_disable(mehci->fs_xcvr_clk);
+ clk_disable(mehci->alt_core_clk);
- ret = clk_reset(mehci->sys_clk, CLK_RESET_DEASSERT);
+ ret = clk_reset(mehci->core_clk, CLK_RESET_DEASSERT);
if (ret)
dev_err(mehci->dev, "usb phy clk deassert failed\n");
@@ -423,8 +423,8 @@
*/
mb();
- clk_disable(mehci->sys_clk);
- clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->core_clk);
+ clk_disable(mehci->phy_clk);
clk_disable(mehci->cal_clk);
clk_disable(mehci->ahb_clk);
pdata = mehci->dev->platform_data;
@@ -477,8 +477,8 @@
pr_err("%s failed to vote for"
"TCXO D1 buffer%d\n", __func__, ret);
}
- clk_enable(mehci->sys_clk);
- clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->core_clk);
+ clk_enable(mehci->phy_clk);
clk_enable(mehci->cal_clk);
clk_enable(mehci->ahb_clk);
@@ -634,71 +634,71 @@
if (!init)
goto put_clocks;
- /*sys_clk is required for LINK protocol engine,it should be at 60MHz */
- mehci->sys_clk = clk_get(mehci->dev, "usb_hsic_system_clk");
- if (IS_ERR(mehci->sys_clk)) {
- dev_err(mehci->dev, "failed to get hsic_sys_clk\n");
- ret = PTR_ERR(mehci->sys_clk);
+ /*core_clk is required for LINK protocol engine,it should be at 60MHz */
+ mehci->core_clk = clk_get(mehci->dev, "core_clk");
+ if (IS_ERR(mehci->core_clk)) {
+ dev_err(mehci->dev, "failed to get core_clk\n");
+ ret = PTR_ERR(mehci->core_clk);
return ret;
}
- clk_set_rate(mehci->sys_clk, 60000000);
+ clk_set_rate(mehci->core_clk, 60000000);
- /* 60MHz fs_xcvr_clk is for LINK to be used during PHY RESET */
- mehci->fs_xcvr_clk = clk_get(mehci->dev, "usb_hsic_xcvr_fs_clk");
- if (IS_ERR(mehci->fs_xcvr_clk)) {
- dev_err(mehci->dev, "failed to get fs_xcvr_clk\n");
- ret = PTR_ERR(mehci->fs_xcvr_clk);
- goto put_sys_clk;
+ /* 60MHz alt_core_clk is for LINK to be used during PHY RESET */
+ mehci->alt_core_clk = clk_get(mehci->dev, "alt_core_clk");
+ if (IS_ERR(mehci->alt_core_clk)) {
+ dev_err(mehci->dev, "failed to core_clk\n");
+ ret = PTR_ERR(mehci->alt_core_clk);
+ goto put_core_clk;
}
- clk_set_rate(mehci->fs_xcvr_clk, 60000000);
+ clk_set_rate(mehci->alt_core_clk, 60000000);
- /* 480MHz hsic_clk is required for HSIC PHY operation */
- mehci->hsic_clk = clk_get(mehci->dev, "usb_hsic_hsic_clk");
- if (IS_ERR(mehci->hsic_clk)) {
- dev_err(mehci->dev, "failed to get hsic_clk\n");
- ret = PTR_ERR(mehci->hsic_clk);
- goto put_fs_xcvr_clk;
+ /* 480MHz phy_clk is required for HSIC PHY operation */
+ mehci->phy_clk = clk_get(mehci->dev, "phy_clk");
+ if (IS_ERR(mehci->phy_clk)) {
+ dev_err(mehci->dev, "failed to get phy_clk\n");
+ ret = PTR_ERR(mehci->phy_clk);
+ goto put_alt_core_clk;
}
- clk_set_rate(mehci->hsic_clk, 480000000);
+ clk_set_rate(mehci->phy_clk, 480000000);
/* 10MHz cal_clk is required for calibration of I/O pads */
- mehci->cal_clk = clk_get(mehci->dev, "usb_hsic_hsio_cal_clk");
+ mehci->cal_clk = clk_get(mehci->dev, "cal_clk");
if (IS_ERR(mehci->cal_clk)) {
- dev_err(mehci->dev, "failed to get hsic_cal_clk\n");
+ dev_err(mehci->dev, "failed to get cal_clk\n");
ret = PTR_ERR(mehci->cal_clk);
- goto put_hsic_clk;
+ goto put_phy_clk;
}
clk_set_rate(mehci->cal_clk, 10000000);
/* ahb_clk is required for data transfers */
- mehci->ahb_clk = clk_get(mehci->dev, "usb_hsic_p_clk");
+ mehci->ahb_clk = clk_get(mehci->dev, "iface_clk");
if (IS_ERR(mehci->ahb_clk)) {
- dev_err(mehci->dev, "failed to get hsic_ahb_clk\n");
+ dev_err(mehci->dev, "failed to get iface_clk\n");
ret = PTR_ERR(mehci->ahb_clk);
goto put_cal_clk;
}
- clk_enable(mehci->sys_clk);
- clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->core_clk);
+ clk_enable(mehci->phy_clk);
clk_enable(mehci->cal_clk);
clk_enable(mehci->ahb_clk);
return 0;
put_clocks:
- clk_disable(mehci->sys_clk);
- clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->core_clk);
+ clk_disable(mehci->phy_clk);
clk_disable(mehci->cal_clk);
clk_disable(mehci->ahb_clk);
clk_put(mehci->ahb_clk);
put_cal_clk:
clk_put(mehci->cal_clk);
-put_hsic_clk:
- clk_put(mehci->hsic_clk);
-put_fs_xcvr_clk:
- clk_put(mehci->fs_xcvr_clk);
-put_sys_clk:
- clk_put(mehci->sys_clk);
+put_phy_clk:
+ clk_put(mehci->phy_clk);
+put_alt_core_clk:
+ clk_put(mehci->alt_core_clk);
+put_core_clk:
+ clk_put(mehci->core_clk);
return ret;
}