| commit | 5553079813b26666c2e1179ecfccb07dcdd8eb5e | [log] [tgz] |
|---|---|---|
| author | Pushkar Joshi <pushkarj@codeaurora.org> | Mon May 13 22:53:52 2013 -0700 |
| committer | Pushkar Joshi <pushkarj@codeaurora.org> | Thu Jul 18 15:28:36 2013 -0700 |
| tree | 5598f7ae60a01cc8c37afe5b942e94b17d87bac9 | |
| parent | bf213a034c4470a071c3edaedc46e569bba17ed2 [diff] |
ARM: dts: msm: Add CoreSight byte counter interrupt for 8226 The CoreSight block can produce an interrupt on transfer of programmed number of bytes to ETR-memory. Add device tree entry to support this feature. Change-Id: I1d2ff81def7573b1b0ed44dc4c94553594f2a386 Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>