msm: pil-q6v5: Enable q6ss_ahbm_clk for LPASS Q6
This clock must be enabled for the LPASS Q6 to reach its own clock
registers, so that it can turn on additional clocks on its own. Do
this.
To avoid adding another clock to struct q6v5_data, rename the mem_clk
member in it (used by MSS) to something more generic so it can also
be used by LPASS.
Change-Id: I0b4ec626d249a48dd832a818f630f1f6aed1f98a
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/pil-q6v5-lpass.c b/arch/arm/mach-msm/pil-q6v5-lpass.c
index 311f8a7..99223f2 100644
--- a/arch/arm/mach-msm/pil-q6v5-lpass.c
+++ b/arch/arm/mach-msm/pil-q6v5-lpass.c
@@ -96,6 +96,10 @@
desc->owner = THIS_MODULE;
desc->proxy_timeout = PROXY_TIMEOUT_MS;
+ drv->ss_clk = devm_clk_get(&pdev->dev, "reg_clk");
+ if (IS_ERR(drv->ss_clk))
+ return PTR_ERR(drv->ss_clk);
+
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil))
return PTR_ERR(drv->pil);
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index 5c9c3c4..72ea57cc 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -247,9 +247,9 @@
return ret;
}
- drv->mem_clk = devm_clk_get(&pdev->dev, "mem_clk");
- if (IS_ERR(drv->mem_clk))
- return PTR_ERR(drv->mem_clk);
+ drv->ss_clk = devm_clk_get(&pdev->dev, "mem_clk");
+ if (IS_ERR(drv->ss_clk))
+ return PTR_ERR(drv->ss_clk);
drv->pil = msm_pil_register(desc);
if (IS_ERR(drv->pil))
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index d6ad2aa3..cb13805 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -126,15 +126,15 @@
ret = clk_prepare_enable(drv->bus_clk);
if (ret)
goto err_bus_clk;
- if (drv->mem_clk) {
- ret = clk_prepare_enable(drv->mem_clk);
+ if (drv->ss_clk) {
+ ret = clk_prepare_enable(drv->ss_clk);
if (ret)
- goto err_mem_clk;
+ goto err_ss_clk;
}
return 0;
-err_mem_clk:
+err_ss_clk:
clk_disable_unprepare(drv->bus_clk);
err_bus_clk:
clk_disable_unprepare(drv->core_clk);
@@ -151,7 +151,7 @@
clk_disable_unprepare(drv->bus_clk);
clk_disable_unprepare(drv->core_clk);
- clk_disable_unprepare(drv->mem_clk);
+ clk_disable_unprepare(drv->ss_clk);
clk_reset(drv->core_clk, CLK_RESET_ASSERT);
}
EXPORT_SYMBOL(pil_q6v5_disable_clks);
diff --git a/arch/arm/mach-msm/pil-q6v5.h b/arch/arm/mach-msm/pil-q6v5.h
index e0d7a20..f94129d 100644
--- a/arch/arm/mach-msm/pil-q6v5.h
+++ b/arch/arm/mach-msm/pil-q6v5.h
@@ -24,7 +24,7 @@
struct clk *xo;
struct clk *bus_clk;
struct clk *core_clk;
- struct clk *mem_clk;
+ struct clk *ss_clk;
void __iomem *axi_halt_base;
void __iomem *rmb_base;
void __iomem *restart_reg;