msm: clock-8226: Add BCR registers for GDSC-collapsible cores
The GDSC driver allows collapse of cores to be disabled
via device tree. Client drivers may still expect the core
to be reset to a clean state after calls to the GDSC APIs,
however.
Specify .bcr_reg addresses for GDSC-collapsible cores so
that the GDSC driver can assert resets to these cores in
lieu of collapsing them.
Change-Id: Ied58115e13d30d62b41622e8cf9f90e7639edbce
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8226.c b/arch/arm/mach-msm/clock-8226.c
index 452bc28..734926f 100644
--- a/arch/arm/mach-msm/clock-8226.c
+++ b/arch/arm/mach-msm/clock-8226.c
@@ -265,6 +265,7 @@
#define MMPLL1_PLL_STATUS (0x005C)
#define MMSS_PLL_VOTE_APCS (0x0100)
#define VCODEC0_CMD_RCGR (0x1000)
+#define VENUS0_BCR (0x1020)
#define VENUS0_VCODEC0_CBCR (0x1028)
#define VENUS0_AHB_CBCR (0x1030)
#define VENUS0_AXI_CBCR (0x1034)
@@ -274,6 +275,7 @@
#define BYTE0_CMD_RCGR (0x2120)
#define ESC0_CMD_RCGR (0x2160)
#define MDSS_AHB_CBCR (0x2308)
+#define MDSS_BCR (0x2300)
#define MDSS_AXI_CBCR (0x2310)
#define MDSS_PCLK0_CBCR (0x2314)
#define MDSS_MDP_CBCR (0x231C)
@@ -312,18 +314,22 @@
#define CAMSS_TOP_AHB_CBCR (0x3484)
#define CAMSS_MICRO_AHB_CBCR (0x3494)
#define JPEG0_CMD_RCGR (0x3500)
+#define CAMSS_JPEG_BCR (0x35A0)
#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
#define VFE0_CMD_RCGR (0x3600)
#define CPP_CMD_RCGR (0x3640)
+#define CAMSS_VFE_BCR (0x36A0)
#define CAMSS_VFE_VFE0_CBCR (0x36A8)
#define CAMSS_VFE_CPP_CBCR (0x36B0)
#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
+#define CAMSS_CSI_VFE0_BCR (0x3700)
#define CAMSS_CSI_VFE0_CBCR (0x3704)
#define OXILI_GFX3D_CBCR (0x4028)
+#define OXILICX_BCR (0x4030)
#define OXILICX_AXI_CBCR (0x4038)
#define OXILICX_AHB_CBCR (0x403C)
#define MMPLL2_PLL_MODE (0x4100)
@@ -2255,6 +2261,7 @@
static struct branch_clk camss_csi_vfe0_clk = {
.cbcr_reg = CAMSS_CSI_VFE0_CBCR,
+ .bcr_reg = CAMSS_CSI_VFE0_BCR,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
@@ -2302,6 +2309,7 @@
static struct branch_clk camss_jpeg_jpeg0_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
+ .bcr_reg = CAMSS_JPEG_BCR,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
@@ -2430,6 +2438,7 @@
static struct branch_clk camss_vfe_vfe0_clk = {
.cbcr_reg = CAMSS_VFE_VFE0_CBCR,
+ .bcr_reg = CAMSS_VFE_BCR,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
@@ -2512,6 +2521,7 @@
static struct branch_clk mdss_mdp_clk = {
.cbcr_reg = MDSS_MDP_CBCR,
+ .bcr_reg = MDSS_BCR,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
@@ -2608,6 +2618,7 @@
static struct branch_clk oxili_gfx3d_clk = {
.cbcr_reg = OXILI_GFX3D_CBCR,
+ .bcr_reg = OXILICX_BCR,
.has_sibling = 0,
.max_div = 0,
.base = &virt_bases[MMSS_BASE],
@@ -2667,6 +2678,7 @@
static struct branch_clk venus0_vcodec0_clk = {
.cbcr_reg = VENUS0_VCODEC0_CBCR,
+ .bcr_reg = VENUS0_BCR,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {