| commit | 5864810bc50de57e1b4757850d3208f69579af7f | [log] [tgz] |
|---|---|---|
| author | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | Wed Mar 18 09:04:01 2009 +0900 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Mon Mar 23 23:38:04 2009 +0100 |
| tree | 918469c22095b0734d19b31f5ad56bc43a411778 | |
| parent | d7001198366bffce4506ba21b7b0fee2de194f73 [diff] |
MIPS: VR5500: Enable prefetch Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..871e828 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c
@@ -780,7 +780,7 @@ c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: