microblaze: Define correct L1_CACHE_SHIFT value
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.
We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.
Here is the calculation for cacheline lenght 8 32bit=4Byte values
which is corresponding with SHIFT 5.
Signed-off-by: Michal Simek <monstr@monstr.eu>
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index e522108..4efe96a 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -15,7 +15,7 @@
#include <asm/registers.h>
-#define L1_CACHE_SHIFT 2
+#define L1_CACHE_SHIFT 5
/* word-granular cache in microblaze */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)