gpio: msm-v3: Clear the reset state before configuring a gpio interrupt
The reset state for the INTR_CFG register is 0xE2. We need
the upper nibble to specify the target processor for the
gpio interrupt (Value 0x4 for APPS). But we were ORing
0x4 with 0xE still keeps it as 0xE. Get rid of the
incorrect read, modify, write cycle. Make sure the
reset state is wiped off before setting the interrupt
configuration bits.
Change-Id: I3deee9fcebe9eec78f89635313c5f3d0923fede5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
1 file changed