tree a6110351bc5d3ceebcc425ea02d0dbd9ac67398d
parent 0c4ca9eb696cbab65692ee77c7f4fcfa65455857
author Manu Gautam <mgautam@codeaurora.org> 1379503529 +0530
committer Manu Gautam <mgautam@codeaurora.org> 1402895316 +0530

USB: ehci-msm2: Correct USB PHY RESET sequence

Existing code assumes that USB PHY is reset as part of block
reset using GCC, but that is not the case. This results in
PHY access failures later when ulpi accesses are performed,
or device enumeration fails as CORE can't access PHY.
Correct PHY reset sequence by using USB_PHY_PON bit with
USB_OTG_HS_PHY_CTRL register as per hardware programming
guidelines. Since, driver supports selection of primary or
secondary PHY with CI controller, choose PHY_CTRL_REG
accordingly. Also, debug out important USB register when
ulpi read/write timeout is seen with USB PHY.

CRs-fixed: 676343
Change-Id: Ie69e44a1134c1f4458619ae93520e722aad9e0c8
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>