msm: acpuclock-8960: Run from PLL8 when reprogramming the HFPLLs
On 8960v2 and 8064 devices, the QSB (Apps Fabric) clock source
may run fast enough such that, if it were used as a CPU clock
source, the CPU may need to run at an elevated voltage to work
reliably.
Instead of incurring the overhead of temporarily increasing the
CPU voltage while reprogramming the HFPLL, use another always-on
source that won't run fast enough to require a CPU voltage
increase.
Change-Id: I2b11f3f5a45e5673adebb4efca57317f000d201c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 405c59a..659c292 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -51,6 +51,7 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
#define SEC_SRC_SEL_QSB 0
+#define SEC_SRC_SEL_AUX 2
/* HFPLL registers offsets. */
#define HFPLL_MODE 0x00
@@ -548,12 +549,11 @@
return;
if (strt_s->src == HFPLL && tgt_s->src == HFPLL) {
- /* Move CPU to QSB source. */
/*
- * TODO: If using QSB here requires elevating voltages,
- * consider using PLL8 instead.
+ * Move to an always-on source running at a frequency that does
+ * not require an elevated CPU voltage. PLL8 is used here.
*/
- set_sec_clk_src(sc, SEC_SRC_SEL_QSB);
+ set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
/* Program CPU HFPLL. */
@@ -882,7 +882,7 @@
writel_relaxed(0x3, sc->aux_clk_sel);
/* Switch away from the HFPLL while it's re-initialized. */
- set_sec_clk_src(sc, SEC_SRC_SEL_QSB);
+ set_sec_clk_src(sc, SEC_SRC_SEL_AUX);
set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
hfpll_init(sc, tgt_s);