msm: 8960: WCNSS restart module, removed Watchdog bite IRQ
Watchdog bite interrupt is expected to be a level interrupt.
However when requested for this interrupt, Krait0 has trouble
in power collapse. APSS may be expecting an edge triggered
interrupt.
Acked-by: Sameer Thalappil <sameert@qca.qualcomm.com>
Signed-off-by: Ankur Nandwani <ankurn@codeaurora.org>
diff --git a/arch/arm/mach-msm/wcnss-ssr-8960.c b/arch/arm/mach-msm/wcnss-ssr-8960.c
index 8615de5..954b925 100644
--- a/arch/arm/mach-msm/wcnss-ssr-8960.c
+++ b/arch/arm/mach-msm/wcnss-ssr-8960.c
@@ -64,16 +64,6 @@
subsystem_restart("riva");
}
-static irqreturn_t riva_wdog_bite_irq_hdlr(int irq, void *dev_id)
-{
- riva_crash = true;
- pr_debug("%s: rxed irq[0x%x]", MODULE_NAME, irq);
- disable_irq_nosync(RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ);
- schedule_work(&riva_fatal_work);
-
- return IRQ_HANDLED;
-}
-
/* SMSM reset Riva */
static void smsm_riva_reset(void)
{
@@ -146,14 +136,6 @@
" (%d)\n", MODULE_NAME, ret);
goto out;
}
- ret = request_irq(RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ,
- riva_wdog_bite_irq_hdlr,
- IRQF_TRIGGER_HIGH, "riva_wdog", NULL);
- if (ret < 0) {
- pr_err("%s: Unable to register RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ irq.",
- MODULE_NAME);
- goto out;
- }
ret = riva_restart_init();
if (ret < 0) {
pr_err("%s: Unable to register with ssr. (%d)\n",