msm: acpuclock-krait: Keep the secondary MUX input fixed
With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot. Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.
Change-Id: I5cd8c981f1be49be7dbba1310d84df439e8be83b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index ee2ca45..4fb9cc2 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -52,6 +52,7 @@
[CPU0] = {
.hfpll_phys_base = 0xF908A000,
.l2cpmr_iaddr = 0x4501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait0", 1050000 },
.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
@@ -61,6 +62,7 @@
[CPU1] = {
.hfpll_phys_base = 0xF909A000,
.l2cpmr_iaddr = 0x5501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait1", 1050000 },
.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
@@ -70,6 +72,7 @@
[CPU2] = {
.hfpll_phys_base = 0xF90AA000,
.l2cpmr_iaddr = 0x6501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait2", 1050000 },
.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
@@ -79,6 +82,7 @@
[CPU3] = {
.hfpll_phys_base = 0xF90BA000,
.l2cpmr_iaddr = 0x7501,
+ .sec_clk_sel = 2,
.vreg[VREG_CORE] = { "krait3", 1050000 },
.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
@@ -88,6 +92,7 @@
[L2] = {
.hfpll_phys_base = 0xF9016000,
.l2cpmr_iaddr = 0x0500,
+ .sec_clk_sel = 2,
.vreg[VREG_HFPLL_A] = { "l2_hfpll_a", 2150000 },
.vreg[VREG_HFPLL_B] = { "l2_hfpll_b", 1800000 },
},
@@ -108,60 +113,60 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 300000, PLL_0, 0, 2, 0 }, LVL_LOW, 950000, 0 },
- [1] = { { 384000, HFPLL, 2, 0, 40 }, LVL_NOM, 950000, 1 },
- [2] = { { 460800, HFPLL, 2, 0, 48 }, LVL_NOM, 950000, 1 },
- [3] = { { 537600, HFPLL, 1, 0, 28 }, LVL_NOM, 950000, 2 },
- [4] = { { 576000, HFPLL, 1, 0, 30 }, LVL_NOM, 950000, 2 },
- [5] = { { 652800, HFPLL, 1, 0, 34 }, LVL_NOM, 950000, 2 },
- [6] = { { 729600, HFPLL, 1, 0, 38 }, LVL_NOM, 950000, 2 },
- [7] = { { 806400, HFPLL, 1, 0, 42 }, LVL_NOM, 950000, 2 },
- [8] = { { 883200, HFPLL, 1, 0, 46 }, LVL_HIGH, 1050000, 2 },
- [9] = { { 960000, HFPLL, 1, 0, 50 }, LVL_HIGH, 1050000, 2 },
- [10] = { { 1036800, HFPLL, 1, 0, 54 }, LVL_HIGH, 1050000, 3 },
- [11] = { { 1113600, HFPLL, 1, 0, 58 }, LVL_HIGH, 1050000, 3 },
- [12] = { { 1190400, HFPLL, 1, 0, 62 }, LVL_HIGH, 1050000, 3 },
- [13] = { { 1267200, HFPLL, 1, 0, 66 }, LVL_HIGH, 1050000, 3 },
- [14] = { { 1344000, HFPLL, 1, 0, 70 }, LVL_HIGH, 1050000, 3 },
- [15] = { { 1420800, HFPLL, 1, 0, 74 }, LVL_HIGH, 1050000, 3 },
- [16] = { { 1497600, HFPLL, 1, 0, 78 }, LVL_HIGH, 1050000, 3 },
- [17] = { { 1574400, HFPLL, 1, 0, 82 }, LVL_HIGH, 1050000, 3 },
- [18] = { { 1651200, HFPLL, 1, 0, 86 }, LVL_HIGH, 1050000, 3 },
- [19] = { { 1728000, HFPLL, 1, 0, 90 }, LVL_HIGH, 1050000, 3 },
- [20] = { { 1804800, HFPLL, 1, 0, 94 }, LVL_HIGH, 1050000, 3 },
- [21] = { { 1881600, HFPLL, 1, 0, 98 }, LVL_HIGH, 1050000, 3 },
- [22] = { { 1958400, HFPLL, 1, 0, 102 }, LVL_HIGH, 1050000, 3 },
- [23] = { { 2035200, HFPLL, 1, 0, 106 }, LVL_HIGH, 1050000, 3 },
- [24] = { { 2112000, HFPLL, 1, 0, 110 }, LVL_HIGH, 1050000, 3 },
- [25] = { { 2188800, HFPLL, 1, 0, 114 }, LVL_HIGH, 1050000, 3 },
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 384000, HFPLL, 2, 40 }, LVL_NOM, 950000, 1 },
+ [2] = { { 460800, HFPLL, 2, 48 }, LVL_NOM, 950000, 1 },
+ [3] = { { 537600, HFPLL, 1, 28 }, LVL_NOM, 950000, 2 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 2 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 2 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 2 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 2 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 2 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 2 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 3 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 3 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 3 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 3 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 3 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 3 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 3 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 3 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 3 },
+ [19] = { { 1728000, HFPLL, 1, 90 }, LVL_HIGH, 1050000, 3 },
+ [20] = { { 1804800, HFPLL, 1, 94 }, LVL_HIGH, 1050000, 3 },
+ [21] = { { 1881600, HFPLL, 1, 98 }, LVL_HIGH, 1050000, 3 },
+ [22] = { { 1958400, HFPLL, 1, 102 }, LVL_HIGH, 1050000, 3 },
+ [23] = { { 2035200, HFPLL, 1, 106 }, LVL_HIGH, 1050000, 3 },
+ [24] = { { 2112000, HFPLL, 1, 110 }, LVL_HIGH, 1050000, 3 },
+ [25] = { { 2188800, HFPLL, 1, 114 }, LVL_HIGH, 1050000, 3 },
{ }
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 300000, PLL_0, 0, 2, 0 }, L2(0), 950000, 3200000 },
- { 1, { 384000, HFPLL, 2, 0, 40 }, L2(3), 950000, 3200000 },
- { 1, { 460800, HFPLL, 2, 0, 48 }, L2(3), 950000, 3200000 },
- { 1, { 537600, HFPLL, 1, 0, 28 }, L2(5), 950000, 3200000 },
- { 1, { 576000, HFPLL, 1, 0, 30 }, L2(5), 950000, 3200000 },
- { 1, { 652800, HFPLL, 1, 0, 34 }, L2(5), 950000, 3200000 },
- { 1, { 729600, HFPLL, 1, 0, 38 }, L2(5), 950000, 3200000 },
- { 1, { 806400, HFPLL, 1, 0, 42 }, L2(7), 950000, 3200000 },
- { 1, { 883200, HFPLL, 1, 0, 46 }, L2(7), 950000, 3200000 },
- { 1, { 960000, HFPLL, 1, 0, 50 }, L2(7), 950000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 0, 54 }, L2(7), 950000, 3200000 },
- { 1, { 1113600, HFPLL, 1, 0, 58 }, L2(12), 1050000, 3200000 },
- { 1, { 1190400, HFPLL, 1, 0, 62 }, L2(12), 1050000, 3200000 },
- { 1, { 1267200, HFPLL, 1, 0, 66 }, L2(12), 1050000, 3200000 },
- { 1, { 1344000, HFPLL, 1, 0, 70 }, L2(15), 1050000, 3200000 },
- { 1, { 1420800, HFPLL, 1, 0, 74 }, L2(15), 1050000, 3200000 },
- { 1, { 1497600, HFPLL, 1, 0, 78 }, L2(16), 1050000, 3200000 },
- { 0, { 1574400, HFPLL, 1, 0, 82 }, L2(20), 1050000, 3200000 },
- { 0, { 1651200, HFPLL, 1, 0, 86 }, L2(20), 1050000, 3200000 },
- { 0, { 1728000, HFPLL, 1, 0, 90 }, L2(20), 1050000, 3200000 },
- { 0, { 1804800, HFPLL, 1, 0, 94 }, L2(25), 1050000, 3200000 },
- { 0, { 1881600, HFPLL, 1, 0, 98 }, L2(25), 1050000, 3200000 },
- { 0, { 1958400, HFPLL, 1, 0, 102 }, L2(25), 1050000, 3200000 },
- { 0, { 1996800, HFPLL, 1, 0, 104 }, L2(25), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 3200000 },
+ { 1, { 384000, HFPLL, 2, 40 }, L2(3), 950000, 3200000 },
+ { 1, { 460800, HFPLL, 2, 48 }, L2(3), 950000, 3200000 },
+ { 1, { 537600, HFPLL, 1, 28 }, L2(5), 950000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(5), 950000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(5), 950000, 3200000 },
+ { 1, { 729600, HFPLL, 1, 38 }, L2(5), 950000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 42 }, L2(7), 950000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(7), 950000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(7), 950000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(7), 950000, 3200000 },
+ { 1, { 1113600, HFPLL, 1, 58 }, L2(12), 1050000, 3200000 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(12), 1050000, 3200000 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(12), 1050000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(15), 1050000, 3200000 },
+ { 1, { 1420800, HFPLL, 1, 74 }, L2(15), 1050000, 3200000 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
+ { 0, { 1574400, HFPLL, 1, 82 }, L2(20), 1050000, 3200000 },
+ { 0, { 1651200, HFPLL, 1, 86 }, L2(20), 1050000, 3200000 },
+ { 0, { 1728000, HFPLL, 1, 90 }, L2(20), 1050000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(25), 1050000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(25), 1050000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(25), 1050000, 3200000 },
+ { 0, { 1996800, HFPLL, 1, 104 }, L2(25), 1050000, 3200000 },
{ 0, { 0 } }
};