tree dabf4577ba47d2f7b70741c94353c94f1770b9f8
parent 91756acb58b17aee68d055fc15b1e2550ff00801
author Catalin Marinas <catalin.marinas@arm.com> 1327488862 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1328204262 +0000

ARM: 7302/1: Add TLB flushing for both entries in a PMD

Linux uses two PMD entries for a PTE with the classic page table format,
covering 2MB range. However, the __pte_free_tlb() function only adds a
single TLB flush corresponding to 1MB range covering 'addr'. On
Cortex-A15, level 1 entries can be cached by the TLB independently of
the level 2 entries and without additional flushing a PMD entry would be
left pointing at the wrong PTE. The patch limits the TLB flushing range
to two 4KB pages around the 1MB boundary within PMD.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>