Merge changes Idca5ac07,Ifc85b131,I0a7a113f,I5087584a,I40360498 into msm-3.4
* changes:
msm_serial_hs_lite: Unconditionally control UART AHB clock
arm/dt: msm8974: Disable simulation UARTs by default
msm: clock-8974: Remove support for mmss_mmssnoc_ahb_clk
msm: clock-8974: Enable GPLL0's AUX2 output for acpuclock
msm: clock-8974: Don't program an N value of zero
diff --git a/arch/arm/boot/dts/msm8974-rumi.dts b/arch/arm/boot/dts/msm8974-rumi.dts
index 1706327..3533151 100644
--- a/arch/arm/boot/dts/msm8974-rumi.dts
+++ b/arch/arm/boot/dts/msm8974-rumi.dts
@@ -23,8 +23,8 @@
clock-frequency = <5000000>;
};
- serial@f991f000 {
- status = "disable";
+ serial@f995e000 {
+ status = "ok";
};
usb@f9a55000 {
diff --git a/arch/arm/boot/dts/msm8974-sim.dts b/arch/arm/boot/dts/msm8974-sim.dts
index 885453c..8cd925e 100644
--- a/arch/arm/boot/dts/msm8974-sim.dts
+++ b/arch/arm/boot/dts/msm8974-sim.dts
@@ -25,4 +25,12 @@
status = "ok";
};
};
+
+ serial@f991f000 {
+ status = "ok";
+ };
+
+ serial@f995e000 {
+ status = "ok";
+ };
};
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 1c8b8c4..e3dad4f 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -63,12 +63,14 @@
compatible = "qcom,msm-lsuart-v14";
reg = <0xf991f000 0x1000>;
interrupts = <0 109 0>;
+ status = "disabled";
};
serial@f995e000 {
compatible = "qcom,msm-lsuart-v14";
reg = <0xf995e000 0x1000>;
interrupts = <0 114 0>;
+ status = "disabled";
};
usb@f9a55000 {
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index c0ee569..007e63e 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -518,7 +518,7 @@
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
- .n_val = ~((n)-(m)), \
+ .n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_source_val), \
@@ -529,7 +529,7 @@
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
- .n_val = ~((n)-(m)), \
+ .n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_mm_source_val), \
@@ -539,7 +539,7 @@
{ \
.freq_hz = (f), \
.m_val = (m), \
- .n_val = ~((n)-(m)), \
+ .n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_mm_source_val), \
@@ -550,7 +550,7 @@
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
- .n_val = ~((n)-(m)), \
+ .n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_hsic_source_val), \
@@ -561,7 +561,7 @@
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
- .n_val = ~((n)-(m)), \
+ .n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_lpass_source_val), \
@@ -3744,17 +3744,6 @@
},
};
-static struct branch_clk mmss_mmssnoc_ahb_clk = {
- .cbcr_reg = MMSS_MMSSNOC_AHB_CBCR,
- .has_sibling = 1,
- .base = &virt_bases[MMSS_BASE],
- .c = {
- .dbg_name = "mmss_mmssnoc_ahb_clk",
- .ops = &clk_ops_branch,
- CLK_INIT(mmss_mmssnoc_ahb_clk.c),
- },
-};
-
static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
.cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
.has_sibling = 1,
@@ -4436,7 +4425,6 @@
{&gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071},
{&gcc_ocmem_noc_cfg_ahb_clk.c, GCC_BASE, 0x0029},
{&gcc_ce1_clk.c, GCC_BASE, 0x0138},
- {&mmss_mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001},
{&mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004},
{&ocmemnoc_clk.c, MMSS_BASE, 0x0007},
{&ocmemcx_ocmemnoc_clk.c, MMSS_BASE, 0x0009},
@@ -4863,7 +4851,6 @@
/* Multimedia clocks */
CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
- CLK_LOOKUP("bus_clk", mmss_mmssnoc_ahb_clk.c, ""),
CLK_LOOKUP("bus_clk", mmss_mmssnoc_axi_clk.c, ""),
CLK_LOOKUP("core_clk", mdss_edpaux_clk.c, ""),
CLK_LOOKUP("core_clk", mdss_edppixel_clk.c, ""),
@@ -5231,6 +5218,7 @@
};
#define PLL_AUX_OUTPUT_BIT 1
+#define PLL_AUX2_OUTPUT_BIT 2
static void __init reg_init(void)
{
@@ -5249,9 +5237,9 @@
configure_pll(&mmpll3_config, &mmpll3_regs, 0);
configure_pll(&lpapll0_config, &lpapll0_regs, 1);
- /* Active GPLL0's aux output. This is needed by acpuclock. */
+ /* Enable GPLL0's aux outputs. */
regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL_REG));
- regval |= BIT(PLL_AUX_OUTPUT_BIT);
+ regval |= BIT(PLL_AUX_OUTPUT_BIT) | BIT(PLL_AUX2_OUTPUT_BIT);
writel_relaxed(regval, GCC_REG_BASE(GPLL0_USER_CTL_REG));
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index 987008d..f065eaa 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -1384,13 +1384,12 @@
if (!gsbi_resource)
gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
msm_hsl_port->clk = clk_get(&pdev->dev, "core_clk");
- if (gsbi_resource) {
+ msm_hsl_port->pclk = clk_get(&pdev->dev, "iface_clk");
+
+ if (gsbi_resource)
msm_hsl_port->is_uartdm = 1;
- msm_hsl_port->pclk = clk_get(&pdev->dev, "iface_clk");
- } else {
+ else
msm_hsl_port->is_uartdm = 0;
- msm_hsl_port->pclk = NULL;
- }
if (unlikely(IS_ERR(msm_hsl_port->clk))) {
printk(KERN_ERR "%s: Error getting clk\n", __func__);