tree f4905768cf9cc469b79e92a3c7cf9dec2c6079b1
parent b0b07a2bd4fbb6198d4e7142337214eeb77c417a
author Borislav Petkov <borislav.petkov@amd.com> 1316446485 +0200
committer Borislav Petkov <borislav.petkov@amd.com> 1317897245 +0200

amd64_edac: Add a fix for Erratum 505

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>