msm: idle-v7.S: Change the cache flush sequence operations for 8x25
On current implementation when the core0 enter into either
idlePC/SuspendPC it follows the below sequence to flush the
caches.
1. L2 cache clean & invalidation by way
2. Disable the L2 cache
3. invalidate the L1
4. disable data caching at all levels
5. goto PC
But PL310 TRM says, to avoid any kind of data corruption we need to
follow the below sequence of operations on cache.
1. invalidate the L1
2. disable data caching at all levels
3. L2 cache clean & invalidation by way
4. Disable the L2 cache
5. goto PC
Refer the PL310 TRM Page no: 91 for more information.
Change-Id: I908fcee72dec600945396e073f03517e265656b1
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
4 files changed