commit 73f4871e2cf31e8b97361330a8d8f4ea971e877a
author Dilip Kota <c_dkota@codeaurora.org> Mon Dec 16 19:44:38 2013 +0530
committer Dilip Kota <c_dkota@codeaurora.org> Tue Mar 25 15:53:18 2014 +0530
tree a6dc39e3d05f21b294e7dea0ffc52a547c309967
parent c1c3ef29538df5094a7d4fe821256e03312cf771

msm_serial_hs: Programming BCR Register

UART Core is showing inconsistent behaviour in firing
Stale Timeout Interrupt. Stale Timeout is not happening
at some points. After programming the BCR register the
Stale Timeout is happening as expected.
Also fix the BCR register offset to avoid instablilities when
console is disabled.

CRs-Fixed: 590176, 628523
Change-Id: I5a2522b87fe0951cad80e56f8f880c214d2d3bb5
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>