msm: clock: Add 'gp' clocks for 8660, 8960, 8064, and 9615
The frequency tables are populated with example clock rates, but
board-specific customization is expected. All three drivers use
identical implementations, except for the missing PXO support
on 9615 and different Fmax data between SoCs.
Change-Id: I482a9398abc7ffa624d146a3abe5744d5db1ca35
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 66c6436..7d82b8d 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -57,6 +57,8 @@
#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
#define CLK_TEST_REG REG(0x2FA0)
+#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
@@ -319,7 +321,7 @@
/* MUX source input identifiers. */
#define pxo_to_bb_mux 0
-#define cxo_to_bb_mux pxo_to_bb_mux
+#define cxo_to_bb_mux 5
#define pll0_to_bb_mux 2
#define pll8_to_bb_mux 3
#define pll6_to_bb_mux 4
@@ -1222,6 +1224,55 @@
/*
* Peripheral Clocks
*/
+#define CLK_GP(i, n, h_r, h_b) \
+ struct rcg_clk i##_clk = { \
+ .b = { \
+ .ctl_reg = GPn_NS_REG(n), \
+ .en_mask = BIT(9), \
+ .halt_reg = h_r, \
+ .halt_bit = h_b, \
+ }, \
+ .ns_reg = GPn_NS_REG(n), \
+ .md_reg = GPn_MD_REG(n), \
+ .root_en_mask = BIT(11), \
+ .ns_mask = (BM(23, 16) | BM(6, 0)), \
+ .set_rate = set_rate_mnd, \
+ .freq_tbl = clk_tbl_gp, \
+ .current_freq = &rcg_dummy_freq, \
+ .c = { \
+ .dbg_name = #i "_clk", \
+ .ops = &clk_ops_rcg_8960, \
+ VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
+ CLK_INIT(i##_clk.c), \
+ }, \
+ }
+#define F_GP(f, s, d, m, n) \
+ { \
+ .freq_hz = f, \
+ .src_clk = &s##_clk.c, \
+ .md_val = MD8(16, m, 0, n), \
+ .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+ .mnd_en_mask = BIT(8) * !!(n), \
+ }
+static struct clk_freq_tbl clk_tbl_gp[] = {
+ F_GP( 0, gnd, 1, 0, 0),
+ F_GP( 9600000, cxo, 2, 0, 0),
+ F_GP( 13500000, pxo, 2, 0, 0),
+ F_GP( 19200000, cxo, 1, 0, 0),
+ F_GP( 27000000, pxo, 1, 0, 0),
+ F_GP( 64000000, pll8, 2, 1, 3),
+ F_GP( 76800000, pll8, 1, 1, 5),
+ F_GP( 96000000, pll8, 4, 0, 0),
+ F_GP(128000000, pll8, 3, 0, 0),
+ F_GP(192000000, pll8, 2, 0, 0),
+ F_GP(384000000, pll8, 1, 0, 0),
+ F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
#define CLK_GSBI_UART(i, n, h_r, h_b) \
struct rcg_clk i##_clk = { \
.b = { \
@@ -4681,6 +4732,9 @@
{ TEST_PER_LS(0x19), &sdc4_clk.c },
{ TEST_PER_LS(0x1A), &sdc5_p_clk.c },
{ TEST_PER_LS(0x1B), &sdc5_clk.c },
+ { TEST_PER_LS(0x1F), &gp0_clk.c },
+ { TEST_PER_LS(0x20), &gp1_clk.c },
+ { TEST_PER_LS(0x21), &gp2_clk.c },
{ TEST_PER_LS(0x25), &dfab_clk.c },
{ TEST_PER_LS(0x25), &dfab_a_clk.c },
{ TEST_PER_LS(0x26), &pmem_clk.c },
@@ -5070,6 +5124,9 @@
CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
+ CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
@@ -5298,6 +5355,9 @@
CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 6707757..d1b2513 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -55,6 +55,8 @@
#define CLK_TEST_REG REG(0x2FA0)
#define EBI2_2X_CLK_CTL_REG REG(0x2660)
#define EBI2_CLK_CTL_REG REG(0x2664)
+#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
@@ -207,7 +209,7 @@
/* MUX source input identifiers. */
#define pxo_to_bb_mux 0
#define mxo_to_bb_mux 1
-#define cxo_to_bb_mux pxo_to_bb_mux
+#define cxo_to_bb_mux 5
#define pll0_to_bb_mux 2
#define pll8_to_bb_mux 3
#define pll6_to_bb_mux 4
@@ -1050,6 +1052,49 @@
/*
* Peripheral Clocks
*/
+#define CLK_GP(i, n, h_r, h_b) \
+ struct rcg_clk i##_clk = { \
+ .b = { \
+ .ctl_reg = GPn_NS_REG(n), \
+ .en_mask = BIT(9), \
+ .halt_reg = h_r, \
+ .halt_bit = h_b, \
+ }, \
+ .ns_reg = GPn_NS_REG(n), \
+ .md_reg = GPn_MD_REG(n), \
+ .root_en_mask = BIT(11), \
+ .ns_mask = (BM(23, 16) | BM(6, 0)), \
+ .set_rate = set_rate_mnd, \
+ .freq_tbl = clk_tbl_gp, \
+ .current_freq = &rcg_dummy_freq, \
+ .c = { \
+ .dbg_name = #i "_clk", \
+ .ops = &clk_ops_rcg_8x60, \
+ VDD_DIG_FMAX_MAP1(LOW, 27000000), \
+ CLK_INIT(i##_clk.c), \
+ }, \
+ }
+#define F_GP(f, s, d, m, n) \
+ { \
+ .freq_hz = f, \
+ .src_clk = &s##_clk.c, \
+ .md_val = MD8(16, m, 0, n), \
+ .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+ .mnd_en_mask = BIT(8) * !!(n), \
+ }
+static struct clk_freq_tbl clk_tbl_gp[] = {
+ F_GP( 0, gnd, 1, 0, 0),
+ F_GP( 9600000, cxo, 2, 0, 0),
+ F_GP( 13500000, pxo, 2, 0, 0),
+ F_GP( 19200000, cxo, 1, 0, 0),
+ F_GP( 27000000, pxo, 1, 0, 0),
+ F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
#define CLK_GSBI_UART(i, n, h_r, h_b) \
struct rcg_clk i##_clk = { \
.b = { \
@@ -3215,6 +3260,9 @@
{ TEST_PER_LS(0x1B), &sdc5_clk.c },
{ TEST_PER_LS(0x1D), &ebi2_2x_clk.c },
{ TEST_PER_LS(0x1E), &ebi2_clk.c },
+ { TEST_PER_LS(0x1F), &gp0_clk.c },
+ { TEST_PER_LS(0x20), &gp1_clk.c },
+ { TEST_PER_LS(0x21), &gp2_clk.c },
{ TEST_PER_LS(0x25), &dfab_clk.c },
{ TEST_PER_LS(0x25), &dfab_a_clk.c },
{ TEST_PER_LS(0x26), &pmem_clk.c },
@@ -3567,6 +3615,9 @@
CLK_LOOKUP("smi_clk", smi_clk.c, NULL),
CLK_LOOKUP("smi_a_clk", smi_a_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, "msm_serial_hsl.2"),
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index cd028e4..7e163df 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -50,6 +50,8 @@
#define CLK_HALT_MSS_KPSS_MISC_STATE_REG REG(0x2FDC)
#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
#define CLK_TEST_REG REG(0x2FA0)
+#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
+#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
@@ -346,6 +348,47 @@
/*
* Peripheral Clocks
*/
+#define CLK_GP(i, n, h_r, h_b) \
+ struct rcg_clk i##_clk = { \
+ .b = { \
+ .ctl_reg = GPn_NS_REG(n), \
+ .en_mask = BIT(9), \
+ .halt_reg = h_r, \
+ .halt_bit = h_b, \
+ }, \
+ .ns_reg = GPn_NS_REG(n), \
+ .md_reg = GPn_MD_REG(n), \
+ .root_en_mask = BIT(11), \
+ .ns_mask = (BM(23, 16) | BM(6, 0)), \
+ .set_rate = set_rate_mnd, \
+ .freq_tbl = clk_tbl_gp, \
+ .current_freq = &rcg_dummy_freq, \
+ .c = { \
+ .dbg_name = #i "_clk", \
+ .ops = &clk_ops_rcg_9615, \
+ VDD_DIG_FMAX_MAP1(LOW, 27000000), \
+ CLK_INIT(i##_clk.c), \
+ }, \
+ }
+#define F_GP(f, s, d, m, n) \
+ { \
+ .freq_hz = f, \
+ .src_clk = &s##_clk.c, \
+ .md_val = MD8(16, m, 0, n), \
+ .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
+ .mnd_en_mask = BIT(8) * !!(n), \
+ }
+static struct clk_freq_tbl clk_tbl_gp[] = {
+ F_GP( 0, gnd, 1, 0, 0),
+ F_GP( 9600000, cxo, 2, 0, 0),
+ F_GP( 19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
+static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
+static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
+
#define CLK_GSBI_UART(i, n, h_r, h_b) \
struct rcg_clk i##_clk = { \
.b = { \
@@ -1298,6 +1341,9 @@
{ TEST_PER_LS(0x13), &sdc1_clk.c },
{ TEST_PER_LS(0x14), &sdc2_p_clk.c },
{ TEST_PER_LS(0x15), &sdc2_clk.c },
+ { TEST_PER_LS(0x1F), &gp0_clk.c },
+ { TEST_PER_LS(0x20), &gp1_clk.c },
+ { TEST_PER_LS(0x21), &gp2_clk.c },
{ TEST_PER_LS(0x26), &pmem_clk.c },
{ TEST_PER_LS(0x25), &dfab_clk.c },
{ TEST_PER_LS(0x25), &dfab_a_clk.c },
@@ -1524,6 +1570,10 @@
CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp0_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp1_clk.c, NULL),
+ CLK_LOOKUP("core_clk", gp2_clk.c, NULL),
+
CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),