| commit | a81cbd2da48eacc860acf4f40ea05db790f4c7c3 | [log] [tgz] |
|---|---|---|
| author | Oskar Schirmer <os@emlix.com> | Wed Mar 04 16:21:30 2009 +0100 |
| committer | Chris Zankel <chris@zankel.net> | Thu Apr 02 23:41:16 2009 -0700 |
| tree | e6d8b940bfa97afebb713a01ad96e31b6ca0de48 | |
| parent | c947a585ab13f310c9223284dfd502790abd05f9 [diff] |
xtensa: enforce slab alignment to maximum register width XCHAL_DATA_WIDTH is the maximum register width, slab caches should be aligned to this. Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4 (wordsize) for now. But the S6000 variant will raise this to 16. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>