msm: clock: Fix rate storage for pll/pll_vote/fixed clocks
pll_clk, pll_vote_clk and fixed_clk have a separate rate field in
their definition structs. This is redundant since the clk struct
embedded in these three clocks has the rate already. In addition,
there is a problem of finding the correct vdd level while update
the vdd for the pll clk which support vdd voting because the level
is found by looking at the rate in the clk struct instead of the
rate outside of clk struct.
Therefore, remove the rate field for these clocks and update the
corresponding get_rate functions.
Change-Id: Iff21488cb7f45447949674ce0bf7543482463bfe
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 8374636..9bf864a 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -227,14 +227,13 @@
static struct clk_ops clk_ops_tcxo = {
.enable = tcxo_clk_enable,
.disable = tcxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = pcom_is_local,
};
static struct fixed_clk tcxo_clk = {
- .rate = 19200000,
.c = {
.dbg_name = "tcxo_clk",
+ .rate = 19200000,
.ops = &clk_ops_tcxo,
CLK_INIT(tcxo_clk.c),
},
@@ -253,66 +252,65 @@
static struct clk_ops clk_ops_lpxo = {
.enable = lpxo_clk_enable,
.disable = lpxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = pcom_is_local,
};
static struct fixed_clk lpxo_clk = {
- .rate = 24576000,
.c = {
.dbg_name = "lpxo_clk",
+ .rate = 24576000,
.ops = &clk_ops_lpxo,
CLK_INIT(lpxo_clk.c),
},
};
static struct pll_vote_clk pll1_clk = {
- .rate = 768000000,
.en_reg = PLL_ENA_REG,
.en_mask = BIT(1),
.status_reg = PLL1_STATUS_BASE_REG,
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll1_clk",
+ .rate = 768000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll1_clk.c),
},
};
static struct pll_vote_clk pll2_clk = {
- .rate = 806400000, /* TODO: Support scaling */
.en_reg = PLL_ENA_REG,
.en_mask = BIT(2),
.status_reg = PLL2_STATUS_BASE_REG,
.parent = &tcxo_clk.c,
.c = {
.dbg_name = "pll2_clk",
+ .rate = 806400000, /* TODO: Support scaling */
.ops = &clk_ops_pll_vote,
CLK_INIT(pll2_clk.c),
},
};
static struct pll_vote_clk pll3_clk = {
- .rate = 737280000,
.en_reg = PLL_ENA_REG,
.en_mask = BIT(3),
.status_reg = PLL3_STATUS_BASE_REG,
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll3_clk",
+ .rate = 737280000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll3_clk.c),
},
};
static struct pll_vote_clk pll4_clk = {
- .rate = 891000000,
.en_reg = PLL_ENA_REG,
.en_mask = BIT(4),
.status_reg = PLL4_STATUS_BASE_REG,
.parent = &lpxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
+ .rate = 891000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
},
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 65dd405..d06b250 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -470,14 +470,13 @@
static struct clk_ops clk_ops_pxo = {
.enable = pxo_clk_enable,
.disable = pxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = local_clk_is_local,
};
static struct fixed_clk pxo_clk = {
- .rate = 27000000,
.c = {
.dbg_name = "pxo_clk",
+ .rate = 27000000,
.ops = &clk_ops_pxo,
CLK_INIT(pxo_clk.c),
},
@@ -496,36 +495,35 @@
static struct clk_ops clk_ops_cxo = {
.enable = cxo_clk_enable,
.disable = cxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = local_clk_is_local,
};
static struct fixed_clk cxo_clk = {
- .rate = 19200000,
.c = {
.dbg_name = "cxo_clk",
+ .rate = 19200000,
.ops = &clk_ops_cxo,
CLK_INIT(cxo_clk.c),
},
};
static struct pll_clk pll2_clk = {
- .rate = 800000000,
.mode_reg = MM_PLL1_MODE_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll2_clk",
+ .rate = 800000000,
.ops = &clk_ops_pll,
CLK_INIT(pll2_clk.c),
},
};
static struct pll_clk pll3_clk = {
- .rate = 1200000000,
.mode_reg = BB_MMCC_PLL2_MODE_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll3_clk",
+ .rate = 1200000000,
.ops = &clk_ops_pll,
.vdd_class = &vdd_sr2_pll,
.fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
@@ -534,50 +532,50 @@
};
static struct pll_vote_clk pll4_clk = {
- .rate = 393216000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
+ .rate = 393216000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
},
};
static struct pll_vote_clk pll8_clk = {
- .rate = 384000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
+ .rate = 384000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll8_clk.c),
},
};
static struct pll_vote_clk pll14_clk = {
- .rate = 480000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
+ .rate = 480000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll14_clk.c),
},
};
static struct pll_clk pll15_clk = {
- .rate = 975000000,
.mode_reg = MM_PLL3_MODE_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll15_clk",
+ .rate = 975000000,
.ops = &clk_ops_pll,
CLK_INIT(pll15_clk.c),
},
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index e53d441..7476dc1 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -318,14 +318,13 @@
static struct clk_ops clk_ops_pxo = {
.enable = pxo_clk_enable,
.disable = pxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = xo_clk_is_local,
};
static struct fixed_clk pxo_clk = {
- .rate = 27000000,
.c = {
.dbg_name = "pxo_clk",
+ .rate = 27000000,
.ops = &clk_ops_pxo,
CLK_INIT(pxo_clk.c),
},
@@ -344,49 +343,48 @@
static struct clk_ops clk_ops_cxo = {
.enable = cxo_clk_enable,
.disable = cxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = xo_clk_is_local,
};
static struct fixed_clk cxo_clk = {
- .rate = 19200000,
.c = {
.dbg_name = "cxo_clk",
+ .rate = 19200000,
.ops = &clk_ops_cxo,
CLK_INIT(cxo_clk.c),
},
};
static struct pll_vote_clk pll8_clk = {
- .rate = 384000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll8_clk",
+ .rate = 384000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll8_clk.c),
},
};
static struct pll_clk pll2_clk = {
- .rate = 800000000,
.mode_reg = MM_PLL1_MODE_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll2_clk",
+ .rate = 800000000,
.ops = &clk_ops_pll,
CLK_INIT(pll2_clk.c),
},
};
static struct pll_clk pll3_clk = {
- .rate = 0, /* TODO: Detect rate dynamically */
.mode_reg = MM_PLL2_MODE_REG,
.parent = &pxo_clk.c,
.c = {
.dbg_name = "pll3_clk",
+ .rate = 0, /* TODO: Detect rate dynamically */
.ops = &clk_ops_pll,
CLK_INIT(pll3_clk.c),
},
@@ -417,15 +415,14 @@
static struct clk_ops clk_ops_pll4 = {
.enable = pll4_clk_enable,
.disable = pll4_clk_disable,
- .get_rate = fixed_clk_get_rate,
.get_parent = pll4_clk_get_parent,
.is_local = pll4_clk_is_local,
};
static struct fixed_clk pll4_clk = {
- .rate = 540672000,
.c = {
.dbg_name = "pll4_clk",
+ .rate = 540672000,
.ops = &clk_ops_pll4,
CLK_INIT(pll4_clk.c),
},
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 7233a16..16bd112 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -223,14 +223,13 @@
static struct clk_ops clk_ops_cxo = {
.enable = cxo_clk_enable,
.disable = cxo_clk_disable,
- .get_rate = fixed_clk_get_rate,
.is_local = local_clk_is_local,
};
static struct fixed_clk cxo_clk = {
- .rate = 19200000,
.c = {
.dbg_name = "cxo_clk",
+ .rate = 19200000,
.ops = &clk_ops_cxo,
CLK_INIT(cxo_clk.c),
},
@@ -274,7 +273,6 @@
.disable = pll_acpu_vote_clk_disable,
.auto_off = pll_acpu_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_rate = pll_vote_clk_get_rate,
.get_parent = pll_vote_clk_get_parent,
.is_local = local_clk_is_local,
};
@@ -285,7 +283,6 @@
static unsigned int soft_vote_pll0;
static struct pll_vote_clk pll0_clk = {
- .rate = 276000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
@@ -294,13 +291,13 @@
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
.dbg_name = "pll0_clk",
+ .rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll0_clk.c),
},
};
static struct pll_vote_clk pll0_acpu_clk = {
- .rate = 276000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
@@ -308,19 +305,20 @@
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
.dbg_name = "pll0_acpu_clk",
+ .rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll0_acpu_clk.c),
},
};
static struct pll_vote_clk pll4_clk = {
- .rate = 393216000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll4_clk",
+ .rate = 393216000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll4_clk.c),
},
@@ -329,7 +327,6 @@
static unsigned int soft_vote_pll8;
static struct pll_vote_clk pll8_clk = {
- .rate = 384000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
@@ -338,13 +335,13 @@
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
.dbg_name = "pll8_clk",
+ .rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll8_clk.c),
},
};
static struct pll_vote_clk pll8_acpu_clk = {
- .rate = 384000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
@@ -352,29 +349,30 @@
.soft_vote_mask = PLL_SOFT_VOTE_ACPU,
.c = {
.dbg_name = "pll8_acpu_clk",
+ .rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
CLK_INIT(pll8_acpu_clk.c),
},
};
static struct pll_clk pll9_acpu_clk = {
- .rate = 440000000,
.mode_reg = SC_PLL0_MODE_REG,
.c = {
.dbg_name = "pll9_acpu_clk",
+ .rate = 440000000,
.ops = &clk_ops_pll,
CLK_INIT(pll9_acpu_clk.c),
},
};
static struct pll_vote_clk pll14_clk = {
- .rate = 480000000,
.en_reg = BB_PLL_ENA_SC0_REG,
.en_mask = BIT(11),
.status_reg = BB_PLL14_STATUS_REG,
.parent = &cxo_clk.c,
.c = {
.dbg_name = "pll14_clk",
+ .rate = 480000000,
.ops = &clk_ops_pll_vote,
CLK_INIT(pll14_clk.c),
},
@@ -1821,7 +1819,7 @@
pll9_lval = readl_relaxed(SC_PLL0_L_VAL_REG);
if (pll9_lval == 0x1C)
- pll9_acpu_clk.rate = 550000000;
+ pll9_acpu_clk.c.rate = 550000000;
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regval = readl_relaxed(LCC_PRI_PLL_CLK_CTL_REG);
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index c02c6f3..677884c 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -686,12 +686,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-unsigned long pll_vote_clk_get_rate(struct clk *clk)
-{
- struct pll_vote_clk *pll = to_pll_vote_clk(clk);
- return pll->rate;
-}
-
struct clk *pll_vote_clk_get_parent(struct clk *clk)
{
struct pll_vote_clk *pll = to_pll_vote_clk(clk);
@@ -709,7 +703,6 @@
.disable = pll_vote_clk_disable,
.auto_off = pll_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_rate = pll_vote_clk_get_rate,
.get_parent = pll_vote_clk_get_parent,
.is_local = local_clk_is_local,
};
@@ -766,12 +759,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static unsigned long pll_clk_get_rate(struct clk *clk)
-{
- struct pll_clk *pll = to_pll_clk(clk);
- return pll->rate;
-}
-
static struct clk *pll_clk_get_parent(struct clk *clk)
{
struct pll_clk *pll = to_pll_clk(clk);
@@ -817,13 +804,11 @@
.enable = pll_clk_enable,
.disable = pll_clk_disable,
.auto_off = pll_clk_disable,
- .get_rate = pll_clk_get_rate,
.get_parent = pll_clk_get_parent,
.is_local = local_clk_is_local,
};
struct clk_ops clk_ops_gnd = {
- .get_rate = fixed_clk_get_rate,
.is_local = local_clk_is_local,
};
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index d312f24..8c67b13 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -249,29 +249,14 @@
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
- * @rate: output rate
* @c: clk
*/
struct fixed_clk {
- unsigned long rate;
struct clk c;
};
-static inline struct fixed_clk *to_fixed_clk(struct clk *clk)
-{
- return container_of(clk, struct fixed_clk, c);
-}
-
-static inline unsigned long fixed_clk_get_rate(struct clk *clk)
-{
- struct fixed_clk *f = to_fixed_clk(clk);
- return f->rate;
-}
-
-
/**
* struct pll_vote_clk - phase locked loop (HW voteable)
- * @rate: output rate
* @soft_vote: soft voting variable for multiple PLL software instances
* @soft_vote_mask: soft voting mask for multiple PLL software instances
* @en_reg: enable register
@@ -281,8 +266,6 @@
* @c: clk
*/
struct pll_vote_clk {
- unsigned long rate;
-
u32 *soft_vote;
const u32 soft_vote_mask;
void __iomem *const en_reg;
@@ -303,14 +286,11 @@
/**
* struct pll_clk - phase locked loop
- * @rate: output rate
* @mode_reg: enable register
* @parent: clock source
* @c: clk
*/
struct pll_clk {
- unsigned long rate;
-
void __iomem *const mode_reg;
struct clk *parent;
@@ -394,7 +374,6 @@
*/
int pll_vote_clk_enable(struct clk *clk);
void pll_vote_clk_disable(struct clk *clk);
-unsigned long pll_vote_clk_get_rate(struct clk *clk);
struct clk *pll_vote_clk_get_parent(struct clk *clk);
int pll_vote_clk_is_enabled(struct clk *clk);
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index 57fd749..5b89fa9 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/clock.c
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -222,7 +222,7 @@
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk->ops->get_rate)
- return 0;
+ return clk->rate;
return clk->ops->get_rate(clk);
}