msm: spm: add intermediate LPM mode for L2 PC
Currently when the core decide to enter into "PC + L2 PC"
LPM mode it informs to RPM and there is a chance of
system can enter into either XO or VDDmin. But this LPM
mode take longer time to enter and exit. Because of this
limitation some of the usecases where there is a less
latency APPS proc stays at lower LPM level (i.e GDFS) and
causing more power consumption. To address this issue adding
an intermediate LPM mode where L2 goes to PC but not inform
to RPM.
CRs-fixed: 552743
Change-Id: I321ff260d5baf8ac44917d67e9c9dfd260c8d5ca
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
diff --git a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
index f57d928..917ea75 100644
--- a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
+++ b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
@@ -20,6 +20,7 @@
"pc_no_xo_shutdown" - Power Collapse with no XO shutdown
- qcom,l2: The state of L2 cache. Values are:
"l2_cache_pc" - L2 cache in power collapse
+ "l2_cache_pc_no_rpm" - L2 cache in power collapse. This mode wouldn't inform the RPM
"l2_cache_retenetion" - L2 cache in retention
"l2_cache_gdhs" - L2 cache in GDHS
"l2_cache_active" - L2 cache in active mode
diff --git a/arch/arm/mach-msm/lpm_levels.c b/arch/arm/mach-msm/lpm_levels.c
index 180d277..249a334 100644
--- a/arch/arm/mach-msm/lpm_levels.c
+++ b/arch/arm/mach-msm/lpm_levels.c
@@ -191,6 +191,9 @@
case MSM_SPM_L2_MODE_GDHS:
msm_pm_set_l2_flush_flag(MSM_SCM_L2_GDHS);
break;
+ case MSM_SPM_L2_MODE_PC_NO_RPM:
+ msm_pm_set_l2_flush_flag(MSM_SCM_L2_OFF);
+ break;
case MSM_SPM_L2_MODE_RETENTION:
case MSM_SPM_L2_MODE_DISABLED:
break;
@@ -448,6 +451,7 @@
int i;
struct lpm_lookup_table l2_mode_lookup[] = {
{MSM_SPM_L2_MODE_POWER_COLLAPSE, "l2_cache_pc"},
+ {MSM_SPM_L2_MODE_PC_NO_RPM, "l2_cache_pc_no_rpm"},
{MSM_SPM_L2_MODE_GDHS, "l2_cache_gdhs"},
{MSM_SPM_L2_MODE_RETENTION, "l2_cache_retention"},
{MSM_SPM_L2_MODE_DISABLED, "l2_cache_active"}
diff --git a/arch/arm/mach-msm/spm.h b/arch/arm/mach-msm/spm.h
index 3207011..1769402 100644
--- a/arch/arm/mach-msm/spm.h
+++ b/arch/arm/mach-msm/spm.h
@@ -24,6 +24,7 @@
MSM_SPM_L2_MODE_DISABLED = MSM_SPM_MODE_DISABLED,
MSM_SPM_L2_MODE_RETENTION,
MSM_SPM_L2_MODE_GDHS,
+ MSM_SPM_L2_MODE_PC_NO_RPM,
MSM_SPM_L2_MODE_POWER_COLLAPSE,
};
diff --git a/arch/arm/mach-msm/spm_devices.c b/arch/arm/mach-msm/spm_devices.c
index 3ac1348..19b0b80 100644
--- a/arch/arm/mach-msm/spm_devices.c
+++ b/arch/arm/mach-msm/spm_devices.c
@@ -397,6 +397,7 @@
struct mode_of of_l2_modes[] = {
{"qcom,saw2-spm-cmd-ret", MSM_SPM_L2_MODE_RETENTION, 1},
{"qcom,saw2-spm-cmd-gdhs", MSM_SPM_L2_MODE_GDHS, 1},
+ {"qcom,saw2-spm-cmd-pc-no-rpm", MSM_SPM_L2_MODE_PC_NO_RPM, 1},
{"qcom,saw2-spm-cmd-pc", MSM_SPM_L2_MODE_POWER_COLLAPSE, 1},
};