| commit | 8315b9f89a0bfe5b930cc59a3982747cad896a37 | [log] [tgz] |
|---|---|---|
| author | Trilok Soni <tsoni@codeaurora.org> | Sun Sep 02 02:48:14 2012 +0530 |
| committer | Trilok Soni <tsoni@codeaurora.org> | Mon Sep 03 17:20:31 2012 +0530 |
| tree | 1de395ed5fc5bd0a9d62b7b25b46ac7e7feb42d9 | |
| parent | db64ae9cc896f239acf783a6291e0680dfeebd3c [diff] |
msm: vp: Clear APC_PLEVELx register's VREG_PD_EN bit The current logic in the set_voltage is not clearing VREG_PD_EN bit, so if this bit is set once then we will see increase in the one PMIC step size from the given voltage caller has requested to set. Change-Id: Id91f0dbdec004bcc111efdcaa08e613240c191b6 Signed-off-by: Trilok Soni <tsoni@codeaurora.org>