Merge "arm/dt: msm9625: Remove qcom,allow-atomic regulator property for S2"
diff --git a/Documentation/ABI/testing/sysfs-bus-pil b/Documentation/ABI/testing/sysfs-bus-pil
deleted file mode 100644
index 797b2ea..0000000
--- a/Documentation/ABI/testing/sysfs-bus-pil
+++ /dev/null
@@ -1,18 +0,0 @@
-What: /sys/bus/pil/devices/.../name
-Date: March 2012
-Contact: Stephen Boyd <sboyd@codeaurora.org>
-Description:
- Shows the name of the peripheral used in pil_get().
-
-What: /sys/bus/pil/devices/.../state
-Date: March 2012
-Contact: Stephen Boyd <sboyd@codeaurora.org>
-Description:
- Shows the state state of a peripheral. Current states
- supported are:
-
- OFFLINE - peripheral is offline
- ONLINE - peripheral is online
-
- This file supports poll() to detect when a peripheral changes
- state.
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
index 5c72eed..d62d0c6 100644
--- a/Documentation/DMA-attributes.txt
+++ b/Documentation/DMA-attributes.txt
@@ -49,3 +49,30 @@
consistent or non-consistent memory as it sees fit. By using this API,
you are guaranteeing to the platform that you have all the correct and
necessary sync points for this memory in the driver.
+
+DMA_ATTR_NO_KERNEL_MAPPING
+--------------------------
+
+DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
+virtual mapping for the allocated buffer. On some architectures creating
+such mapping is non-trivial task and consumes very limited resources
+(like kernel virtual address space or dma consistent address space).
+Buffers allocated with this attribute can be only passed to user space
+by calling dma_mmap_attrs(). By using this API, you are guaranteeing
+that you won't dereference the pointer returned by dma_alloc_attr(). You
+can threat it as a cookie that must be passed to dma_mmap_attrs() and
+dma_free_attrs(). Make sure that both of these also get this attribute
+set on each call.
+
+Since it is optional for platforms to implement
+DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
+attribute and exhibit default behavior.
+
+DMA_ATTR_STRONGLY_ORDERED
+-------------------------
+
+DMA_ATTR_STRONGLY_ORDERED allocates memory with a very restrictive type
+of mapping (no unaligned accesses, no re-ordering, no write merging, no
+buffering, no pre-fetching). This has severe performance penalties and
+should not be used for general purpose DMA allocations. It should only
+be used if one of the restrictions on strongly ordered memory is required.
diff --git a/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt b/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt
index d82284d..53a67a4 100644
--- a/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt
+++ b/Documentation/devicetree/bindings/arm/msm/bam_dmux.txt
@@ -5,10 +5,14 @@
- reg : the location and size of the BAM hardware
- interrupts : the BAM hardware to apps processor interrupt line
+Optional properties:
+-qcom,satellite-mode: the hardware needs to be configured in satellite mode
+
Example:
qcom,bam_dmux@fc834000 {
compatible = "qcom,bam_dmux";
reg = <0xfc834000 0x7000>;
interrupts = <0 29 1>;
+ qcom,satellite-mode;
};
diff --git a/Documentation/devicetree/bindings/arm/msm/memory-reserve.txt b/Documentation/devicetree/bindings/arm/msm/memory-reserve.txt
index 5f18893..c1b79ae 100644
--- a/Documentation/devicetree/bindings/arm/msm/memory-reserve.txt
+++ b/Documentation/devicetree/bindings/arm/msm/memory-reserve.txt
@@ -41,6 +41,17 @@
The EXPORT_COMPAT is to ensure that memory is only carved out if the
driver is actually enabled, otherwise the memory will not be used.
+If a reservation is needed that isn't associated directly with any one
+driver, the compatible string "qcom,msm-contig-mem" can be used. For
+example:
+
+ qcom,msm-contig-mem {
+ compatible = "qcom,msm-contig-mem";
+ qcom,memory-reservation-type = "EBI1";
+ qcom,memory-reservation-size = <0x280000>; /* 2.5M EBI1 buffer */
+ };
+
+
In order to specify the size and address of the fixed memory which has
previously been removed the memory-fixed binding can be used. This assumes
that the region has been removed by a separate memblock-remove property
diff --git a/Documentation/devicetree/bindings/arm/msm/pm-8x60.txt b/Documentation/devicetree/bindings/arm/msm/pm-8x60.txt
new file mode 100644
index 0000000..b429072
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/pm-8x60.txt
@@ -0,0 +1,28 @@
+* MSM PM-8x60
+
+PM-8x60 is the low power management device for MSM (Snapdragon class) chipsets.
+This device sets up different components to do low power modes and registers with
+the kernel to be notified of idle and suspend states and when called, follows
+through the set of instructions in putting the application cores to the lowest
+power mode possible.
+
+The required properties for PM-8x60 are:
+
+- compatible: "qcom,pm-8x60"
+
+The optional properties are:
+
+- qcom,use-sync-timer: Indicates whether the target uses the synchronized QTimer.
+- qcom,pc-mode: Indicates the type of power collapse used by the target. The
+ valid values for this are:
+ 0 (Power collapse terminates in TZ; integrated L2 cache controller)
+ 1, (Power collapse doesn't terminate in TZ; external L2 cache controller)
+ 2 (Power collapse terminates in TZ; external L2 cache controller)
+
+Example:
+
+qcom,pm-8x60 {
+ compatible = "qcom,pm-8x60";
+ qcom,pc-mode = <0>;
+ qcom,use-sync-timer;
+ };
diff --git a/Documentation/devicetree/bindings/arm/msm/rpm-stats.txt b/Documentation/devicetree/bindings/arm/msm/rpm-stats.txt
new file mode 100644
index 0000000..3137e91
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/rpm-stats.txt
@@ -0,0 +1,22 @@
+* RPM Sleep Stats
+
+RPM maintains sleep data in the RPM RAM. A device tree node is added
+that will hold the address of the RPM RAM from where sleep stats are read.
+Additionally a version number is added to distinguish the type of data
+structure being read from the RAM.
+
+The required properties for rpm-stats are:
+
+- compatible: "qcom,rpm-stats"
+- reg: The address on the RPM RAM from where stats are read.
+- reg-names: Name given the register holding address.
+- qcom,sleep-stats-version: Version number.
+
+Example:
+
+qcom,rpm-stats@fc19dbd0 {
+ compatible = "qcom,rpm-stats";
+ reg = <0xfc19dbd0 0x1000>;
+ reg-names = "phys_addr_base";
+ qcom,sleep-stats-version = <2>;
+};
diff --git a/Documentation/devicetree/bindings/arm/msm/smem.txt b/Documentation/devicetree/bindings/arm/msm/smem.txt
new file mode 100644
index 0000000..a38984c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/smem.txt
@@ -0,0 +1,107 @@
+Qualcomm Shared Memory
+
+[Root level node]
+Required properties:
+-compatible : should be "qcom,smem"
+-reg : the location and size of smem, the irq register base memory, and
+ optionally any auxiliary smem areas
+-reg-names : "smem" - string to identify the shared memory region
+ "irq-reg-base" - string to identify the irq register region
+ "aux-mem1", "aux-mem2", "aux-mem3", ... - optional strings to
+ identify any auxiliary shared memory regions
+
+[Second level nodes]
+
+qcom,smd
+Required properties:
+-compatible : should be "qcom,smd"
+-qcom,smd-edge : the smd edge
+-qcom,smd-irq-offset : the offset into the irq register base memory for sending
+ interrupts
+-qcom,smd-irq-bitmask : the sending irq bitmask
+-interrupts : the receiving interrupt line
+
+Optional properties:
+-qcom,pil-string : the name to use when loading this edge
+-qcom,irq-no-suspend: configure the incoming irq line as active during suspend
+
+qcom,smsm
+Required properties:
+-compatible : should be "qcom,smsm"
+-qcom,smsm-edge : the smsm edge
+-qcom,smsm-irq-offset : the offset into the irq register base memory for sending
+ interrupts
+-qcom,smsm-irq-bitmask : the sending irq bitmask
+-interrupts : the receiving interrupt line
+
+
+Example:
+
+ qcom,smem@fa00000 {
+ compatible = "qcom,smem";
+ reg = <0xfa00000 0x200000>,
+ <0xfa006000 0x1000>,
+ <0xfc428000 0x4000>;
+ reg-names = "smem", "irq-reg-base", "aux-mem1";
+
+ qcom,smd-modem {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <0>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1000>;
+ qcom,pil-string = "modem";
+ interrupts = <0 25 1>;
+ };
+
+ qcom,smsm-modem {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <0>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x2000>;
+ interrupts = <0 26 1>;
+ };
+
+ qcom,smd-adsp {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <1>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x100>;
+ qcom,pil-string = "adsp";
+ interrupts = <0 156 1>;
+ };
+
+ qcom,smsm-adsp {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <1>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x200>;
+ interrupts = <0 157 1>;
+ };
+
+ qcom,smd-wcnss {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <6>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x20000>;
+ qcom,pil-string = "wcnss";
+ interrupts = <0 142 1>;
+ };
+
+ qcom,smsm-wcnss {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <6>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x80000>;
+ interrupts = <0 144 1>;
+ };
+
+ qcom,smd-rpm {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <15>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1>;
+ interrupts = <0 168 1>;
+ qcom,irq-no-syspend;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/gpio/qpnp-pin.txt b/Documentation/devicetree/bindings/gpio/qpnp-pin.txt
index 31c3bc2..36ac336 100644
--- a/Documentation/devicetree/bindings/gpio/qpnp-pin.txt
+++ b/Documentation/devicetree/bindings/gpio/qpnp-pin.txt
@@ -94,7 +94,7 @@
QPNP_PIN_OUT_STRENGTH_MED = 2, (GPIO)
QPNP_PIN_OUT_STRENGTH_HIGH = 3, (GPIO)
- - qcom,src-select: select a function for the pin. Certain pins
+ - qcom,src-sel: select a function for the pin. Certain pins
can be paired (shorted) with each other. Some gpio pins
can act as alternate functions.
In the context of gpio, this acts as a source select.
diff --git a/Documentation/devicetree/bindings/i2c/sii8334-i2c.txt b/Documentation/devicetree/bindings/i2c/sii8334-i2c.txt
new file mode 100644
index 0000000..ed45192
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/sii8334-i2c.txt
@@ -0,0 +1,26 @@
+* Silicon Image-8334 MHL Tx
+
+Required properties:
+- compatible: must be "qcom,mhl-sii8334"
+- reg: i2c slave address
+- mhl-intr-gpio: MHL interrupt gpio coming out of sii8334
+- mhl-pwr-gpio: MHL power gpio required for power rails
+- mhl-rst-gpio: MHL reset gpio going into sii8334 for toggling reset pin
+- <supply-name>-supply: phandle to the regulator device tree node.
+
+Example:
+ i2c@f9967000 {
+ sii8334@72 {
+ compatible = "qcom,mhl-sii8334";
+ reg = <0x72>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <82 0x8>;
+ mhl-intr-gpio = <&msmgpio 82 0>;
+ mhl-pwr-gpio = <&msmgpio 12 0>;
+ mhl-rst-gpio = <&pm8941_mpps 8 0>;
+ avcc_18-supply = <&pm8941_l24>;
+ avcc_12-supply = <&pm8941_l2>;
+ smps3a-supply = <&pm8941_s3>;
+ vdda-supply = <&pm8941_l12>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
index 88fca69..bcea355 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/atmel-mxt-ts.txt
@@ -29,6 +29,8 @@
needed
- atmel,need-calibration : specify to indicate whether calibration is
needed during wakeup.
+ - atmel,no-force-update : flag that signifies whether force configuration
+ update is applicable or not
Example:
i2c@f9966000 {
@@ -52,7 +54,8 @@
vcc_i2c-supply = <&pm8941_lvs1>;
atmel,panel-coords = <0 0 479 799>;
atmel,display-coords = <0 0 479 799>;
- atmel,i2c-pull-up = <1>;
+ atmel,i2c-pull-up;
+ atmel,no-force-update;
atmel,dig-reg-support;
atmel,key-codes = <
102 139 0 0 0 0 0 0
diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp.txt b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
index eda7cba..10732cf 100644
--- a/Documentation/devicetree/bindings/leds/leds-qpnp.txt
+++ b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
@@ -4,9 +4,7 @@
controlling LEDs that are part of PMIC on Qualcomm reference
platforms. The PMIC is connected to Host processor via
SPMI bus. This driver supports various LED modules such as
-WLED (white LED), RGB LED and flash LED. The first version of
-the driver supports WLED and other features are added in the
-next versions.
+WLED (white LED), RGB LED and flash LED.
Required Properties:
- compatible : should be "qcom,leds-qpnp"
@@ -26,19 +24,104 @@
Optional properties for WLED:
- qcom,num-strings: number of wled strings supported
-- qcom,ovp_val: over voltage protection threshold,
+- qcom,ovp-val: over voltage protection threshold,
follows enum wled_ovp_threshold
-- qcom,boost_curr_lim: boot currnet limit, follows enum wled_current_bost_limit
-- qcom,ctrl_delay_us: delay in activation of led
-- qcom,dig_mod_gen_en: digital module generator
-- qcom,cs_out_en: current sink output enable
-- qcom,op_fdbck: selection of output as feedback for the boost
-- qcom,cp_select: high pole capacitance
+- qcom,boost-curr-lim: boot currnet limit, follows enum wled_current_bost_limit
+- qcom,ctrl-delay-us: delay in activation of led
+- qcom,dig-mod-gen-en: digital module generator
+- qcom,cs-out-en: current sink output enable
+- qcom,op-fdbck: selection of output as feedback for the boost
+- qcom,cp-select: high pole capacitance
+- linux,default-trigger: trigger the led from external modules such as display
+- qcom,default-state: default state of the led, should be "on" or "off"
+
+Flash is used primarily as a camera or video flash.
+
+Optional properties for flash:
+- qcom,headroom: headroom to use, mV
+- qcom,duration: duration of the flash, ms
+- qcom,clamp-curr: current to clamp at, mA
+- qcom,startup-dly: delay before flashing after flash executed, us
+- qcom,saftey-timer: include for safety timer use, otherwise watchdog timer will be used
+- linux,default-trigger: trigger the led from external modules such as display
+- qcom,default-state: default state of the led, should be "on" or "off"
+
+RGB Led is a tri-colored led, Red, Blue & Green.
+
+Required properties for RGB led:
+- qcom,mode: mode the led should operate in, options 0 = PWM, 1 = LPG
+- qcom,pwm-channel: pwm channel the led will operate on
+- qcom,pwm-us: time the pwm device will modulate at (us)
+
+Required properties for LPG mode only:
+- qcom,duty-ms: duty cycle time the led will operate at (ms)
+- qcom,duty-pcts: array of values for duty cycle to go through
+- qcom,start-idx: starting point duty-pcts array
+
+Optional properties for RGB led:
- linux,default-trigger: trigger the led from external modules such as display
- qcom,default-state: default state of the led, should be "on" or "off"
Example:
+ qcom,leds@d000 {
+ status = "okay";
+ qcom,rgb_pwm {
+ label = "rgb";
+ linux,name = "led:rgb_red";
+ qcom,mode = <0>;
+ qcom,pwm-channel = <6>;
+ qcom,pwm-us = <1000>;
+ qcom,duty-ms = <20>;
+ qcom,start-idx = <1>;
+ qcom,idx-len = <10>;
+ qcom,duty-pcts = [00 19 32 4B 64
+ 64 4B 32 19 00];
+ qcom,max-current = <12>;
+ qcom,default-state = "off";
+ qcom,id = <3>;
+ linux,default-trigger =
+ "battery-charging";
+ };
+
+ qcom,rgb_lpg {
+ label = "rgb";
+ linux,name = "led:rgb_blue";
+ qcom,mode = <1>;
+ qcom,pwm-channel = <4>;
+ qcom,pwm-us = <1000>;
+ qcom,duty-ms = <20>;
+ qcom,start-idx = <1>;
+ qcom,idx-len = <10>;
+ qcom,duty-pcts = [00 19 32 4B 64
+ 64 4B 32 19 00];
+ qcom,max-current = <12>;
+ qcom,default-state = "off";
+ qcom,id = <5>;
+ linux,default-trigger = "none";
+ };
+ };
+
+ qcom,leds@d300 {
+ compatible = "qcom,leds-qpnp";
+ status = "okay";
+ qcom,flash_0 {
+ qcom,max-current = <1000>;
+ qcom,default-state = "off";
+ qcom,headroom = <0>;
+ qcom,duration = <200>;
+ qcom,clamp-curr = <200>;
+ qcom,startup-dly = <1>;
+ qcom,safety-timer;
+ label = "flash";
+ linux,default-trigger =
+ "flash0_trigger";
+ linux,name = "led:flash_0";
+ qcom,current = <625>;
+ qcom,id = <1>;
+ };
+ };
+
qcom,leds@d800 {
compatible = "qcom,leds-qpnp";
status = "okay";
@@ -59,4 +142,3 @@
linux,name = "led:wled_backlight";
};
};
-
diff --git a/Documentation/devicetree/bindings/misc/ti_drv2667.txt b/Documentation/devicetree/bindings/misc/ti_drv2667.txt
new file mode 100644
index 0000000..3a8f4b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/ti_drv2667.txt
@@ -0,0 +1,44 @@
+TI DRV2667 is a haptic controller chip. It can drive piezo haptics
+and can operate in two modes - analog and digital.
+
+Required properties:
+
+-compatible : should be "ti,drv2667".
+-reg : i2c address to be used.
+-vdd-supply : regulator to power the chip.
+-vdd-i2c-supply : regulator to power i2c bus.
+
+Optional properties:
+
+-ti,label : Name to be registered with timedoutput class.
+-ti,mode : Mode to be supported, 0 to 3 - FIFO, RAM, WAVE and ANALOG.
+-ti,wav-seq : Wave Sequence composed of 11 bytes - wave form id,
+ Header size, start upper byte, start lower byte,
+ stop upper byte, stop lower byte, repeat count,
+ amplitude, frequency, duration and envelope
+-ti,gain : Gain to be programmed for the chip.
+-ti,idle-timeout-ms : Idle timeout in ms to be programmed for the chip to go into
+ low power mode after finishing its operation.
+-ti,max-runtime-ms : Maximum time in ms for which chip can drive haptics.
+
+Example:
+ i2c@f9967000 {
+ ti-drv2667@59 {
+ compatible = "ti,drv2667";
+ reg = <0x59>;
+ vdd-supply = <&drv2667_vreg>;
+ vdd-i2c-supply = <&pm8941_s3>;
+ ti,label = "vibrator";
+ ti,gain = <3>;
+ ti,idle-timeout-ms = <20>;
+ ti,max-runtime-ms = <15000>;
+ ti,mode = <2>;
+ ti,wav-seq = [
+ /* wave form id */
+ 01
+ /* header size, start and stop bytes */
+ 05 80 06 00 09
+ /* repeat, amp, freq, duration, envelope */
+ 01 ff 19 02 00];
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mmc/msm_sdcc.txt b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
index 5f7651a..46173a0 100644
--- a/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
+++ b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
@@ -10,42 +10,56 @@
"reg-names" examples are "core_mem", "dml_mem" and "bam_mem"
- interrupts : should contain SDCC core interrupt.
- interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
- "interrupt-names" examples are "core_irq", "bam_irq" and "status_irq"
- - qcom,sdcc-clk-rates : specifies supported SDCC clock frequencies, Units - Hz.
- - qcom,sdcc-sup-voltages: specifies supported voltage ranges for card. Should always be
+ "core_irq" is mandatory, "bam_irq" is mandatory only when BAM DMA engine is used,
+ "status_irq" and "sdiowakeup_irq" are optional.
+ - qcom,clk-rates : specifies supported SDCC clock frequencies, Units - Hz.
+ - qcom,sup-voltages: specifies supported voltage ranges for card. Should always be
specified in pairs (min, max), Units - mV.
- <supply-name>-supply: phandle to the regulator device tree node
"supply-name" examples are "vdd", "vdd-io".
Optional Properties:
- cell-index - defines slot ID.
- - qcom,sdcc-bus-width - defines the bus I/O width that controller supports.
+ - qcom,bus-width - defines the bus I/O width that controller supports.
- wp-gpios - specify GPIO for write protect switch detection.
- cd-gpios - specify GPIO for card detection.
- - qcom,sdcc-nonremovable - specifies whether the card in slot is
+ - qcom,nonremovable - specifies whether the card in slot is
hot pluggable or hard wired.
- - qcom,sdcc-disable_cmd23 - disable sending CMD23 to card when controller can't support it.
- - qcom,sdcc-bus-speed-mode - specifies supported bus speed modes by host.
- - qcom,sdcc-current-limit - specifies max. current the host can drive.
- - qcom,sdcc-xpc - specifies if the host can supply more than 150mA for SDXC cards.
+ - qcom,disable-cmd23 - disable sending CMD23 to card when controller can't support it.
+ - qcom,bus-speed-mode - specifies supported bus speed modes by host.
+ - qcom,current-limit - specifies max. current the host can drive.
+ - qcom,xpc - specifies if the host can supply more than 150mA for SDXC cards.
+ - qcom,dat1-mpm-int - specifies MPM interrupt number corresponding to DAT1 line of SDCC
+ (used only if slot has dedicated DAT1 MSM pin (not GPIO))
In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
- - qcom,sdcc-<supply>-always_on - specifies whether supply should be kept "on" always.
- - qcom,sdcc-<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).
- - qcom,sdcc-<supply>-voltage_level - specifies voltage levels for supply. Should be
+ - qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
+ - qcom,<supply>-lpm-sup - specifies whether supply can be kept in low power mode (lpm).
+ - qcom,<supply>-voltage-level - specifies voltage levels for supply. Should be
specified in pairs (min, max), units uV.
- - qcom,sdcc-<supply>-current_level - specifies load levels for supply in lpm or
+ - qcom,<supply>-current-level - specifies load levels for supply in lpm or
high power mode (hpm). Should be specified in pairs (lpm, hpm), units uA.
- gpios - specifies gpios assigned for sdcc slot.
- - qcom,sdcc-gpio-names - a list of strings that map in order to the list of gpios
+ - qcom,gpio-names - a list of strings that map in order to the list of gpios
A slot has either gpios or dedicated tlmm pins as represented below.
- - qcom,sdcc-pad-pull-on - Active pull configuration for sdc tlmm pins
- - qcom,sdcc-pad-pull-off - Suspend pull configuration for sdc tlmm pins.
- - qcom,sdcc-pad-drv-on - Active drive strength configuration for sdc tlmm pins.
- - qcom,sdcc-pad-drv-off - Suspend drive strength configuration for sdc tlmm pins.
+ - qcom,pad-pull-on - Active pull configuration for sdc tlmm pins
+ - qcom,pad-pull-off - Suspend pull configuration for sdc tlmm pins.
+ - qcom,pad-drv-on - Active drive strength configuration for sdc tlmm pins.
+ - qcom,pad-drv-off - Suspend drive strength configuration for sdc tlmm pins.
Tlmm pins are specified as <clk cmd data>
+ - qcom,bus-bw-vectors-bps - specifies array of throughput values in Bytes/sec. The
+ values in the array are determined according to supported bus speed modes. For example,
+ if host supports SDR12 mode, value is 13631488 Bytes/sec.
+ - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
+ below optional properties:
+ - qcom,msm-bus,name
+ - qcom,msm-bus,num-cases
+ - qcom,msm-bus,active-only
+ - qcom,msm-bus,num-paths
+ - qcom,msm-bus,vectors-KBps
+
Example:
qcom,sdcc@f9600000 {
@@ -57,8 +71,21 @@
0xf9602000 0x2000> // BAM register interface
interrupts = <123>;
- qcom,sdcc-clk-rates = <400000 24000000 48000000>;
- qcom,sdcc-sup-voltages = <2700 3300>;
- qcom,sdcc-bus-width = <8>; //8-bit wide
- qcom,sdcc-nonremovable;
+ qcom,clk-rates = <400000 24000000 48000000>;
+ qcom,sup-voltages = <2700 3300>;
+ qcom,bus-width = <8>; //8-bit wide
+ qcom,nonremovable;
+
+ qcom,msm-bus,name = "sdcc2";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,active-only = <0>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+ <81 512 6656 13312>, /* 13 MB/s*/
+ <81 512 13312 26624>, /* 26 MB/s */
+ <81 512 26624 53248>, /* 52 MB/s */
+ <81 512 53248 106496>, /* 104 MB/s */
+ <81 512 106496 212992>, /* 208 MB/s */
+ <81 512 2147483647 4294967295>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
};
diff --git a/Documentation/devicetree/bindings/net/wireless/ath/ath6kl.txt b/Documentation/devicetree/bindings/net/wireless/ath/ath6kl.txt
new file mode 100644
index 0000000..7b9feae
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/ath/ath6kl.txt
@@ -0,0 +1,24 @@
+* Qualcomm Atheros mobile chipsets
+
+Required properties:
+ - compatible: Can be "qca,ar6004-sdio" for SDIO device and
+ "qca,ar6004-hsic" for HSIC devcie.
+ - qca,chip-pwd-l-gpios: specify GPIO for CHIP_PWD_L.
+
+Optional Properties:
+ - cell-index: WLAN Hardware index.
+ - qca,pm-enable-gpios: Specify this GPIO if internal PMU needs to be used.
+ - qca,ar6004-vbatt-supply: Specify this if VBATT is provided through a
+ regulator.
+ - qca,ar6004-vdd-io-supply: Specify this if VDD-IO is provided through a
+ regulator.
+
+Example:
+
+ wlan0: qca,wlan {
+ cell-index = <0>;
+ compatible = "qca,ar6004-sdio";
+ qca,chip-pwd-l-gpios = <&msmgpio 62 0>;
+ qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;
+ qca,ar6004-vdd-io-supply = <&pm8019_l11>;
+ };
diff --git a/Documentation/devicetree/bindings/pil/pil-mba.txt b/Documentation/devicetree/bindings/pil/pil-mba.txt
deleted file mode 100644
index ce6bb8f..0000000
--- a/Documentation/devicetree/bindings/pil/pil-mba.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Qualcomm Modem Boot Authenticator Peripheral Image Loader
-
-pil-mba is a peripheral image loader (PIL) driver. It is used for loading
-modem images using the self-authenticating hardware and software features
-of the Modem Boot Authenticator.
-
-Required properties:
-- compatible: Must be "qcom,pil-mba"
-- reg: Two pairs of physical base addresses and sizes. The
- first corresponds to the Relay Message Buffer (RMB)
- register base. The second specifies the address at which
- the primary modem image metadata should be stored.
-- reg-names: Names for the above base addresses. "rmb_base" and
- "metadata_base" are expected.
-- interrupts: The modem watchdog interrupt
-- qcom,firmware-name: Base name of the firmware image. Ex. "modem"
-
-Optional properties:
-- qcom,depends-on: firmware-name of a prerequisite image that must already
- be running.
-
-Example:
- qcom,mba@fc820000 {
- compatible = "qcom,pil-mba";
- reg = <0xfc820000 0x0020>,
- <0x0d1f0000 0x4000>;
- reg-names = "rmb_base", "metadata_base";
- interrupts = <0 56 1>;
-
- qcom,firmware-name = "modem";
- qcom,depends-on = "mba";
- };
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index dd59ae8..802716c 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -10,12 +10,15 @@
- reg: Pairs of physical base addresses and region sizes of
memory mapped registers.
- reg-names: Names of the bases for the above registers. "qdsp6_base",
- "halt_base", "rmb_base", and "restart_reg" are expected.
+ "halt_base", "rmb_base", "restart_reg", and
+ "metadata_base" are expected.
+- interrupts: The modem watchdog interrupt
- vdd_mss-supply: Reference to the regulator that supplies the processor.
- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp"
- qcom,pil-self-auth: <0> if the hardware does not require self-authenticating
images and self-authentication is not desired;
<1> if the hardware requires self-authenticating images.
+- qcom,is-loadable: if PIL is required to load the modem image
Example:
qcom,mss@fc880000 {
@@ -23,11 +26,14 @@
reg = <0xfc880000 0x100>,
<0xfd485000 0x400>,
<0xfc820000 0x020>,
- <0xfc401680 0x004>;
+ <0xfc401680 0x004>,
+ <0x0d1f0000 0x4000>;
reg-names = "qdsp6_base", "halt_base", "rmb_base",
- "restart_reg";
+ "restart_reg", metadata_base";
+ interrupts = <0 24 1>;
vdd_mss-supply = <&pm8841_s3>;
+ qcom,is-loadable;
qcom,firmware-name = "mba";
qcom,pil-self-auth = <1>;
};
diff --git a/Documentation/devicetree/bindings/pil/pil-venus.txt b/Documentation/devicetree/bindings/pil/pil-venus.txt
index 4b87f17..232c2cd 100644
--- a/Documentation/devicetree/bindings/pil/pil-venus.txt
+++ b/Documentation/devicetree/bindings/pil/pil-venus.txt
@@ -12,8 +12,6 @@
"vbif_base" are expected.
- vdd-supply: regulator to supply venus.
- qcom,firmware-name: Base name of the firmware image. Ex. "venus"
-- qcom,firmware-min-paddr: The lowest addr boundary for firmware image in DDR
-- qcom,firmware-max-paddr: The highest addr boundary for firmware image in DDR
Example:
qcom,venus@fdce0000 {
@@ -24,7 +22,4 @@
vdd-supply = <&gdsc_venus>;
qcom,firmware-name = "venus";
- qcom,firmware-min-paddr = <0xF500000>;
- qcom,firmware-max-paddr = <0xFA00000>;
-
};
diff --git a/Documentation/devicetree/bindings/platform/msm/ipa.txt b/Documentation/devicetree/bindings/platform/msm/ipa.txt
new file mode 100644
index 0000000..86c60e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/platform/msm/ipa.txt
@@ -0,0 +1,81 @@
+Qualcomm Internet Packet Accelerator
+
+Internet Packet Accelerator (IPA) is a programmable protocol
+processor HW block. It is designed to support generic HW processing
+of UL/DL IP packets for various use cases independent of radio technology.
+
+Required properties:
+
+IPA node:
+
+- compatible : "qcom,ipa"
+- reg: Specifies the base physical addresses and the sizes of the IPA
+ registers.
+- reg-names: "ipa-base" - string to identify the IPA CORE base registers.
+ "bam-base" - string to identify the IPA BAM base registers.
+- interrupts: Specifies the interrupt associated with IPA.
+- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
+ "bam-irq" - string to identify the IPA BAM interrupt.
+
+IPA pipe sub nodes (A2 static pipes configurations):
+
+-label: two labels are supported, a2-to-ipa and ipa-to-a2 which
+supply static configuration for A2-IPA connection.
+-qcom,src-bam-physical-address: The physical address of the source BAM
+-qcom,ipa-bam-mem-type:The memory type:
+ 0(Pipe memory), 1(Private memory), 2(System memory)
+-qcom,src-bam-pipe-index: Source pipe index
+-qcom,dst-bam-physical-address: The physical address of the
+ destination BAM
+-qcom,dst-bam-pipe-index: Destination pipe index
+-qcom,data-fifo-offset: Data fifo base offset
+-qcom,data-fifo-size: Data fifo size (bytes)
+-qcom,descriptor-fifo-offset: Descriptor fifo base offset
+-qcom,descriptor-fifo-size: Descriptor fifo size (bytes)
+
+Optional properties:
+-qcom,ipa-pipe-mem: Specifies the base physical address and the
+ size of the IPA pipe memory region.
+ Pipe memory is a feature which may be supported by the
+ target (HW platform). The Driver support using pipe
+ memory instead of system memory. In case this property
+ will not appear in the IPA DTS entry, the driver will
+ use system memory.
+
+Example:
+
+qcom,ipa@fd4c0000 {
+ compatible = "qcom,ipa";
+ reg = <0xfd4c0000 0x26000>,
+ <0xfd4c4000 0x14818>;
+ reg-names = "ipa-base", "bam-base";
+ interrupts = <0 252 0>,
+ <0 253 0>;
+ interrupt-names = "ipa-irq", "bam-irq";
+
+ qcom,pipe1 {
+ label = "a2-to-ipa";
+ qcom,src-bam-physical-address = <0xfc834000>;
+ qcom,ipa-bam-mem-type = <0>;
+ qcom,src-bam-pipe-index = <1>;
+ qcom,dst-bam-physical-address = <0xfd4c0000>;
+ qcom,dst-bam-pipe-index = <6>;
+ qcom,data-fifo-offset = <0x1000>;
+ qcom,data-fifo-size = <0xd00>;
+ qcom,descriptor-fifo-offset = <0x1d00>;
+ qcom,descriptor-fifo-size = <0x300>;
+ };
+
+ qcom,pipe2 {
+ label = "ipa-to-a2";
+ qcom,src-bam-physical-address = <0xfd4c0000>;
+ qcom,ipa-bam-mem-type = <0>;
+ qcom,src-bam-pipe-index = <7>;
+ qcom,dst-bam-physical-address = <0xfc834000>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x00>;
+ qcom,data-fifo-size = <0xd00>;
+ qcom,descriptor-fifo-offset = <0xd00>;
+ qcom,descriptor-fifo-size = <0x300>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/power/bq28400-battery.txt b/Documentation/devicetree/bindings/power/bq28400-battery.txt
index 3879b4d..1460d70 100644
--- a/Documentation/devicetree/bindings/power/bq28400-battery.txt
+++ b/Documentation/devicetree/bindings/power/bq28400-battery.txt
@@ -5,13 +5,13 @@
The device is usually embedded inside the "smart battery" pack.
node required properties:
-- compatible: Must be "ti,bq28400-battery".
+- compatible: Must be "ti,bq28400-battery" or "ti,bq30z55-battery"
- reg: I2C Address must be 0xb.
Example:
i2c@f9967000 {
battery@b {
- compatible = "ti,bq28400-battery";
+ compatible = "ti,bq28400-battery", "ti,bq30z55-battery";
reg = <0xb>;
};
};
diff --git a/Documentation/devicetree/bindings/power/qpnp-bms.txt b/Documentation/devicetree/bindings/power/qpnp-bms.txt
index 1d3c2db..4d571eb 100644
--- a/Documentation/devicetree/bindings/power/qpnp-bms.txt
+++ b/Documentation/devicetree/bindings/power/qpnp-bms.txt
@@ -36,12 +36,34 @@
- qcom,bms-adjust-soc-low-threshold : The low threshold for the "flat portion"
of the charging curve. The BMS will not adjust SoC
based on voltage during this time.
-- qcom,bms-adjust-soc-high-threshold : The high threshold for the "flat
+- qcom,bms-adjust-soc-high-threshold : The high threshold for the "flat
portion" of the charging curve. The BMS will not
adjust SoC based on voltage during this time.
+- qcom,bms-low-soc-calculate-soc-threshold : The SoC threshold for when
+ the period calculate_soc work speeds up. This ensures
+ SoC is updated in userspace constantly when we are near
+ shutdown.
+- qcom,bms-low-soc-calculate-soc-ms : The time period between subsequent
+ SoC recalculations when the current SoC is below
+ qcom,bms-low-soc-calculate-soc-threshold.
+- qcom,bms-soc-calculate-soc-ms : The time period between subsequent SoC
+ recalculations when the current SoC is above or equal
+ qcom,bms-low-soc-calculate-soc-threshold.
- qcom,bms-chg-term-ua : current in micro-amps when charging is considered done.
As soon as current passes this point, charging is
stopped.
+- qcom,bms-batt-type: Type of battery used. This is an integer that corresponds
+ to the enum defined in
+ include/linux/mfd/pm8xxx/batterydata-lib.h
+
+Optional properties:
+- qcom,bms-ignore-shutdown-soc: A boolean that controls whether BMS will
+ try to force the startup SoC to be the same as the
+ shutdown SoC. Defining it will make BMS ignore the
+ shutdown SoC.
+- qcom,bms-use-voltage-soc : A boolean that controls whether BMS will use
+ voltage-based SoC instead of a coulomb counter based
+ one. Voltage-based SoC will not guarantee linearity.
Example:
bms@4000 {
@@ -76,5 +98,10 @@
qcom,bms-shutdown-soc-valid-limit = <20>;
qcom,bms-adjust-soc-low-threshold = <25>;
qcom,bms-adjust-soc-high-threshold = <45>;
+ qcom,bms-low-soc-calculate-soc-threshold = <15>;
+ qcom,bms-low-soc-calculate-soc-ms = <5000>;
+ qcom,bms-calculate-soc-ms = <20000>;
qcom,bms-chg-term-ua = <100000>;
+ qcom,bms-batt-type = <0>;
+ qcom,bms-ignore-shutdown-soc;
};
diff --git a/Documentation/devicetree/bindings/power/smb137c-charger.txt b/Documentation/devicetree/bindings/power/smb137c-charger.txt
new file mode 100644
index 0000000..c0c4333
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/smb137c-charger.txt
@@ -0,0 +1,86 @@
+Summit SMB137C Battery Charger
+
+The SMB137C is controlled via an I2C bus. Its 7-bit I2C slave address is
+programmed during manufacturing.
+
+Required properties:
+- compatible: Must be "summit,smb137c".
+- reg: The device's 7-bit I2C address.
+
+Optional properties:
+- summit,chg-current-ma Maximum battery charging current in milliamps.
+ Supported values are: 500, 650, 750, 850, 950,
+ 1100, 1300, and 1500.
+- summit,term-current-ma Charging terminaton current in milliamps.
+ Supported values are: 0, 35, 50, 100, and 150.
+ A value of 0 means no termination current is
+ used.
+- summit,pre-chg-current-ma Maximum battery pre-charging current in
+ milliamps. This current limit is applied while
+ the battery voltage is below the pre-charge /
+ fast-charge threshold. Supported values are:
+ 50, 100, 150, and 200.
+- summit,float-voltage-mv Battery voltage threshold in millivolts at which
+ point charging switches from constant current to
+ constant voltage. Supported values are: 3460 up
+ through 4730 in 10 mV steps.
+- summit,thresh-voltage-mv Threshold voltage in millivolts which is used to
+ switch between pre-charge and fast-charge
+ current limits. Supported values are: 2400 up
+ to 3100 in 100 mV steps.
+- summit,recharge-thresh-mv Specifies the minimum voltage drop in millivolts
+ below the float voltage that is required in
+ order to initiate a new charging cycle.
+ Supported values are: 75 and 120.
+- summit,system-voltage-mv Regulated voltage output on the VOUTL pin in
+ millivolts. Supported values are 4250 and 4460.
+- summit,charging-timeout Maximum duration in minutes that a single charge
+ cycle may last. Supported values are: 0, 382,
+ 764, and 1527. A value of 0 means that no
+ charge cycle timeout is used and charging can
+ continue indefinitely.
+- summit,pre-charge-timeout Maximum time in minutes spent in the pre-charge
+ state in any given charge cycle. Supports
+ values are: 0, 48, 95, and 191. A value of 0
+ means that there is no limit to the amount of
+ time that may be spent in the pre-charge state.
+- summit,therm-current-ua Thermistor current in microamps to be used for
+ battery temperature monitoring. Supported
+ values are 10, 20, 40, and 100. These values
+ correspond to 100, 50, 25, and 10 kohm NTC
+ thermistors respectively.
+- summit,temperature-min Specifies the minimum temperature at which
+ charging is allowed. Supported values are
+ 0 to 7. These values correspond to -20 C to
+ +15 C in 5 C increments for an NTC thermistor
+ with beta = 4400.
+- summit,temperature-max Specifies the maximum temperature at which
+ charging is allowed. Supported values are
+ 0 to 7. These values correspond to +30 C to
+ +65 C in 5 C increments for an NTC thermistor
+ with beta = 4400.
+
+Note: If an optional property is not specified, then the hardware default value
+will be used.
+
+Example:
+/ {
+ i2c@f9925000 {
+ charger@57 {
+ compatible = "summit,smb137c";
+ reg = <0x57>;
+ summit,chg-current-ma = <1500>;
+ summit,term-current-ma = <50>;
+ summit,pre-chg-current-ma = <100>;
+ summit,float-voltage-mv = <4200>;
+ summit,thresh-voltage-mv = <3000>;
+ summit,recharge-thresh-mv = <75>;
+ summit,system-voltage-mv = <4250>;
+ summit,charging-timeout = <382>;
+ summit,pre-charge-timeout = <48>;
+ summit,therm-current-ua = <10>;
+ summit,temperature-min = <4>; /* 0 C */
+ summit,temperature-max = <3>; /* 45 C */
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/prng/msm-rng.txt b/Documentation/devicetree/bindings/prng/msm-rng.txt
index 3d55808..28dfe50 100644
--- a/Documentation/devicetree/bindings/prng/msm-rng.txt
+++ b/Documentation/devicetree/bindings/prng/msm-rng.txt
@@ -4,9 +4,13 @@
- compatible : Should be "qcom,msm-rng"
- reg : Offset and length of the register set for the device
+Optional property:
+- qcom,msm-rng-iface-clk : If the device uses iface-clk.
+
Example:
- qcom,msm-rng@f9bff000 {
- compatible = "qcom,msm-rng";
- reg = <0xf9bff000 0x200>;
- };
+ qcom,msm-rng@f9bff000 {
+ compatible = "qcom,msm-rng";
+ reg = <0xf9bff000 0x200>;
+ qcom,msm-rng-iface-clk;
+ };
diff --git a/Documentation/devicetree/bindings/regulator/krait-regulator.txt b/Documentation/devicetree/bindings/regulator/krait-regulator.txt
new file mode 100644
index 0000000..fddae80
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/krait-regulator.txt
@@ -0,0 +1,27 @@
+Krait Voltage regulators
+
+Required properties:
+- compatible: Must be "qcom,krait-regulator"
+- reg: Specifies the address and size for this regulator device
+- qcom,headroom-voltage: The minimum required voltage drop between the input
+ voltage and the output voltage for the LDO to be
+ operational, in microvolts
+- qcom,retention-voltage: The value for retention voltage in microvolts
+- qcom,ldo-default-voltage: The default value for LDO voltage in microvolts
+- qcom,ldo-threshold-voltage: The voltage value above which LDO is nonfunctional
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+ krait0_vreg: regulator@f9088000 {
+ compatible = "qcom,krait-regulator";
+ regulator-name = "krait0";
+ reg = <0xf9088000 0x1000>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ qcom,headroom-voltage = <150000>;
+ qcom,retention-voltage = <745000>;
+ qcom,ldo-default-voltage = <745000>;
+ qcom,ldo-threshold-voltage = <750000>;
+ };
diff --git a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt b/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
index ecac09d..6b090fa 100644
--- a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
+++ b/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
@@ -1,4 +1,19 @@
Qualcomm SLIMBUS controller
+Qualcomm implements 2 type of slimbus controllers:
+1. "qcom,slim-msm": This controller is used if applications processor
+ driver is controlling slimbus master component. This driver is
+ responsible for communicating with slave HW directly using
+ messaging interface, and doing data channel management. Driver
+ also communicates with satellite component (driver implemented
+ by other execution environment, such as ADSP) to get its
+ requirements for data channel and bandwidth requirements.
+2. "qcom,slim-ngd": This controller is used if applications processor
+ driver is controlling slimbus satellite component (also known as
+ Non-ported Generic Device, or NGD). This is light-weight slimbus
+ controller responsible for communicating with slave HW directly
+ over bus messaging interface, and communicating with master component
+ (driver residing on other execution environment, such as ADSP)
+ for bandwidth and data channel management.
Required properties:
@@ -8,7 +23,8 @@
"slimbus_physical": Physical adderss of controller register blocks
"slimbus_bam_physical": Physical address of Bus Access Module (BAM)
for this controller
- - compatible : should be "qcom,slim-msm"
+ - compatible : should be "qcom,slim-msm" if this is master component driver
+ - compatible : should be "qcom,slim-ngd" if this is satellite component driver
- cell-index : SLIMBUS number used for this controller
- interrupts : Interrupt numbers used by this controller
- interrupt-names : Required interrupt resource entries are:
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index 9743d0d..1e647a7 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -212,6 +212,36 @@
qcom,msm-dai-q6-dev-id = <16385>;
};
+ qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
qcom,msm-dai-q6-bt-sco-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12288>;
@@ -351,3 +381,96 @@
taiko-mclk-clk = <&pm8941_clkdiv1>;
qcom,taiko-mclk-clk-freq = <9600000>;
};
+
+* msm-dai-mi2s
+
+[First Level Nodes]
+
+Required properties:
+
+ - compatible : "msm-dai-mi2s"
+
+ [Second Level Nodes]
+
+Required properties:
+
+ - compatible : "qcom,msm-dai-q6-mi2s"
+ - qcom,msm-dai-q6-mi2s-dev-id: MSM or MDM can use Slimbus or I2S interface to transfer data
+ to (WCD9XXX) codec. If slimbus interface is used then
+ "msm-dai-q6" needs to be filled with correct data for slimbus
+ interface. The sections "msm-dai-mi2s" is used by MDM or MSM
+ to use I2S interface with codec. This section is used by CPU
+ driver in ASOC MSM to configure MI2S interface. MSM internally
+ has multiple MI2S namely Primary, Secondary, Tertiary and
+ Quaternary MI2S. They are represented with id 0, 1, 2, 3
+ respectively. The field "qcom,msm-dai-q6-mi2s-dev-id" represents
+ which of the MI2S block is used. These MI2S are connected to I2S
+ interface.
+
+ - qcom,msm-mi2s-rx-lines: Each MI2S interface in MSM has one or more SD lines. These lines
+ are used for data transfer between codec and MSM. This element in
+ indicates which output RX lines are used in the MI2S interface.
+
+ - qcom,msm-mi2s-tx-lines: Each MI2S interface in MSM has one or more SD lines. These lines
+ are used for data transfer between codec and MSM. This element in
+ indicates which input TX lines are used in the MI2S interface.
+
+Example:
+
+qcom,msm-dai-mi2s {
+ compatible = "qcom,msm-dai-mi2s";
+ qcom,msm-dai-q6-mi2s-prim {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <0>;
+ qcom,msm-mi2s-rx-lines = <2>;
+ qcom,msm-mi2s-tx-lines = <1>;
+ };
+};
+
+* MSM9625 ASoC Machine driver
+
+Required properties:
+- compatible : "qcom,mdm9625-audio-taiko"
+- qcom,model : The user-visible name of this sound card.
+- qcom,audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source.
+- qcom,taiko-mclk-clk-freq : Master clock value given to codec. Some WCD9XXX
+ codec can run at different mclk values. Mclk value can be 9.6MHz or 12.288MHz.
+ This element represents the value for MCLK provided to codec.
+
+Example:
+
+sound {
+ compatible = "qcom,mdm9625-audio-taiko";
+ qcom,model = "mdm9625-taiko-i2s-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,taiko-mclk-clk-freq = <12288000>;
+};
diff --git a/Documentation/devicetree/bindings/sound/taiko_codec.txt b/Documentation/devicetree/bindings/sound/taiko_codec.txt
index 96e3a61..090d8db 100644
--- a/Documentation/devicetree/bindings/sound/taiko_codec.txt
+++ b/Documentation/devicetree/bindings/sound/taiko_codec.txt
@@ -22,12 +22,14 @@
- qcom,cdc-micbias-cfilt1-mv - cfilt1 output voltage in milli volts.
- qcom,cdc-micbias-cfilt2-mv - cfilt2 output voltage in milli volts.
- qcom,cdc-micbias-cfilt3-mv - cfilt3 output voltage in milli volts.
- cfilt volatge can be set to max of qcom,cdc-micbias-ldoh-v - 0.15V.
+ cfilt voltage can be set to max of qcom,cdc-micbias-ldoh-v - 0.15V.
- qcom,cdc-micbias1-cfilt-sel = cfilt to use for micbias1 (should be from 1 to 3).
- qcom,cdc-micbias2-cfilt-sel = cfilt to use for micbias2 (should be from 1 to 3).
- qcom,cdc-micbias3-cfilt-sel = cfilt to use for micbias3 (should be from 1 to 3).
- qcom,cdc-micbias4-cfilt-sel = cfilt to use for micbias4 (should be from 1 to 3).
+ This value represents the connected CFLIT to MIC Bias.
+
- qcom,cdc-micbias1-ext-cap: Boolean. Enable micbias 1 external capacitor mode.
- qcom,cdc-micbias2-ext-cap: Boolean. Enable micbias 2 external capacitor mode.
- qcom,cdc-micbias3-ext-cap: Boolean. Enable micbias 3 external capacitor mode.
@@ -88,3 +90,109 @@
qcom,cdc-slim-ifd = "taiko-slim-ifd";
qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 00 17 02];
};
+
+Wcd9xxx audio CODEC in I2C mode
+
+ - compatible = "qcom,wcd9xxx-i2c-device";
+ - reg: represents the slave address provided to the I2C driver.
+ - qcom,cdc-reset-gpio: gpio used for codec SOC reset.
+ - <supply-name>-supply: phandle to the regulator device tree node.
+ - qcom,<supply-name>-voltage - specifies voltage levels for supply. Should be
+ specified in pairs (min, max), units mV.
+ - qcom,<supply-name>-current - specifies max current in mA that can drawn
+ from the <supply-name>.
+
+ above three properties with "supply-name" set to "qcom,cdc-vdd-buck", "qcom,cdc-vdd-tx-h",
+ "qcom,cdc-vdd-rx-h", "qcom,cdc-vddpx-1", "qcom,cdc-vdd-a-1p2v", "qcom,cdc-vddcx-1",
+ "qcom,cdc-vddcx-2" should be present.
+
+ - qcom,cdc-micbias-ldoh-v - LDOH output in volts ( should be 1.95 V and 3.00 V).
+
+ - qcom,cdc-micbias-cfilt1-mv - cfilt1 output voltage in milli volts.
+ - qcom,cdc-micbias-cfilt2-mv - cfilt2 output voltage in milli volts.
+ - qcom,cdc-micbias-cfilt3-mv - cfilt3 output voltage in milli volts.
+ cfilt voltage can be set to max of qcom,cdc-micbias-ldoh-v - 0.15V.
+
+ - qcom,cdc-micbias1-cfilt-sel = cfilt to use for micbias1 (should be from 1 to 3).
+ - qcom,cdc-micbias2-cfilt-sel = cfilt to use for micbias2 (should be from 1 to 3).
+ - qcom,cdc-micbias3-cfilt-sel = cfilt to use for micbias3 (should be from 1 to 3).
+ - qcom,cdc-micbias4-cfilt-sel = cfilt to use for micbias4 (should be from 1 to 3).
+ This value represents the connected CFLIT to MIC Bias.
+
+ - qcom,cdc-micbias1-ext-cap: Boolean. Enable micbias 1 external capacitor mode.
+ - qcom,cdc-micbias2-ext-cap: Boolean. Enable micbias 2 external capacitor mode.
+ - qcom,cdc-micbias3-ext-cap: Boolean. Enable micbias 3 external capacitor mode.
+ - qcom,cdc-micbias4-ext-cap: Boolean. Enable micbias 4 external capacitor mode.
+
+Example:
+i2c@f9925000 {
+ cell-index = <3>;
+ compatible = "qcom,i2c-qup";
+ reg = <0xf9925000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ interrupts = <0 97 0>;
+ interrupt-names = "qup_err_intr";
+ qcom,i2c-bus-freq = <100000>;
+ qcom,i2c-src-freq = <24000000>;
+
+ wcd9xxx_codec@0d{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x0d>;
+ qcom,cdc-reset-gpio = <&msmgpio 22 0>;
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
+
+ cdc-vdd-buck-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <25000>;
+
+ cdc-vdd-tx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-tx-h-current = <25000>;
+
+ cdc-vdd-rx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rx-h-current = <25000>;
+
+ cdc-vddpx-1-supply = <&pm8019_l11>;
+ qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
+ qcom,cdc-vddpx-1-current = <10000>;
+
+ cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
+ qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-a-1p2v-current = <10000>;
+
+ cdc-vddcx-1-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-1-current = <10000>;
+
+ cdc-vddcx-2-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-2-current = <10000>;
+
+ qcom,cdc-micbias-ldoh-v = <0x3>;
+ qcom,cdc-micbias-cfilt1-mv = <1800>;
+ qcom,cdc-micbias-cfilt2-mv = <2700>;
+ qcom,cdc-micbias-cfilt3-mv = <1800>;
+ qcom,cdc-micbias1-cfilt-sel = <0x0>;
+ qcom,cdc-micbias2-cfilt-sel = <0x1>;
+ qcom,cdc-micbias3-cfilt-sel = <0x2>;
+ qcom,cdc-micbias4-cfilt-sel = <0x2>;
+ };
+
+ wcd9xxx_codec@77{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x77>;
+ };
+
+ wcd9xxx_codec@66{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x66>;
+ };
+ wcd9xxx_codec@55{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x55>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
index 3b0426b..ae7d736 100644
--- a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
+++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
@@ -34,9 +34,19 @@
- reg : offset and length of the register set for the device.
- interrupts : should contain the uart interrupt.
-Example:
+Aliases:
+An alias may optionally be used to bind the serial device to a tty device
+(ttyHSLx) with a given line number. Aliases are of the form serial<n> where <n>
+is an integer representing the line number to use. On systems with multiple
+serial devices present it is recommended that an alias be defined for each such
+device.
- serial@19c400000 {
+Example:
+ aliases {
+ serial0 = &uart0; // This device will be called ttyHSL0
+ };
+
+ uart0: serial@19c400000 {
compatible = "qcom,msm-lsuart-v14"
reg = <0x19c40000 0x1000">;
interrupts = <195>;
diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 186a58d..7bff0f2 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -81,13 +81,16 @@
- compatible: should be "qcom,android-usb"
Optional properties :
-- reg : offset and length of memory region that is used by driver to
+- reg : offset and length of memory region that is used by device to
update USB PID and serial numbers used by bootloader in DLOAD mode.
+- qcom,android-usb-swfi-latency : value to be used by device to vote
+ for DMA latency in microsecs.
Example Android USB device node :
android_usb@fc42b0c8 {
compatible = "qcom,android-usb";
reg = <0xfc42b0c8 0xc8>;
+ qcom,android-usb-swfi-latency = <1>;
};
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
index 99274d5..57d776f 100644
--- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -28,8 +28,10 @@
- interrupt-names : Optional interrupt resource entries are:
"hs_phy_irq" : Interrupt from HSPHY for asynchronous events in LPM.
This is not used if wakeup events are received externally (e.g. PMIC)
-- qcom,dwc-usb3-msm-otg-capability: If present then depends on PMIC
- for VBUS notifications, otherwise depends on PHY.
+- qcom,otg-capability: If present then depend on PMIC for VBUS notifications,
+ otherwise depend on PHY.
+- qcom,charging-disabled: If present then battery charging using USB
+ is disabled.
Example MSM USB3.0 controller device node :
usb@f9200000 {
diff --git a/Documentation/trace/events-msm-low-power.txt b/Documentation/trace/events-msm-low-power.txt
new file mode 100644
index 0000000..5414146
--- /dev/null
+++ b/Documentation/trace/events-msm-low-power.txt
@@ -0,0 +1,57 @@
+Subsystem Trace Points: msm_low_power
+
+The msm_low_power tracing system captures the events during the entry
+and exit of various low power modes like power collapse, standalone
+power collapse, retention and wfi. The tracing system adds the following
+events to capture the state of the low power mode.
+
+1) msm_pm_enter
+===================
+msm_pm_enter: cpu: %u latency: %uus sleep: %uus
+msm_pm_enter_pc: cpu: %u latency: %uus sleep: %uus wake_up: %u
+msm_pm_enter_ret: cpu: %u latency: %uus sleep: %uus wake_up: %u
+msm_pm_enter_spc: cpu: %u latency: %uus sleep: %uus wake_up: %u
+msm_pm_enter_wfi: cpu: %u latency: %uus sleep: %uus wake_up: %u
+
+The event captures various parameters during the entry into low power
+modes.
+
+The 'cpu' parameter represents the cpu on which the low power mode is
+chosen.
+
+The 'latency_us' parameter represents the system latency at the time of
+choosing the low power mode.
+
+The 'sleep_us' parameter tells the maximum amount of time the kernel can
+sleep in this low power mode.
+
+The 'wake_up' parameter tells if there was any immediate wakeup required
+before entering low power mode.
+
+2) msm_pm_exit
+=================
+msm_pm_exit: cpu:%u success:%d
+msm_pm_exit_pc: cpu:%u success:%d
+msm_pm_exit_ret: cpu:%u success:%d
+msm_pm_exit_spc: cpu:%u success:%d
+msm_pm_exit_wfi: cpu:%u success:%d
+
+The event captures parameters during the exit of the low power modes.
+
+The 'cpu' parameter represents the cpu on which the low power mode is chosen.
+
+The 'success' parameter shows the state of power collapse/standalone power
+collapse. It will be set if power collapse/standalone power collapse were
+successful. For the rest of the low power modes it is set to one.
+
+3) lpm_resources
+=================
+lpm_resources: name:%s sleep_value:%d
+
+This event captures parameters for each of the lpm resources.
+
+The 'name' parameter represents the name of the lpm resource and it can hold
+l2, pxo, vdd mem, vdd dig depending on the resource chosen during power
+collapse.
+
+The 'sleep_value' parameter corresponds to the sleep value set for the resource.
diff --git a/Documentation/trace/events-rpm-smd.txt b/Documentation/trace/events-rpm-smd.txt
new file mode 100644
index 0000000..f6c6bef
--- /dev/null
+++ b/Documentation/trace/events-rpm-smd.txt
@@ -0,0 +1,43 @@
+Subsystem Trace Points: rpm_smd
+
+The rpm-smd tracing system captures the events related to sending/receiving
+messages to/from RPM hardware. The tracing system adds the following events to
+capture the transactions with the RPM driver.
+
+1) RPM send message
+===================
+rpm_send_message: ctx:%s set:%s rsc_type:0%x(%s),rsc_id:i0x%x, id:%u
+
+The event captures the parameters of the message that was sent to the RPM.
+
+The 'ctx' parameters takes one of the following string constants to indicate
+if the request was made in atomic/non-atomic context.
+ . "sleep" - non-atomic context
+ . "noslp" - atomic context
+
+The 'set' parameter takes one of the following string values to indicate if
+the message affects active or sleep set value of the resource
+ . "act" - active set configuraion
+ . "slp" - sleep set configuration
+
+The 'rsc_type' and 'rsc_id' identify the resource whose parametes is being
+modified. The 4 bytes string equivalent of the resource type is also displayed
+for easier identification of resources.
+
+The 'id' parameter is the id that RPM uses to acknowledge the receipt of the
+message in its ACK message
+
+
+2) RPM ack message
+=================
+rpm_ack_recd: ctx:%s id:%u
+
+The event captures the acknowledgement messages received from the RPM after
+successfully send a message request.
+
+The 'ctx' parameter has the same string constants referred to the "RPM Send
+Message"
+
+The 'id' parameter is the id that RPM uses to acknowledge the receipt of the
+message in its ACK message
+
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d5f9de..89c7417 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -264,6 +264,29 @@
def_bool y
depends on BUG
+config GENERIC_TIME_VSYSCALL
+ bool "Enable gettimeofday updates"
+ depends on CPU_V7
+ help
+ Enables updating the kernel user helper area with the xtime struct
+ data for gettimeofday via kernel user helpers.
+
+config ARM_USE_USER_ACCESSIBLE_TIMERS
+ bool "Enables mapping a timer counter page to user space"
+ depends on USE_USER_ACCESSIBLE_TIMERS && GENERIC_TIME_VSYSCALL
+ help
+ Enables ARM-specific user-accessible timers via a shared
+ memory page containing the cycle counter.
+
+config ARM_USER_ACCESSIBLE_TIMER_BASE
+ hex "Base address of user-accessible timer counter page"
+ default 0xfffef000
+ depends on ARM_USE_USER_ACCESSIBLE_TIMERS
+ help
+ Specify the base user-space virtual address where the user-accessible
+ timer counter page should be mapped by the kernel. User-space apps
+ will read directly from the page at this address.
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
diff --git a/arch/arm/boot/dts/mpq8092-regulator.dtsi b/arch/arm/boot/dts/mpq8092-regulator.dtsi
index fbc9586..b724a3d 100644
--- a/arch/arm/boot/dts/mpq8092-regulator.dtsi
+++ b/arch/arm/boot/dts/mpq8092-regulator.dtsi
@@ -159,7 +159,7 @@
};
pm8644_l13: regulator@4c00 {
- regulator-min-microvolt = <2950000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
qcom,enable-time = <200>;
qcom,pull-down-enable = <1>;
diff --git a/arch/arm/boot/dts/mpq8092.dtsi b/arch/arm/boot/dts/mpq8092.dtsi
index 470d540..502d34a 100644
--- a/arch/arm/boot/dts/mpq8092.dtsi
+++ b/arch/arm/boot/dts/mpq8092.dtsi
@@ -65,6 +65,7 @@
/* 190,ee0_krait_hlos_spmi_periph_irq */
/* 187,channel_0_krait_hlos_trans_done_irq */
interrupts = <0 190 0 0 187 0>;
+ qcom,not-wakeup;
qcom,pmic-arb-ee = <0>;
qcom,pmic-arb-channel = <0>;
qcom,pmic-arb-ppid-map = <0x00100000>, /* PM8644_0 */
@@ -237,16 +238,16 @@
interrupts = <0 123 0>;
interrupt-names = "core_irq";
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <8>;
- qcom,sdcc-nonremovable;
- qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <8>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
};
sdcc2: qcom,sdcc@f98a4000 {
@@ -257,19 +258,47 @@
interrupts = <0 125 0>;
interrupt-names = "core_irq";
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-xpc;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
- qcom,sdcc-current-limit = <800>;
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <4>;
+ qcom,xpc;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+ qcom,current-limit = <800>;
};
};
+&gdsc_venus {
+ status = "ok";
+};
+
+&gdsc_mdss {
+ status = "ok";
+};
+
+&gdsc_jpeg {
+ status = "ok";
+};
+
+&gdsc_vfe {
+ status = "ok";
+};
+
+&gdsc_oxili_gx {
+ status = "ok";
+};
+
+&gdsc_oxili_cx {
+ status = "ok";
+};
+
+&gdsc_usb_hsic {
+ status = "ok";
+};
+
/include/ "msm-pm8644.dtsi"
/include/ "mpq8092-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm-gdsc.dtsi b/arch/arm/boot/dts/msm-gdsc.dtsi
index f83fe76..f0570ba 100644
--- a/arch/arm/boot/dts/msm-gdsc.dtsi
+++ b/arch/arm/boot/dts/msm-gdsc.dtsi
@@ -18,41 +18,48 @@
compatible = "qcom,gdsc";
regulator-name = "gdsc_venus";
reg = <0xfd8c1024 0x4>;
+ status = "disabled";
};
gdsc_mdss: qcom,gdsc@fd8c2304 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_mdss";
reg = <0xfd8c2304 0x4>;
+ status = "disabled";
};
gdsc_jpeg: qcom,gdsc@fd8c35a4 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_jpeg";
reg = <0xfd8c35a4 0x4>;
+ status = "disabled";
};
gdsc_vfe: qcom,gdsc@fd8c36a4 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_vfe";
reg = <0xfd8c36a4 0x4>;
+ status = "disabled";
};
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_oxili_gx";
reg = <0xfd8c4024 0x4>;
+ status = "disabled";
};
gdsc_oxili_cx: qcom,gdsc@fd8c4034 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_oxili_cx";
reg = <0xfd8c4034 0x4>;
+ status = "disabled";
};
gdsc_usb_hsic: qcom,gdsc@fc400404 {
compatible = "qcom,gdsc";
regulator-name = "gdsc_usb_hsic";
reg = <0xfc400404 0x4>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index de30884..89d4df8 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -58,10 +58,10 @@
};
};
- bms@4000 {
+ pm8941_bms: bms@4000 {
#address-cells = <1>;
#size-cells = <1>;
-
+ status = "disabled";
compatible = "qcom,qpnp-bms";
reg = <0x4000 0x100>;
@@ -90,7 +90,12 @@
qcom,bms-shutdown-soc-valid-limit = <20>;
qcom,bms-adjust-soc-low-threshold = <25>;
qcom,bms-adjust-soc-high-threshold = <45>;
+ qcom,bms-low-soc-calculate-soc-threshold = <15>;
+ qcom,bms-low-soc-calculate-soc-ms = <5000>;
+ qcom,bms-calculate-soc-ms = <20000>;
qcom,bms-chg-term-ua = <100000>;
+ qcom,bms-batt-type = <0>;
+ qcom,bms-use-voltage-soc;
};
clkdiv@5b00 {
@@ -136,14 +141,14 @@
<0x0 0x10 0x6>,
<0x0 0x10 0x7>;
- interrupt-names = "chg-done",
- "chg-failed",
- "fast-chg-on",
- "trkl-chg-on",
- "state-change",
- "chgwdog",
+ interrupt-names = "vbat-det-lo",
"vbat-det-hi",
- "vbat-det-lo";
+ "chgwdog",
+ "state-change",
+ "trkl-chg-on",
+ "fast-chg-on",
+ "chg-failed",
+ "chg-done";
};
qcom,chg-buck@1100 {
@@ -157,13 +162,13 @@
<0x0 0x11 0x5>,
<0x0 0x11 0x6>;
- interrupt-names = "vdd-loop",
- "ibat-loop",
- "ichg-loop",
- "vchg-loop",
+ interrupt-names = "vbat-ov",
+ "vreg-ov",
"overtemp",
- "vref-ov",
- "vbat-ov";
+ "vchg-loop",
+ "ichg-loop",
+ "ibat-loop",
+ "vdd-loop";
};
qcom,chg-bat-if@1200 {
@@ -175,11 +180,12 @@
<0x0 0x12 0x3>,
<0x0 0x12 0x4>;
- interrupt-names = "psi",
- "vcp-on",
- "bat-fet-on",
+ interrupt-names = "batt-pres",
"bat-temp-ok",
- "batt-pres";
+ "bat-fet-on",
+ "vcp-on",
+ "psi";
+
};
qcom,chg-usb-chgpth@1300 {
@@ -200,8 +206,8 @@
interrupts = <0x0 0x14 0x0>,
<0x0 0x14 0x1>;
- interrupt-names = "dcin-valid",
- "coarse-det-dc";
+ interrupt-names = "coarse-det-dc",
+ "dcin-valid";
};
qcom,chg-boost@1500 {
@@ -210,8 +216,8 @@
interrupts = <0x0 0x15 0x0>,
<0x0 0x15 0x1>;
- interrupt-names = "limit-error",
- "boost-pwr-ok";
+ interrupt-names = "boost-pwr-ok",
+ "limit-error";
};
qcom,chg-misc@1600 {
@@ -993,6 +999,54 @@
status = "disabled";
};
+ qcom,leds@d000 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd000 0x100>;
+ label = "rgb";
+ };
+
+ qcom,leds@d100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd100 0x100>;
+ label = "rgb";
+ };
+
+ qcom,leds@d200 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd200 0x100>;
+ label = "rgb";
+ };
+
+ qcom,leds@d300 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ };
+
+ qcom,leds@d400 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd400 0x100>;
+ label = "flash";
+ };
+
+ qcom,leds@d500 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd500 0x100>;
+ label = "flash";
+ };
+
+ qcom,leds@d600 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd600 0x100>;
+ label = "flash";
+ };
+
+ qcom,leds@d700 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xd700 0x100>;
+ label = "flash";
+ };
+
qcom,leds@d800 {
compatible = "qcom,leds-qpnp";
reg = <0xd800 0x100>;
diff --git a/arch/arm/boot/dts/msm8226-ion.dtsi b/arch/arm/boot/dts/msm8226-ion.dtsi
index beaffe5..b06ad42 100644
--- a/arch/arm/boot/dts/msm8226-ion.dtsi
+++ b/arch/arm/boot/dts/msm8226-ion.dtsi
@@ -19,5 +19,33 @@
qcom,ion-heap@30 { /* SYSTEM HEAP */
reg = <30>;
};
+
+ qcom,ion-heap@8 { /* CP_MM HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <8>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
+ qcom,memory-reservation-size = <0x3800000>;
+ };
+
+ qcom,ion-heap@25 { /* IOMMU HEAP */
+ reg = <25>;
+ };
+
+ qcom,ion-heap@27 { /* QSECOM HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <27>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
+ qcom,memory-reservation-size = <0x780000>;
+ };
+
+ qcom,ion-heap@28 { /* AUDIO HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <28>;
+ qcom,heap-align = <0x1000>;
+ qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
+ qcom,memory-reservation-size = <0x314000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/msm8226-sim.dts b/arch/arm/boot/dts/msm8226-sim.dts
index 7c25680..41ac69d 100644
--- a/arch/arm/boot/dts/msm8226-sim.dts
+++ b/arch/arm/boot/dts/msm8226-sim.dts
@@ -12,7 +12,6 @@
/dts-v1/;
/include/ "msm8226.dtsi"
-/include/ "msm8226-ion.dtsi"
/include/ "msm8226-camera.dtsi"
/ {
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index db2bfb3..b900c3f 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -11,6 +11,8 @@
*/
/include/ "skeleton.dtsi"
+/include/ "msm8226-ion.dtsi"
+/include/ "msm-gdsc.dtsi"
/ {
model = "Qualcomm MSM 8226";
@@ -72,6 +74,39 @@
compatible = "qcom,android-usb";
};
+ qcom,wdt@f9017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf9017000 0x1000>;
+ interrupts = <0 3 0>, <0 4 0>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <10000>;
+ qcom,ipi-ping = <1>;
+ };
+
+};
+
+&gdsc_venus {
+ status = "ok";
+};
+
+&gdsc_mdss {
+ status = "ok";
+};
+
+&gdsc_jpeg {
+ status = "ok";
+};
+
+&gdsc_vfe {
+ status = "ok";
+};
+
+&gdsc_oxili_cx {
+ status = "ok";
+};
+
+&gdsc_usb_hsic {
+ status = "ok";
};
/include/ "msm8226-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm8910-rumi.dts b/arch/arm/boot/dts/msm8910-rumi.dts
new file mode 100644
index 0000000..0d944aa
--- /dev/null
+++ b/arch/arm/boot/dts/msm8910-rumi.dts
@@ -0,0 +1,25 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/include/ "msm8910.dtsi"
+
+/ {
+ model = "Qualcomm MSM 8910 Rumi";
+ compatible = "qcom,msm8910-rumi", "qcom,msm8910";
+ qcom,msm-id = <147 1 0>;
+
+ serial@f991f000 {
+ status = "ok";
+ };
+};
diff --git a/arch/arm/boot/dts/msm8910.dtsi b/arch/arm/boot/dts/msm8910.dtsi
index a2e1338..1c31e5d 100644
--- a/arch/arm/boot/dts/msm8910.dtsi
+++ b/arch/arm/boot/dts/msm8910.dtsi
@@ -51,6 +51,9 @@
reg = <0xf9a55000 0x400>;
interrupts = <0 134 0>;
interrupt-names = "core_irq";
+ HSUSB_VDDCX-supply = <&pm8110_s1>;
+ HSUSB_1p8-supply = <&pm8110_l10>;
+ HSUSB_3p3-supply = <&pm8110_l20>;
qcom,hsusb-otg-phy-type = <2>;
qcom,hsusb-otg-mode = <1>;
@@ -70,16 +73,28 @@
interrupts = <0 123 0>;
interrupt-names = "core_irq";
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ vdd-supply = <&pm8110_l17>;
+ qcom,vdd-always-on;
+ qcom,vdd-lpm-sup;
+ qcom,vdd-voltage-level = <2900000 2900000>;
+ qcom,vdd-current-level = <9000 400000>;
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <8>;
- qcom,sdcc-nonremovable;
- qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+ vdd-io-supply = <&pm8110_l6>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <9000 60000>;
+
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2900 2900>;
+ qcom,bus-width = <8>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
};
sdcc2: qcom,sdcc@f98a4000 {
@@ -90,19 +105,94 @@
interrupts = <0 125 0>;
interrupt-names = "core_irq";
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ vdd-supply = <&pm8110_l18>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <9000 400000>;
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-xpc;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
- qcom,sdcc-current-limit = <800>;
+ vdd-io-supply = <&pm8110_l21>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <9000 50000>;
+
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <4>;
+ qcom,xpc;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+ qcom,current-limit = <800>;
};
+ qcom,smem@fa00000 {
+ compatible = "qcom,smem";
+ reg = <0xfa00000 0x200000>,
+ <0xfa006000 0x1000>,
+ <0xfc428000 0x4000>;
+ reg-names = "smem", "irq-reg-base", "aux-mem1";
+
+ qcom,smd-modem {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <0>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1000>;
+ qcom,pil-string = "modem";
+ interrupts = <0 25 1>;
+ };
+
+ qcom,smsm-modem {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <0>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x2000>;
+ interrupts = <0 26 1>;
+ };
+
+ qcom,smd-adsp {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <1>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x100>;
+ qcom,pil-string = "adsp";
+ interrupts = <0 156 1>;
+ };
+
+ qcom,smsm-adsp {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <1>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x200>;
+ interrupts = <0 157 1>;
+ };
+
+ qcom,smd-wcnss {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <6>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x20000>;
+ qcom,pil-string = "wcnss";
+ interrupts = <0 142 1>;
+ };
+
+ qcom,smsm-wcnss {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <6>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x80000>;
+ interrupts = <0 144 1>;
+ };
+
+ qcom,smd-rpm {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <15>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1>;
+ interrupts = <0 168 1>;
+ qcom,irq-no-suspend;
+ };
+ };
};
/include/ "msm8910-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm8974-camera-sensor-liquid.dtsi b/arch/arm/boot/dts/msm8974-camera-sensor-liquid.dtsi
new file mode 100644
index 0000000..25f79f8
--- /dev/null
+++ b/arch/arm/boot/dts/msm8974-camera-sensor-liquid.dtsi
@@ -0,0 +1,98 @@
+
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&cci {
+
+ qcom,camera@6e {
+ compatible = "qcom,s5k3l1yx";
+ reg = <0x6e 0x0>;
+ qcom,csi-if = <1>;
+ qcom,csid-core = <0>;
+ qcom,flash-type = <0>;
+ qcom,mount-angle = <0>;
+ qcom,sensor-name = "s5k3l1yx";
+ cam_vdig-supply = <&pm8941_l3>;
+ cam_vana-supply = <&pm8941_l17>;
+ cam_vio-supply = <&pm8941_lvs3>;
+ cam_vaf-supply = <&pm8941_l23>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio",
+ "cam_vaf";
+ qcom,cam-vreg-type = <0 0 1 0>;
+ qcom,cam-vreg-min-voltage = <1225000 2850000 0 3000000>;
+ qcom,cam-vreg-max-voltage = <1225000 2850000 0 3000000>;
+ qcom,cam-vreg-op-mode = <105000 80000 0 100000>;
+ qcom,gpio-no-mux = <0>;
+ gpios = <&msmgpio 15 0>,
+ <&msmgpio 19 0>,
+ <&msmgpio 20 0>,
+ <&msmgpio 90 0>;
+ qcom,gpio-common-tbl-num = <0 1 2>;
+ qcom,gpio-common-tbl-flags = <1 1 1>;
+ qcom,gpio-common-tbl-label = "CAMIF_MCLK",
+ "CAMIF_I2C_DATA",
+ "CAMIF_I2C_CLK";
+ qcom,gpio-req-tbl-num = <3>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "CAM_RESET1";
+ qcom,gpio-set-tbl-num = <3 3>;
+ qcom,gpio-set-tbl-flags = <0 2>;
+ qcom,gpio-set-tbl-delay = <1000 30000>;
+ qcom,csi-lane-assign = <0x4320>;
+ qcom,csi-lane-mask = <0x1F>;
+ qcom,csi-phy-sel = <0>;
+ qcom,camera-type = <0>;
+ qcom,sensor-type = <0>;
+ status = "ok";
+ };
+
+ qcom,camera@6c {
+ compatible = "qcom,ov2720";
+ reg = <0x6c 0x0>;
+ qcom,csi-if = <1>;
+ qcom,csid-core = <0>;
+ qcom,flash-type = <0>;
+ qcom,mount-angle = <180>;
+ qcom,sensor-name = "ov2720";
+ cam_vdig-supply = <&pm8941_l3>;
+ cam_vana-supply = <&pm8941_l17>;
+ cam_vio-supply = <&pm8941_lvs2>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
+ qcom,cam-vreg-type = <0 0 1>;
+ qcom,cam-vreg-min-voltage = <1225000 2850000 0>;
+ qcom,cam-vreg-max-voltage = <1225000 2850000 0>;
+ qcom,cam-vreg-op-mode = <105000 80000 0>;
+ qcom,gpio-no-mux = <0>;
+ gpios = <&msmgpio 17 0>,
+ <&msmgpio 19 0>,
+ <&msmgpio 20 0>,
+ <&msmgpio 18 0>;
+ qcom,gpio-common-tbl-num = <0 1 2>;
+ qcom,gpio-common-tbl-flags = <1 1 1>;
+ qcom,gpio-common-tbl-label = "CAMIF_MCLK",
+ "CAMIF_I2C_DATA",
+ "CAMIF_I2C_CLK";
+ qcom,gpio-req-tbl-num = <3>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "CAM_RESET1";
+ qcom,gpio-set-tbl-num = <3 3>;
+ qcom,gpio-set-tbl-flags = <0 2>;
+ qcom,gpio-set-tbl-delay = <1000 4000>;
+ qcom,csi-lane-assign = <0x4320>;
+ qcom,csi-lane-mask = <0x7>;
+ qcom,csi-phy-sel = <2>;
+ qcom,camera-type = <1>;
+ qcom,sensor-type = <0>;
+ status = "ok";
+ };
+};
diff --git a/arch/arm/boot/dts/msm8974-camera-sensor.dtsi b/arch/arm/boot/dts/msm8974-camera-sensor.dtsi
new file mode 100644
index 0000000..d804355
--- /dev/null
+++ b/arch/arm/boot/dts/msm8974-camera-sensor.dtsi
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&cci {
+
+ qcom,camera@6e {
+ compatible = "qcom,s5k3l1yx";
+ reg = <0x6e 0x0>;
+ qcom,csi-if = <1>;
+ qcom,csid-core = <0>;
+ qcom,flash-type = <0>;
+ qcom,mount-angle = <90>;
+ qcom,sensor-name = "s5k3l1yx";
+ cam_vdig-supply = <&pm8941_l3>;
+ cam_vana-supply = <&pm8941_l17>;
+ cam_vio-supply = <&pm8941_lvs3>;
+ cam_vaf-supply = <&pm8941_l23>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio",
+ "cam_vaf";
+ qcom,cam-vreg-type = <0 0 1 0>;
+ qcom,cam-vreg-min-voltage = <1225000 2850000 0 3000000>;
+ qcom,cam-vreg-max-voltage = <1225000 2850000 0 3000000>;
+ qcom,cam-vreg-op-mode = <105000 80000 0 100000>;
+ qcom,gpio-no-mux = <0>;
+ gpios = <&msmgpio 15 0>,
+ <&msmgpio 19 0>,
+ <&msmgpio 20 0>,
+ <&msmgpio 90 0>;
+ qcom,gpio-common-tbl-num = <0 1 2>;
+ qcom,gpio-common-tbl-flags = <1 1 1>;
+ qcom,gpio-common-tbl-label = "CAMIF_MCLK",
+ "CAMIF_I2C_DATA",
+ "CAMIF_I2C_CLK";
+ qcom,gpio-req-tbl-num = <3>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "CAM_RESET1";
+ qcom,gpio-set-tbl-num = <3 3>;
+ qcom,gpio-set-tbl-flags = <0 2>;
+ qcom,gpio-set-tbl-delay = <1000 30000>;
+ qcom,csi-lane-assign = <0x4320>;
+ qcom,csi-lane-mask = <0x1F>;
+ qcom,csi-phy-sel = <0>;
+ qcom,camera-type = <0>;
+ qcom,sensor-type = <0>;
+ status = "ok";
+ };
+
+ qcom,camera@6c {
+ compatible = "qcom,ov2720";
+ reg = <0x6c 0x0>;
+ qcom,csi-if = <1>;
+ qcom,csid-core = <0>;
+ qcom,flash-type = <0>;
+ qcom,mount-angle = <180>;
+ qcom,sensor-name = "ov2720";
+ cam_vdig-supply = <&pm8941_l3>;
+ cam_vana-supply = <&pm8941_l17>;
+ cam_vio-supply = <&pm8941_lvs3>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
+ qcom,cam-vreg-type = <0 0 1>;
+ qcom,cam-vreg-min-voltage = <1225000 2850000 0>;
+ qcom,cam-vreg-max-voltage = <1225000 2850000 0>;
+ qcom,cam-vreg-op-mode = <105000 80000 0>;
+ qcom,gpio-no-mux = <0>;
+ gpios = <&msmgpio 17 0>,
+ <&msmgpio 19 0>,
+ <&msmgpio 20 0>,
+ <&msmgpio 18 0>;
+ qcom,gpio-common-tbl-num = <0 1 2>;
+ qcom,gpio-common-tbl-flags = <1 1 1>;
+ qcom,gpio-common-tbl-label = "CAMIF_MCLK",
+ "CAMIF_I2C_DATA",
+ "CAMIF_I2C_CLK";
+ qcom,gpio-req-tbl-num = <3>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "CAM_RESET1";
+ qcom,gpio-set-tbl-num = <3 3>;
+ qcom,gpio-set-tbl-flags = <0 2>;
+ qcom,gpio-set-tbl-delay = <1000 4000>;
+ qcom,csi-lane-assign = <0x4320>;
+ qcom,csi-lane-mask = <0x7>;
+ qcom,csi-phy-sel = <2>;
+ qcom,camera-type = <1>;
+ qcom,sensor-type = <0>;
+ status = "ok";
+ };
+};
diff --git a/arch/arm/boot/dts/msm8974-camera.dtsi b/arch/arm/boot/dts/msm8974-camera.dtsi
index fd652a0..4b96811 100644
--- a/arch/arm/boot/dts/msm8974-camera.dtsi
+++ b/arch/arm/boot/dts/msm8974-camera.dtsi
@@ -165,7 +165,7 @@
vdd-supply = <&gdsc_vfe>;
};
- qcom,cci@fda0C000 {
+ cci: qcom,cci@fda0C000 {
cell-index = <0>;
compatible = "qcom,cci";
reg = <0xfda0C000 0x1000>;
@@ -177,83 +177,11 @@
interrupt-names = "cci";
qcom,camera@6e {
- compatible = "qcom,s5k3l1yx";
- reg = <0x6e 0x0>;
- qcom,csi-if = <1>;
- qcom,csid-core = <0>;
- qcom,flash-type = <0>;
- qcom,mount-angle = <90>;
- qcom,sensor-name = "s5k3l1yx";
- cam_vdig-supply = <&pm8941_l3>;
- cam_vana-supply = <&pm8941_l17>;
- cam_vio-supply = <&pm8941_lvs3>;
- cam_vaf-supply = <&pm8941_l23>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio",
- "cam_vaf";
- qcom,cam-vreg-type = <0 0 1 0>;
- qcom,cam-vreg-min-voltage = <1225000 2850000 0 3000000>;
- qcom,cam-vreg-max-voltage = <1225000 2850000 0 3000000>;
- qcom,cam-vreg-op-mode = <105000 80000 0 100000>;
- qcom,gpio-no-mux = <0>;
- gpios = <&msmgpio 15 0>,
- <&msmgpio 19 0>,
- <&msmgpio 20 0>,
- <&msmgpio 90 0>;
- qcom,gpio-common-tbl-num = <0 1 2>;
- qcom,gpio-common-tbl-flags = <1 1 1>;
- qcom,gpio-common-tbl-label = "CAMIF_MCLK",
- "CAMIF_I2C_DATA",
- "CAMIF_I2C_CLK";
- qcom,gpio-req-tbl-num = <3>;
- qcom,gpio-req-tbl-flags = <0>;
- qcom,gpio-req-tbl-label = "CAM_RESET1";
- qcom,gpio-set-tbl-num = <3 3>;
- qcom,gpio-set-tbl-flags = <0 2>;
- qcom,gpio-set-tbl-delay = <1000 30000>;
- qcom,csi-lane-assign = <0x4320>;
- qcom,csi-lane-mask = <0x1F>;
- qcom,csi-phy-sel = <0>;
- qcom,camera-type = <0>;
- qcom,sensor-type = <0>;
+ status = "disable";
};
qcom,camera@6c {
- compatible = "qcom,ov2720";
- reg = <0x6c 0x0>;
- qcom,csi-if = <1>;
- qcom,csid-core = <0>;
- qcom,flash-type = <0>;
- qcom,mount-angle = <0>;
- qcom,sensor-name = "ov2720";
- cam_vdig-supply = <&pm8941_l3>;
- cam_vana-supply = <&pm8941_l17>;
- cam_vio-supply = <&pm8941_lvs3>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vana", "cam_vio";
- qcom,cam-vreg-type = <0 0 1>;
- qcom,cam-vreg-min-voltage = <1225000 2850000 0>;
- qcom,cam-vreg-max-voltage = <1225000 2850000 0>;
- qcom,cam-vreg-op-mode = <105000 80000 0>;
- qcom,gpio-no-mux = <0>;
- gpios = <&msmgpio 16 0>,
- <&msmgpio 19 0>,
- <&msmgpio 20 0>,
- <&msmgpio 92 0>;
- qcom,gpio-common-tbl-num = <0 1 2>;
- qcom,gpio-common-tbl-flags = <1 1 1>;
- qcom,gpio-common-tbl-label = "CAMIF_MCLK",
- "CAMIF_I2C_DATA",
- "CAMIF_I2C_CLK";
- qcom,gpio-req-tbl-num = <3>;
- qcom,gpio-req-tbl-flags = <0>;
- qcom,gpio-req-tbl-label = "CAM_RESET1";
- qcom,gpio-set-tbl-num = <3 3>;
- qcom,gpio-set-tbl-flags = <0 2>;
- qcom,gpio-set-tbl-delay = <1000 4000>;
- qcom,csi-lane-assign = <0x4320>;
- qcom,csi-lane-mask = <0x7>;
- qcom,csi-phy-sel = <1>;
- qcom,camera-type = <1>;
- qcom,sensor-type = <0>;
+ status = "disable";
};
qcom,camera@90 {
diff --git a/arch/arm/boot/dts/msm8974-cdp.dtsi b/arch/arm/boot/dts/msm8974-cdp.dtsi
index 00f20ad..e1b2863 100644
--- a/arch/arm/boot/dts/msm8974-cdp.dtsi
+++ b/arch/arm/boot/dts/msm8974-cdp.dtsi
@@ -11,6 +11,7 @@
*/
/include/ "dsi-panel-toshiba-720p-video.dtsi"
+/include/ "msm8974-camera-sensor.dtsi"
/ {
serial@f991e000 {
@@ -39,7 +40,8 @@
atmel,irq-gpio = <&msmgpio 61 0x00>;
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
- atmel,i2c-pull-up = <1>;
+ atmel,i2c-pull-up;
+ atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
@@ -151,6 +153,43 @@
vdd-phy-supply = <&spi_eth_vreg>;
};
};
+
+ sound {
+ compatible = "qcom,msm8974-audio-taiko";
+ qcom,model = "msm8974-taiko-cdp-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+
+ qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>;
+ taiko-mclk-clk = <&pm8941_clkdiv1>;
+ qcom,taiko-mclk-clk-freq = <9600000>;
+ };
};
&sdcc2 {
@@ -178,21 +217,21 @@
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c300 { /* GPIO 4 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c400 { /* GPIO 5 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c500 { /* GPIO 6 */
@@ -228,7 +267,7 @@
qcom,pull = <5>;
qcom,vin-sel = <2>;
qcom,out-strength = <3>;
- qcom,src-select = <2>;
+ qcom,src-sel = <2>;
qcom,master-en = <1>;
};
@@ -247,7 +286,7 @@
qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
- qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
qcom,master-en = <1>;
};
@@ -325,7 +364,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -334,7 +373,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
diff --git a/arch/arm/boot/dts/msm8974-fluid.dtsi b/arch/arm/boot/dts/msm8974-fluid.dtsi
index a55e6d4..1857121 100644
--- a/arch/arm/boot/dts/msm8974-fluid.dtsi
+++ b/arch/arm/boot/dts/msm8974-fluid.dtsi
@@ -11,6 +11,7 @@
*/
/include/ "dsi-panel-toshiba-720p-video.dtsi"
+/include/ "msm8974-camera-sensor.dtsi"
/ {
serial@f991e000 {
@@ -39,7 +40,8 @@
atmel,irq-gpio = <&msmgpio 61 0x00>;
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
- atmel,i2c-pull-up = <1>;
+ atmel,i2c-pull-up;
+ atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
@@ -107,6 +109,22 @@
};
};
+ i2c@f9967000 {
+ sii8334@72 {
+ compatible = "qcom,mhl-sii8334";
+ reg = <0x72>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <82 0x8>;
+ mhl-intr-gpio = <&msmgpio 82 0>;
+ mhl-pwr-gpio = <&msmgpio 12 0>;
+ mhl-rst-gpio = <&pm8941_mpps 8 0>;
+ avcc_18-supply = <&pm8941_l24>;
+ avcc_12-supply = <&pm8941_l2>;
+ smps3a-supply = <&pm8941_s3>;
+ vdda-supply = <&pm8941_l12>;
+ };
+ };
+
gpio_keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
@@ -151,10 +169,47 @@
vdd-phy-supply = <&spi_eth_vreg>;
};
};
+
+ sound {
+ compatible = "qcom,msm8974-audio-taiko";
+ qcom,model = "msm8974-taiko-fluid-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+
+ qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>;
+ taiko-mclk-clk = <&pm8941_clkdiv1>;
+ qcom,taiko-mclk-clk-freq = <9600000>;
+ };
};
&sdcc1 {
- qcom,sdcc-bus-width = <4>;
+ qcom,bus-width = <4>;
};
&sdcc2 {
@@ -181,21 +236,21 @@
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c300 { /* GPIO 4 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c400 { /* GPIO 5 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c500 { /* GPIO 6 */
@@ -217,6 +272,13 @@
};
gpio@cb00 { /* GPIO 12 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,master-en = <1>;
};
gpio@cc00 { /* GPIO 13 */
@@ -231,7 +293,7 @@
qcom,pull = <5>;
qcom,vin-sel = <2>;
qcom,out-strength = <3>;
- qcom,src-select = <2>;
+ qcom,src-sel = <2>;
qcom,master-en = <1>;
};
@@ -250,7 +312,7 @@
qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
- qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
qcom,master-en = <1>;
};
@@ -328,7 +390,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -337,7 +399,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -345,6 +407,12 @@
};
mpp@a700 { /* MPP 8 */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,pull-up = <0>;
+ qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
+ qcom,src-select = <0>; /* CONSTANT */
+ qcom,master-en = <1>; /* ENABLE MPP */
};
};
diff --git a/arch/arm/boot/dts/msm8974-ion.dtsi b/arch/arm/boot/dts/msm8974-ion.dtsi
index 9b5aaac..01e200a 100644
--- a/arch/arm/boot/dts/msm8974-ion.dtsi
+++ b/arch/arm/boot/dts/msm8974-ion.dtsi
@@ -28,41 +28,30 @@
qcom,memory-reservation-size = <0x7800000>;
};
- qcom,ion-heap@29 { /* FIRMWARE HEAP */
+ qcom,ion-heap@23 { /* PIL1 HEAP */
compatible = "qcom,msm-ion-reserve";
- reg = <29>;
- qcom,heap-align = <0x20000>;
- qcom,heap-adjacent = <8>;
- qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
- qcom,memory-reservation-size = <0xA00000>;
- };
-
- qcom,ion-heap@12 { /* MFC HEAP */
- compatible = "qcom,msm-ion-reserve";
- reg = <12>;
- qcom,heap-align = <0x1000>;
- qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
- qcom,memory-reservation-size = <0x2000>;
- };
-
- qcom,ion-heap@24 { /* SF HEAP */
- compatible = "qcom,msm-ion-reserve";
- reg = <24>;
- qcom,heap-align = <0x1000>;
- qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
- qcom,memory-reservation-size = <0x2800000>;
+ reg = <23>;
+ qcom,heap-align = <0x10000>;
+ qcom,memory-fixed = <0xd200000 0x2800000>;
};
qcom,ion-heap@25 { /* IOMMU HEAP */
reg = <25>;
};
+ qcom,ion-heap@26 { /* PIL2 HEAP */
+ compatible = "qcom,msm-ion-reserve";
+ reg = <26>;
+ qcom,heap-align = <0x10000>;
+ qcom,memory-fixed = <0x8400000 0x4e00000>;
+ };
+
qcom,ion-heap@27 { /* QSECOM HEAP */
compatible = "qcom,msm-ion-reserve";
reg = <27>;
qcom,heap-align = <0x1000>;
qcom,memory-reservation-type = "EBI1"; /* reserve EBI memory */
- qcom,memory-reservation-size = <0x600000>;
+ qcom,memory-reservation-size = <0x780000>;
};
qcom,ion-heap@28 { /* AUDIO HEAP */
diff --git a/arch/arm/boot/dts/msm8974-liquid.dtsi b/arch/arm/boot/dts/msm8974-liquid.dtsi
index 1e3d1b3..96889aa 100644
--- a/arch/arm/boot/dts/msm8974-liquid.dtsi
+++ b/arch/arm/boot/dts/msm8974-liquid.dtsi
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
+/include/ "msm8974-camera-sensor-liquid.dtsi"
+
/ {
serial@f991e000 {
status = "ok";
@@ -24,6 +26,16 @@
compatible = "ti,bq28400-battery";
reg = <0xb>;
};
+
+ charger@2b {
+ compatible = "summit,smb350-charger";
+ reg = <0x2b>; /* 0x56/0x57 */
+ summit,stat-gpio = <&pm8941_gpios 30 0x00>;
+ summit,chg-en-n-gpio = <&pm8941_gpios 10 0x00>;
+ summit,chg-susp-n-gpio = <&pm8941_gpios 13 0x00>;
+ summit,chg-current-ma = <1600>;
+ summit,term-current-ma = <300>;
+ };
};
gpio_keys {
@@ -66,6 +78,32 @@
status = "ok";
};
+ drv2667_vreg: drv2667_vdd_vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_drv2667";
+ };
+
+ i2c@f9967000 {
+ ti-drv2667@59 {
+ compatible = "ti,drv2667";
+ reg = <0x59>;
+ vdd-supply = <&drv2667_vreg>;
+ vdd-i2c-supply = <&pm8941_s3>;
+ ti,label = "vibrator";
+ ti,gain = <2>;
+ ti,idle-timeout-ms = <20>;
+ ti,max-runtime-ms = <15000>;
+ ti,mode = <2>;
+ ti,wav-seq = [
+ /* wave form id */
+ 01
+ /* header size, start and stop bytes */
+ 05 80 06 00 09
+ /* repeat, amp, freq, duration, envelope */
+ 01 ff 19 02 00];
+ };
+ };
+
i2c@f9924000 {
atmel_mxt_ts@4a {
compatible = "atmel,mxt-ts";
@@ -78,7 +116,8 @@
atmel,irq-gpio = <&msmgpio 61 0x00>;
atmel,panel-coords = <0 0 1080 1920>;
atmel,display-coords = <0 0 1080 1920>;
- atmel,i2c-pull-up = <1>;
+ atmel,i2c-pull-up;
+ atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0xa2>;
atmel,variant-id = <0x00>;
@@ -165,10 +204,15 @@
compatible = "regulator-fixed";
regulator-name = "ext_5v";
gpio = <&pm8941_mpps 2 0>;
+ startup-delay-us = <12000>;
enable-active-high;
};
};
+&usb3 {
+ qcom,charging-disabled;
+};
+
&pm8941_mvs1 {
parent-supply = <&ext_5v>;
};
@@ -182,14 +226,14 @@
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c100 { /* GPIO 2 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c200 { /* GPIO 3 */
@@ -202,7 +246,7 @@
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c500 { /* GPIO 6 */
@@ -218,6 +262,14 @@
};
gpio@c900 { /* GPIO 10 */
+ /* SMB350-CHG-EN-N */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,pull = <5>; /* PULL_NO */
+ qcom,vin-sel = <0>; /* VPH */
+ qcom,out-strength = <2>; /* STRENGTH_MED */
+ qcom,src-sel = <0>; /* CONSTANT */
+ qcom,master-en = <1>;
};
gpio@ca00 { /* GPIO 11 */
@@ -227,6 +279,14 @@
};
gpio@cc00 { /* GPIO 13 */
+ /* SMB350-CHG-SUSP-N */
+ qcom,mode = <1>; /* DIG_OUT */
+ qcom,output-type = <0>; /* CMOS */
+ qcom,pull = <5>; /* PULL_NO */
+ qcom,vin-sel = <0>; /* VPH */
+ qcom,out-strength = <2>; /* STRENGTH_MED */
+ qcom,src-sel = <0>; /* CONSTANT */
+ qcom,master-en = <1>;
};
gpio@cd00 { /* GPIO 14 */
@@ -238,7 +298,7 @@
qcom,pull = <5>;
qcom,vin-sel = <2>;
qcom,out-strength = <3>;
- qcom,src-select = <2>;
+ qcom,src-sel = <2>;
qcom,master-en = <1>;
};
@@ -257,7 +317,7 @@
qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
- qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
qcom,master-en = <1>;
};
@@ -295,6 +355,12 @@
};
gpio@dd00 { /* GPIO 30 */
+ /* SMB350-STAT */
+ qcom,mode = <0>; /* DIG_IN */
+ qcom,pull = <5>; /* PULL_NO */
+ qcom,vin-sel = <2>; /* S3 1.8V */
+ qcom,src-sel = <0>; /* CONSTANT */
+ qcom,master-en = <1>;
};
gpio@de00 { /* GPIO 31 */
@@ -304,9 +370,25 @@
};
gpio@e000 { /* GPIO 33 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,invert = <1>;
+ qcom,master-en = <1>;
};
gpio@e100 { /* GPIO 34 */
+ qcom,mode = <1>; /* QPNP_PIN_MODE_DIG_OUT */
+ qcom,output-type = <0>; /* QPNP_PIN_OUT_BUF_CMOS */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,invert = <0>;
+ qcom,master-en = <1>;
};
gpio@e200 { /* GPIO 35 */
@@ -318,7 +400,7 @@
qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
qcom,out-strength = <3>; /* QPNP_PIN_OUT_STRENGTH_HIGH */
- qcom,src-select = <3>; /* QPNP_PIN_SEL_FUNC_2 */
+ qcom,src-sel = <3>; /* QPNP_PIN_SEL_FUNC_2 */
qcom,master-en = <1>;
};
};
@@ -333,7 +415,7 @@
qcom,mode = <1>; /* Digital output */
qcom,invert = <0>; /* Output low initially */
qcom,vin-sel = <2>; /* PM8941 S3 = 1.8 V */
- qcom,src-select = <0>; /* Constant */
+ qcom,src-sel = <0>; /* Constant */
qcom,master-en = <1>; /* Enable MPP */
};
@@ -348,7 +430,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -357,7 +439,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -381,7 +463,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8841_S3A 1.8V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -390,7 +472,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <0>; /* PM8841_VPH 3.4V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/msm8974-mtp.dtsi b/arch/arm/boot/dts/msm8974-mtp.dtsi
index f1f4286..80d2440 100644
--- a/arch/arm/boot/dts/msm8974-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8974-mtp.dtsi
@@ -11,6 +11,7 @@
*/
/include/ "dsi-panel-toshiba-720p-video.dtsi"
+/include/ "msm8974-camera-sensor.dtsi"
/ {
serial@f991e000 {
@@ -39,7 +40,8 @@
atmel,irq-gpio = <&msmgpio 61 0x00>;
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
- atmel,i2c-pull-up = <1>;
+ atmel,i2c-pull-up;
+ atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
@@ -151,6 +153,43 @@
vdd-phy-supply = <&spi_eth_vreg>;
};
};
+
+ sound {
+ compatible = "qcom,msm8974-audio-taiko";
+ qcom,model = "msm8974-taiko-mtp-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+
+ qcom,cdc-mclk-gpios = <&pm8941_gpios 15 0>;
+ taiko-mclk-clk = <&pm8941_clkdiv1>;
+ qcom,taiko-mclk-clk-freq = <9600000>;
+ };
};
&sdcc2 {
@@ -171,7 +210,11 @@
};
&usb3 {
- qcom,dwc-usb3-msm-otg-capability;
+ qcom,otg-capability;
+};
+
+&pm8941_bms {
+ status = "ok";
};
&pm8941_chg {
@@ -219,21 +262,21 @@
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c300 { /* GPIO 4 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c400 { /* GPIO 5 */
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel = <2>;
- qcom,select = <0>;
+ qcom,src-sel = <0>;
};
gpio@c500 { /* GPIO 6 */
@@ -269,7 +312,7 @@
qcom,pull = <5>;
qcom,vin-sel = <2>;
qcom,out-strength = <3>;
- qcom,src-select = <2>;
+ qcom,src-sel = <2>;
qcom,master-en = <1>;
};
@@ -288,7 +331,7 @@
qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
qcom,out-strength = <2>; /* QPNP_PIN_OUT_STRENGTH_MED */
- qcom,src-select = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
+ qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
qcom,master-en = <1>;
};
@@ -366,7 +409,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
@@ -375,7 +418,7 @@
qcom,mode = <1>; /* DIG_OUT */
qcom,output-type = <0>; /* CMOS */
qcom,vin-sel = <2>; /* PM8941_S3 1.8V > 1.6V */
- qcom,src-select = <0>; /* CONSTANT */
+ qcom,src-sel = <0>; /* CONSTANT */
qcom,master-en = <1>; /* ENABLE MPP */
};
diff --git a/arch/arm/boot/dts/msm8974-pm.dtsi b/arch/arm/boot/dts/msm8974-pm.dtsi
index c6cbca3..52f2a41 100644
--- a/arch/arm/boot/dts/msm8974-pm.dtsi
+++ b/arch/arm/boot/dts/msm8974-pm.dtsi
@@ -125,7 +125,7 @@
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
qcom,pfm-port = <0x2>;
- qcom,saw2-spm-cmd-ret = [00 20 03 22 00 0f];
+ qcom,saw2-spm-cmd-ret = [1f 00 20 03 22 00 0f];
qcom,saw2-spm-cmd-gdhs = [00 20 32 42 07 44 22 50 02 32 50 0f];
qcom,saw2-spm-cmd-pc = [00 10 32 b0 11 42 07 01 b0 12 44
50 02 32 50 0f];
@@ -422,4 +422,17 @@
compatible = "qcom,pc-cntr";
reg = <0xfe805664 0x40>;
};
+
+ qcom,pm-8x60 {
+ compatible = "qcom,pm-8x60";
+ qcom,pc-mode = <0>; /*MSM_PC_TZ_L2_INT */
+ qcom,use-sync-timer;
+ };
+
+ qcom,rpm-stats@0xfc19dbd0{
+ compatible = "qcom,rpm-stats";
+ reg = <0xfc19dbd0 0x1000>;
+ reg-names = "phys_addr_base";
+ qcom,sleep-stats-version = <2>;
+ };
};
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index de9e98c..3f7e9de 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -71,7 +71,6 @@
rpm-regulator-smpb2 {
status = "okay";
- qcom,allow-atomic = <1>;
pm8841_s2: regulator-s2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
@@ -131,7 +130,6 @@
rpm-regulator-smpa2 {
status = "okay";
- qcom,allow-atomic = <1>;
pm8941_s2: regulator-s2 {
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
@@ -284,7 +282,6 @@
rpm-regulator-ldoa12 {
status = "okay";
- qcom,allow-atomic = <1>;
pm8941_l12: regulator-l12 {
parent-supply = <&pm8941_s2>;
regulator-min-microvolt = <1800000>;
@@ -456,6 +453,10 @@
reg = <0xf9088000 0x1000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
+ qcom,headroom-voltage = <150000>;
+ qcom,retention-voltage = <745000>;
+ qcom,ldo-default-voltage = <745000>;
+ qcom,ldo-threshold-voltage = <750000>;
};
krait1_vreg: regulator@f9098000 {
@@ -464,6 +465,10 @@
reg = <0xf9098000 0x1000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
+ qcom,headroom-voltage = <150000>;
+ qcom,retention-voltage = <745000>;
+ qcom,ldo-default-voltage = <745000>;
+ qcom,ldo-threshold-voltage = <750000>;
};
krait2_vreg: regulator@f90a8000 {
@@ -472,6 +477,10 @@
reg = <0xf90a8000 0x1000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
+ qcom,headroom-voltage = <150000>;
+ qcom,retention-voltage = <745000>;
+ qcom,ldo-default-voltage = <745000>;
+ qcom,ldo-threshold-voltage = <750000>;
};
krait3_vreg: regulator@f90b8000 {
@@ -480,6 +489,10 @@
reg = <0xf90b8000 0x1000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
+ qcom,headroom-voltage = <150000>;
+ qcom,retention-voltage = <745000>;
+ qcom,ldo-default-voltage = <745000>;
+ qcom,ldo-threshold-voltage = <750000>;
};
spi_eth_vreg: spi_eth_phy_vreg {
diff --git a/arch/arm/boot/dts/msm8974-rumi.dtsi b/arch/arm/boot/dts/msm8974-rumi.dtsi
index d4b7793..33656cd 100644
--- a/arch/arm/boot/dts/msm8974-rumi.dtsi
+++ b/arch/arm/boot/dts/msm8974-rumi.dtsi
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
+/include/ "msm8974-camera-sensor.dtsi"
+
/ {
timer {
clock-frequency = <5000000>;
@@ -24,11 +26,11 @@
};
qcom,sdcc@f9824000 {
- qcom,sdcc-clk-rates = <400000 19200000>;
+ qcom,clk-rates = <400000 19200000>;
};
qcom,sdcc@f98a4000 {
- qcom,sdcc-clk-rates = <400000 19200000>;
+ qcom,clk-rates = <400000 19200000>;
};
qcom,sps@f998000 {
diff --git a/arch/arm/boot/dts/msm8974-sim.dtsi b/arch/arm/boot/dts/msm8974-sim.dtsi
index 41e37de..8e8b3c3 100644
--- a/arch/arm/boot/dts/msm8974-sim.dtsi
+++ b/arch/arm/boot/dts/msm8974-sim.dtsi
@@ -11,6 +11,7 @@
*/
/include/ "dsi-panel-sim-video.dtsi"
+/include/ "msm8974-camera-sensor.dtsi"
/ {
qcom,mdss_dsi@fd922800 {
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 6b65837..4618ca2 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -122,6 +122,7 @@
android_usb@fc42b0c8 {
compatible = "qcom,android-usb";
reg = <0xfc42b0c8 0xc8>;
+ qcom,android-usb-swfi-latency = <1>;
};
sdcc1: qcom,sdcc@f9824000 {
@@ -136,25 +137,39 @@
vdd-supply = <&pm8941_l20>;
vdd-io-supply = <&pm8941_s3>;
- qcom,sdcc-vdd-always_on;
- qcom,sdcc-vdd-lpm_sup;
- qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
- qcom,sdcc-vdd-current_level = <800 500000>;
+ qcom,vdd-always-on;
+ qcom,vdd-lpm-sup;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <800 500000>;
- qcom,sdcc-vdd-io-always_on;
- qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
- qcom,sdcc-vdd-io-current_level = <250 154000>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <250 154000>;
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <8>;
- qcom,sdcc-nonremovable;
- qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <8>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+
+ qcom,msm-bus,name = "sdcc1";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,active-only = <0>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
+ <78 512 6656 13312>, /* 13 MB/s*/
+ <78 512 13312 26624>, /* 26 MB/s */
+ <78 512 26624 53248>, /* 52 MB/s */
+ <78 512 53248 106496>, /* 104 MB/s */
+ <78 512 106496 212992>, /* 208 MB/s */
+ <78 512 2147483647 4294967295>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ qcom,dat1-mpm-int = <42>;
};
sdcc2: qcom,sdcc@f98a4000 {
@@ -169,25 +184,39 @@
vdd-supply = <&pm8941_l21>;
vdd-io-supply = <&pm8941_l13>;
- qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
- qcom,sdcc-vdd-current_level = <9000 800000>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <9000 800000>;
- qcom,sdcc-vdd-io-always_on;
- qcom,sdcc-vdd-io-lpm_sup;
- qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
- qcom,sdcc-vdd-io-current_level = <6 22000>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <6 22000>;
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+ qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+ qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+ qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-xpc;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
- qcom,sdcc-current-limit = <800>;
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <4>;
+ qcom,xpc;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+ qcom,current-limit = <800>;
+
+ qcom,msm-bus,name = "sdcc2";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,active-only = <0>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+ <81 512 6656 13312>, /* 13 MB/s*/
+ <81 512 13312 26624>, /* 26 MB/s */
+ <81 512 26624 53248>, /* 52 MB/s */
+ <81 512 53248 106496>, /* 104 MB/s */
+ <81 512 106496 212992>, /* 208 MB/s */
+ <81 512 2147483647 4294967295>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ qcom,dat1-mpm-int = <44>;
};
sdcc3: qcom,sdcc@f9864000 {
@@ -197,8 +226,15 @@
<0xf9864800 0x100>,
<0xf9844000 0x7000>;
reg-names = "core_mem", "dml_mem", "bam_mem";
- interrupts = <0 127 0>, <0 223 0>;
- interrupt-names = "core_irq", "bam_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&sdcc3>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 127 0
+ 1 &intc 0 223 0
+ 2 &msmgpio 37 0x8>;
+ interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq";
gpios = <&msmgpio 40 0>, /* CLK */
<&msmgpio 39 0>, /* CMD */
@@ -206,12 +242,25 @@
<&msmgpio 37 0>, /* DATA1 */
<&msmgpio 36 0>, /* DATA2 */
<&msmgpio 35 0>; /* DATA3 */
- qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
+ qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
- qcom,sdcc-sup-voltages = <1800 1800>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
+ qcom,clk-rates = <400000 25000000 50000000 100000000>;
+ qcom,sup-voltages = <1800 1800>;
+ qcom,bus-width = <4>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
+
+ qcom,msm-bus,name = "sdcc3";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,active-only = <0>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
+ <79 512 6656 13312>, /* 13 MB/s*/
+ <79 512 13312 26624>, /* 26 MB/s */
+ <79 512 26624 53248>, /* 52 MB/s */
+ <79 512 53248 106496>, /* 104 MB/s */
+ <79 512 106496 212992>, /* 208 MB/s */
+ <79 512 2147483647 4294967295>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
status = "disable";
};
@@ -222,8 +271,15 @@
<0xf98e4800 0x100>,
<0xf98c4000 0x7000>;
reg-names = "core_mem", "dml_mem", "bam_mem";
- interrupts = <0 129 0>, <0 226 0>;
- interrupt-names = "core_irq", "bam_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&sdcc4>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 129 0
+ 1 &intc 0 226 0
+ 2 &msmgpio 95 0x8>;
+ interrupt-names = "core_irq", "bam_irq", "sdiowakeup_irq";
gpios = <&msmgpio 93 0>, /* CLK */
<&msmgpio 91 0>, /* CMD */
@@ -231,12 +287,25 @@
<&msmgpio 95 0>, /* DATA1 */
<&msmgpio 94 0>, /* DATA2 */
<&msmgpio 92 0>; /* DATA3 */
- qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
+ qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
- qcom,sdcc-sup-voltages = <1800 1800>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
+ qcom,clk-rates = <400000 25000000 50000000 100000000>;
+ qcom,sup-voltages = <1800 1800>;
+ qcom,bus-width = <4>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
+
+ qcom,msm-bus,name = "sdcc4";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,active-only = <0>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */
+ <80 512 6656 13312>, /* 13 MB/s*/
+ <80 512 13312 26624>, /* 26 MB/s */
+ <80 512 26624 53248>, /* 52 MB/s */
+ <80 512 53248 106496>, /* 104 MB/s */
+ <80 512 106496 212992>, /* 208 MB/s */
+ <80 512 2147483647 4294967295>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
status = "disable";
};
@@ -282,14 +351,12 @@
slim_msm: slim@fe12f000 {
cell-index = <1>;
- compatible = "qcom,slim-msm";
+ compatible = "qcom,slim-ngd";
reg = <0xfe12f000 0x35000>,
<0xfe104000 0x20000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0 0 164 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
- qcom,min-clk-gear = <10>;
- qcom,rxreg-access;
taiko_codec {
compatible = "qcom,taiko-slim-pgd";
@@ -527,6 +594,57 @@
<0x1e70008c>; /* LPG_CHAN12 */
qcom,pm8941@1 {
+ qcom,leds@d300 {
+ status = "okay";
+ qcom,flash_0 {
+ qcom,max-current = <1000>;
+ qcom,default-state = "off";
+ qcom,headroom = <0>;
+ qcom,duration = <1280>;
+ qcom,clamp-curr = <200>;
+ qcom,startup-dly = <1>;
+ qcom,safety-timer;
+ label = "flash";
+ linux,default-trigger =
+ "flash0_trigger";
+ qcom,id = <1>;
+ linux,name = "led:flash_0";
+ qcom,current = <625>;
+ };
+
+ qcom,flash_1 {
+ qcom,max-current = <1000>;
+ qcom,default-state = "off";
+ qcom,headroom = <0>;
+ qcom,duration = <1280>;
+ qcom,clamp-curr = <200>;
+ qcom,startup-dly = <1>;
+ qcom,safety-timer;
+ linux,default-trigger =
+ "flash1_trigger";
+ label = "flash";
+ qcom,id = <2>;
+ linux,name = "led:flash_1";
+ qcom,current = <625>;
+ };
+ };
+
+ qcom,leds@d400 {
+ status = "disabled";
+ };
+
+ qcom,leds@d500 {
+ status = "disabled";
+ };
+
+ qcom,leds@d600 {
+ status = "disabled";
+ };
+
+ qcom,leds@d700 {
+ status = "disabled";
+ };
+
qcom,leds@d800 {
status = "okay";
qcom,wled_0 {
@@ -535,7 +653,7 @@
linux,default-trigger = "bkl-trigger";
qcom,cs-out-en;
qcom,op-fdbck;
- qcom,default-state = "on";
+ qcom,default-state = "off";
qcom,max-current = <25>;
qcom,ctrl-delay-us = <0>;
qcom,boost-curr-lim = <3>;
@@ -582,6 +700,7 @@
qcom,leds@e100 {
status = "disabled";
};
+
};
};
@@ -745,6 +864,36 @@
qcom,msm-dai-q6-dev-id = <16385>;
};
+ qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
qcom,msm-dai-q6-bt-sco-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12288>;
@@ -828,27 +977,19 @@
reg = <0xfc880000 0x100>,
<0xfd485000 0x400>,
<0xfc820000 0x020>,
- <0xfc401680 0x004>;
+ <0xfc401680 0x004>,
+ <0x0d1fc000 0x4000>;
reg-names = "qdsp6_base", "halt_base", "rmb_base",
- "restart_reg";
+ "restart_reg", "metadata_base";
+ interrupts = <0 24 1>;
vdd_mss-supply = <&pm8841_s3>;
+ qcom,is-loadable;
qcom,firmware-name = "mba";
qcom,pil-self-auth = <1>;
};
- qcom,mba@fc820000 {
- compatible = "qcom,pil-mba";
- reg = <0xfc820000 0x0020>,
- <0x0d1fc000 0x4000>;
- reg-names = "rmb_base", "metadata_base";
- interrupts = <0 24 1>;
-
- qcom,firmware-name = "modem";
- qcom,depends-on = "mba";
- };
-
qcom,pronto@fb21b000 {
compatible = "qcom,pil-pronto";
reg = <0xfb21b000 0x3000>,
@@ -973,8 +1114,6 @@
vdd-supply = <&gdsc_venus>;
qcom,firmware-name = "venus";
- qcom,firmware-min-paddr = <0xF500000>;
- qcom,firmware-max-paddr = <0xFA00000>;
};
qcom,cache_erp {
@@ -1009,6 +1148,12 @@
qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
};
+ qcom,msm-contig-mem {
+ compatible = "qcom,msm-contig-mem";
+ qcom,memory-reservation-type = "EBI1";
+ qcom,memory-reservation-size = <0x280000>; /* 2.5M EBI1 buffer */
+ };
+
qcom,qcedev@fd440000 {
compatible = "qcom,qcedev";
reg = <0xfd440000 0x20000>,
@@ -1117,7 +1262,106 @@
compatible = "qcom,msm-wdog-debug";
reg = <0xfc401000 0x1000>;
};
+ qcom,msm-mem-hole {
+ compatible = "qcom,msm-mem-hole";
+ qcom,memblock-remove = <0x8400000 0x7b00000>; /* Address and Size of Hole */
+ };
+ qcom,smem@fa00000 {
+ compatible = "qcom,smem";
+ reg = <0xfa00000 0x200000>,
+ <0xfa006000 0x1000>,
+ <0xfc428000 0x4000>;
+ reg-names = "smem", "irq-reg-base", "aux-mem1";
+
+ qcom,smd-modem {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <0>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1000>;
+ qcom,pil-string = "modem";
+ interrupts = <0 25 1>;
+ };
+
+ qcom,smsm-modem {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <0>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x2000>;
+ interrupts = <0 26 1>;
+ };
+
+ qcom,smd-adsp {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <1>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x100>;
+ qcom,pil-string = "adsp";
+ interrupts = <0 156 1>;
+ };
+
+ qcom,smsm-adsp {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <1>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x200>;
+ interrupts = <0 157 1>;
+ };
+
+ qcom,smd-wcnss {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <6>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x20000>;
+ qcom,pil-string = "wcnss";
+ interrupts = <0 142 1>;
+ };
+
+ qcom,smsm-wcnss {
+ compatible = "qcom,smsm";
+ qcom,smsm-edge = <6>;
+ qcom,smsm-irq-offset = <0x8>;
+ qcom,smsm-irq-bitmask = <0x80000>;
+ interrupts = <0 144 1>;
+ };
+
+ qcom,smd-rpm {
+ compatible = "qcom,smd";
+ qcom,smd-edge = <15>;
+ qcom,smd-irq-offset = <0x8>;
+ qcom,smd-irq-bitmask = <0x1>;
+ interrupts = <0 168 1>;
+ qcom,irq-no-suspend;
+ };
+ };
+};
+
+&gdsc_venus {
+ status = "ok";
+};
+
+&gdsc_mdss {
+ status = "ok";
+};
+
+&gdsc_jpeg {
+ status = "ok";
+};
+
+&gdsc_vfe {
+ status = "ok";
+};
+
+&gdsc_oxili_gx {
+ status = "ok";
+};
+
+&gdsc_oxili_cx {
+ status = "ok";
+};
+
+&gdsc_usb_hsic {
+ status = "ok";
};
/include/ "msm-pm8x41-rpm-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm9625-cdp.dts b/arch/arm/boot/dts/msm9625-cdp.dts
index 89c269e..232fba7 100644
--- a/arch/arm/boot/dts/msm9625-cdp.dts
+++ b/arch/arm/boot/dts/msm9625-cdp.dts
@@ -18,6 +18,33 @@
model = "Qualcomm MSM 9625 CDP";
compatible = "qcom,msm9625-cdp", "qcom,msm9625";
qcom,msm-id = <134 1 0>, <152 1 0>;
+
+ i2c@f9925000 {
+ charger@57 {
+ compatible = "summit,smb137c";
+ reg = <0x57>;
+ summit,chg-current-ma = <1500>;
+ summit,term-current-ma = <50>;
+ summit,pre-chg-current-ma = <100>;
+ summit,float-voltage-mv = <4200>;
+ summit,thresh-voltage-mv = <3000>;
+ summit,recharge-thresh-mv = <75>;
+ summit,system-voltage-mv = <4250>;
+ summit,charging-timeout = <382>;
+ summit,pre-charge-timeout = <48>;
+ summit,therm-current-ua = <10>;
+ summit,temperature-min = <4>; /* 0 C */
+ summit,temperature-max = <3>; /* 45 C */
+ };
+ };
+
+ wlan0: qca,wlan {
+ cell-index = <0>;
+ compatible = "qca,ar6004-sdio";
+ qca,chip-pwd-l-gpios = <&msmgpio 62 0>;
+ qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;
+ qca,ar6004-vdd-io-supply = <&pm8019_l11>;
+ };
};
/* PM8019 GPIO and MPP configuration */
@@ -38,7 +65,7 @@
qcom,invert = <0>; /* Output low */
qcom,out-strength = <1>; /* Low */
qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */
- qcom,src-select = <0>; /* Constant */
+ qcom,src-sel = <0>; /* Constant */
qcom,master-en = <1>; /* Enable GPIO */
};
diff --git a/arch/arm/boot/dts/msm9625-coresight.dtsi b/arch/arm/boot/dts/msm9625-coresight.dtsi
new file mode 100644
index 0000000..f01fe63
--- /dev/null
+++ b/arch/arm/boot/dts/msm9625-coresight.dtsi
@@ -0,0 +1,118 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/ {
+ tmc_etr: tmc@fc322000 {
+ compatible = "arm,coresight-tmc";
+ reg = <0xfc322000 0x1000>,
+ <0xfc37c000 0x3000>;
+
+ qcom,memory-reservation-type = "EBI1";
+ qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
+
+ coresight-id = <0>;
+ coresight-name = "coresight-tmc-etr";
+ coresight-nr-inports = <1>;
+ };
+
+ tpiu: tpiu@fc318000 {
+ compatible = "arm,coresight-tpiu";
+ reg = <0xfc318000 0x1000>;
+
+ coresight-id = <1>;
+ coresight-name = "coresight-tpiu";
+ coresight-nr-inports = <1>;
+ };
+
+ replicator: replicator@fc31c000 {
+ compatible = "qcom,coresight-replicator";
+ reg = <0xfc31c000 0x1000>;
+
+ coresight-id = <2>;
+ coresight-name = "coresight-replicator";
+ coresight-nr-inports = <1>;
+ coresight-outports = <0 1>;
+ coresight-child-list = <&tmc_etr &tpiu>;
+ coresight-child-ports = <0 0>;
+ };
+
+ tmc_etf: tmc@fc307000 {
+ compatible = "arm,coresight-tmc";
+ reg = <0xfc307000 0x1000>;
+
+ coresight-id = <3>;
+ coresight-name = "coresight-tmc-etf";
+ coresight-nr-inports = <1>;
+ coresight-outports = <0>;
+ coresight-child-list = <&replicator>;
+ coresight-child-ports = <0>;
+ coresight-default-sink;
+ };
+
+ funnel_merg: funnel@fc31b000 {
+ compatible = "arm,coresight-funnel";
+ reg = <0xfc31b000 0x1000>;
+
+ coresight-id = <4>;
+ coresight-name = "coresight-funnel-merg";
+ coresight-nr-inports = <2>;
+ coresight-outports = <0>;
+ coresight-child-list = <&tmc_etf>;
+ coresight-child-ports = <0>;
+ };
+
+ funnel_in0: funnel@fc319000 {
+ compatible = "arm,coresight-funnel";
+ reg = <0xfc319000 0x1000>;
+
+ coresight-id = <5>;
+ coresight-name = "coresight-funnel-in0";
+ coresight-nr-inports = <8>;
+ coresight-outports = <0>;
+ coresight-child-list = <&funnel_merg>;
+ coresight-child-ports = <0>;
+ };
+
+ funnel_in1: funnel@fc31a000 {
+ compatible = "arm,coresight-funnel";
+ reg = <0xfc31a000 0x1000>;
+
+ coresight-id = <6>;
+ coresight-name = "coresight-funnel-in1";
+ coresight-nr-inports = <8>;
+ coresight-outports = <0>;
+ coresight-child-list = <&funnel_merg>;
+ coresight-child-ports = <1>;
+ };
+
+ stm: stm@fc321000 {
+ compatible = "arm,coresight-stm";
+ reg = <0xfc321000 0x1000>,
+ <0xfa280000 0x180000>;
+
+ coresight-id = <7>;
+ coresight-name = "coresight-stm";
+ coresight-nr-inports = <0>;
+ coresight-outports = <0>;
+ coresight-child-list = <&funnel_in1>;
+ coresight-child-ports = <7>;
+ };
+
+ csr: csr@fc302000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0xfc302000 0x1000>;
+
+ coresight-id = <8>;
+ coresight-name = "coresight-csr";
+ coresight-nr-inports = <0>;
+ };
+};
diff --git a/arch/arm/boot/dts/msm9625-mtp.dts b/arch/arm/boot/dts/msm9625-mtp.dts
index a5673e5..faf86d4 100644
--- a/arch/arm/boot/dts/msm9625-mtp.dts
+++ b/arch/arm/boot/dts/msm9625-mtp.dts
@@ -18,6 +18,33 @@
model = "Qualcomm MSM 9625 MTP";
compatible = "qcom,msm9625-mtp", "qcom,msm9625";
qcom,msm-id = <134 7 0>, <152 7 0>;
+
+ i2c@f9925000 {
+ charger@57 {
+ compatible = "summit,smb137c";
+ reg = <0x57>;
+ summit,chg-current-ma = <1500>;
+ summit,term-current-ma = <50>;
+ summit,pre-chg-current-ma = <100>;
+ summit,float-voltage-mv = <4200>;
+ summit,thresh-voltage-mv = <3000>;
+ summit,recharge-thresh-mv = <75>;
+ summit,system-voltage-mv = <4250>;
+ summit,charging-timeout = <382>;
+ summit,pre-charge-timeout = <48>;
+ summit,therm-current-ua = <10>;
+ summit,temperature-min = <4>; /* 0 C */
+ summit,temperature-max = <3>; /* 45 C */
+ };
+ };
+
+ wlan0: qca,wlan {
+ cell-index = <0>;
+ compatible = "qca,ar6004-sdio";
+ qca,chip-pwd-l-gpios = <&msmgpio 62 0>;
+ qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;
+ qca,ar6004-vdd-io-supply = <&pm8019_l11>;
+ };
};
/* PM8019 GPIO and MPP configuration */
@@ -38,7 +65,7 @@
qcom,invert = <0>; /* Output low */
qcom,out-strength = <1>; /* Low */
qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */
- qcom,src-select = <0>; /* Constant */
+ qcom,src-sel = <0>; /* Constant */
qcom,master-en = <1>; /* Enable GPIO */
};
diff --git a/arch/arm/boot/dts/msm9625-pm.dtsi b/arch/arm/boot/dts/msm9625-pm.dtsi
new file mode 100644
index 0000000..d62f7e7
--- /dev/null
+++ b/arch/arm/boot/dts/msm9625-pm.dtsi
@@ -0,0 +1,214 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ qcom,spm@f9009000 {
+ compatible = "qcom,spm-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xf9009000 0x1000>;
+ qcom,core-id = <0>;
+ qcom,saw2-ver-reg = <0xfd0>;
+ qcom,saw2-cfg = <0x101>;
+ qcom,saw2-spm-dly= <0>;
+ qcom,saw2-spm-ctl = <0x1>;
+ qcom,saw2-spm-cmd-wfi = [04 03 04 0f];
+ qcom,saw2-spm-cmd-spc = [34 04 44 14 24 54 03 54 44 14 04 24
+ 3e 0f];
+ qcom,saw2-spm-cmd-pc = [34 04 44 14 24 54 07 54 44 14 04 24
+ 3e 0f];
+ };
+
+ qcom,lpm-resources {
+ compatible = "qcom,lpm-resources";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,lpm-resources@0 {
+ reg = <0x0>;
+ qcom,name = "vdd-dig";
+ qcom,resource-type = <0>;
+ qcom,type = <0x616F646C>; /* "ldoa" */
+ qcom,id = <0x0A>;
+ qcom,key = <0x6e726f63>; /* "corn" */
+ };
+
+ qcom,lpm-resources@1 {
+ reg = <0x1>;
+ qcom,name = "vdd-mem";
+ qcom,resource-type = <0>;
+ qcom,type = <0x616F646C>; /* "ldoa" */
+ qcom,id = <0x0C>;
+ qcom,key = <0x7675>; /* "uv" */
+ };
+
+ qcom,lpm-resources@2 {
+ reg = <0x2>;
+ qcom,name = "pxo";
+ qcom,resource-type = <0>;
+ qcom,type = <0x306b6c63>; /* "clk0" */
+ qcom,id = <0x00>;
+ qcom,key = <0x62616e45>; /* "Enab" */
+ };
+ };
+
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,lpm-level@0 {
+ reg = <0x0>;
+ qcom,mode = <0>; /* MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT */
+ qcom,xo = <1>; /* ON */
+ qcom,l2 = <3>; /* ACTIVE */
+ qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */
+ qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */
+ qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */
+ qcom,vdd-dig-lower-bound = <4>; /* NORMAL */
+ qcom,latency-us = <100>;
+ qcom,ss-power = <8000>;
+ qcom,energy-overhead = <100000>;
+ qcom,time-overhead = <1>;
+ };
+
+ qcom,lpm-level@1 {
+ reg = <0x1>;
+ qcom,mode = <2>; /* MSM_PM_SLEEP_MODE_STANDALONE_POWER_COLLAPSE */
+ qcom,xo = <1>; /* ON */
+ qcom,l2 = <3>; /* ACTIVE */
+ qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */
+ qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */
+ qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */
+ qcom,vdd-dig-lower-bound = <4>; /* NORMAL */
+ qcom,latency-us = <2000>;
+ qcom,ss-power = <5000>;
+ qcom,energy-overhead = <60100000>;
+ qcom,time-overhead = <3000>;
+ };
+
+ qcom,lpm-level@2 {
+ reg = <0x2>;
+ qcom,mode = <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
+ qcom,xo = <1>; /* ON */
+ qcom,l2 = <1>; /* GDHS */
+ qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */
+ qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */
+ qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */
+ qcom,vdd-dig-lower-bound = <4>; /* NORMAL */
+ qcom,latency-us = <3500>;
+ qcom,ss-power = <5000>;
+ qcom,energy-overhead = <60350000>;
+ qcom,time-overhead = <6300>;
+ };
+
+ qcom,lpm-level@3 {
+ reg = <0x3>;
+ qcom,mode= <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
+ qcom,xo = <0>; /* OFF */
+ qcom,l2 = <0>; /* OFF */
+ qcom,vdd-mem-upper-bound = <1050000>; /* SUPER TURBO */
+ qcom,vdd-mem-lower-bound = <950000>; /* NORMAL */
+ qcom,vdd-dig-upper-bound = <6>; /* SUPER TURBO */
+ qcom,vdd-dig-lower-bound = <4>; /* NORMAL */
+ qcom,latency-us = <6800>;
+ qcom,ss-power = <2000>;
+ qcom,energy-overhead = <71850000>;
+ qcom,time-overhead = <13300>;
+ };
+
+ qcom,lpm-level@4 {
+ reg = <0x4>;
+ qcom,mode= <3>; /* MSM_PM_SLEEP_MODE_POWER_COLLAPSE */
+ qcom,xo = <0>; /* OFF */
+ qcom,l2 = <0>; /* OFF */
+ qcom,vdd-mem-upper-bound = <950000>; /* SVS SOC */
+ qcom,vdd-mem-lower-bound = <675000>; /* RETENTION */
+ qcom,vdd-dig-upper-bound = <3>; /* SVS SOC */
+ qcom,vdd-dig-lower-bound = <1>; /* RETENTION */
+ qcom,latency-us = <9800>;
+ qcom,ss-power = <0>;
+ qcom,energy-overhead = <76350000>;
+ qcom,time-overhead = <28300>;
+ };
+ };
+
+ qcom,pm-boot {
+ compatible = "qcom,pm-boot";
+ qcom,mode = <0>; /* MSM_PM_BOOT_CONFIG_TZ */
+ };
+
+ qcom,mpm@fc4281d0 {
+ compatible = "qcom,mpm-v2";
+ reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */
+ <0xf9011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ interrupts = <0 171 1>;
+
+ qcom,ipc-bit-offset = <1>;
+
+ qcom,gic-parent = <&intc>;
+ qcom,gic-map = <41 172>, /* usb2_hsic_async_wakeup_irq */
+ <0xff 208>; /* summary_irq_kpss */
+
+ qcom,gpio-parent = <&msmgpio>;
+ qcom,gpio-map = <4 1>,
+ <5 5>,
+ <6 9>,
+ <7 18>,
+ <8 20>,
+ <9 24>,
+ <10 27>,
+ <11 28>,
+ <12 34>,
+ <13 35>,
+ <14 37>,
+ <15 42>,
+ <16 44>,
+ <17 46>,
+ <18 50>,
+ <19 54>,
+ <20 59>,
+ <21 61>,
+ <22 62>,
+ <23 64>,
+ <24 65>,
+ <25 66>,
+ <26 67>,
+ <27 68>,
+ <28 71>,
+ <29 72>,
+ <30 73>,
+ <31 74>,
+ <32 75>,
+ <33 77>,
+ <34 79>,
+ <35 80>,
+ <36 82>,
+ <37 86>;
+ };
+
+ qcom,pm-8x60 {
+ compatible = "qcom,pm-8x60";
+ qcom,pc-mode = <2>; /*MSM_PC_TZ_L2_EXT */
+ qcom,use-sync-timer;
+ };
+
+ qcom,rpm-stats@fc19dbd0 {
+ compatible = "qcom,rpm-stats";
+ reg = <0xfc19dbd0 0x1000>;
+ reg-names = "phys_addr_base";
+ qcom,sleep-stats-version = <2>;
+ };
+};
diff --git a/arch/arm/boot/dts/msm9625-regulator.dtsi b/arch/arm/boot/dts/msm9625-regulator.dtsi
index d410bd4..24f616d 100644
--- a/arch/arm/boot/dts/msm9625-regulator.dtsi
+++ b/arch/arm/boot/dts/msm9625-regulator.dtsi
@@ -214,7 +214,7 @@
status = "okay";
pm8019_l12: regulator-l12 {
parent-supply = <&pm8019_s3>;
- regulator-min-microvolt = <750000>;
+ regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
status = "okay";
};
@@ -223,10 +223,20 @@
regulator-name = "8019_l12_ao";
qcom,set = <1>;
parent-supply = <&pm8019_s3_ao>;
- regulator-min-microvolt = <750000>;
+ regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
status = "okay";
};
+ pm8019_l12_so: regulator-l12-so {
+ compatible = "qcom,rpm-regulator-smd";
+ regulator-name = "8019_l12_so";
+ qcom,set = <2>;
+ parent-supply = <&pm8019_s3>;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ qcom,init-voltage = <675000>;
+ status = "okay";
+ };
};
rpm-regulator-ldoa13 {
@@ -257,4 +267,9 @@
gpio = <&pm8019_gpios 4 0>;
enable-active-high;
};
+
+ usb_vbus: regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ };
};
diff --git a/arch/arm/boot/dts/msm9625.dtsi b/arch/arm/boot/dts/msm9625.dtsi
index 0ebeb9c..6e4d9e6 100644
--- a/arch/arm/boot/dts/msm9625.dtsi
+++ b/arch/arm/boot/dts/msm9625.dtsi
@@ -12,6 +12,8 @@
/include/ "skeleton.dtsi"
/include/ "msm9625-ion.dtsi"
+/include/ "msm9625-pm.dtsi"
+/include/ "msm9625-coresight.dtsi"
/ {
model = "Qualcomm MSM 9625";
@@ -73,6 +75,7 @@
HSUSB_VDDCX-supply = <&pm8019_l12>;
HSUSB_1p8-supply = <&pm8019_l2>;
HSUSB_3p3-supply = <&pm8019_l4>;
+ vbus_otg-supply = <&usb_vbus>;
qcom,hsusb-otg-phy-type = <2>;
qcom,hsusb-otg-mode = <1>;
@@ -95,25 +98,26 @@
interrupt-names = "bam_irq";
};
- spi@f9928000 {
+ spi@f9924000 {
+ cell-index = <0>;
compatible = "qcom,spi-qup-v2";
- reg = <0xf9928000 0x1000>;
- interrupts = <0 100 0>;
- spi-max-frequency = <24000000>;
+ reg = <0xf9924000 0x1000>;
+ interrupts = <0 96 0>;
+ spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
- gpios = <&msmgpio 23 0>, /* CLK */
- <&msmgpio 21 0>, /* MISO */
- <&msmgpio 20 0>; /* MOSI */
+ gpios = <&msmgpio 7 0>, /* CLK */
+ <&msmgpio 5 0>, /* MISO */
+ <&msmgpio 4 0>; /* MOSI */
- cs-gpios = <&msmgpio 69 0>;
+ cs-gpios = <&msmgpio 6 0>;
ethernet-switch@0 {
compatible = "simtec,ks8851";
reg = <0>;
interrupt-parent = <&msmgpio>;
interrupts = <75 0>;
- spi-max-frequency = <5000000>;
+ spi-max-frequency = <4800000>;
};
};
@@ -140,7 +144,6 @@
/* 190,ee0_krait_hlos_spmi_periph_irq */
/* 187,channel_0_krait_hlos_trans_done_irq */
interrupts = <0 190 0 0 187 0>;
- qcom,not-wakeup;
qcom,pmic-arb-ee = <0>;
qcom,pmic-arb-channel = <0>;
qcom,pmic-arb-ppid-map = <0x02400000>, /* TEMP_ALARM */
@@ -183,22 +186,22 @@
vdd-supply = <&ext_2p95v>;
vdd-io-supply = <&pm8019_l13>;
- qcom,sdcc-vdd-io-always_on;
- qcom,sdcc-vdd-io-lpm_sup;
- qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
- qcom,sdcc-vdd-io-current_level = <6 22000>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <6 22000>;
- qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>;
- qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>;
- qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>;
- qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>;
+ qcom,pad-pull-on = <0x0 0x3 0x3>;
+ qcom,pad-pull-off = <0x0 0x3 0x3>;
+ qcom,pad-drv-on = <0x7 0x4 0x4>;
+ qcom,pad-drv-off = <0x0 0x0 0x0>;
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-xpc;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
- qcom,sdcc-current-limit = <800>;
+ qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <4>;
+ qcom,xpc;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+ qcom,current-limit = <800>;
interrupt-parent = <&sdcc2>;
#address-cells = <0>;
@@ -228,12 +231,12 @@
<&msmgpio 17 0>,
<&msmgpio 18 0>,
<&msmgpio 19 0>;
- qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
+ qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
- qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
- qcom,sdcc-sup-voltages = <2950 2950>;
- qcom,sdcc-bus-width = <4>;
- qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
+ qcom,clk-rates = <400000 25000000 50000000 100000000>;
+ qcom,sup-voltages = <2950 2950>;
+ qcom,bus-width = <4>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
};
qcom,bam_dmux@fc834000 {
@@ -256,6 +259,192 @@
reg = <0xfc400404 0x4>;
regulator-name = "gdsc_usb_hsic";
};
+
+ tsens@fc4a8000 {
+ compatible = "qcom,msm-tsens";
+ reg = <0xfc4a8000 0x2000>,
+ <0xfc4b8000 0x1000>;
+ reg-names = "tsens_physical", "tsens_eeprom_physical";
+ interrupts = <0 184 0>;
+ qcom,sensors = <5>;
+ qcom,slope = <3200 3200 3200 3200 3200>;
+ };
+
+ qcom,msm-rng@f9bff000 {
+ compatible = "qcom,msm-rng";
+ reg = <0xf9bff000 0x200>;
+ qcom,msm-rng-iface-clk;
+ };
+
+ wcd9xxx_intc: wcd9xxx-irq {
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <20 0>;
+ interrupt-names = "cdc-int";
+ };
+
+ i2c@f9925000 {
+ cell-index = <3>;
+ compatible = "qcom,i2c-qup";
+ reg = <0xf9925000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ interrupts = <0 97 0>;
+ interrupt-names = "qup_err_intr";
+ qcom,i2c-bus-freq = <100000>;
+ qcom,i2c-src-freq = <24000000>;
+
+ wcd9xxx_codec@0d{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x0d>;
+ qcom,cdc-reset-gpio = <&msmgpio 22 0>;
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
+ cdc-vdd-buck-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <25000>;
+
+ cdc-vdd-tx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-tx-h-current = <25000>;
+
+ cdc-vdd-rx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rx-h-current = <25000>;
+
+ cdc-vddpx-1-supply = <&pm8019_l11>;
+ qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
+ qcom,cdc-vddpx-1-current = <10000>;
+
+ cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
+ qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-a-1p2v-current = <10000>;
+
+ cdc-vddcx-1-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-1-current = <10000>;
+
+ cdc-vddcx-2-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-2-current = <10000>;
+
+ qcom,cdc-micbias-ldoh-v = <0x3>;
+ qcom,cdc-micbias-cfilt1-mv = <1800>;
+ qcom,cdc-micbias-cfilt2-mv = <2700>;
+ qcom,cdc-micbias-cfilt3-mv = <1800>;
+ qcom,cdc-micbias1-cfilt-sel = <0x0>;
+ qcom,cdc-micbias2-cfilt-sel = <0x1>;
+ qcom,cdc-micbias3-cfilt-sel = <0x2>;
+ qcom,cdc-micbias4-cfilt-sel = <0x2>;
+ };
+
+ wcd9xxx_codec@77{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x77>;
+ };
+
+ wcd9xxx_codec@66{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x66>;
+ };
+
+ wcd9xxx_codec@55{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x55>;
+ };
+ };
+
+ sound {
+ compatible = "qcom,mdm9625-audio-taiko";
+ qcom,model = "mdm9625-taiko-i2s-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,taiko-mclk-clk-freq = <12288000>;
+ };
+
+ qcom,msm-adsp-loader {
+ compatible = "qcom,adsp-loader";
+ };
+
+ qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ };
+
+ qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
+ };
+
+ qcom,msm-dai-mi2s {
+ compatible = "qcom,msm-dai-mi2s";
+ qcom,msm-dai-q6-mi2s-prim {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <0>;
+ qcom,msm-mi2s-rx-lines = <2>;
+ qcom,msm-mi2s-tx-lines = <1>;
+ };
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ };
+
+ qcom,mss {
+ compatible = "qcom,pil-q6v5-mss";
+ interrupts = <0 24 1>;
+ };
};
/include/ "msm-pm8019-rpm-regulator.dtsi"
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 76650e0..8e948c2 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -42,6 +42,7 @@
# CONFIG_MSM_SMD_NMEA is not set
# CONFIG_MSM_SMD_QMI is not set
CONFIG_MSM_ONCRPCROUTER=y
+CONFIG_MSM_IPC_ROUTER=y
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
CONFIG_MSM_RMT_STORAGE_CLIENT=y
# CONFIG_MSM_HW3D is not set
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index 8ab57de..d403cec 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -42,6 +42,7 @@
# CONFIG_MSM_SMD_NMEA is not set
# CONFIG_MSM_SMD_QMI is not set
CONFIG_MSM_ONCRPCROUTER=y
+CONFIG_MSM_IPC_ROUTER=y
# CONFIG_MSM_RPCSERVER_TIME_REMOTE is not set
CONFIG_MSM_RMT_STORAGE_CLIENT=y
# CONFIG_MSM_HW3D is not set
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 2ee3f3b..828484a 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -295,7 +295,6 @@
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
-# CONFIG_BATTERY_MSM is not set
CONFIG_BATTERY_MSM8X60=y
CONFIG_PM8058_CHARGER=y
CONFIG_ISL9519_CHARGER=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index 25c5207..28d7b12 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -295,7 +295,6 @@
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
-# CONFIG_BATTERY_MSM is not set
CONFIG_BATTERY_MSM8X60=y
CONFIG_PM8058_CHARGER=y
CONFIG_ISL9519_CHARGER=y
diff --git a/arch/arm/configs/msm8910_defconfig b/arch/arm/configs/msm8910_defconfig
index 83a499b..e2e05b2 100644
--- a/arch/arm/configs/msm8910_defconfig
+++ b/arch/arm/configs/msm8910_defconfig
@@ -10,8 +10,6 @@
CONFIG_CGROUP_CPUACCT=y
CONFIG_RESOURCE_COUNTERS=y
CONFIG_CGROUP_SCHED=y
-CONFIG_VFP=y
-# CONFIG_FAIR_GROUP_SCHED is not set
CONFIG_RT_GROUP_SCHED=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
@@ -22,24 +20,33 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
+CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
CONFIG_OPROFILE=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8910=y
+CONFIG_ARCH_MSM8226=y
# CONFIG_MSM_STACKED_MEMORY is not set
CONFIG_CPU_HAS_L2_PMU=y
# CONFIG_MSM_FIQ_SUPPORT is not set
# CONFIG_MSM_PROC_COMM is not set
CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
+# CONFIG_MSM_HW3D is not set
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
+CONFIG_MSM_WATCHDOG_V2=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_SMP_ON_UP is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
@@ -47,21 +54,47 @@
CONFIG_HIGHMEM=y
CONFIG_VMALLOC_RESERVE=0x19000000
CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SUSPEND is not set
CONFIG_NET=y
+CONFIG_PACKET=y
CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
CONFIG_NETFILTER=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
-# CONFIG_ANDROID_PMEM is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_GPIO=m
-CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_MSM_HSL=y
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
CONFIG_DIAG_CHAR=y
@@ -71,6 +104,10 @@
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_STUB=y
+CONFIG_ION=y
+CONFIG_ION_MSM=y
+CONFIG_FB=y
+CONFIG_FB_VIRTUAL=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
@@ -88,10 +125,21 @@
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_TEST=m
CONFIG_MMC_MSM=y
-CONFIG_MMC_MSM_SPS_SUPPORT=y
+CONFIG_STAGING=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
@@ -106,19 +154,11 @@
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_USER=y
CONFIG_KEYS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index ec00b68..d5e15f1 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -315,7 +315,6 @@
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
-# CONFIG_BATTERY_MSM is not set
CONFIG_ISL9519_CHARGER=y
CONFIG_SMB349_CHARGER=y
CONFIG_PM8921_CHARGER=y
@@ -356,6 +355,7 @@
CONFIG_MSM_CAMERA_FLASH_SC628A=y
CONFIG_MSM_CAMERA_FLASH_TPS61310=y
CONFIG_OV2720=y
+CONFIG_IMX135=y
CONFIG_MSM_CAMERA_SENSOR=y
CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_EEPROM=y
@@ -367,14 +367,12 @@
CONFIG_S5K3L1YX=y
CONFIG_IMX091=y
CONFIG_MSM_WFD=y
-CONFIG_IMX135=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
# CONFIG_DVB_FE_CUSTOMISE is not set
CONFIG_DVB_MPQ=m
CONFIG_DVB_MPQ_DEMUX=m
CONFIG_DVB_MPQ_VIDEO=m
-CONFIG_DVB_MPQ_TSPP1=y
CONFIG_ION=y
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
@@ -416,7 +414,6 @@
CONFIG_USB_EHCI_MSM_HOST4=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index 33f7987..386f311 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -320,7 +320,6 @@
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SX150X=y
CONFIG_POWER_SUPPLY=y
-# CONFIG_BATTERY_MSM is not set
CONFIG_ISL9519_CHARGER=y
CONFIG_SMB349_CHARGER=y
CONFIG_PM8921_CHARGER=y
@@ -360,6 +359,7 @@
CONFIG_IMX074_ACT=y
CONFIG_MSM_CAMERA_FLASH_SC628A=y
CONFIG_OV2720=y
+CONFIG_IMX135=y
CONFIG_MSM_CAMERA_SENSOR=y
CONFIG_MSM_ACTUATOR=y
CONFIG_MSM_EEPROM=y
@@ -371,14 +371,12 @@
CONFIG_S5K3L1YX=y
CONFIG_IMX091=y
CONFIG_MSM_WFD=y
-CONFIG_IMX135=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
# CONFIG_DVB_FE_CUSTOMISE is not set
CONFIG_DVB_MPQ=m
CONFIG_DVB_MPQ_DEMUX=m
CONFIG_DVB_MPQ_VIDEO=m
-CONFIG_DVB_MPQ_TSPP1=y
CONFIG_ION=y
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
@@ -419,7 +417,6 @@
CONFIG_USB_EHCI_MSM_HOST4=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
index 98c1ede..6517945 100644
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -37,7 +37,6 @@
CONFIG_EFI_PARTITION=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MSM8226=y
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
# CONFIG_MSM_STACKED_MEMORY is not set
CONFIG_CPU_HAS_L2_PMU=y
@@ -48,12 +47,12 @@
CONFIG_MSM_BAM_DMUX=y
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
+CONFIG_MSM_QMI_INTERFACE=y
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_LPASS_QDSP6V5=y
CONFIG_MSM_PIL_MSS_QDSP6V5=y
-CONFIG_MSM_PIL_MBA=y
CONFIG_MSM_PIL_VENUS=y
CONFIG_MSM_PIL_PRONTO=y
CONFIG_MSM_TZ_LOG=y
@@ -240,6 +239,7 @@
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
CONFIG_WCNSS_CORE=y
CONFIG_WCNSS_CORE_PRONTO=y
CONFIG_INPUT_EVDEV=y
@@ -264,7 +264,7 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
-CONFIG_SLIMBUS_MSM_CTRL=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_QPNP_PIN=y
@@ -272,7 +272,9 @@
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_BQ28400=y
CONFIG_QPNP_CHARGER=y
+CONFIG_BATTERY_BCL=y
CONFIG_QPNP_BMS=y
+CONFIG_SENSORS_EPM_ADC=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_SENSORS_QPNP_ADC_CURRENT=y
CONFIG_THERMAL=y
@@ -287,6 +289,7 @@
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEOBUF2_MSM_MEM=y
+CONFIG_USB_VIDEO_CLASS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_MSM_CAMERA_V4L2=y
CONFIG_MT9M114=y
@@ -319,10 +322,12 @@
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_SOUND=y
CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_MSM8974=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
@@ -338,7 +343,7 @@
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_DWC3_MSM=y
CONFIG_USB_G_ANDROID=y
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 328a4dc..33400ea 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -46,12 +46,12 @@
CONFIG_MSM_BAM_DMUX=y
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
+CONFIG_MSM_QMI_INTERFACE=y
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_SYSMON_COMM=y
CONFIG_MSM_PIL_LPASS_QDSP6V5=y
CONFIG_MSM_PIL_MSS_QDSP6V5=y
-CONFIG_MSM_PIL_MBA=y
CONFIG_MSM_PIL_VENUS=y
CONFIG_MSM_PIL_PRONTO=y
CONFIG_MSM_TZ_LOG=y
@@ -241,6 +241,7 @@
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
CONFIG_WCNSS_CORE=y
CONFIG_WCNSS_CORE_PRONTO=y
CONFIG_INPUT_EVDEV=y
@@ -265,15 +266,18 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
-CONFIG_SLIMBUS_MSM_CTRL=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_QPNP_PIN=y
CONFIG_GPIO_QPNP_PIN_DEBUG=y
CONFIG_POWER_SUPPLY=y
+CONFIG_SMB350_CHARGER=y
CONFIG_BATTERY_BQ28400=y
CONFIG_QPNP_CHARGER=y
+CONFIG_BATTERY_BCL=y
CONFIG_QPNP_BMS=y
+CONFIG_SENSORS_EPM_ADC=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_SENSORS_QPNP_ADC_CURRENT=y
CONFIG_THERMAL=y
@@ -288,6 +292,7 @@
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEOBUF2_MSM_MEM=y
+CONFIG_USB_VIDEO_CLASS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_MSM_CAMERA_V4L2=y
CONFIG_MT9M114=y
@@ -320,10 +325,12 @@
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_SOUND=y
CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_MSM8974=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
@@ -339,7 +346,7 @@
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_DWC3_MSM=y
CONFIG_USB_G_ANDROID=y
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
@@ -398,6 +405,7 @@
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 81b853d..a052609 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -199,7 +199,6 @@
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
-# CONFIG_BATTERY_MSM is not set
CONFIG_SENSORS_PM8XXX_ADC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8960=y
diff --git a/arch/arm/configs/msm9625_defconfig b/arch/arm/configs/msm9625_defconfig
index e1d4ca0..97fef39 100644
--- a/arch/arm/configs/msm9625_defconfig
+++ b/arch/arm/configs/msm9625_defconfig
@@ -21,6 +21,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PROFILING=y
@@ -41,8 +42,12 @@
CONFIG_MSM_IPC_ROUTER=y
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_RPM_REGULATOR_SMD=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_DLOAD_MODE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_ARM_ARCH_TIMER=y
@@ -51,12 +56,12 @@
CONFIG_HIGHMEM=y
CONFIG_VMALLOC_RESERVE=0x19000000
CONFIG_USE_OF=y
-CONFIG_CPU_IDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -66,11 +71,23 @@
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IPV6=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
CONFIG_NET_CLS_FW=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=m
+CONFIG_NL80211_TESTMODE=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
@@ -85,13 +102,6 @@
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-CONFIG_ATH_COMMON=m
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_DEBUG=y
CONFIG_KS8851=y
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_MSM_RMNET is not set
@@ -102,6 +112,7 @@
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_MISC=y
@@ -113,24 +124,28 @@
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
+CONFIG_MSM_BUS_SCALING=y
CONFIG_SPI=y
CONFIG_SPI_QUP=y
CONFIG_SPI_SPIDEV=m
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_QPNP_PIN=y
CONFIG_GPIO_QPNP_PIN_DEBUG=y
CONFIG_POWER_SUPPLY=y
-CONFIG_HWMON=y
+CONFIG_SMB137C_CHARGER=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_TSENS8974=y
CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_QPNP=y
CONFIG_ION=y
CONFIG_ION_MSM=y
@@ -191,5 +206,58 @@
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
-CONFIG_PANIC_TIMEOUT=5
-CONFIG_MSM_DLOAD_MODE=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_MSM_QDSS=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_IP_SET=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_HL=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_WCD9320_CODEC=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_MDM9625=y
+CONFIG_MSM_ADSP_LOADER=m
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 5f28327..abb222f 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -261,6 +261,58 @@
return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
}
+static inline void *dma_alloc_stronglyordered(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_STRONGLY_ORDERED, &attrs);
+ return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
+}
+
+static inline void dma_free_stronglyordered(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t dma_handle)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_STRONGLY_ORDERED, &attrs);
+ return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
+}
+
+static inline int dma_mmap_stronglyordered(struct device *dev,
+ struct vm_area_struct *vma, void *cpu_addr,
+ dma_addr_t dma_addr, size_t size)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_STRONGLY_ORDERED, &attrs);
+ return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
+}
+
+static inline void *dma_alloc_nonconsistent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs);
+ return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
+}
+
+static inline void dma_free_nonconsistent(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t dma_handle)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs);
+ return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
+}
+
+static inline int dma_mmap_nonconsistent(struct device *dev,
+ struct vm_area_struct *vma, void *cpu_addr,
+ dma_addr_t dma_addr, size_t size)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs);
+ return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
+}
+
+
+
/*
* This can be called during boot to increase the size of the consistent
* DMA region above it's default value of 2MB. It must be called before the
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 42fef7c..938be62 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -268,12 +268,17 @@
__raw_readw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
__raw_readl(c)); __r; })
+#define readl_relaxed_no_log(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+ __raw_readl_no_log(c)); __r; })
+
#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
cpu_to_le16(v),c))
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
cpu_to_le32(v),c))
+#define writel_relaxed_no_log(v, c) ((void)__raw_writel_no_log((__force u32) \
+ cpu_to_le32(v), c))
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index cd5be28..f705388 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -37,6 +37,7 @@
#define MT_MEMORY_RW 16
#define MT_MEMORY_RX 17
#define MT_MEMORY_DMA_READY 18
+#define MT_DEVICE_USER_ACCESSIBLE 19
#ifdef CONFIG_MMU
extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index d341ea9..e7de62e 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -149,7 +149,7 @@
int status_gpio;
/* Indicates the polarity of the GPIO line when card is inserted */
bool is_status_gpio_active_low;
- unsigned int sdiowakeup_irq;
+ int sdiowakeup_irq;
unsigned long irq_flags;
unsigned long mmc_bus_width;
int (*wpswitch) (struct device *);
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 88d0872..5188dbf 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -32,6 +32,10 @@
* interrupt and passed the address of the low level handler,
* and can be used to implement any platform specific handling
* before or after calling it.
+ * @request_pmu_irq: an optional handler in case the platform wants
+ * to use a percpu IRQ API call. e.g. request_percpu_irq
+ * @free_pmu_irq: an optional handler in case the platform wants
+ * to use a percpu IRQ API call. e.g. free_percpu_irq
* @enable_irq: an optional handler which will be called after
* request_irq and be used to handle some platform specific
* irq enablement
@@ -42,6 +46,8 @@
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
+ int (*request_pmu_irq)(int irq, irq_handler_t *irq_h);
+ void (*free_pmu_irq)(int irq);
void (*enable_irq)(int irq);
void (*disable_irq)(int irq);
};
@@ -114,8 +120,8 @@
u64 max_period;
struct platform_device *plat_device;
irqreturn_t (*handle_irq)(int irq_num, void *dev);
- int (*request_pmu_irq)(int irq, irq_handler_t *irq_h);
- void (*free_pmu_irq)(int irq);
+ int (*request_pmu_irq)(int irq, irq_handler_t *irq_h);
+ void (*free_pmu_irq)(int irq);
void (*enable)(struct hw_perf_event *evt, int idx, int cpu);
void (*disable)(struct hw_perf_event *evt, int idx);
int (*get_event_idx)(struct pmu_hw_events *hw_events,
diff --git a/arch/arm/include/asm/user_accessible_timer.h b/arch/arm/include/asm/user_accessible_timer.h
new file mode 100644
index 0000000..c6d7bd4
--- /dev/null
+++ b/arch/arm/include/asm/user_accessible_timer.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ARM_KERNEL_USER_ACCESSIBLE_TIMER_H_
+#define _ARM_KERNEL_USER_ACCESSIBLE_TIMER_H_
+
+#define ARM_USER_ACCESSIBLE_TIMERS_INVALID_PAGE -1
+
+extern unsigned long zero_pfn;
+
+#ifdef CONFIG_ARM_USE_USER_ACCESSIBLE_TIMERS
+#ifndef CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE
+#define CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE 0xfffef000
+#endif
+extern void setup_user_timer_offset(unsigned long addr);
+extern int get_timer_page_address(void);
+static inline int get_user_accessible_timers_base(void)
+{
+ return CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE;
+}
+extern void set_user_accessible_timer_flag(bool flag);
+#else
+#define CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE 0
+static inline void setup_user_timer_offset(unsigned long addr)
+{
+}
+static inline int get_timer_page_address(void)
+{
+ return ARM_USER_ACCESSIBLE_TIMERS_INVALID_PAGE;
+}
+static inline int get_user_accessible_timers_base(void)
+{
+ return 0;
+}
+static inline void set_user_accessible_timer_flag(bool flag)
+{
+}
+#endif
+
+#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 22b0f1e..fc00a23 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -63,6 +63,7 @@
obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o
CFLAGS_swp_emulate.o := -Wa,-march=armv7-a
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
+obj-$(CONFIG_GENERIC_TIME_VSYSCALL) += update_vsyscall_arm.o
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
@@ -73,6 +74,7 @@
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
+obj-$(CONFIG_ARM_USE_USER_ACCESSIBLE_TIMERS) += user_accessible_timer.o
ifneq ($(CONFIG_ARCH_EBSA110),y)
obj-y += io.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7a8c2d6..ddd421c 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -764,6 +764,97 @@
.align 5
.globl __kuser_helper_start
__kuser_helper_start:
+#ifdef GENERIC_TIME_VSYSCALL
+/*
+ * Reference declaration:
+ *
+ * extern struct timezone __kernel_helper_gtod_timezone
+ * extern unsigned int __kernel_helper_gtod_seqnum
+ *
+ * Definition and user space usage example:
+ *
+ * #define __kernel_helper_gtod_timezone (*(unsigned int*)0xffff0f20)
+ * #define __kernel_helper_gtod_seqnum (*(unsigned int*)0xffff0f28)
+ *
+ * unsigned int prelock, postlock ;
+ * do {
+ * prelock = __kernel_helper_gtod_seqnum;
+ * memcpy(&tz, (void*)&(__kernel_helper_gtod_timezone),
+ * sizeof(struct timezone)) ;
+ * postlock = __kernel_helper_gtod_seqnum;
+ * } while (prelock != postlock);
+ *
+ * 0xffff0f20-3: tz_minuteswest
+ * 0xffff0f24-7: tz_dsttime
+ * 0xffff0f28-b: sequence #.
+ * 0xffff0f30-3: offset into CONFIG_USER_ACCESSIBLE_TIMER_BASE to get the timer.
+ * 0xffff0f34-7: Feature flag
+ * 0xffff0f38-b: wall-to-mononic: tv_sec
+ * 0xffff0f3c-f: wall-to-mononic: tv_nsec
+ */
+ .globl __kuser_gtod_timezone
+__kuser_gtod_timezone: @0xffff0f20
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ /* This offset is where the flag to enable the
+ * user accessible timers is located.
+ */
+ .word 0
+ .word 0
+ .word 0
+ .align 5
+
+/*
+ * Reference declaration:
+ *
+ * extern struct timeval __kernel_helper_gtod_timeval
+ * extern unsigned int __kernel_helper_gtod_seqnum
+ *
+ * Definition and user space usage example:
+ *
+ * #define __kernel_helper_gtod_timeval (*(unsigned int*)0xffff0f40)
+ * #define __kernel_helper_gtod_seqnum (*(unsigned int*)0xffff0f48)
+ *
+ * unsigned int prelock, postlock ;
+ * struct gtod {
+ * uint64_t cycle_last;
+ * uint64_t mask;
+ * uint32_t mult;
+ * uint32_t shift;
+ * uint32_t tv_sec;
+ * uint32_t tv_nsec;
+ * };
+ * struct gtod gdtod;
+ *
+ * do {
+ * prelock = __kernel_helper_gtod_seqnum;
+ * memcpy(&gdtod, (void*)&(__kernel_helper_gtod_timeval),
+ * sizeof(struct gtod)) ;
+ * postlock = __kernel_helper_gtod_seqnum;
+ * } while (prelock != postlock);
+ *
+ * 0xffff0f40-7: cycle_last
+ * 0xffff0f48-f: mask
+ * 0xffff0f50-3: mult
+ * 0xffff0f54-7: shift
+ * 0xffff0f58-b: tv_sec
+ * 0xffff0f5c-f: tv_nsec
+ */
+ .globl __kuser_gtod_timeval
+__kuser_gtod_timeval: @0xffff0f40
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .align 5
+#endif
/*
* Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 3f6a6d3..2464140 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -437,6 +437,16 @@
else
handle_irq = armpmu->handle_irq;
+ if (plat && plat->request_pmu_irq)
+ armpmu->request_pmu_irq = plat->request_pmu_irq;
+ else
+ armpmu->request_pmu_irq = armpmu_generic_request_irq;
+
+ if (plat && plat->free_pmu_irq)
+ armpmu->free_pmu_irq = plat->free_pmu_irq;
+ else
+ armpmu->free_pmu_irq = armpmu_generic_free_irq;
+
irqs = min(pmu_device->num_resources, num_possible_cpus());
if (irqs < 1) {
pr_err("no irqs for PMUs defined\n");
diff --git a/arch/arm/kernel/perf_event_msm.c b/arch/arm/kernel/perf_event_msm.c
index 8f58adf..92dc7c7 100644
--- a/arch/arm/kernel/perf_event_msm.c
+++ b/arch/arm/kernel/perf_event_msm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -729,9 +729,6 @@
scorpion_pmu.name = "ARMv7 Scorpion";
scorpion_pmu.num_events = armv7_read_num_pmnc_events();
scorpion_pmu.pmu.attr_groups = msm_l1_pmu_attr_grps;
- /* Unicore can't use the percpu IRQ API. */
- scorpion_pmu.request_pmu_irq = armpmu_generic_request_irq;
- scorpion_pmu.free_pmu_irq = armpmu_generic_free_irq;
scorpion_clear_pmuregs();
return &scorpion_pmu;
}
@@ -742,8 +739,6 @@
scorpion_pmu.name = "ARMv7 Scorpion-MP";
scorpion_pmu.num_events = armv7_read_num_pmnc_events();
scorpion_pmu.pmu.attr_groups = msm_l1_pmu_attr_grps;
- scorpion_pmu.request_pmu_irq = msm_request_irq;
- scorpion_pmu.free_pmu_irq = msm_free_irq;
scorpion_clear_pmuregs();
return &scorpion_pmu;
}
diff --git a/arch/arm/kernel/perf_event_msm_krait.c b/arch/arm/kernel/perf_event_msm_krait.c
index eec614b..5708d74 100644
--- a/arch/arm/kernel/perf_event_msm_krait.c
+++ b/arch/arm/kernel/perf_event_msm_krait.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -520,53 +520,6 @@
armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
}
-static void enable_irq_callback(void *info)
-{
- int irq = *(unsigned int *)info;
-
- enable_percpu_irq(irq, IRQ_TYPE_EDGE_RISING);
-}
-
-static void disable_irq_callback(void *info)
-{
- int irq = *(unsigned int *)info;
-
- disable_percpu_irq(irq);
-}
-
-static int
-msm_request_irq(int irq, irq_handler_t *handle_irq)
-{
- int err = 0;
- int cpu;
-
- err = request_percpu_irq(irq, *handle_irq, "l1-armpmu",
- &cpu_hw_events);
-
- if (!err) {
- for_each_cpu(cpu, cpu_online_mask) {
- smp_call_function_single(cpu,
- enable_irq_callback, &irq, 1);
- }
- }
-
- return err;
-}
-
-static void
-msm_free_irq(int irq)
-{
- int cpu;
-
- if (irq >= 0) {
- for_each_cpu(cpu, cpu_online_mask) {
- smp_call_function_single(cpu,
- disable_irq_callback, &irq, 1);
- }
- free_percpu_irq(irq, &cpu_hw_events);
- }
-}
-
/*
* We check for column exclusion constraints here.
* Two events cant have same reg and same group.
@@ -621,8 +574,6 @@
static struct arm_pmu krait_pmu = {
.handle_irq = armv7pmu_handle_irq,
- .request_pmu_irq = msm_request_irq,
- .free_pmu_irq = msm_free_irq,
.enable = krait_pmu_enable_event,
.disable = krait_pmu_disable_event,
.read_counter = armv7pmu_read_counter,
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 3163b2a..678c55d 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1235,8 +1235,6 @@
}
static struct arm_pmu armv7pmu = {
- .request_pmu_irq = armpmu_generic_request_irq,
- .free_pmu_irq = armpmu_generic_free_irq,
.handle_irq = armv7pmu_handle_irq,
.enable = armv7pmu_enable_event,
.disable = armv7pmu_disable_event,
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index af21496..ac17480 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -680,6 +680,11 @@
const char *arch_vma_name(struct vm_area_struct *vma)
{
- return (vma == &gate_vma) ? "[vectors]" : NULL;
+ if (vma == &gate_vma)
+ return "[vectors]";
+ else if (vma == get_user_timers_vma(NULL))
+ return "[timers]";
+ else
+ return NULL;
}
#endif
diff --git a/arch/arm/kernel/update_vsyscall_arm.c b/arch/arm/kernel/update_vsyscall_arm.c
new file mode 100644
index 0000000..51f47ae
--- /dev/null
+++ b/arch/arm/kernel/update_vsyscall_arm.c
@@ -0,0 +1,100 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/clocksource.h>
+#include <linux/time.h>
+#include "update_vsyscall_arm.h"
+/*
+ * See entry-armv.S for the offsets into the kernel user helper for
+ * these fields.
+ */
+#define ARM_VSYSCALL_TIMER_TZ 0xf20
+#define ARM_VSYSCALL_TIMER_SEQ 0xf28
+#define ARM_VSYSCALL_TIMER_OFFSET 0xf30
+#define ARM_VSYSCALL_TIMER_WTM_TV_SEC 0xf38
+#define ARM_VSYSCALL_TIMER_WTM_TV_NSEC 0xf3c
+#define ARM_VSYSCALL_TIMER_CYCLE_LAST 0xf40
+#define ARM_VSYSCALL_TIMER_MASK 0xf48
+#define ARM_VSYSCALL_TIMER_MULT 0xf50
+#define ARM_VSYSCALL_TIMER_SHIFT 0xf54
+#define ARM_VSYSCALL_TIMER_TV_SEC 0xf58
+#define ARM_VSYSCALL_TIMER_TV_NSEC 0xf5c
+
+struct kernel_gtod_t {
+ u64 cycle_last;
+ u64 mask;
+ u32 mult;
+ u32 shift;
+ u32 tv_sec;
+ u32 tv_nsec;
+};
+
+struct kernel_tz_t {
+ u32 tz_minuteswest;
+ u32 tz_dsttime;
+};
+
+struct kernel_wtm_t {
+ u32 tv_sec;
+ u32 tv_nsec;
+};
+
+/*
+ * Updates the kernel user helper area with the current timespec
+ * data, as well as additional fields needed to calculate
+ * gettimeofday, clock_gettime, etc.
+ */
+void
+update_vsyscall(struct timespec *ts, struct timespec *wtm,
+ struct clocksource *c, u32 mult)
+{
+ unsigned long vectors = (unsigned long)vectors_page;
+ unsigned long flags;
+ unsigned *seqnum = (unsigned *)(vectors + ARM_VSYSCALL_TIMER_SEQ);
+ struct kernel_gtod_t *dgtod = (struct kernel_gtod_t *)(vectors +
+ ARM_VSYSCALL_TIMER_CYCLE_LAST);
+ struct kernel_wtm_t *dgwtm = (struct kernel_wtm_t *)(vectors +
+ ARM_VSYSCALL_TIMER_WTM_TV_SEC);
+
+ write_seqlock_irqsave(&kuh_time_lock, flags);
+ *seqnum = kuh_time_lock.sequence;
+ dgtod->cycle_last = c->cycle_last;
+ dgtod->mask = c->mask;
+ dgtod->mult = c->mult;
+ dgtod->shift = c->shift;
+ dgtod->tv_sec = ts->tv_sec;
+ dgtod->tv_nsec = ts->tv_nsec;
+ dgwtm->tv_sec = wtm->tv_sec;
+ dgwtm->tv_nsec = wtm->tv_nsec;
+ *seqnum = kuh_time_lock.sequence + 1;
+ write_sequnlock_irqrestore(&kuh_time_lock, flags);
+}
+EXPORT_SYMBOL(update_vsyscall);
+
+void
+update_vsyscall_tz(void)
+{
+ unsigned long vectors = (unsigned long)vectors_page;
+ unsigned long flags;
+ unsigned *seqnum = (unsigned *)(vectors + ARM_VSYSCALL_TIMER_SEQ);
+ struct kernel_tz_t *dgtod = (struct kernel_tz_t *)(vectors +
+ ARM_VSYSCALL_TIMER_TZ);
+
+ write_seqlock_irqsave(&kuh_time_lock, flags);
+ *seqnum = kuh_time_lock.sequence;
+ dgtod->tz_minuteswest = sys_tz.tz_minuteswest;
+ dgtod->tz_dsttime = sys_tz.tz_dsttime;
+ *seqnum = kuh_time_lock.sequence + 1;
+ write_sequnlock_irqrestore(&kuh_time_lock, flags);
+}
+EXPORT_SYMBOL(update_vsyscall_tz);
diff --git a/arch/arm/kernel/update_vsyscall_arm.h b/arch/arm/kernel/update_vsyscall_arm.h
new file mode 100644
index 0000000..d06ca56
--- /dev/null
+++ b/arch/arm/kernel/update_vsyscall_arm.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/export.h>
+#include <linux/clocksource.h>
+#include <linux/time.h>
+
+extern void *vectors_page;
+extern struct timezone sys_tz;
+
+/*
+ * This read-write spinlock protects us from races in SMP while
+ * updating the kernel user helper-embedded time.
+ */
+__cacheline_aligned_in_smp DEFINE_SEQLOCK(kuh_time_lock);
diff --git a/arch/arm/kernel/user_accessible_timer.c b/arch/arm/kernel/user_accessible_timer.c
new file mode 100644
index 0000000..c550c03
--- /dev/null
+++ b/arch/arm/kernel/user_accessible_timer.c
@@ -0,0 +1,132 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <asm/user_accessible_timer.h>
+#include <asm/traps.h>
+
+#define USER_ACCESS_TIMER_OFFSET 0xf30
+#define USER_ACCESS_FEATURE_OFFSET 0xf34
+#define USER_ACCESS_FEATURE_FLAG 0xffff0f20
+
+static struct vm_area_struct user_timers_vma;
+static int __init user_timers_vma_init(void)
+{
+ user_timers_vma.vm_start = CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE;
+ user_timers_vma.vm_end = CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE
+ + PAGE_SIZE;
+ user_timers_vma.vm_page_prot = PAGE_READONLY;
+ user_timers_vma.vm_flags = VM_READ | VM_MAYREAD;
+ return 0;
+}
+arch_initcall(user_timers_vma_init);
+
+int in_user_timers_area(struct mm_struct *mm, unsigned long addr)
+{
+ return (addr >= user_timers_vma.vm_start) &&
+ (addr < user_timers_vma.vm_end);
+}
+EXPORT_SYMBOL(in_user_timers_area);
+
+struct vm_area_struct *get_user_timers_vma(struct mm_struct *mm)
+{
+ return &user_timers_vma;
+}
+EXPORT_SYMBOL(get_user_timers_vma);
+
+int get_user_timer_page(struct vm_area_struct *vma,
+ struct mm_struct *mm, unsigned long start, unsigned int gup_flags,
+ struct page **pages, int idx, int *goto_next_page)
+{
+ /* Replicates the earlier work done in mm/memory.c */
+ unsigned long pg = start & PAGE_MASK;
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
+ pte_t *pte;
+
+ /* Unset this flag -- this only gets activated if the
+ * caller should go straight to the next_page label on
+ * return.
+ */
+ *goto_next_page = 0;
+
+ /* user gate pages are read-only */
+ if (gup_flags & FOLL_WRITE)
+ return idx ? : -EFAULT;
+ if (pg > TASK_SIZE)
+ pgd = pgd_offset_k(pg);
+ else
+ pgd = pgd_offset_gate(mm, pg);
+ BUG_ON(pgd_none(*pgd));
+ pud = pud_offset(pgd, pg);
+ BUG_ON(pud_none(*pud));
+ pmd = pmd_offset(pud, pg);
+ if (pmd_none(*pmd))
+ return idx ? : -EFAULT;
+ VM_BUG_ON(pmd_trans_huge(*pmd));
+ pte = pte_offset_map(pmd, pg);
+ if (pte_none(*pte)) {
+ pte_unmap(pte);
+ return idx ? : -EFAULT;
+ }
+ vma = get_user_timers_vma(mm);
+ if (pages) {
+ struct page *page;
+
+ page = vm_normal_page(vma, start, *pte);
+ if (!page) {
+ if (!(gup_flags & FOLL_DUMP) &&
+ zero_pfn == pte_pfn(*pte))
+ page = pte_page(*pte);
+ else {
+ pte_unmap(pte);
+ return idx ? : -EFAULT;
+ }
+ }
+ pages[idx] = page;
+ get_page(page);
+ }
+ pte_unmap(pte);
+ /* In this case, set the next page */
+ *goto_next_page = 1;
+ return 0;
+}
+EXPORT_SYMBOL(get_user_timer_page);
+
+void setup_user_timer_offset(unsigned long addr)
+{
+#if defined(CONFIG_CPU_USE_DOMAINS)
+ unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+ unsigned long vectors = (unsigned long)vectors_page;
+#endif
+ unsigned long *timer_offset = (unsigned long *)(vectors +
+ USER_ACCESS_TIMER_OFFSET);
+ *timer_offset = addr;
+}
+EXPORT_SYMBOL(setup_user_timer_offset);
+
+void set_user_accessible_timer_flag(bool flag)
+{
+#if defined(CONFIG_CPU_USE_DOMAINS)
+ unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+ unsigned long vectors = (unsigned long)vectors_page;
+#endif
+ unsigned long *timer_offset = (unsigned long *)(vectors +
+ USER_ACCESS_FEATURE_OFFSET);
+ *timer_offset = (flag ? USER_ACCESS_FEATURE_FLAG : 0);
+}
+EXPORT_SYMBOL(set_user_accessible_timer_flag);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 73e1ad2..a0868c7 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -177,6 +177,10 @@
select ARM_HAS_SG_CHAIN
select MSM_KRAIT_WFE_FIXUP
select MSM_ULTRASOUND_A
+ select GENERIC_TIME_VSYSCALL
+ select USE_USER_ACCESSIBLE_TIMERS
+ select ARM_USE_USER_ACCESSIBLE_TIMERS
+ select MSM_USE_USER_ACCESSIBLE_TIMERS
config ARCH_MSM8930
bool "MSM8930"
@@ -209,6 +213,10 @@
select HOLES_IN_ZONE if SPARSEMEM
select ARM_HAS_SG_CHAIN
select MSM_KRAIT_WFE_FIXUP
+ select GENERIC_TIME_VSYSCALL
+ select USE_USER_ACCESSIBLE_TIMERS
+ select ARM_USE_USER_ACCESSIBLE_TIMERS
+ select MSM_USE_USER_ACCESSIBLE_TIMERS
config ARCH_APQ8064
bool "APQ8064"
@@ -237,6 +245,10 @@
select ARM_HAS_SG_CHAIN
select MSM_KRAIT_WFE_FIXUP
select MSM_ULTRASOUND_A
+ select GENERIC_TIME_VSYSCALL
+ select USE_USER_ACCESSIBLE_TIMERS
+ select ARM_USE_USER_ACCESSIBLE_TIMERS
+ select MSM_USE_USER_ACCESSIBLE_TIMERS
config ARCH_MSM8974
bool "MSM8974"
@@ -265,6 +277,8 @@
select ARM_HAS_SG_CHAIN
select MSM_RUN_QUEUE_STATS
select MEMORY_HOLE_CARVEOUT
+ select MSM_RPM_STATS_LOG
+ select QMI_ENCDEC
config ARCH_MPQ8092
bool "MPQ8092"
@@ -278,30 +292,6 @@
select SPARSE_IRQ
select MSM_NOPM
-config ARCH_MSM8226
- bool "MSM8226"
- select ARCH_MSM_KRAITMP
- select GPIO_MSM_V3
- select ARM_GIC
- select CPU_V7
- select MSM_SCM if SMP
- select MSM_GPIOMUX
- select MULTI_IRQ_HANDLER
- select MSM_MULTIMEDIA_USE_ION
- select MSM_PIL
- select MSM_SPM_V2
- select MSM_L2_SPM
- select MSM_PM8X60 if PM
- select MAY_HAVE_SPARSE_IRQ
- select SPARSE_IRQ
- select MSM_RPM_SMD
- select REGULATOR
- select MSM_QDSP6_APRV2
- select MSM_QDSP6V2_CODECS
- select MSM_AUDIO_QDSP6V2 if SND_SOC
- select MSM_RPM_REGULATOR_SMD
- select ARM_HAS_SG_CHAIN
-
config ARCH_FSM9XXX
bool "FSM9XXX"
select ARCH_MSM_SCORPION
@@ -370,6 +360,10 @@
select MAY_HAVE_SPARSE_IRQ
select SPARSE_IRQ
select MSM_MULTIMEDIA_USE_ION
+ select MSM_RPM_STATS_LOG
+ select MSM_QDSP6_APRV2
+ select MSM_QDSP6V2_CODECS
+ select MSM_AUDIO_QDSP6V2 if SND_SOC
config ARCH_MSM8910
bool "MSM8910"
@@ -384,6 +378,22 @@
select MULTI_IRQ_HANDLER
select GPIO_MSM_V3
select MSM_GPIOMUX
+ select MSM_NATIVE_RESTART
+ select MSM_RESTART_V2
+
+config ARCH_MSM8226
+ bool "MSM8226"
+ select ARM_GIC
+ select GIC_SECURE
+ select SMP
+ select ARCH_MSM_CORTEXMP
+ select CPU_V7
+ select MSM_SCM if SMP
+ select MAY_HAVE_SPARSE_IRQ
+ select SPARSE_IRQ
+ select MULTI_IRQ_HANDLER
+ select GPIO_MSM_V3
+ select MSM_GPIOMUX
endmenu
choice
@@ -963,7 +973,7 @@
default "0x00000000" if ARCH_MSM8974
default "0x00000000" if ARCH_MPQ8092
default "0x00000000" if ARCH_MSM8226
- default "0x80200000" if ARCH_MSM8910
+ default "0x00000000" if ARCH_MSM8910
default "0x10000000" if ARCH_FSM9XXX
default "0x00200000" if ARCH_MSM9625
default "0x00200000" if !MSM_STACKED_MEMORY
@@ -1523,6 +1533,17 @@
help
SMD Transport Layer for IPC Router
+config MSM_QMI_INTERFACE
+ depends on MSM_IPC_ROUTER
+ depends on QMI_ENCDEC
+ default n
+ bool "MSM QMI Interface Library"
+ help
+ Library to send and receive QMI messages over IPC Router.
+ This library provides interface functions to the kernel drivers
+ to perform QMI message marshaling and transport them over IPC
+ Router.
+
config MSM_ONCRPCROUTER_DEBUG
depends on MSM_ONCRPCROUTER
default y
@@ -1982,18 +2003,14 @@
ADSP if the processor encounters a fatal error.
config MSM_PIL_MSS_QDSP6V5
- tristate "MSS QDSP6v5 (Hexagon) Boot Support"
- depends on MSM_PIL
- help
- Support for booting and shutting down QDSP6v5 (Hexagon) processors
- in modem subsystems.
-
-config MSM_PIL_MBA
- tristate "Support for modem self-authentication"
- depends on MSM_PIL_MSS_QDSP6V5 && MSM_SUBSYSTEM_RESTART
+ tristate "MSS QDSP6v5 (Hexagon) Boot Support"
+ depends on MSM_PIL && MSM_SUBSYSTEM_RESTART
help
- Support for booting self-authenticating modems using the Modem Boot
- Authenticator.
+ Support for booting and shutting down QDSP6v5 (Hexagon) processors
+ in modem subsystems. If you would like to make or receive phone
+ calls then say Y here.
+
+ If unsure, say N.
config MSM_PIL_RIVA
tristate "RIVA (WCNSS) Boot Support"
@@ -2099,7 +2116,7 @@
config MSM_RPM_STATS_LOG
tristate "MSM Resource Power Manager Stat Driver"
depends on DEBUG_FS
- depends on MSM_RPM
+ depends on MSM_RPM || MSM_RPM_SMD
default n
help
This option enables a driver which reads RPM messages from a shared
@@ -2659,4 +2676,12 @@
if apps is not responding and holding lock with irqs disabled.
Modem will then generate an raise a FIQ on this line before sending
SMSM reset.
+
+config MSM_USE_USER_ACCESSIBLE_TIMERS
+ bool "Enables mapping an MSM timer counter page to user space."
+ depends on ARM_USE_USER_ACCESSIBLE_TIMERS
+ help
+ Enables MSM-specific user accessible timers via a shared
+ memory page containing the cycle counter.
+
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index fe5fe8c..2c7424e 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -46,15 +46,15 @@
endif
obj-$(CONFIG_SMP) += headsmp.o
+ifdef CONFIG_ARCH_MSM_CORTEXMP
ifdef CONFIG_ARCH_MSM8625
obj-$(CONFIG_SMP) += platsmp-8625.o
else
-ifdef CONFIG_ARCH_MSM8910
obj-$(CONFIG_SMP) += platsmp-8910.o
+endif
else
obj-$(CONFIG_SMP) += platsmp.o
endif
-endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_MSM_CPU_AVS) += avs.o
@@ -84,7 +84,6 @@
obj-$(CONFIG_MSM_PIL_MODEM_QDSP6V4) += pil-q6v4.o pil-q6v4-mss.o
obj-$(CONFIG_MSM_PIL_LPASS_QDSP6V5) += pil-q6v5.o pil-q6v5-lpass.o
obj-$(CONFIG_MSM_PIL_MSS_QDSP6V5) += pil-q6v5.o pil-q6v5-mss.o
-obj-$(CONFIG_MSM_PIL_MBA) += pil-mba.o
obj-$(CONFIG_MSM_PIL_RIVA) += pil-riva.o
obj-$(CONFIG_MSM_PIL_TZAPPS) += pil-tzapps.o
obj-$(CONFIG_MSM_PIL_VIDC) += pil-vidc.o
@@ -139,6 +138,7 @@
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_device.o
obj-$(CONFIG_MSM_IPC_ROUTER) += ipc_router.o
obj-$(CONFIG_MSM_IPC_ROUTER)+= ipc_socket.o
+obj-$(CONFIG_MSM_QMI_INTERFACE) += msm_qmi_interface.o
obj-$(CONFIG_DEBUG_FS) += smd_rpc_sym.o
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_servers.o
obj-$(CONFIG_MSM_ONCRPCROUTER) += smd_rpcrouter_clients.o
@@ -282,6 +282,7 @@
obj-$(CONFIG_MACH_MSM8930_MTP) += board-8930-all.o board-8930-regulator-pm8038.o board-8930-regulator-pm8917.o
obj-$(CONFIG_MACH_MSM8930_FLUID) += board-8930-all.o board-8930-regulator-pm8038.o board-8930-regulator-pm8917.o
obj-$(CONFIG_PM8921_BMS) += bms-batterydata.o bms-batterydata-desay.o batterydata-lib.o
+obj-$(CONFIG_QPNP_BMS) += bms-batterydata.o bms-batterydata-desay.o batterydata-lib.o
obj-$(CONFIG_MACH_APQ8064_CDP) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_APQ8064_MTP) += board-8064-all.o board-8064-regulator.o
obj-$(CONFIG_MACH_APQ8064_LIQUID) += board-8064-all.o board-8064-regulator.o
@@ -294,13 +295,14 @@
obj-$(CONFIG_ARCH_MSM8974) += clock-local2.o clock-pll.o clock-8974.o clock-rpm.o clock-voter.o clock-mdss-8974.o
obj-$(CONFIG_ARCH_MSM8974) += gdsc.o
obj-$(CONFIG_ARCH_MSM9625) += gdsc.o
+obj-$(CONFIG_ARCH_MSM8226) += gdsc.o
obj-$(CONFIG_ARCH_MSM8974) += krait-regulator.o
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += clock-local2.o clock-pll.o clock-9625.o clock-rpm.o clock-voter.o acpuclock-9625.o
-obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o
+obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o acpuclock-8930ab.o
obj-$(CONFIG_ARCH_MPQ8092) += board-8092.o board-8092-gpiomux.o
obj-$(CONFIG_ARCH_MSM8226) += board-8226.o board-8226-gpiomux.o
-obj-$(CONFIG_ARCH_MSM8910) += board-8910.o
+obj-$(CONFIG_ARCH_MSM8910) += board-8910.o board-8910-gpiomux.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
@@ -397,6 +399,8 @@
obj-$(CONFIG_MSM_ENABLE_WDOG_DEBUG_CONTROL) += wdog_debug.o
+obj-$(CONFIG_MSM_USE_USER_ACCESSIBLE_TIMERS) += timer_page.o
+
ifdef CONFIG_MSM_CPR
obj-$(CONFIG_DEBUG_FS) += msm_cpr-debug.o
endif
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index fa9ee54..cf1f401 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -66,4 +66,4 @@
zreladdr-$(CONFIG_ARCH_MPQ8092) := 0x00008000
# MSM8910
- zreladdr-$(CONFIG_ARCH_MSM8910) := 0x80208000
+ zreladdr-$(CONFIG_ARCH_MSM8910) := 0x00008000
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index cda952f..88237af 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -233,40 +233,40 @@
};
static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 912500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 962500 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 987500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1012500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1025000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1075000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1112500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1200000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1262500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 962500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1000000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1037500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1062500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1175000 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1225000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1287500 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS1_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 962500 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 987500 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 937500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1062500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1087500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1187500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1237500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1275000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1037500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1100000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1137500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1187500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1250000 },
{ 0, { 0 } }
};
@@ -275,17 +275,17 @@
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 987500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1000000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1050000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1112500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1162500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1212500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1250000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 912500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1112500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1162500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1212500 },
{ 0, { 0 } }
};
@@ -295,44 +295,44 @@
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 950000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 912500 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 937500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 962500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 975000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1037500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1112500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1162500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1200000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1000000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1025000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1050000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1087500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1137500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1175000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS4_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 950000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 975000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1000000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1037500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1062500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1075000 },
{ 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1112500 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1150000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS5_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
@@ -340,18 +340,18 @@
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 987500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1012500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1037500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1050000 },
{ 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1087500 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1125000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 900000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },
diff --git a/arch/arm/mach-msm/acpuclock-8930ab.c b/arch/arm/mach-msm/acpuclock-8930ab.c
new file mode 100644
index 0000000..764ae41
--- /dev/null
+++ b/arch/arm/mach-msm/acpuclock-8930ab.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <mach/rpm-regulator.h>
+#include <mach/msm_bus_board.h>
+#include <mach/msm_bus.h>
+
+#include "acpuclock.h"
+#include "acpuclock-krait.h"
+
+/* Corner type vreg VDD values */
+#define LVL_NONE RPM_VREG_CORNER_NONE
+#define LVL_LOW RPM_VREG_CORNER_LOW
+#define LVL_NOM RPM_VREG_CORNER_NOMINAL
+#define LVL_HIGH RPM_VREG_CORNER_HIGH
+
+static struct hfpll_data hfpll_data __initdata = {
+ .mode_offset = 0x00,
+ .l_offset = 0x08,
+ .m_offset = 0x0C,
+ .n_offset = 0x10,
+ .config_offset = 0x04,
+ .config_val = 0x7845C665,
+ .has_droop_ctl = true,
+ .droop_offset = 0x14,
+ .droop_val = 0x0108C000,
+ .low_vdd_l_max = 37,
+ .nom_vdd_l_max = 74,
+ .vdd[HFPLL_VDD_NONE] = LVL_NONE,
+ .vdd[HFPLL_VDD_LOW] = LVL_LOW,
+ .vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
+};
+
+static struct scalable scalable_pm8917[] __initdata = {
+ [CPU0] = {
+ .hfpll_phys_base = 0x00903200,
+ .aux_clk_sel_phys = 0x02088014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x4501,
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
+ },
+ [CPU1] = {
+ .hfpll_phys_base = 0x00903300,
+ .aux_clk_sel_phys = 0x02098014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x5501,
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
+ },
+ [L2] = {
+ .hfpll_phys_base = 0x00903400,
+ .aux_clk_sel_phys = 0x02011028,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x0500,
+ .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
+ },
+};
+
+static struct scalable scalable[] __initdata = {
+ [CPU0] = {
+ .hfpll_phys_base = 0x00903200,
+ .aux_clk_sel_phys = 0x02088014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x4501,
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
+ },
+ [CPU1] = {
+ .hfpll_phys_base = 0x00903300,
+ .aux_clk_sel_phys = 0x02098014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x5501,
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
+ },
+ [L2] = {
+ .hfpll_phys_base = 0x00903400,
+ .aux_clk_sel_phys = 0x02011028,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x0500,
+ .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
+ },
+};
+
+static struct msm_bus_paths bw_level_tbl[] __initdata = {
+ [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
+ [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
+ [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
+ [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
+ [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
+ [5] = BW_MBPS(4800), /* At least 600 MHz on bus. */
+};
+
+static struct msm_bus_scale_pdata bus_scale_data __initdata = {
+ .usecase = bw_level_tbl,
+ .num_usecases = ARRAY_SIZE(bw_level_tbl),
+ .active_only = 1,
+ .name = "acpuclk-8930ab",
+};
+
+/* TODO: Update new L2 freqs once they are available */
+static struct l2_level l2_freq_tbl[] __initdata = {
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 5 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 5 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 5 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 5 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 5 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 5 },
+ { }
+};
+
+static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+/* TODO: Update boost voltage once the pvs data is available */
+static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
+[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 0 },
+[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 0 },
+};
+
+static struct acpuclk_krait_params acpuclk_8930ab_params __initdata = {
+ .scalable = scalable,
+ .scalable_size = sizeof(scalable),
+ .hfpll_data = &hfpll_data,
+ .pvs_tables = pvs_tables,
+ .l2_freq_tbl = l2_freq_tbl,
+ .l2_freq_tbl_size = sizeof(l2_freq_tbl),
+ .bus_scale = &bus_scale_data,
+ .pte_efuse_phys = 0x007000C0,
+ .stby_khz = 384000,
+};
+
+static int __init acpuclk_8930ab_probe(struct platform_device *pdev)
+{
+ struct acpuclk_platform_data *pdata = pdev->dev.platform_data;
+ if (pdata && pdata->uses_pm8917)
+ acpuclk_8930ab_params.scalable = scalable_pm8917;
+
+ return acpuclk_krait_init(&pdev->dev, &acpuclk_8930ab_params);
+}
+
+static struct platform_driver acpuclk_8930ab_driver = {
+ .driver = {
+ .name = "acpuclk-8930ab",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init acpuclk_8930ab_init(void)
+{
+ return platform_driver_probe(&acpuclk_8930ab_driver,
+ acpuclk_8930ab_probe);
+}
+device_initcall(acpuclk_8930ab_init);
diff --git a/arch/arm/mach-msm/acpuclock-8960ab.c b/arch/arm/mach-msm/acpuclock-8960ab.c
index ae1cd7b..03a2004 100644
--- a/arch/arm/mach-msm/acpuclock-8960ab.c
+++ b/arch/arm/mach-msm/acpuclock-8960ab.c
@@ -105,40 +105,140 @@
{ }
};
-static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
+static struct acpu_level freq_tbl_PVS0[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(3), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(3), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(3), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(3), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(3), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(3), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(9), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(9), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(9), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(9), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(9), 1250000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1250000 },
- { 1, { 1620000, HFPLL, 1, 0x3C }, L2(9), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1250000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 975000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 1000000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 1025000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1050000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1100000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1150000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1175000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1200000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1225000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1250000 },
{ 0, { 0 } }
};
+static struct acpu_level freq_tbl_PVS1[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 925000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 950000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1125000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1150000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1175000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1225000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level freq_tbl_PVS2[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 975000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1025000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1050000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1075000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1100000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1125000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level freq_tbl_PVS3[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 925000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 950000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 1000000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1050000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1075000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1175000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level freq_tbl_PVS4[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 925000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 975000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1000000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1025000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1050000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1075000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1100000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1125000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1150000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level freq_tbl_PVS5[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 875000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 875000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 975000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1000000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1025000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1050000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1100000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level freq_tbl_PVS6[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(3), 850000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(3), 850000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(3), 850000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(3), 875000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(3), 900000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(3), 925000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 950000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 975000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1000000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1025000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1050000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1075000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1100000 },
+ { 0, { 0 } }
+};
+
static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_NOMINAL] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_FAST] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
+[0][0] = { freq_tbl_PVS0, sizeof(freq_tbl_PVS0), 0 },
+[0][1] = { freq_tbl_PVS1, sizeof(freq_tbl_PVS1), 0 },
+[0][2] = { freq_tbl_PVS2, sizeof(freq_tbl_PVS2), 0 },
+[0][3] = { freq_tbl_PVS3, sizeof(freq_tbl_PVS3), 0 },
+[0][4] = { freq_tbl_PVS4, sizeof(freq_tbl_PVS4), 0 },
+[0][5] = { freq_tbl_PVS5, sizeof(freq_tbl_PVS5), 0 },
+[0][6] = { freq_tbl_PVS6, sizeof(freq_tbl_PVS6), 0 },
};
static struct acpuclk_krait_params acpuclk_8960ab_params __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 61213cf..0fbd6dc 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -113,14 +113,14 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
- [1] = { { 384000, HFPLL, 2, 40 }, LVL_NOM, 950000, 1 },
- [2] = { { 460800, HFPLL, 2, 48 }, LVL_NOM, 950000, 1 },
- [3] = { { 537600, HFPLL, 1, 28 }, LVL_NOM, 950000, 2 },
- [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 2 },
- [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 2 },
- [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 2 },
- [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 2 },
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 1050000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_NOM, 1050000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_NOM, 1050000, 1 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 1050000, 2 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 1050000, 2 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 1050000, 2 },
[8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 2 },
[9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 2 },
[10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 3 },
@@ -143,30 +143,30 @@
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 100000 },
- { 1, { 384000, HFPLL, 2, 40 }, L2(3), 950000, 3200000 },
- { 1, { 460800, HFPLL, 2, 48 }, L2(3), 950000, 3200000 },
- { 1, { 537600, HFPLL, 1, 28 }, L2(5), 950000, 3200000 },
- { 1, { 576000, HFPLL, 1, 30 }, L2(5), 950000, 3200000 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(5), 950000, 3200000 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(5), 950000, 3200000 },
- { 1, { 806400, HFPLL, 1, 42 }, L2(7), 950000, 3200000 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(7), 950000, 3200000 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(7), 950000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(7), 950000, 3200000 },
- { 1, { 1113600, HFPLL, 1, 58 }, L2(12), 1050000, 3200000 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(12), 1050000, 3200000 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(12), 1050000, 3200000 },
- { 1, { 1344000, HFPLL, 1, 70 }, L2(15), 1050000, 3200000 },
- { 1, { 1420800, HFPLL, 1, 74 }, L2(15), 1050000, 3200000 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
- { 0, { 1574400, HFPLL, 1, 82 }, L2(20), 1050000, 3200000 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(20), 1050000, 3200000 },
- { 0, { 1728000, HFPLL, 1, 90 }, L2(20), 1050000, 3200000 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(25), 1050000, 3200000 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(25), 1050000, 3200000 },
- { 0, { 1958400, HFPLL, 1, 102 }, L2(25), 1050000, 3200000 },
- { 0, { 1996800, HFPLL, 1, 104 }, L2(25), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 850000, 100000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(0), 850000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(0), 850000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(0), 850000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(0), 850000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(16), 850000, 3200000 },
+ { 0, { 729600, HFPLL, 1, 38 }, L2(16), 850000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 42 }, L2(16), 850000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(16), 870000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(16), 880000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(16), 900000, 3200000 },
+ { 1, { 1113600, HFPLL, 1, 58 }, L2(16), 915000, 3200000 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(16), 935000, 3200000 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(16), 950000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(16), 970000, 3200000 },
+ { 1, { 1420800, HFPLL, 1, 74 }, L2(16), 985000, 3200000 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1000000, 3200000 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(16), 1015000, 3200000 },
+ { 1, { 1651200, HFPLL, 1, 86 }, L2(16), 1030000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(16), 1050000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(16), 1050000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(16), 1050000, 3200000 },
+ { 0, { 1996800, HFPLL, 1, 104 }, L2(16), 1050000, 3200000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-9625.c b/arch/arm/mach-msm/acpuclock-9625.c
index 7fd00e6..b0556c3 100644
--- a/arch/arm/mach-msm/acpuclock-9625.c
+++ b/arch/arm/mach-msm/acpuclock-9625.c
@@ -386,7 +386,7 @@
{
unsigned long max_cpu_khz = 0;
struct resource *res;
- int i;
+ int i, rc;
u32 regval;
mutex_init(&drv_data.lock);
@@ -447,12 +447,43 @@
acpu_freq_tbl[i].use_for_scaling; i++)
max_cpu_khz = acpu_freq_tbl[i].khz;
+ /* Initialize regulators */
+ rc = increase_vdd(acpu_freq_tbl[i].vdd_cpu, acpu_freq_tbl[i].vdd_mem);
+ if (rc)
+ goto err_vdd;
+
+ rc = regulator_enable(drv_data.vdd_mem);
+ if (rc) {
+ dev_err(&pdev->dev, "regulator_enable for a5_mem failed\n");
+ goto err_vdd;
+ }
+
+ rc = regulator_enable(drv_data.vdd_cpu);
+ if (rc) {
+ dev_err(&pdev->dev, "regulator_enable for a5_cpu failed\n");
+ goto err_vdd_cpu;
+ }
+
acpuclk_9625_set_rate(smp_processor_id(), max_cpu_khz, SETRATE_INIT);
acpuclk_register(&acpuclk_9625_data);
cpufreq_table_init();
return 0;
+
+err_vdd_cpu:
+ regulator_disable(drv_data.vdd_mem);
+err_vdd:
+ regulator_put(drv_data.vdd_mem);
+ regulator_put(drv_data.vdd_cpu);
+
+ for (i = 0; i < NUM_SRC; i++) {
+ if (!src_clocks[i].name)
+ continue;
+ clk_unprepare(src_clocks[i].clk);
+ clk_put(src_clocks[i].clk);
+ }
+ return rc;
}
static struct of_device_id acpuclk_9625_match_table[] = {
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index bf57eab..10c4d6c 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -33,6 +33,7 @@
#include <mach/rpm-regulator.h>
#include <mach/rpm-regulator-smd.h>
#include <mach/msm_bus.h>
+#include <mach/msm_dcvs.h>
#include "acpuclock.h"
#include "acpuclock-krait.h"
@@ -951,6 +952,17 @@
static void __init cpufreq_table_init(void) {}
#endif
+static void __init dcvs_freq_init(void)
+{
+ int i;
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz != 0; i++)
+ if (drv.acpu_freq_tbl[i].use_for_scaling)
+ msm_dcvs_register_cpu_freq(
+ drv.acpu_freq_tbl[i].speed.khz,
+ drv.acpu_freq_tbl[i].vdd_core / 1000);
+}
+
static int __cpuinit acpuclk_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
@@ -965,7 +977,11 @@
/* Fall through. */
case CPU_UP_CANCELED:
acpuclk_krait_set_rate(cpu, hot_unplug_khz, SETRATE_HOTPLUG);
+
+ regulator_disable(sc->vreg[VREG_CORE].reg);
regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg, 0);
+ regulator_set_voltage(sc->vreg[VREG_CORE].reg, 0,
+ sc->vreg[VREG_CORE].max_vdd);
break;
case CPU_UP_PREPARE:
if (!sc->initialized) {
@@ -976,10 +992,20 @@
}
if (WARN_ON(!prev_khz[cpu]))
return NOTIFY_BAD;
+
+ rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
+ sc->vreg[VREG_CORE].cur_vdd,
+ sc->vreg[VREG_CORE].max_vdd);
+ if (rc < 0)
+ return NOTIFY_BAD;
rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
sc->vreg[VREG_CORE].cur_ua);
if (rc < 0)
return NOTIFY_BAD;
+ rc = regulator_enable(sc->vreg[VREG_CORE].reg);
+ if (rc < 0)
+ return NOTIFY_BAD;
+
acpuclk_krait_set_rate(cpu, prev_khz[cpu], SETRATE_HOTPLUG);
break;
default:
@@ -1156,6 +1182,7 @@
hw_init();
cpufreq_table_init();
+ dcvs_freq_init();
acpuclk_register(&acpuclk_krait_data);
register_hotcpu_notifier(&acpuclk_cpu_notifier);
diff --git a/arch/arm/mach-msm/avs.h b/arch/arm/mach-msm/avs.h
index a549e9d..e87bded 100644
--- a/arch/arm/mach-msm/avs.h
+++ b/arch/arm/mach-msm/avs.h
@@ -37,7 +37,8 @@
u32 avs_get_avsdscr(void);
u32 avs_get_tscsr(void);
void avs_set_tscsr(u32 to_tscsr);
-void avs_disable(void);
+u32 avs_disable(void);
+void avs_enable(u32 avscsr);
#else
static inline u32 avs_reset_delays(u32 avsdscr)
{ return 0; }
@@ -48,7 +49,9 @@
static inline u32 avs_get_tscsr(void)
{ return 0; }
static inline void avs_set_tscsr(u32 to_tscsr) {}
-static inline void avs_disable(void) {}
+static inline u32 avs_disable(void)
+{return 0; }
+static inline void avs_enable(u32 avscsr) {}
#endif
/*#define AVSDEBUG(x...) pr_info("AVS: " x);*/
@@ -60,9 +63,13 @@
put_cpu(); \
} while (0);
+/* AVSCSR(0x61) to enable CPU, V and L2 AVS module */
+
#define AVS_ENABLE(cpu, x) do { \
- if (get_cpu() == (cpu)) \
+ if (get_cpu() == (cpu)) { \
avs_reset_delays((x)); \
+ avs_enable(0x61); \
+ } \
put_cpu(); \
} while (0);
diff --git a/arch/arm/mach-msm/avs_hw.S b/arch/arm/mach-msm/avs_hw.S
index 1cc3ce0..efb9c47 100644
--- a/arch/arm/mach-msm/avs_hw.S
+++ b/arch/arm/mach-msm/avs_hw.S
@@ -102,23 +102,23 @@
/* Read r0=AVSDSCR */
mrc p15, 7, r0, c15, c0, 6
-
-/* AVSCSR(0x61) to enable CPU, V and L2 AVS module */
- mov r3, #0x61
- mcr p15, 7, r3, c15, c1, 7
-
bx lr
-
+ .global avs_enable
+avs_enable:
+/* Restore the avs_scr register */
+ mcr p15, 7, r0, c15, c1, 7
+ bx lr
.global avs_disable
avs_disable:
+/* Get the AVSCSR value */
+ mrc p15, 7, r0, c15, c1, 7
/* Clear AVSCSR */
- mov r0, #0
-
+ mov r1, #0
/* Write AVSCSR */
- mcr p15, 7, r0, c15, c1, 7
+ mcr p15, 7, r1, c15, c1, 7
bx lr
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 7ba22f4..c475e2d 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -193,6 +193,7 @@
static struct sps_mem_buffer rx_desc_mem_buf;
static struct sps_register_event tx_register_event;
static struct sps_register_event rx_register_event;
+static bool satellite_mode;
static struct bam_ch_info bam_ch[BAM_DMUX_NUM_CHANNELS];
static int bam_mux_initialized;
@@ -2074,7 +2075,7 @@
a2_props.options = SPS_BAM_OPT_IRQ_WAKEUP;
a2_props.num_pipes = A2_NUM_PIPES;
a2_props.summing_threshold = A2_SUMMING_THRESHOLD;
- if (cpu_is_msm9615())
+ if (cpu_is_msm9615() || satellite_mode)
a2_props.manage = SPS_BAM_MGR_DEVICE_REMOTE;
/* need to free on tear down */
ret = sps_register_bam_device(&a2_props, &h);
@@ -2246,7 +2247,7 @@
a2_props.options = SPS_BAM_OPT_IRQ_WAKEUP;
a2_props.num_pipes = A2_NUM_PIPES;
a2_props.summing_threshold = A2_SUMMING_THRESHOLD;
- if (cpu_is_msm9615())
+ if (cpu_is_msm9615() || satellite_mode)
a2_props.manage = SPS_BAM_MGR_DEVICE_REMOTE;
ret = sps_register_bam_device(&a2_props, &h);
if (ret < 0) {
@@ -2374,10 +2375,14 @@
pr_err("%s: irq field missing\n", __func__);
return -ENODEV;
}
- DBG("%s: base:%p size:%x irq:%d\n", __func__,
+ satellite_mode = of_property_read_bool(pdev->dev.of_node,
+ "qcom,satellite-mode");
+
+ DBG("%s: base:%p size:%x irq:%d satellite:%d\n", __func__,
a2_phys_base,
a2_phys_size,
- a2_bam_irq);
+ a2_bam_irq,
+ satellite_mode);
} else { /* fallback to default init data */
a2_phys_base = (void *)(A2_PHYS_BASE);
a2_phys_size = A2_PHYS_SIZE;
diff --git a/arch/arm/mach-msm/board-8064-camera.c b/arch/arm/mach-msm/board-8064-camera.c
index 0a95e51..76d2844 100644
--- a/arch/arm/mach-msm/board-8064-camera.c
+++ b/arch/arm/mach-msm/board-8064-camera.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -187,8 +187,22 @@
#define VFE_CAMIF_TIMER1_GPIO 3
#define VFE_CAMIF_TIMER2_GPIO 1
+static struct gpio flash_init_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER1"},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER2"},
+};
+
+static struct msm_gpio_set_tbl flash_set_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+};
+
static struct msm_camera_sensor_flash_src msm_flash_src = {
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
+ .init_gpio_tbl = flash_init_gpio,
+ .init_gpio_tbl_size = ARRAY_SIZE(flash_init_gpio),
+ .set_gpio_tbl = flash_set_gpio,
+ .set_gpio_tbl_size = ARRAY_SIZE(flash_set_gpio),
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_SC628A,
@@ -531,9 +545,15 @@
.sensor_type = BAYER_SENSOR,
};
+static struct i2c_board_info sc628a_flash_i2c_info = {
+ I2C_BOARD_INFO("sc628a", 0x6E),
+};
+
static struct msm_camera_sensor_flash_data flash_imx074 = {
.flash_type = MSM_CAMERA_FLASH_LED,
- .flash_src = &msm_flash_src
+ .flash_src = &msm_flash_src,
+ .board_info = &sc628a_flash_i2c_info,
+ .bus_id = APQ_8064_GSBI4_QUP_I2C_BUS_ID,
};
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
@@ -740,9 +760,6 @@
.platform_data = &msm_camera_sensor_ov2720_data,
},
{
- I2C_BOARD_INFO("sc628a", 0x6E),
- },
- {
I2C_BOARD_INFO("imx091", 0x34),
.platform_data = &msm_camera_sensor_imx091_data,
},
diff --git a/arch/arm/mach-msm/board-8064-gpu.c b/arch/arm/mach-msm/board-8064-gpu.c
index f35ae6b..5ebb010 100644
--- a/arch/arm/mach-msm/board-8064-gpu.c
+++ b/arch/arm/mach-msm/board-8064-gpu.c
@@ -226,7 +226,7 @@
.io_fraction = 0,
},
{
- .gpu_freq = 325000000,
+ .gpu_freq = 320000000,
.bus_freq = 3,
.io_fraction = 33,
},
diff --git a/arch/arm/mach-msm/board-8064-pmic.c b/arch/arm/mach-msm/board-8064-pmic.c
index c973bd5..fe2d2d2 100644
--- a/arch/arm/mach-msm/board-8064-pmic.c
+++ b/arch/arm/mach-msm/board-8064-pmic.c
@@ -395,7 +395,6 @@
#define CHG_TERM_MA 100
static struct pm8921_charger_platform_data
apq8064_pm8921_chg_pdata __devinitdata = {
- .safety_time = 180,
.update_time = 60000,
.max_voltage = MAX_VOLTAGE_MV,
.min_voltage = 3200,
@@ -420,14 +419,14 @@
static struct pm8xxx_ccadc_platform_data
apq8064_pm8xxx_ccadc_pdata = {
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.calib_delay_ms = 600000,
};
static struct pm8921_bms_platform_data
apq8064_pm8921_bms_pdata __devinitdata = {
.battery_type = BATT_UNKNOWN,
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.v_cutoff = 3400,
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
.rconn_mohm = 18,
diff --git a/arch/arm/mach-msm/board-8064-regulator.c b/arch/arm/mach-msm/board-8064-regulator.c
index 851f7d9..a66495d 100644
--- a/arch/arm/mach-msm/board-8064-regulator.c
+++ b/arch/arm/mach-msm/board-8064-regulator.c
@@ -455,7 +455,8 @@
{ \
.constraints = { \
.name = _name, \
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
+ REGULATOR_CHANGE_STATUS, \
.min_uV = _min_uV, \
.max_uV = _max_uV, \
}, \
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index c6bcb6b..95246a7 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -693,12 +693,6 @@
static struct msm_bus_vectors hsic_init_vectors[] = {
{
.src = MSM_BUS_MASTER_SPS,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 0,
- .ib = 0,
- },
- {
- .src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ab = 0,
.ib = 0,
@@ -709,15 +703,9 @@
static struct msm_bus_vectors hsic_max_vectors[] = {
{
.src = MSM_BUS_MASTER_SPS,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 60000000, /* At least 480Mbps on bus. */
- .ib = 960000000, /* MAX bursts rate */
- },
- {
- .src = MSM_BUS_MASTER_SPS,
.dst = MSM_BUS_SLAVE_SPS,
.ab = 0,
- .ib = 512000000, /*vote for 64Mhz dfab clk rate*/
+ .ib = 256000000, /*vote for 32Mhz dfab clk rate*/
},
};
@@ -1257,29 +1245,20 @@
* clock is running at 100KHz and voltage levels are at 3.3
* and 5 volts
*/
-static int enable_100KHz_ls(int enable)
+static int enable_100KHz_ls(int enable, int gpio)
{
- int ret = 0;
- if (enable) {
- ret = gpio_request(SX150X_GPIO(1, 10),
- "cs8427_100KHZ_ENABLE");
- if (ret) {
- pr_err("%s: Failed to request gpio %d\n", __func__,
- SX150X_GPIO(1, 10));
- return ret;
- }
- gpio_direction_output(SX150X_GPIO(1, 10), 1);
- } else {
- gpio_direction_output(SX150X_GPIO(1, 10), 0);
- gpio_free(SX150X_GPIO(1, 10));
- }
- return ret;
+ if (enable)
+ gpio_direction_output(gpio, 1);
+ else
+ gpio_direction_output(gpio, 0);
+ return 0;
}
static struct cs8427_platform_data cs8427_i2c_platform_data = {
.irq = SX150X_GPIO(1, 4),
.reset_gpio = SX150X_GPIO(1, 6),
.enable = enable_100KHz_ls,
+ .ls_gpio = SX150X_GPIO(1, 10),
};
static struct i2c_board_info cs8427_device_info[] __initdata = {
@@ -1397,7 +1376,7 @@
/* T6 Object */
0, 0, 0, 0, 0, 0,
/* T38 Object */
- 14, 3, 0, 5, 7, 12, 0, 0, 0, 0,
+ 14, 4, 0, 5, 11, 12, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1405,7 +1384,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* T7 Object */
- 32, 10, 50,
+ 32, 8, 50,
/* T8 Object */
25, 0, 20, 20, 0, 0, 0, 0, 0, 0,
/* T9 Object */
@@ -2132,6 +2111,21 @@
0x24, 0x30, 0x0f,
};
+/* 8064AB has a different command to assert apc_pdn */
+static uint8_t spm_power_collapse_without_rpm_krait_v3[] __initdata = {
+ 0x00, 0x24, 0x84, 0x10,
+ 0x09, 0x03, 0x01,
+ 0x10, 0x84, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
+static uint8_t spm_power_collapse_with_rpm_krait_v3[] __initdata = {
+ 0x00, 0x24, 0x84, 0x10,
+ 0x09, 0x07, 0x01, 0x0B,
+ 0x10, 0x84, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
static struct msm_spm_seq_entry msm_spm_boot_cpu_seq_list[] __initdata = {
[0] = {
.mode = MSM_SPM_MODE_CLOCK_GATING,
@@ -2284,6 +2278,27 @@
},
};
+static void __init apq8064ab_update_krait_spm(void)
+{
+ int i;
+
+ /* Update the SPM sequences for SPC and PC */
+ for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
+ int j;
+ struct msm_spm_platform_data *pdata = &msm_spm_data[i];
+ for (j = 0; j < pdata->num_modes; j++) {
+ if (pdata->modes[j].cmd ==
+ spm_power_collapse_without_rpm)
+ pdata->modes[j].cmd =
+ spm_power_collapse_without_rpm_krait_v3;
+ else if (pdata->modes[j].cmd ==
+ spm_power_collapse_with_rpm)
+ pdata->modes[j].cmd =
+ spm_power_collapse_with_rpm_krait_v3;
+ }
+ }
+}
+
static void __init apq8064_init_buses(void)
{
msm_bus_rpm_set_mt_mask();
@@ -2524,6 +2539,7 @@
&msm_pil_vidc,
&msm_gss,
&apq8064_rtb_device,
+ &apq8064_dcvs_device,
&apq8064_msm_gov_device,
&apq8064_device_cache_erp,
&msm8960_device_ebi1_ch0_erp,
@@ -2703,7 +2719,7 @@
};
static struct msm_spi_platform_data mpq8064_qup_spi_gsbi6_pdata = {
- .max_clock_speed = 1100000,
+ .max_clock_speed = 10800000,
};
static struct ci_bridge_platform_data mpq8064_ci_bridge_pdata = {
@@ -3379,6 +3395,7 @@
static void __init apq8064_common_init(void)
{
u32 platform_version = socinfo_get_platform_version();
+ struct msm_rpmrs_level rpmrs_level;
if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
apq8064_pm8917_pdata_fixup();
@@ -3455,8 +3472,12 @@
}
enable_ddr3_regulator();
- msm_hsic_pdata.swfi_latency =
- msm_rpmrs_levels[0].latency_us;
+ rpmrs_level =
+ msm_rpmrs_levels[MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT];
+ msm_hsic_pdata.swfi_latency = rpmrs_level.latency_us;
+ rpmrs_level =
+ msm_rpmrs_levels[MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE];
+ msm_hsic_pdata.standalone_latency = rpmrs_level.latency_us;
if (machine_is_apq8064_mtp()) {
msm_hsic_pdata.log2_irq_thresh = 5,
apq8064_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
@@ -3487,6 +3508,8 @@
apq8064_init_dsps();
platform_device_register(&msm_8960_riva);
}
+ if (cpu_is_apq8064ab())
+ apq8064ab_update_krait_spm();
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
diff --git a/arch/arm/mach-msm/board-8226.c b/arch/arm/mach-msm/board-8226.c
index 33f18a2..e5263c7 100644
--- a/arch/arm/mach-msm/board-8226.c
+++ b/arch/arm/mach-msm/board-8226.c
@@ -43,6 +43,21 @@
#include "board-dt.h"
#include "clock.h"
+static struct memtype_reserve msm8226_reserve_table[] __initdata = {
+ [MEMTYPE_SMI] = {
+ },
+ [MEMTYPE_EBI0] = {
+ .flags = MEMTYPE_FLAGS_1M_ALIGN,
+ },
+ [MEMTYPE_EBI1] = {
+ .flags = MEMTYPE_FLAGS_1M_ALIGN,
+ },
+};
+
+static int msm8226_paddr_to_memtype(unsigned int paddr)
+{
+ return MEMTYPE_EBI1;
+}
static struct clk_lookup msm_clocks_dummy[] = {
CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
@@ -50,11 +65,28 @@
CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
};
-struct clock_init_data msm_dummy_clock_init_data __initdata = {
+static struct clock_init_data msm_dummy_clock_init_data __initdata = {
.table = msm_clocks_dummy,
.size = ARRAY_SIZE(msm_clocks_dummy),
};
+static struct reserve_info msm8226_reserve_info __initdata = {
+ .memtype_reserve_table = msm8226_reserve_table,
+ .paddr_to_memtype = msm8226_paddr_to_memtype,
+};
+
+static void __init msm8226_early_memory(void)
+{
+ reserve_info = &msm8226_reserve_info;
+ of_scan_flat_dt(dt_scan_for_memory_reserve, msm8226_reserve_table);
+}
+
+static void __init msm8226_reserve(void)
+{
+ msm_reserve();
+}
+
+
void __init msm8226_init(void)
{
msm8226_init_gpiomux();
@@ -66,7 +98,6 @@
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
-
static const char *msm8226_dt_match[] __initconst = {
"qcom,msm8226",
NULL
@@ -79,4 +110,6 @@
.handle_irq = gic_handle_irq,
.timer = &msm_dt_timer,
.dt_compat = msm8226_dt_match,
+ .reserve = msm8226_reserve,
+ .init_very_early = msm8226_early_memory
MACHINE_END
diff --git a/arch/arm/mach-msm/board-8910-gpiomux.c b/arch/arm/mach-msm/board-8910-gpiomux.c
new file mode 100644
index 0000000..a67f916
--- /dev/null
+++ b/arch/arm/mach-msm/board-8910-gpiomux.c
@@ -0,0 +1,29 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/gpiomux.h>
+
+void __init msm8910_init_gpiomux(void)
+{
+ int rc;
+
+ rc = msm_gpiomux_init(NR_GPIO_IRQS);
+ if (rc) {
+ pr_err(KERN_ERR "msm_8910_init_gpiomux failed %d\n", rc);
+ return;
+ }
+}
diff --git a/arch/arm/mach-msm/board-8910.c b/arch/arm/mach-msm/board-8910.c
index eaf146b..b031dac 100644
--- a/arch/arm/mach-msm/board-8910.c
+++ b/arch/arm/mach-msm/board-8910.c
@@ -31,6 +31,7 @@
#include <mach/board.h>
#include <mach/gpiomux.h>
#include <mach/msm_iomap.h>
+#include <mach/restart.h>
#ifdef CONFIG_ION_MSM
#include <mach/ion.h>
#endif
@@ -45,27 +46,38 @@
CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
- CLK_DUMMY("iface_clk", NULL, "f9824000.qcom,sdcc", OFF),
- CLK_DUMMY("core_clk", NULL, "f9824000.qcom,sdcc", OFF),
- CLK_DUMMY("bus_clk", NULL, "f9824000.qcom,sdcc", OFF),
- CLK_DUMMY("iface_clk", NULL, "f98a4000.qcom,sdcc", OFF),
- CLK_DUMMY("core_clk", NULL, "f98a4000.qcom,sdcc", OFF),
- CLK_DUMMY("bus_clk", NULL, "f98a4000.qcom,sdcc", OFF),
+ CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
+ CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
+ CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
+ CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
+ CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
+ CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
};
-struct clock_init_data msm_dummy_clock_init_data __initdata = {
+static struct clock_init_data msm_dummy_clock_init_data __initdata = {
.table = msm_clocks_dummy,
.size = ARRAY_SIZE(msm_clocks_dummy),
};
+static struct of_dev_auxdata msm8910_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF9824000, \
+ "msm_sdcc.1", NULL),
+ OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF98A4000, \
+ "msm_sdcc.2", NULL),
+ {}
+};
+
void __init msm8910_init(void)
{
+ struct of_dev_auxdata *adata = msm8910_auxdata_lookup;
+
+ msm8910_init_gpiomux();
msm_clock_init(&msm_dummy_clock_init_data);
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed\n", __func__);
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, adata, NULL);
}
static const char *msm8910_dt_match[] __initconst = {
@@ -80,4 +92,5 @@
.handle_irq = gic_handle_irq,
.timer = &msm_dt_timer,
.dt_compat = msm8910_dt_match,
+ .restart = msm_restart,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-8930-camera.c b/arch/arm/mach-msm/board-8930-camera.c
index eb00f34..be55031 100644
--- a/arch/arm/mach-msm/board-8930-camera.c
+++ b/arch/arm/mach-msm/board-8930-camera.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -188,6 +188,17 @@
#define VFE_CAMIF_TIMER1_GPIO 2
#define VFE_CAMIF_TIMER2_GPIO 3
#define VFE_CAMIF_TIMER3_GPIO_INT 4
+
+static struct gpio flash_init_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER1"},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER2"},
+};
+
+static struct msm_gpio_set_tbl flash_set_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+};
+
static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
.flash_trigger = VFE_CAMIF_TIMER2_GPIO,
.flash_charge = VFE_CAMIF_TIMER1_GPIO,
@@ -196,14 +207,16 @@
.irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
};
-#ifdef CONFIG_MSM_CAMERA_FLASH
static struct msm_camera_sensor_flash_src msm_flash_src = {
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
+ .init_gpio_tbl = flash_init_gpio,
+ .init_gpio_tbl_size = ARRAY_SIZE(flash_init_gpio),
+ .set_gpio_tbl = flash_set_gpio,
+ .set_gpio_tbl_size = ARRAY_SIZE(flash_set_gpio),
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_TPS61310,
};
-#endif
static struct msm_bus_vectors cam_init_vectors[] = {
{
@@ -231,7 +244,7 @@
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 27648000,
- .ib = 110592000,
+ .ib = 2656000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -252,7 +265,7 @@
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 274406400,
- .ib = 561807360,
+ .ib = 2656000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -272,8 +285,8 @@
{
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 274423680,
- .ib = 1097694720,
+ .ab = 600000000,
+ .ib = 2656000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -293,8 +306,8 @@
{
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 302071680,
- .ib = 1208286720,
+ .ab = 600000000,
+ .ib = 2656000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -314,8 +327,8 @@
{
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 348192000,
- .ib = 617103360,
+ .ab = 600000000,
+ .ib = 4264000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -336,7 +349,7 @@
.src = MSM_BUS_MASTER_VFE,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 302071680,
- .ib = 1208286720,
+ .ib = 2656000000UL,
},
{
.src = MSM_BUS_MASTER_VPE,
@@ -352,6 +365,27 @@
},
};
+static struct msm_bus_vectors cam_adv_video_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_VFE,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 274406400,
+ .ib = 2656000000UL,
+ },
+ {
+ .src = MSM_BUS_MASTER_VPE,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 206807040,
+ .ib = 488816640,
+ },
+ {
+ .src = MSM_BUS_MASTER_JPEG_ENC,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
static struct msm_bus_paths cam_bus_client_config[] = {
{
@@ -382,6 +416,11 @@
ARRAY_SIZE(cam_dual_vectors),
cam_dual_vectors,
},
+ {
+ ARRAY_SIZE(cam_adv_video_vectors),
+ cam_adv_video_vectors,
+ },
+
};
static struct msm_bus_scale_pdata cam_bus_client_pdata = {
@@ -476,9 +515,7 @@
static struct msm_camera_sensor_flash_data flash_imx074 = {
.flash_type = MSM_CAMERA_FLASH_LED,
-#ifdef CONFIG_MSM_CAMERA_FLASH
.flash_src = &msm_flash_src
-#endif
};
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
@@ -560,9 +597,15 @@
.sensor_type = BAYER_SENSOR,
};
+static struct i2c_board_info tps61310_flash_i2c_info = {
+ I2C_BOARD_INFO("tps61310", 0x66),
+};
+
static struct msm_camera_sensor_flash_data flash_s5k3l1yx = {
.flash_type = MSM_CAMERA_FLASH_LED,
- .flash_src = &msm_flash_src
+ .flash_src = &msm_flash_src,
+ .board_info = &tps61310_flash_i2c_info,
+ .bus_id = MSM_8930_GSBI4_QUP_I2C_BUS_ID,
};
static struct msm_camera_csi_lane_params s5k3l1yx_csi_lane_params = {
@@ -650,9 +693,6 @@
I2C_BOARD_INFO("s5k3l1yx", 0x20),
.platform_data = &msm_camera_sensor_s5k3l1yx_data,
},
- {
- I2C_BOARD_INFO("tps61310", 0x66),
- },
};
struct msm_camera_board_info msm8930_camera_board_info = {
diff --git a/arch/arm/mach-msm/board-8930-display.c b/arch/arm/mach-msm/board-8930-display.c
index a0bfabf..7e477b1 100644
--- a/arch/arm/mach-msm/board-8930-display.c
+++ b/arch/arm/mach-msm/board-8930-display.c
@@ -740,11 +740,29 @@
return 0;
if (on) {
+ if (!(hdmi_msm_data.is_mhl_enabled)) {
+ rc = gpio_request(HDMI_MHL_MUX_GPIO, "MHL_HDMI_MUX");
+ if (rc < 0) {
+ pr_err("gpio hdmi_mhl mux req failed:%d\n",
+ rc);
+ return rc;
+ }
+ rc = gpio_direction_output(HDMI_MHL_MUX_GPIO, 1);
+ if (rc < 0) {
+ pr_err("set gpio hdmi_mhl dir failed:%d\n",
+ rc);
+ goto error0;
+ }
+ gpio_set_value(HDMI_MHL_MUX_GPIO, 1);
+ pr_debug("set gpio hdmi mhl mux %d to 1\n",
+ HDMI_MHL_MUX_GPIO);
+ }
+
rc = gpio_request(100, "HDMI_DDC_CLK");
if (rc) {
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
"HDMI_DDC_CLK", 100, rc);
- return rc;
+ goto error0;
}
rc = gpio_request(101, "HDMI_DDC_DATA");
if (rc) {
@@ -760,6 +778,8 @@
}
pr_debug("%s(on): success\n", __func__);
} else {
+ if (!(hdmi_msm_data.is_mhl_enabled))
+ gpio_free(HDMI_MHL_MUX_GPIO);
gpio_free(100);
gpio_free(101);
gpio_free(102);
@@ -773,6 +793,9 @@
gpio_free(101);
error1:
gpio_free(100);
+error0:
+ if (!(hdmi_msm_data.is_mhl_enabled))
+ gpio_free(HDMI_MHL_MUX_GPIO);
return rc;
}
diff --git a/arch/arm/mach-msm/board-8930-pmic.c b/arch/arm/mach-msm/board-8930-pmic.c
index 0c7666b..618f83b 100644
--- a/arch/arm/mach-msm/board-8930-pmic.c
+++ b/arch/arm/mach-msm/board-8930-pmic.c
@@ -315,7 +315,6 @@
#define MAX_VOLTAGE_MV 4200
#define CHG_TERM_MA 100
static struct pm8921_charger_platform_data pm8921_chg_pdata __devinitdata = {
- .safety_time = 180,
.update_time = 60000,
.max_voltage = MAX_VOLTAGE_MV,
.min_voltage = 3200,
@@ -438,7 +437,7 @@
};
static struct pm8xxx_ccadc_platform_data pm8xxx_ccadc_pdata = {
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.calib_delay_ms = 600000,
};
@@ -466,7 +465,7 @@
static struct pm8921_bms_platform_data pm8921_bms_pdata __devinitdata = {
.battery_type = BATT_UNKNOWN,
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.v_cutoff = 3400,
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
.shutdown_soc_valid_limit = 20,
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8038.c b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
index 727c4c6..eaebea0 100644
--- a/arch/arm/mach-msm/board-8930-regulator-pm8038.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
@@ -189,12 +189,14 @@
REGULATOR_SUPPLY("krait0", "acpuclk-8627"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait0", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S6) = {
REGULATOR_SUPPLY("8038_s6", NULL),
REGULATOR_SUPPLY("krait1", "acpuclk-8627"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait1", "acpuclk-8930ab"),
};
VREG_CONSUMERS(LVS1) = {
REGULATOR_SUPPLY("8038_lvs1", NULL),
@@ -447,7 +449,8 @@
{ \
.constraints = { \
.name = _name, \
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
+ REGULATOR_CHANGE_STATUS, \
.min_uV = _min_uV, \
.max_uV = _max_uV, \
}, \
@@ -490,7 +493,7 @@
/* ID a_on pd ss min_uV max_uV supply sys_uA freq fm ss_fm */
RPM_SMPS(S1, 0, 1, 1, 500000, 1150000, NULL, 100000, 4p80, AUTO, LPM),
RPM_SMPS(S2, 1, 1, 1, 1400000, 1400000, NULL, 100000, 1p60, AUTO, LPM),
- RPM_SMPS(S3, 0, 1, 1, 1150000, 1150000, NULL, 100000, 3p20, AUTO, LPM),
+ RPM_SMPS(S3, 0, 1, 1, 1150000, 1150000, NULL, 100000, 3p20, AUTO, AUTO),
RPM_SMPS(S4, 1, 1, 1, 1950000, 2200000, NULL, 100000, 1p60, AUTO, LPM),
/* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
@@ -564,6 +567,14 @@
RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930aa"),
+
+ RPM_REG_MAP(L23, 0, 1, "krait0_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 2, "krait1_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 6, "l2_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 1, "krait0_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930ab"),
};
struct rpm_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8917.c b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
index 33e38ab..9a2967a 100644
--- a/arch/arm/mach-msm/board-8930-regulator-pm8917.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
@@ -34,6 +34,7 @@
REGULATOR_SUPPLY("8917_l2", NULL),
REGULATOR_SUPPLY("iris_vdddig", "wcnss_wlan.0"),
REGULATOR_SUPPLY("dsi_vdda", "mipi_dsi.1"),
+ REGULATOR_SUPPLY("dsi_pll_vdda", "mdp.0"),
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.0"),
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.1"),
REGULATOR_SUPPLY("mipi_csi_vdd", "msm_csid.2"),
@@ -117,6 +118,7 @@
VREG_CONSUMERS(L23) = {
REGULATOR_SUPPLY("8917_l23", NULL),
REGULATOR_SUPPLY("dsi_vddio", "mipi_dsi.1"),
+ REGULATOR_SUPPLY("dsi_pll_vddio", "mdp.0"),
REGULATOR_SUPPLY("hdmi_avdd", "hdmi_msm.0"),
REGULATOR_SUPPLY("hdmi_vcc", "hdmi_msm.0"),
REGULATOR_SUPPLY("pll_vdd", "pil_riva"),
@@ -204,12 +206,14 @@
REGULATOR_SUPPLY("krait0", "acpuclk-8627"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait0", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S6) = {
REGULATOR_SUPPLY("8917_s6", NULL),
REGULATOR_SUPPLY("krait1", "acpuclk-8627"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait1", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S7) = {
REGULATOR_SUPPLY("8917_s7", NULL),
@@ -483,7 +487,8 @@
{ \
.constraints = { \
.name = _name, \
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
+ REGULATOR_CHANGE_STATUS, \
.min_uV = _min_uV, \
.max_uV = _max_uV, \
}, \
@@ -629,6 +634,18 @@
RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930aa"),
+
+ RPM_REG_MAP(L23, 0, 1, "krait0_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 1, "krait0_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 2, "krait1_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 2, "krait1_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 6, "l2_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 6, "l2_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 1, "krait0_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930ab"),
+
};
struct rpm_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 05d2fe1..512ae72 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -112,7 +112,6 @@
#define KS8851_IRQ_GPIO 90
#define HAP_SHIFT_LVL_OE_GPIO 47
-#define HDMI_MHL_MUX_GPIO 73
#define MHL_GPIO_INT 72
#define MHL_GPIO_RESET 71
#define MHL_GPIO_PWR_EN 5
@@ -133,7 +132,7 @@
#endif
#define MSM_PMEM_ADSP_SIZE 0x7800000
-#define MSM_PMEM_AUDIO_SIZE 0x4CF000
+#define MSM_PMEM_AUDIO_SIZE 0x314000
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
#else
@@ -762,7 +761,7 @@
.regulator = {
{
.name = "CDC_VDD_CP",
- .min_uV = 1800000,
+ .min_uV = 2200000,
.max_uV = 2200000,
.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
},
@@ -828,7 +827,7 @@
.regulator = {
{
.name = "CDC_VDD_CP",
- .min_uV = 1800000,
+ .min_uV = 2200000,
.max_uV = 2200000,
.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
},
@@ -2295,7 +2294,6 @@
static struct platform_device *common_devices[] __initdata = {
&msm_8960_q6_lpass,
- &msm_8960_q6_mss,
&msm_8960_riva,
&msm_pil_tzapps,
&msm_pil_vidc,
@@ -2714,11 +2712,34 @@
#endif
}
+/*Modify the WCD9xxx platform data to support supplies from PM8917 */
+static void __init msm8930_pm8917_wcd9xxx_pdata_fixup(
+ struct wcd9xxx_pdata *cdc_pdata)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cdc_pdata->regulator); i++) {
+
+ if (cdc_pdata->regulator[i].name != NULL
+ && strncmp(cdc_pdata->regulator[i].name,
+ "CDC_VDD_CP", 10) == 0) {
+ cdc_pdata->regulator[i].min_uV =
+ cdc_pdata->regulator[i].max_uV = 1800000;
+ pr_info("%s: CDC_VDD_CP forced to 1.8 volts for PM8917\n",
+ __func__);
+ return;
+ }
+ }
+}
+
/* Modify platform data values to match requirements for PM8917. */
static void __init msm8930_pm8917_pdata_fixup(void)
{
struct acpuclk_platform_data *pdata;
+ msm8930_pm8917_wcd9xxx_pdata_fixup(&sitar_platform_data);
+ msm8930_pm8917_wcd9xxx_pdata_fixup(&sitar1p1_platform_data);
+
mhl_platform_data.gpio_mhl_power = MHL_POWER_GPIO_PM8917;
gpio_keys_8930_pdata.buttons = keys_8930_pm8917;
@@ -2734,6 +2755,9 @@
pdata = msm8930_device_acpuclk.dev.platform_data;
pdata->uses_pm8917 = true;
+
+ pdata = msm8930ab_device_acpuclk.dev.platform_data;
+ pdata->uses_pm8917 = true;
}
static void __init msm8930_cdp_init(void)
@@ -2790,18 +2814,25 @@
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
msm8930_init_buses();
- if (cpu_is_msm8627())
+ if (cpu_is_msm8627()) {
platform_add_devices(msm8627_footswitch,
msm8627_num_footswitch);
- else
- platform_add_devices(msm8930_footswitch,
- msm8930_num_footswitch);
+ } else {
+ if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
+ platform_add_devices(msm8930_pm8917_footswitch,
+ msm8930_pm8917_num_footswitch);
+ else
+ platform_add_devices(msm8930_footswitch,
+ msm8930_num_footswitch);
+ }
if (cpu_is_msm8627())
platform_device_register(&msm8627_device_acpuclk);
else if (cpu_is_msm8930())
platform_device_register(&msm8930_device_acpuclk);
else if (cpu_is_msm8930aa())
platform_device_register(&msm8930aa_device_acpuclk);
+ else if (cpu_is_msm8930ab())
+ platform_device_register(&msm8930ab_device_acpuclk);
platform_add_devices(early_common_devices,
ARRAY_SIZE(early_common_devices));
if (socinfo_get_pmic_model() != PMIC_MODEL_PM8917)
@@ -2825,6 +2856,10 @@
else
msm8930_pm8917_gpio_mpp_init();
#endif
+ /* Don't add modem devices on APQ targets */
+ if (socinfo_get_id() != 119 && socinfo_get_id() != 157
+ && socinfo_get_id() != 160)
+ platform_device_register(&msm_8960_q6_mss);
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
#ifdef CONFIG_MSM_CAMERA
msm8930_init_cam();
diff --git a/arch/arm/mach-msm/board-8930.h b/arch/arm/mach-msm/board-8930.h
index 055576f..dbcfa9d 100644
--- a/arch/arm/mach-msm/board-8930.h
+++ b/arch/arm/mach-msm/board-8930.h
@@ -164,5 +164,7 @@
#define MSM_8930_GSBI10_QUP_I2C_BUS_ID 10
#define MSM_8930_GSBI12_QUP_I2C_BUS_ID 12
+#define HDMI_MHL_MUX_GPIO 73
+
extern struct msm_rtb_platform_data msm8930_rtb_pdata;
extern struct msm_cache_dump_platform_data msm8930_cache_dump_pdata;
diff --git a/arch/arm/mach-msm/board-8960-camera.c b/arch/arm/mach-msm/board-8960-camera.c
index 88fd527..7a2e9e1 100644
--- a/arch/arm/mach-msm/board-8960-camera.c
+++ b/arch/arm/mach-msm/board-8960-camera.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -185,6 +185,17 @@
#define VFE_CAMIF_TIMER1_GPIO 2
#define VFE_CAMIF_TIMER2_GPIO 3
#define VFE_CAMIF_TIMER3_GPIO_INT 4
+
+static struct gpio flash_init_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER1"},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_LOW, "CAMIF_TIMER2"},
+};
+
+static struct msm_gpio_set_tbl flash_set_gpio[] = {
+ {VFE_CAMIF_TIMER1_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+ {VFE_CAMIF_TIMER2_GPIO, GPIOF_OUT_INIT_HIGH, 2000},
+};
+
static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
.flash_trigger = VFE_CAMIF_TIMER2_GPIO,
.flash_charge = VFE_CAMIF_TIMER1_GPIO,
@@ -193,14 +204,16 @@
.irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
};
-#ifdef CONFIG_MSM_CAMERA_FLASH
static struct msm_camera_sensor_flash_src msm_flash_src = {
.flash_sr_type = MSM_CAMERA_FLASH_SRC_EXT,
+ .init_gpio_tbl = flash_init_gpio,
+ .init_gpio_tbl_size = ARRAY_SIZE(flash_init_gpio),
+ .set_gpio_tbl = flash_set_gpio,
+ .set_gpio_tbl_size = ARRAY_SIZE(flash_set_gpio),
._fsrc.ext_driver_src.led_en = VFE_CAMIF_TIMER1_GPIO,
._fsrc.ext_driver_src.led_flash_en = VFE_CAMIF_TIMER2_GPIO,
._fsrc.ext_driver_src.flash_id = MAM_CAMERA_EXT_LED_FLASH_SC628A,
};
-#endif
static struct msm_bus_vectors cam_init_vectors[] = {
{
@@ -570,11 +583,15 @@
.vcm_enable = 0,
};
+static struct i2c_board_info sc628a_flash_i2c_info = {
+ I2C_BOARD_INFO("sc628a", 0x6E),
+};
+
static struct msm_camera_sensor_flash_data flash_imx074 = {
.flash_type = MSM_CAMERA_FLASH_LED,
-#ifdef CONFIG_MSM_CAMERA_FLASH
- .flash_src = &msm_flash_src
-#endif
+ .flash_src = &msm_flash_src,
+ .board_info = &sc628a_flash_i2c_info,
+ .bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
};
static struct msm_camera_csi_lane_params imx074_csi_lane_params = {
@@ -715,9 +732,9 @@
static struct msm_camera_sensor_flash_data flash_imx091 = {
.flash_type = MSM_CAMERA_FLASH_LED,
-#ifdef CONFIG_MSM_CAMERA_FLASH
- .flash_src = &msm_flash_src
-#endif
+ .flash_src = &msm_flash_src,
+ .board_info = &sc628a_flash_i2c_info,
+ .bus_id = MSM_8960_GSBI4_QUP_I2C_BUS_ID,
};
static struct msm_camera_sensor_platform_info sensor_board_info_imx091 = {
@@ -876,11 +893,6 @@
I2C_BOARD_INFO("s5k3l1yx", 0x20),
.platform_data = &msm_camera_sensor_s5k3l1yx_data,
},
-#ifdef CONFIG_MSM_CAMERA_FLASH_SC628A
- {
- I2C_BOARD_INFO("sc628a", 0x6E),
- },
-#endif
{
I2C_BOARD_INFO("imx091", 0x34),
.platform_data = &msm_camera_sensor_imx091_data,
diff --git a/arch/arm/mach-msm/board-8960-pmic.c b/arch/arm/mach-msm/board-8960-pmic.c
index 9efedb1..2071a55 100644
--- a/arch/arm/mach-msm/board-8960-pmic.c
+++ b/arch/arm/mach-msm/board-8960-pmic.c
@@ -396,7 +396,6 @@
#define MAX_VOLTAGE_MV 4200
#define CHG_TERM_MA 100
static struct pm8921_charger_platform_data pm8921_chg_pdata __devinitdata = {
- .safety_time = 180,
.update_time = 60000,
.max_voltage = MAX_VOLTAGE_MV,
.min_voltage = 3200,
@@ -425,7 +424,7 @@
static struct pm8921_bms_platform_data pm8921_bms_pdata __devinitdata = {
.battery_type = BATT_UNKNOWN,
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.v_cutoff = 3400,
.max_voltage_uv = MAX_VOLTAGE_MV * 1000,
.rconn_mohm = 18,
@@ -553,7 +552,7 @@
};
static struct pm8xxx_ccadc_platform_data pm8xxx_ccadc_pdata = {
- .r_sense = 10,
+ .r_sense_uohm = 10000,
.calib_delay_ms = 600000,
};
diff --git a/arch/arm/mach-msm/board-8960-regulator.c b/arch/arm/mach-msm/board-8960-regulator.c
index f9e2c8e..397411d 100644
--- a/arch/arm/mach-msm/board-8960-regulator.c
+++ b/arch/arm/mach-msm/board-8960-regulator.c
@@ -382,7 +382,8 @@
{ \
.constraints = { \
.name = _name, \
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, \
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
+ REGULATOR_CHANGE_STATUS, \
.min_uV = _min_uV, \
.max_uV = _max_uV, \
}, \
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index ce2531b..9efc60a 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -1593,26 +1593,41 @@
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
- 0x03, 0x0f,
+ 0x03, 0x0f,
};
static uint8_t spm_retention_cmd_sequence[] __initdata = {
- 0x00, 0x05, 0x03, 0x0D,
- 0x0B, 0x00, 0x0f,
+ 0x00, 0x05, 0x03, 0x0D,
+ 0x0B, 0x00, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
- 0x00, 0x24, 0x54, 0x10,
- 0x09, 0x03, 0x01,
- 0x10, 0x54, 0x30, 0x0C,
- 0x24, 0x30, 0x0f,
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x03, 0x01,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
- 0x00, 0x24, 0x54, 0x10,
- 0x09, 0x07, 0x01, 0x0B,
- 0x10, 0x54, 0x30, 0x0C,
- 0x24, 0x30, 0x0f,
+ 0x00, 0x24, 0x54, 0x10,
+ 0x09, 0x07, 0x01, 0x0B,
+ 0x10, 0x54, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
+/* 8960AB has a different command to assert apc_pdn */
+static uint8_t spm_power_collapse_without_rpm_krait_v3[] __initdata = {
+ 0x00, 0x24, 0x84, 0x10,
+ 0x09, 0x03, 0x01,
+ 0x10, 0x84, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
+};
+
+static uint8_t spm_power_collapse_with_rpm_krait_v3[] __initdata = {
+ 0x00, 0x24, 0x84, 0x10,
+ 0x09, 0x07, 0x01, 0x0B,
+ 0x10, 0x84, 0x30, 0x0C,
+ 0x24, 0x30, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_boot_cpu_seq_list[] __initdata = {
@@ -1621,13 +1636,11 @@
.notify_rpm = false,
.cmd = spm_wfi_cmd_sequence,
},
-
[1] = {
.mode = MSM_SPM_MODE_POWER_RETENTION,
.notify_rpm = false,
.cmd = spm_retention_cmd_sequence,
},
-
[2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
@@ -2875,8 +2888,8 @@
/* Fixup data that needs to change based on GPU ID */
if (cpu_is_msm8960ab()) {
kgsl_3d0_pdata->chipid = ADRENO_CHIPID(3, 2, 1, 0);
- /* 8960PRO nominal clock rate is 325Mhz instead of 320Mhz */
- kgsl_3d0_pdata->pwrlevel[1].gpu_freq = 325000000;
+ /* 8960PRO nominal clock rate is 320Mhz */
+ kgsl_3d0_pdata->pwrlevel[1].gpu_freq = 320000000;
} else {
kgsl_3d0_pdata->iommu_count = 1;
if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1) {
@@ -3216,15 +3229,32 @@
msm_tsens_early_init(&msm_tsens_pdata);
}
-static void __init msm8960_reset_spm_avs(void)
+static void __init msm8960ab_update_krait_spm(void)
{
int i;
+ /* Reset the AVS registers until we have support for AVS */
for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
struct msm_spm_platform_data *pdata = &msm_spm_data[i];
pdata->reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0;
pdata->reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0;
}
+
+ /* Update the SPM sequences for SPC and PC */
+ for (i = 0; i < ARRAY_SIZE(msm_spm_data); i++) {
+ int j;
+ struct msm_spm_platform_data *pdata = &msm_spm_data[i];
+ for (j = 0; j < pdata->num_modes; j++) {
+ if (pdata->modes[j].cmd ==
+ spm_power_collapse_without_rpm)
+ pdata->modes[j].cmd =
+ spm_power_collapse_without_rpm_krait_v3;
+ else if (pdata->modes[j].cmd ==
+ spm_power_collapse_with_rpm)
+ pdata->modes[j].cmd =
+ spm_power_collapse_with_rpm_krait_v3;
+ }
+ }
}
static void __init msm8960_cdp_init(void)
@@ -3282,7 +3312,7 @@
msm8960_gfx_init();
if (cpu_is_msm8960ab())
- msm8960_reset_spm_avs();
+ msm8960ab_update_krait_spm();
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
diff --git a/arch/arm/mach-msm/board-8974-gpiomux.c b/arch/arm/mach-msm/board-8974-gpiomux.c
index 50b59e1..89ad4ef 100644
--- a/arch/arm/mach-msm/board-8974-gpiomux.c
+++ b/arch/arm/mach-msm/board-8974-gpiomux.c
@@ -152,6 +152,26 @@
};
+static struct gpiomux_setting mhl_suspend_config = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting mhl_active_1_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+ .dir = GPIOMUX_OUT_HIGH,
+};
+
+static struct gpiomux_setting mhl_active_2_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+
static struct gpiomux_setting hdmi_suspend_cfg = {
.func = GPIOMUX_FUNC_GPIO,
.drv = GPIOMUX_DRV_2MA,
@@ -170,6 +190,34 @@
.pull = GPIOMUX_PULL_DOWN,
};
+static struct msm_gpiomux_config msm_mhl_configs[] __initdata = {
+ {
+ /* mhl-sii8334 pwr */
+ .gpio = 12,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_1_cfg,
+ },
+ },
+ {
+ /* mhl-sii8334 intr */
+ .gpio = 82,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_1_cfg,
+ },
+ },
+ {
+ /* mhl-sii8334 reset */
+ .gpio = 8,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_2_cfg,
+ },
+ },
+};
+
+
static struct msm_gpiomux_config msm_hdmi_configs[] __initdata = {
{
.gpio = 31,
@@ -575,4 +623,5 @@
msm_gpiomux_install(msm_taiko_config, ARRAY_SIZE(msm_taiko_config));
msm_gpiomux_install(msm_hdmi_configs, ARRAY_SIZE(msm_hdmi_configs));
+ msm_gpiomux_install(msm_mhl_configs, ARRAY_SIZE(msm_mhl_configs));
}
diff --git a/arch/arm/mach-msm/board-8974.c b/arch/arm/mach-msm/board-8974.c
index 19fb222..b092a53 100644
--- a/arch/arm/mach-msm/board-8974.c
+++ b/arch/arm/mach-msm/board-8974.c
@@ -49,17 +49,6 @@
#include "modem_notifier.h"
#include "lpm_resources.h"
-#define MSM_KERNEL_EBI1_MEM_SIZE 0x280000
-
-#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
-static unsigned kernel_ebi1_mem_size = MSM_KERNEL_EBI1_MEM_SIZE;
-static int __init kernel_ebi1_mem_size_setup(char *p)
-{
- kernel_ebi1_mem_size = memparse(p, NULL);
- return 0;
-}
-early_param("kernel_ebi1_mem_size", kernel_ebi1_mem_size_setup);
-#endif
static struct memtype_reserve msm8974_reserve_table[] __initdata = {
[MEMTYPE_SMI] = {
@@ -77,183 +66,8 @@
return MEMTYPE_EBI1;
}
-static void __init reserve_ebi_memory(void)
-{
-#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
- msm8974_reserve_table[MEMTYPE_EBI1].size += kernel_ebi1_mem_size;
-#endif
-}
-
-static struct resource smd_resource[] = {
- {
- .name = "modem_smd_in",
- .start = 32 + 25, /* mss_sw_to_kpss_ipc_irq0 */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "modem_smsm_in",
- .start = 32 + 26, /* mss_sw_to_kpss_ipc_irq1 */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "adsp_smd_in",
- .start = 32 + 156, /* lpass_to_kpss_ipc_irq0 */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "adsp_smsm_in",
- .start = 32 + 157, /* lpass_to_kpss_ipc_irq1 */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "wcnss_smd_in",
- .start = 32 + 142, /* WcnssAppsSmdMedIrq */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "wcnss_smsm_in",
- .start = 32 + 144, /* RivaAppsWlanSmsmIrq */
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "rpm_smd_in",
- .start = 32 + 168, /* rpm_to_kpss_ipc_irq4 */
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct smd_subsystem_config smd_config_list[] = {
- {
- .irq_config_id = SMD_MODEM,
- .subsys_name = "modem",
- .edge = SMD_APPS_MODEM,
-
- .smd_int.irq_name = "modem_smd_in",
- .smd_int.flags = IRQF_TRIGGER_RISING,
- .smd_int.irq_id = -1,
- .smd_int.device_name = "smd_dev",
- .smd_int.dev_id = 0,
- .smd_int.out_bit_pos = 1 << 12,
- .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smd_int.out_offset = 0x8,
-
- .smsm_int.irq_name = "modem_smsm_in",
- .smsm_int.flags = IRQF_TRIGGER_RISING,
- .smsm_int.irq_id = -1,
- .smsm_int.device_name = "smsm_dev",
- .smsm_int.dev_id = 0,
- .smsm_int.out_bit_pos = 1 << 13,
- .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smsm_int.out_offset = 0x8,
- },
- {
- .irq_config_id = SMD_Q6,
- .subsys_name = "adsp",
- .edge = SMD_APPS_QDSP,
-
- .smd_int.irq_name = "adsp_smd_in",
- .smd_int.flags = IRQF_TRIGGER_RISING,
- .smd_int.irq_id = -1,
- .smd_int.device_name = "smd_dev",
- .smd_int.dev_id = 0,
- .smd_int.out_bit_pos = 1 << 8,
- .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smd_int.out_offset = 0x8,
-
- .smsm_int.irq_name = "adsp_smsm_in",
- .smsm_int.flags = IRQF_TRIGGER_RISING,
- .smsm_int.irq_id = -1,
- .smsm_int.device_name = "smsm_dev",
- .smsm_int.dev_id = 0,
- .smsm_int.out_bit_pos = 1 << 9,
- .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smsm_int.out_offset = 0x8,
- },
- {
- .irq_config_id = SMD_WCNSS,
- .subsys_name = "wcnss",
- .edge = SMD_APPS_WCNSS,
-
- .smd_int.irq_name = "wcnss_smd_in",
- .smd_int.flags = IRQF_TRIGGER_RISING,
- .smd_int.irq_id = -1,
- .smd_int.device_name = "smd_dev",
- .smd_int.dev_id = 0,
- .smd_int.out_bit_pos = 1 << 17,
- .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smd_int.out_offset = 0x8,
-
- .smsm_int.irq_name = "wcnss_smsm_in",
- .smsm_int.flags = IRQF_TRIGGER_RISING,
- .smsm_int.irq_id = -1,
- .smsm_int.device_name = "smsm_dev",
- .smsm_int.dev_id = 0,
- .smsm_int.out_bit_pos = 1 << 19,
- .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smsm_int.out_offset = 0x8,
- },
- {
- .irq_config_id = SMD_RPM,
- .subsys_name = NULL, /* do not use PIL to load RPM */
- .edge = SMD_APPS_RPM,
-
- .smd_int.irq_name = "rpm_smd_in",
- .smd_int.flags = IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
- .smd_int.irq_id = -1,
- .smd_int.device_name = "smd_dev",
- .smd_int.dev_id = 0,
- .smd_int.out_bit_pos = 1 << 0,
- .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
- .smd_int.out_offset = 0x8,
-
- .smsm_int.irq_name = NULL, /* RPM does not support SMSM */
- .smsm_int.flags = 0,
- .smsm_int.irq_id = 0,
- .smsm_int.device_name = NULL,
- .smsm_int.dev_id = 0,
- .smsm_int.out_bit_pos = 0,
- .smsm_int.out_base = NULL,
- .smsm_int.out_offset = 0,
- },
-};
-
-static struct smd_smem_regions aux_smem_areas[] = {
- {
- .phys_addr = (void *)(0xfc428000),
- .size = 0x4000,
- },
-};
-
-static struct smd_subsystem_restart_config smd_ssr_cfg = {
- .disable_smsm_reset_handshake = 1,
-};
-
-static struct smd_platform smd_platform_data = {
- .num_ss_configs = ARRAY_SIZE(smd_config_list),
- .smd_ss_configs = smd_config_list,
- .smd_ssr_config = &smd_ssr_cfg,
- .num_smem_areas = ARRAY_SIZE(aux_smem_areas),
- .smd_smem_areas = aux_smem_areas,
-};
-
-struct platform_device msm_device_smd_8974 = {
- .name = "msm_smd",
- .id = -1,
- .resource = smd_resource,
- .num_resources = ARRAY_SIZE(smd_resource),
- .dev = {
- .platform_data = &smd_platform_data,
- }
-};
-
-static void __init msm8974_calculate_reserve_sizes(void)
-{
- reserve_ebi_memory();
-}
-
static struct reserve_info msm8974_reserve_info __initdata = {
.memtype_reserve_table = msm8974_reserve_table,
- .calculate_reserve_sizes = msm8974_calculate_reserve_sizes,
.paddr_to_memtype = msm8974_paddr_to_memtype,
};
@@ -450,11 +264,6 @@
ARRAY_SIZE(msm_bus_8974_devices));
};
-void __init msm8974_add_devices(void)
-{
- platform_device_register(&msm_device_smd_8974);
-}
-
/*
* Used to satisfy dependencies for devices that need to be
* run early or in a particular order. Most likely your device doesn't fall
@@ -501,7 +310,6 @@
OF_DEV_AUXDATA("qcom,pil-q6v5-lpass", 0xFE200000, \
"pil-q6v5-lpass", NULL),
OF_DEV_AUXDATA("qcom,pil-q6v5-mss", 0xFC880000, "pil-q6v5-mss", NULL),
- OF_DEV_AUXDATA("qcom,pil-mba", 0xFC820000, "pil-mba", NULL),
OF_DEV_AUXDATA("qcom,pil-pronto", 0xFB21B000, \
"pil_pronto", NULL),
OF_DEV_AUXDATA("arm,coresight-tmc", 0xFC322000, \
@@ -561,7 +369,6 @@
regulator_has_full_constraints();
of_platform_populate(NULL, of_default_bus_match_table, adata, NULL);
- msm8974_add_devices();
msm8974_add_drivers();
}
diff --git a/arch/arm/mach-msm/board-9615-gpiomux.c b/arch/arm/mach-msm/board-9615-gpiomux.c
index 9339638..e5b7678 100644
--- a/arch/arm/mach-msm/board-9615-gpiomux.c
+++ b/arch/arm/mach-msm/board-9615-gpiomux.c
@@ -37,7 +37,7 @@
static struct gpiomux_setting gsbi5 = {
.func = GPIOMUX_FUNC_1,
- .drv = GPIOMUX_DRV_8MA,
+ .drv = GPIOMUX_DRV_2MA,
.pull = GPIOMUX_PULL_NONE,
};
@@ -201,6 +201,23 @@
},
};
+static struct gpiomux_setting sd_card_det = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_IN,
+};
+
+struct msm_gpiomux_config sd_card_det_config[] __initdata = {
+ {
+ .gpio = 80,
+ .settings = {
+ [GPIOMUX_ACTIVE] = &sd_card_det,
+ [GPIOMUX_SUSPENDED] = &sd_card_det,
+ },
+ },
+};
+
#ifdef CONFIG_LTC4088_CHARGER
static struct msm_gpiomux_config
msm9615_ltc4088_charger_config[] __initdata = {
@@ -362,6 +379,8 @@
msm_gpiomux_install(msm9615_ps_hold_config,
ARRAY_SIZE(msm9615_ps_hold_config));
+ msm_gpiomux_install(sd_card_det_config,
+ ARRAY_SIZE(sd_card_det_config));
msm_gpiomux_install(msm9615_sdcc2_configs,
ARRAY_SIZE(msm9615_sdcc2_configs));
#ifdef CONFIG_LTC4088_CHARGER
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index b9da615..39060ad 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -762,6 +762,7 @@
.disable_reset_on_disconnect = true,
.enable_lpm_on_dev_suspend = true,
.core_clk_always_on_workaround = true,
+ .delay_lpm_on_disconnect = true,
};
@@ -907,6 +908,7 @@
&msm_cpu_fe,
&msm_stub_codec,
&msm_voice,
+ &msm_dtmf,
&msm_voip,
&msm_i2s_cpudai0,
&msm_i2s_cpudai1,
@@ -922,6 +924,10 @@
&msm_cpudai_auxpcm_tx,
&msm_cpudai_sec_auxpcm_rx,
&msm_cpudai_sec_auxpcm_tx,
+ &msm_cpudai_stub,
+ &msm_cpudai_incall_music_rx,
+ &msm_cpudai_incall_record_rx,
+ &msm_cpudai_incall_record_tx,
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
@@ -939,6 +945,7 @@
&msm9615_rpm_stat_device,
&msm9615_rpm_master_stat_device,
&msm_tsens_device,
+ &msm9615_pm_8x60,
};
static void __init msm9615_i2c_init(void)
diff --git a/arch/arm/mach-msm/board-9625-gpiomux.c b/arch/arm/mach-msm/board-9625-gpiomux.c
index c4e174b..9102875 100644
--- a/arch/arm/mach-msm/board-9625-gpiomux.c
+++ b/arch/arm/mach-msm/board-9625-gpiomux.c
@@ -25,19 +25,49 @@
};
static struct gpiomux_setting gpio_spi_cs_config = {
- .func = GPIOMUX_FUNC_9,
+ .func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_12MA,
.pull = GPIOMUX_PULL_NONE,
};
static struct gpiomux_setting gpio_spi_config = {
- .func = GPIOMUX_FUNC_2,
+ .func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_12MA,
.pull = GPIOMUX_PULL_NONE,
};
+static struct gpiomux_setting gpio_i2c_config = {
+ .func = GPIOMUX_FUNC_3,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
{
+ .gpio = 4, /* BLSP1 QUP2 SPI_DATA_MOSI */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 5, /* BLSP1 QUP2 SPI_DATA_MISO */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 6, /* BLSP1 QUP2 SPI_CS_N */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_cs_config,
+ },
+ },
+ {
+ .gpio = 7, /* BLSP1 QUP2 SPI_CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
.gpio = 8, /* BLSP1 UART TX */
.settings = {
[GPIOMUX_SUSPENDED] = &gpio_uart_config,
@@ -50,30 +80,83 @@
},
},
{
- .gpio = 69, /* BLSP6 QUP SPI_CS_N */
+ .gpio = 10, /* BLSP1 QUP3 I2C_DAT */
.settings = {
- [GPIOMUX_SUSPENDED] = &gpio_spi_cs_config,
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config,
},
},
{
- .gpio = 20, /* BLSP6 QUP SPI_DATA_MOSI */
+ .gpio = 11, /* BLSP1 QUP3 I2C_CLK */
.settings = {
- [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config,
},
},
- {
- .gpio = 21, /* BLSP6 QUP SPI_DATA_MISO */
- .settings = {
- [GPIOMUX_SUSPENDED] = &gpio_spi_config,
- },
- },
- {
- .gpio = 23, /* BLSP6 QUP SPI_CLK */
- .settings = {
- [GPIOMUX_SUSPENDED] = &gpio_spi_config,
- },
- },
+};
+static struct gpiomux_setting mi2s_active_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting mi2s_suspend_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting codec_reset = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_6MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_OUT_LOW,
+};
+
+static struct msm_gpiomux_config mdm9625_mi2s_configs[] __initdata = {
+ {
+ .gpio = 12, /* mi2s ws */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mi2s_suspend_cfg,
+ [GPIOMUX_ACTIVE] = &mi2s_active_cfg,
+ },
+ },
+ {
+ .gpio = 15, /* mi2s sclk */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mi2s_suspend_cfg,
+ [GPIOMUX_ACTIVE] = &mi2s_active_cfg,
+ },
+ },
+ {
+ .gpio = 14, /* mi2s dout */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mi2s_suspend_cfg,
+ [GPIOMUX_ACTIVE] = &mi2s_active_cfg,
+ },
+ },
+ {
+ .gpio = 13, /* mi2s din */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mi2s_suspend_cfg,
+ [GPIOMUX_ACTIVE] = &mi2s_active_cfg,
+ },
+ },
+ {
+ .gpio = 71, /* mi2s mclk */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mi2s_suspend_cfg,
+ [GPIOMUX_ACTIVE] = &mi2s_active_cfg,
+ },
+ },
+};
+
+static struct msm_gpiomux_config mdm9625_cdc_reset_config[] __initdata = {
+ {
+ .gpio = 22, /* SYS_RST_N */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &codec_reset,
+ },
+ }
};
static struct gpiomux_setting sdc3_clk_active_cfg = {
@@ -152,6 +235,30 @@
},
};
+static struct gpiomux_setting wlan_ath6kl_active_config = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_OUT_LOW,
+};
+
+static struct gpiomux_setting wlan_ath6kl_suspend_config = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+ .dir = GPIOMUX_IN,
+};
+
+static struct msm_gpiomux_config wlan_ath6kl_configs[] __initdata = {
+ {
+ .gpio = 62,/* CHIP_PWD_L */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &wlan_ath6kl_active_config,
+ [GPIOMUX_SUSPENDED] = &wlan_ath6kl_suspend_config,
+ },
+ },
+};
+
void __init msm9625_init_gpiomux(void)
{
int rc;
@@ -164,4 +271,10 @@
msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
msm_gpiomux_install(sdc3_configs, ARRAY_SIZE(sdc3_configs));
+ msm_gpiomux_install(wlan_ath6kl_configs,
+ ARRAY_SIZE(wlan_ath6kl_configs));
+ msm_gpiomux_install(mdm9625_mi2s_configs,
+ ARRAY_SIZE(mdm9625_mi2s_configs));
+ msm_gpiomux_install(mdm9625_cdc_reset_config,
+ ARRAY_SIZE(mdm9625_cdc_reset_config));
}
diff --git a/arch/arm/mach-msm/board-9625.c b/arch/arm/mach-msm/board-9625.c
index 5c7eebe..8e8d3e7 100644
--- a/arch/arm/mach-msm/board-9625.c
+++ b/arch/arm/mach-msm/board-9625.c
@@ -35,6 +35,7 @@
#include <mach/rpm-smd.h>
#include <mach/rpm-regulator-smd.h>
#include "board-dt.h"
+#include <mach/msm_bus_board.h>
#include "clock.h"
#include "modem_notifier.h"
#include "lpm_resources.h"
@@ -100,14 +101,14 @@
static struct of_dev_auxdata msm9625_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("qcom,msm-lsuart-v14", 0xF991F000, \
"msm_serial_hsl.0", NULL),
- OF_DEV_AUXDATA("qcom,spi-qup-v2", 0xF9928000, \
- "spi_qsd.1", NULL),
OF_DEV_AUXDATA("qcom,spmi-pmic-arb", 0xFC4C0000, \
"spmi-pmic-arb.0", NULL),
OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF98A4000, \
"msm_sdcc.2", NULL),
OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF9864000, \
"msm_sdcc.3", NULL),
+ OF_DEV_AUXDATA("qcom,msm-tsens", 0xFC4A8000, \
+ "msm-tsens", NULL),
{}
};
@@ -251,6 +252,97 @@
}
};
+#define BIMC_BASE 0xfc380000
+#define BIMC_SIZE 0x0006A000
+#define SYS_NOC_BASE 0xfc460000
+#define PERIPH_NOC_BASE 0xFC468000
+#define CONFIG_NOC_BASE 0xfc480000
+#define NOC_SIZE 0x00004000
+
+static struct resource bimc_res[] = {
+ {
+ .start = BIMC_BASE,
+ .end = BIMC_BASE + BIMC_SIZE,
+ .flags = IORESOURCE_MEM,
+ .name = "bimc_mem",
+ },
+};
+
+static struct resource sys_noc_res[] = {
+ {
+ .start = SYS_NOC_BASE,
+ .end = SYS_NOC_BASE + NOC_SIZE,
+ .flags = IORESOURCE_MEM,
+ .name = "sys_noc_mem",
+ },
+};
+
+static struct resource config_noc_res[] = {
+ {
+ .start = CONFIG_NOC_BASE,
+ .end = CONFIG_NOC_BASE + NOC_SIZE,
+ .flags = IORESOURCE_MEM,
+ .name = "config_noc_mem",
+ },
+};
+
+static struct resource periph_noc_res[] = {
+ {
+ .start = PERIPH_NOC_BASE,
+ .end = PERIPH_NOC_BASE + NOC_SIZE,
+ .flags = IORESOURCE_MEM,
+ .name = "periph_noc_mem",
+ },
+};
+
+static struct platform_device msm_bus_sys_noc = {
+ .name = "msm_bus_fabric",
+ .id = MSM_BUS_FAB_SYS_NOC,
+ .num_resources = ARRAY_SIZE(sys_noc_res),
+ .resource = sys_noc_res,
+};
+
+static struct platform_device msm_bus_bimc = {
+ .name = "msm_bus_fabric",
+ .id = MSM_BUS_FAB_BIMC,
+ .num_resources = ARRAY_SIZE(bimc_res),
+ .resource = bimc_res,
+};
+
+static struct platform_device msm_bus_periph_noc = {
+ .name = "msm_bus_fabric",
+ .id = MSM_BUS_FAB_PERIPH_NOC,
+ .num_resources = ARRAY_SIZE(periph_noc_res),
+ .resource = periph_noc_res,
+};
+
+static struct platform_device msm_bus_config_noc = {
+ .name = "msm_bus_fabric",
+ .id = MSM_BUS_FAB_CONFIG_NOC,
+ .num_resources = ARRAY_SIZE(config_noc_res),
+ .resource = config_noc_res,
+};
+
+static struct platform_device *msm_bus_9625_devices[] = {
+ &msm_bus_sys_noc,
+ &msm_bus_bimc,
+ &msm_bus_periph_noc,
+ &msm_bus_config_noc,
+};
+
+static void __init msm9625_init_buses(void)
+{
+#ifdef CONFIG_MSM_BUS_SCALING
+ msm_bus_sys_noc.dev.platform_data =
+ &msm_bus_9625_sys_noc_pdata;
+ msm_bus_bimc.dev.platform_data = &msm_bus_9625_bimc_pdata;
+ msm_bus_periph_noc.dev.platform_data = &msm_bus_9625_periph_noc_pdata;
+ msm_bus_config_noc.dev.platform_data = &msm_bus_9625_config_noc_pdata;
+#endif
+ platform_add_devices(msm_bus_9625_devices,
+ ARRAY_SIZE(msm_bus_9625_devices));
+}
+
void __init msm9625_add_devices(void)
{
platform_device_register(&msm_device_smd_9625);
@@ -271,6 +363,7 @@
rpm_regulator_smd_driver_init();
msm_spm_device_init();
msm_clock_init(&msm9625_clock_init_data);
+ msm9625_init_buses();
}
void __init msm9625_init(void)
diff --git a/arch/arm/mach-msm/board-msm7627a-bt.c b/arch/arm/mach-msm/board-msm7627a-bt.c
index bcc9645..1c2d8a2 100644
--- a/arch/arm/mach-msm/board-msm7627a-bt.c
+++ b/arch/arm/mach-msm/board-msm7627a-bt.c
@@ -103,11 +103,12 @@
if (machine_is_msm7627a_qrd1())
gpio_bt_sys_rest_en = 114;
if (machine_is_msm7627a_evb() || machine_is_msm8625_evb()
- || machine_is_msm8625_evt()
- || machine_is_qrd_skud_prime())
+ || machine_is_msm8625_evt())
gpio_bt_sys_rest_en = 16;
if (machine_is_msm8625_qrd7())
gpio_bt_sys_rest_en = 88;
+ if (machine_is_qrd_skud_prime())
+ gpio_bt_sys_rest_en = 35;
if (machine_is_msm7627a_qrd3()) {
if (socinfo == 0x70002)
gpio_bt_sys_rest_en = 88;
@@ -976,9 +977,6 @@
int i, rc = 0;
struct device *dev;
- if (machine_is_qrd_skud_prime())
- return;
-
gpio_bt_config();
rc = i2c_register_board_info(MSM_GSBI1_QUP_I2C_BUS_ID,
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 13c4be2..4e14ff3 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -375,7 +375,8 @@
};
/* 8625 PM platform data */
-static struct msm_pm_platform_data msm8625_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
+static struct msm_pm_platform_data
+ msm8625_pm_data[MSM_PM_SLEEP_MODE_NR * CONFIG_NR_CPUS] = {
/* CORE0 entries */
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 1,
@@ -433,6 +434,44 @@
.residency = 10,
},
+ /* picked latency & redisdency values from 7x30 */
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ .latency = 500,
+ .residency = 6000,
+ },
+
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 1,
+ .suspend_enabled = 1,
+ .latency = 2,
+ .residency = 10,
+ },
+
+ /* picked latency & redisdency values from 7x30 */
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ .latency = 500,
+ .residency = 6000,
+ },
+
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 1,
+ .suspend_enabled = 1,
+ .latency = 2,
+ .residency = 10,
+ },
+
};
static struct msm_pm_boot_platform_data msm_pm_8625_boot_pdata __initdata = {
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index fd322e9..023ce86 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -349,7 +349,8 @@
};
/* 8625 PM platform data */
-static struct msm_pm_platform_data msm8625_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
+static struct msm_pm_platform_data
+ msm8625_pm_data[MSM_PM_SLEEP_MODE_NR * CONFIG_NR_CPUS] = {
/* CORE0 entries */
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 1,
@@ -407,6 +408,44 @@
.residency = 10,
},
+ /* picked latency & redisdency values from 7x30 */
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ .latency = 500,
+ .residency = 6000,
+ },
+
+ [MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 1,
+ .suspend_enabled = 1,
+ .latency = 2,
+ .residency = 10,
+ },
+
+ /* picked latency & redisdency values from 7x30 */
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 0,
+ .suspend_enabled = 0,
+ .latency = 500,
+ .residency = 6000,
+ },
+
+ [MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
+ .idle_supported = 1,
+ .suspend_supported = 1,
+ .idle_enabled = 1,
+ .suspend_enabled = 1,
+ .latency = 2,
+ .residency = 10,
+ },
+
};
static struct msm_pm_boot_platform_data msm_pm_8625_boot_pdata __initdata = {
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index e1390db..3f59035 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -279,8 +279,8 @@
.en_mask = BIT(1),
.status_reg = PLL1_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &tcxo_clk.c,
.c = {
+ .parent = &tcxo_clk.c,
.dbg_name = "pll1_clk",
.rate = 768000000,
.ops = &clk_ops_pll_vote,
@@ -293,8 +293,8 @@
.en_mask = BIT(2),
.status_reg = PLL2_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &tcxo_clk.c,
.c = {
+ .parent = &tcxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 806400000, /* TODO: Support scaling */
.ops = &clk_ops_pll_vote,
@@ -307,8 +307,8 @@
.en_mask = BIT(3),
.status_reg = PLL3_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &lpxo_clk.c,
.c = {
+ .parent = &lpxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 737280000,
.ops = &clk_ops_pll_vote,
@@ -321,8 +321,8 @@
.en_mask = BIT(4),
.status_reg = PLL4_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &lpxo_clk.c,
.c = {
+ .parent = &lpxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 891000000,
.ops = &clk_ops_pll_vote,
@@ -363,8 +363,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 2,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "axi_li_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_apps_clk.c),
@@ -379,8 +379,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 14,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_adsp_a_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_adsp_a_clk.c),
@@ -395,8 +395,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 19,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_jpeg_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_jpeg_clk.c),
@@ -411,8 +411,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 23,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_vfe_clk.c),
@@ -427,8 +427,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 29,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_mdp_clk.c),
@@ -443,8 +443,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 3,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "axi_li_vg_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_vg_clk.c),
@@ -459,8 +459,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 21,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_grp_2d_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_grp_2d_clk.c),
@@ -475,8 +475,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 22,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_li_grp_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_grp_clk.c),
@@ -491,8 +491,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 20,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_mfc_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_mfc_clk.c),
@@ -508,8 +508,8 @@
.halt_bit = 22,
.reset_mask = P_AXI_ROTATOR_CLK,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_rotator_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_rotator_clk.c),
@@ -524,8 +524,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 21,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_vpe_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_vpe_clk.c),
@@ -542,8 +542,8 @@
.halt_bit = 5,
.reset_mask = P_ADM_CLK,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "adm_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm_clk.c),
@@ -558,8 +558,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 15,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "adm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm_p_clk.c),
@@ -575,8 +575,8 @@
.halt_bit = 6,
.reset_mask = P_CE_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "ce_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce_clk.c),
@@ -592,8 +592,8 @@
.halt_bit = 9,
.reset_mask = P_CAMIF_PAD_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "camif_pad_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(camif_pad_p_clk.c),
@@ -609,8 +609,8 @@
.halt_bit = 30,
.reset_mask = P_CSI0_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "csi0_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_p_clk.c),
@@ -626,8 +626,8 @@
.halt_bit = 3,
.reset_mask = P_EMDH_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "emdh_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(emdh_p_clk.c),
@@ -643,8 +643,8 @@
.halt_bit = 24,
.reset_mask = P_GRP_2D_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "grp_2d_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_2d_p_clk.c),
@@ -660,8 +660,8 @@
.halt_bit = 17,
.reset_mask = P_GRP_3D_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "grp_3d_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_3d_p_clk.c),
@@ -677,8 +677,8 @@
.halt_bit = 24,
.reset_mask = P_JPEG_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "jpeg_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(jpeg_p_clk.c),
@@ -694,8 +694,8 @@
.halt_bit = 7,
.reset_mask = P_LPA_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "lpa_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(lpa_p_clk.c),
@@ -711,8 +711,8 @@
.halt_bit = 6,
.reset_mask = P_MDP_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "mdp_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_p_clk.c),
@@ -728,8 +728,8 @@
.halt_bit = 26,
.reset_mask = P_MFC_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "mfc_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(mfc_p_clk.c),
@@ -745,8 +745,8 @@
.halt_bit = 4,
.reset_mask = P_PMDH_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "pmdh_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(pmdh_p_clk.c),
@@ -762,8 +762,8 @@
.halt_bit = 23,
.reset_mask = P_ROTATOR_IMEM_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "rotator_imem_clk",
.ops = &clk_ops_branch,
CLK_INIT(rotator_imem_clk.c),
@@ -779,8 +779,8 @@
.halt_bit = 25,
.reset_mask = P_ROTATOR_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "rotator_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(rotator_p_clk.c),
@@ -796,8 +796,8 @@
.halt_bit = 7,
.reset_mask = P_SDC1_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc1_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc1_p_clk.c),
@@ -813,8 +813,8 @@
.halt_bit = 8,
.reset_mask = P_SDC2_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc2_p_clk.c),
@@ -830,8 +830,8 @@
.halt_bit = 27,
.reset_mask = P_SDC3_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc3_p_clk.c),
@@ -847,8 +847,8 @@
.halt_bit = 28,
.reset_mask = P_SDC4_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc4_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc4_p_clk.c),
@@ -864,8 +864,8 @@
.halt_bit = 10,
.reset_mask = P_SPI_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "spi_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(spi_p_clk.c),
@@ -881,8 +881,8 @@
.halt_bit = 18,
.reset_mask = P_TSIF_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "tsif_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(tsif_p_clk.c),
@@ -897,8 +897,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 17,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "uart1dm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(uart1dm_p_clk.c),
@@ -913,8 +913,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 26,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "uart2dm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(uart2dm_p_clk.c),
@@ -930,8 +930,8 @@
.halt_bit = 8,
.reset_mask = P_USB_HS2_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_p_clk.c),
@@ -947,8 +947,8 @@
.halt_bit = 9,
.reset_mask = P_USB_HS3_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_p_clk.c),
@@ -964,8 +964,8 @@
.halt_bit = 25,
.reset_mask = P_USB_HS_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs_p_clk.c),
@@ -981,8 +981,8 @@
.halt_bit = 27,
.reset_mask = P_VFE_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "vfe_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_p_clk.c),
@@ -1320,8 +1320,8 @@
.halt_bit = 18,
.reset_mask = P_GRP_3D_CLK,
},
- .parent = &grp_3d_src_clk.c,
.c = {
+ .parent = &grp_3d_src_clk.c,
.dbg_name = "grp_3d_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_3d_clk.c),
@@ -1336,8 +1336,8 @@
.halt_bit = 19,
.reset_mask = P_IMEM_CLK,
},
- .parent = &grp_3d_src_clk.c,
.c = {
+ .parent = &grp_3d_src_clk.c,
.dbg_name = "imem_clk",
.ops = &clk_ops_branch,
CLK_INIT(imem_clk.c),
@@ -1542,8 +1542,8 @@
.halt_bit = 29,
.reset_mask = P_MDP_LCDC_PAD_PCLK_CLK,
},
- .parent = &mdp_lcdc_pclk_clk.c,
.c = {
+ .parent = &mdp_lcdc_pclk_clk.c,
.dbg_name = "mdp_lcdc_pad_pclk_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_lcdc_pad_pclk_clk.c),
@@ -1616,8 +1616,8 @@
.halt_bit = 13,
.reset_mask = P_MI2S_CODEC_RX_S_CLK,
},
- .parent = &mi2s_codec_rx_m_clk.c,
.c = {
+ .parent = &mi2s_codec_rx_m_clk.c,
.dbg_name = "mi2s_codec_rx_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_codec_rx_s_clk.c),
@@ -1656,8 +1656,8 @@
.halt_bit = 11,
.reset_mask = P_MI2S_CODEC_TX_S_CLK,
},
- .parent = &mi2s_codec_tx_m_clk.c,
.c = {
+ .parent = &mi2s_codec_tx_m_clk.c,
.dbg_name = "mi2s_codec_tx_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_codec_tx_s_clk.c),
@@ -1702,8 +1702,8 @@
.halt_bit = 3,
.reset_mask = P_MI2S_S_CLK,
},
- .parent = &mi2s_m_clk.c,
.c = {
+ .parent = &mi2s_m_clk.c,
.dbg_name = "mi2s_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_s_clk.c),
@@ -1763,8 +1763,8 @@
.halt_bit = 17,
.reset_mask = P_SDAC_M_CLK,
},
- .parent = &sdac_clk.c,
.c = {
+ .parent = &sdac_clk.c,
.dbg_name = "sdac_m_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdac_m_clk.c),
@@ -1807,8 +1807,8 @@
.halt_bit = 7,
.reset_mask = P_HDMI_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "hdmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_clk.c),
@@ -1823,8 +1823,8 @@
.halt_bit = 27,
.reset_mask = P_TV_DAC_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -1839,8 +1839,8 @@
.halt_bit = 10,
.reset_mask = P_TV_ENC_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -1856,8 +1856,8 @@
.halt_bit = 11,
.reset_mask = P_TSIF_REF_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(tsif_ref_clk.c),
@@ -1915,8 +1915,8 @@
.halt_bit = 27,
.reset_mask = P_USB_HS_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs_core_clk.c),
@@ -1931,8 +1931,8 @@
.halt_bit = 3,
.reset_mask = P_USB_HS2_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs2_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_clk.c),
@@ -1947,8 +1947,8 @@
.halt_bit = 28,
.reset_mask = P_USB_HS2_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs2_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_core_clk.c),
@@ -1963,8 +1963,8 @@
.halt_bit = 2,
.reset_mask = P_USB_HS3_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs3_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_clk.c),
@@ -1979,8 +1979,8 @@
.halt_bit = 29,
.reset_mask = P_USB_HS3_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs3_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_core_clk.c),
@@ -2062,8 +2062,8 @@
.halt_bit = 9,
.reset_mask = P_VFE_MDC_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "vfe_mdc_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_mdc_clk.c),
@@ -2078,8 +2078,8 @@
.halt_bit = 13,
.reset_mask = P_VFE_CAMIF_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "vfe_camif_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_camif_clk.c),
@@ -2094,8 +2094,8 @@
.halt_bit = 16,
.reset_mask = P_CSI0_VFE_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi0_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_vfe_clk.c),
@@ -2219,8 +2219,8 @@
.halt_bit = 11,
.reset_mask = P_MFC_DIV2_CLK,
},
- .parent = &mfc_clk.c,
.c = {
+ .parent = &mfc_clk.c,
.dbg_name = "mfc_div2_clk",
.ops = &clk_ops_branch,
CLK_INIT(mfc_div2_clk.c),
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 3c417c3..a4d7e61 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -525,8 +525,8 @@
static struct pll_clk pll2_clk = {
.mode_reg = MM_PLL1_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 800000000,
.ops = &clk_ops_local_pll,
@@ -536,8 +536,8 @@
static struct pll_clk pll3_clk = {
.mode_reg = BB_MMCC_PLL2_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 1200000000,
.ops = &clk_ops_local_pll,
@@ -555,8 +555,8 @@
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 393216000,
.ops = &clk_ops_pll_vote,
@@ -569,8 +569,8 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_vote,
@@ -583,8 +583,8 @@
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll14_clk",
.rate = 480000000,
.ops = &clk_ops_pll_vote,
@@ -594,8 +594,8 @@
static struct pll_clk pll15_clk = {
.mode_reg = MM_PLL3_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll15_clk",
.rate = 975000000,
.ops = &clk_ops_local_pll,
@@ -1701,8 +1701,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 24,
},
- .parent = &usb_hsic_xcvr_fs_clk.c,
.c = {
+ .parent = &usb_hsic_xcvr_fs_clk.c,
.dbg_name = "usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_system_clk.c),
@@ -1743,8 +1743,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 19,
},
- .parent = &usb_hsic_hsic_src_clk.c,
.c = {
+ .parent = &usb_hsic_hsic_src_clk.c,
.dbg_name = "usb_hsic_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_hsic_clk.c),
@@ -1823,8 +1823,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 15,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_xcvr_clk.c),
@@ -1840,8 +1840,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 16,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_sys_clk.c),
@@ -1858,8 +1858,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 12,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_xcvr_clk.c),
@@ -1875,8 +1875,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 13,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_sys_clk.c),
@@ -1962,8 +1962,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 5,
},
- .parent = &ce3_src_clk.c,
.c = {
+ .parent = &ce3_src_clk.c,
.dbg_name = "ce3_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce3_core_clk.c),
@@ -1979,8 +1979,8 @@
.halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
.halt_bit = 16,
},
- .parent = &ce3_src_clk.c,
.c = {
+ .parent = &ce3_src_clk.c,
.dbg_name = "ce3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce3_p_clk.c),
@@ -2027,8 +2027,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 26,
},
- .parent = &sata_src_clk.c,
.c = {
+ .parent = &sata_src_clk.c,
.dbg_name = "sata_rxoob_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_rxoob_clk.c),
@@ -2042,8 +2042,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 25,
},
- .parent = &sata_src_clk.c,
.c = {
+ .parent = &sata_src_clk.c,
.dbg_name = "sata_pmalive_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_pmalive_clk.c),
@@ -2057,8 +2057,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 24,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "sata_phy_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_phy_ref_clk.c),
@@ -2750,8 +2750,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 13,
},
- .parent = &csi0_src_clk.c,
.c = {
+ .parent = &csi0_src_clk.c,
.dbg_name = "csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_clk.c),
@@ -2767,8 +2767,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 9,
},
- .parent = &csi0_src_clk.c,
.c = {
+ .parent = &csi0_src_clk.c,
.dbg_name = "csi0_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_phy_clk.c),
@@ -2806,8 +2806,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 14,
},
- .parent = &csi1_src_clk.c,
.c = {
+ .parent = &csi1_src_clk.c,
.dbg_name = "csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_clk.c),
@@ -2823,8 +2823,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 10,
},
- .parent = &csi1_src_clk.c,
.c = {
+ .parent = &csi1_src_clk.c,
.dbg_name = "csi1_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_phy_clk.c),
@@ -2862,8 +2862,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 29,
},
- .parent = &csi2_src_clk.c,
.c = {
+ .parent = &csi2_src_clk.c,
.dbg_name = "csi2_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2_clk.c),
@@ -2879,8 +2879,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 29,
},
- .parent = &csi2_src_clk.c,
.c = {
+ .parent = &csi2_src_clk.c,
.dbg_name = "csi2_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2_phy_clk.c),
@@ -2977,6 +2977,7 @@
mb();
udelay(1);
rdi->cur_rate = rate;
+ c->parent = mux_map[rate];
spin_unlock(&local_clock_reg_lock);
if (rdi->enabled)
@@ -3038,11 +3039,6 @@
return branch_reset(&to_pix_rdi_clk(c)->b, action);
}
-static struct clk *pix_rdi_clk_get_parent(struct clk *c)
-{
- return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate];
-}
-
static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
{
if (pix_rdi_mux_map[n])
@@ -3064,6 +3060,7 @@
rdi->cur_rate = reg & rdi->s_mask ? 1 : 0;
reg = readl_relaxed(rdi->s2_reg);
rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate;
+ c->parent = pix_rdi_mux_map[rdi->cur_rate];
return HANDOFF_ENABLED_CLK;
}
@@ -3078,7 +3075,6 @@
.get_rate = pix_rdi_clk_get_rate,
.list_rate = pix_rdi_clk_list_rate,
.reset = pix_rdi_clk_reset,
- .get_parent = pix_rdi_clk_get_parent,
};
static struct pix_rdi_clk csi_pix_clk = {
@@ -3220,8 +3216,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 17,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi0phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0phy_timer_clk.c),
@@ -3235,8 +3231,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 18,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi1phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1phy_timer_clk.c),
@@ -3250,8 +3246,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 30,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi2phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2phy_timer_clk.c),
@@ -3510,24 +3506,26 @@
.ctl_val = CC_BANKED(9, 6, n), \
}
-static struct clk_freq_tbl clk_tbl_gfx3d_8960ab[] = {
- F_GFX3D( 0, gnd, 0, 0),
- F_GFX3D( 27000000, pxo, 0, 0),
- F_GFX3D( 48000000, pll8, 1, 8),
- F_GFX3D( 54857000, pll8, 1, 7),
- F_GFX3D( 64000000, pll8, 1, 6),
- F_GFX3D( 76800000, pll8, 1, 5),
- F_GFX3D( 96000000, pll8, 1, 4),
- F_GFX3D(128000000, pll8, 1, 3),
- F_GFX3D(145455000, pll2, 2, 11),
- F_GFX3D(160000000, pll2, 1, 5),
- F_GFX3D(177778000, pll2, 2, 9),
- F_GFX3D(200000000, pll2, 1, 4),
- F_GFX3D(228571000, pll2, 2, 7),
- F_GFX3D(266667000, pll2, 1, 3),
- F_GFX3D(320000000, pll2, 2, 5),
- F_GFX3D(325000000, pll3, 1, 2),
- F_GFX3D(400000000, pll2, 1, 2),
+/*Shared by 8064, 8930, and 8960ab*/
+static struct clk_freq_tbl clk_tbl_gfx3d[] = {
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(192000000, pll8, 1, 2),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(320000000, pll2, 2, 5),
+ F_GFX3D(400000000, pll2, 1, 2),
+ F_GFX3D(450000000, pll15, 1, 2),
F_END
};
@@ -3552,28 +3550,7 @@
F_END
};
-static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0),
- F_GFX3D( 27000000, pxo, 0, 0),
- F_GFX3D( 48000000, pll8, 1, 8),
- F_GFX3D( 54857000, pll8, 1, 7),
- F_GFX3D( 64000000, pll8, 1, 6),
- F_GFX3D( 76800000, pll8, 1, 5),
- F_GFX3D( 96000000, pll8, 1, 4),
- F_GFX3D(128000000, pll8, 1, 3),
- F_GFX3D(145455000, pll2, 2, 11),
- F_GFX3D(160000000, pll2, 1, 5),
- F_GFX3D(177778000, pll2, 2, 9),
- F_GFX3D(192000000, pll8, 1, 2),
- F_GFX3D(200000000, pll2, 1, 4),
- F_GFX3D(228571000, pll2, 2, 7),
- F_GFX3D(266667000, pll2, 1, 3),
- F_GFX3D(400000000, pll2, 1, 2),
- F_GFX3D(450000000, pll15, 1, 2),
- F_END
-};
-
-static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
+static struct clk_freq_tbl clk_tbl_gfx3d_8930ab[] = {
F_GFX3D( 0, gnd, 0, 0),
F_GFX3D( 27000000, pxo, 0, 0),
F_GFX3D( 48000000, pll8, 1, 8),
@@ -3591,7 +3568,7 @@
F_GFX3D(266667000, pll2, 1, 3),
F_GFX3D(320000000, pll2, 2, 5),
F_GFX3D(400000000, pll2, 1, 2),
- F_GFX3D(450000000, pll15, 1, 2),
+ F_GFX3D(500000000, pll15, 1, 2),
F_END
};
@@ -3619,6 +3596,12 @@
[VDD_DIG_HIGH] = 450000000
};
+static unsigned long fmax_gfx3d_8930ab[VDD_DIG_NUM] = {
+ [VDD_DIG_LOW] = 192000000,
+ [VDD_DIG_NOMINAL] = 320000000,
+ [VDD_DIG_HIGH] = 500000000
+};
+
static struct bank_masks bmnd_info_gfx3d = {
.bank_sel_mask = BIT(11),
.bank0_mask = {
@@ -3651,7 +3634,7 @@
.ns_reg = GFX3D_NS_REG,
.root_en_mask = BIT(2),
.set_rate = set_rate_mnd_banked,
- .freq_tbl = clk_tbl_gfx3d_8960,
+ .freq_tbl = clk_tbl_gfx3d,
.bank_info = &bmnd_info_gfx3d,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -3732,8 +3715,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 25,
},
- .parent = &vcap_clk.c,
.c = {
+ .parent = &vcap_clk.c,
.dbg_name = "vcap_npl_clk",
.ops = &clk_ops_branch,
CLK_INIT(vcap_npl_clk.c),
@@ -3950,8 +3933,8 @@
.retain_reg = MDP_LUT_CC_REG,
.retain_mask = BIT(31),
},
- .parent = &mdp_clk.c,
.c = {
+ .parent = &mdp_clk.c,
.dbg_name = "lut_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(lut_mdp_clk.c),
@@ -4071,18 +4054,13 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
-{
- return &pxo_clk.c;
-}
-
static struct clk_ops clk_ops_hdmi_pll = {
.enable = hdmi_pll_clk_enable,
.disable = hdmi_pll_clk_disable,
- .get_parent = hdmi_pll_clk_get_parent,
};
static struct clk hdmi_pll_clk = {
+ .parent = &pxo_clk.c,
.dbg_name = "hdmi_pll_clk",
.ops = &clk_ops_hdmi_pll,
.vdd_class = &vdd_sr2_hdmi_pll,
@@ -4189,8 +4167,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 9,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -4204,8 +4182,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 10,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -4223,8 +4201,8 @@
.retain_reg = TV_CC2_REG,
.retain_mask = BIT(10),
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "mdp_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_tv_clk.c),
@@ -4240,8 +4218,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 11,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "hdmi_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_tv_clk.c),
@@ -4255,8 +4233,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 27,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "rgb_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(rgb_tv_clk.c),
@@ -4270,8 +4248,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 26,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "npl_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(npl_tv_clk.c),
@@ -4366,6 +4344,12 @@
[VDD_DIG_HIGH] = 266670000,
};
+static unsigned long fmax_vcodec_8930ab[VDD_DIG_NUM] = {
+ [VDD_DIG_LOW] = 100000000,
+ [VDD_DIG_NOMINAL] = 200000000,
+ [VDD_DIG_HIGH] = 266670000
+};
+
#define F_VPE(f, s, d) \
{ \
.freq_hz = f, \
@@ -4487,8 +4471,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 8,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi_vfe_clk.c),
@@ -4760,8 +4744,8 @@
.halt_check = ENABLE,
.halt_bit = 1,
},
- .parent = &audio_slimbus_clk.c,
.c = {
+ .parent = &audio_slimbus_clk.c,
.dbg_name = "sps_slimbus_clk",
.ops = &clk_ops_branch,
CLK_INIT(sps_slimbus_clk.c),
@@ -4775,8 +4759,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 28,
},
- .parent = &sps_slimbus_clk.c,
.c = {
+ .parent = &sps_slimbus_clk.c,
.dbg_name = "slimbus_xo_src_clk",
.ops = &clk_ops_branch,
CLK_INIT(slimbus_xo_src_clk.c),
@@ -6335,12 +6319,12 @@
*/
/*
* Initialize MM AHB registers: Enable the FPB clock and disable HW
- * gating on 8627 and 8960 for all clocks. Also set VFE_AHB's
+ * gating on 8627, 8960 and 8930ab for all clocks. Also set VFE_AHB's
* FORCE_CORE_ON bit to prevent its memory from being collapsed when
* the clock is halted. The sleep and wake-up delays are set to safe
* values.
*/
- if (cpu_is_msm8627() || cpu_is_msm8960ab()) {
+ if (cpu_is_msm8627() || cpu_is_msm8960ab() || cpu_is_msm8930ab()) {
rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
writel_relaxed(0x000007F9, AHB_EN2_REG);
} else {
@@ -6360,7 +6344,7 @@
* delays to safe values. */
if (cpu_is_msm8960ab() || (cpu_is_msm8960() &&
SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 3) ||
- cpu_is_msm8627()) {
+ cpu_is_msm8627() || cpu_is_msm8930ab()) {
rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
} else {
@@ -6373,12 +6357,13 @@
if (cpu_is_apq8064() || cpu_is_apq8064ab())
rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF);
- if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627())
+ if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627() ||
+ cpu_is_msm8930ab())
rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
if (cpu_is_msm8960ab())
rmwreg(0x009FE000, MAXI_EN5_REG, 0x01FFE000);
- if (cpu_is_msm8627())
+ if (cpu_is_msm8627() || cpu_is_msm8930ab())
rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
else if (cpu_is_msm8960ab())
rmwreg(0x000001C6, SAXI_EN_REG, 0x00001DF6);
@@ -6419,7 +6404,7 @@
rmwreg(0x00000001, DSI2_PIXEL_CC2_REG, 0x00000001);
if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
- cpu_is_msm8627())
+ cpu_is_msm8627() || cpu_is_msm8930ab())
rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
if (cpu_is_msm8960ab())
rmwreg(0x00000000, TV_CC_REG, 0x00004010);
@@ -6519,8 +6504,7 @@
}
/*
- * Program PLL15 to 900MHz with ref clk = 27MHz and
- * only enable PLL main output.
+ * Change PLL15 configuration based on the SoC we're running on.
*/
if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
@@ -6529,6 +6513,13 @@
configure_sr_pll(&pll15_config, &pll15_regs, 0);
/* Disable AUX and BIST outputs */
writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
+ } else if (cpu_is_msm8930ab()) {
+ pll15_config.l = 0x25 | BVAL(31, 7, 0x600);
+ pll15_config.m = 0x25;
+ pll15_config.n = 0x3E7;
+ configure_sr_pll(&pll15_config, &pll15_regs, 0);
+ /* Disable AUX and BIST outputs */
+ writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
}
}
@@ -6558,7 +6549,6 @@
sizeof(msm_clocks_8960_common));
if (cpu_is_msm8960ab()) {
pll3_clk.c.rate = 650000000;
- gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960ab;
gfx3d_clk.c.fmax[VDD_DIG_LOW] = 192000000;
gfx3d_clk.c.fmax[VDD_DIG_NOMINAL] = 325000000;
gfx3d_clk.c.fmax[VDD_DIG_HIGH] = 400000000;
@@ -6573,6 +6563,7 @@
gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
} else if (cpu_is_msm8960()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960;
memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common),
msm_clocks_8960_only, sizeof(msm_clocks_8960_only));
msm8960_clock_init_data.size -=
@@ -6583,11 +6574,9 @@
* clocks which differ between chips.
*/
if (cpu_is_apq8064()) {
- gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
gfx3d_clk.c.fmax = fmax_gfx3d_8064;
}
if (cpu_is_apq8064ab()) {
- gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
gfx3d_clk.c.fmax = fmax_gfx3d_8064ab;
}
if ((cpu_is_apq8064() &&
@@ -6610,15 +6599,19 @@
* Change the freq tables and voltage requirements for
* clocks which differ between 8960 and 8930.
*/
- if (cpu_is_msm8930() || cpu_is_msm8627()) {
+ if (cpu_is_msm8930() || cpu_is_msm8627())
gfx3d_clk.c.fmax = fmax_gfx3d_8930;
- } else if (cpu_is_msm8930aa()) {
+ else if (cpu_is_msm8930aa())
gfx3d_clk.c.fmax = fmax_gfx3d_8930aa;
- }
if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
- gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
pll15_clk.c.rate = 900000000;
gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
+ } else if (cpu_is_msm8930ab()) {
+ gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930ab;
+ pll15_clk.c.rate = 1000000000;
+ gfx3d_clk.c.fmax = fmax_gfx3d_8930ab;
+ gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
+ vcodec_clk.c.fmax = fmax_vcodec_8930ab;
}
if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B)
prng_clk.freq_tbl = clk_tbl_prng_64;
@@ -6673,7 +6666,7 @@
}
clk_set_rate(&usb_fs1_src_clk.c, 60000000);
if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_msm8930() ||
- cpu_is_msm8930aa() || cpu_is_msm8627())
+ cpu_is_msm8930aa() || cpu_is_msm8627() || cpu_is_msm8930ab())
clk_set_rate(&usb_fs2_src_clk.c, 60000000);
clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 76b8abf..c0a553f 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -694,9 +694,9 @@
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG,
.status_reg = (void __iomem *)GPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 600000000,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -709,9 +709,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)GPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 480000000,
.dbg_name = "gpll1_clk_src",
.ops = &clk_ops_pll_vote,
@@ -724,9 +724,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)LPAPLL_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 491520000,
.dbg_name = "lpapll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -739,9 +739,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)MMPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll0_clk_src",
.rate = 800000000,
.ops = &clk_ops_pll_vote,
@@ -754,9 +754,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)MMPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll1_clk_src",
.rate = 846000000,
.ops = &clk_ops_pll_vote,
@@ -767,9 +767,9 @@
static struct pll_clk mmpll3_clk_src = {
.mode_reg = (void __iomem *)MMPLL3_MODE_REG,
.status_reg = (void __iomem *)MMPLL3_STATUS_REG,
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll3_clk_src",
.rate = 1000000000,
.ops = &clk_ops_local_pll,
@@ -1512,10 +1512,10 @@
static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
@@ -1524,9 +1524,9 @@
static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
- .parent = &blsp1_qup1_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
@@ -1535,10 +1535,10 @@
static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
@@ -1547,9 +1547,9 @@
static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
- .parent = &blsp1_qup2_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
@@ -1558,10 +1558,10 @@
static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
@@ -1570,9 +1570,9 @@
static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
- .parent = &blsp1_qup3_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
@@ -1581,10 +1581,10 @@
static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
@@ -1593,9 +1593,9 @@
static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
- .parent = &blsp1_qup4_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
@@ -1604,10 +1604,10 @@
static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
@@ -1616,9 +1616,9 @@
static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
- .parent = &blsp1_qup5_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
@@ -1627,10 +1627,10 @@
static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
@@ -1639,9 +1639,9 @@
static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
- .parent = &blsp1_qup6_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
@@ -1650,9 +1650,9 @@
static struct branch_clk gcc_blsp1_uart1_apps_clk = {
.cbcr_reg = BLSP1_UART1_APPS_CBCR,
- .parent = &blsp1_uart1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
@@ -1661,9 +1661,9 @@
static struct branch_clk gcc_blsp1_uart2_apps_clk = {
.cbcr_reg = BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
@@ -1672,9 +1672,9 @@
static struct branch_clk gcc_blsp1_uart3_apps_clk = {
.cbcr_reg = BLSP1_UART3_APPS_CBCR,
- .parent = &blsp1_uart3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
@@ -1683,9 +1683,9 @@
static struct branch_clk gcc_blsp1_uart4_apps_clk = {
.cbcr_reg = BLSP1_UART4_APPS_CBCR,
- .parent = &blsp1_uart4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
@@ -1694,9 +1694,9 @@
static struct branch_clk gcc_blsp1_uart5_apps_clk = {
.cbcr_reg = BLSP1_UART5_APPS_CBCR,
- .parent = &blsp1_uart5_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
@@ -1705,9 +1705,9 @@
static struct branch_clk gcc_blsp1_uart6_apps_clk = {
.cbcr_reg = BLSP1_UART6_APPS_CBCR,
- .parent = &blsp1_uart6_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
@@ -1740,10 +1740,10 @@
static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
@@ -1752,9 +1752,9 @@
static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
- .parent = &blsp2_qup1_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
@@ -1763,10 +1763,10 @@
static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
@@ -1775,9 +1775,9 @@
static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
- .parent = &blsp2_qup2_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
@@ -1786,10 +1786,10 @@
static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
@@ -1798,9 +1798,9 @@
static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
- .parent = &blsp2_qup3_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
@@ -1809,10 +1809,10 @@
static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
@@ -1821,9 +1821,9 @@
static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
- .parent = &blsp2_qup4_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
@@ -1832,10 +1832,10 @@
static struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup5_i2c_apps_clk.c),
@@ -1844,9 +1844,9 @@
static struct branch_clk gcc_blsp2_qup5_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP5_SPI_APPS_CBCR,
- .parent = &blsp2_qup5_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup5_spi_apps_clk.c),
@@ -1855,10 +1855,10 @@
static struct branch_clk gcc_blsp2_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup6_i2c_apps_clk.c),
@@ -1867,9 +1867,9 @@
static struct branch_clk gcc_blsp2_qup6_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP6_SPI_APPS_CBCR,
- .parent = &blsp2_qup6_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup6_spi_apps_clk.c),
@@ -1878,9 +1878,9 @@
static struct branch_clk gcc_blsp2_uart1_apps_clk = {
.cbcr_reg = BLSP2_UART1_APPS_CBCR,
- .parent = &blsp2_uart1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
@@ -1889,9 +1889,9 @@
static struct branch_clk gcc_blsp2_uart2_apps_clk = {
.cbcr_reg = BLSP2_UART2_APPS_CBCR,
- .parent = &blsp2_uart2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
@@ -1900,9 +1900,9 @@
static struct branch_clk gcc_blsp2_uart3_apps_clk = {
.cbcr_reg = BLSP2_UART3_APPS_CBCR,
- .parent = &blsp2_uart3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart3_apps_clk.c),
@@ -1911,9 +1911,9 @@
static struct branch_clk gcc_blsp2_uart4_apps_clk = {
.cbcr_reg = BLSP2_UART4_APPS_CBCR,
- .parent = &blsp2_uart4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart4_apps_clk.c),
@@ -1922,9 +1922,9 @@
static struct branch_clk gcc_blsp2_uart5_apps_clk = {
.cbcr_reg = BLSP2_UART5_APPS_CBCR,
- .parent = &blsp2_uart5_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart5_apps_clk.c),
@@ -1933,9 +1933,9 @@
static struct branch_clk gcc_blsp2_uart6_apps_clk = {
.cbcr_reg = BLSP2_UART6_APPS_CBCR,
- .parent = &blsp2_uart6_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart6_apps_clk.c),
@@ -2016,9 +2016,9 @@
static struct branch_clk gcc_gp1_clk = {
.cbcr_reg = GP1_CBCR,
- .parent = &gp1_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp1_clk_src.c,
.dbg_name = "gcc_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp1_clk.c),
@@ -2027,9 +2027,9 @@
static struct branch_clk gcc_gp2_clk = {
.cbcr_reg = GP2_CBCR,
- .parent = &gp2_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp2_clk_src.c,
.dbg_name = "gcc_gp2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp2_clk.c),
@@ -2038,9 +2038,9 @@
static struct branch_clk gcc_gp3_clk = {
.cbcr_reg = GP3_CBCR,
- .parent = &gp3_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp3_clk_src.c,
.dbg_name = "gcc_gp3_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp3_clk.c),
@@ -2049,9 +2049,9 @@
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
- .parent = &pdm2_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &pdm2_clk_src.c,
.dbg_name = "gcc_pdm2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_pdm2_clk.c),
@@ -2094,9 +2094,9 @@
static struct branch_clk gcc_sdcc1_apps_clk = {
.cbcr_reg = SDCC1_APPS_CBCR,
- .parent = &sdcc1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc1_apps_clk_src.c,
.dbg_name = "gcc_sdcc1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc1_apps_clk.c),
@@ -2116,9 +2116,9 @@
static struct branch_clk gcc_sdcc2_apps_clk = {
.cbcr_reg = SDCC2_APPS_CBCR,
- .parent = &sdcc2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc2_apps_clk_src.c,
.dbg_name = "gcc_sdcc2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc2_apps_clk.c),
@@ -2138,9 +2138,9 @@
static struct branch_clk gcc_sdcc3_apps_clk = {
.cbcr_reg = SDCC3_APPS_CBCR,
- .parent = &sdcc3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc3_apps_clk_src.c,
.dbg_name = "gcc_sdcc3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc3_apps_clk.c),
@@ -2160,9 +2160,9 @@
static struct branch_clk gcc_sdcc4_apps_clk = {
.cbcr_reg = SDCC4_APPS_CBCR,
- .parent = &sdcc4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc4_apps_clk_src.c,
.dbg_name = "gcc_sdcc4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc4_apps_clk.c),
@@ -2182,9 +2182,9 @@
static struct branch_clk gcc_tsif_ref_clk = {
.cbcr_reg = TSIF_REF_CBCR,
- .parent = &tsif_ref_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &tsif_ref_clk_src.c,
.dbg_name = "gcc_tsif_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_tsif_ref_clk.c),
@@ -2193,10 +2193,10 @@
struct branch_clk gcc_sys_noc_usb3_axi_clk = {
.cbcr_reg = SYS_NOC_USB3_AXI_CBCR,
- .parent = &usb30_master_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_master_clk_src.c,
.dbg_name = "gcc_sys_noc_usb3_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sys_noc_usb3_axi_clk.c),
@@ -2206,10 +2206,10 @@
static struct branch_clk gcc_usb30_master_clk = {
.cbcr_reg = USB30_MASTER_CBCR,
.bcr_reg = USB_30_BCR,
- .parent = &usb30_master_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_master_clk_src.c,
.dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb30_master_clk.c),
@@ -2219,9 +2219,9 @@
static struct branch_clk gcc_usb30_mock_utmi_clk = {
.cbcr_reg = USB30_MOCK_UTMI_CBCR,
- .parent = &usb30_mock_utmi_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_mock_utmi_clk_src.c,
.dbg_name = "gcc_usb30_mock_utmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb30_mock_utmi_clk.c),
@@ -2275,9 +2275,9 @@
static struct branch_clk gcc_usb_hs_system_clk = {
.cbcr_reg = USB_HS_SYSTEM_CBCR,
.bcr_reg = USB_HS_BCR,
- .parent = &usb_hs_system_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hs_system_clk_src.c,
.dbg_name = "gcc_usb_hs_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hs_system_clk.c),
@@ -2298,9 +2298,9 @@
static struct branch_clk gcc_usb_hsic_clk = {
.cbcr_reg = USB_HSIC_CBCR,
.bcr_reg = USB_HS_HSIC_BCR,
- .parent = &usb_hsic_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_clk_src.c,
.dbg_name = "gcc_usb_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_clk.c),
@@ -2309,9 +2309,9 @@
static struct branch_clk gcc_usb_hsic_io_cal_clk = {
.cbcr_reg = USB_HSIC_IO_CAL_CBCR,
- .parent = &usb_hsic_io_cal_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_io_cal_clk_src.c,
.dbg_name = "gcc_usb_hsic_io_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
@@ -2320,9 +2320,9 @@
static struct branch_clk gcc_usb_hsic_system_clk = {
.cbcr_reg = USB_HSIC_SYSTEM_CBCR,
- .parent = &usb_hsic_system_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_system_clk_src.c,
.dbg_name = "gcc_usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_system_clk.c),
@@ -2807,18 +2807,15 @@
},
};
-static struct clk *dsi_pll_clk_get_parent(struct clk *c)
-{
- return &cxo_clk_src.c;
-}
-
static struct clk dsipll0_byte_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "dsipll0_byte_clk_src",
.ops = &clk_ops_dsi_byte_pll,
CLK_INIT(dsipll0_byte_clk_src),
};
static struct clk dsipll0_pixel_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "dsipll0_pixel_clk_src",
.ops = &clk_ops_dsi_pixel_pll,
CLK_INIT(dsipll0_pixel_clk_src),
@@ -2829,8 +2826,8 @@
.div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
};
static struct clk_freq_tbl pixel_freq = {
- .src_clk = &dsipll0_byte_clk_src,
- .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
+ .src_clk = &dsipll0_pixel_clk_src,
+ .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val),
};
static struct clk_ops clk_ops_byte;
static struct clk_ops clk_ops_pixel;
@@ -2900,6 +2897,7 @@
.current_freq = &byte_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_byte_clk_src,
.dbg_name = "byte0_clk_src",
.ops = &clk_ops_byte,
VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000,
@@ -2913,6 +2911,7 @@
.current_freq = &byte_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_byte_clk_src,
.dbg_name = "byte1_clk_src",
.ops = &clk_ops_byte,
VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000,
@@ -3045,19 +3044,14 @@
return rc;
}
-static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
-{
- return &cxo_clk_src.c;
-}
-
static struct clk_ops clk_ops_hdmi_pll = {
.enable = hdmi_pll_clk_enable,
.disable = hdmi_pll_clk_disable,
.set_rate = hdmi_pll_clk_set_rate,
- .get_parent = hdmi_pll_clk_get_parent,
};
static struct clk hdmipll_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "hdmipll_clk_src",
.ops = &clk_ops_hdmi_pll,
CLK_INIT(hdmipll_clk_src),
@@ -3127,6 +3121,7 @@
.current_freq = &pixel_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_pixel_clk_src,
.dbg_name = "pclk0_clk_src",
.ops = &clk_ops_pixel,
VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000),
@@ -3139,6 +3134,7 @@
.current_freq = &pixel_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_pixel_clk_src,
.dbg_name = "pclk1_clk_src",
.ops = &clk_ops_pixel,
VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000),
@@ -3203,10 +3199,10 @@
static struct branch_clk camss_cci_cci_clk = {
.cbcr_reg = CAMSS_CCI_CCI_CBCR,
- .parent = &cci_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cci_clk_src.c,
.dbg_name = "camss_cci_cci_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_cci_cci_clk.c),
@@ -3226,10 +3222,10 @@
static struct branch_clk camss_csi0_clk = {
.cbcr_reg = CAMSS_CSI0_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0_clk.c),
@@ -3238,10 +3234,10 @@
static struct branch_clk camss_csi0phy_clk = {
.cbcr_reg = CAMSS_CSI0PHY_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0phy_clk.c),
@@ -3250,10 +3246,10 @@
static struct branch_clk camss_csi0pix_clk = {
.cbcr_reg = CAMSS_CSI0PIX_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0pix_clk.c),
@@ -3262,10 +3258,10 @@
static struct branch_clk camss_csi0rdi_clk = {
.cbcr_reg = CAMSS_CSI0RDI_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0rdi_clk.c),
@@ -3285,10 +3281,10 @@
static struct branch_clk camss_csi1_clk = {
.cbcr_reg = CAMSS_CSI1_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1_clk.c),
@@ -3297,10 +3293,10 @@
static struct branch_clk camss_csi1phy_clk = {
.cbcr_reg = CAMSS_CSI1PHY_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1phy_clk.c),
@@ -3309,10 +3305,10 @@
static struct branch_clk camss_csi1pix_clk = {
.cbcr_reg = CAMSS_CSI1PIX_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1pix_clk.c),
@@ -3321,10 +3317,10 @@
static struct branch_clk camss_csi1rdi_clk = {
.cbcr_reg = CAMSS_CSI1RDI_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1rdi_clk.c),
@@ -3344,10 +3340,10 @@
static struct branch_clk camss_csi2_clk = {
.cbcr_reg = CAMSS_CSI2_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2_clk.c),
@@ -3356,10 +3352,10 @@
static struct branch_clk camss_csi2phy_clk = {
.cbcr_reg = CAMSS_CSI2PHY_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2phy_clk.c),
@@ -3368,10 +3364,10 @@
static struct branch_clk camss_csi2pix_clk = {
.cbcr_reg = CAMSS_CSI2PIX_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2pix_clk.c),
@@ -3380,10 +3376,10 @@
static struct branch_clk camss_csi2rdi_clk = {
.cbcr_reg = CAMSS_CSI2RDI_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2rdi_clk.c),
@@ -3403,10 +3399,10 @@
static struct branch_clk camss_csi3_clk = {
.cbcr_reg = CAMSS_CSI3_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3_clk.c),
@@ -3415,10 +3411,10 @@
static struct branch_clk camss_csi3phy_clk = {
.cbcr_reg = CAMSS_CSI3PHY_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3phy_clk.c),
@@ -3427,10 +3423,10 @@
static struct branch_clk camss_csi3pix_clk = {
.cbcr_reg = CAMSS_CSI3PIX_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3pix_clk.c),
@@ -3439,10 +3435,10 @@
static struct branch_clk camss_csi3rdi_clk = {
.cbcr_reg = CAMSS_CSI3RDI_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3rdi_clk.c),
@@ -3451,10 +3447,10 @@
static struct branch_clk camss_csi_vfe0_clk = {
.cbcr_reg = CAMSS_CSI_VFE0_CBCR,
- .parent = &vfe0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe0_clk_src.c,
.dbg_name = "camss_csi_vfe0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi_vfe0_clk.c),
@@ -3463,10 +3459,10 @@
static struct branch_clk camss_csi_vfe1_clk = {
.cbcr_reg = CAMSS_CSI_VFE1_CBCR,
- .parent = &vfe1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe1_clk_src.c,
.dbg_name = "camss_csi_vfe1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi_vfe1_clk.c),
@@ -3475,10 +3471,10 @@
static struct branch_clk camss_gp0_clk = {
.cbcr_reg = CAMSS_GP0_CBCR,
- .parent = &mmss_gp0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mmss_gp0_clk_src.c,
.dbg_name = "camss_gp0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_gp0_clk.c),
@@ -3487,10 +3483,10 @@
static struct branch_clk camss_gp1_clk = {
.cbcr_reg = CAMSS_GP1_CBCR,
- .parent = &mmss_gp1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mmss_gp1_clk_src.c,
.dbg_name = "camss_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_gp1_clk.c),
@@ -3510,10 +3506,10 @@
static struct branch_clk camss_jpeg_jpeg0_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
- .parent = &jpeg0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg0_clk_src.c,
.dbg_name = "camss_jpeg_jpeg0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg0_clk.c),
@@ -3522,10 +3518,10 @@
static struct branch_clk camss_jpeg_jpeg1_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG1_CBCR,
- .parent = &jpeg1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg1_clk_src.c,
.dbg_name = "camss_jpeg_jpeg1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg1_clk.c),
@@ -3534,10 +3530,10 @@
static struct branch_clk camss_jpeg_jpeg2_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG2_CBCR,
- .parent = &jpeg2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg2_clk_src.c,
.dbg_name = "camss_jpeg_jpeg2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg2_clk.c),
@@ -3557,10 +3553,10 @@
static struct branch_clk camss_jpeg_jpeg_axi_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "camss_jpeg_jpeg_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
@@ -3569,10 +3565,10 @@
static struct branch_clk camss_jpeg_jpeg_ocmemnoc_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "camss_jpeg_jpeg_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg_ocmemnoc_clk.c),
@@ -3581,10 +3577,10 @@
static struct branch_clk camss_mclk0_clk = {
.cbcr_reg = CAMSS_MCLK0_CBCR,
- .parent = &mclk0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk0_clk_src.c,
.dbg_name = "camss_mclk0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk0_clk.c),
@@ -3593,10 +3589,10 @@
static struct branch_clk camss_mclk1_clk = {
.cbcr_reg = CAMSS_MCLK1_CBCR,
- .parent = &mclk1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk1_clk_src.c,
.dbg_name = "camss_mclk1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk1_clk.c),
@@ -3605,10 +3601,10 @@
static struct branch_clk camss_mclk2_clk = {
.cbcr_reg = CAMSS_MCLK2_CBCR,
- .parent = &mclk2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk2_clk_src.c,
.dbg_name = "camss_mclk2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk2_clk.c),
@@ -3617,10 +3613,10 @@
static struct branch_clk camss_mclk3_clk = {
.cbcr_reg = CAMSS_MCLK3_CBCR,
- .parent = &mclk3_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk3_clk_src.c,
.dbg_name = "camss_mclk3_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk3_clk.c),
@@ -3640,10 +3636,10 @@
static struct branch_clk camss_phy0_csi0phytimer_clk = {
.cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
- .parent = &csi0phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0phytimer_clk_src.c,
.dbg_name = "camss_phy0_csi0phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy0_csi0phytimer_clk.c),
@@ -3652,10 +3648,10 @@
static struct branch_clk camss_phy1_csi1phytimer_clk = {
.cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
- .parent = &csi1phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1phytimer_clk_src.c,
.dbg_name = "camss_phy1_csi1phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy1_csi1phytimer_clk.c),
@@ -3664,10 +3660,10 @@
static struct branch_clk camss_phy2_csi2phytimer_clk = {
.cbcr_reg = CAMSS_PHY2_CSI2PHYTIMER_CBCR,
- .parent = &csi2phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2phytimer_clk_src.c,
.dbg_name = "camss_phy2_csi2phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy2_csi2phytimer_clk.c),
@@ -3698,10 +3694,10 @@
static struct branch_clk camss_vfe_cpp_clk = {
.cbcr_reg = CAMSS_VFE_CPP_CBCR,
- .parent = &cpp_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cpp_clk_src.c,
.dbg_name = "camss_vfe_cpp_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_cpp_clk.c),
@@ -3710,10 +3706,10 @@
static struct branch_clk camss_vfe_vfe0_clk = {
.cbcr_reg = CAMSS_VFE_VFE0_CBCR,
- .parent = &vfe0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe0_clk_src.c,
.dbg_name = "camss_vfe_vfe0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe0_clk.c),
@@ -3722,10 +3718,10 @@
static struct branch_clk camss_vfe_vfe1_clk = {
.cbcr_reg = CAMSS_VFE_VFE1_CBCR,
- .parent = &vfe1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe1_clk_src.c,
.dbg_name = "camss_vfe_vfe1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe1_clk.c),
@@ -3745,10 +3741,10 @@
static struct branch_clk camss_vfe_vfe_axi_clk = {
.cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "camss_vfe_vfe_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe_axi_clk.c),
@@ -3757,10 +3753,10 @@
static struct branch_clk camss_vfe_vfe_ocmemnoc_clk = {
.cbcr_reg = CAMSS_VFE_VFE_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "camss_vfe_vfe_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe_ocmemnoc_clk.c),
@@ -3780,10 +3776,10 @@
static struct branch_clk mdss_axi_clk = {
.cbcr_reg = MDSS_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mdss_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_axi_clk.c),
@@ -3792,10 +3788,10 @@
static struct branch_clk mdss_byte0_clk = {
.cbcr_reg = MDSS_BYTE0_CBCR,
- .parent = &byte0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &byte0_clk_src.c,
.dbg_name = "mdss_byte0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_byte0_clk.c),
@@ -3804,10 +3800,10 @@
static struct branch_clk mdss_byte1_clk = {
.cbcr_reg = MDSS_BYTE1_CBCR,
- .parent = &byte1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &byte1_clk_src.c,
.dbg_name = "mdss_byte1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_byte1_clk.c),
@@ -3816,10 +3812,10 @@
static struct branch_clk mdss_edpaux_clk = {
.cbcr_reg = MDSS_EDPAUX_CBCR,
- .parent = &edpaux_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edpaux_clk_src.c,
.dbg_name = "mdss_edpaux_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edpaux_clk.c),
@@ -3828,10 +3824,10 @@
static struct branch_clk mdss_edplink_clk = {
.cbcr_reg = MDSS_EDPLINK_CBCR,
- .parent = &edplink_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edplink_clk_src.c,
.dbg_name = "mdss_edplink_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edplink_clk.c),
@@ -3840,10 +3836,10 @@
static struct branch_clk mdss_edppixel_clk = {
.cbcr_reg = MDSS_EDPPIXEL_CBCR,
- .parent = &edppixel_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edppixel_clk_src.c,
.dbg_name = "mdss_edppixel_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edppixel_clk.c),
@@ -3852,10 +3848,10 @@
static struct branch_clk mdss_esc0_clk = {
.cbcr_reg = MDSS_ESC0_CBCR,
- .parent = &esc0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &esc0_clk_src.c,
.dbg_name = "mdss_esc0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_esc0_clk.c),
@@ -3864,10 +3860,10 @@
static struct branch_clk mdss_esc1_clk = {
.cbcr_reg = MDSS_ESC1_CBCR,
- .parent = &esc1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &esc1_clk_src.c,
.dbg_name = "mdss_esc1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_esc1_clk.c),
@@ -3876,10 +3872,10 @@
static struct branch_clk mdss_extpclk_clk = {
.cbcr_reg = MDSS_EXTPCLK_CBCR,
- .parent = &extpclk_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &extpclk_clk_src.c,
.dbg_name = "mdss_extpclk_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_extpclk_clk.c),
@@ -3899,10 +3895,10 @@
static struct branch_clk mdss_hdmi_clk = {
.cbcr_reg = MDSS_HDMI_CBCR,
- .parent = &hdmi_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &hdmi_clk_src.c,
.dbg_name = "mdss_hdmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_hdmi_clk.c),
@@ -3911,10 +3907,10 @@
static struct branch_clk mdss_mdp_clk = {
.cbcr_reg = MDSS_MDP_CBCR,
- .parent = &mdp_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mdp_clk_src.c,
.dbg_name = "mdss_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_mdp_clk.c),
@@ -3923,10 +3919,10 @@
static struct branch_clk mdss_mdp_lut_clk = {
.cbcr_reg = MDSS_MDP_LUT_CBCR,
- .parent = &mdp_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mdp_clk_src.c,
.dbg_name = "mdss_mdp_lut_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_mdp_lut_clk.c),
@@ -3935,10 +3931,10 @@
static struct branch_clk mdss_pclk0_clk = {
.cbcr_reg = MDSS_PCLK0_CBCR,
- .parent = &pclk0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &pclk0_clk_src.c,
.dbg_name = "mdss_pclk0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_pclk0_clk.c),
@@ -3947,10 +3943,10 @@
static struct branch_clk mdss_pclk1_clk = {
.cbcr_reg = MDSS_PCLK1_CBCR,
- .parent = &pclk1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &pclk1_clk_src.c,
.dbg_name = "mdss_pclk1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_pclk1_clk.c),
@@ -3959,10 +3955,10 @@
static struct branch_clk mdss_vsync_clk = {
.cbcr_reg = MDSS_VSYNC_CBCR,
- .parent = &vsync_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vsync_clk_src.c,
.dbg_name = "mdss_vsync_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_vsync_clk.c),
@@ -3993,10 +3989,10 @@
static struct branch_clk mmss_mmssnoc_axi_clk = {
.cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mmss_mmssnoc_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mmss_mmssnoc_axi_clk.c),
@@ -4005,11 +4001,11 @@
static struct branch_clk mmss_s0_axi_clk = {
.cbcr_reg = MMSS_S0_AXI_CBCR,
- .parent = &axi_clk_src.c,
/* The bus driver needs set_rate to go through to the parent */
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mmss_s0_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mmss_s0_axi_clk.c),
@@ -4019,11 +4015,11 @@
struct branch_clk ocmemnoc_clk = {
.cbcr_reg = OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 0,
.bcr_reg = 0x50b0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(ocmemnoc_clk.c),
@@ -4032,10 +4028,10 @@
struct branch_clk ocmemcx_ocmemnoc_clk = {
.cbcr_reg = OCMEMCX_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "ocmemcx_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(ocmemcx_ocmemnoc_clk.c),
@@ -4055,10 +4051,10 @@
static struct branch_clk venus0_axi_clk = {
.cbcr_reg = VENUS0_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "venus0_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_axi_clk.c),
@@ -4067,10 +4063,10 @@
static struct branch_clk venus0_ocmemnoc_clk = {
.cbcr_reg = VENUS0_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "venus0_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_ocmemnoc_clk.c),
@@ -4079,10 +4075,10 @@
static struct branch_clk venus0_vcodec0_clk = {
.cbcr_reg = VENUS0_VCODEC0_CBCR,
- .parent = &vcodec0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vcodec0_clk_src.c,
.dbg_name = "venus0_vcodec0_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_vcodec0_clk.c),
@@ -4091,10 +4087,10 @@
static struct branch_clk oxilicx_axi_clk = {
.cbcr_reg = OXILICX_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "oxilicx_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(oxilicx_axi_clk.c),
@@ -4103,9 +4099,9 @@
static struct branch_clk oxili_gfx3d_clk = {
.cbcr_reg = OXILI_GFX3D_CBCR,
- .parent = &oxili_gfx3d_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &oxili_gfx3d_clk_src.c,
.dbg_name = "oxili_gfx3d_clk",
.ops = &clk_ops_branch,
CLK_INIT(oxili_gfx3d_clk.c),
@@ -4145,9 +4141,9 @@
static struct branch_clk audio_core_slimbus_core_clk = {
.cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR,
- .parent = &audio_core_slimbus_core_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_slimbus_core_clk_src.c,
.dbg_name = "audio_core_slimbus_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_slimbus_core_clk.c),
@@ -4293,10 +4289,10 @@
static struct branch_clk audio_core_lpaif_codec_spkr_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR,
- .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.dbg_name = "audio_core_lpaif_codec_spkr_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_codec_spkr_osr_clk.c),
@@ -4316,11 +4312,11 @@
static struct branch_clk audio_core_lpaif_codec_spkr_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR,
- .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.dbg_name = "audio_core_lpaif_codec_spkr_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_codec_spkr_ibit_clk.c),
@@ -4329,10 +4325,10 @@
static struct branch_clk audio_core_lpaif_pri_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_osr_clk.c),
@@ -4352,11 +4348,11 @@
static struct branch_clk audio_core_lpaif_pri_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_ibit_clk.c),
@@ -4365,10 +4361,10 @@
static struct branch_clk audio_core_lpaif_sec_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_osr_clk.c),
@@ -4388,11 +4384,11 @@
static struct branch_clk audio_core_lpaif_sec_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_ibit_clk.c),
@@ -4401,10 +4397,10 @@
static struct branch_clk audio_core_lpaif_ter_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_TER_OSR_CBCR,
- .parent = &audio_core_lpaif_ter_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_ter_clk_src.c,
.dbg_name = "audio_core_lpaif_ter_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_ter_osr_clk.c),
@@ -4424,11 +4420,11 @@
static struct branch_clk audio_core_lpaif_ter_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_TER_IBIT_CBCR,
- .parent = &audio_core_lpaif_ter_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_ter_clk_src.c,
.dbg_name = "audio_core_lpaif_ter_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_ter_ibit_clk.c),
@@ -4437,10 +4433,10 @@
static struct branch_clk audio_core_lpaif_quad_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_QUAD_OSR_CBCR,
- .parent = &audio_core_lpaif_quad_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_quad_clk_src.c,
.dbg_name = "audio_core_lpaif_quad_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_quad_osr_clk.c),
@@ -4460,11 +4456,11 @@
static struct branch_clk audio_core_lpaif_quad_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR,
- .parent = &audio_core_lpaif_quad_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_quad_clk_src.c,
.dbg_name = "audio_core_lpaif_quad_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_quad_ibit_clk.c),
@@ -4484,10 +4480,10 @@
static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm0_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm0_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c),
@@ -4496,10 +4492,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ebit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ebit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ebit_clk.c),
@@ -4508,10 +4504,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c),
@@ -4520,9 +4516,9 @@
struct branch_clk audio_core_lpaif_pcmoe_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR,
- .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.dbg_name = "audio_core_lpaif_pcmoe_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcmoe_clk.c),
@@ -5022,7 +5018,6 @@
CLK_LOOKUP("xo", cxo_clk_src.c, "msm_otg"),
CLK_LOOKUP("xo", cxo_clk_src.c, "pil-q6v5-lpass"),
CLK_LOOKUP("xo", cxo_clk_src.c, "pil-q6v5-mss"),
- CLK_LOOKUP("xo", cxo_clk_src.c, "pil-mba"),
CLK_LOOKUP("xo", cxo_clk_src.c, "fb000000.qcom,wcnss-wlan"),
CLK_LOOKUP("xo", cxo_clk_src.c, "pil_pronto"),
CLK_LOOKUP("measure", measure_clk.c, "debug"),
@@ -5160,10 +5155,10 @@
/* MM sensor clocks */
CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6e.qcom,camera"),
- CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "6c.qcom,camera"),
+ CLK_LOOKUP("cam_src_clk", mclk2_clk_src.c, "6c.qcom,camera"),
CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6e.qcom,camera"),
- CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "6c.qcom,camera"),
+ CLK_LOOKUP("cam_clk", camss_mclk2_clk.c, "6c.qcom,camera"),
CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, ""),
CLK_LOOKUP("cam_clk", camss_mclk2_clk.c, ""),
@@ -5682,11 +5677,9 @@
{
clk_ops_byte = clk_ops_rcg_mnd;
clk_ops_byte.set_rate = set_rate_byte;
- clk_ops_dsi_byte_pll.get_parent = dsi_pll_clk_get_parent;
clk_ops_pixel = clk_ops_rcg;
clk_ops_pixel.set_rate = set_rate_pixel;
- clk_ops_dsi_pixel_pll.get_parent = dsi_pll_clk_get_parent;
mdss_clk_ctrl_init();
}
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 3816b54..2ad425d 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -317,8 +317,8 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_vote,
@@ -328,8 +328,8 @@
static struct pll_clk pll2_clk = {
.mode_reg = MM_PLL1_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 800000000,
.ops = &clk_ops_local_pll,
@@ -339,8 +339,8 @@
static struct pll_clk pll3_clk = {
.mode_reg = MM_PLL2_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 0, /* TODO: Detect rate dynamically */
.ops = &clk_ops_local_pll,
@@ -360,11 +360,6 @@
msm_rpm_set_noirq(MSM_RPM_CTX_SET_0, &iv, 1);
}
-static struct clk *pll4_clk_get_parent(struct clk *c)
-{
- return &pxo_clk.c;
-}
-
static bool pll4_clk_is_local(struct clk *c)
{
return false;
@@ -383,13 +378,13 @@
static struct clk_ops clk_ops_pll4 = {
.enable = pll4_clk_enable,
.disable = pll4_clk_disable,
- .get_parent = pll4_clk_get_parent,
.is_local = pll4_clk_is_local,
.handoff = pll4_clk_handoff,
};
static struct fixed_clk pll4_clk = {
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 540672000,
.ops = &clk_ops_pll4,
@@ -607,7 +602,7 @@
},
.c = {
.dbg_name = "smi_2x_axi_clk",
- .ops = &clk_ops_branch,
+ .ops = &clk_ops_smi_2x,
CLK_INIT(smi_2x_axi_clk.c),
},
};
@@ -1386,8 +1381,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 15,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_xcvr_clk.c),
@@ -1403,8 +1398,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 16,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_sys_clk.c),
@@ -1421,8 +1416,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 12,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_xcvr_clk.c),
@@ -1438,8 +1433,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 13,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_sys_clk.c),
@@ -1454,8 +1449,8 @@
.halt_reg = CLK_HALT_CFPB_STATEC_REG,
.halt_bit = 0,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "ce2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce2_p_clk.c),
@@ -1808,8 +1803,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 14,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "adm0_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm0_clk.c),
@@ -1839,8 +1834,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 12,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "adm1_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm1_clk.c),
@@ -2044,8 +2039,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 13,
},
- .parent = &csi_src_clk.c,
.c = {
+ .parent = &csi_src_clk.c,
.dbg_name = "csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_clk.c),
@@ -2061,8 +2056,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 14,
},
- .parent = &csi_src_clk.c,
.c = {
+ .parent = &csi_src_clk.c,
.dbg_name = "csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_clk.c),
@@ -2566,8 +2561,8 @@
.halt_reg = DBG_BUS_VEC_C_REG,
.halt_bit = 21,
},
- .parent = &pixel_mdp_clk.c,
.c = {
+ .parent = &pixel_mdp_clk.c,
.dbg_name = "pixel_lcdc_clk",
.ops = &clk_ops_branch,
CLK_INIT(pixel_lcdc_clk.c),
@@ -2695,8 +2690,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 8,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -2710,8 +2705,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 9,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -2727,8 +2722,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 11,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "mdp_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_tv_clk.c),
@@ -2744,8 +2739,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 10,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "hdmi_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_tv_clk.c),
@@ -2934,8 +2929,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 7,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi0_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_vfe_clk.c),
@@ -2951,8 +2946,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 8,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi1_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_vfe_clk.c),
@@ -3101,7 +3096,7 @@
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg,
- VDD_DIG_FMAX_MAP1(LOW, 24580000),
+ VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pcm_clk.c),
.rate = ULONG_MAX,
},
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 338361b..fffbcea 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -228,10 +228,10 @@
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll0_clk",
.rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
@@ -259,8 +259,8 @@
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 393216000,
.ops = &clk_ops_pll_vote,
@@ -275,10 +275,10 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
@@ -316,8 +316,8 @@
.en_mask = BIT(11),
.status_reg = BB_PLL14_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll14_clk",
.rate = 480000000,
.ops = &clk_ops_pll_vote,
@@ -767,8 +767,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 8,
},
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_hsio_cal_clk.c),
@@ -1295,8 +1295,8 @@
.halt_check = ENABLE,
.halt_bit = 1,
},
- .parent = &audio_slimbus_clk.c,
.c = {
+ .parent = &audio_slimbus_clk.c,
.dbg_name = "sps_slimbus_clk",
.ops = &clk_ops_branch,
CLK_INIT(sps_slimbus_clk.c),
@@ -1310,8 +1310,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 28,
},
- .parent = &sps_slimbus_clk.c,
.c = {
+ .parent = &sps_slimbus_clk.c,
.dbg_name = "slimbus_xo_src_clk",
.ops = &clk_ops_branch,
CLK_INIT(slimbus_xo_src_clk.c),
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index b9362cf..b284168 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -388,11 +388,11 @@
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG,
.status_reg = (void __iomem *)GPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.soft_vote = &soft_vote_gpll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 600000000,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_acpu_vote,
@@ -420,9 +420,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)LPAPLL_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 393216000,
.dbg_name = "lpapll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -435,9 +435,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)GPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 480000000,
.dbg_name = "gpll1_clk_src",
.ops = &clk_ops_pll_vote,
@@ -988,10 +988,10 @@
static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
@@ -1000,10 +1000,10 @@
static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
- .parent = &blsp1_qup1_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
@@ -1012,10 +1012,10 @@
static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
@@ -1024,10 +1024,10 @@
static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
- .parent = &blsp1_qup2_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
@@ -1036,10 +1036,10 @@
static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
@@ -1048,10 +1048,10 @@
static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
- .parent = &blsp1_qup3_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
@@ -1060,10 +1060,10 @@
static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
@@ -1072,10 +1072,10 @@
static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
- .parent = &blsp1_qup4_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
@@ -1084,10 +1084,10 @@
static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
@@ -1096,10 +1096,10 @@
static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
- .parent = &blsp1_qup5_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
@@ -1108,10 +1108,10 @@
static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
@@ -1120,10 +1120,10 @@
static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
- .parent = &blsp1_qup6_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
@@ -1132,10 +1132,10 @@
static struct branch_clk gcc_blsp1_uart1_apps_clk = {
.cbcr_reg = BLSP1_UART1_APPS_CBCR,
- .parent = &blsp1_uart1_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
@@ -1144,10 +1144,10 @@
static struct branch_clk gcc_blsp1_uart2_apps_clk = {
.cbcr_reg = BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
@@ -1156,10 +1156,10 @@
static struct branch_clk gcc_blsp1_uart3_apps_clk = {
.cbcr_reg = BLSP1_UART3_APPS_CBCR,
- .parent = &blsp1_uart3_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
@@ -1168,10 +1168,10 @@
static struct branch_clk gcc_blsp1_uart4_apps_clk = {
.cbcr_reg = BLSP1_UART4_APPS_CBCR,
- .parent = &blsp1_uart4_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
@@ -1180,10 +1180,10 @@
static struct branch_clk gcc_blsp1_uart5_apps_clk = {
.cbcr_reg = BLSP1_UART5_APPS_CBCR,
- .parent = &blsp1_uart5_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
@@ -1192,10 +1192,10 @@
static struct branch_clk gcc_blsp1_uart6_apps_clk = {
.cbcr_reg = BLSP1_UART6_APPS_CBCR,
- .parent = &blsp1_uart6_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
@@ -1252,10 +1252,10 @@
static struct branch_clk gcc_gp1_clk = {
.cbcr_reg = GP1_CBCR,
- .parent = &gp1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp1_clk_src.c,
.dbg_name = "gcc_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp1_clk.c),
@@ -1264,10 +1264,10 @@
static struct branch_clk gcc_gp2_clk = {
.cbcr_reg = GP2_CBCR,
- .parent = &gp2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp2_clk_src.c,
.dbg_name = "gcc_gp2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp2_clk.c),
@@ -1276,10 +1276,10 @@
static struct branch_clk gcc_gp3_clk = {
.cbcr_reg = GP3_CBCR,
- .parent = &gp3_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp3_clk_src.c,
.dbg_name = "gcc_gp3_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp3_clk.c),
@@ -1288,10 +1288,10 @@
static struct branch_clk gcc_ipa_clk = {
.cbcr_reg = IPA_CBCR,
- .parent = &ipa_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ipa_clk_src.c,
.dbg_name = "gcc_ipa_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_ipa_clk.c),
@@ -1311,10 +1311,10 @@
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
- .parent = &pdm2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &pdm2_clk_src.c,
.dbg_name = "gcc_pdm2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_pdm2_clk.c),
@@ -1357,10 +1357,10 @@
static struct branch_clk gcc_qpic_clk = {
.cbcr_reg = QPIC_CBCR,
- .parent = &qpic_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &qpic_clk_src.c,
.dbg_name = "gcc_qpic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_qpic_clk.c),
@@ -1380,10 +1380,10 @@
static struct branch_clk gcc_sdcc2_apps_clk = {
.cbcr_reg = SDCC2_APPS_CBCR,
- .parent = &sdcc2_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc2_apps_clk_src.c,
.dbg_name = "gcc_sdcc2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc2_apps_clk.c),
@@ -1403,10 +1403,10 @@
static struct branch_clk gcc_sdcc3_apps_clk = {
.cbcr_reg = SDCC3_APPS_CBCR,
- .parent = &sdcc3_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc3_apps_clk_src.c,
.dbg_name = "gcc_sdcc3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc3_apps_clk.c),
@@ -1415,10 +1415,10 @@
static struct branch_clk gcc_sys_noc_ipa_axi_clk = {
.cbcr_reg = SYS_NOC_IPA_AXI_CBCR,
- .parent = &ipa_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ipa_clk_src.c,
.dbg_name = "gcc_sys_noc_ipa_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sys_noc_ipa_axi_clk.c),
@@ -1439,10 +1439,10 @@
static struct branch_clk gcc_usb_hs_system_clk = {
.cbcr_reg = USB_HS_SYSTEM_CBCR,
.bcr_reg = USB_HS_BCR,
- .parent = &usb_hs_system_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hs_system_clk_src.c,
.dbg_name = "gcc_usb_hs_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hs_system_clk.c),
@@ -1462,10 +1462,10 @@
static struct branch_clk gcc_usb_hsic_clk = {
.cbcr_reg = USB_HSIC_CBCR,
- .parent = &usb_hsic_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_clk_src.c,
.dbg_name = "gcc_usb_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_clk.c),
@@ -1474,10 +1474,10 @@
static struct branch_clk gcc_usb_hsic_io_cal_clk = {
.cbcr_reg = USB_HSIC_IO_CAL_CBCR,
- .parent = &usb_hsic_io_cal_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_io_cal_clk_src.c,
.dbg_name = "gcc_usb_hsic_io_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
@@ -1487,10 +1487,10 @@
static struct branch_clk gcc_usb_hsic_system_clk = {
.cbcr_reg = USB_HSIC_SYSTEM_CBCR,
.bcr_reg = USB_HS_HSIC_BCR,
- .parent = &usb_hsic_system_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_system_clk_src.c,
.dbg_name = "gcc_usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_system_clk.c),
@@ -1499,10 +1499,10 @@
static struct branch_clk gcc_usb_hsic_xcvr_fs_clk = {
.cbcr_reg = USB_HSIC_XCVR_FS_CBCR,
- .parent = &usb_hsic_xcvr_fs_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_xcvr_fs_clk_src.c,
.dbg_name = "gcc_usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_xcvr_fs_clk.c),
@@ -1639,9 +1639,9 @@
static struct branch_clk audio_core_lpaif_pcm_data_oe_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR,
- .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm_data_oe_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm_data_oe_clk.c),
@@ -1650,9 +1650,9 @@
static struct branch_clk audio_core_slimbus_core_clk = {
.cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR,
- .parent = &audio_core_slimbus_core_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_slimbus_core_clk_src.c,
.dbg_name = "audio_core_slimbus_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_slimbus_core_clk.c),
@@ -1672,11 +1672,11 @@
static struct branch_clk audio_core_lpaif_pri_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_ibit_clk.c),
@@ -1685,10 +1685,10 @@
static struct branch_clk audio_core_lpaif_pri_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_osr_clk.c),
@@ -1708,10 +1708,10 @@
static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm0_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm0_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c),
@@ -1731,11 +1731,11 @@
static struct branch_clk audio_core_lpaif_sec_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_ibit_clk.c),
@@ -1744,10 +1744,10 @@
static struct branch_clk audio_core_lpaif_sec_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_osr_clk.c),
@@ -1767,10 +1767,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c),
@@ -2027,13 +2027,13 @@
CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "msm_serial_hsl.0"),
- CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "spi_qsd.1"),
+ CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9924000.spi"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
- CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "spi_qsd.1"),
+ CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
- CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
+ CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, "f9924000.spi"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
@@ -2058,6 +2058,7 @@
CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
+ CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
CLK_LOOKUP("core_src_clk", ipa_clk_src.c, "fd4c0000.qcom,ipa"),
CLK_LOOKUP("core_clk", gcc_ipa_clk.c, "fd4c0000.qcom,ipa"),
CLK_LOOKUP("bus_clk", gcc_sys_noc_ipa_axi_clk.c, "fd4c0000.qcom,ipa"),
@@ -2085,10 +2086,15 @@
/* LPASS clocks */
CLK_LOOKUP("core_clk", audio_core_slimbus_core_clk.c, "fe12f000.slim"),
CLK_LOOKUP("iface_clk", audio_core_slimbus_lfabif_clk.c, ""),
- CLK_LOOKUP("core_clk", audio_core_lpaif_pri_clk_src.c, ""),
- CLK_LOOKUP("osr_clk", audio_core_lpaif_pri_osr_clk.c, ""),
- CLK_LOOKUP("ebit_clk", audio_core_lpaif_pri_ebit_clk.c, ""),
- CLK_LOOKUP("ibit_clk", audio_core_lpaif_pri_ibit_clk.c, ""),
+
+ CLK_LOOKUP("core_clk", audio_core_lpaif_pri_clk_src.c,
+ "msm-dai-q6-mi2s.0"),
+ CLK_LOOKUP("osr_clk", audio_core_lpaif_pri_osr_clk.c,
+ "msm-dai-q6-mi2s.0"),
+ CLK_LOOKUP("ebit_clk", audio_core_lpaif_pri_ebit_clk.c,
+ "msm-dai-q6-mi2s.0"),
+ CLK_LOOKUP("ibit_clk", audio_core_lpaif_pri_ibit_clk.c,
+ "msm-dai-q6-mi2s.0"),
CLK_LOOKUP("core_clk", audio_core_lpaif_sec_clk_src.c, ""),
CLK_LOOKUP("osr_clk", audio_core_lpaif_sec_osr_clk.c, ""),
CLK_LOOKUP("ebit_clk", audio_core_lpaif_sec_ebit_clk.c, ""),
@@ -2124,6 +2130,26 @@
CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
CLK_LOOKUP("a5_m_clk", a5_m_clk, ""),
+
+ /* Coresight QDSS clocks */
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
+ CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
+
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc322000.tmc"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc318000.tpiu"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc31c000.replicator"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc307000.tmc"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc31b000.funnel"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc319000.funnel"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc31a000.funnel"),
+ CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc321000.stm"),
+
};
static struct pll_config_regs gpll0_regs __initdata = {
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index d2260cb..4432795 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -527,6 +527,7 @@
* is called to make sure the MNCNTR_EN bit is set correctly.
*/
rcg->current_freq = nf;
+ c->parent = nf->src_clk;
/* Enable any clocks that were disabled. */
if (!rcg->bank_info) {
@@ -583,11 +584,6 @@
return (rcg->freq_tbl + n)->freq_hz;
}
-static struct clk *rcg_clk_get_parent(struct clk *c)
-{
- return to_rcg_clk(c)->current_freq->src_clk;
-}
-
/* Disable hw clock gating if not set at boot */
enum handoff branch_handoff(struct branch *b, struct clk *c)
{
@@ -644,6 +640,7 @@
return HANDOFF_UNKNOWN_RATE;
rcg->current_freq = freq;
+ c->parent = freq->src_clk;
c->rate = freq->freq_hz;
return HANDOFF_ENABLED_CLK;
@@ -683,11 +680,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static struct clk *branch_clk_get_parent(struct clk *c)
-{
- return to_branch_clk(c)->parent;
-}
-
static int branch_clk_is_enabled(struct clk *c)
{
return to_branch_clk(c)->enabled;
@@ -834,11 +826,17 @@
.in_hwcg_mode = branch_clk_in_hwcg_mode,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
- .get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
.set_flags = branch_clk_set_flags,
};
+struct clk_ops clk_ops_smi_2x = {
+ .prepare = branch_clk_enable,
+ .unprepare = branch_clk_disable,
+ .is_enabled = branch_clk_is_enabled,
+ .handoff = branch_clk_handoff,
+};
+
struct clk_ops clk_ops_reset = {
.reset = branch_clk_reset,
};
@@ -862,7 +860,6 @@
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
- .get_parent = rcg_clk_get_parent,
.set_flags = rcg_clk_set_flags,
};
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index 1873343..ff6dc69 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -153,6 +153,7 @@
};
extern struct clk_ops clk_ops_branch;
+extern struct clk_ops clk_ops_smi_2x;
extern struct clk_ops clk_ops_reset;
int branch_reset(struct branch *b, enum clk_reset_action action);
@@ -234,7 +235,6 @@
* struct branch_clk - branch
* @enabled: true if clock is on, false otherwise
* @b: branch
- * @parent: clock source
* @c: clock
*
* An on/off switch with a rate derived from the parent.
@@ -242,7 +242,6 @@
struct branch_clk {
bool enabled;
struct branch b;
- struct clk *parent;
struct clk c;
};
diff --git a/arch/arm/mach-msm/clock-local2.c b/arch/arm/mach-msm/clock-local2.c
index b9c3036..5923951 100644
--- a/arch/arm/mach-msm/clock-local2.c
+++ b/arch/arm/mach-msm/clock-local2.c
@@ -206,6 +206,7 @@
clk_unprepare(cf->src_clk);
rcg->current_freq = nf;
+ c->parent = nf->src_clk;
return 0;
}
@@ -234,11 +235,6 @@
return (rcg->freq_tbl + n)->freq_hz;
}
-static struct clk *rcg_clk_get_parent(struct clk *c)
-{
- return to_rcg_clk(c)->current_freq->src_clk;
-}
-
static enum handoff _rcg_clk_handoff(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
@@ -306,6 +302,7 @@
return HANDOFF_UNKNOWN_RATE;
rcg->current_freq = freq;
+ rcg->c.parent = freq->src_clk;
rcg->c.rate = freq->freq_hz;
return HANDOFF_ENABLED_CLK;
@@ -431,7 +428,7 @@
return branch_cdiv_set_rate(branch, rate);
if (!branch->has_sibling)
- return clk_set_rate(branch->parent, rate);
+ return clk_set_rate(c->parent, rate);
return -EPERM;
}
@@ -444,7 +441,7 @@
return rate <= (branch->max_div) ? rate : -EPERM;
if (!branch->has_sibling)
- return clk_round_rate(branch->parent, rate);
+ return clk_round_rate(c->parent, rate);
return -EPERM;
}
@@ -457,16 +454,11 @@
return branch->c.rate;
if (!branch->has_sibling)
- return clk_get_rate(branch->parent);
+ return clk_get_rate(c->parent);
return 0;
}
-static struct clk *branch_clk_get_parent(struct clk *c)
-{
- return to_branch_clk(c)->parent;
-}
-
static int branch_clk_list_rate(struct clk *c, unsigned n)
{
struct branch_clk *branch = to_branch_clk(c);
@@ -474,8 +466,8 @@
if (branch->has_sibling == 1)
return -ENXIO;
- if (branch->parent && branch->parent->ops->list_rate)
- return branch->parent->ops->list_rate(branch->parent, n);
+ if (c->parent && c->parent->ops->list_rate)
+ return c->parent->ops->list_rate(c->parent, n);
else
return -ENXIO;
}
@@ -489,9 +481,9 @@
if ((cbcr_regval & CBCR_BRANCH_OFF_BIT))
return HANDOFF_DISABLED_CLK;
- if (branch->parent) {
- if (branch->parent->ops->handoff)
- return branch->parent->ops->handoff(branch->parent);
+ if (c->parent) {
+ if (c->parent->ops->handoff)
+ return c->parent->ops->handoff(c->parent);
}
return HANDOFF_ENABLED_CLK;
@@ -603,7 +595,6 @@
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.round_rate = rcg_clk_round_rate,
- .get_parent = rcg_clk_get_parent,
.handoff = rcg_clk_handoff,
};
@@ -612,7 +603,6 @@
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.round_rate = rcg_clk_round_rate,
- .get_parent = rcg_clk_get_parent,
.handoff = rcg_mnd_clk_handoff,
};
@@ -624,7 +614,6 @@
.list_rate = branch_clk_list_rate,
.round_rate = branch_clk_round_rate,
.reset = branch_clk_reset,
- .get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
};
diff --git a/arch/arm/mach-msm/clock-local2.h b/arch/arm/mach-msm/clock-local2.h
index 101dc2d..a6d2ed6 100644
--- a/arch/arm/mach-msm/clock-local2.h
+++ b/arch/arm/mach-msm/clock-local2.h
@@ -87,7 +87,6 @@
/**
* struct branch_clk - branch clock
* @set_rate: Set the frequency of this branch clock.
- * @parent: clock source
* @c: clk
* @cbcr_reg: branch control register
* @bcr_reg: block reset register
@@ -99,7 +98,6 @@
*/
struct branch_clk {
void (*set_rate)(struct branch_clk *, struct clk_freq_tbl *);
- struct clk *parent;
struct clk c;
const u32 cbcr_reg;
const u32 bcr_reg;
diff --git a/arch/arm/mach-msm/clock-mdss-8974.c b/arch/arm/mach-msm/clock-mdss-8974.c
index 1603c93..e7a596d 100644
--- a/arch/arm/mach-msm/clock-mdss-8974.c
+++ b/arch/arm/mach-msm/clock-mdss-8974.c
@@ -67,7 +67,6 @@
static int pll_byte_clk_rate;
static int pll_pclk_rate;
static int pll_initialized;
-static int pll_enabled;
static struct clk *mdss_dsi_ahb_clk;
static unsigned long dsi_pll_rate;
@@ -208,15 +207,12 @@
return 0;
}
-static int mdss_dsi_pll_enable(struct clk *c)
+static int __mdss_dsi_pll_enable(struct clk *c)
{
u32 status;
u32 max_reads, timeout_us;
int i;
- if (pll_enabled)
- return 0;
-
if (!pll_initialized) {
if (dsi_pll_rate)
mdss_dsi_pll_byte_set_rate(c, dsi_pll_rate);
@@ -266,12 +262,11 @@
pr_debug("%s: **** PLL Lock success\n", __func__);
clk_disable(mdss_dsi_ahb_clk);
- pll_enabled = 1;
return 0;
}
-static void mdss_dsi_pll_disable(struct clk *c)
+static void __mdss_dsi_pll_disable(void)
{
if (!mdss_dsi_ahb_clk)
pr_err("%s: mdss_dsi_ahb_clk not initialized\n",
@@ -282,7 +277,40 @@
clk_disable(mdss_dsi_ahb_clk);
pr_debug("%s: **** disable pll Initialize\n", __func__);
pll_initialized = 0;
- pll_enabled = 0;
+}
+
+static DEFINE_SPINLOCK(dsipll_lock);
+static int dsipll_refcount;
+
+static void mdss_dsi_pll_disable(struct clk *c)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dsipll_lock, flags);
+ if (WARN(dsipll_refcount == 0, "DSI PLL clock is unbalanced"))
+ goto out;
+ if (dsipll_refcount == 1)
+ __mdss_dsi_pll_disable();
+ dsipll_refcount--;
+out:
+ spin_unlock_irqrestore(&dsipll_lock, flags);
+}
+
+static int mdss_dsi_pll_enable(struct clk *c)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&dsipll_lock, flags);
+ if (dsipll_refcount == 0) {
+ ret = __mdss_dsi_pll_enable(c);
+ if (ret < 0)
+ goto out;
+ }
+ dsipll_refcount++;
+out:
+ spin_unlock_irqrestore(&dsipll_lock, flags);
+ return ret;
}
void hdmi_pll_disable(void)
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 240f4e4..8e11d37 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -98,11 +98,6 @@
spin_unlock_irqrestore(&pll_reg_lock, flags);
}
-static struct clk *pll_vote_clk_get_parent(struct clk *c)
-{
- return to_pll_vote_clk(c)->parent;
-}
-
static int pll_vote_clk_is_enabled(struct clk *c)
{
struct pll_vote_clk *pllv = to_pll_vote_clk(c);
@@ -122,7 +117,6 @@
.enable = pll_vote_clk_enable,
.disable = pll_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
.handoff = pll_vote_clk_handoff,
};
@@ -229,11 +223,6 @@
return HANDOFF_DISABLED_CLK;
}
-static struct clk *local_pll_clk_get_parent(struct clk *c)
-{
- return to_pll_clk(c)->parent;
-}
-
static int local_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
struct pll_freq_tbl *nf;
@@ -346,7 +335,6 @@
.disable = local_pll_clk_disable,
.set_rate = local_pll_clk_set_rate,
.handoff = local_pll_clk_handoff,
- .get_parent = local_pll_clk_get_parent,
};
struct pll_rate {
@@ -537,7 +525,6 @@
.enable = pll_acpu_vote_clk_enable,
.disable = pll_acpu_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
};
static void __init __set_fsm_mode(void __iomem *mode_reg,
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index 33b35a8..cb334d7 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -35,7 +35,6 @@
* any HW voting
* @id: PLL ID
* @mode_reg: enable register
- * @parent: clock source
* @c: clock
*/
struct pll_shared_clk {
@@ -104,7 +103,6 @@
* @en_mask: ORed with @en_reg to enable the clock
* @status_mask: ANDed with @status_reg to determine if PLL is active.
* @status_reg: status register
- * @parent: clock source
* @c: clock
*/
struct pll_vote_clk {
@@ -115,7 +113,6 @@
void __iomem *const status_reg;
const u32 status_mask;
- struct clk *parent;
struct clk c;
void *const __iomem *base;
};
@@ -144,7 +141,6 @@
* @status_reg: status register, contains the lock detection bit
* @masks: masks used for settings in config_reg
* @freq_tbl: pll freq table
- * @parent: clock source
* @c: clk
* @base: pointer to base address of ioremapped registers.
*/
@@ -159,7 +155,6 @@
struct pll_config_masks masks;
struct pll_freq_tbl *freq_tbl;
- struct clk *parent;
struct clk c;
void *const __iomem *base;
};
diff --git a/arch/arm/mach-msm/clock-rpm.c b/arch/arm/mach-msm/clock-rpm.c
index daf83e2..63e67b3 100644
--- a/arch/arm/mach-msm/clock-rpm.c
+++ b/arch/arm/mach-msm/clock-rpm.c
@@ -12,37 +12,29 @@
*/
#include <linux/err.h>
+#include <linux/mutex.h>
#include <mach/clk-provider.h>
#include "rpm_resources.h"
#include "clock-rpm.h"
-#define __clk_rpmrs_set_rate(r, value, ctx, noirq) \
- ((r)->rpmrs_data->set_rate_fn((r), (value), (ctx), (noirq)))
+#define __clk_rpmrs_set_rate(r, value, ctx) \
+ ((r)->rpmrs_data->set_rate_fn((r), (value), (ctx)))
#define clk_rpmrs_set_rate_sleep(r, value) \
- __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_sleep_id, 0)
-
-#define clk_rpmrs_set_rate_sleep_noirq(r, value) \
- __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_sleep_id, 1)
+ __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_sleep_id)
#define clk_rpmrs_set_rate_active(r, value) \
- __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_active_id, 0)
-
-#define clk_rpmrs_set_rate_active_noirq(r, value) \
- __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_active_id, 1)
+ __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_active_id)
static int clk_rpmrs_set_rate(struct rpm_clk *r, uint32_t value,
- uint32_t context, int noirq)
+ uint32_t context)
{
struct msm_rpm_iv_pair iv = {
.id = r->rpm_clk_id,
.value = value,
};
- if (noirq)
- return msm_rpmrs_set_noirq(context, &iv, 1);
- else
- return msm_rpmrs_set(context, &iv, 1);
+ return msm_rpmrs_set(context, &iv, 1);
}
static int clk_rpmrs_get_rate(struct rpm_clk *r)
@@ -72,7 +64,7 @@
}
static int clk_rpmrs_set_rate_smd(struct rpm_clk *r, uint32_t value,
- uint32_t context, int noirq)
+ uint32_t context)
{
struct msm_rpm_kvp kvp = {
.key = r->rpm_key,
@@ -80,12 +72,8 @@
.length = sizeof(value),
};
- if (noirq)
- return msm_rpm_send_message_noirq(context,
- r->rpm_res_type, r->rpm_clk_id, &kvp, 1);
- else
- return msm_rpm_send_message(context, r->rpm_res_type,
- r->rpm_clk_id, &kvp, 1);
+ return msm_rpm_send_message(context, r->rpm_res_type, r->rpm_clk_id,
+ &kvp, 1);
}
static int clk_rpmrs_handoff_smd(struct rpm_clk *r)
@@ -94,8 +82,7 @@
}
struct clk_rpmrs_data {
- int (*set_rate_fn)(struct rpm_clk *r, uint32_t value,
- uint32_t context, int noirq);
+ int (*set_rate_fn)(struct rpm_clk *r, uint32_t value, uint32_t context);
int (*get_rate_fn)(struct rpm_clk *r);
int (*handoff_fn)(struct rpm_clk *r);
int ctx_active_id;
@@ -117,11 +104,10 @@
.ctx_sleep_id = MSM_RPM_CTX_SLEEP_SET,
};
-static DEFINE_SPINLOCK(rpm_clock_lock);
+static DEFINE_MUTEX(rpm_clock_lock);
-static int rpm_clk_enable(struct clk *clk)
+static int rpm_clk_prepare(struct clk *clk)
{
- unsigned long flags;
struct rpm_clk *r = to_rpm_clk(clk);
uint32_t value;
int rc = 0;
@@ -129,7 +115,7 @@
unsigned long peer_khz = 0, peer_sleep_khz = 0;
struct rpm_clk *peer = r->peer;
- spin_lock_irqsave(&rpm_clock_lock, flags);
+ mutex_lock(&rpm_clock_lock);
this_khz = r->last_set_khz;
/* Don't send requests to the RPM if the rate has not been set. */
@@ -148,7 +134,7 @@
if (r->branch)
value = !!value;
- rc = clk_rpmrs_set_rate_active_noirq(r, value);
+ rc = clk_rpmrs_set_rate_active(r, value);
if (rc)
goto out;
@@ -156,28 +142,27 @@
if (r->branch)
value = !!value;
- rc = clk_rpmrs_set_rate_sleep_noirq(r, value);
+ rc = clk_rpmrs_set_rate_sleep(r, value);
if (rc) {
/* Undo the active set vote and restore it to peer_khz */
value = peer_khz;
- rc = clk_rpmrs_set_rate_active_noirq(r, value);
+ rc = clk_rpmrs_set_rate_active(r, value);
}
out:
if (!rc)
r->enabled = true;
- spin_unlock_irqrestore(&rpm_clock_lock, flags);
+ mutex_unlock(&rpm_clock_lock);
return rc;
}
-static void rpm_clk_disable(struct clk *clk)
+static void rpm_clk_unprepare(struct clk *clk)
{
- unsigned long flags;
struct rpm_clk *r = to_rpm_clk(clk);
- spin_lock_irqsave(&rpm_clock_lock, flags);
+ mutex_lock(&rpm_clock_lock);
if (r->last_set_khz) {
uint32_t value;
@@ -192,30 +177,29 @@
}
value = r->branch ? !!peer_khz : peer_khz;
- rc = clk_rpmrs_set_rate_active_noirq(r, value);
+ rc = clk_rpmrs_set_rate_active(r, value);
if (rc)
goto out;
value = r->branch ? !!peer_sleep_khz : peer_sleep_khz;
- rc = clk_rpmrs_set_rate_sleep_noirq(r, value);
+ rc = clk_rpmrs_set_rate_sleep(r, value);
}
r->enabled = false;
out:
- spin_unlock_irqrestore(&rpm_clock_lock, flags);
+ mutex_unlock(&rpm_clock_lock);
return;
}
static int rpm_clk_set_rate(struct clk *clk, unsigned long rate)
{
- unsigned long flags;
struct rpm_clk *r = to_rpm_clk(clk);
unsigned long this_khz, this_sleep_khz;
int rc = 0;
this_khz = DIV_ROUND_UP(rate, r->factor);
- spin_lock_irqsave(&rpm_clock_lock, flags);
+ mutex_lock(&rpm_clock_lock);
/* Active-only clocks don't care what the rate is during sleep. So,
* they vote for zero. */
@@ -236,12 +220,12 @@
}
value = max(this_khz, peer_khz);
- rc = clk_rpmrs_set_rate_active_noirq(r, value);
+ rc = clk_rpmrs_set_rate_active(r, value);
if (rc)
goto out;
value = max(this_sleep_khz, peer_sleep_khz);
- rc = clk_rpmrs_set_rate_sleep_noirq(r, value);
+ rc = clk_rpmrs_set_rate_sleep(r, value);
}
if (!rc) {
r->last_set_khz = this_khz;
@@ -249,7 +233,7 @@
}
out:
- spin_unlock_irqrestore(&rpm_clock_lock, flags);
+ mutex_unlock(&rpm_clock_lock);
return rc;
}
@@ -319,8 +303,8 @@
}
struct clk_ops clk_ops_rpm = {
- .enable = rpm_clk_enable,
- .disable = rpm_clk_disable,
+ .prepare = rpm_clk_prepare,
+ .unprepare = rpm_clk_unprepare,
.set_rate = rpm_clk_set_rate,
.get_rate = rpm_clk_get_rate,
.is_enabled = rpm_clk_is_enabled,
@@ -330,8 +314,8 @@
};
struct clk_ops clk_ops_rpm_branch = {
- .enable = rpm_clk_enable,
- .disable = rpm_clk_disable,
+ .prepare = rpm_clk_prepare,
+ .unprepare = rpm_clk_unprepare,
.is_local = rpm_clk_is_local,
.handoff = rpm_clk_handoff,
};
diff --git a/arch/arm/mach-msm/clock-voter.c b/arch/arm/mach-msm/clock-voter.c
index fa170bf4..7421ba6 100644
--- a/arch/arm/mach-msm/clock-voter.c
+++ b/arch/arm/mach-msm/clock-voter.c
@@ -43,7 +43,7 @@
mutex_lock(&voter_clk_lock);
if (v->enabled) {
- struct clk *parent = v->parent;
+ struct clk *parent = clk->parent;
/*
* Get the aggregate rate without this clock's vote and update
@@ -79,7 +79,7 @@
struct clk_voter *v = to_clk_voter(clk);
mutex_lock(&voter_clk_lock);
- parent = v->parent;
+ parent = clk->parent;
/*
* Increase the rate if this clock is voting for a higher rate
@@ -105,7 +105,7 @@
struct clk_voter *v = to_clk_voter(clk);
mutex_lock(&voter_clk_lock);
- parent = v->parent;
+ parent = clk->parent;
/*
* Decrease the rate if this clock was the only one voting for
@@ -129,14 +129,7 @@
static long voter_clk_round_rate(struct clk *clk, unsigned long rate)
{
- struct clk_voter *v = to_clk_voter(clk);
- return clk_round_rate(v->parent, rate);
-}
-
-static struct clk *voter_clk_get_parent(struct clk *clk)
-{
- struct clk_voter *v = to_clk_voter(clk);
- return v->parent;
+ return clk_round_rate(clk->parent, rate);
}
static bool voter_clk_is_local(struct clk *clk)
@@ -159,7 +152,6 @@
.set_rate = voter_clk_set_rate,
.is_enabled = voter_clk_is_enabled,
.round_rate = voter_clk_round_rate,
- .get_parent = voter_clk_get_parent,
.is_local = voter_clk_is_local,
.handoff = voter_clk_handoff,
};
diff --git a/arch/arm/mach-msm/clock-voter.h b/arch/arm/mach-msm/clock-voter.h
index 82c071b..eb55a12 100644
--- a/arch/arm/mach-msm/clock-voter.h
+++ b/arch/arm/mach-msm/clock-voter.h
@@ -21,7 +21,6 @@
struct clk_voter {
bool enabled;
- struct clk *parent;
struct clk c;
};
@@ -32,8 +31,8 @@
#define DEFINE_CLK_VOTER(clk_name, _parent, _default_rate) \
struct clk_voter clk_name = { \
- .parent = _parent, \
.c = { \
+ .parent = _parent, \
.dbg_name = #clk_name, \
.ops = &clk_ops_voter, \
.rate = _default_rate, \
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index e9dd974..c2bf5ba 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -163,7 +163,7 @@
mutex_lock(&clk->prepare_lock);
if (clk->prepare_count == 0) {
- parent = clk_get_parent(clk);
+ parent = clk->parent;
ret = clk_prepare(parent);
if (ret)
@@ -213,7 +213,7 @@
WARN(!clk->prepare_count,
"%s: Don't call enable on unprepared clocks\n", name);
if (clk->count == 0) {
- parent = clk_get_parent(clk);
+ parent = clk->parent;
ret = clk_enable(parent);
if (ret)
@@ -258,7 +258,7 @@
if (WARN(clk->count == 0, "%s is unbalanced", name))
goto out;
if (clk->count == 1) {
- struct clk *parent = clk_get_parent(clk);
+ struct clk *parent = clk->parent;
trace_clock_disable(name, 0, smp_processor_id());
if (clk->ops->disable)
@@ -283,7 +283,7 @@
if (WARN(!clk->prepare_count, "%s is unbalanced (prepare)", name))
goto out;
if (clk->prepare_count == 1) {
- struct clk *parent = clk_get_parent(clk);
+ struct clk *parent = clk->parent;
WARN(clk->count,
"%s: Don't call unprepare when the clock is enabled\n",
@@ -411,10 +411,7 @@
if (IS_ERR_OR_NULL(clk))
return NULL;
- if (!clk->ops->get_parent)
- return NULL;
-
- return clk->ops->get_parent(clk);
+ return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
@@ -438,7 +435,7 @@
for (n = 0; n < num_clocks; n++) {
clk = clock_tbl[n].clk;
- parent = clk_get_parent(clk);
+ parent = clk->parent;
if (parent && list_empty(&clk->siblings))
list_add(&clk->siblings, &parent->children);
}
@@ -492,11 +489,11 @@
/*
* Handoff functions for children must be called before their parents'
- * so that the correct parent is returned by the clk_get_parent() below.
+ * so that the correct parent is available below.
*/
ret = clk->ops->handoff(clk);
if (ret == HANDOFF_ENABLED_CLK) {
- ret = __handoff_clk(clk_get_parent(clk));
+ ret = __handoff_clk(clk->parent);
if (ret == HANDOFF_ENABLED_CLK) {
h = kmalloc(sizeof(*h), GFP_KERNEL);
if (!h) {
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 6c9b413..e0d98b7 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -52,8 +52,11 @@
static int set_cpu_freq(struct cpufreq_policy *policy, unsigned int new_freq)
{
int ret = 0;
+ int saved_sched_policy = -EINVAL;
+ int saved_sched_rt_prio = -EINVAL;
struct cpufreq_freqs freqs;
struct cpu_freq *limit = &per_cpu(cpu_freq_info, policy->cpu);
+ struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
if (limit->limits_init) {
if (new_freq > limit->allowed_max) {
@@ -70,11 +73,29 @@
freqs.old = policy->cur;
freqs.new = new_freq;
freqs.cpu = policy->cpu;
+
+ /*
+ * Put the caller into SCHED_FIFO priority to avoid cpu starvation
+ * in the acpuclk_set_rate path while increasing frequencies
+ */
+
+ if (freqs.new > freqs.old && current->policy != SCHED_FIFO) {
+ saved_sched_policy = current->policy;
+ saved_sched_rt_prio = current->rt_priority;
+ sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m);
+ }
+
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
ret = acpuclk_set_rate(policy->cpu, new_freq, SETRATE_CPUFREQ);
if (!ret)
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ /* Restore priority after clock ramp-up */
+ if (freqs.new > freqs.old && saved_sched_policy >= 0) {
+ param.sched_priority = saved_sched_rt_prio;
+ sched_setscheduler_nocheck(current, saved_sched_policy, ¶m);
+ }
return ret;
}
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index fbfa036..14edbcf 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -1103,10 +1103,10 @@
.flags = IORESOURCE_IRQ,
},
{
- .start = 47,
- .end = 47,
+ .start = MSM_GPIO_TO_INT(47),
+ .end = MSM_GPIO_TO_INT(47),
.name = "wakeup",
- .flags = IORESOURCE_IO,
+ .flags = IORESOURCE_IRQ,
},
};
@@ -1874,7 +1874,7 @@
},
{
.irq_config_id = SMD_Q6,
- .subsys_name = "q6",
+ .subsys_name = "adsp",
.edge = SMD_APPS_QDSP,
.smd_int.irq_name = "adsp_a11",
@@ -2020,6 +2020,11 @@
.flags = IORESOURCE_MEM,
},
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = GSS_A5_WDOG_EXPIRED,
.end = GSS_A5_WDOG_EXPIRED,
.flags = IORESOURCE_IRQ,
@@ -2396,16 +2401,28 @@
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
- .phys_addr_base = 0x0010DD04,
- .phys_size = SZ_256,
+ .version = 1,
};
+
+static struct resource msm_rpm_stat_resource[] = {
+ {
+ .start = 0x0010D204,
+ .end = 0x0010D204 + SZ_8K,
+ .flags = IORESOURCE_MEM,
+ .name = "phys_addr_base"
+ },
+};
+
+
struct platform_device apq8064_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
- .dev = {
+ .resource = msm_rpm_stat_resource,
+ .num_resources = ARRAY_SIZE(msm_rpm_stat_resource),
+ .dev = {
.platform_data = &msm_rpm_stat_pdata,
- },
+ }
};
static struct resource resources_rpm_master_stats[] = {
@@ -2709,18 +2726,26 @@
.resource = i2s_mdm_resources,
};
-static struct msm_dcvs_freq_entry apq8064_freq[] = {
- { 384000, 900, 0, 0, 0},
- { 594000, 950, 0, 0, 0},
- { 702000, 975, 0, 0, 0},
- {1026000, 1075, 0, 0, 0},
- {1242000, 1150, 0, 100, 100},
- {1458000, 1188, 0, 100, 100},
- {1512000, 1200, 1, 100, 100},
+static struct msm_dcvs_sync_rule apq8064_dcvs_sync_rules[] = {
+ {1026000, 400000},
+ {384000, 200000},
+ {0, 128000},
+};
+
+static struct msm_dcvs_platform_data apq8064_dcvs_data = {
+ .sync_rules = apq8064_dcvs_sync_rules,
+ .num_sync_rules = ARRAY_SIZE(apq8064_dcvs_sync_rules),
+};
+
+struct platform_device apq8064_dcvs_device = {
+ .name = "dcvs",
+ .id = -1,
+ .dev = {
+ .platform_data = &apq8064_dcvs_data,
+ },
};
static struct msm_dcvs_core_info apq8064_core_info = {
- .freq_tbl = &apq8064_freq[0],
.num_cores = 4,
.sensors = (int[]){7, 8, 9, 10},
.thermal_poll_ms = 60000,
@@ -2755,7 +2780,7 @@
},
.power_param = {
.current_temp = 25,
- .num_freq = ARRAY_SIZE(apq8064_freq),
+ .num_freq = 0, /* set at runtime */
}
};
diff --git a/arch/arm/mach-msm/devices-8930.c b/arch/arm/mach-msm/devices-8930.c
index 322347b..0faf500 100644
--- a/arch/arm/mach-msm/devices-8930.c
+++ b/arch/arm/mach-msm/devices-8930.c
@@ -547,16 +547,28 @@
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
- .phys_addr_base = 0x0010DD04,
- .phys_size = SZ_256,
+ .version = 1,
};
+static struct resource msm_rpm_stat_resource[] = {
+ {
+ .start = 0x0010D204,
+ .end = 0x0010D204 + SZ_8K,
+ .flags = IORESOURCE_MEM,
+ .name = "phys_addr_base"
+
+ },
+};
+
+
struct platform_device msm8930_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
- .dev = {
+ .resource = msm_rpm_stat_resource,
+ .num_resources = ARRAY_SIZE(msm_rpm_stat_resource),
+ .dev = {
.platform_data = &msm_rpm_stat_pdata,
- },
+ }
};
static struct resource resources_rpm_master_stats[] = {
@@ -657,6 +669,18 @@
.id = -1,
};
+static struct acpuclk_platform_data acpuclk_8930ab_pdata = {
+ .uses_pm8917 = false,
+};
+
+struct platform_device msm8930ab_device_acpuclk = {
+ .name = "acpuclk-8930ab",
+ .id = -1,
+ .dev = {
+ .platform_data = &acpuclk_8930ab_pdata,
+ },
+};
+
static struct fs_driver_data gfx3d_fs_data = {
.clks = (struct fs_clk_data[]){
{ .name = "core_clk", .reset_rate = 27000000 },
@@ -693,6 +717,20 @@
.bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
};
+static struct fs_driver_data mdp_fs_data_8930_pm8917 = {
+ .clks = (struct fs_clk_data[]){
+ { .name = "core_clk" },
+ { .name = "iface_clk" },
+ { .name = "bus_clk" },
+ { .name = "vsync_clk" },
+ { .name = "lut_clk" },
+ { .name = "reset1_clk" },
+ { 0 }
+ },
+ .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
+ .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
+};
+
static struct fs_driver_data mdp_fs_data_8627 = {
.clks = (struct fs_clk_data[]){
{ .name = "core_clk" },
@@ -759,6 +797,18 @@
};
unsigned msm8930_num_footswitch __initdata = ARRAY_SIZE(msm8930_footswitch);
+struct platform_device *msm8930_pm8917_footswitch[] __initdata = {
+ FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8930_pm8917),
+ FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
+ FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
+ FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
+ FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
+ FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
+ FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
+};
+unsigned msm8930_pm8917_num_footswitch __initdata =
+ ARRAY_SIZE(msm8930_pm8917_footswitch);
+
struct platform_device *msm8627_footswitch[] __initdata = {
FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8627),
FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index f8132b4..a839fcf 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -1373,6 +1373,11 @@
.flags = IORESOURCE_MEM,
},
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = 0x08B00000,
.end = 0x08B00000 + SZ_256 - 1,
.flags = IORESOURCE_MEM,
@@ -1412,7 +1417,6 @@
.aclk_reg = MSM_CLK_CTL_BASE + 0x2C6C,
.jtag_clk_reg = MSM_CLK_CTL_BASE + 0x2044,
.name = "modem_fw",
- .depends = "q6",
.pas_id = PAS_MODEM_FW,
.bus_port = MSM_BUS_MASTER_MSS_FW_PROC,
},
@@ -1423,7 +1427,6 @@
.aclk_reg = MSM_CLK_CTL_BASE + 0x2040,
.jtag_clk_reg = MSM_CLK_CTL_BASE + 0x2C68,
.name = "modem",
- .depends = "modem_fw",
.pas_id = PAS_MODEM_SW,
.bus_port = MSM_BUS_MASTER_MSS_SW_PROC,
}
@@ -1444,6 +1447,11 @@
.flags = IORESOURCE_MEM,
},
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ,
.end = RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ,
.flags = IORESOURCE_IRQ,
@@ -1464,6 +1472,11 @@
static struct resource msm_pil_dsps_resources[] = {
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = PPSS_WDOG_TIMER_IRQ,
.end = PPSS_WDOG_TIMER_IRQ,
.flags = IORESOURCE_IRQ,
@@ -1557,7 +1570,7 @@
},
{
.irq_config_id = SMD_Q6,
- .subsys_name = "q6",
+ .subsys_name = "adsp",
.edge = SMD_APPS_QDSP,
.smd_int.irq_name = "adsp_a11",
@@ -2520,6 +2533,17 @@
.bus_port1 = MSM_BUS_MASTER_HD_CODEC_PORT1,
};
+static struct fs_driver_data ved_fs_data_8960ab = {
+ .clks = (struct fs_clk_data[]){
+ { .name = "core_clk" },
+ { .name = "iface_clk" },
+ { .name = "bus_clk" },
+ { 0 }
+ },
+ .bus_port0 = MSM_BUS_MASTER_VIDEO_DEC,
+ .bus_port1 = MSM_BUS_MASTER_VIDEO_ENC,
+};
+
static struct fs_driver_data vfe_fs_data = {
.clks = (struct fs_clk_data[]){
{ .name = "core_clk" },
@@ -2560,7 +2584,7 @@
FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
- FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
+ FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data_8960ab),
};
unsigned msm8960ab_num_footswitch __initdata = ARRAY_SIZE(msm8960ab_footswitch);
@@ -3760,16 +3784,28 @@
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
- .phys_addr_base = 0x0010DD04,
- .phys_size = SZ_256,
+ .version = 1,
};
+static struct resource msm_rpm_stat_resource[] = {
+ {
+ .start = 0x0010D204,
+ .end = 0x0010D204 + SZ_8K,
+ .flags = IORESOURCE_MEM,
+ .name = "phys_addr_base"
+ },
+};
+
+
+
struct platform_device msm8960_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
- .dev = {
+ .resource = msm_rpm_stat_resource,
+ .num_resources = ARRAY_SIZE(msm_rpm_stat_resource),
+ .dev = {
.platform_data = &msm_rpm_stat_pdata,
- },
+ }
};
static struct resource resources_rpm_master_stats[] = {
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index fe3a4d5..e55e9a7 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -562,6 +562,21 @@
.id = -1,
};
+struct platform_device msm_cpudai_incall_music_rx = {
+ .name = "msm-dai-q6",
+ .id = 0x8005,
+};
+
+struct platform_device msm_cpudai_incall_record_rx = {
+ .name = "msm-dai-q6",
+ .id = 0x8004,
+};
+
+struct platform_device msm_cpudai_incall_record_tx = {
+ .name = "msm-dai-q6",
+ .id = 0x8003,
+};
+
struct platform_device msm_i2s_cpudai0 = {
.name = "msm-dai-q6",
.id = PRIMARY_I2S_RX,
@@ -584,6 +599,14 @@
.name = "msm-voip-dsp",
.id = -1,
};
+struct platform_device msm_cpudai_stub = {
+ .name = "msm-dai-stub",
+ .id = -1,
+};
+struct platform_device msm_dtmf = {
+ .name = "msm-pcm-dtmf",
+ .id = -1,
+};
struct platform_device msm_compr_dsp = {
.name = "msm-compr-dsp",
@@ -1361,16 +1384,29 @@
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
- .phys_addr_base = 0x0010DD04,
- .phys_size = SZ_256,
+ .version = 1,
};
+
+static struct resource msm_rpm_stat_resource[] = {
+ {
+ .start = 0x0010D204,
+ .end = 0x0010D204 + SZ_8K,
+ .flags = IORESOURCE_MEM,
+ .name = "phys_addr_base"
+ },
+};
+
+
+
struct platform_device msm9615_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
- .dev = {
+ .resource = msm_rpm_stat_resource,
+ .num_resources = ARRAY_SIZE(msm_rpm_stat_resource),
+ .dev = {
.platform_data = &msm_rpm_stat_pdata,
- },
+ }
};
static struct resource resources_rpm_master_stats[] = {
@@ -1421,6 +1457,19 @@
},
};
+static struct msm_pm_init_data_type msm_pm_data = {
+ .use_sync_timer = false,
+ .pc_mode = MSM_PM_PC_NOTZ_L2_EXT,
+};
+
+struct platform_device msm9615_pm_8x60 = {
+ .name = "pm-8x60",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_pm_data,
+ },
+};
+
uint32_t __init msm9615_rpm_get_swfi_latency(void)
{
int i;
diff --git a/arch/arm/mach-msm/devices-fsm9xxx.c b/arch/arm/mach-msm/devices-fsm9xxx.c
index 639eeae..9043223 100644
--- a/arch/arm/mach-msm/devices-fsm9xxx.c
+++ b/arch/arm/mach-msm/devices-fsm9xxx.c
@@ -228,6 +228,7 @@
.parts = NULL,
.nr_parts = 0,
.interleave = 0,
+ .version = VERSION_2,
};
struct platform_device msm_device_nand = {
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index 63c1dbd..983b13e 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -312,11 +312,6 @@
},
};
-static struct platform_device msm_root_iommu_dev = {
- .name = "msm_iommu",
- .id = -1,
-};
-
static struct msm_iommu_dev jpegd_iommu = {
.name = "jpegd",
.ncb = 2,
@@ -365,25 +360,25 @@
static struct msm_iommu_dev gfx3d_iommu = {
.name = "gfx3d",
.ncb = 3,
- .ttbr_split = 1,
+ .ttbr_split = 0,
};
static struct msm_iommu_dev gfx3d1_iommu = {
.name = "gfx3d1",
.ncb = 3,
- .ttbr_split = 1,
+ .ttbr_split = 0,
};
static struct msm_iommu_dev gfx2d0_iommu = {
.name = "gfx2d0",
.ncb = 2,
- .ttbr_split = 1,
+ .ttbr_split = 0,
};
static struct msm_iommu_dev gfx2d1_iommu = {
.name = "gfx2d1",
.ncb = 2,
- .ttbr_split = 1,
+ .ttbr_split = 0,
};
static struct msm_iommu_dev vcap_iommu = {
@@ -395,7 +390,6 @@
.name = "msm_iommu",
.id = 0,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &jpegd_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
@@ -406,7 +400,6 @@
.name = "msm_iommu",
.id = 1,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &vpe_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
@@ -417,7 +410,6 @@
.name = "msm_iommu",
.id = 2,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &mdp0_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
@@ -428,7 +420,6 @@
.name = "msm_iommu",
.id = 3,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &mdp1_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
@@ -439,7 +430,6 @@
.name = "msm_iommu",
.id = 4,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &rot_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
@@ -450,7 +440,6 @@
.name = "msm_iommu",
.id = 5,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &ijpeg_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
@@ -461,7 +450,6 @@
.name = "msm_iommu",
.id = 6,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &vfe_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
@@ -472,7 +460,6 @@
.name = "msm_iommu",
.id = 7,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &vcodec_a_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
@@ -483,7 +470,6 @@
.name = "msm_iommu",
.id = 8,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &vcodec_b_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
@@ -494,7 +480,6 @@
.name = "msm_iommu",
.id = 9,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &gfx3d_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
@@ -505,7 +490,6 @@
.name = "msm_iommu",
.id = 10,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &gfx3d1_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx3d1_resources),
@@ -516,7 +500,6 @@
.name = "msm_iommu",
.id = 10,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &gfx2d0_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
@@ -527,7 +510,6 @@
.name = "msm_iommu",
.id = 11,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &gfx2d1_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
@@ -538,7 +520,6 @@
.name = "msm_iommu",
.id = 11,
.dev = {
- .parent = &msm_root_iommu_dev.dev,
.platform_data = &vcap_iommu,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcap_resources),
@@ -999,12 +980,6 @@
return -ENODEV;
}
- ret = platform_device_register(&msm_root_iommu_dev);
- if (ret != 0) {
- pr_err("Failed to register root IOMMU device!\n");
- goto failure;
- }
-
/* Initialize common devs */
platform_add_devices(msm_iommu_common_devs,
ARRAY_SIZE(msm_iommu_common_devs));
@@ -1051,9 +1026,6 @@
ARRAY_SIZE(msm_iommu_vcap_ctx_devs));
return 0;
-
-failure:
- return ret;
}
static void __exit iommu_exit(void)
@@ -1112,8 +1084,6 @@
for (i = 0; i < ARRAY_SIZE(msm_iommu_jpegd_devs); i++)
platform_device_unregister(msm_iommu_jpegd_devs[i]);
}
-
- platform_device_unregister(&msm_root_iommu_dev);
}
subsys_initcall(iommu_init);
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 2c49b21..5296048 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -780,6 +780,16 @@
.notify_rpm = false,
.cmd = spm_pc_without_modem,
},
+ [2] = {
+ .mode = MSM_SPM_MODE_POWER_COLLAPSE,
+ .notify_rpm = false,
+ .cmd = spm_pc_without_modem,
+ },
+ [3] = {
+ .mode = MSM_SPM_MODE_POWER_COLLAPSE,
+ .notify_rpm = false,
+ .cmd = spm_pc_without_modem,
+ },
};
static struct msm_spm_platform_data msm_spm_data[] __initdata = {
@@ -797,6 +807,20 @@
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
+ [2] = {
+ .reg_base_addr = MSM_SAW2_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x0,
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
+ },
+ [3] = {
+ .reg_base_addr = MSM_SAW3_BASE,
+ .reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x0,
+ .reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
+ .num_modes = ARRAY_SIZE(msm_spm_seq_list),
+ .modes = msm_spm_seq_list,
+ },
};
void __init msm8x25_spm_device_init(void)
@@ -1643,6 +1667,7 @@
case 0x771:
case 0x77C:
case 0x780:
+ case 0x785: /* Edge-only MSM8125-0 */
case 0x8D0:
cpu = MSM8625;
break;
@@ -1770,7 +1795,7 @@
static struct msm_cpr_config msm_cpr_pdata = {
.ref_clk_khz = 19200,
- .delay_us = 1000,
+ .delay_us = 25000,
.irq_line = 0,
.cpr_mode_data = msm_cpr_mode_data,
.tgt_count_div_N = 1,
@@ -1778,12 +1803,13 @@
.ceiling = 40,
.sw_vlevel = 20,
.up_threshold = 1,
- .dn_threshold = 4,
+ .dn_threshold = 3,
.up_margin = 0,
.dn_margin = 0,
.max_nom_freq = 700800,
.max_freq = 1401600,
.max_quot = 0,
+ .disable_cpr = false,
.vp_data = &vp_data,
.get_quot = msm_cpr_get_quot,
.clk_enable = msm_cpr_clk_enable,
@@ -1816,6 +1842,7 @@
}
msm_smem_get_cpr_info(cpr_info);
+ msm_cpr_pdata.disable_cpr = cpr_info->disable_cpr;
/**
* Set the ring_osc based on efuse BIT(0)
@@ -1848,11 +1875,11 @@
* Ditto for a 1.0GHz part.
*/
if (msm8625_cpu_id() == MSM8625A) {
- msm_cpr_pdata.max_quot += 100;
+ msm_cpr_pdata.max_quot += 30;
if (msm_cpr_pdata.max_quot > 1400)
msm_cpr_pdata.max_quot = 1400;
} else if (msm8625_cpu_id() == MSM8625) {
- msm_cpr_pdata.max_quot += 120;
+ msm_cpr_pdata.max_quot += 50;
if (msm_cpr_pdata.max_quot > 1350)
msm_cpr_pdata.max_quot = 1350;
}
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 5554eb8..c6513d9 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -213,6 +213,11 @@
.flags = IORESOURCE_MEM,
},
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = LPASS_Q6SS_WDOG_EXPIRED,
.end = LPASS_Q6SS_WDOG_EXPIRED,
.flags = IORESOURCE_IRQ,
@@ -241,6 +246,11 @@
.flags = IORESOURCE_MEM,
},
{
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = MARM_WDOG_EXPIRED,
.end = MARM_WDOG_EXPIRED,
.flags = IORESOURCE_IRQ,
@@ -259,9 +269,19 @@
.id = -1,
};
+static struct resource msm_pil_dsps_resources[] = {
+ {
+ .start = 0x00900000,
+ .end = 0x00900000 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
struct platform_device msm_pil_dsps = {
.name = "pil_dsps",
.id = -1,
+ .resource = msm_pil_dsps_resources,
+ .num_resources = ARRAY_SIZE(msm_pil_dsps_resources),
.dev.platform_data = "dsps",
};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 97adb35..bd5a20f 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -109,6 +109,8 @@
extern struct platform_device msm_device_sdc3;
extern struct platform_device msm_device_sdc4;
+extern struct platform_device msm9615_pm_8x60;
+
extern struct platform_device msm8960_pc_cntr;
extern struct platform_device msm8064_pc_cntr;
extern struct platform_device msm8930_pc_cntr;
@@ -232,6 +234,7 @@
extern struct platform_device msm_stub_codec;
extern struct platform_device msm_voice;
extern struct platform_device msm_voip;
+extern struct platform_device msm_dtmf;
extern struct platform_device msm_lpa_pcm;
extern struct platform_device msm_pcm_hostless;
extern struct platform_device msm_cpudai_afe_01_rx;
@@ -247,6 +250,8 @@
extern struct platform_device msm_i2s_cpudai1;
extern struct platform_device msm_i2s_cpudai4;
extern struct platform_device msm_i2s_cpudai5;
+extern struct platform_device msm_cpudai_stub;
+
extern struct platform_device msm_pil_q6v3;
extern struct platform_device msm_pil_modem;
extern struct platform_device msm_pil_tzapps;
@@ -307,6 +312,8 @@
extern unsigned apq8064_num_footswitch;
extern struct platform_device *msm8930_footswitch[];
extern unsigned msm8930_num_footswitch;
+extern struct platform_device *msm8930_pm8917_footswitch[];
+extern unsigned msm8930_pm8917_num_footswitch;
extern struct platform_device *msm8627_footswitch[];
extern unsigned msm8627_num_footswitch;
@@ -403,6 +410,7 @@
extern struct platform_device *msm_8974_stub_regulator_devices[];
extern int msm_8974_stub_regulator_devices_len;
+extern struct platform_device apq8064_dcvs_device;
extern struct platform_device apq8064_msm_gov_device;
extern struct platform_device msm_bus_8930_apps_fabric;
@@ -447,6 +455,7 @@
extern struct platform_device msm8x60_device_acpuclk;
extern struct platform_device msm8930_device_acpuclk;
extern struct platform_device msm8930aa_device_acpuclk;
+extern struct platform_device msm8930ab_device_acpuclk;
extern struct platform_device msm8960_device_acpuclk;
extern struct platform_device msm8960ab_device_acpuclk;
extern struct platform_device msm9615_device_acpuclk;
diff --git a/arch/arm/mach-msm/idle-v7.S b/arch/arm/mach-msm/idle-v7.S
index 1d8f313..ccd0bf7 100644
--- a/arch/arm/mach-msm/idle-v7.S
+++ b/arch/arm/mach-msm/idle-v7.S
@@ -22,7 +22,7 @@
#include "idle.h"
#include "idle-macros.S"
-#ifdef CONFIG_ARCH_MSM_KRAIT
+#ifdef CONFIG_MSM_SCM
#define SCM_SVC_BOOT 0x1
#define SCM_CMD_TERMINATE_PC 0x2
#endif
@@ -127,7 +127,18 @@
cmp r1, #1
bne skip
bl v7_flush_dcache_all
+ ldr r1, =msm_pm_flush_l2_fn
+ ldr r1, [r1]
+ cmp r1, #0
+ blxne r1
+
skip:
+ ldr r1, =msm_pm_disable_l2_fn
+ ldr r1, [r1]
+ cmp r1, #0
+ blxne r1
+ dmb
+
mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
and r0, r0, #15 /* what CPU am I */
@@ -141,7 +152,7 @@
str r2, [r1]
skip_pc_debug1:
-#ifdef CONFIG_ARCH_MSM_KRAIT
+#ifdef CONFIG_MSM_SCM
ldr r0, =SCM_SVC_BOOT
ldr r1, =SCM_CMD_TERMINATE_PC
ldr r2, =msm_pm_flush_l2_flag
@@ -182,6 +193,11 @@
str r2, [r1]
skip_pc_debug2:
+ ldr r1, =msm_pm_enable_l2_fn
+ ldr r1, [r1]
+ cmp r1, #0
+ blxne r1
+ dmb
#ifdef CONFIG_MSM_JTAG
bl msm_jtag_restore_state
@@ -286,11 +302,16 @@
SET_SMP_COHERENCY ON
#endif
-#ifdef CONFIG_MSM_JTAG
+ ldr r1, =msm_pm_enable_l2_fn
+ ldr r1, [r1]
+ cmp r1, #0
stmfd sp!, {lr}
+ blxne r1
+ dmb
+#ifdef CONFIG_MSM_JTAG
bl msm_jtag_restore_state
- ldmfd sp!, {lr}
#endif
+ ldmfd sp!, {lr}
mov r0, #1
bx lr
nop
@@ -377,6 +398,18 @@
msm_pc_debug_counters:
.long 0x0
+ .globl msm_pm_enable_l2_fn
+msm_pm_enable_l2_fn:
+ .long 0x0
+
+ .globl msm_pm_disable_l2_fn
+msm_pm_disable_l2_fn:
+ .long 0x0
+
+ .globl msm_pm_flush_l2_fn
+msm_pm_flush_l2_fn:
+ .long 0x0
+
/*
* Default the l2 flush flag to 1 so that caches are flushed during power
* collapse unless the L2 driver decides to flush them only during L2
diff --git a/arch/arm/mach-msm/idle.h b/arch/arm/mach-msm/idle.h
index 7a939ab..ee3209c 100644
--- a/arch/arm/mach-msm/idle.h
+++ b/arch/arm/mach-msm/idle.h
@@ -33,6 +33,9 @@
int msm_pm_collapse(void);
void msm_pm_collapse_exit(void);
extern void *msm_saved_state;
+extern void (*msm_pm_disable_l2_fn)(void);
+extern void (*msm_pm_enable_l2_fn)(void);
+extern void (*msm_pm_flush_l2_fn)(void);
extern unsigned long msm_saved_state_phys;
#ifdef CONFIG_CPU_V7
diff --git a/arch/arm/mach-msm/include/mach/bam_dmux.h b/arch/arm/mach-msm/include/mach/bam_dmux.h
index f02a882..f11b72c 100644
--- a/arch/arm/mach-msm/include/mach/bam_dmux.h
+++ b/arch/arm/mach-msm/include/mach/bam_dmux.h
@@ -28,6 +28,18 @@
BAM_DMUX_DATA_RMNET_6,
BAM_DMUX_DATA_RMNET_7,
BAM_DMUX_USB_RMNET_0,
+ BAM_DMUX_RESERVED_0, /* 9..11 are reserved*/
+ BAM_DMUX_RESERVED_1,
+ BAM_DMUX_RESERVED_2,
+ BAM_DMUX_DATA_REV_RMNET_0,
+ BAM_DMUX_DATA_REV_RMNET_1,
+ BAM_DMUX_DATA_REV_RMNET_2,
+ BAM_DMUX_DATA_REV_RMNET_3,
+ BAM_DMUX_DATA_REV_RMNET_4,
+ BAM_DMUX_DATA_REV_RMNET_5,
+ BAM_DMUX_DATA_REV_RMNET_6,
+ BAM_DMUX_DATA_REV_RMNET_7,
+ BAM_DMUX_DATA_REV_RMNET_8,
BAM_DMUX_NUM_CHANNELS
};
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index ff4776a..9c5e52c 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -129,6 +129,10 @@
struct msm_camera_sensor_flash_src {
int flash_sr_type;
+ struct gpio *init_gpio_tbl;
+ uint8_t init_gpio_tbl_size;
+ struct msm_gpio_set_tbl *set_gpio_tbl;
+ uint8_t set_gpio_tbl_size;
union {
struct msm_camera_sensor_flash_pmic pmic_src;
@@ -144,6 +148,9 @@
struct msm_camera_sensor_flash_data {
int flash_type;
struct msm_camera_sensor_flash_src *flash_src;
+ struct i2c_board_info const *board_info;
+ int bus_id;
+ uint8_t flash_src_index;
};
struct msm_camera_sensor_strobe_flash_data {
@@ -587,6 +594,7 @@
void msm_map_msm8226_io(void);
void msm8226_init_irq(void);
void msm8226_init_gpiomux(void);
+void msm8910_init_gpiomux(void);
void msm_map_msm8910_io(void);
void msm8910_init_irq(void);
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index f5a158f..3dfa659c 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -508,35 +508,6 @@
struct msm_pmem_region *region;
};
-#ifdef CONFIG_MSM_CAMERA_FLASH
-int msm_camera_flash_set_led_state(
- struct msm_camera_sensor_flash_data *fdata,
- unsigned led_state);
-int msm_strobe_flash_init(struct msm_sync *sync, uint32_t sftype);
-int msm_flash_ctrl(struct msm_camera_sensor_info *sdata,
- struct flash_ctrl_data *flash_info);
-#else
-static inline int msm_camera_flash_set_led_state(
- struct msm_camera_sensor_flash_data *fdata,
- unsigned led_state)
-{
- return -ENOTSUPP;
-}
-static inline int msm_strobe_flash_init(
- struct msm_sync *sync, uint32_t sftype)
-{
- return -ENOTSUPP;
-}
-static inline int msm_flash_ctrl(
- struct msm_camera_sensor_info *sdata,
- struct flash_ctrl_data *flash_info)
-{
- return -ENOTSUPP;
-}
-#endif
-
-
-
void msm_camvfe_init(void);
int msm_camvfe_check(void *);
void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *);
@@ -634,6 +605,7 @@
S_DEFAULT,
S_LIVESHOT,
S_DUAL,
+ S_ADV_VIDEO,
S_EXIT
};
@@ -704,4 +676,10 @@
(struct msm_camera_sensor_info *sinfo, int gpio_en);
void msm_camera_bus_scale_cfg(uint32_t bus_perf_client,
enum msm_bus_perf_setting perf_setting);
+
+int msm_camera_init_gpio_table(struct gpio *gpio_tbl, uint8_t gpio_tbl_size,
+ int gpio_en);
+
+int msm_camera_set_gpio_table(struct msm_gpio_set_tbl *gpio_tbl,
+ uint8_t gpio_tbl_size, int gpio_en);
#endif
diff --git a/arch/arm/mach-msm/include/mach/clk-provider.h b/arch/arm/mach-msm/include/mach/clk-provider.h
index d47e88e..0f2feaa 100644
--- a/arch/arm/mach-msm/include/mach/clk-provider.h
+++ b/arch/arm/mach-msm/include/mach/clk-provider.h
@@ -103,6 +103,7 @@
* @depends: non-direct parent of clock to enable when this clock is enabled
* @vdd_class: voltage scaling requirement class
* @fmax: maximum frequency in Hz supported at each voltage level
+ * @parent: the current source of this clock
*/
struct clk {
uint32_t flags;
@@ -113,6 +114,7 @@
unsigned long *fmax;
int num_fmax;
unsigned long rate;
+ struct clk *parent;
struct list_head children;
struct list_head siblings;
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 988b249..5fcf579 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -269,7 +269,7 @@
#define DMOV8064_CE_OUT_CHAN 1
#define DMOV8064_CE_OUT_CRCI 15
-#define DMOV8064_TSIF_CHAN 2
+#define DMOV8064_TSIF_CHAN 4
#define DMOV8064_TSIF_CRCI 1
/* channels for MPQ8064 */
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 69ddeb9..57b4bd3 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,11 +15,11 @@
#include <linux/interrupt.h>
#include <linux/clk.h>
+#include <linux/list.h>
#include <linux/regulator/consumer.h>
#include <mach/socinfo.h>
extern pgprot_t pgprot_kernel;
-extern struct platform_device *msm_iommu_root_dev;
extern struct bus_type msm_iommu_sec_bus_type;
/* Domain attributes */
@@ -91,6 +91,8 @@
* @name: Human-readable name of this IOMMU device
* @gdsc: Regulator needed to power this HW block (v2 only)
* @bfb_settings: Optional BFB performance tuning parameters
+ * @dev: Struct device this hardware instance is tied to
+ * @list: List head to link all iommus together
*
* A msm_iommu_drvdata holds the global driver data about a single piece
* of an IOMMU hardware instance.
@@ -106,8 +108,13 @@
struct regulator *gdsc;
struct msm_iommu_bfb_settings *bfb_settings;
int sec_id;
+ struct device *dev;
+ struct list_head list;
};
+void msm_iommu_add_drv(struct msm_iommu_drvdata *drv);
+void msm_iommu_remove_drv(struct msm_iommu_drvdata *drv);
+
/**
* struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
* @num: Hardware context number of this context
@@ -154,7 +161,12 @@
}
#endif
-#endif
+/*
+ * Function to program the global registers of an IOMMU securely.
+ * This should only be called on IOMMUs for which kernel programming
+ * of global registers is not possible
+ */
+int msm_iommu_sec_program_iommu(int sec_id);
static inline int msm_soc_version_supports_iommu_v1(void)
{
@@ -178,3 +190,4 @@
}
return 1;
}
+#endif
diff --git a/arch/arm/mach-msm/include/mach/ipa.h b/arch/arm/mach-msm/include/mach/ipa.h
new file mode 100644
index 0000000..0f689ac
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/ipa.h
@@ -0,0 +1,458 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_H_
+#define _IPA_H_
+
+#include <linux/msm_ipa.h>
+#include <linux/skbuff.h>
+#include <linux/types.h>
+#include <mach/sps.h>
+
+/**
+ * enum ipa_nat_en_type - NAT setting type in IPA end-point
+ */
+enum ipa_nat_en_type {
+ IPA_BYPASS_NAT,
+ IPA_SRC_NAT,
+ IPA_DST_NAT,
+};
+
+/**
+ * enum ipa_mode_type - mode setting type in IPA end-point
+ * @BASIC: basic mode
+ * @ENABLE_FRAMING_HDLC: not currently supported
+ * @ENABLE_DEFRAMING_HDLC: not currently supported
+ */
+enum ipa_mode_type {
+ IPA_BASIC,
+ IPA_ENABLE_FRAMING_HDLC,
+ IPA_ENABLE_DEFRAMING_HDLC,
+ IPA_DMA,
+};
+
+/**
+ * enum ipa_aggr_en_type - aggregation setting type in IPA
+ * end-point
+ */
+enum ipa_aggr_en_type {
+ IPA_BYPASS_AGGR,
+ IPA_ENABLE_AGGR,
+ IPA_ENABLE_DEAGGR,
+};
+
+/**
+ * enum ipa_aggr_type - type of aggregation in IPA end-point
+ */
+enum ipa_aggr_type {
+ IPA_MBIM_16,
+ IPA_MBIM_32,
+ IPA_TLP,
+};
+
+/**
+ * enum ipa_aggr_mode - global aggregation mode
+ */
+enum ipa_aggr_mode {
+ IPA_MBIM,
+ IPA_QCNCM,
+};
+
+/**
+ * enum ipa_dp_evt_type - type of event client callback is
+ * invoked for on data path
+ * @IPA_RECEIVE: data is struct sk_buff
+ * @IPA_WRITE_DONE: data is struct sk_buff
+ */
+enum ipa_dp_evt_type {
+ IPA_RECEIVE,
+ IPA_WRITE_DONE,
+};
+
+/**
+ * struct ipa_ep_cfg_nat - NAT configuration in IPA end-point
+ * @nat_en: This defines the default NAT mode for the pipe: in case of
+ * filter miss - the default NAT mode defines the NATing operation
+ * on the packet. Valid for Input Pipes only (IPA consumer)
+ */
+struct ipa_ep_cfg_nat {
+ enum ipa_nat_en_type nat_en;
+};
+
+/**
+ * struct ipa_ep_cfg_hdr - header configuration in IPA end-point
+ * @hdr_len: Header length in bytes to be added/removed. Assuming header len
+ * is constant per endpoint. Valid for both Input and Output Pipes
+ * @hdr_ofst_metadata_valid: 0: Metadata_Ofst value is invalid, i.e., no
+ * metadata within header.
+ * 1: Metadata_Ofst value is valid, i.e., metadata
+ * within header is in offset Metadata_Ofst Valid
+ * for Input Pipes only (IPA Consumer) (for output
+ * pipes, metadata already set within the header)
+ * @hdr_ofst_metadata: Offset within header in which metadata resides
+ * Size of metadata - 4bytes
+ * Example - Stream ID/SSID/mux ID.
+ * Valid for Input Pipes only (IPA Consumer) (for output
+ * pipes, metadata already set within the header)
+ * @hdr_additional_const_len: Defines the constant length that should be added
+ * to the payload length in order for IPA to update
+ * correctly the length field within the header
+ * (valid only in case Hdr_Ofst_Pkt_Size_Valid=1)
+ * Valid for Output Pipes (IPA Producer)
+ * @hdr_ofst_pkt_size_valid: 0: Hdr_Ofst_Pkt_Size value is invalid, i.e., no
+ * length field within the inserted header
+ * 1: Hdr_Ofst_Pkt_Size value is valid, i.e., a
+ * packet length field resides within the header
+ * Valid for Output Pipes (IPA Producer)
+ * @hdr_ofst_pkt_size: Offset within header in which packet size reside. Upon
+ * Header Insertion, IPA will update this field within the
+ * header with the packet length . Assumption is that
+ * header length field size is constant and is 2Bytes
+ * Valid for Output Pipes (IPA Producer)
+ * @hdr_a5_mux: Determines whether A5 Mux header should be added to the packet.
+ * This bit is valid only when Hdr_En=01(Header Insertion)
+ * SW should set this bit for IPA-to-A5 pipes.
+ * 0: Do not insert A5 Mux Header
+ * 1: Insert A5 Mux Header
+ * Valid for Output Pipes (IPA Producer)
+ */
+struct ipa_ep_cfg_hdr {
+ u32 hdr_len;
+ u32 hdr_ofst_metadata_valid;
+ u32 hdr_ofst_metadata;
+ u32 hdr_additional_const_len;
+ u32 hdr_ofst_pkt_size_valid;
+ u32 hdr_ofst_pkt_size;
+ u32 hdr_a5_mux;
+};
+
+/**
+ * struct ipa_ep_cfg_mode - mode configuration in IPA end-point
+ * @mode: Valid for Input Pipes only (IPA Consumer)
+ * @dst: This parameter specifies the output pipe to which the packets
+ * will be routed to.
+ * This parameter is valid for Mode=DMA and not valid for
+ * Mode=Basic
+ * Valid for Input Pipes only (IPA Consumer)
+ */
+struct ipa_ep_cfg_mode {
+ enum ipa_mode_type mode;
+ enum ipa_client_type dst;
+};
+
+/**
+ * struct ipa_ep_cfg_aggr - aggregation configuration in IPA end-point
+ * @aggr_en: Valid for both Input and Output Pipes
+ * @aggr: Valid for both Input and Output Pipes
+ * @aggr_byte_limit: Limit of aggregated packet size in KB (<=32KB) When set
+ * to 0, there is no size limitation on the aggregation.
+ * When both, Aggr_Byte_Limit and Aggr_Time_Limit are set
+ * to 0, there is no aggregation, every packet is sent
+ * independently according to the aggregation structure
+ * Valid for Output Pipes only (IPA Producer )
+ * @aggr_time_limit: Timer to close aggregated packet (<=32ms) When set to 0,
+ * there is no time limitation on the aggregation. When
+ * both, Aggr_Byte_Limit and Aggr_Time_Limit are set to 0,
+ * there is no aggregation, every packet is sent
+ * independently according to the aggregation structure
+ * Valid for Output Pipes only (IPA Producer)
+ */
+struct ipa_ep_cfg_aggr {
+ enum ipa_aggr_en_type aggr_en;
+ enum ipa_aggr_type aggr;
+ u32 aggr_byte_limit;
+ u32 aggr_time_limit;
+};
+
+/**
+ * struct ipa_ep_cfg_route - route configuration in IPA end-point
+ * @rt_tbl_hdl: Defines the default routing table index to be used in case there
+ * is no filter rule matching, valid for Input Pipes only (IPA
+ * Consumer). Clients should set this to 0 which will cause default
+ * v4 and v6 routes setup internally by IPA driver to be used for
+ * this end-point
+ */
+struct ipa_ep_cfg_route {
+ u32 rt_tbl_hdl;
+};
+
+/**
+ * struct ipa_ep_cfg - configuration of IPA end-point
+ * @nat: NAT parmeters
+ * @hdr: Header parameters
+ * @mode: Mode parameters
+ * @aggr: Aggregation parameters
+ * @route: Routing parameters
+ */
+struct ipa_ep_cfg {
+ struct ipa_ep_cfg_nat nat;
+ struct ipa_ep_cfg_hdr hdr;
+ struct ipa_ep_cfg_mode mode;
+ struct ipa_ep_cfg_aggr aggr;
+ struct ipa_ep_cfg_route route;
+};
+
+/**
+ * struct ipa_connect_params - low-level client connect input parameters. Either
+ * client allocates the data and desc FIFO and specifies that in data+desc OR
+ * specifies sizes and pipe_mem pref and IPA does the allocation.
+ *
+ * @ipa_ep_cfg: IPA EP configuration
+ * @client: type of "client"
+ * @client_bam_hdl: client SPS handle
+ * @client_ep_idx: client PER EP index
+ * @priv: callback cookie
+ * @notify: callback
+ * priv - callback cookie evt - type of event data - data relevant
+ * to event. May not be valid. See event_type enum for valid
+ * cases.
+ * @desc_fifo_sz: size of desc FIFO
+ * @data_fifo_sz: size of data FIFO
+ * @pipe_mem_preferred: if true, try to alloc the FIFOs in pipe mem, fallback
+ * to sys mem if pipe mem alloc fails
+ * @desc: desc FIFO meta-data when client has allocated it
+ * @data: data FIFO meta-data when client has allocated it
+ */
+struct ipa_connect_params {
+ struct ipa_ep_cfg ipa_ep_cfg;
+ enum ipa_client_type client;
+ u32 client_bam_hdl;
+ u32 client_ep_idx;
+ void *priv;
+ void (*notify)(void *priv, enum ipa_dp_evt_type evt,
+ unsigned long data);
+ u32 desc_fifo_sz;
+ u32 data_fifo_sz;
+ bool pipe_mem_preferred;
+ struct sps_mem_buffer desc;
+ struct sps_mem_buffer data;
+};
+
+/**
+ * struct ipa_sps_params - SPS related output parameters resulting from
+ * low/high level client connect
+ * @ipa_bam_hdl: IPA SPS handle
+ * @ipa_ep_idx: IPA PER EP index
+ * @desc: desc FIFO meta-data
+ * @data: data FIFO meta-data
+ */
+struct ipa_sps_params {
+ u32 ipa_bam_hdl;
+ u32 ipa_ep_idx;
+ struct sps_mem_buffer desc;
+ struct sps_mem_buffer data;
+};
+
+/**
+ * struct ipa_tx_intf - interface tx properties
+ * @num_props: number of tx properties
+ * @prop: the tx properties array
+ */
+struct ipa_tx_intf {
+ u32 num_props;
+ struct ipa_ioc_tx_intf_prop *prop;
+};
+
+/**
+ * struct ipa_rx_intf - interface rx properties
+ * @num_props: number of rx properties
+ * @prop: the rx properties array
+ */
+struct ipa_rx_intf {
+ u32 num_props;
+ struct ipa_ioc_rx_intf_prop *prop;
+};
+
+/**
+ * struct ipa_sys_connect_params - information needed to setup an IPA end-point
+ * in system-BAM mode
+ * @ipa_ep_cfg: IPA EP configuration
+ * @client: the type of client who "owns" the EP
+ * @desc_fifo_sz: size of desc FIFO
+ * @priv: callback cookie
+ * @notify: callback
+ * priv - callback cookie
+ * evt - type of event
+ * data - data relevant to event. May not be valid. See event_type
+ * enum for valid cases.
+ */
+struct ipa_sys_connect_params {
+ struct ipa_ep_cfg ipa_ep_cfg;
+ enum ipa_client_type client;
+ u32 desc_fifo_sz;
+ void *priv;
+ void (*notify)(void *priv,
+ enum ipa_dp_evt_type evt,
+ unsigned long data);
+};
+
+/**
+ * struct ipa_msg_meta_wrapper - message meta-data wrapper
+ * @meta: the meta-data itself
+ * @link: opaque to client
+ * @meta_wrapper_free: function to free the metadata wrapper when IPA driver
+ * is done with it
+ */
+struct ipa_msg_meta_wrapper {
+ struct ipa_msg_meta meta;
+ struct list_head link;
+ void (*meta_wrapper_free)(struct ipa_msg_meta_wrapper *buff);
+};
+
+/**
+ * struct ipa_tx_meta - meta-data for the TX packet
+ * @mbim_stream_id: the stream ID used in NDP signature
+ * @mbim_stream_id_valid: is above field valid?
+ */
+struct ipa_tx_meta {
+ u8 mbim_stream_id;
+ bool mbim_stream_id_valid;
+};
+
+/**
+ * struct ipa_msg_wrapper - message wrapper
+ * @msg: the message buffer itself, MUST exist after call returns, will
+ * be freed by IPA driver when it is done with it
+ * @link: opaque to client
+ * @msg_free: function to free the message when IPA driver is done with it
+ * @msg_wrapper_free: function to free the message wrapper when IPA driver is
+ * done with it
+ */
+struct ipa_msg_wrapper {
+ void *msg;
+ struct list_head link;
+ void (*msg_free)(void *msg);
+ void (*msg_wrapper_free)(struct ipa_msg_wrapper *buff);
+};
+
+/**
+ * typedef ipa_pull_fn - callback function
+ * @buf - [in] the buffer to populate the message into
+ * @sz - [in] the size of the buffer
+ *
+ * callback function registered by kernel client with IPA driver for IPA driver
+ * to be able to pull messages from the kernel client asynchronously.
+ *
+ * Returns how many bytes were copied into the buffer, negative on failure.
+ */
+typedef int (*ipa_pull_fn)(void *buf, uint16_t sz);
+
+/*
+ * Connect / Disconnect
+ */
+int ipa_connect(const struct ipa_connect_params *in, struct ipa_sps_params *sps,
+ u32 *clnt_hdl);
+int ipa_disconnect(u32 clnt_hdl);
+
+/*
+ * Configuration
+ */
+int ipa_cfg_ep(u32 clnt_hdl, const struct ipa_ep_cfg *ipa_ep_cfg);
+
+int ipa_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ipa_ep_cfg);
+
+int ipa_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ipa_ep_cfg);
+
+int ipa_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ipa_ep_cfg);
+
+int ipa_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ipa_ep_cfg);
+
+int ipa_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ipa_ep_cfg);
+
+/*
+ * Header removal / addition
+ */
+int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs);
+
+int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls);
+
+int ipa_commit_hdr(void);
+
+int ipa_reset_hdr(void);
+
+int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup);
+
+int ipa_put_hdr(u32 hdr_hdl);
+
+int ipa_copy_hdr(struct ipa_ioc_copy_hdr *copy);
+
+/*
+ * Routing
+ */
+int ipa_add_rt_rule(struct ipa_ioc_add_rt_rule *rules);
+
+int ipa_del_rt_rule(struct ipa_ioc_del_rt_rule *hdls);
+
+int ipa_commit_rt(enum ipa_ip_type ip);
+
+int ipa_reset_rt(enum ipa_ip_type ip);
+
+int ipa_get_rt_tbl(struct ipa_ioc_get_rt_tbl *lookup);
+
+int ipa_put_rt_tbl(u32 rt_tbl_hdl);
+
+/*
+ * Filtering
+ */
+int ipa_add_flt_rule(struct ipa_ioc_add_flt_rule *rules);
+
+int ipa_del_flt_rule(struct ipa_ioc_del_flt_rule *hdls);
+
+int ipa_commit_flt(enum ipa_ip_type ip);
+
+int ipa_reset_flt(enum ipa_ip_type ip);
+
+/*
+ * NAT
+ */
+int allocate_nat_device(struct ipa_ioc_nat_alloc_mem *mem);
+
+int ipa_nat_init_cmd(struct ipa_ioc_v4_nat_init *init);
+
+int ipa_nat_dma_cmd(struct ipa_ioc_nat_dma_cmd *dma);
+
+int ipa_nat_del_cmd(struct ipa_ioc_v4_nat_del *del);
+
+/*
+ * Aggregation
+ */
+int ipa_set_aggr_mode(enum ipa_aggr_mode mode);
+
+int ipa_set_qcncm_ndp_sig(char sig[3]);
+
+int ipa_set_single_ndp_per_mbim(bool enable);
+
+/*
+ * rmnet bridge
+ */
+int rmnet_bridge_init(void);
+
+int rmnet_bridge_disconnect(void);
+
+int rmnet_bridge_connect(u32 producer_hdl,
+ u32 consumer_hdl,
+ int wwan_logical_channel_id);
+
+/*
+ * Data path
+ */
+int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb,
+ struct ipa_tx_meta *metadata);
+
+/*
+ * System pipes
+ */
+int ipa_setup_sys_pipe(struct ipa_sys_connect_params *sys_in, u32 *clnt_hdl);
+
+int ipa_teardown_sys_pipe(u32 clnt_hdl);
+
+#endif /* _IPA_H_ */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8226.h b/arch/arm/mach-msm/include/mach/irqs-8226.h
index fad7b90..72602b1 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8226.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8226.h
@@ -24,18 +24,15 @@
#define GIC_PPI_START 16
#define GIC_SPI_START 32
-#define AVS_SVICINT (GIC_PPI_START + 6)
-#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
/* PPI 15 is unused */
#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
-#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#define NR_MSM_IRQS 256
-#define NR_GPIO_IRQS 146
+#define NR_GPIO_IRQS 117
#define NR_QPNP_IRQS 32768 /* SPARSE_IRQ is required to support this */
#define NR_BOARD_IRQS NR_QPNP_IRQS
#define NR_TLMM_MSM_DIR_CONN_IRQ 8
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
index 2a61118..f591a9e 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -21,7 +21,7 @@
#endif
/* As per QGIC2 PPI 16 aka 0 is reserved */
-#define MSM8625_INT_A5_PMU_IRQ (GIC_PPI_START + 1)
+#define MSM8625_INT_ARMQC_PERFMON (GIC_PPI_START + 1)
#define MSM8625_INT_DEBUG_TIMER_EXP (GIC_PPI_START + 2)
#define MSM8625_INT_GP_TIMER_EXP (GIC_PPI_START + 3)
#define MSM8625_INT_COMMRX (GIC_PPI_START + 4)
diff --git a/arch/arm/mach-msm/include/mach/irqs-9625.h b/arch/arm/mach-msm/include/mach/irqs-9625.h
index f50606d..abafc23 100644
--- a/arch/arm/mach-msm/include/mach/irqs-9625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-9625.h
@@ -28,7 +28,7 @@
#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
#define NR_MSM_IRQS 288
-#define NR_GPIO_IRQS 88
+#define NR_GPIO_IRQS 76
#define NR_BOARD_IRQS 0
#define NR_TLMM_MSM_DIR_CONN_IRQ 8 /*Need to Verify this Count*/
#define NR_MSM_GPIOS NR_GPIO_IRQS
diff --git a/arch/arm/mach-msm/include/mach/msm_bus_board.h b/arch/arm/mach-msm/include/mach/msm_bus_board.h
index 0a53b46..84a7dc0 100644
--- a/arch/arm/mach-msm/include/mach/msm_bus_board.h
+++ b/arch/arm/mach-msm/include/mach/msm_bus_board.h
@@ -92,6 +92,11 @@
extern struct msm_bus_fabric_registration msm_bus_8974_config_noc_pdata;
extern struct msm_bus_fabric_registration msm_bus_8974_ocmem_vnoc_pdata;
+extern struct msm_bus_fabric_registration msm_bus_9625_sys_noc_pdata;
+extern struct msm_bus_fabric_registration msm_bus_9625_bimc_pdata;
+extern struct msm_bus_fabric_registration msm_bus_9625_periph_noc_pdata;
+extern struct msm_bus_fabric_registration msm_bus_9625_config_noc_pdata;
+
void msm_bus_rpm_set_mt_mask(void);
int msm_bus_board_rpm_get_il_ids(uint16_t *id);
int msm_bus_board_get_iid(int id);
@@ -291,8 +296,10 @@
MSM_BUS_MASTER_USB_HS,
MSM_BUS_MASTER_PNOC_CFG,
MSM_BUS_MASTER_V_OCMEM_GFX3D,
+ MSM_BUS_MASTER_IPA,
+ MSM_BUS_MASTER_QPIC,
- MSM_BUS_MASTER_LAST = MSM_BUS_MASTER_V_OCMEM_GFX3D,
+ MSM_BUS_MASTER_LAST = MSM_BUS_MASTER_QPIC,
MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM =
MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB,
@@ -446,8 +453,10 @@
MSM_BUS_SLAVE_PHY_APU_CFG,
MSM_BUS_SLAVE_EBI1_PHY_CFG,
MSM_BUS_SLAVE_SERVICE_CNOC,
+ MSM_BUS_SLAVE_IPS_CFG,
+ MSM_BUS_SLAVE_QPIC,
- MSM_BUS_SLAVE_LAST = MSM_BUS_SLAVE_SERVICE_CNOC,
+ MSM_BUS_SLAVE_LAST = MSM_BUS_SLAVE_QPIC,
MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM =
MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB,
diff --git a/arch/arm/mach-msm/include/mach/msm_dcvs.h b/arch/arm/mach-msm/include/mach/msm_dcvs.h
index e81cee4..c29b57a 100644
--- a/arch/arm/mach-msm/include/mach/msm_dcvs.h
+++ b/arch/arm/mach-msm/include/mach/msm_dcvs.h
@@ -36,12 +36,36 @@
MSM_DCVS_DISABLE_HIGH_LATENCY_MODES,
};
+struct msm_dcvs_sync_rule {
+ unsigned long cpu_khz;
+ unsigned long gpu_floor_khz;
+};
+
+struct msm_dcvs_platform_data {
+ struct msm_dcvs_sync_rule *sync_rules;
+ unsigned num_sync_rules;
+};
+
struct msm_gov_platform_data {
struct msm_dcvs_core_info *info;
int latency;
};
/**
+ * msm_dcvs_register_cpu_freq
+ * @freq: the frequency value to register
+ * @voltage: the operating voltage (in mV) associated with the above frequency
+ *
+ * Register a cpu frequency and its operating voltage with dcvs.
+ */
+#ifdef CONFIG_MSM_DCVS
+void msm_dcvs_register_cpu_freq(uint32_t freq, uint32_t voltage);
+#else
+static inline void msm_dcvs_register_cpu_freq(uint32_t freq, uint32_t voltage)
+{}
+#endif
+
+/**
* msm_dcvs_idle
* @dcvs_core_id: The id returned by msm_dcvs_register_core
* @state: The enter/exit idle state the core is in
@@ -98,6 +122,7 @@
unsigned int (*get_frequency)(int type_core_num),
int (*idle_enable)(int type_core_num,
enum msm_core_control_event event),
+ int (*set_floor_frequency)(int type_core_num, unsigned int freq),
int sensor);
/**
diff --git a/arch/arm/mach-msm/include/mach/msm_hdmi_audio.h b/arch/arm/mach-msm/include/mach/msm_hdmi_audio.h
index 2455e93..9b04141 100644
--- a/arch/arm/mach-msm/include/mach/msm_hdmi_audio.h
+++ b/arch/arm/mach-msm/include/mach/msm_hdmi_audio.h
@@ -29,7 +29,8 @@
HDMI_SAMPLE_RATE_88_2KHZ,
HDMI_SAMPLE_RATE_96KHZ,
HDMI_SAMPLE_RATE_176_4KHZ,
- HDMI_SAMPLE_RATE_192KHZ
+ HDMI_SAMPLE_RATE_192KHZ,
+ HDMI_SAMPLE_RATE_MAX
};
int hdmi_audio_enable(bool on , u32 fifo_water_mark);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8226.h b/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
index 08bc981..c03b513 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8226.h
@@ -45,7 +45,4 @@
#define MSM_DEBUG_UART_PHYS 0xF991E000
#endif
-#define MSM8226_DBG_IMEM_PHYS 0xFE805000
-#define MSM8226_DBG_IMEM_SIZE SZ_4K
-
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8625.h b/arch/arm/mach-msm/include/mach/msm_iomap-8625.h
index 43250f5..9b6de20 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8625.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8625.h
@@ -54,6 +54,12 @@
#define MSM8625_SAW1_PHYS 0xC0700000
#define MSM8625_SAW1_SIZE SZ_4K
+#define MSM8625_SAW2_PHYS 0xC0A00000
+#define MSM8625_SAW2_SIZE SZ_4K
+
+#define MSM8625_SAW3_PHYS 0xC0B00000
+#define MSM8625_SAW3_SIZE SZ_4K
+
#define MSM8625_CFG_CTL_PHYS 0xA9800000
#define MSM8625_CFG_CTL_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8910.h b/arch/arm/mach-msm/include/mach/msm_iomap-8910.h
index e4cd312..08f21b6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8910.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8910.h
@@ -30,9 +30,12 @@
#define MSM8910_TLMM_PHYS 0xFD510000
#define MSM8910_TLMM_SIZE SZ_16K
-#define MSM8910_IMEM_PHYS 0xFC42B000
+#define MSM8910_IMEM_PHYS 0xFE805000
#define MSM8910_IMEM_SIZE SZ_4K
+#define MSM8910_MPM2_PSHOLD_PHYS 0xFC4AB000
+#define MSM8910_MPM2_PSHOLD_SIZE SZ_4K
+
#ifdef CONFIG_DEBUG_MSM8910_UART
#define MSM_DEBUG_UART_BASE IOMEM(0xFA71E000)
#define MSM_DEBUG_UART_PHYS 0xF991E000
diff --git a/arch/arm/mach-msm/include/mach/msm_ipc_router.h b/arch/arm/mach-msm/include/mach/msm_ipc_router.h
new file mode 100644
index 0000000..45a7e19
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_ipc_router.h
@@ -0,0 +1,181 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MSM_IPC_ROUTER_H
+#define _MSM_IPC_ROUTER_H
+
+#include <linux/types.h>
+#include <linux/socket.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/wakelock.h>
+#include <linux/msm_ipc.h>
+
+#define MAX_WAKELOCK_NAME_SZ 32
+
+/**
+ * enum msm_ipc_router_event - Events that will be generated by IPC Router
+ */
+enum msm_ipc_router_event {
+ MSM_IPC_ROUTER_READ_CB = 0,
+ MSM_IPC_ROUTER_WRITE_DONE,
+};
+
+struct msm_ipc_port {
+ struct list_head list;
+
+ struct msm_ipc_port_addr this_port;
+ struct msm_ipc_port_name port_name;
+ uint32_t type;
+ unsigned flags;
+ spinlock_t port_lock;
+
+ struct list_head incomplete;
+ struct mutex incomplete_lock;
+
+ struct list_head port_rx_q;
+ struct mutex port_rx_q_lock;
+ char rx_wakelock_name[MAX_WAKELOCK_NAME_SZ];
+ struct wake_lock port_rx_wake_lock;
+ wait_queue_head_t port_rx_wait_q;
+
+ int restart_state;
+ spinlock_t restart_lock;
+ wait_queue_head_t restart_wait;
+
+ void *endpoint;
+ void (*notify)(unsigned event, void *priv);
+
+ uint32_t num_tx;
+ uint32_t num_rx;
+ unsigned long num_tx_bytes;
+ unsigned long num_rx_bytes;
+ void *priv;
+};
+
+#ifdef CONFIG_MSM_IPC_ROUTER
+/**
+ * msm_ipc_router_create_port() - Create a IPC Router port/endpoint
+ * @notify: Callback function to notify any event on the port.
+ * @priv: Private info to be passed while the notification is generated.
+ *
+ * @return: Pointer to the port on success, NULL on error.
+ */
+struct msm_ipc_port *msm_ipc_router_create_port(
+ void (*notify)(unsigned event, void *priv),
+ void *priv);
+
+/**
+ * msm_ipc_router_lookup_server_name() - Resolve server address
+ * @srv_name: Name<service:instance> of the server to be resolved.
+ * @srv_info: Buffer to hold the resolved address.
+ * @num_entries_in_array: Number of server info the buffer can hold.
+ * @lookup_mask: Mask to specify the range of instances to be resolved.
+ *
+ * @return: Number of server addresses resolved on success, < 0 on error.
+ */
+int msm_ipc_router_lookup_server_name(struct msm_ipc_port_name *srv_name,
+ struct msm_ipc_server_info *srv_info,
+ int num_entries_in_array,
+ uint32_t lookup_mask);
+
+/**
+ * msm_ipc_router_send_msg() - Send a message/packet
+ * @src: Sender's address/port.
+ * @dest: Destination address.
+ * @data: Pointer to the data to be sent.
+ * @data_len: Length of the data to be sent.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int msm_ipc_router_send_msg(struct msm_ipc_port *src,
+ struct msm_ipc_addr *dest,
+ void *data, unsigned int data_len);
+
+/**
+ * msm_ipc_router_get_curr_pkt_size() - Get the packet size of the first
+ * packet in the rx queue
+ * @port_ptr: Port which owns the rx queue.
+ *
+ * @return: Returns the size of the first packet, if available.
+ * 0 if no packets available, < 0 on error.
+ */
+int msm_ipc_router_get_curr_pkt_size(struct msm_ipc_port *port_ptr);
+
+/**
+ * msm_ipc_router_read_msg() - Read a message/packet
+ * @port_ptr: Receiver's port/address.
+ * @data: Pointer containing the address of the received data.
+ * @src: Address of the sender/source.
+ * @len: Length of the data being read.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int msm_ipc_router_read_msg(struct msm_ipc_port *port_ptr,
+ struct msm_ipc_addr *src,
+ unsigned char **data,
+ unsigned int *len);
+
+/**
+ * msm_ipc_router_close_port() - Close the port
+ * @port_ptr: Pointer to the port to be closed.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int msm_ipc_router_close_port(struct msm_ipc_port *port_ptr);
+
+#else
+
+struct msm_ipc_port *msm_ipc_router_create_port(
+ void (*notify)(unsigned event, void *priv),
+ void *priv)
+{
+ return NULL;
+}
+
+int msm_ipc_router_lookup_server_name(struct msm_ipc_port_name *srv_name,
+ struct msm_ipc_server_info *srv_info,
+ int num_entries_in_array,
+ uint32_t lookup_mask)
+{
+ return -ENODEV;
+}
+
+int msm_ipc_router_send_msg(struct msm_ipc_port *src,
+ struct msm_ipc_addr *dest,
+ void *data, unsigned int data_len)
+{
+ return -ENODEV;
+}
+
+int msm_ipc_router_get_curr_pkt_size(struct msm_ipc_port *port_ptr)
+{
+ return -ENODEV;
+}
+
+int msm_ipc_router_read_msg(struct msm_ipc_port *port_ptr,
+ struct msm_ipc_addr *src,
+ unsigned char **data,
+ unsigned int *len)
+{
+ return -ENODEV;
+}
+
+int msm_ipc_router_close_port(struct msm_ipc_port *port_ptr)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_qmi_interface.h b/arch/arm/mach-msm/include/mach/msm_qmi_interface.h
new file mode 100644
index 0000000..11867f3
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_qmi_interface.h
@@ -0,0 +1,280 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MSM_QMI_INTERFACE_H_
+#define _MSM_QMI_INTERFACE_H_
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/socket.h>
+#include <linux/gfp.h>
+#include <linux/qmi_encdec.h>
+
+#define QMI_COMMON_TLV_TYPE 0
+
+enum qmi_event_type {
+ QMI_RECV_MSG = 1,
+ QMI_SERVER_ARRIVE,
+ QMI_SERVER_EXIT,
+};
+
+struct qmi_handle {
+ void *src_port;
+ void *dest_info;
+ uint16_t next_txn_id;
+ struct list_head txn_list;
+ struct mutex handle_lock;
+ spinlock_t notify_lock;
+ void (*notify)(struct qmi_handle *handle, enum qmi_event_type event,
+ void *notify_priv);
+ void *notify_priv;
+ void (*ind_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ unsigned int msg_len, void *ind_cb_priv);
+ void *ind_cb_priv;
+ int handle_reset;
+ wait_queue_head_t reset_waitq;
+};
+
+enum qmi_result_type_v01 {
+ /* To force a 32 bit signed enum. Do not change or use*/
+ QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
+ QMI_RESULT_SUCCESS_V01 = 0,
+ QMI_RESULT_FAILURE_V01 = 1,
+ QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
+};
+
+enum qmi_error_type_v01 {
+ /* To force a 32 bit signed enum. Do not change or use*/
+ QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
+ QMI_ERR_NONE_V01 = 0x0000,
+ QMI_ERROR_MALFORMED_MSG_V01 = 0x0001,
+ QMI_ERR_NO_MEMORY_V01 = 0x0002,
+ QMI_ERR_INTERNAL_V01 = 0x0003,
+ QMI_ERR_INVALID_ID_V01 = 0x0029,
+ QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A,
+ QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
+};
+
+struct qmi_response_type_v01 {
+ enum qmi_result_type_v01 result;
+ enum qmi_error_type_v01 error;
+};
+
+#ifdef CONFIG_MSM_QMI_INTERFACE
+
+/* Element info array describing common qmi response structure */
+extern struct elem_info qmi_response_type_v01_ei[];
+#define get_qmi_response_type_v01_ei() qmi_response_type_v01_ei
+
+/**
+ * qmi_handle_create() - Create a QMI handle
+ * @notify: Callback to notify events on the handle created.
+ * @notify_priv: Private information to be passed along with the notification.
+ *
+ * @return: Valid QMI handle on success, NULL on error.
+ */
+struct qmi_handle *qmi_handle_create(
+ void (*notify)(struct qmi_handle *handle,
+ enum qmi_event_type event, void *notify_priv),
+ void *notify_priv);
+
+/**
+ * qmi_handle_destroy() - Destroy the QMI handle
+ * @handle: QMI handle to be destroyed.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_handle_destroy(struct qmi_handle *handle);
+
+/**
+ * qmi_register_ind_cb() - Register the indication callback function
+ * @handle: QMI handle with which the function is registered.
+ * @ind_cb: Callback function to be registered.
+ * @ind_cb_priv: Private data to be passed with the indication callback.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_register_ind_cb(struct qmi_handle *handle,
+ void (*ind_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ unsigned int msg_len, void *ind_cb_priv),
+ void *ind_cb_priv);
+
+/**
+ * qmi_send_req_wait() - Send a synchronous QMI request
+ * @handle: QMI handle through which the QMI request is sent.
+ * @request_desc: Structure describing the request data structure.
+ * @req: Buffer containing the request data structure.
+ * @req_len: Length of the request data structure.
+ * @resp_desc: Structure describing the response data structure.
+ * @resp: Buffer to hold the response data structure.
+ * @resp_len: Length of the response data structure.
+ * @timeout_ms: Timeout before a response is received.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_send_req_wait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ unsigned long timeout_ms);
+
+/**
+ * qmi_send_req_nowait() - Send an asynchronous QMI request
+ * @handle: QMI handle through which the QMI request is sent.
+ * @request_desc: Structure describing the request data structure.
+ * @req: Buffer containing the request data structure.
+ * @req_len: Length of the request data structure.
+ * @resp_desc: Structure describing the response data structure.
+ * @resp: Buffer to hold the response data structure.
+ * @resp_len: Length of the response data structure.
+ * @resp_cb: Callback function to be invoked when the response arrives.
+ * @resp_cb_data: Private information to be passed along with the callback.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_send_req_nowait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ void (*resp_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ void *resp_cb_data),
+ void *resp_cb_data);
+
+/**
+ * qmi_recv_msg() - Receive the QMI message
+ * @handle: Handle for which the QMI message has to be received.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_recv_msg(struct qmi_handle *handle);
+
+/**
+ * qmi_connect_to_service() - Connect the QMI handle with a QMI service
+ * @handle: QMI handle to be connected with the QMI service.
+ * @service_id: Service id to identify the QMI service.
+ * @instance_id: Instance id to identify the instance of the QMI service.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_connect_to_service(struct qmi_handle *handle,
+ uint32_t service_id, uint32_t instance_id);
+
+/**
+ * qmi_svc_event_notifier_register() - Register a notifier block to receive
+ * events regarding a QMI service
+ * @service_id: Service ID to identify the QMI service.
+ * @instance_id: Instance ID to identify the instance of the QMI service.
+ * @nb: Notifier block used to receive the event.
+ *
+ * @return: 0 if successfully registered, < 0 on error.
+ */
+int qmi_svc_event_notifier_register(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb);
+
+/**
+ * qmi_svc_event_notifier_unregister() - Unregister service event
+ * notifier block
+ * @service_id: Service ID to identify the QMI service.
+ * @instance_id: Instance ID to identify the instance of the QMI service.
+ * @nb: Notifier block registered to receive the events.
+ *
+ * @return: 0 if successfully registered, < 0 on error.
+ */
+int qmi_svc_event_notifier_unregister(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb);
+#else
+
+#define get_qmi_response_type_v01_ei() NULL
+
+static inline struct qmi_handle *qmi_handle_create(
+ void (*notify)(struct qmi_handle *handle,
+ enum qmi_event_type event, void *notify_priv),
+ void *notify_priv)
+{
+ return NULL;
+}
+
+static inline int qmi_handle_destroy(struct qmi_handle *handle)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_register_ind_cb(struct qmi_handle *handle,
+ void (*ind_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ unsigned int msg_len, void *ind_cb_priv),
+ void *ind_cb_priv)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_send_req_wait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ unsigned long timeout_ms)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_send_req_nowait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ void (*resp_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ void *resp_cb_data),
+ void *resp_cb_data)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_recv_msg(struct qmi_handle *handle)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_connect_to_service(struct qmi_handle *handle,
+ uint32_t service_id,
+ uint32_t instance_id)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_svc_event_notifier_register(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb)
+{
+ return -ENODEV;
+}
+
+static inline int qmi_svc_event_notifier_unregister(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smsm.h b/arch/arm/mach-msm/include/mach/msm_smsm.h
index 44b52b6..c77c181 100644
--- a/arch/arm/mach-msm/include/mach/msm_smsm.h
+++ b/arch/arm/mach-msm/include/mach/msm_smsm.h
@@ -83,7 +83,7 @@
#define SMSM_WKUP_REASON_TIMER 0x00000008
#define SMSM_WKUP_REASON_ALARM 0x00000010
#define SMSM_WKUP_REASON_RESET 0x00000020
-#define SMSM_A2_FORCE_SHUTDOWN 0x00002000
+#define SMSM_USB_PLUG_UNPLUG 0x00002000
#define SMSM_A2_RESET_BAM 0x00004000
#define SMSM_VENDOR 0x00020000
diff --git a/arch/arm/mach-msm/include/mach/msm_tspp.h b/arch/arm/mach-msm/include/mach/msm_tspp.h
index 5395b88..a024a99 100644
--- a/arch/arm/mach-msm/include/mach/msm_tspp.h
+++ b/arch/arm/mach-msm/include/mach/msm_tspp.h
@@ -25,31 +25,34 @@
struct tspp_data_descriptor {
void *virt_base; /* logical address of the actual data */
u32 phys_base; /* physical address of the actual data */
- int size; /* size of buffer in bytes */
+ u32 size; /* size of buffer in bytes */
int id; /* unique identifier */
void *user; /* user-defined data */
};
-typedef void (tspp_notifier)(int channel, void *user);
-typedef void* (tspp_allocator)(int channel, int size,
+typedef void (tspp_notifier)(int channel_id, void *user);
+typedef void* (tspp_allocator)(int channel_id, u32 size,
u32 *phys_base, void *user);
+typedef void (tspp_memfree)(int channel_id, u32 size,
+ void *virt_base, u32 phys_base, void *user);
/* Kernel API functions */
int tspp_open_stream(u32 dev, u32 channel_id,
- struct tspp_select_source *source);
+ struct tspp_select_source *source);
int tspp_close_stream(u32 dev, u32 channel_id);
int tspp_open_channel(u32 dev, u32 channel_id);
int tspp_close_channel(u32 dev, u32 channel_id);
-int tspp_add_filter(u32 dev, u32 channel_id, struct tspp_filter *filter);
+int tspp_add_filter(u32 dev, u32 channel_id, struct tspp_filter *filter);
int tspp_remove_filter(u32 dev, u32 channel_id, struct tspp_filter *filter);
int tspp_set_key(u32 dev, u32 channel_id, struct tspp_key *key);
-int tspp_register_notification(u32 dev, u32 channel, tspp_notifier *notify,
+int tspp_register_notification(u32 dev, u32 channel_id, tspp_notifier *notify,
void *data, u32 timer_ms);
-int tspp_unregister_notification(u32 dev, u32 channel);
-const struct tspp_data_descriptor *tspp_get_buffer(u32 dev, u32 channel);
-int tspp_release_buffer(u32 dev, u32 channel, u32 descriptor_id);
+int tspp_unregister_notification(u32 dev, u32 channel_id);
+const struct tspp_data_descriptor *tspp_get_buffer(u32 dev, u32 channel_id);
+int tspp_release_buffer(u32 dev, u32 channel_id, u32 descriptor_id);
int tspp_allocate_buffers(u32 dev, u32 channel_id, u32 count,
- u32 size, u32 int_freq, tspp_allocator *alloc, void *user);
+ u32 size, u32 int_freq, tspp_allocator *alloc,
+ tspp_memfree *memfree, void *user);
#endif /* _MSM_TSPP_H_ */
diff --git a/arch/arm/mach-msm/include/mach/peripheral-loader.h b/arch/arm/mach-msm/include/mach/peripheral-loader.h
deleted file mode 100644
index 327c82f..0000000
--- a/arch/arm/mach-msm/include/mach/peripheral-loader.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_PERIPHERAL_LOADER_H
-#define __MACH_PERIPHERAL_LOADER_H
-
-#ifdef CONFIG_MSM_PIL
-extern void *pil_get(const char *name);
-extern void pil_put(void *peripheral_handle);
-extern void pil_force_shutdown(const char *name);
-extern int pil_force_boot(const char *name);
-#else
-static inline void *pil_get(const char *name) { return NULL; }
-static inline void pil_put(void *peripheral_handle) { }
-static inline void pil_force_shutdown(const char *name) { }
-static inline int pil_force_boot(const char *name) { return -ENOSYS; }
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
index d34536d..88cb94a 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
@@ -14,7 +14,7 @@
#define _AUDIO_ACDB_H
#include <linux/msm_audio_acdb.h>
-#ifdef CONFIG_ARCH_MSM8974
+#if defined CONFIG_ARCH_MSM8974 || defined CONFIG_ARCH_MSM9625
#include <sound/q6adm-v2.h>
#else
#include <sound/q6adm.h>
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index 34bdc79..0499a7a 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -111,6 +111,7 @@
MSM_CPU_8092,
MSM_CPU_8226,
MSM_CPU_8910,
+ MSM_CPU_8625Q,
};
enum pmic_model {
@@ -447,6 +448,18 @@
#endif
}
+static inline int cpu_is_msm8625q(void)
+{
+#ifdef CONFIG_ARCH_MSM8625
+ enum msm_cpu cpu = socinfo_get_msm_cpu();
+
+ BUG_ON(cpu == MSM_CPU_UNKNOWN);
+ return cpu == MSM_CPU_8625Q;
+#else
+ return 0;
+#endif
+}
+
static inline int soc_class_is_msm8960(void)
{
return cpu_is_msm8960() || cpu_is_msm8960ab();
diff --git a/arch/arm/mach-msm/include/mach/subsystem_restart.h b/arch/arm/mach-msm/include/mach/subsystem_restart.h
index a95e943..64190d2 100644
--- a/arch/arm/mach-msm/include/mach/subsystem_restart.h
+++ b/arch/arm/mach-msm/include/mach/subsystem_restart.h
@@ -70,6 +70,8 @@
extern struct subsys_device *subsys_register(struct subsys_desc *desc);
extern void subsys_unregister(struct subsys_device *dev);
+extern void subsys_default_online(struct subsys_device *dev);
+
#else
static inline int get_restart_level(void)
@@ -102,6 +104,8 @@
static inline void subsys_unregister(struct subsys_device *dev) { }
+static inline void subsys_default_online(struct subsys_device *dev) { }
+
#endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index c2c9233..52bb8ef 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -430,6 +430,8 @@
MSM_CHIP_DEVICE(CLK_CTL, MSM8625),
MSM_CHIP_DEVICE(SAW0, MSM8625),
MSM_CHIP_DEVICE(SAW1, MSM8625),
+ MSM_CHIP_DEVICE(SAW2, MSM8625),
+ MSM_CHIP_DEVICE(SAW3, MSM8625),
MSM_CHIP_DEVICE(AD5, MSM7XXX),
MSM_CHIP_DEVICE(MDC, MSM7XXX),
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
@@ -517,7 +519,6 @@
MSM_CHIP_DEVICE(APCS_GCC, MSM8226),
MSM_CHIP_DEVICE(TLMM, MSM8226),
MSM_CHIP_DEVICE(IMEM, MSM8226),
- MSM_CHIP_DEVICE(DBG_IMEM, MSM8226),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.length = MSM_SHARED_RAM_SIZE,
@@ -540,6 +541,7 @@
static struct map_desc msm8910_io_desc[] __initdata = {
MSM_CHIP_DEVICE(APCS_GCC, MSM8910),
MSM_CHIP_DEVICE(TLMM, MSM8910),
+ MSM_CHIP_DEVICE(MPM2_PSHOLD, MSM8910),
MSM_CHIP_DEVICE(IMEM, MSM8910),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
diff --git a/arch/arm/mach-msm/ipc_router.c b/arch/arm/mach-msm/ipc_router.c
index 3a632e5..8f1d197 100644
--- a/arch/arm/mach-msm/ipc_router.c
+++ b/arch/arm/mach-msm/ipc_router.c
@@ -33,6 +33,7 @@
#include <mach/smem_log.h>
#include <mach/subsystem_notif.h>
+#include <mach/msm_ipc_router.h>
#include "ipc_router.h"
#include "modem_notifier.h"
@@ -111,11 +112,14 @@
struct msm_ipc_server {
struct list_head list;
struct msm_ipc_port_name name;
+ char pdev_name[32];
+ int next_pdev_id;
struct list_head server_port_list;
};
struct msm_ipc_server_port {
struct list_head list;
+ struct platform_device pdev;
struct msm_ipc_port_addr server_addr;
struct msm_ipc_router_xprt_info *xprt_info;
};
@@ -366,6 +370,102 @@
return;
}
+static struct sk_buff_head *msm_ipc_router_buf_to_skb(void *buf,
+ unsigned int buf_len)
+{
+ struct sk_buff_head *skb_head;
+ struct sk_buff *skb;
+ int first = 1, offset = 0;
+ int skb_size, data_size;
+ void *data;
+
+ skb_head = kmalloc(sizeof(struct sk_buff_head), GFP_KERNEL);
+ if (!skb_head) {
+ pr_err("%s: Couldnot allocate skb_head\n", __func__);
+ return NULL;
+ }
+ skb_queue_head_init(skb_head);
+
+ data_size = buf_len;
+ while (offset != buf_len) {
+ skb_size = data_size;
+ if (first)
+ skb_size += IPC_ROUTER_HDR_SIZE;
+
+ skb = alloc_skb(skb_size, GFP_KERNEL);
+ if (!skb) {
+ if (skb_size <= (PAGE_SIZE/2)) {
+ pr_err("%s: cannot allocate skb\n", __func__);
+ goto buf_to_skb_error;
+ }
+ data_size = data_size / 2;
+ continue;
+ }
+
+ if (first) {
+ skb_reserve(skb, IPC_ROUTER_HDR_SIZE);
+ first = 0;
+ }
+
+ data = skb_put(skb, data_size);
+ memcpy(skb->data, buf + offset, data_size);
+ skb_queue_tail(skb_head, skb);
+ offset += data_size;
+ data_size = buf_len - offset;
+ }
+ return skb_head;
+
+buf_to_skb_error:
+ while (!skb_queue_empty(skb_head)) {
+ skb = skb_dequeue(skb_head);
+ kfree_skb(skb);
+ }
+ kfree(skb_head);
+ return NULL;
+}
+
+static void *msm_ipc_router_skb_to_buf(struct sk_buff_head *skb_head,
+ unsigned int len)
+{
+ struct sk_buff *temp;
+ int offset = 0, buf_len = 0, copy_len;
+ void *buf;
+
+ if (!skb_head) {
+ pr_err("%s: NULL skb_head\n", __func__);
+ return NULL;
+ }
+
+ temp = skb_peek(skb_head);
+ buf_len = len;
+ buf = kmalloc(buf_len, GFP_KERNEL);
+ if (!buf) {
+ pr_err("%s: cannot allocate buf\n", __func__);
+ return NULL;
+ }
+ skb_queue_walk(skb_head, temp) {
+ copy_len = buf_len < temp->len ? buf_len : temp->len;
+ memcpy(buf + offset, temp->data, copy_len);
+ offset += copy_len;
+ buf_len -= copy_len;
+ }
+ return buf;
+}
+
+static void msm_ipc_router_free_skb(struct sk_buff_head *skb_head)
+{
+ struct sk_buff *temp_skb;
+
+ if (!skb_head)
+ return;
+
+ while (!skb_queue_empty(skb_head)) {
+ temp_skb = skb_dequeue(skb_head);
+ kfree_skb(temp_skb);
+ }
+ kfree(skb_head);
+}
+
static int post_control_ports(struct rr_packet *pkt)
{
struct msm_ipc_port *port_ptr;
@@ -437,8 +537,7 @@
}
struct msm_ipc_port *msm_ipc_router_create_raw_port(void *endpoint,
- void (*notify)(unsigned event, void *data,
- void *addr, void *priv),
+ void (*notify)(unsigned event, void *priv),
void *priv)
{
struct msm_ipc_port *port_ptr;
@@ -628,6 +727,10 @@
return NULL;
}
+static void dummy_release(struct device *dev)
+{
+}
+
/**
* msm_ipc_router_create_server() - Add server info to hash table
* @service: Service ID of the server info to be created.
@@ -660,7 +763,7 @@
goto create_srv_port;
}
- server = kmalloc(sizeof(struct msm_ipc_server), GFP_KERNEL);
+ server = kzalloc(sizeof(struct msm_ipc_server), GFP_KERNEL);
if (!server) {
pr_err("%s: Server allocation failed\n", __func__);
return NULL;
@@ -669,9 +772,12 @@
server->name.instance = instance;
INIT_LIST_HEAD(&server->server_port_list);
list_add_tail(&server->list, &server_list[key]);
+ scnprintf(server->pdev_name, sizeof(server->pdev_name),
+ "QMI%08x:%08x", service, instance);
+ server->next_pdev_id = 1;
create_srv_port:
- server_port = kmalloc(sizeof(struct msm_ipc_server_port), GFP_KERNEL);
+ server_port = kzalloc(sizeof(struct msm_ipc_server_port), GFP_KERNEL);
if (!server_port) {
if (list_empty(&server->server_port_list)) {
list_del(&server->list);
@@ -685,6 +791,11 @@
server_port->xprt_info = xprt_info;
list_add_tail(&server_port->list, &server->server_port_list);
+ server_port->pdev.name = server->pdev_name;
+ server_port->pdev.id = server->next_pdev_id++;
+ server_port->pdev.dev.release = dummy_release;
+ platform_device_register(&server_port->pdev);
+
return server;
}
@@ -714,6 +825,7 @@
break;
}
if (server_port) {
+ platform_device_unregister(&server_port->pdev);
list_del(&server_port->list);
kfree(server_port);
}
@@ -815,7 +927,6 @@
ctl.cmd = IPC_ROUTER_CTRL_CMD_NEW_SERVER;
- mutex_lock(&server_list_lock);
for (i = 0; i < SRV_HASH_SIZE; i++) {
list_for_each_entry(server, &server_list[i], list) {
ctl.srv.service = server->name.service;
@@ -835,7 +946,6 @@
}
}
}
- mutex_unlock(&server_list_lock);
return 0;
}
@@ -1081,6 +1191,7 @@
ctl.srv.port_id = svr_port->server_addr.port_id;
relay_ctl_msg(xprt_info, &ctl);
broadcast_ctl_msg_locally(&ctl);
+ platform_device_unregister(&svr_port->pdev);
list_del(&svr_port->list);
kfree(svr_port);
}
@@ -1255,6 +1366,7 @@
* Send list of servers from the local node and from nodes
* outside the mesh network in which this XPRT is part of.
*/
+ mutex_lock(&server_list_lock);
mutex_lock(&routing_table_lock);
for (i = 0; i < RT_HASH_SIZE; i++) {
list_for_each_entry(rt_entry, &routing_table[i], list) {
@@ -1266,11 +1378,13 @@
xprt_info);
if (rc < 0) {
mutex_unlock(&routing_table_lock);
+ mutex_unlock(&server_list_lock);
return rc;
}
}
}
mutex_unlock(&routing_table_lock);
+ mutex_unlock(&server_list_lock);
RR("HELLO message processed\n");
return rc;
}
@@ -1431,7 +1545,6 @@
struct rr_packet *pkt = NULL;
struct msm_ipc_port *port_ptr;
struct sk_buff *head_skb;
- struct msm_ipc_port_addr *src_addr;
struct msm_ipc_router_remote_port *rport_ptr;
uint32_t resume_tx, resume_tx_node_id, resume_tx_port_id;
@@ -1526,30 +1639,15 @@
}
}
- if (!port_ptr->notify) {
- mutex_lock(&port_ptr->port_rx_q_lock);
- wake_lock(&port_ptr->port_rx_wake_lock);
- list_add_tail(&pkt->list, &port_ptr->port_rx_q);
- wake_up(&port_ptr->port_rx_wait_q);
- mutex_unlock(&port_ptr->port_rx_q_lock);
- mutex_unlock(&local_ports_lock);
- } else {
- mutex_lock(&port_ptr->port_rx_q_lock);
- src_addr = kmalloc(sizeof(struct msm_ipc_port_addr),
- GFP_KERNEL);
- if (src_addr) {
- src_addr->node_id = hdr->src_node_id;
- src_addr->port_id = hdr->src_port_id;
- }
- skb_pull(head_skb, IPC_ROUTER_HDR_SIZE);
- mutex_unlock(&local_ports_lock);
+ mutex_lock(&port_ptr->port_rx_q_lock);
+ wake_lock(&port_ptr->port_rx_wake_lock);
+ list_add_tail(&pkt->list, &port_ptr->port_rx_q);
+ wake_up(&port_ptr->port_rx_wait_q);
+ if (port_ptr->notify)
port_ptr->notify(MSM_IPC_ROUTER_READ_CB,
- pkt->pkt_fragment_q, src_addr, port_ptr->priv);
- mutex_unlock(&port_ptr->port_rx_q_lock);
- pkt->pkt_fragment_q = NULL;
- src_addr = NULL;
- release_pkt(pkt);
- }
+ port_ptr->priv);
+ mutex_unlock(&port_ptr->port_rx_q_lock);
+ mutex_unlock(&local_ports_lock);
process_done:
if (resume_tx) {
@@ -1903,6 +2001,28 @@
return ret;
}
+int msm_ipc_router_send_msg(struct msm_ipc_port *src,
+ struct msm_ipc_addr *dest,
+ void *data, unsigned int data_len)
+{
+ struct sk_buff_head *out_skb_head;
+ int ret;
+
+ out_skb_head = msm_ipc_router_buf_to_skb(data, data_len);
+ if (!out_skb_head) {
+ pr_err("%s: SKB conversion failed\n", __func__);
+ return -EFAULT;
+ }
+
+ ret = msm_ipc_router_send_to(src, out_skb_head, dest);
+ if (ret < 0) {
+ pr_err("%s: msm_ipc_router_send_to failed - ret: %d\n",
+ __func__, ret);
+ msm_ipc_router_free_skb(out_skb_head);
+ }
+ return 0;
+}
+
int msm_ipc_router_read(struct msm_ipc_port *port_ptr,
struct sk_buff_head **data,
size_t buf_len)
@@ -1938,7 +2058,7 @@
int msm_ipc_router_recv_from(struct msm_ipc_port *port_ptr,
struct sk_buff_head **data,
struct msm_ipc_addr *src,
- unsigned long timeout)
+ long timeout)
{
int ret, data_len, align_size;
struct sk_buff *temp_skb;
@@ -1995,11 +2115,42 @@
return data_len;
}
+int msm_ipc_router_read_msg(struct msm_ipc_port *port_ptr,
+ struct msm_ipc_addr *src,
+ unsigned char **data,
+ unsigned int *len)
+{
+ struct sk_buff_head *in_skb_head;
+ int ret;
+
+ ret = msm_ipc_router_recv_from(port_ptr, &in_skb_head, src, -1);
+ if (ret < 0) {
+ pr_err("%s: msm_ipc_router_recv_from failed - ret: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ *data = msm_ipc_router_skb_to_buf(in_skb_head, ret);
+ if (!(*data))
+ pr_err("%s: Buf conversion failed\n", __func__);
+
+ *len = ret;
+ msm_ipc_router_free_skb(in_skb_head);
+ return 0;
+}
+
struct msm_ipc_port *msm_ipc_router_create_port(
- void (*notify)(unsigned event, void *data, void *addr, void *priv),
+ void (*notify)(unsigned event, void *priv),
void *priv)
{
struct msm_ipc_port *port_ptr;
+ int ret;
+
+ ret = wait_for_completion_interruptible(&msm_ipc_local_router_up);
+ if (ret < 0) {
+ pr_err("%s: Error waiting for local router\n", __func__);
+ return NULL;
+ }
port_ptr = msm_ipc_router_create_raw_port(NULL, notify, priv);
if (!port_ptr)
diff --git a/arch/arm/mach-msm/ipc_router.h b/arch/arm/mach-msm/ipc_router.h
index 07bc5e0..39038f2 100644
--- a/arch/arm/mach-msm/ipc_router.h
+++ b/arch/arm/mach-msm/ipc_router.h
@@ -18,22 +18,18 @@
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/list.h>
-#include <linux/cdev.h>
#include <linux/platform_device.h>
-#include <linux/wakelock.h>
#include <linux/msm_ipc.h>
#include <net/sock.h>
/* definitions for the R2R wire protcol */
#define IPC_ROUTER_VERSION 1
-#define IPC_ROUTER_PROCESSORS_MAX 4
#define IPC_ROUTER_CLIENT_BCAST_ID 0xffffffff
#define IPC_ROUTER_ADDRESS 0xfffffffe
#define IPC_ROUTER_NID_LOCAL 1
-#define IPC_ROUTER_NID_REMOTE 0
#define IPC_ROUTER_CTRL_CMD_DATA 1
#define IPC_ROUTER_CTRL_CMD_HELLO 2
@@ -51,18 +47,11 @@
#define IPC_ROUTER_XPRT_EVENT_OPEN 2
#define IPC_ROUTER_XPRT_EVENT_CLOSE 3
-#define NUM_NODES 2
-
#define IPC_ROUTER_INFINITY -1
#define DEFAULT_RCV_TIMEO IPC_ROUTER_INFINITY
#define ALIGN_SIZE(x) ((4 - ((x) & 3)) & 3)
-enum {
- MSM_IPC_ROUTER_READ_CB = 0,
- MSM_IPC_ROUTER_WRITE_DONE,
-};
-
union rr_control_msg {
uint32_t cmd;
struct {
@@ -92,10 +81,6 @@
#define IPC_ROUTER_HDR_SIZE sizeof(struct rr_header)
#define MAX_IPC_PKT_SIZE 66000
-/* internals */
-
-#define IPC_ROUTER_MAX_REMOTE_SERVERS 100
-#define MAX_WAKELOCK_NAME_SZ 32
struct rr_packet {
struct list_head list;
@@ -103,50 +88,12 @@
uint32_t length;
};
-struct msm_ipc_port {
- struct list_head list;
-
- struct msm_ipc_port_addr this_port;
- struct msm_ipc_port_name port_name;
- uint32_t type;
- unsigned flags;
- spinlock_t port_lock;
-
- struct list_head incomplete;
- struct mutex incomplete_lock;
-
- struct list_head port_rx_q;
- struct mutex port_rx_q_lock;
- char rx_wakelock_name[MAX_WAKELOCK_NAME_SZ];
- struct wake_lock port_rx_wake_lock;
- wait_queue_head_t port_rx_wait_q;
-
- int restart_state;
- spinlock_t restart_lock;
- wait_queue_head_t restart_wait;
-
- void *endpoint;
- void (*notify)(unsigned event, void *data, void *addr, void *priv);
-
- uint32_t num_tx;
- uint32_t num_rx;
- unsigned long num_tx_bytes;
- unsigned long num_rx_bytes;
- void *priv;
-};
-
struct msm_ipc_sock {
struct sock sk;
struct msm_ipc_port *port;
void *default_pil;
};
-enum write_data_type {
- HEADER = 1,
- PACKMARK,
- PAYLOAD,
-};
-
struct msm_ipc_router_xprt {
char *name;
uint32_t link_id;
@@ -161,8 +108,6 @@
int (*close)(struct msm_ipc_router_xprt *xprt);
};
-extern struct completion msm_ipc_remote_router_up;
-
void msm_ipc_router_xprt_notify(struct msm_ipc_router_xprt *xprt,
unsigned event,
void *data);
@@ -173,8 +118,7 @@
struct msm_ipc_port *msm_ipc_router_create_raw_port(void *endpoint,
- void (*notify)(unsigned event, void *data,
- void *addr, void *priv),
+ void (*notify)(unsigned event, void *priv),
void *priv);
int msm_ipc_router_send_to(struct msm_ipc_port *src,
struct sk_buff_head *data,
@@ -182,27 +126,16 @@
int msm_ipc_router_read(struct msm_ipc_port *port_ptr,
struct sk_buff_head **data,
size_t buf_len);
-int msm_ipc_router_get_curr_pkt_size(struct msm_ipc_port *port_ptr);
int msm_ipc_router_bind_control_port(struct msm_ipc_port *port_ptr);
-int msm_ipc_router_lookup_server_name(struct msm_ipc_port_name *srv_name,
- struct msm_ipc_server_info *srv_info,
- int num_entries_in_array,
- uint32_t lookup_mask);
-int msm_ipc_router_close_port(struct msm_ipc_port *port_ptr);
-struct msm_ipc_port *msm_ipc_router_create_port(
- void (*notify)(unsigned event, void *data,
- void *addr, void *priv),
- void *priv);
int msm_ipc_router_recv_from(struct msm_ipc_port *port_ptr,
struct sk_buff_head **data,
struct msm_ipc_addr *src_addr,
- unsigned long timeout);
+ long timeout);
int msm_ipc_router_register_server(struct msm_ipc_port *server_port,
struct msm_ipc_addr *name);
int msm_ipc_router_unregister_server(struct msm_ipc_port *server_port);
-
int msm_ipc_router_init_sockets(void);
void msm_ipc_router_exit_sockets(void);
diff --git a/arch/arm/mach-msm/ipc_router_smd_xprt.c b/arch/arm/mach-msm/ipc_router_smd_xprt.c
index b2e6490..8c0bf4b 100644
--- a/arch/arm/mach-msm/ipc_router_smd_xprt.c
+++ b/arch/arm/mach-msm/ipc_router_smd_xprt.c
@@ -20,7 +20,7 @@
#include <linux/types.h>
#include <mach/msm_smd.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include "ipc_router.h"
#include "smd_private.h"
@@ -210,7 +210,7 @@
rc = smd_close(smd_xprtp->channel);
if (smd_xprtp->pil) {
- pil_put(smd_xprtp->pil);
+ subsystem_put(smd_xprtp->pil);
smd_xprtp->pil = NULL;
}
return rc;
@@ -402,7 +402,7 @@
peripheral = smd_edge_to_subsystem(edge);
if (peripheral) {
- pil = pil_get(peripheral);
+ pil = subsystem_get(peripheral);
if (IS_ERR(pil)) {
pr_err("%s: Failed to load %s\n",
__func__, peripheral);
@@ -460,7 +460,7 @@
pr_err("%s: Channel open failed for %s\n",
__func__, smd_xprt_cfg[id].ch_name);
if (smd_remote_xprt[id].pil) {
- pil_put(smd_remote_xprt[id].pil);
+ subsystem_put(smd_remote_xprt[id].pil);
smd_remote_xprt[id].pil = NULL;
}
destroy_workqueue(smd_remote_xprt[id].smd_xprt_wq);
@@ -481,7 +481,7 @@
peripheral = smd_edge_to_subsystem(SMD_APPS_MODEM);
if (peripheral && !strncmp(peripheral, "modem", 6)) {
- pil = pil_get(peripheral);
+ pil = subsystem_get(peripheral);
if (IS_ERR(pil)) {
pr_err("%s: Failed to load %s\n",
__func__, peripheral);
@@ -495,7 +495,7 @@
void msm_ipc_unload_default_node(void *pil)
{
if (pil)
- pil_put(pil);
+ subsystem_put(pil);
}
EXPORT_SYMBOL(msm_ipc_unload_default_node);
diff --git a/arch/arm/mach-msm/ipc_socket.c b/arch/arm/mach-msm/ipc_socket.c
index d3917f1..3a6abbd 100644
--- a/arch/arm/mach-msm/ipc_socket.c
+++ b/arch/arm/mach-msm/ipc_socket.c
@@ -30,6 +30,8 @@
#include <net/sock.h>
+#include <mach/msm_ipc_router.h>
+
#include "ipc_router.h"
#define msm_ipc_sk(sk) ((struct msm_ipc_sock *)(sk))
diff --git a/arch/arm/mach-msm/krait-regulator.c b/arch/arm/mach-msm/krait-regulator.c
index aa9b344..f7b2b1e 100644
--- a/arch/arm/mach-msm/krait-regulator.c
+++ b/arch/arm/mach-msm/krait-regulator.c
@@ -56,16 +56,10 @@
* |_________________|
*/
-#define V_RETENTION 600000
-#define V_LDO_HEADROOM 150000
-
#define PMIC_VOLTAGE_MIN 350000
#define PMIC_VOLTAGE_MAX 1355000
#define LV_RANGE_STEP 5000
-/* use LDO for core voltage below LDO_THRESH */
-#define CORE_VOLTAGE_LDO_THRESH 750000
-
#define LOAD_PER_PHASE 3200000
#define CORE_VOLTAGE_MIN 900000
@@ -161,6 +155,11 @@
int load_uA;
enum krait_supply_mode mode;
void __iomem *reg_base;
+ int ldo_default_uV;
+ int retention_uV;
+ int headroom_uV;
+ int ldo_threshold_uV;
+ bool online;
};
static u32 version;
@@ -200,11 +199,22 @@
return uV;
}
-static int set_krait_ldo_uv(struct krait_power_vreg *kvreg)
+static int set_krait_retention_uv(struct krait_power_vreg *kvreg, int uV)
{
uint32_t reg_val;
- reg_val = kvreg->uV - KRAIT_LDO_VOLTAGE_OFFSET / KRAIT_LDO_STEP;
+ reg_val = DIV_ROUND_UP(uV - KRAIT_LDO_VOLTAGE_OFFSET, KRAIT_LDO_STEP);
+ krait_masked_write(kvreg, APC_LDO_VREF_SET, VREF_RET_MASK,
+ reg_val << VREF_RET_POS);
+
+ return 0;
+}
+
+static int set_krait_ldo_uv(struct krait_power_vreg *kvreg, int uV)
+{
+ uint32_t reg_val;
+
+ reg_val = DIV_ROUND_UP(uV - KRAIT_LDO_VOLTAGE_OFFSET, KRAIT_LDO_STEP);
krait_masked_write(kvreg, APC_LDO_VREF_SET, VREF_LDO_MASK,
reg_val << VREF_LDO_BIT_POS);
@@ -252,7 +262,7 @@
if (kvreg->mode == LDO_MODE)
switch_to_using_hs(kvreg);
- set_krait_ldo_uv(kvreg);
+ set_krait_ldo_uv(kvreg, kvreg->uV);
/*
* enable ldo - note that both LDO and BHS are are supplying voltage to
@@ -300,6 +310,7 @@
}
setpoint = DIV_ROUND_UP(uV, LV_RANGE_STEP);
+
return msm_spm_apcs_set_vdd(setpoint);
}
@@ -310,8 +321,10 @@
int rc = 0;
list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
- if (kvreg->uV > CORE_VOLTAGE_LDO_THRESH
- || kvreg->uV > vmax - V_LDO_HEADROOM) {
+ if (!kvreg->online)
+ continue;
+ if (kvreg->uV > kvreg->ldo_threshold_uV
+ || kvreg->uV > vmax - kvreg->headroom_uV) {
rc = switch_to_using_hs(kvreg);
if (rc < 0) {
pr_err("could not switch %s to hs rc = %d\n",
@@ -434,7 +447,7 @@
return rc;
}
-static int __init pvreg_init(struct platform_device *pdev)
+static int __devinit pvreg_init(struct platform_device *pdev)
{
struct pmic_gang_vreg *pvreg;
@@ -473,6 +486,9 @@
struct pmic_gang_vreg *pvreg = from->pvreg;
list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
+ if (!kvreg->online)
+ continue;
+
v = kvreg->uV;
if (kvreg == from)
@@ -481,6 +497,7 @@
if (vmax < v)
vmax = v;
}
+
return vmax;
}
@@ -490,14 +507,17 @@
struct krait_power_vreg *kvreg;
struct pmic_gang_vreg *pvreg = from->pvreg;
- list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link)
+ list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
+ if (!kvreg->online)
+ continue;
load_total += kvreg->load_uA;
+ }
return load_total;
}
#define ROUND_UP_VOLTAGE(v, res) (DIV_ROUND_UP(v, res) * res)
-static int krait_power_set_voltage(struct regulator_dev *rdev,
+static int _set_voltage(struct regulator_dev *rdev,
int min_uV, int max_uV, unsigned *selector)
{
struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
@@ -505,30 +525,11 @@
int rc;
int vmax;
- /*
- * if the voltage requested is below LDO_THRESHOLD this cpu could
- * switch to LDO mode. Hence round the voltage as per the LDO
- * resolution
- */
- if (min_uV < CORE_VOLTAGE_LDO_THRESH) {
- if (min_uV < KRAIT_LDO_VOLTAGE_MIN)
- min_uV = KRAIT_LDO_VOLTAGE_MIN;
- min_uV = ROUND_UP_VOLTAGE(min_uV, KRAIT_LDO_STEP);
- }
-
- mutex_lock(&pvreg->krait_power_vregs_lock);
-
vmax = get_vmax(kvreg, min_uV);
/* round up the pmic voltage as per its resolution */
vmax = ROUND_UP_VOLTAGE(vmax, LV_RANGE_STEP);
- /*
- * Assign the voltage before updating the gang voltage as we iterate
- * over all the core voltages and choose HS or LDO for each of them
- */
- kvreg->uV = min_uV;
-
rc = pmic_gang_set_voltage(kvreg, vmax);
if (rc < 0) {
dev_err(&rdev->dev, "%s failed set voltage (%d, %d) rc = %d\n",
@@ -539,27 +540,51 @@
pvreg->pmic_vmax_uV = vmax;
out:
+ return rc;
+}
+
+static int krait_power_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ /*
+ * if the voltage requested is below LDO_THRESHOLD this cpu could
+ * switch to LDO mode. Hence round the voltage as per the LDO
+ * resolution
+ */
+ if (min_uV < kvreg->ldo_threshold_uV) {
+ if (min_uV < KRAIT_LDO_VOLTAGE_MIN)
+ min_uV = KRAIT_LDO_VOLTAGE_MIN;
+ min_uV = ROUND_UP_VOLTAGE(min_uV, KRAIT_LDO_STEP);
+ }
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->uV = min_uV;
+
+ if (!kvreg->online) {
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return 0;
+ }
+
+ rc = _set_voltage(rdev, min_uV, max_uV, selector);
mutex_unlock(&pvreg->krait_power_vregs_lock);
+
return rc;
}
#define PMIC_FTS_MODE_PFM 0x00
#define PMIC_FTS_MODE_PWM 0x80
#define PFM_LOAD_UA 500000
-static unsigned int krait_power_get_optimum_mode(struct regulator_dev *rdev,
+static unsigned int _get_optimum_mode(struct regulator_dev *rdev,
int input_uV, int output_uV, int load_uA)
{
struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
struct pmic_gang_vreg *pvreg = kvreg->pvreg;
int rc;
int load_total_uA;
- int reg_mode = -EINVAL;
-
- mutex_lock(&pvreg->krait_power_vregs_lock);
-
- reg_mode = kvreg->mode;
-
- kvreg->load_uA = load_uA;
load_total_uA = get_total_load(kvreg);
@@ -575,8 +600,7 @@
pvreg->pfm_mode = true;
}
}
- mutex_unlock(&pvreg->krait_power_vregs_lock);
- return reg_mode;
+ return kvreg->mode;
}
if (pvreg->pfm_mode) {
@@ -599,8 +623,27 @@
}
out:
+ return kvreg->mode;
+}
+
+static unsigned int krait_power_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->load_uA = load_uA;
+ if (!kvreg->online) {
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return kvreg->mode;
+ }
+
+ rc = _get_optimum_mode(rdev, input_uV, output_uV, load_uA);
mutex_unlock(&pvreg->krait_power_vregs_lock);
- return reg_mode;
+
+ return rc;
}
static int krait_power_set_mode(struct regulator_dev *rdev, unsigned int mode)
@@ -615,12 +658,62 @@
return kvreg->mode;
}
+static int krait_power_is_enabled(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+
+ return kvreg->online;
+}
+
+static int krait_power_enable(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->online = true;
+ rc = _get_optimum_mode(rdev, kvreg->uV, kvreg->uV,
+ kvreg->load_uA);
+ if (rc < 0)
+ goto en_err;
+ rc = _set_voltage(rdev, kvreg->uV,
+ rdev->constraints->max_uV, NULL);
+en_err:
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return rc;
+}
+
+static int krait_power_disable(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->online = false;
+
+ rc = _get_optimum_mode(rdev, kvreg->uV, kvreg->uV,
+ kvreg->load_uA);
+ if (rc < 0)
+ goto dis_err;
+
+ rc = _set_voltage(rdev, kvreg->uV,
+ rdev->constraints->max_uV, NULL);
+dis_err:
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return rc;
+}
+
static struct regulator_ops krait_power_ops = {
.get_voltage = krait_power_get_voltage,
.set_voltage = krait_power_set_voltage,
.get_optimum_mode = krait_power_get_optimum_mode,
.set_mode = krait_power_set_mode,
.get_mode = krait_power_get_mode,
+ .enable = krait_power_enable,
+ .disable = krait_power_disable,
+ .is_enabled = krait_power_is_enabled,
};
static void kvreg_hw_init(struct krait_power_vreg *kvreg)
@@ -638,6 +731,9 @@
/* BHS has six different segments, turn them all on */
krait_masked_write(kvreg, APC_PWR_GATE_CTL,
BHS_SEG_EN_MASK, BHS_SEG_EN_DEFAULT << BHS_SEG_EN_BIT_POS);
+
+ set_krait_retention_uv(kvreg, kvreg->retention_uV);
+ set_krait_ldo_uv(kvreg, kvreg->ldo_default_uV);
}
static void glb_init(struct platform_device *pdev)
@@ -649,12 +745,31 @@
pr_debug("version= 0x%x\n", version);
}
+static int is_between(int left, int right, int value)
+{
+ if (left >= right && left >= value && value >= right)
+ return 1;
+ if (left <= right && left <= value && value <= right)
+ return 1;
+ return 0;
+}
+
+#define LDO_HDROOM_MIN 50000
+#define LDO_HDROOM_MAX 250000
+
+#define LDO_UV_MIN 465000
+#define LDO_UV_MAX 750000
+
+#define LDO_TH_MIN 600000
+#define LDO_TH_MAX 800000
+
static int __devinit krait_power_probe(struct platform_device *pdev)
{
struct krait_power_vreg *kvreg;
struct resource *res;
struct regulator_init_data *init_data = pdev->dev.platform_data;
int rc = 0;
+ int headroom_uV, retention_uV, ldo_default_uV, ldo_threshold_uV;
/* Initialize the pmic gang if it hasn't been initialized already */
if (the_gang == NULL) {
@@ -679,6 +794,57 @@
|= REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE
| REGULATOR_MODE_FAST;
init_data->constraints.input_uV = init_data->constraints.max_uV;
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,headroom-voltage",
+ &headroom_uV);
+ if (rc < 0) {
+ pr_err("headroom-voltage missing rc=%d\n", rc);
+ return rc;
+ }
+ if (!is_between(LDO_HDROOM_MIN, LDO_HDROOM_MAX, headroom_uV)) {
+ pr_err("bad headroom-voltage = %d specified\n",
+ headroom_uV);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,retention-voltage",
+ &retention_uV);
+ if (rc < 0) {
+ pr_err("retention-voltage missing rc=%d\n", rc);
+ return rc;
+ }
+ if (!is_between(LDO_UV_MIN, LDO_UV_MAX, retention_uV)) {
+ pr_err("bad retention-voltage = %d specified\n",
+ retention_uV);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,ldo-default-voltage",
+ &ldo_default_uV);
+ if (rc < 0) {
+ pr_err("ldo-default-voltage missing rc=%d\n", rc);
+ return rc;
+ }
+ if (!is_between(LDO_UV_MIN, LDO_UV_MAX, ldo_default_uV)) {
+ pr_err("bad ldo-default-voltage = %d specified\n",
+ ldo_default_uV);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,ldo-threshold-voltage",
+ &ldo_threshold_uV);
+ if (rc < 0) {
+ pr_err("ldo-threshold-voltage missing rc=%d\n", rc);
+ return rc;
+ }
+ if (!is_between(LDO_TH_MIN, LDO_TH_MAX, ldo_threshold_uV)) {
+ pr_err("bad ldo-threshold-voltage = %d specified\n",
+ ldo_threshold_uV);
+ return -EINVAL;
+ }
}
if (!init_data) {
@@ -708,15 +874,19 @@
kvreg->reg_base = devm_ioremap(&pdev->dev,
res->start, resource_size(res));
- kvreg->pvreg = the_gang;
- kvreg->name = init_data->constraints.name;
- kvreg->desc.name = kvreg->name;
- kvreg->desc.ops = &krait_power_ops;
- kvreg->desc.type = REGULATOR_VOLTAGE;
- kvreg->desc.owner = THIS_MODULE;
- kvreg->uV = CORE_VOLTAGE_MIN;
- kvreg->mode = HS_MODE;
- kvreg->desc.ops = &krait_power_ops;
+ kvreg->pvreg = the_gang;
+ kvreg->name = init_data->constraints.name;
+ kvreg->desc.name = kvreg->name;
+ kvreg->desc.ops = &krait_power_ops;
+ kvreg->desc.type = REGULATOR_VOLTAGE;
+ kvreg->desc.owner = THIS_MODULE;
+ kvreg->uV = CORE_VOLTAGE_MIN;
+ kvreg->mode = HS_MODE;
+ kvreg->desc.ops = &krait_power_ops;
+ kvreg->headroom_uV = headroom_uV;
+ kvreg->retention_uV = retention_uV;
+ kvreg->ldo_default_uV = ldo_default_uV;
+ kvreg->ldo_threshold_uV = ldo_threshold_uV;
platform_set_drvdata(pdev, kvreg);
diff --git a/arch/arm/mach-msm/lpm_levels.c b/arch/arm/mach-msm/lpm_levels.c
index 4854fc48..61c2aa8 100644
--- a/arch/arm/mach-msm/lpm_levels.c
+++ b/arch/arm/mach-msm/lpm_levels.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -145,6 +145,11 @@
if (time_param->latency_us < level->latency_us)
continue;
+ if ((MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE == sleep_mode)
+ || (MSM_PM_SLEEP_MODE_POWER_COLLAPSE == sleep_mode))
+ if (!cpu && msm_rpm_waiting_for_ack())
+ break;
+
if (time_param->sleep_us <= 1) {
pwr = level->energy_overhead;
} else if (time_param->sleep_us <= level->time_overhead_us) {
diff --git a/arch/arm/mach-msm/lpm_resources.c b/arch/arm/mach-msm/lpm_resources.c
index 255cd46..c21ea33 100644
--- a/arch/arm/mach-msm/lpm_resources.c
+++ b/arch/arm/mach-msm/lpm_resources.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -27,6 +27,7 @@
#include "lpm_resources.h"
#include "rpm-notifier.h"
#include "idle.h"
+#include "trace_msm_low_power.h"
/*Debug Definitions*/
enum {
@@ -417,6 +418,7 @@
if (rs->valid)
rs->sleep_value = limits->l2_cache;
+ trace_lpm_resources(rs->sleep_value, rs->name);
}
static void msm_lpm_flush_l2(int notify_rpm)
@@ -497,6 +499,7 @@
else
rs->sleep_value = vdd_buf;
}
+ trace_lpm_resources(rs->sleep_value, rs->name);
}
static void msm_lpm_flush_vdd_dig(int notify_rpm)
@@ -551,6 +554,7 @@
else
rs->sleep_value = vdd_buf;
}
+ trace_lpm_resources(rs->sleep_value, rs->name);
}
static void msm_lpm_flush_vdd_mem(int notify_rpm)
@@ -608,6 +612,7 @@
pr_info("%s: pxo buf %d sleep value %d\n",
__func__, pxo_buf, rs->sleep_value);
}
+ trace_lpm_resources(rs->sleep_value, rs->name);
}
static void msm_lpm_flush_pxo(int notify_rpm)
diff --git a/arch/arm/mach-msm/mdm.c b/arch/arm/mach-msm/mdm.c
index 02978cf..8dd4bac 100644
--- a/arch/arm/mach-msm/mdm.c
+++ b/arch/arm/mach-msm/mdm.c
@@ -354,6 +354,7 @@
ret = PTR_ERR(charm_subsys);
goto fatal_err;
}
+ subsys_default_online(charm_subsys);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
diff --git a/arch/arm/mach-msm/mdm_common.c b/arch/arm/mach-msm/mdm_common.c
index 58b26f2..b81832e 100644
--- a/arch/arm/mach-msm/mdm_common.c
+++ b/arch/arm/mach-msm/mdm_common.c
@@ -681,6 +681,7 @@
ret = PTR_ERR(mdm_subsys_dev);
goto fatal_err;
}
+ subsys_default_online(mdm_subsys_dev);
/* ERR_FATAL irq. */
irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_errfatal_gpio);
diff --git a/arch/arm/mach-msm/memory.c b/arch/arm/mach-msm/memory.c
index 7d7380b..3fe65b8 100644
--- a/arch/arm/mach-msm/memory.c
+++ b/arch/arm/mach-msm/memory.c
@@ -464,3 +464,8 @@
return ret;
}
+
+/* Provide a string that anonymous device tree allocations (those not
+ * directly associated with any driver) can use for their "compatible"
+ * field */
+EXPORT_COMPAT("qcom,msm-contig-mem");
diff --git a/arch/arm/mach-msm/mpm-8625.c b/arch/arm/mach-msm/mpm-8625.c
index c70ff5c..aaac476 100644
--- a/arch/arm/mach-msm/mpm-8625.c
+++ b/arch/arm/mach-msm/mpm-8625.c
@@ -101,6 +101,7 @@
static uint16_t msm_bypassed_apps_irqs[] = {
MSM8625_INT_CPR_IRQ0,
+ MSM8625_INT_L2CC_INTR,
};
/* Check IRQ falls into bypassed list are not */
diff --git a/arch/arm/mach-msm/msm_bus/Makefile b/arch/arm/mach-msm/msm_bus/Makefile
index bdc6fac..dde25ab 100644
--- a/arch/arm/mach-msm/msm_bus/Makefile
+++ b/arch/arm/mach-msm/msm_bus/Makefile
@@ -11,4 +11,5 @@
obj-$(CONFIG_ARCH_APQ8064) += msm_bus_board_8064.o
obj-$(CONFIG_ARCH_MSM8930) += msm_bus_board_8930.o
obj-$(CONFIG_ARCH_MSM8974) += msm_bus_board_8974.o
+obj-$(CONFIG_ARCH_MSM9625) += msm_bus_board_9625.o
obj-$(CONFIG_DEBUG_FS) += msm_bus_dbg.o
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c b/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
index e0ab983..ea17efe 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_bimc.c
@@ -485,7 +485,7 @@
};
#define M_PRIOLVL_OVERRIDE_ADDR(b, n) \
- (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000220)
+ (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000230)
enum bimc_m_priolvl_override {
M_PRIOLVL_OVERRIDE_RMSK = 0x301,
M_PRIOLVL_OVERRIDE_BMSK = 0x300,
@@ -495,10 +495,10 @@
};
#define M_RD_CMD_OVERRIDE_ADDR(b, n) \
- (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000230)
+ (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000240)
enum bimc_m_read_command_override {
- M_RD_CMD_OVERRIDE_RMSK = 0x37f3f,
- M_RD_CMD_OVERRIDE_AREQPRIO_BMSK = 0x300000,
+ M_RD_CMD_OVERRIDE_RMSK = 0x3071f7f,
+ M_RD_CMD_OVERRIDE_AREQPRIO_BMSK = 0x3000000,
M_RD_CMD_OVERRIDE_AREQPRIO_SHFT = 0x18,
M_RD_CMD_OVERRIDE_AMEMTYPE_BMSK = 0x70000,
M_RD_CMD_OVERRIDE_AMEMTYPE_SHFT = 0x10,
@@ -529,13 +529,15 @@
};
#define M_WR_CMD_OVERRIDE_ADDR(b, n) \
- (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000240)
+ (M_REG_BASE(b) + (0x4000 * (n)) + 0x00000250)
enum bimc_m_write_command_override {
- M_WR_CMD_OVERRIDE_RMSK = 0x37f3f,
- M_WR_CMD_OVERRIDE_AREQPRIO_BMSK = 0x30000,
- M_WR_CMD_OVERRIDE_AREQPRIO_SHFT = 0x10,
- M_WR_CMD_OVERRIDE_AMEMTYPE_BMSK = 0x7000,
- M_WR_CMD_OVERRIDE_AMEMTYPE_SHFT = 0xc,
+ M_WR_CMD_OVERRIDE_RMSK = 0x3071f7f,
+ M_WR_CMD_OVERRIDE_AREQPRIO_BMSK = 0x3000000,
+ M_WR_CMD_OVERRIDE_AREQPRIO_SHFT = 0x18,
+ M_WR_CMD_OVERRIDE_AMEMTYPE_BMSK = 0x70000,
+ M_WR_CMD_OVERRIDE_AMEMTYPE_SHFT = 0x10,
+ M_WR_CMD_OVERRIDE_ATRANSIENT_BMSK = 0x1000,
+ M_WR_CMD_OVERRIDE_ATRANSIENT_SHFT = 0xc,
M_WR_CMD_OVERRIDE_ASHARED_BMSK = 0x800,
M_WR_CMD_OVERRIDE_ASHARED_SHFT = 0xb,
M_WR_CMD_OVERRIDE_AREDIRECT_BMSK = 0x400,
@@ -544,8 +546,10 @@
M_WR_CMD_OVERRIDE_AOOO_SHFT = 0x9,
M_WR_CMD_OVERRIDE_AINNERSHARED_BMSK = 0x100,
M_WR_CMD_OVERRIDE_AINNERSHARED_SHFT = 0x8,
- M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK = 0x20,
- M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT = 0x5,
+ M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_BMSK = 0x40,
+ M_WR_CMD_OVERRIDE_OVERRIDE_AREQPRIO_SHFT = 0x6,
+ M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_BMSK = 0x20,
+ M_WR_CMD_OVERRIDE_OVERRIDE_ATRANSIENT_SHFT = 0x5,
M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_BMSK = 0x10,
M_WR_CMD_OVERRIDE_OVERRIDE_AMEMTYPE_SHFT = 0x4,
M_WR_CMD_OVERRIDE_OVERRIDE_ASHARED_BMSK = 0x8,
@@ -1454,7 +1458,7 @@
* boundary in future
*/
wmb();
- set_qos_mode(binfo->base, mas_index, 1, 1, 1);
+ set_qos_mode(binfo->base, mas_index, 0, 1, 1);
break;
case BIMC_QOS_MODE_BYPASS:
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8974.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8974.c
index f0f5cd8..cfd84eb 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8974.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8974.c
@@ -1049,9 +1049,8 @@
.qport = qports_kmpss,
.ws = 10000,
.mas_hw_id = MAS_APPSS_PROC,
- .prio_lvl = 0,
- .prio_rd = 2,
- .prio_wr = 2,
+ .prio_rd = 1,
+ .prio_wr = 1,
},
{
.id = MSM_BUS_MASTER_AMPSS_M1,
@@ -1064,6 +1063,8 @@
.qport = qports_kmpss,
.ws = 10000,
.mas_hw_id = MAS_APPSS_PROC,
+ .prio_rd = 1,
+ .prio_wr = 1,
},
{
.id = MSM_BUS_MASTER_MSS_PROC,
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_9625.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_9625.c
new file mode 100644
index 0000000..92cd255
--- /dev/null
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_9625.c
@@ -0,0 +1,1303 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
+#include <mach/board.h>
+#include <mach/rpm.h>
+#include "msm_bus_core.h"
+#include "msm_bus_noc.h"
+#include "msm_bus_bimc.h"
+
+#define NMASTERS 120
+#define NSLAVES 150
+#define NFAB_9625 4
+
+enum msm_bus_9625_master_ports_type {
+ /* System NOC Masters */
+ MASTER_PORT_LPASS_AHB = 0,
+ MASTER_PORT_QDSS_BAM,
+ MASTER_PORT_SNOC_CFG,
+ MASTER_PORT_GW_BIMC_SNOC,
+ MASTER_PORT_GW_CNOC_SNOC,
+ MASTER_PORT_CRYPTO_CORE0,
+ MASTER_PORT_LPASS_PROC,
+ MASTER_PORT_MSS,
+ MASTER_PORT_MSS_NAV,
+ MASTER_PORT_IPA,
+ MASTER_PORT_GW_PNOC_SNOC,
+ MASTER_PORT_QDSS_ETR,
+
+ /* BIMC Masters */
+ MASTER_PORT_KMPSS_M0 = 0,
+ MASTER_PORT_MSS_PROC,
+ MASTER_PORT_GW_SNOC_BIMC_0,
+
+ /* Peripheral NOC Masters */
+ MASTER_PORT_QPIC = 0,
+ MASTER_PORT_SDCC_1,
+ MASTER_PORT_SDCC_3,
+ MASTER_PORT_SDCC_2,
+ MASTER_PORT_SDCC_4,
+ MASTER_PORT_TSIF,
+ MASTER_PORT_BAM_DMA,
+ MASTER_PORT_BLSP_2,
+ MASTER_PORT_USB_HSIC,
+ MASTER_PORT_BLSP_1,
+ MASTER_PORT_USB_HS1,
+ MASTER_PORT_USB_HS2,
+ MASTER_PORT_PNOC_CFG,
+ MASTER_PORT_GW_SNOC_PNOC,
+
+ /* Config NOC Masters */
+ MASTER_PORT_RPM_INST = 0,
+ MASTER_PORT_RPM_DATA,
+ MASTER_PORT_RPM_SYS,
+ MASTER_PORT_DEHR,
+ MASTER_PORT_QDSS_DAP,
+ MASTER_PORT_SPDM,
+ MASTER_PORT_TIC,
+ MASTER_PORT_GW_SNOC_CNOC,
+};
+
+enum msm_bus_9625_slave_ports_type {
+ /* System NOC Slaves */
+ SLAVE_PORT_KMPSS = 1,
+ SLAVE_PORT_LPASS,
+ SLAVE_PORT_GW_SNOC_BIMC_P0,
+ SLAVE_PORT_GW_SNOC_CNOC,
+ SLAVE_PORT_OCIMEM,
+ SLAVE_PORT_GW_SNOC_PNOC,
+ SLAVE_PORT_SERVICE_SNOC,
+ SLAVE_PORT_QDSS_STM,
+
+ /* BIMC Slaves */
+ SLAVE_PORT_EBI1_CH0 = 0,
+ SLAVE_PORT_GW_BIMC_SNOC,
+
+ /*Peripheral NOC Slaves */
+ SLAVE_PORT_QPIC = 0,
+ SLAVE_PORT_SDCC_1,
+ SLAVE_PORT_SDCC_3,
+ SLAVE_PORT_SDCC_2,
+ SLAVE_PORT_SDCC_4,
+ SLAVE_PORT_TSIF,
+ SLAVE_PORT_BAM_DMA,
+ SLAVE_PORT_BLSP_2,
+ SLAVE_PORT_USB_HSIC,
+ SLAVE_PORT_BLSP_1,
+ SLAVE_PORT_USB_HS1,
+ SLAVE_PORT_USB_HS2,
+ SLAVE_PORT_PDM,
+ SLAVE_PORT_PERIPH_APU_CFG,
+ SLAVE_PORT_PNOC_MPU_CFG,
+ SLAVE_PORT_PRNG,
+ SLAVE_PORT_GW_PNOC_SNOC,
+ SLAVE_PORT_SERVICE_PNOC,
+
+ /* Config NOC slaves */
+ SLAVE_PORT_CLK_CTL = 0,
+ SLAVE_PORT_CNOC_MSS,
+ SLAVE_PORT_SECURITY,
+ SLAVE_PORT_TCSR,
+ SLAVE_PORT_TLMM,
+ SLAVE_PORT_CRYPTO_0_CFG,
+ SLAVE_PORT_IMEM_CFG,
+ SLAVE_PORT_IPS_CFG,
+ SLAVE_PORT_MESSAGE_RAM,
+ SLAVE_PORT_BIMC_CFG,
+ SLAVE_PORT_BOOT_ROM,
+ SLAVE_PORT_PMIC_ARB,
+ SLAVE_PORT_SPDM_WRAPPER,
+ SLAVE_PORT_DEHR_CFG,
+ SLAVE_PORT_MPM,
+ SLAVE_PORT_QDSS_CFG,
+ SLAVE_PORT_RBCPR_CFG,
+ SLAVE_PORT_RBCPR_QDSS_APU_CFG,
+ SLAVE_PORT_SNOC_MPU_CFG,
+ SLAVE_PORT_PNOC_CFG,
+ SLAVE_PORT_SNOC_CFG,
+ SLAVE_PORT_PHY_APU_CFG,
+ SLAVE_PORT_EBI1_PHY_CFG,
+ SLAVE_PORT_RPM,
+ SLAVE_PORT_GW_CNOC_SNOC,
+ SLAVE_PORT_SERVICE_CNOC,
+};
+
+/* Hardware IDs for RPM */
+enum msm_bus_9625_mas_hw_id {
+ MAS_APPSS_PROC = 0,
+ MAS_AMSS_PROC,
+ MAS_MNOC_BIMC,
+ MAS_SNOC_BIMC,
+ MAS_CNOC_MNOC_MMSS_CFG,
+ MAS_CNOC_MNOC_CFG,
+ MAS_GFX3D,
+ MAS_JPEG,
+ MAS_MDP,
+ MAS_VIDEO_P0,
+ MAS_VIDEO_P1,
+ MAS_VFE,
+ MAS_CNOC_ONOC_CFG,
+ MAS_JPEG_OCMEM,
+ MAS_MDP_OCMEM,
+ MAS_VIDEO_P0_OCMEM,
+ MAS_VIDEO_P1_OCMEM,
+ MAS_VFE_OCMEM,
+ MAS_LPASS_AHB,
+ MAS_QDSS_BAM,
+ MAS_SNOC_CFG,
+ MAS_BIMC_SNOC,
+ MAS_CNOC_SNOC,
+ MAS_CRYPTO_CORE0,
+ MAS_CRYPTO_CORE1,
+ MAS_LPASS_PROC,
+ MAS_MSS,
+ MAS_MSS_NAV,
+ MAS_OCMEM_DMA,
+ MAS_PNOC_SNOC,
+ MAS_WCSS,
+ MAS_QDSS_ETR,
+ MAS_USB3,
+ MAS_SDCC_1,
+ MAS_SDCC_3,
+ MAS_SDCC_2,
+ MAS_SDCC_4,
+ MAS_TSIF,
+ MAS_BAM_DMA,
+ MAS_BLSP_2,
+ MAS_USB_HSIC,
+ MAS_BLSP_1,
+ MAS_USB_HS,
+ MAS_PNOC_CFG,
+ MAS_SNOC_PNOC,
+ MAS_RPM_INST,
+ MAS_RPM_DATA,
+ MAS_RPM_SYS,
+ MAS_DEHR,
+ MAS_QDSS_DAP,
+ MAS_SPDM,
+ MAS_TIC,
+ MAS_SNOC_CNOC,
+ MAS_OVNOC_SNOC,
+ MAS_OVNOC_ONOC,
+ MAS_V_OCMEM_GFX3D,
+ MAS_ONOC_OVNOC,
+ MAS_SNOC_OVNOC,
+ MAS_QPIC,
+ MAS_IPA,
+};
+
+enum msm_bus_9625_slv_hw_id {
+ SLV_EBI = 0,
+ SLV_APSS_L2,
+ SLV_BIMC_SNOC,
+ SLV_CAMERA_CFG,
+ SLV_DISPLAY_CFG,
+ SLV_OCMEM_CFG,
+ SLV_CPR_CFG,
+ SLV_CPR_XPU_CFG,
+ SLV_MISC_CFG,
+ SLV_MISC_XPU_CFG,
+ SLV_VENUS_CFG,
+ SLV_GFX3D_CFG,
+ SLV_MMSS_CLK_CFG,
+ SLV_MMSS_CLK_XPU_CFG,
+ SLV_MNOC_MPU_CFG,
+ SLV_ONOC_MPU_CFG,
+ SLV_MMSS_BIMC,
+ SLV_SERVICE_MNOC,
+ SLV_OCMEM,
+ SLV_SERVICE_ONOC,
+ SLV_APPSS,
+ SLV_LPASS,
+ SLV_USB3,
+ SLV_WCSS,
+ SLV_SNOC_BIMC,
+ SLV_SNOC_CNOC,
+ SLV_OCIMEM,
+ SLV_SNOC_OCMEM,
+ SLV_SNOC_PNOC,
+ SLV_SERVICE_SNOC,
+ SLV_QDSS_STM,
+ SLV_SDCC_1,
+ SLV_SDCC_3,
+ SLV_SDCC_2,
+ SLV_SDCC_4,
+ SLV_TSIF,
+ SLV_BAM_DMA,
+ SLV_BLSP_2,
+ SLV_USB_HSIC,
+ SLV_BLSP_1,
+ SLV_USB_HS,
+ SLV_PDM,
+ SLV_PERIPH_APU_CFG,
+ SLV_MPU_CFG,
+ SLV_PRNG,
+ SLV_PNOC_SNOC,
+ SLV_SERVICE_PNOC,
+ SLV_CLK_CTL,
+ SLV_CNOC_MSS,
+ SLV_SECURITY,
+ SLV_TCSR,
+ SLV_TLMM,
+ SLV_CRYPTO_0_CFG,
+ SLV_CRYPTO_1_CFG,
+ SLV_IMEM_CFG,
+ SLV_MESSAGE_RAM,
+ SLV_BIMC_CFG,
+ SLV_BOOT_ROM,
+ SLV_CNOC_MNOC_MMSS_CFG,
+ SLV_PMIC_ARB,
+ SLV_SPDM_WRAPPER,
+ SLV_DEHR_CFG,
+ SLV_MPM,
+ SLV_QDSS_CFG,
+ SLV_RBCPR_CFG,
+ SLV_RBCPR_QDSS_APU_CFG,
+ SLV_CNOC_MNOC_CFG,
+ SLV_SNOC_MPU_CFG,
+ SLV_CNOC_ONOC_CFG,
+ SLV_PNOC_CFG,
+ SLV_SNOC_CFG,
+ SLV_EBI1_DLL_CFG,
+ SLV_PHY_APU_CFG,
+ SLV_EBI1_PHY_CFG,
+ SLV_RPM,
+ SLV_CNOC_SNOC,
+ SLV_SERVICE_CNOC,
+ SLV_SNOC_OVNOC,
+ SLV_ONOC_OVNOC,
+ SLV_USB_HS2,
+ SLV_QPIC,
+ SLV_IPS_CFG,
+};
+
+static uint32_t master_iids[NMASTERS];
+static uint32_t slave_iids[NSLAVES];
+
+/* System NOC nodes */
+static int mport_lpass_ahb[] = {MASTER_PORT_LPASS_AHB,};
+static int mport_qdss_bam[] = {MASTER_PORT_QDSS_BAM,};
+static int mport_snoc_cfg[] = {MASTER_PORT_SNOC_CFG,};
+static int mport_gw_bimc_snoc[] = {MASTER_PORT_GW_BIMC_SNOC,};
+static int mport_gw_cnoc_snoc[] = {MASTER_PORT_GW_CNOC_SNOC,};
+static int mport_crypto_core0[] = {MASTER_PORT_CRYPTO_CORE0,};
+static int mport_lpass_proc[] = {MASTER_PORT_LPASS_PROC};
+static int mport_mss[] = {MASTER_PORT_MSS};
+static int mport_mss_nav[] = {MASTER_PORT_MSS_NAV};
+static int mport_ipa[] = {MASTER_PORT_IPA};
+static int mport_gw_pnoc_snoc[] = {MASTER_PORT_GW_PNOC_SNOC};
+static int mport_qdss_etr[] = {MASTER_PORT_QDSS_ETR};
+
+static int sport_kmpss[] = {SLAVE_PORT_KMPSS};
+static int sport_lpass[] = {SLAVE_PORT_LPASS};
+static int sport_gw_snoc_bimc[] = {SLAVE_PORT_GW_SNOC_BIMC_P0};
+static int sport_gw_snoc_cnoc[] = {SLAVE_PORT_GW_SNOC_CNOC};
+static int sport_ocimem[] = {SLAVE_PORT_OCIMEM};
+static int sport_gw_snoc_pnoc[] = {SLAVE_PORT_GW_SNOC_PNOC};
+static int sport_service_snoc[] = {SLAVE_PORT_SERVICE_SNOC};
+static int sport_qdss_stm[] = {SLAVE_PORT_QDSS_STM};
+
+/* BIMC Nodes */
+
+static int mport_kmpss_m0[] = {MASTER_PORT_KMPSS_M0,};
+static int mport_mss_proc[] = {MASTER_PORT_MSS_PROC};
+static int mport_gw_snoc_bimc[] = {MASTER_PORT_GW_SNOC_BIMC_0};
+
+static int sport_ebi1[] = {SLAVE_PORT_EBI1_CH0};
+static int sport_gw_bimc_snoc[] = {SLAVE_PORT_GW_BIMC_SNOC,};
+
+/* Peripheral NOC Nodes */
+static int mport_sdcc_1[] = {MASTER_PORT_SDCC_1,};
+static int mport_sdcc_3[] = {MASTER_PORT_SDCC_3,};
+static int mport_sdcc_2[] = {MASTER_PORT_SDCC_2,};
+static int mport_sdcc_4[] = {MASTER_PORT_SDCC_4,};
+static int mport_tsif[] = {MASTER_PORT_TSIF,};
+static int mport_bam_dma[] = {MASTER_PORT_BAM_DMA,};
+static int mport_blsp_2[] = {MASTER_PORT_BLSP_2,};
+static int mport_usb_hsic[] = {MASTER_PORT_USB_HSIC,};
+static int mport_blsp_1[] = {MASTER_PORT_BLSP_1,};
+static int mport_pnoc_cfg[] = {MASTER_PORT_PNOC_CFG,};
+static int mport_qpic[] = {MASTER_PORT_QPIC,};
+static int mport_gw_snoc_pnoc[] = {MASTER_PORT_GW_SNOC_PNOC,};
+
+static int sport_sdcc_1[] = {SLAVE_PORT_SDCC_1,};
+static int sport_sdcc_3[] = {SLAVE_PORT_SDCC_3,};
+static int sport_sdcc_2[] = {SLAVE_PORT_SDCC_2,};
+static int sport_sdcc_4[] = {SLAVE_PORT_SDCC_4,};
+static int sport_tsif[] = {SLAVE_PORT_TSIF,};
+static int sport_qpic[] = {SLAVE_PORT_QPIC,};
+static int sport_bam_dma[] = {SLAVE_PORT_BAM_DMA,};
+static int sport_blsp_2[] = {SLAVE_PORT_BLSP_2,};
+static int sport_usb_hsic[] = {SLAVE_PORT_USB_HSIC,};
+static int sport_blsp_1[] = {SLAVE_PORT_BLSP_1,};
+static int sport_pdm[] = {SLAVE_PORT_PDM,};
+static int sport_periph_apu_cfg[] = {
+ SLAVE_PORT_PERIPH_APU_CFG,
+};
+static int sport_pnoc_mpu_cfg[] = {SLAVE_PORT_PNOC_MPU_CFG,};
+static int sport_prng[] = {SLAVE_PORT_PRNG,};
+static int sport_gw_pnoc_snoc[] = {SLAVE_PORT_GW_PNOC_SNOC,};
+static int sport_service_pnoc[] = {SLAVE_PORT_SERVICE_PNOC,};
+
+/* Config NOC Nodes */
+static int mport_rpm_inst[] = {MASTER_PORT_RPM_INST,};
+static int mport_rpm_data[] = {MASTER_PORT_RPM_DATA,};
+static int mport_rpm_sys[] = {MASTER_PORT_RPM_SYS,};
+static int mport_dehr[] = {MASTER_PORT_DEHR,};
+static int mport_qdss_dap[] = {MASTER_PORT_QDSS_DAP,};
+static int mport_spdm[] = {MASTER_PORT_SPDM,};
+static int mport_tic[] = {MASTER_PORT_TIC,};
+static int mport_gw_snoc_cnoc[] = {MASTER_PORT_GW_SNOC_CNOC,};
+
+static int sport_clk_ctl[] = {SLAVE_PORT_CLK_CTL,};
+static int sport_cnoc_mss[] = {SLAVE_PORT_CNOC_MSS,};
+static int sport_security[] = {SLAVE_PORT_SECURITY,};
+static int sport_tcsr[] = {SLAVE_PORT_TCSR,};
+static int sport_tlmm[] = {SLAVE_PORT_TLMM,};
+static int sport_crypto_0_cfg[] = {SLAVE_PORT_CRYPTO_0_CFG,};
+static int sport_imem_cfg[] = {SLAVE_PORT_IMEM_CFG,};
+static int sport_ips_cfg[] = {SLAVE_PORT_IPS_CFG,};
+static int sport_message_ram[] = {SLAVE_PORT_MESSAGE_RAM,};
+static int sport_bimc_cfg[] = {SLAVE_PORT_BIMC_CFG,};
+static int sport_boot_rom[] = {SLAVE_PORT_BOOT_ROM,};
+static int sport_pmic_arb[] = {SLAVE_PORT_PMIC_ARB,};
+static int sport_spdm_wrapper[] = {SLAVE_PORT_SPDM_WRAPPER,};
+static int sport_dehr_cfg[] = {SLAVE_PORT_DEHR_CFG,};
+static int sport_mpm[] = {SLAVE_PORT_MPM,};
+static int sport_qdss_cfg[] = {SLAVE_PORT_QDSS_CFG,};
+static int sport_rbcpr_cfg[] = {SLAVE_PORT_RBCPR_CFG,};
+static int sport_rbcpr_qdss_apu_cfg[] = {SLAVE_PORT_RBCPR_QDSS_APU_CFG,};
+static int sport_snoc_mpu_cfg[] = {SLAVE_PORT_SNOC_MPU_CFG,};
+static int sport_pnoc_cfg[] = {SLAVE_PORT_PNOC_CFG,};
+static int sport_snoc_cfg[] = {SLAVE_PORT_SNOC_CFG,};
+static int sport_phy_apu_cfg[] = {SLAVE_PORT_PHY_APU_CFG,};
+static int sport_ebi1_phy_cfg[] = {SLAVE_PORT_EBI1_PHY_CFG,};
+static int sport_rpm[] = {SLAVE_PORT_RPM,};
+static int sport_gw_cnoc_snoc[] = {SLAVE_PORT_GW_CNOC_SNOC,};
+static int sport_service_cnoc[] = {SLAVE_PORT_SERVICE_CNOC,};
+
+static int tier2[] = {MSM_BUS_BW_TIER2,};
+
+/*
+ * QOS Ports defined only when qos ports are different than
+ * master ports
+ **/
+static int qports_crypto_c0[] = {2};
+static int qports_lpass_proc[] = {4};
+static int qports_gw_snoc_bimc[] = {2};
+static int qports_kmpss[] = {0};
+static int qports_lpass_ahb[] = {0};
+static int qports_qdss_bam[] = {1};
+static int qports_gw_pnoc_snoc[] = {8};
+static int qports_ipa[] = {7};
+static int qports_qdss_etr[] = {10};
+
+static struct msm_bus_node_info sys_noc_info[] = {
+ {
+ .id = MSM_BUS_MASTER_LPASS_AHB,
+ .masterp = mport_lpass_ahb,
+ .num_mports = ARRAY_SIZE(mport_lpass_ahb),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .qport = qports_lpass_ahb,
+ .mas_hw_id = MAS_LPASS_AHB,
+ .mode = NOC_QOS_MODE_FIXED,
+ .prio_rd = 2,
+ .prio_wr = 2,
+ },
+ {
+ .id = MSM_BUS_MASTER_QDSS_BAM,
+ .masterp = mport_qdss_bam,
+ .num_mports = ARRAY_SIZE(mport_qdss_bam),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mode = NOC_QOS_MODE_FIXED,
+ .qport = qports_qdss_bam,
+ .mas_hw_id = MAS_QDSS_BAM,
+ },
+ {
+ .id = MSM_BUS_MASTER_SNOC_CFG,
+ .masterp = mport_snoc_cfg,
+ .num_mports = ARRAY_SIZE(mport_snoc_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mas_hw_id = MAS_SNOC_CFG,
+ },
+ {
+ .id = MSM_BUS_FAB_BIMC,
+ .gateway = 1,
+ .slavep = sport_gw_snoc_bimc,
+ .num_sports = ARRAY_SIZE(sport_gw_snoc_bimc),
+ .masterp = mport_gw_bimc_snoc,
+ .num_mports = ARRAY_SIZE(mport_gw_bimc_snoc),
+ .buswidth = 8,
+ .mas_hw_id = MAS_BIMC_SNOC,
+ .slv_hw_id = SLV_SNOC_BIMC,
+ },
+ {
+ .id = MSM_BUS_FAB_CONFIG_NOC,
+ .gateway = 1,
+ .slavep = sport_gw_snoc_cnoc,
+ .num_sports = ARRAY_SIZE(sport_gw_snoc_cnoc),
+ .masterp = mport_gw_cnoc_snoc,
+ .num_mports = ARRAY_SIZE(mport_gw_cnoc_snoc),
+ .buswidth = 8,
+ .mas_hw_id = MAS_CNOC_SNOC,
+ .slv_hw_id = SLV_SNOC_CNOC,
+ },
+ {
+ .id = MSM_BUS_FAB_PERIPH_NOC,
+ .gateway = 1,
+ .slavep = sport_gw_snoc_pnoc,
+ .num_sports = ARRAY_SIZE(sport_gw_snoc_pnoc),
+ .masterp = mport_gw_pnoc_snoc,
+ .num_mports = ARRAY_SIZE(mport_gw_pnoc_snoc),
+ .buswidth = 8,
+ .qport = qports_gw_pnoc_snoc,
+ .mas_hw_id = MAS_PNOC_SNOC,
+ .slv_hw_id = SLV_SNOC_PNOC,
+ .mode = NOC_QOS_MODE_FIXED,
+ .prio_rd = 2,
+ .prio_wr = 2,
+ },
+ {
+ .id = MSM_BUS_MASTER_CRYPTO_CORE0,
+ .masterp = mport_crypto_core0,
+ .num_mports = ARRAY_SIZE(mport_crypto_core0),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mode = NOC_QOS_MODE_FIXED,
+ .qport = qports_crypto_c0,
+ .mas_hw_id = MAS_CRYPTO_CORE0,
+ .hw_sel = MSM_BUS_NOC,
+ },
+ {
+ .id = MSM_BUS_MASTER_LPASS_PROC,
+ .masterp = mport_lpass_proc,
+ .num_mports = ARRAY_SIZE(mport_lpass_proc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .qport = qports_lpass_proc,
+ .mas_hw_id = MAS_LPASS_PROC,
+ .mode = NOC_QOS_MODE_FIXED,
+ .prio_rd = 2,
+ .prio_wr = 2,
+ },
+ {
+ .id = MSM_BUS_MASTER_MSS,
+ .masterp = mport_mss,
+ .num_mports = ARRAY_SIZE(mport_mss),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mas_hw_id = MAS_MSS,
+ },
+ {
+ .id = MSM_BUS_MASTER_MSS_NAV,
+ .masterp = mport_mss_nav,
+ .num_mports = ARRAY_SIZE(mport_mss_nav),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mas_hw_id = MAS_MSS_NAV,
+ },
+ {
+ .id = MSM_BUS_MASTER_IPA,
+ .masterp = mport_ipa,
+ .num_mports = ARRAY_SIZE(mport_ipa),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .mode = NOC_QOS_MODE_FIXED,
+ .qport = qports_ipa,
+ .mas_hw_id = MAS_IPA,
+ },
+ {
+ .id = MSM_BUS_MASTER_QDSS_ETR,
+ .masterp = mport_qdss_etr,
+ .num_mports = ARRAY_SIZE(mport_qdss_etr),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .qport = qports_qdss_etr,
+ .mode = NOC_QOS_MODE_FIXED,
+ .mas_hw_id = MAS_QDSS_ETR,
+ },
+ {
+ .id = MSM_BUS_SLAVE_AMPSS,
+ .slavep = sport_kmpss,
+ .num_sports = ARRAY_SIZE(sport_kmpss),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_APPSS,
+ },
+ {
+ .id = MSM_BUS_SLAVE_LPASS,
+ .slavep = sport_lpass,
+ .num_sports = ARRAY_SIZE(sport_lpass),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_LPASS,
+ },
+ {
+ .id = MSM_BUS_SLAVE_OCIMEM,
+ .slavep = sport_ocimem,
+ .num_sports = ARRAY_SIZE(sport_ocimem),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_OCIMEM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SERVICE_SNOC,
+ .slavep = sport_service_snoc,
+ .num_sports = ARRAY_SIZE(sport_service_snoc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SERVICE_SNOC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_QDSS_STM,
+ .slavep = sport_qdss_stm,
+ .num_sports = ARRAY_SIZE(sport_qdss_stm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_QDSS_STM,
+ },
+};
+
+static struct msm_bus_node_info bimc_info[] = {
+ {
+ .id = MSM_BUS_MASTER_AMPSS_M0,
+ .masterp = mport_kmpss_m0,
+ .num_mports = ARRAY_SIZE(mport_kmpss_m0),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .hw_sel = MSM_BUS_BIMC,
+ .mode = NOC_QOS_MODE_FIXED,
+ .qport = qports_kmpss,
+ .ws = 10000,
+ .mas_hw_id = MAS_APPSS_PROC,
+ .prio_lvl = 0,
+ .prio_rd = 2,
+ .prio_wr = 2,
+ },
+ {
+ .id = MSM_BUS_MASTER_MSS_PROC,
+ .masterp = mport_mss_proc,
+ .num_mports = ARRAY_SIZE(mport_mss_proc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .hw_sel = MSM_BUS_RPM,
+ .mas_hw_id = MAS_AMSS_PROC,
+ },
+ {
+ .id = MSM_BUS_FAB_SYS_NOC,
+ .gateway = 1,
+ .slavep = sport_gw_bimc_snoc,
+ .num_sports = ARRAY_SIZE(sport_gw_bimc_snoc),
+ .masterp = mport_gw_snoc_bimc,
+ .num_mports = ARRAY_SIZE(mport_gw_snoc_bimc),
+ .qport = qports_gw_snoc_bimc,
+ .buswidth = 8,
+ .ws = 10000,
+ .mas_hw_id = MAS_SNOC_BIMC,
+ .slv_hw_id = SLV_BIMC_SNOC,
+ .mode = NOC_QOS_MODE_BYPASS,
+ },
+ {
+ .id = MSM_BUS_SLAVE_EBI_CH0,
+ .slavep = sport_ebi1,
+ .num_sports = ARRAY_SIZE(sport_ebi1),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_EBI,
+ .mode = NOC_QOS_MODE_BYPASS,
+ },
+};
+
+static struct msm_bus_node_info periph_noc_info[] = {
+ {
+ .id = MSM_BUS_MASTER_PNOC_CFG,
+ .masterp = mport_pnoc_cfg,
+ .num_mports = ARRAY_SIZE(mport_pnoc_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_PNOC_CFG,
+ },
+ {
+ .id = MSM_BUS_MASTER_QPIC,
+ .masterp = mport_qpic,
+ .num_mports = ARRAY_SIZE(mport_qpic),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_QPIC,
+ },
+ {
+ .id = MSM_BUS_MASTER_SDCC_1,
+ .masterp = mport_sdcc_1,
+ .num_mports = ARRAY_SIZE(mport_sdcc_1),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SDCC_1,
+ },
+ {
+ .id = MSM_BUS_MASTER_SDCC_3,
+ .masterp = mport_sdcc_3,
+ .num_mports = ARRAY_SIZE(mport_sdcc_3),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SDCC_3,
+ },
+ {
+ .id = MSM_BUS_MASTER_SDCC_4,
+ .masterp = mport_sdcc_4,
+ .num_mports = ARRAY_SIZE(mport_sdcc_4),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SDCC_4,
+ },
+ {
+ .id = MSM_BUS_MASTER_SDCC_2,
+ .masterp = mport_sdcc_2,
+ .num_mports = ARRAY_SIZE(mport_sdcc_2),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SDCC_2,
+ },
+ {
+ .id = MSM_BUS_MASTER_TSIF,
+ .masterp = mport_tsif,
+ .num_mports = ARRAY_SIZE(mport_tsif),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_TSIF,
+ },
+ {
+ .id = MSM_BUS_MASTER_BAM_DMA,
+ .masterp = mport_bam_dma,
+ .num_mports = ARRAY_SIZE(mport_bam_dma),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_BAM_DMA,
+ },
+ {
+ .id = MSM_BUS_MASTER_BLSP_2,
+ .masterp = mport_blsp_2,
+ .num_mports = ARRAY_SIZE(mport_blsp_2),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_BLSP_2,
+ },
+ {
+ .id = MSM_BUS_MASTER_USB_HSIC,
+ .masterp = mport_usb_hsic,
+ .num_mports = ARRAY_SIZE(mport_usb_hsic),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_USB_HSIC,
+ },
+ {
+ .id = MSM_BUS_MASTER_BLSP_1,
+ .masterp = mport_blsp_1,
+ .num_mports = ARRAY_SIZE(mport_blsp_1),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_BLSP_1,
+ },
+ {
+ .id = MSM_BUS_FAB_SYS_NOC,
+ .gateway = 1,
+ .slavep = sport_gw_pnoc_snoc,
+ .num_sports = ARRAY_SIZE(sport_gw_pnoc_snoc),
+ .masterp = mport_gw_snoc_pnoc,
+ .num_mports = ARRAY_SIZE(mport_gw_snoc_pnoc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PNOC_SNOC,
+ .mas_hw_id = MAS_SNOC_PNOC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SDCC_1,
+ .slavep = sport_sdcc_1,
+ .num_sports = ARRAY_SIZE(sport_sdcc_1),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SDCC_1,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SDCC_3,
+ .slavep = sport_sdcc_3,
+ .num_sports = ARRAY_SIZE(sport_sdcc_3),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SDCC_3,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SDCC_2,
+ .slavep = sport_sdcc_2,
+ .num_sports = ARRAY_SIZE(sport_sdcc_2),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SDCC_2,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SDCC_4,
+ .slavep = sport_sdcc_4,
+ .num_sports = ARRAY_SIZE(sport_sdcc_4),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SDCC_4,
+ },
+ {
+ .id = MSM_BUS_SLAVE_TSIF,
+ .slavep = sport_tsif,
+ .num_sports = ARRAY_SIZE(sport_tsif),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_TSIF,
+ },
+ {
+ .id = MSM_BUS_SLAVE_BAM_DMA,
+ .slavep = sport_bam_dma,
+ .num_sports = ARRAY_SIZE(sport_bam_dma),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_BAM_DMA,
+ },
+ {
+ .id = MSM_BUS_SLAVE_QPIC,
+ .masterp = sport_qpic,
+ .num_mports = ARRAY_SIZE(sport_qpic),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = SLV_QPIC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_BLSP_2,
+ .slavep = sport_blsp_2,
+ .num_sports = ARRAY_SIZE(sport_blsp_2),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_BLSP_2,
+ },
+ {
+ .id = MSM_BUS_SLAVE_USB_HSIC,
+ .slavep = sport_usb_hsic,
+ .num_sports = ARRAY_SIZE(sport_usb_hsic),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_USB_HSIC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_BLSP_1,
+ .slavep = sport_blsp_1,
+ .num_sports = ARRAY_SIZE(sport_blsp_1),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_BLSP_1,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PDM,
+ .slavep = sport_pdm,
+ .num_sports = ARRAY_SIZE(sport_pdm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PDM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PERIPH_APU_CFG,
+ .slavep = sport_periph_apu_cfg,
+ .num_sports = ARRAY_SIZE(sport_periph_apu_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PERIPH_APU_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PNOC_MPU_CFG,
+ .slavep = sport_pnoc_mpu_cfg,
+ .num_sports = ARRAY_SIZE(sport_pnoc_mpu_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_MPU_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PRNG,
+ .slavep = sport_prng,
+ .num_sports = ARRAY_SIZE(sport_prng),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PRNG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SERVICE_PNOC,
+ .slavep = sport_service_pnoc,
+ .num_sports = ARRAY_SIZE(sport_service_pnoc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SERVICE_PNOC,
+ },
+};
+
+static struct msm_bus_node_info config_noc_info[] = {
+ {
+ .id = MSM_BUS_MASTER_RPM_INST,
+ .masterp = mport_rpm_inst,
+ .num_mports = ARRAY_SIZE(mport_rpm_inst),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_RPM_INST,
+ },
+ {
+ .id = MSM_BUS_MASTER_RPM_DATA,
+ .masterp = mport_rpm_data,
+ .num_mports = ARRAY_SIZE(mport_rpm_data),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_RPM_DATA,
+ },
+ {
+ .id = MSM_BUS_MASTER_RPM_SYS,
+ .masterp = mport_rpm_sys,
+ .num_mports = ARRAY_SIZE(mport_rpm_sys),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_RPM_SYS,
+ },
+ {
+ .id = MSM_BUS_MASTER_DEHR,
+ .masterp = mport_dehr,
+ .num_mports = ARRAY_SIZE(mport_dehr),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_DEHR,
+ },
+ {
+ .id = MSM_BUS_MASTER_QDSS_DAP,
+ .masterp = mport_qdss_dap,
+ .num_mports = ARRAY_SIZE(mport_qdss_dap),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_QDSS_DAP,
+ },
+ {
+ .id = MSM_BUS_MASTER_SPDM,
+ .masterp = mport_spdm,
+ .num_mports = ARRAY_SIZE(mport_spdm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SPDM,
+ },
+ {
+ .id = MSM_BUS_MASTER_TIC,
+ .masterp = mport_tic,
+ .num_mports = ARRAY_SIZE(mport_tic),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_TIC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_CLK_CTL,
+ .slavep = sport_clk_ctl,
+ .num_sports = ARRAY_SIZE(sport_clk_ctl),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_CLK_CTL,
+ },
+ {
+ .id = MSM_BUS_SLAVE_CNOC_MSS,
+ .slavep = sport_cnoc_mss,
+ .num_sports = ARRAY_SIZE(sport_cnoc_mss),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_CNOC_MSS,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SECURITY,
+ .slavep = sport_security,
+ .num_sports = ARRAY_SIZE(sport_security),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SECURITY,
+ },
+ {
+ .id = MSM_BUS_SLAVE_TCSR,
+ .slavep = sport_tcsr,
+ .num_sports = ARRAY_SIZE(sport_tcsr),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_TCSR,
+ },
+ {
+ .id = MSM_BUS_SLAVE_TLMM,
+ .slavep = sport_tlmm,
+ .num_sports = ARRAY_SIZE(sport_tlmm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_TLMM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_CRYPTO_0_CFG,
+ .slavep = sport_crypto_0_cfg,
+ .num_sports = ARRAY_SIZE(sport_crypto_0_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_CRYPTO_0_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_IMEM_CFG,
+ .slavep = sport_imem_cfg,
+ .num_sports = ARRAY_SIZE(sport_imem_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_IMEM_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_IPS_CFG,
+ .slavep = sport_ips_cfg,
+ .num_sports = ARRAY_SIZE(sport_ips_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_IPS_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_MESSAGE_RAM,
+ .slavep = sport_message_ram,
+ .num_sports = ARRAY_SIZE(sport_message_ram),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_MESSAGE_RAM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_BIMC_CFG,
+ .slavep = sport_bimc_cfg,
+ .num_sports = ARRAY_SIZE(sport_bimc_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_BIMC_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_BOOT_ROM,
+ .slavep = sport_boot_rom,
+ .num_sports = ARRAY_SIZE(sport_boot_rom),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_BOOT_ROM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PMIC_ARB,
+ .slavep = sport_pmic_arb,
+ .num_sports = ARRAY_SIZE(sport_pmic_arb),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PMIC_ARB,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SPDM_WRAPPER,
+ .slavep = sport_spdm_wrapper,
+ .num_sports = ARRAY_SIZE(sport_spdm_wrapper),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SPDM_WRAPPER,
+ },
+ {
+ .id = MSM_BUS_SLAVE_DEHR_CFG,
+ .slavep = sport_dehr_cfg,
+ .num_sports = ARRAY_SIZE(sport_dehr_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_DEHR_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_MPM,
+ .slavep = sport_mpm,
+ .num_sports = ARRAY_SIZE(sport_mpm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_MPM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_QDSS_CFG,
+ .slavep = sport_qdss_cfg,
+ .num_sports = ARRAY_SIZE(sport_qdss_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_QDSS_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_RBCPR_CFG,
+ .slavep = sport_rbcpr_cfg,
+ .num_sports = ARRAY_SIZE(sport_rbcpr_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_RBCPR_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG,
+ .slavep = sport_rbcpr_qdss_apu_cfg,
+ .num_sports = ARRAY_SIZE(sport_rbcpr_qdss_apu_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_RBCPR_QDSS_APU_CFG,
+ },
+ {
+ .id = MSM_BUS_FAB_SYS_NOC,
+ .gateway = 1,
+ .slavep = sport_gw_cnoc_snoc,
+ .num_sports = ARRAY_SIZE(sport_gw_cnoc_snoc),
+ .masterp = mport_gw_snoc_cnoc,
+ .num_mports = ARRAY_SIZE(mport_gw_snoc_cnoc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .mas_hw_id = MAS_SNOC_CNOC,
+ .slv_hw_id = SLV_CNOC_SNOC,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PNOC_CFG,
+ .slavep = sport_pnoc_cfg,
+ .num_sports = ARRAY_SIZE(sport_pnoc_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PNOC_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SNOC_MPU_CFG,
+ .slavep = sport_snoc_mpu_cfg,
+ .num_sports = ARRAY_SIZE(sport_snoc_mpu_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SNOC_MPU_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SNOC_CFG,
+ .slavep = sport_snoc_cfg,
+ .num_sports = ARRAY_SIZE(sport_snoc_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SNOC_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_PHY_APU_CFG,
+ .slavep = sport_phy_apu_cfg,
+ .num_sports = ARRAY_SIZE(sport_phy_apu_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_PHY_APU_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_EBI1_PHY_CFG,
+ .slavep = sport_ebi1_phy_cfg,
+ .num_sports = ARRAY_SIZE(sport_ebi1_phy_cfg),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_EBI1_PHY_CFG,
+ },
+ {
+ .id = MSM_BUS_SLAVE_RPM,
+ .slavep = sport_rpm,
+ .num_sports = ARRAY_SIZE(sport_rpm),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_RPM,
+ },
+ {
+ .id = MSM_BUS_SLAVE_SERVICE_CNOC,
+ .slavep = sport_service_cnoc,
+ .num_sports = ARRAY_SIZE(sport_service_cnoc),
+ .tier = tier2,
+ .num_tiers = ARRAY_SIZE(tier2),
+ .buswidth = 8,
+ .slv_hw_id = SLV_SERVICE_CNOC,
+ },
+};
+
+static void msm_bus_board_assign_iids(struct msm_bus_fabric_registration
+ *fabreg, int fabid)
+{
+ int i;
+ for (i = 0; i < fabreg->len; i++) {
+ if (!fabreg->info[i].gateway) {
+ fabreg->info[i].priv_id = fabid + fabreg->info[i].id;
+ if (fabreg->info[i].id < SLAVE_ID_KEY) {
+ WARN(fabreg->info[i].id >= NMASTERS,
+ "id %d exceeds array size!\n",
+ fabreg->info[i].id);
+ master_iids[fabreg->info[i].id] =
+ fabreg->info[i].priv_id;
+ } else {
+ WARN((fabreg->info[i].id - SLAVE_ID_KEY) >=
+ NSLAVES, "id %d exceeds array size!\n",
+ fabreg->info[i].id);
+ slave_iids[fabreg->info[i].id - (SLAVE_ID_KEY)]
+ = fabreg->info[i].priv_id;
+ }
+ } else {
+ fabreg->info[i].priv_id = fabreg->info[i].id;
+ }
+ }
+}
+
+static int msm_bus_board_9625_get_iid(int id)
+{
+ if ((id < SLAVE_ID_KEY && id >= NMASTERS) ||
+ id >= (SLAVE_ID_KEY + NSLAVES)) {
+ MSM_BUS_ERR("Cannot get iid. Invalid id %d passed\n", id);
+ return -EINVAL;
+ }
+
+ return CHECK_ID(((id < SLAVE_ID_KEY) ? master_iids[id] :
+ slave_iids[id - SLAVE_ID_KEY]), id);
+}
+
+int msm_bus_board_rpm_get_il_ids(uint16_t *id)
+{
+ return -ENXIO;
+}
+
+static struct msm_bus_board_algorithm msm_bus_board_algo = {
+ .board_nfab = NFAB_9625,
+ .get_iid = msm_bus_board_9625_get_iid,
+ .assign_iids = msm_bus_board_assign_iids,
+};
+
+struct msm_bus_fabric_registration msm_bus_9625_sys_noc_pdata = {
+ .id = MSM_BUS_FAB_SYS_NOC,
+ .name = "msm_sys_noc",
+ .info = sys_noc_info,
+ .len = ARRAY_SIZE(sys_noc_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "bus_clk",
+ .fabclk[ACTIVE_CTX] = "bus_a_clk",
+ .nmasters = 15,
+ .nslaves = 12,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+ .qos_freq = 4800,
+ .hw_sel = MSM_BUS_NOC,
+ .rpm_enabled = 1,
+};
+
+struct msm_bus_fabric_registration msm_bus_9625_bimc_pdata = {
+ .id = MSM_BUS_FAB_BIMC,
+ .name = "msm_bimc",
+ .info = bimc_info,
+ .len = ARRAY_SIZE(bimc_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "mem_clk",
+ .fabclk[ACTIVE_CTX] = "mem_a_clk",
+ .nmasters = 7,
+ .nslaves = 4,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+ .qos_freq = 4800,
+ .hw_sel = MSM_BUS_BIMC,
+ .rpm_enabled = 1,
+};
+
+struct msm_bus_fabric_registration msm_bus_9625_periph_noc_pdata = {
+ .id = MSM_BUS_FAB_PERIPH_NOC,
+ .name = "msm_periph_noc",
+ .info = periph_noc_info,
+ .len = ARRAY_SIZE(periph_noc_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "bus_clk",
+ .fabclk[ACTIVE_CTX] = "bus_a_clk",
+ .nmasters = 14,
+ .nslaves = 15,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+ .hw_sel = MSM_BUS_NOC,
+ .rpm_enabled = 1,
+};
+
+struct msm_bus_fabric_registration msm_bus_9625_config_noc_pdata = {
+ .id = MSM_BUS_FAB_CONFIG_NOC,
+ .name = "msm_config_noc",
+ .info = config_noc_info,
+ .len = ARRAY_SIZE(config_noc_info),
+ .ahb = 0,
+ .fabclk[DUAL_CTX] = "bus_clk",
+ .fabclk[ACTIVE_CTX] = "bus_a_clk",
+ .nmasters = 8,
+ .nslaves = 30,
+ .ntieredslaves = 0,
+ .board_algo = &msm_bus_board_algo,
+ .hw_sel = MSM_BUS_NOC,
+ .rpm_enabled = 1,
+};
diff --git a/arch/arm/mach-msm/msm_cpr.c b/arch/arm/mach-msm/msm_cpr.c
index c00352d..b68a8db 100644
--- a/arch/arm/mach-msm/msm_cpr.c
+++ b/arch/arm/mach-msm/msm_cpr.c
@@ -50,6 +50,7 @@
static struct platform_device *cpr_pdev;
static bool enable = 1;
+static bool disable_cpr;
module_param(enable, bool, 0644);
MODULE_PARM_DESC(enable, "CPR Enable");
@@ -329,12 +330,12 @@
cpr_write_reg(cpr, RBIF_CONT_NACK_CMD, 0x1);
}
-static void cpr_irq_set(struct msm_cpr *cpr, uint32_t irq, bool enable)
+static void cpr_irq_set(struct msm_cpr *cpr, uint32_t irq, bool enable_irq)
{
uint32_t irq_enabled;
irq_enabled = cpr_read_reg(cpr, RBIF_IRQ_EN(cpr->config->irq_line));
- if (enable == 1)
+ if (enable_irq == 1)
irq_enabled |= irq;
else
irq_enabled &= ~irq;
@@ -832,7 +833,7 @@
void msm_cpr_pm_resume(void)
{
- if (!enable)
+ if (!enable || disable_cpr)
return;
msm_cpr_resume(&cpr_pdev->dev);
@@ -841,7 +842,7 @@
void msm_cpr_pm_suspend(void)
{
- if (!enable)
+ if (!enable || disable_cpr)
return;
msm_cpr_suspend(&cpr_pdev->dev);
@@ -853,7 +854,7 @@
{
struct msm_cpr *cpr;
- if (!enable)
+ if (!enable || disable_cpr)
return;
cpr = platform_get_drvdata(cpr_pdev);
@@ -866,7 +867,7 @@
{
struct msm_cpr *cpr;
- if (!enable)
+ if (!enable || disable_cpr)
return;
cpr = platform_get_drvdata(cpr_pdev);
@@ -893,6 +894,12 @@
return -EIO;
}
+ if (pdata->disable_cpr == true) {
+ pr_err("CPR disabled by modem\n");
+ disable_cpr = true;
+ return -EPERM;
+ }
+
cpr = devm_kzalloc(&pdev->dev, sizeof(struct msm_cpr), GFP_KERNEL);
if (!cpr) {
enable = false;
diff --git a/arch/arm/mach-msm/msm_cpr.h b/arch/arm/mach-msm/msm_cpr.h
index 005d9b1..3d10478 100644
--- a/arch/arm/mach-msm/msm_cpr.h
+++ b/arch/arm/mach-msm/msm_cpr.h
@@ -188,6 +188,7 @@
uint32_t max_nom_freq;
uint32_t max_freq;
uint32_t max_quot;
+ bool disable_cpr;
struct msm_cpr_vp_data *vp_data;
uint32_t (*get_quot)(uint32_t max_quot, uint32_t max_freq,
uint32_t new_freq);
diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c
index b2160c5..2736870 100644
--- a/arch/arm/mach-msm/msm_dcvs.c
+++ b/arch/arm/mach-msm/msm_dcvs.c
@@ -23,6 +23,7 @@
#include <linux/stringify.h>
#include <linux/debugfs.h>
#include <linux/msm_tsens.h>
+#include <linux/platform_device.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <mach/msm_dcvs.h>
@@ -33,6 +34,8 @@
#define __info(f, ...) pr_info("MSM_DCVS: %s: " f, __func__, __VA_ARGS__)
#define MAX_PENDING (5)
+#define CORE_FLAG_TEMP_UPDATE 0x1
+
struct core_attribs {
struct kobj_attribute freq_change_us;
@@ -123,12 +126,14 @@
unsigned int (*get_frequency)(int type_core_num);
int (*idle_enable)(int type_core_num,
enum msm_core_control_event event);
+ int (*set_floor_frequency)(int type_core_num, unsigned int freq);
spinlock_t pending_freq_lock;
int pending_freq;
struct hrtimer slack_timer;
struct delayed_work temperature_work;
+ int flags;
};
static int msm_dcvs_enabled = 1;
@@ -140,6 +145,11 @@
static struct kobject *cores_kobj;
+#define DCVS_MAX_NUM_FREQS 15
+static struct msm_dcvs_freq_entry cpu_freq_tbl[DCVS_MAX_NUM_FREQS];
+static unsigned num_cpu_freqs;
+static struct msm_dcvs_platform_data *dcvs_pdata;
+
static void force_stop_slack_timer(struct dcvs_core *core)
{
unsigned long flags;
@@ -246,6 +256,35 @@
spin_unlock_irqrestore(&core->idle_state_change_lock, flags2);
}
+static void apply_gpu_floor(int cpu_freq)
+{
+ int i;
+ int gpu_floor_freq = 0;
+ struct dcvs_core *gpu;
+
+ if (!dcvs_pdata)
+ return;
+
+ for (i = 0; i < dcvs_pdata->num_sync_rules; i++)
+ if (cpu_freq > dcvs_pdata->sync_rules[i].cpu_khz) {
+ gpu_floor_freq =
+ dcvs_pdata->sync_rules[i].gpu_floor_khz;
+ break;
+ }
+
+ if (!gpu_floor_freq)
+ return;
+
+ for (i = GPU_OFFSET; i < CORES_MAX; i++) {
+ gpu = &core_list[i];
+ if (gpu->dcvs_core_id == -1)
+ continue;
+ if (gpu->set_floor_frequency)
+ gpu->set_floor_frequency(gpu->type_core_num,
+ gpu_floor_freq);
+ }
+}
+
static int __msm_dcvs_change_freq(struct dcvs_core *core)
{
int ret = 0;
@@ -277,6 +316,10 @@
spin_unlock_irqrestore(&core->pending_freq_lock, flags);
+ if (core->type == MSM_DCVS_CORE_TYPE_CPU &&
+ core->type_core_num == 0)
+ apply_gpu_floor(requested_freq);
+
/**
* Call the frequency sink driver to change the frequency
* We will need to get back the actual frequency in KHz and
@@ -353,6 +396,9 @@
unsigned long temp = 0;
int interval_ms;
+ if (!(core->flags & CORE_FLAG_TEMP_UPDATE))
+ return;
+
tsens_dev.sensor_num = core->sensor;
ret = tsens_get_temp(&tsens_dev, &temp);
if (!temp) {
@@ -384,9 +430,6 @@
static int msm_dcvs_do_freq(void *data)
{
struct dcvs_core *core = (struct dcvs_core *)data;
- static struct sched_param param = {.sched_priority = MAX_RT_PRIO - 1};
-
- sched_setscheduler(current, SCHED_FIFO, ¶m);
while (!kthread_should_stop()) {
wait_event(core->wait_q, !(core->pending_freq == 0 ||
@@ -828,6 +871,37 @@
return &core_list[offset];
}
+void msm_dcvs_register_cpu_freq(uint32_t freq, uint32_t voltage)
+{
+ BUG_ON(freq == 0 || voltage == 0 ||
+ num_cpu_freqs == DCVS_MAX_NUM_FREQS);
+
+ cpu_freq_tbl[num_cpu_freqs].freq = freq;
+ cpu_freq_tbl[num_cpu_freqs].voltage = voltage;
+
+ num_cpu_freqs++;
+}
+
+static void update_cpu_dcvs_params(struct msm_dcvs_core_info *info)
+{
+ int i;
+
+ BUG_ON(num_cpu_freqs == 0);
+
+ info->freq_tbl = cpu_freq_tbl;
+ info->power_param.num_freq = num_cpu_freqs;
+
+ if (!dcvs_pdata || dcvs_pdata->num_sync_rules == 0)
+ return;
+
+ /* the first sync rule shows what the turbo frequencies are -
+ * these frequencies need energy offsets set */
+ for (i = 0; i < DCVS_MAX_NUM_FREQS && cpu_freq_tbl[i].freq != 0; i++)
+ if (cpu_freq_tbl[i].freq > dcvs_pdata->sync_rules[0].cpu_khz) {
+ cpu_freq_tbl[i].active_energy_offset = 100;
+ cpu_freq_tbl[i].leakage_energy_offset = 100;
+ }
+}
int msm_dcvs_register_core(
enum msm_dcvs_core_type type,
@@ -837,6 +911,7 @@
unsigned int (*get_frequency)(int type_core_num),
int (*idle_enable)(int type_core_num,
enum msm_core_control_event event),
+ int (*set_floor_frequency)(int type_core_num, unsigned int freq),
int sensor)
{
int ret = -EINVAL;
@@ -860,9 +935,13 @@
core->set_frequency = set_frequency;
core->get_frequency = get_frequency;
core->idle_enable = idle_enable;
+ core->set_floor_frequency = set_floor_frequency;
core->pending_freq = STOP_FREQ_CHANGE;
core->info = info;
+ if (type == MSM_DCVS_CORE_TYPE_CPU)
+ update_cpu_dcvs_params(info);
+
memcpy(&core->algo_param, &info->algo_param,
sizeof(struct msm_dcvs_algo_param));
@@ -916,10 +995,6 @@
core->task = kthread_run(msm_dcvs_do_freq, (void *)core,
"msm_dcvs/%d", core->dcvs_core_id);
ret = core->dcvs_core_id;
-
- INIT_DELAYED_WORK(&core->temperature_work, msm_dcvs_report_temp_work);
- schedule_delayed_work(&core->temperature_work,
- msecs_to_jiffies(info->thermal_poll_ms));
return ret;
bail:
core->dcvs_core_id = -1;
@@ -988,6 +1063,10 @@
}
force_start_slack_timer(core, timer_interval_us);
+ core->flags |= CORE_FLAG_TEMP_UPDATE;
+ INIT_DELAYED_WORK(&core->temperature_work, msm_dcvs_report_temp_work);
+ schedule_delayed_work(&core->temperature_work,
+ msecs_to_jiffies(core->info->thermal_poll_ms));
core->idle_enable(core->type_core_num, MSM_DCVS_ENABLE_IDLE_PULSE);
return 0;
@@ -1014,6 +1093,9 @@
return ret;
}
+ core->flags &= ~CORE_FLAG_TEMP_UPDATE;
+ cancel_delayed_work(&core->temperature_work);
+
core->idle_enable(core->type_core_num, MSM_DCVS_DISABLE_IDLE_PULSE);
/* Notify TZ to stop receiving idle info for the core */
ret = msm_dcvs_scm_event(core->dcvs_core_id, MSM_DCVS_SCM_DCVS_ENABLE,
@@ -1112,11 +1194,29 @@
}
late_initcall(msm_dcvs_late_init);
+static int __devinit dcvs_probe(struct platform_device *pdev)
+{
+ if (pdev->dev.platform_data)
+ dcvs_pdata = pdev->dev.platform_data;
+
+ return 0;
+}
+
+static struct platform_driver dcvs_driver = {
+ .probe = dcvs_probe,
+ .driver = {
+ .name = "dcvs",
+ .owner = THIS_MODULE,
+ },
+};
+
static int __init msm_dcvs_early_init(void)
{
int ret = 0;
int i;
+ platform_driver_register(&dcvs_driver);
+
if (!msm_dcvs_enabled) {
__info("Not enabled (%d)\n", msm_dcvs_enabled);
return 0;
diff --git a/arch/arm/mach-msm/msm_dsps.c b/arch/arm/mach-msm/msm_dsps.c
index 859fc15..0551130 100644
--- a/arch/arm/mach-msm/msm_dsps.c
+++ b/arch/arm/mach-msm/msm_dsps.c
@@ -585,7 +585,7 @@
*
* If the DSPS is running, then we must reset DSPS CPU & HW before
* setting the clocks off.
- * The DSPS reset should be done as part of the pil_put().
+ * The DSPS reset should be done as part of the subsystem_put().
* The DSPS reset should be used for error recovery if the DSPS firmware
* has crashed and re-loading the firmware is required.
*/
diff --git a/arch/arm/mach-msm/msm_mpdecision.c b/arch/arm/mach-msm/msm_mpdecision.c
index 9f6cc11..407be6a 100644
--- a/arch/arm/mach-msm/msm_mpdecision.c
+++ b/arch/arm/mach-msm/msm_mpdecision.c
@@ -123,6 +123,7 @@
static unsigned long last_nr;
static int num_present_hundreds;
+static ktime_t last_down_time;
#define RQ_AVG_INSIGNIFICANT_BITS 3
static bool ok_to_update_tz(int nr, int last_nr)
@@ -356,11 +357,8 @@
static int __cpuinit msm_mpd_do_hotplug(void *data)
{
int *event = (int *)data;
- static struct sched_param param = {.sched_priority = MAX_RT_PRIO - 1};
int cpu;
- sched_setscheduler(current, SCHED_FIFO, ¶m);
-
while (1) {
wait_event(msm_mpd.wait_hpq, *event || kthread_should_stop());
if (kthread_should_stop())
@@ -383,14 +381,15 @@
}
}
- for_each_possible_cpu(cpu) {
- if (!(atomic_read(&msm_mpd.algo_cpu_mask) & (1 << cpu))
- && cpu_online(cpu)) {
- bring_down_cpu(cpu);
- if (!cpu_online(cpu))
- goto restart;
- }
- }
+ if (ktime_to_ns(ktime_sub(ktime_get(), last_down_time)) >
+ 100 * NSEC_PER_MSEC)
+ for_each_possible_cpu(cpu)
+ if (!(atomic_read(&msm_mpd.algo_cpu_mask) &
+ (1 << cpu)) && cpu_online(cpu)) {
+ bring_down_cpu(cpu);
+ last_down_time = ktime_get();
+ break;
+ }
msm_mpd.hpupdate = HPUPDATE_WAITING;
}
@@ -400,13 +399,10 @@
static int msm_mpd_do_update_scm(void *data)
{
struct msm_mpd_scm_data *scm_data = (struct msm_mpd_scm_data *)data;
- static struct sched_param param = {.sched_priority = MAX_RT_PRIO - 1};
unsigned long flags;
enum msm_dcvs_scm_event event;
int nr;
- sched_setscheduler(current, SCHED_FIFO, ¶m);
-
while (1) {
wait_event(msm_mpd.wait_q,
msm_mpd.data.event == MSM_DCVS_SCM_MPD_QOS_TIMER_EXPIRED
diff --git a/arch/arm/mach-msm/msm_qmi_interface.c b/arch/arm/mach-msm/msm_qmi_interface.c
new file mode 100644
index 0000000..4c4635a
--- /dev/null
+++ b/arch/arm/mach-msm/msm_qmi_interface.c
@@ -0,0 +1,694 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/socket.h>
+#include <linux/gfp.h>
+#include <linux/qmi_encdec.h>
+
+#include <mach/msm_qmi_interface.h>
+#include <mach/msm_ipc_router.h>
+
+#include "msm_qmi_interface_priv.h"
+
+static LIST_HEAD(svc_event_nb_list);
+static DEFINE_MUTEX(svc_event_nb_list_lock);
+
+struct elem_info qmi_response_type_v01_ei[] = {
+ {
+ .data_type = QMI_SIGNED_2_BYTE_ENUM,
+ .elem_len = 1,
+ .elem_size = sizeof(uint16_t),
+ .is_array = NO_ARRAY,
+ .tlv_type = QMI_COMMON_TLV_TYPE,
+ .offset = offsetof(struct qmi_response_type_v01,
+ result),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_SIGNED_2_BYTE_ENUM,
+ .elem_len = 1,
+ .elem_size = sizeof(uint16_t),
+ .is_array = NO_ARRAY,
+ .tlv_type = QMI_COMMON_TLV_TYPE,
+ .offset = offsetof(struct qmi_response_type_v01,
+ error),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_EOTI,
+ .elem_len = 0,
+ .elem_size = 0,
+ .is_array = NO_ARRAY,
+ .tlv_type = QMI_COMMON_TLV_TYPE,
+ .offset = 0,
+ .ei_array = NULL,
+ },
+};
+
+static void qmi_event_notify(unsigned event, void *priv)
+{
+ struct qmi_handle *handle = (struct qmi_handle *)priv;
+ unsigned long flags;
+
+ if (!handle)
+ return;
+
+ mutex_lock(&handle->handle_lock);
+ if (handle->handle_reset) {
+ mutex_unlock(&handle->handle_lock);
+ return;
+ }
+
+ switch (event) {
+ case MSM_IPC_ROUTER_READ_CB:
+ spin_lock_irqsave(&handle->notify_lock, flags);
+ handle->notify(handle, QMI_RECV_MSG, handle->notify_priv);
+ spin_unlock_irqrestore(&handle->notify_lock, flags);
+ break;
+
+ default:
+ break;
+ }
+ mutex_unlock(&handle->handle_lock);
+}
+
+struct qmi_handle *qmi_handle_create(
+ void (*notify)(struct qmi_handle *handle,
+ enum qmi_event_type event, void *notify_priv),
+ void *notify_priv)
+{
+ struct qmi_handle *temp_handle;
+ struct msm_ipc_port *port_ptr;
+
+ temp_handle = kzalloc(sizeof(struct qmi_handle), GFP_KERNEL);
+ if (!temp_handle) {
+ pr_err("%s: Failure allocating client handle\n", __func__);
+ return NULL;
+ }
+
+ port_ptr = msm_ipc_router_create_port(qmi_event_notify,
+ (void *)temp_handle);
+ if (!port_ptr) {
+ pr_err("%s: IPC router port creation failed\n", __func__);
+ kfree(temp_handle);
+ return NULL;
+ }
+
+ temp_handle->src_port = port_ptr;
+ temp_handle->next_txn_id = 1;
+ INIT_LIST_HEAD(&temp_handle->txn_list);
+ mutex_init(&temp_handle->handle_lock);
+ spin_lock_init(&temp_handle->notify_lock);
+ temp_handle->notify = notify;
+ temp_handle->notify_priv = notify_priv;
+ temp_handle->handle_reset = 0;
+ init_waitqueue_head(&temp_handle->reset_waitq);
+ return temp_handle;
+}
+EXPORT_SYMBOL(qmi_handle_create);
+
+static void clean_txn_info(struct qmi_handle *handle)
+{
+ struct qmi_txn *txn_handle, *temp_txn_handle;
+
+ list_for_each_entry_safe(txn_handle, temp_txn_handle,
+ &handle->txn_list, list) {
+ if (txn_handle->type == QMI_ASYNC_TXN) {
+ list_del(&txn_handle->list);
+ kfree(txn_handle);
+ } else if (txn_handle->type == QMI_SYNC_TXN) {
+ wake_up(&txn_handle->wait_q);
+ }
+ }
+}
+
+int qmi_handle_destroy(struct qmi_handle *handle)
+{
+ int rc;
+
+ if (!handle)
+ return -EINVAL;
+
+ mutex_lock(&handle->handle_lock);
+ handle->handle_reset = 1;
+ clean_txn_info(handle);
+ mutex_unlock(&handle->handle_lock);
+
+ rc = wait_event_interruptible(handle->reset_waitq,
+ list_empty(&handle->txn_list));
+
+ /* TODO: Destroy client owned transaction */
+ msm_ipc_router_close_port((struct msm_ipc_port *)(handle->src_port));
+ kfree(handle->dest_info);
+ kfree(handle);
+ return 0;
+}
+EXPORT_SYMBOL(qmi_handle_destroy);
+
+int qmi_register_ind_cb(struct qmi_handle *handle,
+ void (*ind_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ unsigned int msg_len, void *ind_cb_priv),
+ void *ind_cb_priv)
+{
+ if (!handle)
+ return -EINVAL;
+
+ mutex_lock(&handle->handle_lock);
+ if (handle->handle_reset) {
+ mutex_unlock(&handle->handle_lock);
+ return -ENETRESET;
+ }
+
+ handle->ind_cb = ind_cb;
+ handle->ind_cb_priv = ind_cb_priv;
+ mutex_unlock(&handle->handle_lock);
+ return 0;
+}
+EXPORT_SYMBOL(qmi_register_ind_cb);
+
+static int qmi_encode_and_send_req(struct qmi_txn **ret_txn_handle,
+ struct qmi_handle *handle, enum txn_type type,
+ struct msg_desc *req_desc, void *req, unsigned int req_len,
+ struct msg_desc *resp_desc, void *resp, unsigned int resp_len,
+ void (*resp_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ void *resp_cb_data),
+ void *resp_cb_data)
+{
+ struct qmi_txn *txn_handle;
+ int rc, encoded_req_len;
+ void *encoded_req;
+
+ if (!handle || !handle->dest_info ||
+ !req_desc || !req || !resp_desc || !resp)
+ return -EINVAL;
+
+ mutex_lock(&handle->handle_lock);
+ if (handle->handle_reset) {
+ mutex_unlock(&handle->handle_lock);
+ return -ENETRESET;
+ }
+
+ /* Allocate Transaction Info */
+ txn_handle = kzalloc(sizeof(struct qmi_txn), GFP_KERNEL);
+ if (!txn_handle) {
+ pr_err("%s: Failed to allocate txn handle\n", __func__);
+ mutex_unlock(&handle->handle_lock);
+ return -ENOMEM;
+ }
+ txn_handle->type = type;
+ INIT_LIST_HEAD(&txn_handle->list);
+ init_waitqueue_head(&txn_handle->wait_q);
+
+ /* Cache the parameters passed & mark it as sync*/
+ txn_handle->handle = handle;
+ txn_handle->resp_desc = resp_desc;
+ txn_handle->resp = resp;
+ txn_handle->resp_len = resp_len;
+ txn_handle->resp_received = 0;
+ txn_handle->resp_cb = resp_cb;
+ txn_handle->resp_cb_data = resp_cb_data;
+
+ /* Encode the request msg */
+ encoded_req_len = req_desc->max_msg_len + QMI_HEADER_SIZE;
+ encoded_req = kmalloc(encoded_req_len, GFP_KERNEL);
+ if (!encoded_req) {
+ pr_err("%s: Failed to allocate req_msg_buf\n", __func__);
+ rc = -ENOMEM;
+ goto encode_and_send_req_err1;
+ }
+ rc = qmi_kernel_encode(req_desc,
+ (void *)(encoded_req + QMI_HEADER_SIZE),
+ req_desc->max_msg_len, req);
+ if (rc < 0) {
+ pr_err("%s: Encode Failure %d\n", __func__, rc);
+ goto encode_and_send_req_err2;
+ }
+ encoded_req_len = rc;
+
+ /* Encode the header & Add to the txn_list */
+ if (!handle->next_txn_id)
+ handle->next_txn_id++;
+ txn_handle->txn_id = handle->next_txn_id++;
+ encode_qmi_header(encoded_req, QMI_REQUEST_CONTROL_FLAG,
+ txn_handle->txn_id, req_desc->msg_id,
+ encoded_req_len);
+ encoded_req_len += QMI_HEADER_SIZE;
+ list_add_tail(&txn_handle->list, &handle->txn_list);
+
+ /* Send the request */
+ rc = msm_ipc_router_send_msg((struct msm_ipc_port *)(handle->src_port),
+ (struct msm_ipc_addr *)handle->dest_info,
+ encoded_req, encoded_req_len);
+ if (rc < 0) {
+ pr_err("%s: send_msg failed %d\n", __func__, rc);
+ goto encode_and_send_req_err3;
+ }
+ mutex_unlock(&handle->handle_lock);
+
+ kfree(encoded_req);
+ if (ret_txn_handle)
+ *ret_txn_handle = txn_handle;
+ return 0;
+
+encode_and_send_req_err3:
+ list_del(&txn_handle->list);
+encode_and_send_req_err2:
+ kfree(encoded_req);
+encode_and_send_req_err1:
+ kfree(txn_handle);
+ mutex_unlock(&handle->handle_lock);
+ return rc;
+}
+
+int qmi_send_req_wait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ unsigned long timeout_ms)
+{
+ struct qmi_txn *txn_handle = NULL;
+ int rc;
+
+ /* Encode and send the request */
+ rc = qmi_encode_and_send_req(&txn_handle, handle, QMI_SYNC_TXN,
+ req_desc, req, req_len,
+ resp_desc, resp, resp_len,
+ NULL, NULL);
+ if (rc < 0) {
+ pr_err("%s: Error encode & send req: %d\n", __func__, rc);
+ return rc;
+ }
+
+ /* Wait for the response */
+ if (!timeout_ms) {
+ rc = wait_event_interruptible(txn_handle->wait_q,
+ (txn_handle->resp_received ||
+ handle->handle_reset));
+ } else {
+ rc = wait_event_interruptible_timeout(txn_handle->wait_q,
+ (txn_handle->resp_received ||
+ handle->handle_reset),
+ msecs_to_jiffies(timeout_ms));
+ if (rc == 0)
+ rc = -ETIMEDOUT;
+ }
+
+ mutex_lock(&handle->handle_lock);
+ if (!txn_handle->resp_received) {
+ pr_err("%s: Response Wait Error %d\n", __func__, rc);
+ if (handle->handle_reset)
+ rc = -ENETRESET;
+ if (rc >= 0)
+ rc = -EFAULT;
+ goto send_req_wait_err;
+ }
+ rc = 0;
+
+send_req_wait_err:
+ list_del(&txn_handle->list);
+ kfree(txn_handle);
+ mutex_unlock(&handle->handle_lock);
+ wake_up(&handle->reset_waitq);
+ return rc;
+}
+EXPORT_SYMBOL(qmi_send_req_wait);
+
+int qmi_send_req_nowait(struct qmi_handle *handle,
+ struct msg_desc *req_desc,
+ void *req, unsigned int req_len,
+ struct msg_desc *resp_desc,
+ void *resp, unsigned int resp_len,
+ void (*resp_cb)(struct qmi_handle *handle,
+ unsigned int msg_id, void *msg,
+ void *resp_cb_data),
+ void *resp_cb_data)
+{
+ return qmi_encode_and_send_req(NULL, handle, QMI_ASYNC_TXN,
+ req_desc, req, req_len,
+ resp_desc, resp, resp_len,
+ resp_cb, resp_cb_data);
+}
+EXPORT_SYMBOL(qmi_send_req_nowait);
+
+static struct qmi_txn *find_txn_handle(struct qmi_handle *handle,
+ uint16_t txn_id)
+{
+ struct qmi_txn *txn_handle;
+
+ list_for_each_entry(txn_handle, &handle->txn_list, list) {
+ if (txn_handle->txn_id == txn_id)
+ return txn_handle;
+ }
+ return NULL;
+}
+
+static int handle_qmi_response(struct qmi_handle *handle,
+ unsigned char *resp_msg, uint16_t txn_id,
+ uint16_t msg_id, uint16_t msg_len)
+{
+ struct qmi_txn *txn_handle;
+ int rc;
+
+ /* Find the transaction handle */
+ txn_handle = find_txn_handle(handle, txn_id);
+ if (!txn_handle) {
+ pr_err("%s Response received for non-existent txn_id %d\n",
+ __func__, txn_id);
+ return -EINVAL;
+ }
+
+ /* Decode the message */
+ rc = qmi_kernel_decode(txn_handle->resp_desc, txn_handle->resp,
+ (void *)(resp_msg + QMI_HEADER_SIZE), msg_len);
+ if (rc < 0) {
+ pr_err("%s: Response Decode Failure <%d: %d: %d> rc: %d\n",
+ __func__, txn_id, msg_id, msg_len, rc);
+ wake_up(&txn_handle->wait_q);
+ if (txn_handle->type == QMI_ASYNC_TXN) {
+ list_del(&txn_handle->list);
+ kfree(txn_handle);
+ }
+ return rc;
+ }
+
+ /* Handle async or sync resp */
+ switch (txn_handle->type) {
+ case QMI_SYNC_TXN:
+ txn_handle->resp_received = 1;
+ wake_up(&txn_handle->wait_q);
+ rc = 0;
+ break;
+
+ case QMI_ASYNC_TXN:
+ if (txn_handle->resp_cb)
+ txn_handle->resp_cb(txn_handle->handle, msg_id,
+ txn_handle->resp,
+ txn_handle->resp_cb_data);
+ list_del(&txn_handle->list);
+ kfree(txn_handle);
+ rc = 0;
+ break;
+
+ default:
+ pr_err("%s: Unrecognized transaction type\n", __func__);
+ return -EFAULT;
+ }
+ return rc;
+}
+
+static int handle_qmi_indication(struct qmi_handle *handle, void *msg,
+ unsigned int msg_id, unsigned int msg_len)
+{
+ if (handle->ind_cb)
+ handle->ind_cb(handle, msg_id, msg,
+ msg_len, handle->ind_cb_priv);
+ return 0;
+}
+
+int qmi_recv_msg(struct qmi_handle *handle)
+{
+ unsigned int recv_msg_len;
+ unsigned char *recv_msg = NULL;
+ struct msm_ipc_addr src_addr;
+ unsigned char cntl_flag;
+ uint16_t txn_id, msg_id, msg_len;
+ int rc;
+
+ if (!handle)
+ return -EINVAL;
+
+ mutex_lock(&handle->handle_lock);
+ if (handle->handle_reset) {
+ mutex_unlock(&handle->handle_lock);
+ return -ENETRESET;
+ }
+
+ /* Read the messages */
+ rc = msm_ipc_router_read_msg((struct msm_ipc_port *)(handle->src_port),
+ &src_addr, &recv_msg, &recv_msg_len);
+ if (rc < 0) {
+ pr_err("%s: Read failed %d\n", __func__, rc);
+ mutex_unlock(&handle->handle_lock);
+ return rc;
+ }
+
+ /* Decode the header & Handle the req, resp, indication message */
+ decode_qmi_header(recv_msg, &cntl_flag, &txn_id, &msg_id, &msg_len);
+
+ switch (cntl_flag) {
+ case QMI_RESPONSE_CONTROL_FLAG:
+ rc = handle_qmi_response(handle, recv_msg,
+ txn_id, msg_id, msg_len);
+ break;
+
+ case QMI_INDICATION_CONTROL_FLAG:
+ rc = handle_qmi_indication(handle, recv_msg, msg_id, msg_len);
+ break;
+
+ default:
+ rc = -EFAULT;
+ pr_err("%s: Unsupported message type %d\n",
+ __func__, cntl_flag);
+ break;
+ }
+ kfree(recv_msg);
+ mutex_unlock(&handle->handle_lock);
+ return rc;
+}
+EXPORT_SYMBOL(qmi_recv_msg);
+
+int qmi_connect_to_service(struct qmi_handle *handle,
+ uint32_t service_id, uint32_t instance_id)
+{
+ struct msm_ipc_port_name svc_name;
+ struct msm_ipc_server_info svc_info;
+ struct msm_ipc_addr *svc_dest_addr;
+ int rc;
+
+ if (!handle)
+ return -EINVAL;
+
+ svc_dest_addr = kzalloc(sizeof(struct msm_ipc_addr),
+ GFP_KERNEL);
+ if (!svc_dest_addr) {
+ pr_err("%s: Failure allocating memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ svc_name.service = service_id;
+ svc_name.instance = instance_id;
+
+ rc = msm_ipc_router_lookup_server_name(&svc_name, &svc_info, 1, 0xFF);
+ if (rc <= 0) {
+ pr_err("%s: Server not found\n", __func__);
+ return -ENODEV;
+ }
+ svc_dest_addr->addrtype = MSM_IPC_ADDR_ID;
+ svc_dest_addr->addr.port_addr.node_id = svc_info.node_id;
+ svc_dest_addr->addr.port_addr.port_id = svc_info.port_id;
+ mutex_lock(&handle->handle_lock);
+ if (handle->handle_reset) {
+ mutex_unlock(&handle->handle_lock);
+ return -ENETRESET;
+ }
+ handle->dest_info = svc_dest_addr;
+ mutex_unlock(&handle->handle_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(qmi_connect_to_service);
+
+static struct svc_event_nb *find_svc_event_nb_by_name(const char *name)
+{
+ struct svc_event_nb *temp;
+
+ list_for_each_entry(temp, &svc_event_nb_list, list) {
+ if (!strncmp(name, temp->pdriver_name,
+ sizeof(temp->pdriver_name)))
+ return temp;
+ }
+ return NULL;
+}
+
+static int qmi_svc_event_probe(struct platform_device *pdev)
+{
+ struct svc_event_nb *temp;
+ unsigned long flags;
+
+ mutex_lock(&svc_event_nb_list_lock);
+ temp = find_svc_event_nb_by_name(pdev->name);
+ if (!temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&temp->nb_lock, flags);
+ temp->svc_avail = 1;
+ raw_notifier_call_chain(&temp->svc_event_rcvr_list,
+ QMI_SERVER_ARRIVE, NULL);
+ spin_unlock_irqrestore(&temp->nb_lock, flags);
+ mutex_unlock(&svc_event_nb_list_lock);
+ return 0;
+}
+
+static int qmi_svc_event_remove(struct platform_device *pdev)
+{
+ struct svc_event_nb *temp;
+ unsigned long flags;
+
+ mutex_lock(&svc_event_nb_list_lock);
+ temp = find_svc_event_nb_by_name(pdev->name);
+ if (!temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&temp->nb_lock, flags);
+ temp->svc_avail = 0;
+ raw_notifier_call_chain(&temp->svc_event_rcvr_list,
+ QMI_SERVER_EXIT, NULL);
+ spin_unlock_irqrestore(&temp->nb_lock, flags);
+ mutex_unlock(&svc_event_nb_list_lock);
+ return 0;
+}
+
+static struct svc_event_nb *find_svc_event_nb(uint32_t service_id,
+ uint32_t instance_id)
+{
+ struct svc_event_nb *temp;
+
+ list_for_each_entry(temp, &svc_event_nb_list, list) {
+ if (temp->service_id == service_id &&
+ temp->instance_id == instance_id)
+ return temp;
+ }
+ return NULL;
+}
+
+static struct svc_event_nb *find_and_add_svc_event_nb(uint32_t service_id,
+ uint32_t instance_id)
+{
+ struct svc_event_nb *temp;
+ int ret;
+
+ mutex_lock(&svc_event_nb_list_lock);
+ temp = find_svc_event_nb(service_id, instance_id);
+ if (temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ return temp;
+ }
+
+ temp = kzalloc(sizeof(struct svc_event_nb), GFP_KERNEL);
+ if (!temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ pr_err("%s: Failed to alloc notifier block\n", __func__);
+ return temp;
+ }
+
+ spin_lock_init(&temp->nb_lock);
+ temp->service_id = service_id;
+ temp->instance_id = instance_id;
+ INIT_LIST_HEAD(&temp->list);
+ temp->svc_driver.probe = qmi_svc_event_probe;
+ temp->svc_driver.remove = qmi_svc_event_remove;
+ scnprintf(temp->pdriver_name, sizeof(temp->pdriver_name),
+ "QMI%08x:%08x", service_id, instance_id);
+ temp->svc_driver.driver.name = temp->pdriver_name;
+ RAW_INIT_NOTIFIER_HEAD(&temp->svc_event_rcvr_list);
+
+ list_add_tail(&temp->list, &svc_event_nb_list);
+ mutex_unlock(&svc_event_nb_list_lock);
+
+ ret = platform_driver_register(&temp->svc_driver);
+ if (ret < 0) {
+ pr_err("%s: Failed pdriver register\n", __func__);
+ mutex_lock(&svc_event_nb_list_lock);
+ list_del(&temp->list);
+ mutex_unlock(&svc_event_nb_list_lock);
+ kfree(temp);
+ temp = NULL;
+ }
+
+ return temp;
+}
+
+int qmi_svc_event_notifier_register(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb)
+{
+ struct svc_event_nb *temp;
+ unsigned long flags;
+ int ret;
+
+ temp = find_and_add_svc_event_nb(service_id, instance_id);
+ if (!temp)
+ return -EFAULT;
+
+ mutex_lock(&svc_event_nb_list_lock);
+ temp = find_svc_event_nb(service_id, instance_id);
+ if (!temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ return -EFAULT;
+ }
+ spin_lock_irqsave(&temp->nb_lock, flags);
+ if (temp->svc_avail)
+ nb->notifier_call(nb, QMI_SERVER_ARRIVE, NULL);
+
+ ret = raw_notifier_chain_register(&temp->svc_event_rcvr_list, nb);
+ spin_unlock_irqrestore(&temp->nb_lock, flags);
+ mutex_unlock(&svc_event_nb_list_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(qmi_svc_event_notifier_register);
+
+int qmi_svc_event_notifier_unregister(uint32_t service_id,
+ uint32_t instance_id,
+ struct notifier_block *nb)
+{
+ int ret;
+ struct svc_event_nb *temp;
+ unsigned long flags;
+
+ mutex_lock(&svc_event_nb_list_lock);
+ temp = find_svc_event_nb(service_id, instance_id);
+ if (!temp) {
+ mutex_unlock(&svc_event_nb_list_lock);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&temp->nb_lock, flags);
+ ret = raw_notifier_chain_unregister(&temp->svc_event_rcvr_list, nb);
+ spin_unlock_irqrestore(&temp->nb_lock, flags);
+ mutex_unlock(&svc_event_nb_list_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(qmi_svc_event_notifier_unregister);
+
+MODULE_DESCRIPTION("MSM QMI Interface");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/msm_qmi_interface_priv.h b/arch/arm/mach-msm/msm_qmi_interface_priv.h
new file mode 100644
index 0000000..58f1ce3
--- /dev/null
+++ b/arch/arm/mach-msm/msm_qmi_interface_priv.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MSM_QMI_INTERFACE_PRIV_H_
+#define _MSM_QMI_INTERFACE_PRIV_H_
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/socket.h>
+#include <linux/gfp.h>
+#include <linux/platform_device.h>
+#include <linux/qmi_encdec.h>
+
+#include <mach/msm_qmi_interface.h>
+
+enum txn_type {
+ QMI_SYNC_TXN = 1,
+ QMI_ASYNC_TXN,
+};
+
+struct qmi_txn {
+ struct list_head list;
+ uint16_t txn_id;
+ enum txn_type type;
+ struct qmi_handle *handle;
+ struct msg_desc *resp_desc;
+ void *resp;
+ unsigned int resp_len;
+ int resp_received;
+ void (*resp_cb)(struct qmi_handle *handle, unsigned int msg_id,
+ void *msg, void *resp_cb_data);
+ void *resp_cb_data;
+ wait_queue_head_t wait_q;
+};
+
+struct svc_event_nb {
+ spinlock_t nb_lock;
+ uint32_t service_id;
+ uint32_t instance_id;
+ char pdriver_name[32];
+ int svc_avail;
+ struct platform_driver svc_driver;
+ struct raw_notifier_head svc_event_rcvr_list;
+ struct list_head list;
+};
+
+#endif
diff --git a/arch/arm/mach-msm/msm_smem_iface.c b/arch/arm/mach-msm/msm_smem_iface.c
index b35467b..5ae5772 100644
--- a/arch/arm/mach-msm/msm_smem_iface.c
+++ b/arch/arm/mach-msm/msm_smem_iface.c
@@ -42,4 +42,5 @@
cpr_info->turbo_quot = temp_cpr_info->turbo_quot;
cpr_info->pvs_fuse = temp_cpr_info->pvs_fuse;
cpr_info->floor_fuse = temp_cpr_info->floor_fuse;
+ cpr_info->disable_cpr = temp_cpr_info->disable_cpr;
}
diff --git a/arch/arm/mach-msm/msm_smem_iface.h b/arch/arm/mach-msm/msm_smem_iface.h
index a6d6714..2daf76d 100644
--- a/arch/arm/mach-msm/msm_smem_iface.h
+++ b/arch/arm/mach-msm/msm_smem_iface.h
@@ -16,7 +16,6 @@
#define __ARCH_ARM_MACH_MSM_SMEM_IFACE_H
#include <mach/msm_smsm.h>
-#include "smd_private.h"
#define MAX_KEY_EVENTS 10
#define MAX_SEC_KEY_PAYLOAD 32
@@ -39,6 +38,7 @@
uint8_t turbo_quot; /* CPRFUSE[1:7] : TURBO QUOT*/
uint8_t pvs_fuse; /* TURBO PVS FUSE */
uint8_t floor_fuse; /* Vmin Selection. b1: FAB_ID(2), b0: CPR_fuse[0] */
+ bool disable_cpr;
};
struct boot_info_for_apps {
@@ -49,7 +49,7 @@
uint16_t boot_keys_pressed[MAX_KEY_EVENTS]; /* Log of key presses */
uint32_t timetick; /* Modem tick timer value before apps out of reset */
struct cpr_info_type cpr_info;
- uint8_t PAD[24];
+ uint8_t PAD[23];
};
void msm_smem_get_cpr_info(struct cpr_info_type *cpr_info);
diff --git a/arch/arm/mach-msm/no-pm.c b/arch/arm/mach-msm/no-pm.c
index d38b416..d460c70 100644
--- a/arch/arm/mach-msm/no-pm.c
+++ b/arch/arm/mach-msm/no-pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -12,13 +12,15 @@
*/
#include <linux/module.h>
-
+#include <asm/proc-fns.h>
#include <mach/cpuidle.h>
#include "idle.h"
#include "pm.h"
void arch_idle(void)
-{ }
+{
+ cpu_do_idle();
+}
void msm_pm_set_platform_data(struct msm_pm_platform_data *data, int count)
{ }
diff --git a/arch/arm/mach-msm/peripheral-loader.c b/arch/arm/mach-msm/peripheral-loader.c
index 4ff34bf..65e05a9 100644
--- a/arch/arm/mach-msm/peripheral-loader.c
+++ b/arch/arm/mach-msm/peripheral-loader.c
@@ -12,28 +12,33 @@
#include <linux/module.h>
#include <linux/string.h>
-#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/io.h>
-#include <linux/debugfs.h>
#include <linux/elf.h>
#include <linux/mutex.h>
#include <linux/memblock.h>
#include <linux/slab.h>
-#include <linux/atomic.h>
#include <linux/suspend.h>
#include <linux/rwsem.h>
#include <linux/sysfs.h>
#include <linux/workqueue.h>
#include <linux/jiffies.h>
#include <linux/wakelock.h>
+#include <linux/err.h>
+#include <linux/msm_ion.h>
+#include <linux/list.h>
+#include <linux/list_sort.h>
#include <asm/uaccess.h>
#include <asm/setup.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
+#define pil_err(desc, fmt, ...) \
+ dev_err(desc->dev, "%s: " fmt, desc->name, ##__VA_ARGS__)
+#define pil_info(desc, fmt, ...) \
+ dev_info(desc->dev, "%s: " fmt, desc->name, ##__VA_ARGS__)
+
/**
* proxy_timeout - Override for proxy vote timeouts
* -1: Use driver-specified timeout
@@ -43,146 +48,376 @@
static int proxy_timeout_ms = -1;
module_param(proxy_timeout_ms, int, S_IRUGO | S_IWUSR);
-enum pil_state {
- PIL_OFFLINE,
- PIL_ONLINE,
+/**
+ * struct pil_mdt - Representation of <name>.mdt file in memory
+ * @hdr: ELF32 header
+ * @phdr: ELF32 program headers
+ */
+struct pil_mdt {
+ struct elf32_hdr hdr;
+ struct elf32_phdr phdr[];
};
-static const char *pil_states[] = {
- [PIL_OFFLINE] = "OFFLINE",
- [PIL_ONLINE] = "ONLINE",
+/**
+ * struct pil_seg - memory map representing one segment
+ * @next: points to next seg mentor NULL if last segment
+ * @paddr: start address of segment
+ * @sz: size of segment
+ * @filesz: size of segment on disk
+ * @num: segment number
+ * @relocated: true if segment is relocated, false otherwise
+ *
+ * Loosely based on an elf program header. Contains all necessary information
+ * to load and initialize a segment of the image in memory.
+ */
+struct pil_seg {
+ phys_addr_t paddr;
+ unsigned long sz;
+ unsigned long filesz;
+ int num;
+ struct list_head list;
+ bool relocated;
};
-struct pil_device {
- struct pil_desc *desc;
- int count;
- enum pil_state state;
- struct mutex lock;
- struct device dev;
- struct module *owner;
-#ifdef CONFIG_DEBUG_FS
- struct dentry *dentry;
-#endif
+/**
+ * struct pil_priv - Private state for a pil_desc
+ * @proxy: work item used to run the proxy unvoting routine
+ * @wlock: wakelock to prevent suspend during pil_boot
+ * @wname: name of @wlock
+ * @desc: pointer to pil_desc this is private data for
+ * @seg: list of segments sorted by physical address
+ * @entry_addr: physical address where processor starts booting at
+ * @base_addr: smallest start address among all segments that are relocatable
+ * @region_start: address where relocatable region starts or lowest address
+ * for non-relocatable images
+ * @region_end: address where relocatable region ends or highest address for
+ * non-relocatable images
+ * @region: region allocated for relocatable images
+ *
+ * This struct contains data for a pil_desc that should not be exposed outside
+ * of this file. This structure points to the descriptor and the descriptor
+ * points to this structure so that PIL drivers can't access the private
+ * data of a descriptor but this file can access both.
+ */
+struct pil_priv {
struct delayed_work proxy;
struct wake_lock wlock;
- char wake_name[32];
+ char wname[32];
+ struct pil_desc *desc;
+ struct list_head segs;
+ phys_addr_t entry_addr;
+ phys_addr_t base_addr;
+ phys_addr_t region_start;
+ phys_addr_t region_end;
+ struct ion_handle *region;
};
-#define to_pil_device(d) container_of(d, struct pil_device, dev)
+static struct ion_client *ion;
-static ssize_t name_show(struct device *dev, struct device_attribute *attr,
- char *buf)
+/**
+ * pil_get_entry_addr() - Retrieve the entry address of a peripheral image
+ * @desc: descriptor from pil_desc_init()
+ *
+ * Returns the physical address where the image boots at or 0 if unknown.
+ */
+phys_addr_t pil_get_entry_addr(struct pil_desc *desc)
{
- return snprintf(buf, PAGE_SIZE, "%s\n", to_pil_device(dev)->desc->name);
+ return desc->priv ? desc->priv->entry_addr : 0;
}
-
-static ssize_t state_show(struct device *dev, struct device_attribute *attr,
- char *buf)
-{
- enum pil_state state = to_pil_device(dev)->state;
- return snprintf(buf, PAGE_SIZE, "%s\n", pil_states[state]);
-}
-
-static struct device_attribute pil_attrs[] = {
- __ATTR_RO(name),
- __ATTR_RO(state),
- { },
-};
-
-struct bus_type pil_bus_type = {
- .name = "pil",
- .dev_attrs = pil_attrs,
-};
-
-static int __find_peripheral(struct device *dev, void *data)
-{
- struct pil_device *pdev = to_pil_device(dev);
- return !strncmp(pdev->desc->name, data, INT_MAX);
-}
-
-static struct pil_device *find_peripheral(const char *str)
-{
- struct device *dev;
-
- if (!str)
- return NULL;
-
- dev = bus_find_device(&pil_bus_type, NULL, (void *)str,
- __find_peripheral);
- return dev ? to_pil_device(dev) : NULL;
-}
+EXPORT_SYMBOL(pil_get_entry_addr);
static void pil_proxy_work(struct work_struct *work)
{
- struct pil_device *pil;
+ struct delayed_work *delayed = to_delayed_work(work);
+ struct pil_priv *priv = container_of(delayed, struct pil_priv, proxy);
+ struct pil_desc *desc = priv->desc;
- pil = container_of(work, struct pil_device, proxy.work);
- pil->desc->ops->proxy_unvote(pil->desc);
- wake_unlock(&pil->wlock);
+ desc->ops->proxy_unvote(desc);
+ wake_unlock(&priv->wlock);
+ module_put(desc->owner);
}
-static int pil_proxy_vote(struct pil_device *pil)
+static int pil_proxy_vote(struct pil_desc *desc)
{
int ret = 0;
+ struct pil_priv *priv = desc->priv;
- if (pil->desc->ops->proxy_vote) {
- wake_lock(&pil->wlock);
- ret = pil->desc->ops->proxy_vote(pil->desc);
+ if (desc->ops->proxy_vote) {
+ wake_lock(&priv->wlock);
+ ret = desc->ops->proxy_vote(desc);
if (ret)
- wake_unlock(&pil->wlock);
+ wake_unlock(&priv->wlock);
}
return ret;
}
-static void pil_proxy_unvote(struct pil_device *pil, unsigned long timeout)
+static void pil_proxy_unvote(struct pil_desc *desc, unsigned long timeout)
{
+ struct pil_priv *priv = desc->priv;
+
if (proxy_timeout_ms >= 0)
timeout = proxy_timeout_ms;
- if (timeout && pil->desc->ops->proxy_unvote)
- schedule_delayed_work(&pil->proxy, msecs_to_jiffies(timeout));
+ if (timeout && desc->ops->proxy_unvote) {
+ if (WARN_ON(!try_module_get(desc->owner)))
+ return;
+ schedule_delayed_work(&priv->proxy, msecs_to_jiffies(timeout));
+ }
+}
+
+static bool segment_is_relocatable(const struct elf32_phdr *p)
+{
+ return !!(p->p_flags & BIT(27));
+}
+
+static phys_addr_t pil_reloc(const struct pil_priv *priv, phys_addr_t addr)
+{
+ return addr - priv->base_addr + priv->region_start;
+}
+
+static struct pil_seg *pil_init_seg(const struct pil_desc *desc,
+ const struct elf32_phdr *phdr, int num)
+{
+ bool reloc = segment_is_relocatable(phdr);
+ const struct pil_priv *priv = desc->priv;
+ struct pil_seg *seg;
+
+ if (!reloc && memblock_overlaps_memory(phdr->p_paddr, phdr->p_memsz)) {
+ pil_err(desc, "kernel memory would be overwritten [%#08lx, %#08lx)\n",
+ (unsigned long)phdr->p_paddr,
+ (unsigned long)(phdr->p_paddr + phdr->p_memsz));
+ return ERR_PTR(-EPERM);
+ }
+
+ seg = kmalloc(sizeof(*seg), GFP_KERNEL);
+ if (!seg)
+ return ERR_PTR(-ENOMEM);
+ seg->num = num;
+ seg->paddr = reloc ? pil_reloc(priv, phdr->p_paddr) : phdr->p_paddr;
+ seg->filesz = phdr->p_filesz;
+ seg->sz = phdr->p_memsz;
+ seg->relocated = reloc;
+ INIT_LIST_HEAD(&seg->list);
+
+ return seg;
+}
+
+#define segment_is_hash(flag) (((flag) & (0x7 << 24)) == (0x2 << 24))
+
+static int segment_is_loadable(const struct elf32_phdr *p)
+{
+ return (p->p_type == PT_LOAD) && !segment_is_hash(p->p_flags) &&
+ p->p_memsz;
+}
+
+static void pil_dump_segs(const struct pil_priv *priv)
+{
+ struct pil_seg *seg;
+
+ list_for_each_entry(seg, &priv->segs, list) {
+ pil_info(priv->desc, "%d: %#08zx %#08lx\n", seg->num,
+ seg->paddr, seg->paddr + seg->sz);
+ }
+}
+
+/*
+ * Ensure the entry address lies within the image limits and if the image is
+ * relocatable ensure it lies within a relocatable segment.
+ */
+static int pil_init_entry_addr(struct pil_priv *priv, const struct pil_mdt *mdt)
+{
+ struct pil_seg *seg;
+ phys_addr_t entry = mdt->hdr.e_entry;
+ bool image_relocated = priv->region;
+
+ if (image_relocated)
+ entry = pil_reloc(priv, entry);
+ priv->entry_addr = entry;
+
+ if (priv->desc->flags & PIL_SKIP_ENTRY_CHECK)
+ return 0;
+
+ list_for_each_entry(seg, &priv->segs, list) {
+ if (entry >= seg->paddr && entry < seg->paddr + seg->sz) {
+ if (!image_relocated)
+ return 0;
+ else if (seg->relocated)
+ return 0;
+ }
+ }
+ pil_err(priv->desc, "entry address %08zx not within range\n", entry);
+ pil_dump_segs(priv);
+ return -EADDRNOTAVAIL;
+}
+
+static int pil_alloc_region(struct pil_priv *priv, phys_addr_t min_addr,
+ phys_addr_t max_addr, size_t align)
+{
+ struct ion_handle *region;
+ int ret;
+ unsigned int mask;
+ size_t size = round_up(max_addr - min_addr, align);
+
+ if (!ion) {
+ WARN_ON_ONCE("No ION client, can't support relocation\n");
+ return -ENOMEM;
+ }
+
+ /* Force alignment due to linker scripts not getting it right */
+ if (align > SZ_1M) {
+ mask = ION_HEAP(ION_PIL2_HEAP_ID);
+ align = SZ_4M;
+ } else {
+ mask = ION_HEAP(ION_PIL1_HEAP_ID);
+ align = SZ_1M;
+ }
+
+ region = ion_alloc(ion, size, align, mask, 0);
+ if (IS_ERR(region)) {
+ pil_err(priv->desc, "Failed to allocate relocatable region\n");
+ return PTR_ERR(region);
+ }
+
+ ret = ion_phys(ion, region, (ion_phys_addr_t *)&priv->region_start,
+ &size);
+ if (ret) {
+ ion_free(ion, region);
+ return ret;
+ }
+
+ priv->region = region;
+ priv->region_end = priv->region_start + size;
+ priv->base_addr = min_addr;
+
+ return 0;
+}
+
+static int pil_setup_region(struct pil_priv *priv, const struct pil_mdt *mdt)
+{
+ const struct elf32_phdr *phdr;
+ phys_addr_t min_addr_r, min_addr_n, max_addr_r, max_addr_n, start, end;
+ size_t align = 0;
+ int i, ret = 0;
+ bool relocatable = false;
+
+ min_addr_n = min_addr_r = (phys_addr_t)ULLONG_MAX;
+ max_addr_n = max_addr_r = 0;
+
+ /* Find the image limits */
+ for (i = 0; i < mdt->hdr.e_phnum; i++) {
+ phdr = &mdt->phdr[i];
+ if (!segment_is_loadable(phdr))
+ continue;
+
+ start = phdr->p_paddr;
+ end = start + phdr->p_memsz;
+
+ if (segment_is_relocatable(phdr)) {
+ min_addr_r = min(min_addr_r, start);
+ max_addr_r = max(max_addr_r, end);
+ /*
+ * Lowest relocatable segment dictates alignment of
+ * relocatable region
+ */
+ if (min_addr_r == start)
+ align = phdr->p_align;
+ relocatable = true;
+ } else {
+ min_addr_n = min(min_addr_n, start);
+ max_addr_n = max(max_addr_n, end);
+ }
+
+ }
+
+ if (relocatable) {
+ ret = pil_alloc_region(priv, min_addr_r, max_addr_r, align);
+ } else {
+ priv->region_start = min_addr_n;
+ priv->region_end = max_addr_n;
+ priv->base_addr = min_addr_n;
+ }
+
+ return ret;
+}
+
+static int pil_cmp_seg(void *priv, struct list_head *a, struct list_head *b)
+{
+ struct pil_seg *seg_a = list_entry(a, struct pil_seg, list);
+ struct pil_seg *seg_b = list_entry(b, struct pil_seg, list);
+
+ return seg_a->paddr - seg_b->paddr;
+}
+
+static int pil_init_mmap(struct pil_desc *desc, const struct pil_mdt *mdt)
+{
+ struct pil_priv *priv = desc->priv;
+ const struct elf32_phdr *phdr;
+ struct pil_seg *seg;
+ int i, ret;
+
+ ret = pil_setup_region(priv, mdt);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < mdt->hdr.e_phnum; i++) {
+ phdr = &mdt->phdr[i];
+ if (!segment_is_loadable(phdr))
+ continue;
+
+ seg = pil_init_seg(desc, phdr, i);
+ if (IS_ERR(seg))
+ return PTR_ERR(seg);
+
+ list_add_tail(&seg->list, &priv->segs);
+ }
+ list_sort(NULL, &priv->segs, pil_cmp_seg);
+
+ return pil_init_entry_addr(priv, mdt);
+}
+
+static void pil_release_mmap(struct pil_desc *desc)
+{
+ struct pil_priv *priv = desc->priv;
+ struct pil_seg *p, *tmp;
+
+ if (priv->region)
+ ion_free(ion, priv->region);
+ list_for_each_entry_safe(p, tmp, &priv->segs, list) {
+ list_del(&p->list);
+ kfree(p);
+ }
}
#define IOMAP_SIZE SZ_4M
-static int load_segment(const struct elf32_phdr *phdr, unsigned num,
- struct pil_device *pil)
+static int pil_load_seg(struct pil_desc *desc, struct pil_seg *seg)
{
int ret = 0, count, paddr;
char fw_name[30];
const struct firmware *fw = NULL;
const u8 *data;
+ int num = seg->num;
- if (memblock_overlaps_memory(phdr->p_paddr, phdr->p_memsz)) {
- dev_err(&pil->dev, "%s: kernel memory would be overwritten "
- "[%#08lx, %#08lx)\n", pil->desc->name,
- (unsigned long)phdr->p_paddr,
- (unsigned long)(phdr->p_paddr + phdr->p_memsz));
- return -EPERM;
- }
-
- if (phdr->p_filesz) {
+ if (seg->filesz) {
snprintf(fw_name, ARRAY_SIZE(fw_name), "%s.b%02d",
- pil->desc->name, num);
- ret = request_firmware(&fw, fw_name, &pil->dev);
+ desc->name, num);
+ ret = request_firmware(&fw, fw_name, desc->dev);
if (ret) {
- dev_err(&pil->dev, "%s: Failed to locate blob %s\n",
- pil->desc->name, fw_name);
+ pil_err(desc, "Failed to locate blob %s\n", fw_name);
return ret;
}
- if (fw->size != phdr->p_filesz) {
- dev_err(&pil->dev, "%s: Blob size %u doesn't match "
- "%u\n", pil->desc->name, fw->size,
- phdr->p_filesz);
+ if (fw->size != seg->filesz) {
+ pil_err(desc, "Blob size %u doesn't match %lu\n",
+ fw->size, seg->filesz);
ret = -EPERM;
goto release_fw;
}
}
/* Load the segment into memory */
- count = phdr->p_filesz;
- paddr = phdr->p_paddr;
+ count = seg->filesz;
+ paddr = seg->paddr;
data = fw ? fw->data : NULL;
while (count > 0) {
int size;
@@ -191,8 +426,7 @@
size = min_t(size_t, IOMAP_SIZE, count);
buf = ioremap(paddr, size);
if (!buf) {
- dev_err(&pil->dev, "%s: Failed to map memory\n",
- pil->desc->name);
+ pil_err(desc, "Failed to map memory\n");
ret = -ENOMEM;
goto release_fw;
}
@@ -205,7 +439,7 @@
}
/* Zero out trailing memory */
- count = phdr->p_memsz - phdr->p_filesz;
+ count = seg->sz - seg->filesz;
while (count > 0) {
int size;
u8 __iomem *buf;
@@ -213,8 +447,7 @@
size = min_t(size_t, IOMAP_SIZE, count);
buf = ioremap(paddr, size);
if (!buf) {
- dev_err(&pil->dev, "%s: Failed to map memory\n",
- pil->desc->name);
+ pil_err(desc, "Failed to map memory\n");
ret = -ENOMEM;
goto release_fw;
}
@@ -225,12 +458,10 @@
paddr += size;
}
- if (pil->desc->ops->verify_blob) {
- ret = pil->desc->ops->verify_blob(pil->desc, phdr->p_paddr,
- phdr->p_memsz);
+ if (desc->ops->verify_blob) {
+ ret = desc->ops->verify_blob(desc, seg->paddr, seg->sz);
if (ret)
- dev_err(&pil->dev, "%s: Blob%u failed verification\n",
- pil->desc->name, num);
+ pil_err(desc, "Blob%u failed verification\n", num);
}
release_fw:
@@ -238,423 +469,180 @@
return ret;
}
-#define segment_is_hash(flag) (((flag) & (0x7 << 24)) == (0x2 << 24))
-
-static int segment_is_loadable(const struct elf32_phdr *p)
-{
- return (p->p_type == PT_LOAD) && !segment_is_hash(p->p_flags);
-}
-
-/* Sychronize request_firmware() with suspend */
+/* Synchronize request_firmware() with suspend */
static DECLARE_RWSEM(pil_pm_rwsem);
-static int load_image(struct pil_device *pil)
+/**
+ * pil_boot() - Load a peripheral image into memory and boot it
+ * @desc: descriptor from pil_desc_init()
+ *
+ * Returns 0 on success or -ERROR on failure.
+ */
+int pil_boot(struct pil_desc *desc)
{
- int i, ret;
+ int ret;
char fw_name[30];
- struct elf32_hdr *ehdr;
- const struct elf32_phdr *phdr;
+ const struct pil_mdt *mdt;
+ const struct elf32_hdr *ehdr;
+ struct pil_seg *seg;
const struct firmware *fw;
- unsigned long proxy_timeout = pil->desc->proxy_timeout;
+ unsigned long proxy_timeout = desc->proxy_timeout;
+ struct pil_priv *priv = desc->priv;
+
+ /* Reinitialize for new image */
+ pil_release_mmap(desc);
down_read(&pil_pm_rwsem);
- snprintf(fw_name, sizeof(fw_name), "%s.mdt", pil->desc->name);
- ret = request_firmware(&fw, fw_name, &pil->dev);
+ snprintf(fw_name, sizeof(fw_name), "%s.mdt", desc->name);
+ ret = request_firmware(&fw, fw_name, desc->dev);
if (ret) {
- dev_err(&pil->dev, "%s: Failed to locate %s\n",
- pil->desc->name, fw_name);
+ pil_err(desc, "Failed to locate %s\n", fw_name);
goto out;
}
if (fw->size < sizeof(*ehdr)) {
- dev_err(&pil->dev, "%s: Not big enough to be an elf header\n",
- pil->desc->name);
+ pil_err(desc, "Not big enough to be an elf header\n");
ret = -EIO;
goto release_fw;
}
- ehdr = (struct elf32_hdr *)fw->data;
+ mdt = (const struct pil_mdt *)fw->data;
+ ehdr = &mdt->hdr;
+
if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
- dev_err(&pil->dev, "%s: Not an elf header\n", pil->desc->name);
+ pil_err(desc, "Not an elf header\n");
ret = -EIO;
goto release_fw;
}
if (ehdr->e_phnum == 0) {
- dev_err(&pil->dev, "%s: No loadable segments\n",
- pil->desc->name);
+ pil_err(desc, "No loadable segments\n");
ret = -EIO;
goto release_fw;
}
if (sizeof(struct elf32_phdr) * ehdr->e_phnum +
sizeof(struct elf32_hdr) > fw->size) {
- dev_err(&pil->dev, "%s: Program headers not within mdt\n",
- pil->desc->name);
+ pil_err(desc, "Program headers not within mdt\n");
ret = -EIO;
goto release_fw;
}
- ret = pil->desc->ops->init_image(pil->desc, fw->data, fw->size);
+ ret = pil_init_mmap(desc, mdt);
+ if (ret)
+ goto release_fw;
+
+ if (desc->ops->init_image)
+ ret = desc->ops->init_image(desc, fw->data, fw->size);
if (ret) {
- dev_err(&pil->dev, "%s: Invalid firmware metadata\n",
- pil->desc->name);
+ pil_err(desc, "Invalid firmware metadata\n");
goto release_fw;
}
- phdr = (const struct elf32_phdr *)(fw->data + sizeof(struct elf32_hdr));
- for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
- if (!segment_is_loadable(phdr))
- continue;
+ if (desc->ops->mem_setup)
+ ret = desc->ops->mem_setup(desc, priv->region_start,
+ priv->region_end - priv->region_start);
+ if (ret) {
+ pil_err(desc, "Memory setup error\n");
+ goto release_fw;
+ }
- ret = load_segment(phdr, i, pil);
- if (ret) {
- dev_err(&pil->dev, "%s: Failed to load segment %d\n",
- pil->desc->name, i);
+ list_for_each_entry(seg, &desc->priv->segs, list) {
+ ret = pil_load_seg(desc, seg);
+ if (ret)
goto release_fw;
- }
}
- ret = pil_proxy_vote(pil);
+ ret = pil_proxy_vote(desc);
if (ret) {
- dev_err(&pil->dev, "%s: Failed to proxy vote\n",
- pil->desc->name);
+ pil_err(desc, "Failed to proxy vote\n");
goto release_fw;
}
- ret = pil->desc->ops->auth_and_reset(pil->desc);
+ ret = desc->ops->auth_and_reset(desc);
if (ret) {
- dev_err(&pil->dev, "%s: Failed to bring out of reset\n",
- pil->desc->name);
+ pil_err(desc, "Failed to bring out of reset\n");
proxy_timeout = 0; /* Remove proxy vote immediately on error */
goto err_boot;
}
- dev_info(&pil->dev, "%s: Brought out of reset\n", pil->desc->name);
+ pil_info(desc, "Brought out of reset\n");
err_boot:
- pil_proxy_unvote(pil, proxy_timeout);
+ pil_proxy_unvote(desc, proxy_timeout);
release_fw:
release_firmware(fw);
out:
up_read(&pil_pm_rwsem);
+ if (ret)
+ pil_release_mmap(desc);
return ret;
}
-
-static void pil_set_state(struct pil_device *pil, enum pil_state state)
-{
- if (pil->state != state) {
- pil->state = state;
- sysfs_notify(&pil->dev.kobj, NULL, "state");
- }
-}
+EXPORT_SYMBOL(pil_boot);
/**
- * pil_get() - Load a peripheral into memory and take it out of reset
- * @name: pointer to a string containing the name of the peripheral to load
- *
- * This function returns a pointer if it succeeds. If an error occurs an
- * ERR_PTR is returned.
- *
- * If PIL is not enabled in the kernel, the value %NULL will be returned.
+ * pil_shutdown() - Shutdown a peripheral
+ * @desc: descriptor from pil_desc_init()
*/
-void *pil_get(const char *name)
+void pil_shutdown(struct pil_desc *desc)
{
- int ret;
- struct pil_device *pil;
- struct pil_device *pil_d;
- void *retval;
-
- if (!name)
- return NULL;
-
- pil = retval = find_peripheral(name);
- if (!pil)
- return ERR_PTR(-ENODEV);
- if (!try_module_get(pil->owner)) {
- put_device(&pil->dev);
- return ERR_PTR(-ENODEV);
- }
-
- pil_d = pil_get(pil->desc->depends_on);
- if (IS_ERR(pil_d)) {
- retval = pil_d;
- goto err_depends;
- }
-
- mutex_lock(&pil->lock);
- if (!pil->count) {
- ret = load_image(pil);
- if (ret) {
- retval = ERR_PTR(ret);
- goto err_load;
- }
- }
- pil->count++;
- pil_set_state(pil, PIL_ONLINE);
- mutex_unlock(&pil->lock);
-out:
- return retval;
-err_load:
- mutex_unlock(&pil->lock);
- pil_put(pil_d);
-err_depends:
- put_device(&pil->dev);
- module_put(pil->owner);
- goto out;
-}
-EXPORT_SYMBOL(pil_get);
-
-static void pil_shutdown(struct pil_device *pil)
-{
- pil->desc->ops->shutdown(pil->desc);
- if (proxy_timeout_ms == 0 && pil->desc->ops->proxy_unvote)
- pil->desc->ops->proxy_unvote(pil->desc);
+ struct pil_priv *priv = desc->priv;
+ desc->ops->shutdown(desc);
+ if (proxy_timeout_ms == 0 && desc->ops->proxy_unvote)
+ desc->ops->proxy_unvote(desc);
else
- flush_delayed_work(&pil->proxy);
-
- pil_set_state(pil, PIL_OFFLINE);
+ flush_delayed_work(&priv->proxy);
}
+EXPORT_SYMBOL(pil_shutdown);
/**
- * pil_put() - Inform PIL the peripheral no longer needs to be active
- * @peripheral_handle: pointer from a previous call to pil_get()
+ * pil_desc_init() - Initialize a pil descriptor
+ * @desc: descriptor to intialize
*
- * This doesn't imply that a peripheral is shutdown or in reset since another
- * driver could be using the peripheral.
+ * Initialize a pil descriptor for use by other pil functions. This function
+ * must be called before calling pil_boot() or pil_shutdown().
+ *
+ * Returns 0 for success and -ERROR on failure.
*/
-void pil_put(void *peripheral_handle)
+int pil_desc_init(struct pil_desc *desc)
{
- struct pil_device *pil_d, *pil = peripheral_handle;
-
- if (IS_ERR_OR_NULL(pil))
- return;
-
- mutex_lock(&pil->lock);
- if (WARN(!pil->count, "%s: %s: Reference count mismatch\n",
- pil->desc->name, __func__))
- goto err_out;
- if (!--pil->count)
- pil_shutdown(pil);
- mutex_unlock(&pil->lock);
-
- pil_d = find_peripheral(pil->desc->depends_on);
- module_put(pil->owner);
- if (pil_d) {
- pil_put(pil_d);
- put_device(&pil_d->dev);
- }
- put_device(&pil->dev);
- return;
-err_out:
- mutex_unlock(&pil->lock);
- return;
-}
-EXPORT_SYMBOL(pil_put);
-
-void pil_force_shutdown(const char *name)
-{
- struct pil_device *pil;
-
- pil = find_peripheral(name);
- if (!pil) {
- pr_err("%s: Couldn't find %s\n", __func__, name);
- return;
- }
-
- mutex_lock(&pil->lock);
- if (!WARN(!pil->count, "%s: %s: Reference count mismatch\n",
- pil->desc->name, __func__))
- pil_shutdown(pil);
- mutex_unlock(&pil->lock);
-
- put_device(&pil->dev);
-}
-EXPORT_SYMBOL(pil_force_shutdown);
-
-int pil_force_boot(const char *name)
-{
- int ret = -EINVAL;
- struct pil_device *pil;
-
- pil = find_peripheral(name);
- if (!pil) {
- pr_err("%s: Couldn't find %s\n", __func__, name);
- return -EINVAL;
- }
-
- mutex_lock(&pil->lock);
- if (!WARN(!pil->count, "%s: %s: Reference count mismatch\n",
- pil->desc->name, __func__))
- ret = load_image(pil);
- if (!ret)
- pil_set_state(pil, PIL_ONLINE);
- mutex_unlock(&pil->lock);
- put_device(&pil->dev);
-
- return ret;
-}
-EXPORT_SYMBOL(pil_force_boot);
-
-#ifdef CONFIG_DEBUG_FS
-static int msm_pil_debugfs_open(struct inode *inode, struct file *filp)
-{
- filp->private_data = inode->i_private;
- return 0;
-}
-
-static ssize_t msm_pil_debugfs_read(struct file *filp, char __user *ubuf,
- size_t cnt, loff_t *ppos)
-{
- int r;
- char buf[40];
- struct pil_device *pil = filp->private_data;
-
- mutex_lock(&pil->lock);
- r = snprintf(buf, sizeof(buf), "%d\n", pil->count);
- mutex_unlock(&pil->lock);
- return simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
-}
-
-static ssize_t msm_pil_debugfs_write(struct file *filp,
- const char __user *ubuf, size_t cnt, loff_t *ppos)
-{
- struct pil_device *pil = filp->private_data;
- char buf[4];
-
- if (cnt > sizeof(buf))
- return -EINVAL;
-
- if (copy_from_user(&buf, ubuf, cnt))
- return -EFAULT;
-
- if (!strncmp(buf, "get", 3)) {
- if (IS_ERR(pil_get(pil->desc->name)))
- return -EIO;
- } else if (!strncmp(buf, "put", 3))
- pil_put(pil);
- else
- return -EINVAL;
-
- return cnt;
-}
-
-static const struct file_operations msm_pil_debugfs_fops = {
- .open = msm_pil_debugfs_open,
- .read = msm_pil_debugfs_read,
- .write = msm_pil_debugfs_write,
-};
-
-static struct dentry *pil_base_dir;
-
-static int __init msm_pil_debugfs_init(void)
-{
- pil_base_dir = debugfs_create_dir("pil", NULL);
- if (!pil_base_dir) {
- pil_base_dir = NULL;
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static void __exit msm_pil_debugfs_exit(void)
-{
- debugfs_remove_recursive(pil_base_dir);
-}
-
-static int msm_pil_debugfs_add(struct pil_device *pil)
-{
- if (!pil_base_dir)
- return -ENOMEM;
-
- pil->dentry = debugfs_create_file(pil->desc->name, S_IRUGO | S_IWUSR,
- pil_base_dir, pil, &msm_pil_debugfs_fops);
- return !pil->dentry ? -ENOMEM : 0;
-}
-
-static void msm_pil_debugfs_remove(struct pil_device *pil)
-{
- debugfs_remove(pil->dentry);
-}
-#else
-static int __init msm_pil_debugfs_init(void) { return 0; };
-static void __exit msm_pil_debugfs_exit(void) { return 0; };
-static int msm_pil_debugfs_add(struct pil_device *pil) { return 0; }
-static void msm_pil_debugfs_remove(struct pil_device *pil) { }
-#endif
-
-static void pil_device_release(struct device *dev)
-{
- struct pil_device *pil = to_pil_device(dev);
- wake_lock_destroy(&pil->wlock);
- mutex_destroy(&pil->lock);
- kfree(pil);
-}
-
-struct pil_device *msm_pil_register(struct pil_desc *desc)
-{
- int err;
- static atomic_t pil_count = ATOMIC_INIT(-1);
- struct pil_device *pil;
+ struct pil_priv *priv;
/* Ignore users who don't make any sense */
+ WARN(desc->ops->proxy_unvote && !desc->proxy_timeout,
+ "A proxy timeout of 0 was specified.\n");
if (WARN(desc->ops->proxy_unvote && !desc->ops->proxy_vote,
- "invalid proxy voting. ignoring\n"))
+ "Invalid proxy voting. Ignoring\n"))
((struct pil_reset_ops *)desc->ops)->proxy_unvote = NULL;
- WARN(desc->ops->proxy_unvote && !desc->proxy_timeout,
- "A proxy timeout of 0 ms was specified for %s. Specify one in "
- "desc->proxy_timeout.\n", desc->name);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ desc->priv = priv;
+ priv->desc = desc;
- pil = kzalloc(sizeof(*pil), GFP_KERNEL);
- if (!pil)
- return ERR_PTR(-ENOMEM);
+ snprintf(priv->wname, sizeof(priv->wname), "pil-%s", desc->name);
+ wake_lock_init(&priv->wlock, WAKE_LOCK_SUSPEND, priv->wname);
+ INIT_DELAYED_WORK(&priv->proxy, pil_proxy_work);
+ INIT_LIST_HEAD(&priv->segs);
- mutex_init(&pil->lock);
- pil->desc = desc;
- pil->owner = desc->owner;
- pil->dev.parent = desc->dev;
- pil->dev.bus = &pil_bus_type;
- pil->dev.release = pil_device_release;
-
- snprintf(pil->wake_name, sizeof(pil->wake_name), "pil-%s", desc->name);
- wake_lock_init(&pil->wlock, WAKE_LOCK_SUSPEND, pil->wake_name);
- INIT_DELAYED_WORK(&pil->proxy, pil_proxy_work);
-
- dev_set_name(&pil->dev, "pil%d", atomic_inc_return(&pil_count));
- err = device_register(&pil->dev);
- if (err) {
- put_device(&pil->dev);
- wake_lock_destroy(&pil->wlock);
- mutex_destroy(&pil->lock);
- kfree(pil);
- return ERR_PTR(err);
- }
-
- err = msm_pil_debugfs_add(pil);
- if (err) {
- device_unregister(&pil->dev);
- return ERR_PTR(err);
- }
-
- return pil;
+ return 0;
}
-EXPORT_SYMBOL(msm_pil_register);
+EXPORT_SYMBOL(pil_desc_init);
-void msm_pil_unregister(struct pil_device *pil)
+/**
+ * pil_desc_release() - Release a pil descriptor
+ * @desc: descriptor to free
+ */
+void pil_desc_release(struct pil_desc *desc)
{
- if (IS_ERR_OR_NULL(pil))
- return;
+ struct pil_priv *priv = desc->priv;
- if (get_device(&pil->dev)) {
- mutex_lock(&pil->lock);
- WARN_ON(pil->count);
- flush_delayed_work_sync(&pil->proxy);
- msm_pil_debugfs_remove(pil);
- device_unregister(&pil->dev);
- mutex_unlock(&pil->lock);
- put_device(&pil->dev);
+ if (priv) {
+ flush_delayed_work(&priv->proxy);
+ wake_lock_destroy(&priv->wlock);
}
+ desc->priv = NULL;
+ kfree(priv);
}
-EXPORT_SYMBOL(msm_pil_unregister);
+EXPORT_SYMBOL(pil_desc_release);
static int pil_pm_notify(struct notifier_block *b, unsigned long event, void *p)
{
@@ -675,19 +663,18 @@
static int __init msm_pil_init(void)
{
- int ret = msm_pil_debugfs_init();
- if (ret)
- return ret;
- register_pm_notifier(&pil_pm_notifier);
- return bus_register(&pil_bus_type);
+ ion = msm_ion_client_create(UINT_MAX, "pil");
+ if (IS_ERR(ion)) /* Can't support relocatable images */
+ ion = NULL;
+ return register_pm_notifier(&pil_pm_notifier);
}
-subsys_initcall(msm_pil_init);
+device_initcall(msm_pil_init);
static void __exit msm_pil_exit(void)
{
- bus_unregister(&pil_bus_type);
unregister_pm_notifier(&pil_pm_notifier);
- msm_pil_debugfs_exit();
+ if (ion)
+ ion_client_destroy(ion);
}
module_exit(msm_pil_exit);
diff --git a/arch/arm/mach-msm/peripheral-loader.h b/arch/arm/mach-msm/peripheral-loader.h
index 405b73f..1c2faf7 100644
--- a/arch/arm/mach-msm/peripheral-loader.h
+++ b/arch/arm/mach-msm/peripheral-loader.h
@@ -14,28 +14,33 @@
struct device;
struct module;
+struct pil_priv;
/**
* struct pil_desc - PIL descriptor
* @name: string used for pil_get()
- * @depends_on: booted before this peripheral
* @dev: parent device
* @ops: callback functions
* @owner: module the descriptor belongs to
* @proxy_timeout: delay in ms until proxy vote is removed
+ * @flags: bitfield for image flags
+ * @priv: DON'T USE - internal only
*/
struct pil_desc {
const char *name;
- const char *depends_on;
struct device *dev;
const struct pil_reset_ops *ops;
struct module *owner;
unsigned long proxy_timeout;
+ unsigned long flags;
+#define PIL_SKIP_ENTRY_CHECK BIT(0)
+ struct pil_priv *priv;
};
/**
* struct pil_reset_ops - PIL operations
* @init_image: prepare an image for authentication
+ * @mem_setup: prepare the image memory region
* @verify_blob: authenticate a program segment, called once for each loadable
* program segment (optional)
* @proxy_vote: make proxy votes before auth_and_reset (optional)
@@ -46,6 +51,7 @@
struct pil_reset_ops {
int (*init_image)(struct pil_desc *pil, const u8 *metadata,
size_t size);
+ int (*mem_setup)(struct pil_desc *pil, phys_addr_t addr, size_t size);
int (*verify_blob)(struct pil_desc *pil, u32 phy_addr, size_t size);
int (*proxy_vote)(struct pil_desc *pil);
int (*auth_and_reset)(struct pil_desc *pil);
@@ -53,17 +59,21 @@
int (*shutdown)(struct pil_desc *pil);
};
-struct pil_device;
-
#ifdef CONFIG_MSM_PIL
-extern struct pil_device *msm_pil_register(struct pil_desc *desc);
-extern void msm_pil_unregister(struct pil_device *pil);
+extern int pil_desc_init(struct pil_desc *desc);
+extern int pil_boot(struct pil_desc *desc);
+extern void pil_shutdown(struct pil_desc *desc);
+extern void pil_desc_release(struct pil_desc *desc);
+extern phys_addr_t pil_get_entry_addr(struct pil_desc *desc);
#else
-static inline struct pil_device *msm_pil_register(struct pil_desc *desc)
+static inline int pil_desc_init(struct pil_desc *desc) { return 0; }
+static inline int pil_boot(struct pil_desc *desc) { return 0; }
+static inline void pil_shutdown(struct pil_desc *desc) { }
+static inline void pil_desc_release(struct pil_desc *desc) { }
+static inline phys_addr_t pil_get_entry_addr(struct pil_desc *desc)
{
- return NULL;
+ return 0;
}
-static inline void msm_pil_unregister(struct pil_device *pil) { }
#endif
#endif
diff --git a/arch/arm/mach-msm/pil-dsps.c b/arch/arm/mach-msm/pil-dsps.c
index c074086..519e1c9 100644
--- a/arch/arm/mach-msm/pil-dsps.c
+++ b/arch/arm/mach-msm/pil-dsps.c
@@ -13,34 +13,31 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/elf.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <linux/interrupt.h>
-#include <mach/msm_iomap.h>
#include <mach/subsystem_restart.h>
#include <mach/msm_smsm.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
#include "ramdump.h"
-#define PPSS_RESET (MSM_CLK_CTL_BASE + 0x2594)
+#define PPSS_RESET 0x2594
#define PPSS_RESET_PROC_RESET 0x2
#define PPSS_RESET_RESET 0x1
-#define PPSS_PROC_CLK_CTL (MSM_CLK_CTL_BASE + 0x2588)
+#define PPSS_PROC_CLK_CTL 0x2588
#define CLK_BRANCH_ENA 0x10
-#define PPSS_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2580)
-#define CLK_HALT_DFAB_STATE (MSM_CLK_CTL_BASE + 0x2FC8)
+#define PPSS_HCLK_CTL 0x2580
+#define CLK_HALT_DFAB_STATE 0x2FC8
#define PPSS_WDOG_UNMASKED_INT_EN 0x1808
struct dsps_data {
- struct pil_device *pil;
+ void __iomem *base;
struct pil_desc desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
@@ -58,33 +55,41 @@
};
#define desc_to_drv(d) container_of(d, struct dsps_data, subsys_desc)
+#define pil_to_drv(d) container_of(d, struct dsps_data, desc)
static int init_image_dsps(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
+ struct dsps_data *drv = pil_to_drv(pil);
+
/* Bring memory and bus interface out of reset */
- writel_relaxed(PPSS_RESET_PROC_RESET, PPSS_RESET);
- writel_relaxed(CLK_BRANCH_ENA, PPSS_HCLK_CTL);
+ writel_relaxed(PPSS_RESET_PROC_RESET, drv->base + PPSS_RESET);
+ writel_relaxed(CLK_BRANCH_ENA, drv->base + PPSS_HCLK_CTL);
mb();
return 0;
}
static int reset_dsps(struct pil_desc *pil)
{
- writel_relaxed(CLK_BRANCH_ENA, PPSS_PROC_CLK_CTL);
- while (readl_relaxed(CLK_HALT_DFAB_STATE) & BIT(18))
+ struct dsps_data *drv = pil_to_drv(pil);
+
+ writel_relaxed(CLK_BRANCH_ENA, drv->base + PPSS_PROC_CLK_CTL);
+ while (readl_relaxed(drv->base + CLK_HALT_DFAB_STATE) & BIT(18))
cpu_relax();
/* Bring DSPS out of reset */
- writel_relaxed(0x0, PPSS_RESET);
+ writel_relaxed(0x0, drv->base + PPSS_RESET);
return 0;
}
static int shutdown_dsps(struct pil_desc *pil)
{
- writel_relaxed(PPSS_RESET_PROC_RESET | PPSS_RESET_RESET, PPSS_RESET);
+ struct dsps_data *drv = pil_to_drv(pil);
+
+ writel_relaxed(PPSS_RESET_PROC_RESET | PPSS_RESET_RESET,
+ drv->base + PPSS_RESET);
usleep_range(1000, 2000);
- writel_relaxed(PPSS_RESET_PROC_RESET, PPSS_RESET);
- writel_relaxed(0x0, PPSS_PROC_CLK_CTL);
+ writel_relaxed(PPSS_RESET_PROC_RESET, drv->base + PPSS_RESET);
+ writel_relaxed(0x0, drv->base + PPSS_PROC_CLK_CTL);
return 0;
}
@@ -165,19 +170,15 @@
static int dsps_start(const struct subsys_desc *desc)
{
- void *ret;
struct dsps_data *drv = desc_to_drv(desc);
- ret = pil_get(drv->desc.name);
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->desc);
}
static void dsps_stop(const struct subsys_desc *desc)
{
struct dsps_data *drv = desc_to_drv(desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->desc);
}
static int dsps_shutdown(const struct subsys_desc *desc)
@@ -188,7 +189,7 @@
writel_relaxed(0, drv->ppss_base + PPSS_WDOG_UNMASKED_INT_EN);
mb(); /* Make sure wdog is disabled before shutting down */
}
- pil_force_shutdown(drv->desc.name);
+ pil_shutdown(&drv->desc);
return 0;
}
@@ -196,7 +197,7 @@
{
struct dsps_data *drv = desc_to_drv(desc);
- pil_force_boot(drv->desc.name);
+ pil_boot(&drv->desc);
atomic_set(&drv->crash_in_progress, 0);
enable_irq(drv->wdog_irq);
@@ -253,8 +254,8 @@
{
struct dsps_data *drv;
struct pil_desc *desc;
- int ret;
struct resource *res;
+ int ret;
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
@@ -262,6 +263,13 @@
platform_set_drvdata(pdev, drv);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+ drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!drv->base)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (res) {
drv->ppss_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
@@ -273,6 +281,7 @@
desc->name = pdev->dev.platform_data;
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
+ desc->flags = PIL_SKIP_ENTRY_CHECK;
if (pas_supported(PAS_DSPS) > 0) {
desc->ops = &pil_dsps_ops_trusted;
dev_info(&pdev->dev, "using secure boot\n");
@@ -280,9 +289,9 @@
desc->ops = &pil_dsps_ops;
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
drv->fw_ramdump_segments[0].address = 0x12000000;
drv->fw_ramdump_segments[0].size = 0x28000;
@@ -292,7 +301,7 @@
drv->fw_ramdump_segments[2].size = 0x4000;
drv->fw_ramdump_segments[3].address = 0x8fe00000;
drv->fw_ramdump_segments[3].size = 0x100000;
- drv->ramdump_dev = create_ramdump_device("dsps");
+ drv->ramdump_dev = create_ramdump_device("dsps", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -300,7 +309,7 @@
drv->smem_ramdump_segments[0].address = PHYS_OFFSET - SZ_2M;
drv->smem_ramdump_segments[0].size = SZ_2M;
- drv->smem_ramdump_dev = create_ramdump_device("smem-dsps");
+ drv->smem_ramdump_dev = create_ramdump_device("smem-dsps", &pdev->dev);
if (!drv->smem_ramdump_dev) {
ret = -ENOMEM;
goto err_smem_ramdump;
@@ -350,7 +359,7 @@
err_smem_ramdump:
destroy_ramdump_device(drv->ramdump_dev);
err_ramdump:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -362,7 +371,7 @@
subsys_unregister(drv->subsys);
destroy_ramdump_device(drv->smem_ramdump_dev);
destroy_ramdump_device(drv->ramdump_dev);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-gss.c b/arch/arm/mach-msm/pil-gss.c
index 0c8f4e3..a6d13d0 100644
--- a/arch/arm/mach-msm/pil-gss.c
+++ b/arch/arm/mach-msm/pil-gss.c
@@ -14,7 +14,6 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -25,13 +24,11 @@
#include <linux/reboot.h>
#include <linux/interrupt.h>
-#include <mach/msm_iomap.h>
#include <mach/msm_xo.h>
#include <mach/socinfo.h>
#include <mach/msm_bus_board.h>
#include <mach/msm_bus.h>
#include <mach/subsystem_restart.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
@@ -46,13 +43,13 @@
#define GSS_CSR_POWER_UP_DOWN 0x18
#define GSS_CSR_CFG_HID 0x2C
-#define GSS_SLP_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C60)
-#define GSS_RESET (MSM_CLK_CTL_BASE + 0x2C64)
-#define GSS_CLAMP_ENA (MSM_CLK_CTL_BASE + 0x2C68)
-#define GSS_CXO_SRC_CTL (MSM_CLK_CTL_BASE + 0x2C74)
+#define GSS_SLP_CLK_CTL 0x2C60
+#define GSS_RESET 0x2C64
+#define GSS_CLAMP_ENA 0x2C68
+#define GSS_CXO_SRC_CTL 0x2C74
-#define PLL5_STATUS (MSM_CLK_CTL_BASE + 0x30F8)
-#define PLL_ENA_GSS (MSM_CLK_CTL_BASE + 0x3480)
+#define PLL5_STATUS 0x30F8
+#define PLL_ENA_GSS 0x3480
#define PLL5_VOTE BIT(5)
#define PLL_STATUS BIT(16)
@@ -67,9 +64,9 @@
struct gss_data {
void __iomem *base;
void __iomem *qgic2_base;
- unsigned long start_addr;
+ void __iomem *cbase;
struct clk *xo;
- struct pil_device *pil;
+ struct pil_desc pil_desc;
struct miscdevice misc_dev;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
@@ -80,15 +77,6 @@
struct ramdump_device *smem_ramdump_dev;
};
-static int pil_gss_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct gss_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-
static int make_gss_proxy_votes(struct pil_desc *pil)
{
int ret;
@@ -111,14 +99,15 @@
static void gss_init(struct gss_data *drv)
{
void __iomem *base = drv->base;
+ void __iomem *cbase = drv->cbase;
/* Supply clocks to GSS. */
- writel_relaxed(XO_CLK_BRANCH_ENA, GSS_CXO_SRC_CTL);
- writel_relaxed(SLP_CLK_BRANCH_ENA, GSS_SLP_CLK_CTL);
+ writel_relaxed(XO_CLK_BRANCH_ENA, cbase + GSS_CXO_SRC_CTL);
+ writel_relaxed(SLP_CLK_BRANCH_ENA, cbase + GSS_SLP_CLK_CTL);
/* Deassert GSS reset and clamps. */
- writel_relaxed(0x0, GSS_RESET);
- writel_relaxed(0x0, GSS_CLAMP_ENA);
+ writel_relaxed(0x0, cbase + GSS_RESET);
+ writel_relaxed(0x0, cbase + GSS_CLAMP_ENA);
mb();
/*
@@ -159,6 +148,7 @@
{
struct gss_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
+ void __iomem *cbase = drv->cbase;
u32 regval;
int ret;
@@ -175,8 +165,8 @@
* Vote PLL on in GSS's voting register and wait for it to enable.
* The PLL must be enable to switch the GFMUX to a low-power source.
*/
- writel_relaxed(PLL5_VOTE, PLL_ENA_GSS);
- while ((readl_relaxed(PLL5_STATUS) & PLL_STATUS) == 0)
+ writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS);
+ while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0)
cpu_relax();
/* Perform one-time GSS initialization. */
@@ -201,7 +191,7 @@
writel_relaxed(0x1F, base + GSS_CSR_CLK_ENABLE);
/* Clear GSS PLL votes. */
- writel_relaxed(0, PLL_ENA_GSS);
+ writel_relaxed(0, cbase + PLL_ENA_GSS);
mb();
clk_disable_unprepare(drv->xo);
@@ -213,7 +203,8 @@
{
struct gss_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
- unsigned long start_addr = drv->start_addr;
+ unsigned long start_addr = pil_get_entry_addr(pil);
+ void __iomem *cbase = drv->cbase;
int ret;
/* Unhalt bus port. */
@@ -224,8 +215,8 @@
}
/* Vote PLL on in GSS's voting register and wait for it to enable. */
- writel_relaxed(PLL5_VOTE, PLL_ENA_GSS);
- while ((readl_relaxed(PLL5_STATUS) & PLL_STATUS) == 0)
+ writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS);
+ while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0)
cpu_relax();
/* Perform GSS initialization. */
@@ -258,7 +249,6 @@
}
static struct pil_reset_ops pil_gss_ops = {
- .init_image = pil_gss_init_image,
.auth_and_reset = pil_gss_reset,
.shutdown = pil_gss_shutdown,
.proxy_vote = make_gss_proxy_votes,
@@ -373,14 +363,10 @@
static int gss_start(const struct subsys_desc *desc)
{
- void *ret;
struct gss_data *drv;
drv = container_of(desc, struct gss_data, subsys_desc);
- ret = pil_get("gss");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->pil_desc);
}
static void gss_stop(const struct subsys_desc *desc)
@@ -388,14 +374,14 @@
struct gss_data *drv;
drv = container_of(desc, struct gss_data, subsys_desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int gss_shutdown(const struct subsys_desc *desc)
{
struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
- pil_force_shutdown("gss");
+ pil_shutdown(&drv->pil_desc);
disable_irq_nosync(drv->irq);
return 0;
@@ -405,7 +391,7 @@
{
struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
- pil_force_boot("gss");
+ pil_boot(&drv->pil_desc);
enable_irq(drv->irq);
return 0;
}
@@ -467,8 +453,10 @@
struct gss_data *drv = container_of(c, struct gss_data, misc_dev);
drv->subsys_handle = subsystem_get("gss");
- if (!drv->subsys_handle)
- pr_debug("%s - subsystem_get returned NULL\n", __func__);
+ if (IS_ERR(drv->subsys_handle)) {
+ pr_debug("%s - subsystem_get returned error\n", __func__);
+ return PTR_ERR(drv->subsys_handle);
+ }
return 0;
}
@@ -497,30 +485,26 @@
struct pil_desc *desc;
int ret;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
platform_set_drvdata(pdev, drv);
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->base)
return -ENOMEM;
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ drv->qgic2_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->qgic2_base)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
if (!res)
return -EINVAL;
-
- drv->qgic2_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!drv->qgic2_base)
+ drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!drv->cbase)
return -ENOMEM;
drv->xo = devm_clk_get(&pdev->dev, "xo");
@@ -531,6 +515,7 @@
if (drv->irq < 0)
return drv->irq;
+ desc = &drv->pil_desc;
desc->name = "gss";
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
@@ -543,14 +528,13 @@
desc->ops = &pil_gss_ops;
dev_info(&pdev->dev, "using non-secure boot\n");
}
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
+
/* Force into low power mode because hardware doesn't do this */
desc->ops->shutdown(desc);
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil)) {
- return PTR_ERR(drv->pil);
- }
-
ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
smsm_state_cb, drv);
if (ret < 0)
@@ -579,13 +563,13 @@
if (ret)
goto err_misc;
- drv->ramdump_dev = create_ramdump_device("gss");
+ drv->ramdump_dev = create_ramdump_device("gss", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
}
- drv->smem_ramdump_dev = create_ramdump_device("smem-gss");
+ drv->smem_ramdump_dev = create_ramdump_device("smem-gss", &pdev->dev);
if (!drv->smem_ramdump_dev) {
ret = -ENOMEM;
goto err_smem;
@@ -605,7 +589,7 @@
err_misc:
subsys_unregister(drv->subsys);
err_subsys:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -617,7 +601,7 @@
destroy_ramdump_device(drv->ramdump_dev);
misc_deregister(&drv->misc_dev);
subsys_unregister(drv->subsys);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-mba.c b/arch/arm/mach-msm/pil-mba.c
deleted file mode 100644
index daafd1d..0000000
--- a/arch/arm/mach-msm/pil-mba.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/ioport.h>
-#include <linux/elf.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/interrupt.h>
-
-#include <mach/subsystem_restart.h>
-#include <mach/msm_smsm.h>
-#include <mach/peripheral-loader.h>
-
-#include "peripheral-loader.h"
-#include "ramdump.h"
-
-#define RMB_MBA_COMMAND 0x08
-#define RMB_MBA_STATUS 0x0C
-#define RMB_PMI_META_DATA 0x10
-#define RMB_PMI_CODE_START 0x14
-#define RMB_PMI_CODE_LENGTH 0x18
-
-#define CMD_META_DATA_READY 0x1
-#define CMD_LOAD_READY 0x2
-
-#define STATUS_META_DATA_AUTH_SUCCESS 0x3
-#define STATUS_AUTH_COMPLETE 0x4
-
-#define PROXY_TIMEOUT_MS 10000
-#define POLL_INTERVAL_US 50
-
-#define MAX_SSR_REASON_LEN 81U
-
-static int modem_auth_timeout_ms = 10000;
-module_param(modem_auth_timeout_ms, int, S_IRUGO | S_IWUSR);
-
-struct mba_data {
- void __iomem *reg_base;
- void __iomem *metadata_base;
- unsigned long metadata_phys;
- struct pil_device *pil;
- struct pil_desc desc;
- struct subsys_device *subsys;
- struct subsys_desc subsys_desc;
- struct clk *xo;
- void *ramdump_dev;
- void *smem_ramdump_dev;
- bool crash_shutdown;
- bool ignore_errors;
- u32 img_length;
-};
-
-static int pil_mba_make_proxy_votes(struct pil_desc *pil)
-{
- int ret;
- struct mba_data *drv = dev_get_drvdata(pil->dev);
-
- ret = clk_prepare_enable(drv->xo);
- if (ret) {
- dev_err(pil->dev, "Failed to enable XO\n");
- return ret;
- }
- return 0;
-}
-
-static void pil_mba_remove_proxy_votes(struct pil_desc *pil)
-{
- struct mba_data *drv = dev_get_drvdata(pil->dev);
- clk_disable_unprepare(drv->xo);
-}
-
-static int pil_mba_init_image(struct pil_desc *pil,
- const u8 *metadata, size_t size)
-{
- struct mba_data *drv = dev_get_drvdata(pil->dev);
- s32 status;
- int ret;
-
- /* Copy metadata to assigned shared buffer location */
- memcpy(drv->metadata_base, metadata, size);
-
- /* Initialize length counter to 0 */
- writel_relaxed(0, drv->reg_base + RMB_PMI_CODE_LENGTH);
- drv->img_length = 0;
-
- /* Pass address of meta-data to the MBA and perform authentication */
- writel_relaxed(drv->metadata_phys, drv->reg_base + RMB_PMI_META_DATA);
- writel_relaxed(CMD_META_DATA_READY, drv->reg_base + RMB_MBA_COMMAND);
- ret = readl_poll_timeout(drv->reg_base + RMB_MBA_STATUS, status,
- status == STATUS_META_DATA_AUTH_SUCCESS || status < 0,
- POLL_INTERVAL_US, modem_auth_timeout_ms * 1000);
- if (ret) {
- dev_err(pil->dev, "MBA authentication timed out\n");
- } else if (status < 0) {
- dev_err(pil->dev, "MBA returned error %d\n", status);
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-static int pil_mba_verify_blob(struct pil_desc *pil, u32 phy_addr,
- size_t size)
-{
- struct mba_data *drv = dev_get_drvdata(pil->dev);
- s32 status;
-
- /* Begin image authentication */
- if (drv->img_length == 0) {
- writel_relaxed(phy_addr, drv->reg_base + RMB_PMI_CODE_START);
- writel_relaxed(CMD_LOAD_READY, drv->reg_base + RMB_MBA_COMMAND);
- }
- /* Increment length counter */
- drv->img_length += size;
- writel_relaxed(drv->img_length, drv->reg_base + RMB_PMI_CODE_LENGTH);
-
- status = readl_relaxed(drv->reg_base + RMB_MBA_STATUS);
- if (status < 0) {
- dev_err(pil->dev, "MBA returned error %d\n", status);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int pil_mba_auth(struct pil_desc *pil)
-{
- struct mba_data *drv = dev_get_drvdata(pil->dev);
- int ret;
- s32 status;
-
- /* Wait for all segments to be authenticated or an error to occur */
- ret = readl_poll_timeout(drv->reg_base + RMB_MBA_STATUS, status,
- status == STATUS_AUTH_COMPLETE || status < 0,
- 50, modem_auth_timeout_ms * 1000);
- if (ret) {
- dev_err(pil->dev, "MBA authentication timed out\n");
- } else if (status < 0) {
- dev_err(pil->dev, "MBA returned error %d\n", status);
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-static int pil_mba_shutdown(struct pil_desc *pil)
-{
- return 0;
-}
-
-static struct pil_reset_ops pil_mba_ops = {
- .init_image = pil_mba_init_image,
- .proxy_vote = pil_mba_make_proxy_votes,
- .proxy_unvote = pil_mba_remove_proxy_votes,
- .verify_blob = pil_mba_verify_blob,
- .auth_and_reset = pil_mba_auth,
- .shutdown = pil_mba_shutdown,
-};
-
-#define subsys_to_drv(d) container_of(d, struct mba_data, subsys_desc)
-
-static void log_modem_sfr(void)
-{
- u32 size;
- char *smem_reason, reason[MAX_SSR_REASON_LEN];
-
- smem_reason = smem_get_entry(SMEM_SSR_REASON_MSS0, &size);
- if (!smem_reason || !size) {
- pr_err("modem subsystem failure reason: (unknown, smem_get_entry failed).\n");
- return;
- }
- if (!smem_reason[0]) {
- pr_err("modem subsystem failure reason: (unknown, empty string found).\n");
- return;
- }
-
- strlcpy(reason, smem_reason, min(size, sizeof(reason)));
- pr_err("modem subsystem failure reason: %s.\n", reason);
-
- smem_reason[0] = '\0';
- wmb();
-}
-
-static void restart_modem(struct mba_data *drv)
-{
- log_modem_sfr();
- drv->ignore_errors = true;
- subsystem_restart_dev(drv->subsys);
-}
-
-static void smsm_state_cb(void *data, uint32_t old_state, uint32_t new_state)
-{
- struct mba_data *drv = data;
-
- /* Ignore if we're the one that set SMSM_RESET */
- if (drv->crash_shutdown)
- return;
-
- if (new_state & SMSM_RESET) {
- pr_err("Probable fatal error on the modem.\n");
- restart_modem(drv);
- }
-}
-
-static int modem_shutdown(const struct subsys_desc *subsys)
-{
- pil_force_shutdown("modem");
- pil_force_shutdown("mba");
- return 0;
-}
-
-static int modem_powerup(const struct subsys_desc *subsys)
-{
- struct mba_data *drv = subsys_to_drv(subsys);
- /*
- * At this time, the modem is shutdown. Therefore this function cannot
- * run concurrently with either the watchdog bite error handler or the
- * SMSM callback, making it safe to unset the flag below.
- */
- drv->ignore_errors = 0;
- pil_force_boot("mba");
- pil_force_boot("modem");
- return 0;
-}
-
-static void modem_crash_shutdown(const struct subsys_desc *subsys)
-{
- struct mba_data *drv = subsys_to_drv(subsys);
- drv->crash_shutdown = true;
- smsm_reset_modem(SMSM_RESET);
-}
-
-static struct ramdump_segment modem_segments[] = {
- {0x08400000, 0x0D100000 - 0x08400000},
-};
-
-static struct ramdump_segment smem_segments[] = {
- {0x0FA00000, 0x0FC00000 - 0x0FA00000},
-};
-
-static int modem_ramdump(int enable, const struct subsys_desc *subsys)
-{
- struct mba_data *drv = subsys_to_drv(subsys);
- int ret;
-
- if (!enable)
- return 0;
-
- pil_force_boot("mba");
-
- ret = do_ramdump(drv->ramdump_dev, modem_segments,
- ARRAY_SIZE(modem_segments));
- if (ret < 0) {
- pr_err("Unable to dump modem fw memory (rc = %d).\n", ret);
- goto out;
- }
-
- ret = do_ramdump(drv->smem_ramdump_dev, smem_segments,
- ARRAY_SIZE(smem_segments));
- if (ret < 0) {
- pr_err("Unable to dump smem memory (rc = %d).\n", ret);
- goto out;
- }
-
-out:
- pil_force_shutdown("mba");
- return ret;
-}
-
-static irqreturn_t modem_wdog_bite_irq(int irq, void *dev_id)
-{
- struct mba_data *drv = dev_id;
- if (drv->ignore_errors)
- return IRQ_HANDLED;
- pr_err("Watchdog bite received from modem software!\n");
- restart_modem(drv);
- return IRQ_HANDLED;
-}
-
-static int mss_start(const struct subsys_desc *desc)
-{
- void *ret;
- struct mba_data *drv = subsys_to_drv(desc);
-
- ret = pil_get(drv->desc.name);
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
-}
-
-static void mss_stop(const struct subsys_desc *desc)
-{
- struct mba_data *drv = subsys_to_drv(desc);
- pil_put(drv->pil);
-}
-
-static int __devinit pil_mba_driver_probe(struct platform_device *pdev)
-{
- struct mba_data *drv;
- struct resource *res;
- struct pil_desc *desc;
- int ret, irq;
-
- drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
- if (!drv)
- return -ENOMEM;
- platform_set_drvdata(pdev, drv);
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb_base");
- if (!res)
- return -EINVAL;
- drv->reg_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!drv->reg_base)
- return -ENOMEM;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "metadata_base");
- if (res) {
- drv->metadata_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!drv->metadata_base)
- return -ENOMEM;
- drv->metadata_phys = res->start;
- }
-
- desc = &drv->desc;
- ret = of_property_read_string(pdev->dev.of_node, "qcom,firmware-name",
- &desc->name);
- if (ret)
- return ret;
-
- of_property_read_string(pdev->dev.of_node, "qcom,depends-on",
- &desc->depends_on);
-
- drv->xo = devm_clk_get(&pdev->dev, "xo");
- if (IS_ERR(drv->xo))
- return PTR_ERR(drv->xo);
-
- desc->dev = &pdev->dev;
- desc->ops = &pil_mba_ops;
- desc->owner = THIS_MODULE;
- desc->proxy_timeout = PROXY_TIMEOUT_MS;
-
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
-
- drv->subsys_desc.name = desc->name;
- drv->subsys_desc.dev = &pdev->dev;
- drv->subsys_desc.owner = THIS_MODULE;
- drv->subsys_desc.shutdown = modem_shutdown;
- drv->subsys_desc.powerup = modem_powerup;
- drv->subsys_desc.ramdump = modem_ramdump;
- drv->subsys_desc.crash_shutdown = modem_crash_shutdown;
- drv->subsys_desc.start = mss_start;
- drv->subsys_desc.stop = mss_stop;
-
- drv->ramdump_dev = create_ramdump_device("modem");
- if (!drv->ramdump_dev) {
- pr_err("%s: Unable to create a modem ramdump device.\n",
- __func__);
- ret = -ENOMEM;
- goto err_ramdump;
- }
-
- drv->smem_ramdump_dev = create_ramdump_device("smem-modem");
- if (!drv->smem_ramdump_dev) {
- pr_err("%s: Unable to create an smem ramdump device.\n",
- __func__);
- ret = -ENOMEM;
- goto err_ramdump_smem;
- }
-
- drv->subsys = subsys_register(&drv->subsys_desc);
- if (IS_ERR(drv->subsys)) {
- goto err_subsys;
- ret = PTR_ERR(drv->subsys);
- }
-
- ret = devm_request_irq(&pdev->dev, irq, modem_wdog_bite_irq,
- IRQF_TRIGGER_RISING, "modem_wdog", drv);
- if (ret < 0) {
- dev_err(&pdev->dev, "Unable to request watchdog IRQ.\n");
- goto err_irq;
- }
-
- ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
- smsm_state_cb, drv);
- if (ret < 0) {
- dev_err(&pdev->dev, "Unable to register SMSM callback!\n");
- goto err_irq;
- }
-
- return 0;
-
-err_irq:
- subsys_unregister(drv->subsys);
-err_subsys:
- destroy_ramdump_device(drv->smem_ramdump_dev);
-err_ramdump_smem:
- destroy_ramdump_device(drv->ramdump_dev);
-err_ramdump:
- msm_pil_unregister(drv->pil);
- return ret;
-}
-
-static int __devexit pil_mba_driver_exit(struct platform_device *pdev)
-{
- struct mba_data *drv = platform_get_drvdata(pdev);
- smsm_state_cb_deregister(SMSM_MODEM_STATE, SMSM_RESET,
- smsm_state_cb, drv);
- subsys_unregister(drv->subsys);
- destroy_ramdump_device(drv->smem_ramdump_dev);
- destroy_ramdump_device(drv->ramdump_dev);
- msm_pil_unregister(drv->pil);
- return 0;
-}
-
-static struct of_device_id mba_match_table[] = {
- { .compatible = "qcom,pil-mba" },
- {}
-};
-
-struct platform_driver pil_mba_driver = {
- .probe = pil_mba_driver_probe,
- .remove = __devexit_p(pil_mba_driver_exit),
- .driver = {
- .name = "pil-mba",
- .of_match_table = mba_match_table,
- .owner = THIS_MODULE,
- },
-};
-
-static int __init pil_mba_init(void)
-{
- return platform_driver_register(&pil_mba_driver);
-}
-module_init(pil_mba_init);
-
-static void __exit pil_mba_exit(void)
-{
- platform_driver_unregister(&pil_mba_driver);
-}
-module_exit(pil_mba_exit);
-
-MODULE_DESCRIPTION("Support for modem boot using the Modem Boot Authenticator");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/pil-modem.c b/arch/arm/mach-msm/pil-modem.c
index ad27cd1..d3c832b 100644
--- a/arch/arm/mach-msm/pil-modem.c
+++ b/arch/arm/mach-msm/pil-modem.c
@@ -15,7 +15,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/ioport.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
@@ -23,10 +22,8 @@
#include <linux/interrupt.h>
#include <linux/reboot.h>
-#include <mach/msm_iomap.h>
#include <mach/subsystem_restart.h>
#include <mach/msm_smsm.h>
-#include <mach/peripheral-loader.h>
#include "modem_notifier.h"
#include "peripheral-loader.h"
@@ -34,37 +31,38 @@
#include "ramdump.h"
#define MARM_BOOT_CONTROL 0x0010
-#define MARM_RESET (MSM_CLK_CTL_BASE + 0x2BD4)
-#define MAHB0_SFAB_PORT_RESET (MSM_CLK_CTL_BASE + 0x2304)
-#define MARM_CLK_BRANCH_ENA_VOTE (MSM_CLK_CTL_BASE + 0x3000)
-#define MARM_CLK_SRC0_NS (MSM_CLK_CTL_BASE + 0x2BC0)
-#define MARM_CLK_SRC1_NS (MSM_CLK_CTL_BASE + 0x2BC4)
-#define MARM_CLK_SRC_CTL (MSM_CLK_CTL_BASE + 0x2BC8)
-#define MARM_CLK_CTL (MSM_CLK_CTL_BASE + 0x2BCC)
-#define SFAB_MSS_S_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2C00)
-#define MSS_MODEM_CXO_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C44)
-#define MSS_SLP_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C60)
-#define MSS_MARM_SYS_REF_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C64)
-#define MAHB0_CLK_CTL (MSM_CLK_CTL_BASE + 0x2300)
-#define MAHB1_CLK_CTL (MSM_CLK_CTL_BASE + 0x2BE4)
-#define MAHB2_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C20)
-#define MAHB1_NS (MSM_CLK_CTL_BASE + 0x2BE0)
-#define MARM_CLK_FS (MSM_CLK_CTL_BASE + 0x2BD0)
-#define MAHB2_CLK_FS (MSM_CLK_CTL_BASE + 0x2C24)
-#define PLL_ENA_MARM (MSM_CLK_CTL_BASE + 0x3500)
-#define PLL8_STATUS (MSM_CLK_CTL_BASE + 0x3158)
-#define CLK_HALT_MSS_SMPSS_MISC_STATE (MSM_CLK_CTL_BASE + 0x2FDC)
-#define MSS_MODEM_RESET (MSM_CLK_CTL_BASE + 0x2C48)
+#define MARM_RESET 0x2BD4
+#define MAHB0_SFAB_PORT_RESET 0x2304
+#define MARM_CLK_BRANCH_ENA_VOTE 0x3000
+#define MARM_CLK_SRC0_NS 0x2BC0
+#define MARM_CLK_SRC1_NS 0x2BC4
+#define MARM_CLK_SRC_CTL 0x2BC8
+#define MARM_CLK_CTL 0x2BCC
+#define SFAB_MSS_S_HCLK_CTL 0x2C00
+#define MSS_MODEM_CXO_CLK_CTL 0x2C44
+#define MSS_SLP_CLK_CTL 0x2C60
+#define MSS_MARM_SYS_REF_CLK_CTL 0x2C64
+#define MAHB0_CLK_CTL 0x2300
+#define MAHB1_CLK_CTL 0x2BE4
+#define MAHB2_CLK_CTL 0x2C20
+#define MAHB1_NS 0x2BE0
+#define MARM_CLK_FS 0x2BD0
+#define MAHB2_CLK_FS 0x2C24
+#define PLL_ENA_MARM 0x3500
+#define PLL8_STATUS 0x3158
+#define CLK_HALT_MSS_SMPSS_MISC_STATE 0x2FDC
+#define MSS_MODEM_RESET 0x2C48
struct modem_data {
void __iomem *base;
void __iomem *wdog;
- unsigned long start_addr;
+ void __iomem *cbase;
struct pil_device *pil;
struct clk *xo;
struct notifier_block notifier;
int ignore_smsm_ack;
int irq;
+ struct pil_desc pil_desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
struct delayed_work unlock_work;
@@ -91,90 +89,82 @@
clk_disable_unprepare(drv->xo);
}
-static int modem_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct modem_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-
static int modem_reset(struct pil_desc *pil)
{
u32 reg;
const struct modem_data *drv = dev_get_drvdata(pil->dev);
+ unsigned long start_addr = pil_get_entry_addr(pil);
/* Put modem AHB0,1,2 clocks into reset */
- writel_relaxed(BIT(0) | BIT(1), MAHB0_SFAB_PORT_RESET);
- writel_relaxed(BIT(7), MAHB1_CLK_CTL);
- writel_relaxed(BIT(7), MAHB2_CLK_CTL);
+ writel_relaxed(BIT(0) | BIT(1), drv->cbase + MAHB0_SFAB_PORT_RESET);
+ writel_relaxed(BIT(7), drv->cbase + MAHB1_CLK_CTL);
+ writel_relaxed(BIT(7), drv->cbase + MAHB2_CLK_CTL);
/* Vote for pll8 on behalf of the modem */
- reg = readl_relaxed(PLL_ENA_MARM);
+ reg = readl_relaxed(drv->cbase + PLL_ENA_MARM);
reg |= BIT(8);
- writel_relaxed(reg, PLL_ENA_MARM);
+ writel_relaxed(reg, drv->cbase + PLL_ENA_MARM);
/* Wait for PLL8 to enable */
- while (!(readl_relaxed(PLL8_STATUS) & BIT(16)))
+ while (!(readl_relaxed(drv->cbase + PLL8_STATUS) & BIT(16)))
cpu_relax();
/* Set MAHB1 divider to Div-5 to run MAHB1,2 and sfab at 79.8 Mhz*/
- writel_relaxed(0x4, MAHB1_NS);
+ writel_relaxed(0x4, drv->cbase + MAHB1_NS);
/* Vote for modem AHB1 and 2 clocks to be on on behalf of the modem */
- reg = readl_relaxed(MARM_CLK_BRANCH_ENA_VOTE);
+ reg = readl_relaxed(drv->cbase + MARM_CLK_BRANCH_ENA_VOTE);
reg |= BIT(0) | BIT(1);
- writel_relaxed(reg, MARM_CLK_BRANCH_ENA_VOTE);
+ writel_relaxed(reg, drv->cbase + MARM_CLK_BRANCH_ENA_VOTE);
/* Source marm_clk off of PLL8 */
- reg = readl_relaxed(MARM_CLK_SRC_CTL);
+ reg = readl_relaxed(drv->cbase + MARM_CLK_SRC_CTL);
if ((reg & 0x1) == 0) {
- writel_relaxed(0x3, MARM_CLK_SRC1_NS);
+ writel_relaxed(0x3, drv->cbase + MARM_CLK_SRC1_NS);
reg |= 0x1;
} else {
- writel_relaxed(0x3, MARM_CLK_SRC0_NS);
+ writel_relaxed(0x3, drv->cbase + MARM_CLK_SRC0_NS);
reg &= ~0x1;
}
- writel_relaxed(reg | 0x2, MARM_CLK_SRC_CTL);
+ writel_relaxed(reg | 0x2, drv->cbase + MARM_CLK_SRC_CTL);
/*
* Force core on and periph on signals to remain active during halt
* for marm_clk and mahb2_clk
*/
- writel_relaxed(0x6F, MARM_CLK_FS);
- writel_relaxed(0x6F, MAHB2_CLK_FS);
+ writel_relaxed(0x6F, drv->cbase + MARM_CLK_FS);
+ writel_relaxed(0x6F, drv->cbase + MAHB2_CLK_FS);
/*
* Enable all of the marm_clk branches, cxo sourced marm branches,
* and sleep clock branches
*/
- writel_relaxed(0x10, MARM_CLK_CTL);
- writel_relaxed(0x10, MAHB0_CLK_CTL);
- writel_relaxed(0x10, SFAB_MSS_S_HCLK_CTL);
- writel_relaxed(0x10, MSS_MODEM_CXO_CLK_CTL);
- writel_relaxed(0x10, MSS_SLP_CLK_CTL);
- writel_relaxed(0x10, MSS_MARM_SYS_REF_CLK_CTL);
+ writel_relaxed(0x10, drv->cbase + MARM_CLK_CTL);
+ writel_relaxed(0x10, drv->cbase + MAHB0_CLK_CTL);
+ writel_relaxed(0x10, drv->cbase + SFAB_MSS_S_HCLK_CTL);
+ writel_relaxed(0x10, drv->cbase + MSS_MODEM_CXO_CLK_CTL);
+ writel_relaxed(0x10, drv->cbase + MSS_SLP_CLK_CTL);
+ writel_relaxed(0x10, drv->cbase + MSS_MARM_SYS_REF_CLK_CTL);
/* Wait for above clocks to be turned on */
- while (readl_relaxed(CLK_HALT_MSS_SMPSS_MISC_STATE) & (BIT(7) | BIT(8) |
- BIT(9) | BIT(10) | BIT(4) | BIT(6)))
+ while (readl_relaxed(drv->cbase + CLK_HALT_MSS_SMPSS_MISC_STATE) &
+ (BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(4) | BIT(6)))
cpu_relax();
/* Take MAHB0,1,2 clocks out of reset */
- writel_relaxed(0x0, MAHB2_CLK_CTL);
- writel_relaxed(0x0, MAHB1_CLK_CTL);
- writel_relaxed(0x0, MAHB0_SFAB_PORT_RESET);
+ writel_relaxed(0x0, drv->cbase + MAHB2_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MAHB1_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MAHB0_SFAB_PORT_RESET);
mb();
/* Setup exception vector table base address */
- writel_relaxed(drv->start_addr | 0x1, drv->base + MARM_BOOT_CONTROL);
+ writel_relaxed(start_addr | 0x1, drv->base + MARM_BOOT_CONTROL);
/* Wait for vector table to be setup */
mb();
/* Bring modem out of reset */
- writel_relaxed(0x0, MARM_RESET);
+ writel_relaxed(0x0, drv->cbase + MARM_RESET);
return 0;
}
@@ -182,44 +172,44 @@
static int modem_pil_shutdown(struct pil_desc *pil)
{
u32 reg;
+ const struct modem_data *drv = dev_get_drvdata(pil->dev);
/* Put modem into reset */
- writel_relaxed(0x1, MARM_RESET);
+ writel_relaxed(0x1, drv->cbase + MARM_RESET);
mb();
/* Put modem AHB0,1,2 clocks into reset */
- writel_relaxed(BIT(0) | BIT(1), MAHB0_SFAB_PORT_RESET);
- writel_relaxed(BIT(7), MAHB1_CLK_CTL);
- writel_relaxed(BIT(7), MAHB2_CLK_CTL);
+ writel_relaxed(BIT(0) | BIT(1), drv->cbase + MAHB0_SFAB_PORT_RESET);
+ writel_relaxed(BIT(7), drv->cbase + MAHB1_CLK_CTL);
+ writel_relaxed(BIT(7), drv->cbase + MAHB2_CLK_CTL);
mb();
/*
* Disable all of the marm_clk branches, cxo sourced marm branches,
* and sleep clock branches
*/
- writel_relaxed(0x0, MARM_CLK_CTL);
- writel_relaxed(0x0, MAHB0_CLK_CTL);
- writel_relaxed(0x0, SFAB_MSS_S_HCLK_CTL);
- writel_relaxed(0x0, MSS_MODEM_CXO_CLK_CTL);
- writel_relaxed(0x0, MSS_SLP_CLK_CTL);
- writel_relaxed(0x0, MSS_MARM_SYS_REF_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MARM_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MAHB0_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + SFAB_MSS_S_HCLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MSS_MODEM_CXO_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MSS_SLP_CLK_CTL);
+ writel_relaxed(0x0, drv->cbase + MSS_MARM_SYS_REF_CLK_CTL);
/* Disable marm_clk */
- reg = readl_relaxed(MARM_CLK_SRC_CTL);
+ reg = readl_relaxed(drv->cbase + MARM_CLK_SRC_CTL);
reg &= ~0x2;
- writel_relaxed(reg, MARM_CLK_SRC_CTL);
+ writel_relaxed(reg, drv->cbase + MARM_CLK_SRC_CTL);
/* Clear modem's votes for ahb clocks */
- writel_relaxed(0x0, MARM_CLK_BRANCH_ENA_VOTE);
+ writel_relaxed(0x0, drv->cbase + MARM_CLK_BRANCH_ENA_VOTE);
/* Clear modem's votes for PLLs */
- writel_relaxed(0x0, PLL_ENA_MARM);
+ writel_relaxed(0x0, drv->cbase + PLL_ENA_MARM);
return 0;
}
static struct pil_reset_ops pil_modem_ops = {
- .init_image = modem_init_image,
.auth_and_reset = modem_reset,
.shutdown = modem_pil_shutdown,
.proxy_vote = make_modem_proxy_votes,
@@ -284,7 +274,7 @@
drv = container_of(dwork, struct modem_data, unlock_work);
/* The unlock didn't work, clear the reset */
- writel_relaxed(0x0, MSS_MODEM_RESET);
+ writel_relaxed(0x0, drv->cbase + MSS_MODEM_RESET);
mb();
subsystem_restart_dev(drv->subsys);
@@ -316,7 +306,7 @@
pr_err("Modem AHB locked up. Trying to free up modem!\n");
- writel_relaxed(0x3, MSS_MODEM_RESET);
+ writel_relaxed(0x3, drv->cbase + MSS_MODEM_RESET);
/*
* If we are still alive (allowing for the 5 second
* delayed-panic-reboot), the modem is either still wedged or
@@ -344,14 +334,10 @@
static int modem_start(const struct subsys_desc *subsys)
{
- void *ret;
struct modem_data *drv;
drv = container_of(subsys, struct modem_data, subsys_desc);
- ret = pil_get("modem");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->pil_desc);
}
static void modem_stop(const struct subsys_desc *subsys)
@@ -359,7 +345,7 @@
struct modem_data *drv;
drv = container_of(subsys, struct modem_data, subsys_desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int modem_shutdown(const struct subsys_desc *subsys)
@@ -389,7 +375,7 @@
/* Wait here to allow the modem to clean up caches, etc. */
msleep(20);
- pil_force_shutdown("modem");
+ pil_shutdown(&drv->pil_desc);
disable_irq_nosync(drv->irq);
return 0;
@@ -401,7 +387,7 @@
int ret;
drv = container_of(subsys, struct modem_data, subsys_desc);
- ret = pil_force_boot("modem");
+ ret = pil_boot(&drv->pil_desc);
enable_irq(drv->irq);
return ret;
@@ -431,10 +417,6 @@
struct pil_desc *desc;
int ret;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
@@ -444,28 +426,30 @@
if (drv->irq < 0)
return drv->irq;
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!drv->base)
- return -ENOMEM;
-
drv->xo = devm_clk_get(&pdev->dev, "xo");
if (IS_ERR(drv->xo))
return PTR_ERR(drv->xo);
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->base)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res)
- return -EINVAL;
-
- drv->wdog = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ drv->wdog = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->wdog)
return -ENOMEM;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ if (!res)
+ return -EINVAL;
+
+ drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!drv->cbase)
+ return -ENOMEM;
+
+ desc = &drv->pil_desc;
desc->name = "modem";
- desc->depends_on = "q6";
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
desc->proxy_timeout = 10000;
@@ -477,9 +461,9 @@
desc->ops = &pil_modem_ops;
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
drv->notifier.notifier_call = modem_notif_handler,
ret = modem_register_notifier(&drv->notifier);
@@ -487,7 +471,7 @@
goto err_notify;
drv->subsys_desc.name = "modem";
- drv->subsys_desc.depends_on = "q6";
+ drv->subsys_desc.depends_on = "adsp";
drv->subsys_desc.dev = &pdev->dev;
drv->subsys_desc.owner = THIS_MODULE;
drv->subsys_desc.start = modem_start;
@@ -506,7 +490,7 @@
goto err_subsys;
}
- drv->ramdump_dev = create_ramdump_device("modem");
+ drv->ramdump_dev = create_ramdump_device("modem", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -525,7 +509,7 @@
err_subsys:
modem_unregister_notifier(&drv->notifier);
err_notify:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -536,7 +520,7 @@
destroy_ramdump_device(drv->ramdump_dev);
subsys_unregister(drv->subsys);
modem_unregister_notifier(&drv->notifier);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-pronto.c b/arch/arm/mach-msm/pil-pronto.c
index 04b3a21..6e8d127 100644
--- a/arch/arm/mach-msm/pil-pronto.c
+++ b/arch/arm/mach-msm/pil-pronto.c
@@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -27,13 +26,12 @@
#include <linux/workqueue.h>
#include <linux/wcnss_wlan.h>
-#include <mach/peripheral-loader.h>
#include <mach/subsystem_restart.h>
-#include <mach/peripheral-loader.h>
#include <mach/msm_smsm.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
+#include "ramdump.h"
#define PRONTO_PMU_COMMON_GDSCR 0x24
#define PRONTO_PMU_COMMON_GDSCR_SW_COLLAPSE BIT(0)
@@ -74,7 +72,6 @@
void __iomem *base;
void __iomem *reset_base;
void __iomem *axi_halt_base;
- unsigned long start_addr;
struct pil_device *pil;
struct pil_desc desc;
struct subsys_device *subsys;
@@ -85,6 +82,7 @@
bool crash;
struct delayed_work cancel_vote_work;
int irq;
+ struct ramdump_device *ramdump_dev;
};
static int pil_pronto_make_proxy_vote(struct pil_desc *pil)
@@ -116,22 +114,13 @@
clk_disable_unprepare(drv->cxo);
}
-static int pil_pronto_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct pronto_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-
static int pil_pronto_reset(struct pil_desc *pil)
{
u32 reg;
int rc;
struct pronto_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
- unsigned long start_addr = drv->start_addr;
+ unsigned long start_addr = pil_get_entry_addr(pil);
/* Deassert reset to subsystem and wait for propagation */
reg = readl_relaxed(drv->reset_base);
@@ -234,7 +223,6 @@
}
static struct pil_reset_ops pil_pronto_ops = {
- .init_image = pil_pronto_init_image,
.auth_and_reset = pil_pronto_reset,
.shutdown = pil_pronto_shutdown,
.proxy_vote = pil_pronto_make_proxy_vote,
@@ -245,19 +233,14 @@
static int pronto_start(const struct subsys_desc *desc)
{
- void *ret;
struct pronto_data *drv = subsys_to_drv(desc);
-
- ret = pil_get(drv->desc.name);
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->desc);
}
static void pronto_stop(const struct subsys_desc *desc)
{
struct pronto_data *drv = subsys_to_drv(desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->desc);
}
static void log_wcnss_sfr(void)
@@ -320,6 +303,7 @@
return IRQ_HANDLED;
}
+ disable_irq_nosync(drv->irq);
drv->restart_inprogress = true;
restart_wcnss(drv);
@@ -338,10 +322,9 @@
{
struct pronto_data *drv = subsys_to_drv(subsys);
- pil_force_shutdown("wcnss");
+ pil_shutdown(&drv->desc);
flush_delayed_work(&drv->cancel_vote_work);
wcnss_flush_delayed_boot_votes();
- disable_irq_nosync(drv->irq);
return 0;
}
@@ -358,7 +341,9 @@
WCNSS_WLAN_SWITCH_ON);
if (!ret) {
msleep(1000);
- pil_force_boot("wcnss");
+ ret = pil_boot(&drv->desc);
+ if (ret)
+ return ret;
}
drv->restart_inprogress = false;
enable_irq(drv->irq);
@@ -376,9 +361,19 @@
smsm_change_state(SMSM_APPS_STATE, SMSM_RESET, SMSM_RESET);
}
-static int wcnss_ramdump(int enable, const struct subsys_desc *crashed_subsys)
+static struct ramdump_segment pronto_segments[] = {
+ { 0x0D200000, 0x0D980000 - 0x0D200000 }
+};
+
+static int wcnss_ramdump(int enable, const struct subsys_desc *subsys)
{
- return 0;
+ struct pronto_data *drv = subsys_to_drv(subsys);
+
+ if (enable)
+ return do_ramdump(drv->ramdump_dev, pronto_segments,
+ ARRAY_SIZE(pronto_segments));
+ else
+ return 0;
}
static int __devinit pil_pronto_probe(struct platform_device *pdev)
@@ -389,10 +384,6 @@
int ret;
uint32_t regval;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu_base");
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
@@ -402,23 +393,20 @@
if (drv->irq < 0)
return drv->irq;
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu_base");
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->base)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clk_base");
- if (!res)
- return -EINVAL;
-
- drv->reset_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->reset_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->reset_base)
+ return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "halt_base");
- if (!res)
- return -EINVAL;
-
- drv->axi_halt_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->axi_halt_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->axi_halt_base)
+ return -ENOMEM;
desc = &drv->desc;
ret = of_property_read_string(pdev->dev.of_node, "qcom,firmware-name",
@@ -456,9 +444,9 @@
if (IS_ERR(drv->cxo))
return PTR_ERR(drv->cxo);
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
ret = smsm_state_cb_register(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
@@ -488,6 +476,12 @@
if (ret < 0)
goto err_irq;
+ drv->ramdump_dev = create_ramdump_device("pronto", &pdev->dev);
+ if (!drv->ramdump_dev) {
+ ret = -ENOMEM;
+ goto err_irq;
+ }
+
/* Initialize common_ss GDSCR to wait 4 cycles between states */
regval = readl_relaxed(drv->base + PRONTO_PMU_COMMON_GDSCR)
& PRONTO_PMU_COMMON_GDSCR_SW_COLLAPSE;
@@ -502,7 +496,7 @@
smsm_state_cb_deregister(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
err_smsm:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -512,7 +506,8 @@
subsys_unregister(drv->subsys);
smsm_state_cb_deregister(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->desc);
+ destroy_ramdump_device(drv->ramdump_dev);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v3.c b/arch/arm/mach-msm/pil-q6v3.c
index 9de9c60..d7e712c 100644
--- a/arch/arm/mach-msm/pil-q6v3.c
+++ b/arch/arm/mach-msm/pil-q6v3.c
@@ -16,16 +16,13 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/delay.h>
-#include <linux/elf.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
-#include <mach/msm_iomap.h>
#include <mach/subsystem_restart.h>
#include <mach/scm.h>
-#include <mach/peripheral-loader.h>
#include "ramdump.h"
#include "peripheral-loader.h"
@@ -35,7 +32,7 @@
#define QDSP6SS_STRAP_TCM 0x001C
#define QDSP6SS_STRAP_AHB 0x0020
-#define LCC_Q6_FUNC (MSM_LPASS_CLK_CTL_BASE + 0x001C)
+#define LCC_Q6_FUNC 0x001C
#define LV_EN BIT(27)
#define STOP_CORE BIT(26)
#define CLAMP_IO BIT(25)
@@ -71,9 +68,9 @@
/**
* struct q6v3_data - LPASS driver data
* @base: register base
+ * @cbase: clock base
* @wk_base: wakeup register base
* @wd_base: watchdog register base
- * @start_addr: address that processor starts running at
* @irq: watchdog irq
* @pil: peripheral handle
* @subsys: subsystem restart handle
@@ -84,11 +81,11 @@
*/
struct q6v3_data {
void __iomem *base;
+ void __iomem *cbase;
void __iomem *wk_base;
void __iomem *wd_base;
- unsigned long start_addr;
int irq;
- struct pil_device *pil;
+ struct pil_desc pil_desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
struct work_struct fatal_wrk;
@@ -96,15 +93,6 @@
struct ramdump_device *ramdump_dev;
};
-static int pil_q6v3_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct q6v3_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-
static void pil_q6v3_remove_proxy_votes(struct pil_desc *pil)
{
struct q6v3_data *drv = dev_get_drvdata(pil->dev);
@@ -128,13 +116,14 @@
{
u32 reg;
struct q6v3_data *drv = dev_get_drvdata(pil->dev);
+ unsigned long start_addr = pil_get_entry_addr(pil);
/* Put Q6 into reset */
- reg = readl_relaxed(LCC_Q6_FUNC);
+ reg = readl_relaxed(drv->cbase + LCC_Q6_FUNC);
reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE |
CORE_ARES;
reg &= ~CORE_GFM4_CLK_EN;
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
/* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */
usleep_range(20, 30);
@@ -142,17 +131,17 @@
/* Turn on Q6 memory */
reg |= CORE_GFM4_CLK_EN | CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN |
CORE_TCM_MEM_PERPH_EN;
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
/* Turn on Q6 core clocks and take core out of reset */
reg &= ~(CLAMP_IO | Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES |
CORE_ARES);
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
/* Wait for clocks to be enabled */
mb();
/* Program boot address */
- writel_relaxed((drv->start_addr >> 12) & 0xFFFFF,
+ writel_relaxed((start_addr >> 12) & 0xFFFFF,
drv->base + QDSP6SS_RST_EVB);
writel_relaxed(Q6_STRAP_TCM_CONFIG | Q6_STRAP_TCM_BASE,
@@ -165,7 +154,7 @@
/* Start Q6 instruction execution */
reg &= ~STOP_CORE;
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
return 0;
}
@@ -173,13 +162,14 @@
static int pil_q6v3_shutdown(struct pil_desc *pil)
{
u32 reg;
+ struct q6v3_data *drv = dev_get_drvdata(pil->dev);
/* Put Q6 into reset */
- reg = readl_relaxed(LCC_Q6_FUNC);
+ reg = readl_relaxed(drv->cbase + LCC_Q6_FUNC);
reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE |
CORE_ARES;
reg &= ~CORE_GFM4_CLK_EN;
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
/* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */
usleep_range(20, 30);
@@ -187,16 +177,15 @@
/* Turn off Q6 memory */
reg &= ~(CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN |
CORE_TCM_MEM_PERPH_EN);
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
reg |= CLAMP_IO;
- writel_relaxed(reg, LCC_Q6_FUNC);
+ writel_relaxed(reg, drv->cbase + LCC_Q6_FUNC);
return 0;
}
static struct pil_reset_ops pil_q6v3_ops = {
- .init_image = pil_q6v3_init_image,
.auth_and_reset = pil_q6v3_reset,
.shutdown = pil_q6v3_shutdown,
.proxy_vote = pil_q6v3_make_proxy_votes,
@@ -250,14 +239,10 @@
static int lpass_q6_start(const struct subsys_desc *subsys)
{
- void *ret;
struct q6v3_data *drv;
drv = container_of(subsys, struct q6v3_data, subsys_desc);
- ret = pil_get("q6");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->pil_desc);
}
static void lpass_q6_stop(const struct subsys_desc *subsys)
@@ -265,7 +250,7 @@
struct q6v3_data *drv;
drv = container_of(subsys, struct q6v3_data, subsys_desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int lpass_q6_shutdown(const struct subsys_desc *subsys)
@@ -277,7 +262,7 @@
writel_relaxed(0x0, drv->wd_base + 0x24);
mb();
- pil_force_shutdown("q6");
+ pil_shutdown(&drv->pil_desc);
disable_irq_nosync(drv->irq);
return 0;
@@ -289,7 +274,7 @@
int ret;
drv = container_of(subsys, struct q6v3_data, subsys_desc);
- ret = pil_force_boot("q6");
+ ret = pil_boot(&drv->pil_desc);
enable_irq(drv->irq);
return ret;
}
@@ -338,33 +323,31 @@
struct pil_desc *desc;
int ret;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
platform_set_drvdata(pdev, drv);
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->base)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res)
- return -EINVAL;
-
- drv->wk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ drv->wk_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->wk_base)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ drv->wd_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->wd_base)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
if (!res)
return -EINVAL;
-
- drv->wd_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!drv->wd_base)
+ drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!drv->cbase)
return -ENOMEM;
drv->irq = platform_get_irq(pdev, 0);
@@ -375,10 +358,7 @@
if (IS_ERR(drv->pll))
return PTR_ERR(drv->pll);
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!drv)
- return -ENOMEM;
-
+ desc = &drv->pil_desc;
desc->name = "q6";
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
@@ -392,11 +372,11 @@
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
- drv->subsys_desc.name = "lpass";
+ drv->subsys_desc.name = "adsp";
drv->subsys_desc.dev = &pdev->dev;
drv->subsys_desc.owner = THIS_MODULE;
drv->subsys_desc.start = lpass_q6_start;
@@ -408,7 +388,7 @@
INIT_WORK(&drv->fatal_wrk, q6_fatal_fn);
- drv->ramdump_dev = create_ramdump_device("lpass");
+ drv->ramdump_dev = create_ramdump_device("lpass", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -433,7 +413,7 @@
err_subsys:
destroy_ramdump_device(drv->ramdump_dev);
err_ramdump:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -442,7 +422,7 @@
struct q6v3_data *drv = platform_get_drvdata(pdev);
subsys_unregister(drv->subsys);
destroy_ramdump_device(drv->ramdump_dev);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v4-lpass.c b/arch/arm/mach-msm/pil-q6v4-lpass.c
index 8164d64..1e6c1f6 100644
--- a/arch/arm/mach-msm/pil-q6v4-lpass.c
+++ b/arch/arm/mach-msm/pil-q6v4-lpass.c
@@ -22,7 +22,6 @@
#include <linux/delay.h>
#include <mach/scm.h>
-#include <mach/peripheral-loader.h>
#include <mach/subsystem_restart.h>
#include <mach/subsystem_notif.h>
@@ -43,7 +42,6 @@
void *ramdump_dev;
struct work_struct work;
int loadable;
- void *pil;
};
static int pil_q6v4_lpass_boot(struct pil_desc *pil)
@@ -71,7 +69,6 @@
}
static struct pil_reset_ops pil_q6v4_lpass_ops = {
- .init_image = pil_q6v4_init_image,
.auth_and_reset = pil_q6v4_lpass_boot,
.shutdown = pil_q6v4_lpass_shutdown,
.proxy_vote = pil_q6v4_make_proxy_votes,
@@ -197,19 +194,17 @@
{
struct lpass_q6v4 *drv = subsys_to_lpass(desc);
- if (drv->loadable) {
- drv->pil = pil_get("q6");
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
- }
+ if (drv->loadable)
+ return pil_boot(&drv->q6.desc);
return 0;
}
static void lpass_stop(const struct subsys_desc *desc)
{
struct lpass_q6v4 *drv = subsys_to_lpass(desc);
+
if (drv->loadable)
- pil_put(drv->pil);
+ pil_shutdown(&drv->q6.desc);
}
static int lpass_shutdown(const struct subsys_desc *subsys)
@@ -218,7 +213,7 @@
send_q6_nmi();
if (drv->loadable)
- pil_force_shutdown("q6");
+ pil_shutdown(&drv->q6.desc);
disable_irq_nosync(drv->q6.wdog_irq);
return 0;
@@ -230,7 +225,7 @@
int ret = 0;
if (drv->loadable)
- ret = pil_force_boot("q6");
+ ret = pil_boot(&drv->q6.desc);
enable_irq(drv->q6.wdog_irq);
return ret;
@@ -291,10 +286,7 @@
drv->loadable = !!pdata; /* No pdata = don't use PIL */
if (drv->loadable) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
- q6->base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ q6->base = devm_request_and_ioremap(&pdev->dev, res);
if (!q6->base)
return -ENOMEM;
@@ -320,12 +312,12 @@
dev_info(&pdev->dev, "using non-secure boot\n");
}
- q6->pil = msm_pil_register(desc);
- if (IS_ERR(q6->pil))
- return PTR_ERR(q6->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
}
- drv->subsys_desc.name = "lpass";
+ drv->subsys_desc.name = "adsp";
drv->subsys_desc.dev = &pdev->dev;
drv->subsys_desc.owner = THIS_MODULE;
drv->subsys_desc.start = lpass_start;
@@ -337,7 +329,7 @@
INIT_WORK(&drv->work, lpass_fatal_fn);
- drv->ramdump_dev = create_ramdump_device("lpass");
+ drv->ramdump_dev = create_ramdump_device("lpass", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -348,6 +340,8 @@
ret = PTR_ERR(drv->subsys);
goto err_subsys;
}
+ if (!drv->loadable)
+ subsys_default_online(drv->subsys);
ret = devm_request_irq(&pdev->dev, q6->wdog_irq, lpass_wdog_bite_irq,
IRQF_TRIGGER_RISING, dev_name(&pdev->dev), drv);
@@ -383,7 +377,7 @@
destroy_ramdump_device(drv->ramdump_dev);
err_ramdump:
if (drv->loadable)
- msm_pil_unregister(q6->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -397,7 +391,7 @@
subsys_unregister(drv->subsys);
destroy_ramdump_device(drv->ramdump_dev);
if (drv->loadable)
- msm_pil_unregister(drv->q6.pil);
+ pil_desc_release(&drv->q6.desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v4-mss.c b/arch/arm/mach-msm/pil-q6v4-mss.c
index fe8c3b1..ee01f04 100644
--- a/arch/arm/mach-msm/pil-q6v4-mss.c
+++ b/arch/arm/mach-msm/pil-q6v4-mss.c
@@ -20,10 +20,8 @@
#include <linux/clk.h>
#include <linux/interrupt.h>
-#include <mach/msm_iomap.h>
#include <mach/subsystem_restart.h>
#include <mach/msm_smsm.h>
-#include <mach/peripheral-loader.h>
#include "smd_private.h"
#include "ramdump.h"
@@ -31,16 +29,17 @@
#include "pil-q6v4.h"
#include "scm-pas.h"
-#define MSS_S_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2C70)
-#define MSS_SLP_CLK_CTL (MSM_CLK_CTL_BASE + 0x2C60)
-#define SFAB_MSS_M_ACLK_CTL (MSM_CLK_CTL_BASE + 0x2340)
-#define SFAB_MSS_S_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2C00)
-#define MSS_RESET (MSM_CLK_CTL_BASE + 0x2C64)
+#define MSS_S_HCLK_CTL 0x2C70
+#define MSS_SLP_CLK_CTL 0x2C60
+#define SFAB_MSS_M_ACLK_CTL 0x2340
+#define SFAB_MSS_S_HCLK_CTL 0x2C00
+#define MSS_RESET 0x2C64
struct q6v4_modem {
struct q6v4_data q6_fw;
struct q6v4_data q6_sw;
void __iomem *modem_base;
+ void __iomem *cbase;
void *fw_ramdump_dev;
void *sw_ramdump_dev;
void *smem_ramdump_dev;
@@ -55,21 +54,22 @@
static unsigned pil_q6v4_modem_count;
/* Bring modem subsystem out of reset */
-static void pil_q6v4_init_modem(void __iomem *base, void __iomem *jtag_clk)
+static void pil_q6v4_init_modem(void __iomem *base, void __iomem *cbase,
+ void __iomem *jtag_clk)
{
mutex_lock(&pil_q6v4_modem_lock);
if (!pil_q6v4_modem_count) {
/* Enable MSS clocks */
- writel_relaxed(0x10, SFAB_MSS_M_ACLK_CTL);
- writel_relaxed(0x10, SFAB_MSS_S_HCLK_CTL);
- writel_relaxed(0x10, MSS_S_HCLK_CTL);
- writel_relaxed(0x10, MSS_SLP_CLK_CTL);
+ writel_relaxed(0x10, cbase + SFAB_MSS_M_ACLK_CTL);
+ writel_relaxed(0x10, cbase + SFAB_MSS_S_HCLK_CTL);
+ writel_relaxed(0x10, cbase + MSS_S_HCLK_CTL);
+ writel_relaxed(0x10, cbase + MSS_SLP_CLK_CTL);
/* Wait for clocks to enable */
mb();
udelay(10);
/* De-assert MSS reset */
- writel_relaxed(0x0, MSS_RESET);
+ writel_relaxed(0x0, cbase + MSS_RESET);
mb();
udelay(10);
/* Enable MSS */
@@ -85,13 +85,13 @@
}
/* Put modem subsystem back into reset */
-static void pil_q6v4_shutdown_modem(void)
+static void pil_q6v4_shutdown_modem(struct q6v4_modem *mdm)
{
mutex_lock(&pil_q6v4_modem_lock);
if (pil_q6v4_modem_count)
pil_q6v4_modem_count--;
if (pil_q6v4_modem_count == 0)
- writel_relaxed(0x1, MSS_RESET);
+ writel_relaxed(0x1, mdm->cbase + MSS_RESET);
mutex_unlock(&pil_q6v4_modem_lock);
}
@@ -105,25 +105,25 @@
if (err)
return err;
- pil_q6v4_init_modem(mdm->modem_base, drv->jtag_clk_reg);
+ pil_q6v4_init_modem(mdm->modem_base, mdm->cbase, drv->jtag_clk_reg);
return pil_q6v4_boot(pil);
}
static int pil_q6v4_modem_shutdown(struct pil_desc *pil)
{
struct q6v4_data *drv = pil_to_q6v4_data(pil);
+ struct q6v4_modem *mdm = dev_get_drvdata(pil->dev);
int ret;
ret = pil_q6v4_shutdown(pil);
if (ret)
return ret;
- pil_q6v4_shutdown_modem();
+ pil_q6v4_shutdown_modem(mdm);
pil_q6v4_power_down(drv);
return 0;
}
static struct pil_reset_ops pil_q6v4_modem_ops = {
- .init_image = pil_q6v4_init_image,
.auth_and_reset = pil_q6v4_modem_boot,
.shutdown = pil_q6v4_modem_shutdown,
.proxy_vote = pil_q6v4_make_proxy_votes,
@@ -173,20 +173,26 @@
static int modem_start(const struct subsys_desc *desc)
{
struct q6v4_modem *drv = desc_to_modem(desc);
+ int ret = 0;
if (drv->loadable) {
- drv->pil = pil_get("modem");
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_boot(&drv->q6_fw.desc);
+ if (ret)
+ return ret;
+ ret = pil_boot(&drv->q6_sw.desc);
+ if (ret)
+ pil_shutdown(&drv->q6_fw.desc);
}
- return 0;
+ return ret;
}
static void modem_stop(const struct subsys_desc *desc)
{
struct q6v4_modem *drv = desc_to_modem(desc);
- if (drv->loadable)
- pil_put(drv->pil);
+ if (drv->loadable) {
+ pil_shutdown(&drv->q6_sw.desc);
+ pil_shutdown(&drv->q6_fw.desc);
+ }
}
static int modem_shutdown(const struct subsys_desc *subsys)
@@ -199,8 +205,8 @@
mb();
if (drv->loadable) {
- pil_force_shutdown("modem");
- pil_force_shutdown("modem_fw");
+ pil_shutdown(&drv->q6_sw.desc);
+ pil_shutdown(&drv->q6_fw.desc);
}
disable_irq_nosync(drv->q6_fw.wdog_irq);
@@ -212,10 +218,17 @@
static int modem_powerup(const struct subsys_desc *subsys)
{
struct q6v4_modem *drv = desc_to_modem(subsys);
+ int ret;
if (drv->loadable) {
- pil_force_boot("modem_fw");
- pil_force_boot("modem");
+ ret = pil_boot(&drv->q6_fw.desc);
+ if (ret)
+ return ret;
+ ret = pil_boot(&drv->q6_sw.desc);
+ if (ret) {
+ pil_shutdown(&drv->q6_fw.desc);
+ return ret;
+ }
}
enable_irq(drv->q6_fw.wdog_irq);
enable_irq(drv->q6_sw.wdog_irq);
@@ -299,20 +312,13 @@
struct pil_desc *desc;
struct resource *res;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + (i * 2));
- if (!res)
- return -EINVAL;
-
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + (i * 2));
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->base)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + (i * 2));
- if (!res)
- return -EINVAL;
-
- drv->wdog_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 3 + (i * 2));
+ drv->wdog_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->wdog_base)
return -ENOMEM;
@@ -327,7 +333,6 @@
desc = &drv->desc;
desc->name = pdata->name;
- desc->depends_on = pdata->depends;
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
desc->proxy_timeout = 10000;
@@ -396,27 +401,29 @@
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
-
- drv->modem_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->modem_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->modem_base)
return -ENOMEM;
- drv_fw->pil = msm_pil_register(&drv_fw->desc);
- if (IS_ERR(drv_fw->pil))
- return PTR_ERR(drv_fw->pil);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return -EINVAL;
+ drv->cbase = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!drv->cbase)
+ return -ENOMEM;
- drv_sw->pil = msm_pil_register(&drv_sw->desc);
- if (IS_ERR(drv_sw->pil)) {
- ret = PTR_ERR(drv_sw->pil);
+ ret = pil_desc_init(&drv_fw->desc);
+ if (ret)
+ return ret;
+
+ ret = pil_desc_init(&drv_sw->desc);
+ if (ret)
goto err_pil_sw;
- }
}
drv->subsys_desc.name = "modem";
- drv->subsys_desc.depends_on = "lpass";
+ drv->subsys_desc.depends_on = "adsp";
drv->subsys_desc.dev = &pdev->dev;
drv->subsys_desc.owner = THIS_MODULE;
drv->subsys_desc.start = modem_start;
@@ -426,19 +433,19 @@
drv->subsys_desc.ramdump = modem_ramdump;
drv->subsys_desc.crash_shutdown = modem_crash_shutdown;
- drv->fw_ramdump_dev = create_ramdump_device("modem_fw");
+ drv->fw_ramdump_dev = create_ramdump_device("modem_fw", &pdev->dev);
if (!drv->fw_ramdump_dev) {
ret = -ENOMEM;
goto err_fw_ramdump;
}
- drv->sw_ramdump_dev = create_ramdump_device("modem_sw");
+ drv->sw_ramdump_dev = create_ramdump_device("modem_sw", &pdev->dev);
if (!drv->sw_ramdump_dev) {
ret = -ENOMEM;
goto err_sw_ramdump;
}
- drv->smem_ramdump_dev = create_ramdump_device("smem-modem");
+ drv->smem_ramdump_dev = create_ramdump_device("smem-modem", &pdev->dev);
if (!drv->smem_ramdump_dev) {
ret = -ENOMEM;
goto err_smem_ramdump;
@@ -449,6 +456,8 @@
ret = PTR_ERR(drv->subsys);
goto err_subsys;
}
+ if (!drv->loadable)
+ subsys_default_online(drv->subsys);
ret = devm_request_irq(&pdev->dev, drv_fw->wdog_irq,
modem_wdog_bite_irq, IRQF_TRIGGER_RISING,
@@ -478,9 +487,9 @@
destroy_ramdump_device(drv->fw_ramdump_dev);
err_fw_ramdump:
if (drv->loadable)
- msm_pil_unregister(drv_sw->pil);
+ pil_desc_release(&drv_sw->desc);
err_pil_sw:
- msm_pil_unregister(drv_fw->pil);
+ pil_desc_release(&drv_fw->desc);
return ret;
}
@@ -495,8 +504,8 @@
destroy_ramdump_device(drv->sw_ramdump_dev);
destroy_ramdump_device(drv->fw_ramdump_dev);
if (drv->loadable) {
- msm_pil_unregister(drv->q6_sw.pil);
- msm_pil_unregister(drv->q6_fw.pil);
+ pil_desc_release(&drv->q6_sw.desc);
+ pil_desc_release(&drv->q6_fw.desc);
}
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v4.c b/arch/arm/mach-msm/pil-q6v4.c
index 47033fc..7f04c64 100644
--- a/arch/arm/mach-msm/pil-q6v4.c
+++ b/arch/arm/mach-msm/pil-q6v4.c
@@ -16,7 +16,6 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/regulator/consumer.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
@@ -52,16 +51,6 @@
#define Q6SS_CLK_ENA BIT(1)
#define Q6SS_SRC_SWITCH_CLK_OVR BIT(8)
-int pil_q6v4_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct q6v4_data *drv = pil_to_q6v4_data(pil);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-EXPORT_SYMBOL(pil_q6v4_init_image);
-
int pil_q6v4_make_proxy_votes(struct pil_desc *pil)
{
const struct q6v4_data *drv = pil_to_q6v4_data(pil);
@@ -141,6 +130,7 @@
{
u32 reg, err;
const struct q6v4_data *drv = pil_to_q6v4_data(pil);
+ unsigned long start_addr = pil_get_entry_addr(pil);
/* Enable Q6 ACLK */
writel_relaxed(0x10, drv->aclk_reg);
@@ -156,7 +146,7 @@
writel_relaxed(reg, drv->base + QDSP6SS_RESET);
/* Program boot address */
- writel_relaxed((drv->start_addr >> 8) & 0xFFFFFF,
+ writel_relaxed((start_addr >> 8) & 0xFFFFFF,
drv->base + QDSP6SS_RST_EVB);
/* Program TCM and AHB address ranges */
diff --git a/arch/arm/mach-msm/pil-q6v4.h b/arch/arm/mach-msm/pil-q6v4.h
index 0395bed..86e55ea 100644
--- a/arch/arm/mach-msm/pil-q6v4.h
+++ b/arch/arm/mach-msm/pil-q6v4.h
@@ -21,7 +21,6 @@
void __iomem *aclk_reg;
void __iomem *jtag_clk_reg;
const char *name;
- const char *depends;
const unsigned pas_id;
int bus_port;
};
@@ -36,7 +35,6 @@
struct q6v4_data {
void __iomem *base;
void __iomem *wdog_base;
- unsigned long start_addr;
unsigned long strap_tcm_base;
unsigned long strap_ahb_upper;
unsigned long strap_ahb_lower;
@@ -51,14 +49,11 @@
bool vreg_enabled;
struct clk *xo;
- struct pil_device *pil;
struct pil_desc desc;
};
#define pil_to_q6v4_data(p) container_of(p, struct q6v4_data, desc)
-extern int pil_q6v4_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size);
extern int pil_q6v4_make_proxy_votes(struct pil_desc *pil);
extern void pil_q6v4_remove_proxy_votes(struct pil_desc *pil);
extern int pil_q6v4_power_up(struct q6v4_data *drv);
diff --git a/arch/arm/mach-msm/pil-q6v5-lpass.c b/arch/arm/mach-msm/pil-q6v5-lpass.c
index 3c68da0..662377d 100644
--- a/arch/arm/mach-msm/pil-q6v5-lpass.c
+++ b/arch/arm/mach-msm/pil-q6v5-lpass.c
@@ -26,7 +26,6 @@
#include <mach/subsystem_restart.h>
#include <mach/subsystem_notif.h>
#include <mach/scm.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
#include "pil-q6v5.h"
@@ -119,6 +118,7 @@
static int pil_lpass_reset(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
+ unsigned long start_addr = pil_get_entry_addr(pil);
int ret;
ret = pil_lpass_enable_clks(drv);
@@ -126,7 +126,7 @@
return ret;
/* Program Image Address */
- writel_relaxed(((drv->start_addr >> 4) & 0x0FFFFFF0),
+ writel_relaxed((start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
ret = pil_q6v5_reset(pil);
@@ -141,7 +141,6 @@
}
static struct pil_reset_ops pil_lpass_ops = {
- .init_image = pil_q6v5_init_image,
.proxy_vote = pil_q6v5_make_proxy_votes,
.proxy_unvote = pil_q6v5_remove_proxy_votes,
.auth_and_reset = pil_lpass_reset,
@@ -286,7 +285,7 @@
send_q6_nmi();
/* The write needs to go through before the q6 is shutdown. */
mb();
- pil_force_shutdown("adsp");
+ pil_shutdown(&drv->q6->desc);
disable_irq_nosync(drv->wdog_irq);
return 0;
@@ -302,7 +301,7 @@
msleep(10000);
}
- ret = pil_force_boot("adsp");
+ ret = pil_boot(&drv->q6->desc);
enable_irq(drv->wdog_irq);
return ret;
@@ -339,19 +338,15 @@
static int lpass_start(const struct subsys_desc *desc)
{
- void *ret;
struct lpass_data *drv = subsys_to_drv(desc);
- ret = pil_get(drv->q6->desc.name);
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->q6->desc);
}
static void lpass_stop(const struct subsys_desc *desc)
{
struct lpass_data *drv = subsys_to_drv(desc);
- pil_put(drv->q6->pil);
+ pil_shutdown(&drv->q6->desc);
}
static int __devinit pil_lpass_driver_probe(struct platform_device *pdev)
@@ -403,9 +398,9 @@
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->q6->pil = msm_pil_register(desc);
- if (IS_ERR(drv->q6->pil))
- return PTR_ERR(drv->q6->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
drv->subsys_desc.name = desc->name;
drv->subsys_desc.owner = THIS_MODULE;
@@ -419,7 +414,7 @@
INIT_WORK(&drv->work, adsp_fatal_fn);
- drv->ramdump_dev = create_ramdump_device("adsp");
+ drv->ramdump_dev = create_ramdump_device("adsp", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -464,7 +459,7 @@
err_subsys:
destroy_ramdump_device(drv->ramdump_dev);
err_ramdump:
- msm_pil_unregister(drv->q6->pil);
+ pil_desc_release(desc);
return 0;
}
@@ -477,7 +472,7 @@
adsp_smsm_state_cb, drv);
subsys_unregister(drv->subsys);
destroy_ramdump_device(drv->ramdump_dev);
- msm_pil_unregister(drv->q6->pil);
+ pil_desc_release(&drv->q6->desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index b856d05..5bed8b4 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -17,18 +17,22 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
+#include <linux/interrupt.h>
+#include <mach/subsystem_restart.h>
#include <mach/clk.h>
+#include <mach/msm_smsm.h>
#include "peripheral-loader.h"
#include "pil-q6v5.h"
+#include "ramdump.h"
+#include "sysmon.h"
/* Q6 Register Offsets */
#define QDSP6SS_RST_EVB 0x010
@@ -46,14 +50,48 @@
/* PBL/MBA interface registers */
#define RMB_MBA_IMAGE 0x00
#define RMB_PBL_STATUS 0x04
+#define RMB_MBA_COMMAND 0x08
#define RMB_MBA_STATUS 0x0C
+#define RMB_PMI_META_DATA 0x10
+#define RMB_PMI_CODE_START 0x14
+#define RMB_PMI_CODE_LENGTH 0x18
#define PROXY_TIMEOUT_MS 10000
#define POLL_INTERVAL_US 50
+#define CMD_META_DATA_READY 0x1
+#define CMD_LOAD_READY 0x2
+
+#define STATUS_META_DATA_AUTH_SUCCESS 0x3
+#define STATUS_AUTH_COMPLETE 0x4
+
+#define MAX_SSR_REASON_LEN 81U
+
+struct mba_data {
+ void __iomem *metadata_base;
+ void __iomem *rmb_base;
+ void __iomem *io_clamp_reg;
+ unsigned long metadata_phys;
+ struct pil_desc desc;
+ struct subsys_device *subsys;
+ struct subsys_desc subsys_desc;
+ void *adsp_state_notifier;
+ u32 img_length;
+ struct q6v5_data *q6;
+ int self_auth;
+ void *ramdump_dev;
+ void *smem_ramdump_dev;
+ bool crash_shutdown;
+ bool ignore_errors;
+ int is_loadable;
+};
+
static int pbl_mba_boot_timeout_ms = 100;
module_param(pbl_mba_boot_timeout_ms, int, S_IRUGO | S_IWUSR);
+static int modem_auth_timeout_ms = 10000;
+module_param(modem_auth_timeout_ms, int, S_IRUGO | S_IWUSR);
+
static int pil_mss_power_up(struct q6v5_data *drv)
{
int ret;
@@ -105,11 +143,12 @@
static int wait_for_mba_ready(struct q6v5_data *drv)
{
struct device *dev = drv->desc.dev;
+ struct mba_data *mba = platform_get_drvdata(to_platform_device(dev));
int ret;
u32 status;
/* Wait for PBL completion. */
- ret = readl_poll_timeout(drv->rmb_base + RMB_PBL_STATUS, status,
+ ret = readl_poll_timeout(mba->rmb_base + RMB_PBL_STATUS, status,
status != 0, POLL_INTERVAL_US, pbl_mba_boot_timeout_ms * 1000);
if (ret) {
dev_err(dev, "PBL boot timed out\n");
@@ -121,7 +160,7 @@
}
/* Wait for MBA completion. */
- ret = readl_poll_timeout(drv->rmb_base + RMB_MBA_STATUS, status,
+ ret = readl_poll_timeout(mba->rmb_base + RMB_MBA_STATUS, status,
status != 0, POLL_INTERVAL_US, pbl_mba_boot_timeout_ms * 1000);
if (ret) {
dev_err(dev, "MBA boot timed out\n");
@@ -168,6 +207,9 @@
static int pil_mss_reset(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
+ struct platform_device *pdev = to_platform_device(pil->dev);
+ struct mba_data *mba = platform_get_drvdata(pdev);
+ unsigned long start_addr = pil_get_entry_addr(pil);
int ret;
/* Deassert reset to subsystem and wait for propagation */
@@ -188,12 +230,12 @@
goto err_clks;
/* Program Image Address */
- if (drv->self_auth) {
- writel_relaxed(drv->start_addr, drv->rmb_base + RMB_MBA_IMAGE);
+ if (mba->self_auth) {
+ writel_relaxed(start_addr, mba->rmb_base + RMB_MBA_IMAGE);
/* Ensure write to RMB base occurs before reset is released. */
mb();
} else {
- writel_relaxed((drv->start_addr >> 4) & 0x0FFFFFF0,
+ writel_relaxed((start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
}
@@ -202,7 +244,7 @@
goto err_q6v5_reset;
/* Wait for MBA to start. Check for PBL and MBA errors while waiting. */
- if (drv->self_auth) {
+ if (mba->self_auth) {
ret = wait_for_mba_ready(drv);
if (ret)
goto err_auth;
@@ -223,84 +265,494 @@
}
static struct pil_reset_ops pil_mss_ops = {
- .init_image = pil_q6v5_init_image,
.proxy_vote = pil_q6v5_make_proxy_votes,
.proxy_unvote = pil_q6v5_remove_proxy_votes,
.auth_and_reset = pil_mss_reset,
.shutdown = pil_mss_shutdown,
};
-static int __devinit pil_mss_driver_probe(struct platform_device *pdev)
+static int pil_mba_make_proxy_votes(struct pil_desc *pil)
{
- struct q6v5_data *drv;
- struct pil_desc *desc;
+ int ret;
+ struct mba_data *drv = dev_get_drvdata(pil->dev);
+
+ ret = clk_prepare_enable(drv->q6->xo);
+ if (ret) {
+ dev_err(pil->dev, "Failed to enable XO\n");
+ return ret;
+ }
+ return 0;
+}
+
+static void pil_mba_remove_proxy_votes(struct pil_desc *pil)
+{
+ struct mba_data *drv = dev_get_drvdata(pil->dev);
+ clk_disable_unprepare(drv->q6->xo);
+}
+
+static int pil_mba_init_image(struct pil_desc *pil,
+ const u8 *metadata, size_t size)
+{
+ struct mba_data *drv = dev_get_drvdata(pil->dev);
+ s32 status;
+ int ret;
+
+ /* Copy metadata to assigned shared buffer location */
+ memcpy(drv->metadata_base, metadata, size);
+
+ /* Initialize length counter to 0 */
+ writel_relaxed(0, drv->rmb_base + RMB_PMI_CODE_LENGTH);
+ drv->img_length = 0;
+
+ /* Pass address of meta-data to the MBA and perform authentication */
+ writel_relaxed(drv->metadata_phys, drv->rmb_base + RMB_PMI_META_DATA);
+ writel_relaxed(CMD_META_DATA_READY, drv->rmb_base + RMB_MBA_COMMAND);
+ ret = readl_poll_timeout(drv->rmb_base + RMB_MBA_STATUS, status,
+ status == STATUS_META_DATA_AUTH_SUCCESS || status < 0,
+ POLL_INTERVAL_US, modem_auth_timeout_ms * 1000);
+ if (ret) {
+ dev_err(pil->dev, "MBA authentication of headers timed out\n");
+ } else if (status < 0) {
+ dev_err(pil->dev, "MBA returned error %d for headers\n",
+ status);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int pil_mba_verify_blob(struct pil_desc *pil, u32 phy_addr,
+ size_t size)
+{
+ struct mba_data *drv = dev_get_drvdata(pil->dev);
+ s32 status;
+
+ /* Begin image authentication */
+ if (drv->img_length == 0) {
+ writel_relaxed(phy_addr, drv->rmb_base + RMB_PMI_CODE_START);
+ writel_relaxed(CMD_LOAD_READY, drv->rmb_base + RMB_MBA_COMMAND);
+ }
+ /* Increment length counter */
+ drv->img_length += size;
+ writel_relaxed(drv->img_length, drv->rmb_base + RMB_PMI_CODE_LENGTH);
+
+ status = readl_relaxed(drv->rmb_base + RMB_MBA_STATUS);
+ if (status < 0) {
+ dev_err(pil->dev, "MBA returned error %d\n", status);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int pil_mba_auth(struct pil_desc *pil)
+{
+ struct mba_data *drv = dev_get_drvdata(pil->dev);
+ int ret;
+ s32 status;
+
+ /* Wait for all segments to be authenticated or an error to occur */
+ ret = readl_poll_timeout(drv->rmb_base + RMB_MBA_STATUS, status,
+ status == STATUS_AUTH_COMPLETE || status < 0,
+ 50, modem_auth_timeout_ms * 1000);
+ if (ret) {
+ dev_err(pil->dev, "MBA authentication of image timed out\n");
+ } else if (status < 0) {
+ dev_err(pil->dev, "MBA returned error %d for image\n", status);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static struct pil_reset_ops pil_mba_ops = {
+ .init_image = pil_mba_init_image,
+ .proxy_vote = pil_mba_make_proxy_votes,
+ .proxy_unvote = pil_mba_remove_proxy_votes,
+ .verify_blob = pil_mba_verify_blob,
+ .auth_and_reset = pil_mba_auth,
+};
+
+#define subsys_to_drv(d) container_of(d, struct mba_data, subsys_desc)
+
+static void log_modem_sfr(void)
+{
+ u32 size;
+ char *smem_reason, reason[MAX_SSR_REASON_LEN];
+
+ smem_reason = smem_get_entry(SMEM_SSR_REASON_MSS0, &size);
+ if (!smem_reason || !size) {
+ pr_err("modem subsystem failure reason: (unknown, smem_get_entry failed).\n");
+ return;
+ }
+ if (!smem_reason[0]) {
+ pr_err("modem subsystem failure reason: (unknown, empty string found).\n");
+ return;
+ }
+
+ strlcpy(reason, smem_reason, min(size, sizeof(reason)));
+ pr_err("modem subsystem failure reason: %s.\n", reason);
+
+ smem_reason[0] = '\0';
+ wmb();
+}
+
+static void restart_modem(struct mba_data *drv)
+{
+ log_modem_sfr();
+ drv->ignore_errors = true;
+ subsystem_restart_dev(drv->subsys);
+}
+
+static void smsm_state_cb(void *data, uint32_t old_state, uint32_t new_state)
+{
+ struct mba_data *drv = data;
+
+ /* Ignore if we're the one that set SMSM_RESET */
+ if (drv->crash_shutdown)
+ return;
+
+ if (new_state & SMSM_RESET) {
+ pr_err("Probable fatal error on the modem.\n");
+ restart_modem(drv);
+ }
+}
+
+static int modem_shutdown(const struct subsys_desc *subsys)
+{
+ struct mba_data *drv = subsys_to_drv(subsys);
+
+ if (!drv->is_loadable)
+ return -ENODEV;
+ /* MBA doesn't support shutdown */
+ pil_shutdown(&drv->q6->desc);
+ return 0;
+}
+
+static int modem_powerup(const struct subsys_desc *subsys)
+{
+ struct mba_data *drv = subsys_to_drv(subsys);
+ int ret;
+
+ if (!drv->is_loadable)
+ return -ENODEV;
+ /*
+ * At this time, the modem is shutdown. Therefore this function cannot
+ * run concurrently with either the watchdog bite error handler or the
+ * SMSM callback, making it safe to unset the flag below.
+ */
+ drv->ignore_errors = false;
+ ret = pil_boot(&drv->q6->desc);
+ if (ret)
+ return ret;
+ ret = pil_boot(&drv->desc);
+ if (ret)
+ pil_shutdown(&drv->q6->desc);
+ return ret;
+}
+
+static void modem_crash_shutdown(const struct subsys_desc *subsys)
+{
+ struct mba_data *drv = subsys_to_drv(subsys);
+ drv->crash_shutdown = true;
+ smsm_reset_modem(SMSM_RESET);
+}
+
+static struct ramdump_segment modem_segments[] = {
+ {0x08400000, 0x0D100000 - 0x08400000},
+};
+
+static struct ramdump_segment smem_segments[] = {
+ {0x0FA00000, 0x0FC00000 - 0x0FA00000},
+};
+
+static int modem_ramdump(int enable, const struct subsys_desc *subsys)
+{
+ struct mba_data *drv = subsys_to_drv(subsys);
+ int ret;
+
+ if (!enable)
+ return 0;
+
+ ret = pil_boot(&drv->q6->desc);
+ if (ret)
+ return ret;
+
+ ret = do_ramdump(drv->ramdump_dev, modem_segments,
+ ARRAY_SIZE(modem_segments));
+ if (ret < 0) {
+ pr_err("Unable to dump modem fw memory (rc = %d).\n", ret);
+ goto out;
+ }
+
+ ret = do_ramdump(drv->smem_ramdump_dev, smem_segments,
+ ARRAY_SIZE(smem_segments));
+ if (ret < 0) {
+ pr_err("Unable to dump smem memory (rc = %d).\n", ret);
+ goto out;
+ }
+
+out:
+ pil_shutdown(&drv->q6->desc);
+ return ret;
+}
+
+static int adsp_state_notifier_fn(struct notifier_block *this,
+ unsigned long code, void *ss_handle)
+{
+ int ret;
+ ret = sysmon_send_event(SYSMON_SS_MODEM, "adsp", code);
+ if (ret < 0)
+ pr_err("%s: sysmon_send_event failed (%d).", __func__, ret);
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block adsp_state_notifier_block = {
+ .notifier_call = adsp_state_notifier_fn,
+};
+
+static irqreturn_t modem_wdog_bite_irq(int irq, void *dev_id)
+{
+ struct mba_data *drv = dev_id;
+ if (drv->ignore_errors)
+ return IRQ_HANDLED;
+ pr_err("Watchdog bite received from modem software!\n");
+ restart_modem(drv);
+ return IRQ_HANDLED;
+}
+
+static int mss_start(const struct subsys_desc *desc)
+{
+ int ret;
+ struct mba_data *drv = subsys_to_drv(desc);
+
+ if (!drv->is_loadable)
+ return -ENODEV;
+
+ ret = pil_boot(&drv->q6->desc);
+ if (ret)
+ return ret;
+ ret = pil_boot(&drv->desc);
+ if (ret)
+ pil_shutdown(&drv->q6->desc);
+ return ret;
+}
+
+static void mss_stop(const struct subsys_desc *desc)
+{
+ struct mba_data *drv = subsys_to_drv(desc);
+
+ if (!drv->is_loadable)
+ return;
+
+ /* MBA doesn't support shutdown */
+ pil_shutdown(&drv->q6->desc);
+}
+
+static int __devinit pil_subsys_init(struct mba_data *drv,
+ struct platform_device *pdev)
+{
+ int irq, ret;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ drv->subsys_desc.name = "modem";
+ drv->subsys_desc.dev = &pdev->dev;
+ drv->subsys_desc.owner = THIS_MODULE;
+ drv->subsys_desc.shutdown = modem_shutdown;
+ drv->subsys_desc.powerup = modem_powerup;
+ drv->subsys_desc.ramdump = modem_ramdump;
+ drv->subsys_desc.crash_shutdown = modem_crash_shutdown;
+ drv->subsys_desc.start = mss_start;
+ drv->subsys_desc.stop = mss_stop;
+
+ drv->subsys = subsys_register(&drv->subsys_desc);
+ if (IS_ERR(drv->subsys)) {
+ ret = PTR_ERR(drv->subsys);
+ goto err_subsys;
+ }
+
+ drv->ramdump_dev = create_ramdump_device("modem", &pdev->dev);
+ if (!drv->ramdump_dev) {
+ pr_err("%s: Unable to create a modem ramdump device.\n",
+ __func__);
+ ret = -ENOMEM;
+ goto err_ramdump;
+ }
+
+ drv->smem_ramdump_dev = create_ramdump_device("smem-modem", &pdev->dev);
+ if (!drv->smem_ramdump_dev) {
+ pr_err("%s: Unable to create an smem ramdump device.\n",
+ __func__);
+ ret = -ENOMEM;
+ goto err_ramdump_smem;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, modem_wdog_bite_irq,
+ IRQF_TRIGGER_RISING, "modem_wdog", drv);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Unable to request watchdog IRQ.\n");
+ goto err_irq;
+ }
+
+ ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
+ smsm_state_cb, drv);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Unable to register SMSM callback!\n");
+ goto err_irq;
+ }
+
+ drv->adsp_state_notifier = subsys_notif_register_notifier("adsp",
+ &adsp_state_notifier_block);
+ if (IS_ERR(drv->adsp_state_notifier)) {
+ ret = PTR_ERR(drv->adsp_state_notifier);
+ dev_err(&pdev->dev, "%s: Registration with the SSR notification driver failed (%d)",
+ __func__, ret);
+ goto err_smsm;
+ }
+
+ return 0;
+
+err_smsm:
+ smsm_state_cb_deregister(SMSM_MODEM_STATE, SMSM_RESET, smsm_state_cb,
+ drv);
+err_irq:
+ destroy_ramdump_device(drv->smem_ramdump_dev);
+err_ramdump_smem:
+ destroy_ramdump_device(drv->ramdump_dev);
+err_ramdump:
+ subsys_unregister(drv->subsys);
+err_subsys:
+ return ret;
+}
+
+static int __devinit pil_mss_loadable_init(struct mba_data *drv,
+ struct platform_device *pdev)
+{
+ struct q6v5_data *q6;
+ struct pil_desc *q6_desc, *mba_desc;
struct resource *res;
int ret;
- drv = pil_q6v5_init(pdev);
- if (IS_ERR(drv))
- return PTR_ERR(drv);
- platform_set_drvdata(pdev, drv);
+ q6 = pil_q6v5_init(pdev);
+ if (IS_ERR(q6))
+ return PTR_ERR(q6);
+ drv->q6 = q6;
- desc = &drv->desc;
- desc->ops = &pil_mss_ops;
- desc->owner = THIS_MODULE;
- desc->proxy_timeout = PROXY_TIMEOUT_MS;
+ q6_desc = &q6->desc;
+ q6_desc->ops = &pil_mss_ops;
+ q6_desc->owner = THIS_MODULE;
+ q6_desc->proxy_timeout = PROXY_TIMEOUT_MS;
of_property_read_u32(pdev->dev.of_node, "qcom,pil-self-auth",
&drv->self_auth);
if (drv->self_auth) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"rmb_base");
- drv->rmb_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->rmb_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->rmb_base)
return -ENOMEM;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "metadata_base");
+ if (res) {
+ drv->metadata_base = devm_ioremap(&pdev->dev,
+ res->start, resource_size(res));
+ if (!drv->metadata_base)
+ return -ENOMEM;
+ drv->metadata_phys = res->start;
+ }
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg");
- drv->restart_reg = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!drv->restart_reg)
+ q6->restart_reg = devm_request_and_ioremap(&pdev->dev, res);
+ if (!q6->restart_reg)
return -ENOMEM;
- drv->vreg = devm_regulator_get(&pdev->dev, "vdd_mss");
- if (IS_ERR(drv->vreg))
- return PTR_ERR(drv->vreg);
+ q6->vreg = devm_regulator_get(&pdev->dev, "vdd_mss");
+ if (IS_ERR(q6->vreg))
+ return PTR_ERR(q6->vreg);
- ret = regulator_set_voltage(drv->vreg, 1050000, 1050000);
+ ret = regulator_set_voltage(q6->vreg, 1050000, 1050000);
if (ret)
dev_err(&pdev->dev, "Failed to set regulator's voltage.\n");
- ret = regulator_set_optimum_mode(drv->vreg, 100000);
+ ret = regulator_set_optimum_mode(q6->vreg, 100000);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to set regulator's mode.\n");
return ret;
}
- drv->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
- if (IS_ERR(drv->ahb_clk))
- return PTR_ERR(drv->ahb_clk);
+ q6->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
+ if (IS_ERR(q6->ahb_clk))
+ return PTR_ERR(q6->ahb_clk);
- drv->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
- if (IS_ERR(drv->axi_clk))
- return PTR_ERR(drv->axi_clk);
+ q6->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ if (IS_ERR(q6->axi_clk))
+ return PTR_ERR(q6->axi_clk);
- drv->rom_clk = devm_clk_get(&pdev->dev, "mem_clk");
- if (IS_ERR(drv->rom_clk))
- return PTR_ERR(drv->rom_clk);
+ q6->rom_clk = devm_clk_get(&pdev->dev, "mem_clk");
+ if (IS_ERR(q6->rom_clk))
+ return PTR_ERR(q6->rom_clk);
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(q6_desc);
+ if (ret)
+ return ret;
+
+ mba_desc = &drv->desc;
+ mba_desc->name = "modem";
+ mba_desc->dev = &pdev->dev;
+ mba_desc->ops = &pil_mba_ops;
+ mba_desc->owner = THIS_MODULE;
+ mba_desc->proxy_timeout = PROXY_TIMEOUT_MS;
+
+ ret = pil_desc_init(mba_desc);
+ if (ret)
+ goto err_mba_desc;
return 0;
+
+err_mba_desc:
+ pil_desc_release(q6_desc);
+ return ret;
+
+}
+
+static int __devinit pil_mss_driver_probe(struct platform_device *pdev)
+{
+ struct mba_data *drv;
+ int ret;
+
+ drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, drv);
+
+ drv->is_loadable = of_property_read_bool(pdev->dev.of_node,
+ "qcom,is-loadable");
+ if (drv->is_loadable) {
+ ret = pil_mss_loadable_init(drv, pdev);
+ if (ret)
+ return ret;
+ }
+
+ return pil_subsys_init(drv, pdev);
}
static int __devexit pil_mss_driver_exit(struct platform_device *pdev)
{
- struct q6v5_data *drv = platform_get_drvdata(pdev);
- msm_pil_unregister(drv->pil);
+ struct mba_data *drv = platform_get_drvdata(pdev);
+
+ subsys_notif_unregister_notifier(drv->adsp_state_notifier,
+ &adsp_state_notifier_block);
+ smsm_state_cb_deregister(SMSM_MODEM_STATE, SMSM_RESET,
+ smsm_state_cb, drv);
+ subsys_unregister(drv->subsys);
+ destroy_ramdump_device(drv->smem_ramdump_dev);
+ destroy_ramdump_device(drv->ramdump_dev);
+ pil_desc_release(&drv->desc);
+ pil_desc_release(&drv->q6->desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index 70a12de..ab88749 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -16,7 +16,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
-#include <linux/elf.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/clk.h>
@@ -100,16 +99,6 @@
}
EXPORT_SYMBOL(pil_q6v5_halt_axi_port);
-int pil_q6v5_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-EXPORT_SYMBOL(pil_q6v5_init_image);
-
void pil_q6v5_shutdown(struct pil_desc *pil)
{
u32 val;
@@ -205,12 +194,10 @@
return ERR_PTR(-ENOMEM);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6_base");
- if (!res)
- return ERR_PTR(-EINVAL);
- drv->reg_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->reg_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->reg_base)
return ERR_PTR(-ENOMEM);
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "halt_base");
drv->axi_halt_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
diff --git a/arch/arm/mach-msm/pil-q6v5.h b/arch/arm/mach-msm/pil-q6v5.h
index 7304757..ecdaf9b 100644
--- a/arch/arm/mach-msm/pil-q6v5.h
+++ b/arch/arm/mach-msm/pil-q6v5.h
@@ -29,21 +29,15 @@
struct clk *reg_clk; /* CPU access registers */
struct clk *rom_clk; /* Boot ROM */
void __iomem *axi_halt_base;
- void __iomem *rmb_base;
void __iomem *restart_reg;
- unsigned long start_addr;
struct regulator *vreg;
bool is_booted;
- int self_auth;
- struct pil_device *pil;
struct pil_desc desc;
};
int pil_q6v5_make_proxy_votes(struct pil_desc *pil);
void pil_q6v5_remove_proxy_votes(struct pil_desc *pil);
void pil_q6v5_halt_axi_port(struct pil_desc *pil, void __iomem *halt_base);
-int pil_q6v5_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size);
void pil_q6v5_shutdown(struct pil_desc *pil);
int pil_q6v5_reset(struct pil_desc *pil);
struct q6v5_data *pil_q6v5_init(struct platform_device *pdev);
diff --git a/arch/arm/mach-msm/pil-riva.c b/arch/arm/mach-msm/pil-riva.c
index a0e39ea..7993090 100644
--- a/arch/arm/mach-msm/pil-riva.c
+++ b/arch/arm/mach-msm/pil-riva.c
@@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -23,9 +22,7 @@
#include <linux/interrupt.h>
#include <linux/wcnss_wlan.h>
-#include <mach/msm_iomap.h>
#include <mach/subsystem_restart.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
@@ -54,19 +51,18 @@
#define RIVA_PMU_CCPU_BOOT_REMAP_ADDR 0xA0
-#define RIVA_PLL_MODE (MSM_CLK_CTL_BASE + 0x31A0)
+#define RIVA_PLL_MODE 0x31A0
#define PLL_MODE_OUTCTRL BIT(0)
#define PLL_MODE_BYPASSNL BIT(1)
#define PLL_MODE_RESET_N BIT(2)
#define PLL_MODE_REF_XO_SEL 0x30
#define PLL_MODE_REF_XO_SEL_CXO (2 << 4)
#define PLL_MODE_REF_XO_SEL_RF (3 << 4)
-#define RIVA_PLL_L_VAL (MSM_CLK_CTL_BASE + 0x31A4)
-#define RIVA_PLL_M_VAL (MSM_CLK_CTL_BASE + 0x31A8)
-#define RIVA_PLL_N_VAL (MSM_CLK_CTL_BASE + 0x31Ac)
-#define RIVA_PLL_CONFIG (MSM_CLK_CTL_BASE + 0x31B4)
-#define RIVA_PLL_STATUS (MSM_CLK_CTL_BASE + 0x31B8)
-#define RIVA_RESET (MSM_CLK_CTL_BASE + 0x35E0)
+#define RIVA_PLL_L_VAL 0x31A4
+#define RIVA_PLL_M_VAL 0x31A8
+#define RIVA_PLL_N_VAL 0x31Ac
+#define RIVA_PLL_CONFIG 0x31B4
+#define RIVA_RESET 0x35E0
#define RIVA_PMU_ROOT_CLK_SEL 0xC8
#define RIVA_PMU_ROOT_CLK_SEL_3 BIT(2)
@@ -84,10 +80,10 @@
struct riva_data {
void __iomem *base;
- unsigned long start_addr;
+ void __iomem *cbase;
struct clk *xo;
struct regulator *pll_supply;
- struct pil_device *pil;
+ struct pil_desc pil_desc;
int irq;
int crash;
int rst_in_progress;
@@ -133,21 +129,13 @@
clk_disable_unprepare(drv->xo);
}
-static int pil_riva_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- struct riva_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
- return 0;
-}
-
static int pil_riva_reset(struct pil_desc *pil)
{
u32 reg, sel;
struct riva_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
- unsigned long start_addr = drv->start_addr;
+ unsigned long start_addr = pil_get_entry_addr(pil);
+ void __iomem *cbase = drv->cbase;
bool use_cxo = cxo_is_needed(drv);
/* Enable A2XB bridge */
@@ -156,26 +144,26 @@
writel_relaxed(reg, base + RIVA_PMU_A2XB_CFG);
/* Program PLL 13 to 960 MHz */
- reg = readl_relaxed(RIVA_PLL_MODE);
+ reg = readl_relaxed(cbase + RIVA_PLL_MODE);
reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
- writel_relaxed(reg, RIVA_PLL_MODE);
+ writel_relaxed(reg, cbase + RIVA_PLL_MODE);
if (use_cxo)
- writel_relaxed(0x40000C00 | 50, RIVA_PLL_L_VAL);
+ writel_relaxed(0x40000C00 | 50, cbase + RIVA_PLL_L_VAL);
else
- writel_relaxed(0x40000C00 | 40, RIVA_PLL_L_VAL);
- writel_relaxed(0, RIVA_PLL_M_VAL);
- writel_relaxed(1, RIVA_PLL_N_VAL);
- writel_relaxed(0x01495227, RIVA_PLL_CONFIG);
+ writel_relaxed(0x40000C00 | 40, cbase + RIVA_PLL_L_VAL);
+ writel_relaxed(0, cbase + RIVA_PLL_M_VAL);
+ writel_relaxed(1, cbase + RIVA_PLL_N_VAL);
+ writel_relaxed(0x01495227, cbase + RIVA_PLL_CONFIG);
- reg = readl_relaxed(RIVA_PLL_MODE);
+ reg = readl_relaxed(cbase + RIVA_PLL_MODE);
reg &= ~(PLL_MODE_REF_XO_SEL);
reg |= use_cxo ? PLL_MODE_REF_XO_SEL_CXO : PLL_MODE_REF_XO_SEL_RF;
- writel_relaxed(reg, RIVA_PLL_MODE);
+ writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/* Enable PLL 13 */
reg |= PLL_MODE_BYPASSNL;
- writel_relaxed(reg, RIVA_PLL_MODE);
+ writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/*
* H/W requires a 5us delay between disabling the bypass and
@@ -185,9 +173,9 @@
usleep_range(10, 20);
reg |= PLL_MODE_RESET_N;
- writel_relaxed(reg, RIVA_PLL_MODE);
+ writel_relaxed(reg, cbase + RIVA_PLL_MODE);
reg |= PLL_MODE_OUTCTRL;
- writel_relaxed(reg, RIVA_PLL_MODE);
+ writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/* Wait for PLL to settle */
mb();
@@ -241,20 +229,22 @@
static int pil_riva_shutdown(struct pil_desc *pil)
{
+ struct riva_data *drv = dev_get_drvdata(pil->dev);
+ void __iomem *cbase = drv->cbase;
+
/* Assert reset to Riva */
- writel_relaxed(1, RIVA_RESET);
+ writel_relaxed(1, cbase + RIVA_RESET);
mb();
usleep_range(1000, 2000);
/* Deassert reset to Riva */
- writel_relaxed(0, RIVA_RESET);
+ writel_relaxed(0, cbase + RIVA_RESET);
mb();
return 0;
}
static struct pil_reset_ops pil_riva_ops = {
- .init_image = pil_riva_init_image,
.auth_and_reset = pil_riva_reset,
.shutdown = pil_riva_shutdown,
.proxy_vote = pil_riva_make_proxy_vote,
@@ -374,15 +364,10 @@
static int riva_start(const struct subsys_desc *desc)
{
- void *ret;
struct riva_data *drv;
drv = container_of(desc, struct riva_data, subsys_desc);
-
- ret = pil_get("wcnss");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->pil_desc);
}
static void riva_stop(const struct subsys_desc *desc)
@@ -390,7 +375,7 @@
struct riva_data *drv;
drv = container_of(desc, struct riva_data, subsys_desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int riva_shutdown(const struct subsys_desc *desc)
@@ -398,7 +383,7 @@
struct riva_data *drv;
drv = container_of(desc, struct riva_data, subsys_desc);
- pil_force_shutdown("wcnss");
+ pil_shutdown(&drv->pil_desc);
flush_delayed_work(&drv->cancel_work);
wcnss_flush_delayed_boot_votes();
disable_irq_nosync(drv->irq);
@@ -418,7 +403,7 @@
ret = wcnss_wlan_power(&pdev->dev, pwlanconfig,
WCNSS_WLAN_SWITCH_ON);
if (!ret)
- pil_force_boot("wcnss");
+ pil_boot(&drv->pil_desc);
}
drv->rst_in_progress = 0;
enable_irq(drv->irq);
@@ -467,21 +452,20 @@
struct pil_desc *desc;
int ret;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
platform_set_drvdata(pdev, drv);
- drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ drv->base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->base)
return -ENOMEM;
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ drv->cbase = devm_request_and_ioremap(&pdev->dev, res);
+ if (!drv->cbase)
return -ENOMEM;
drv->pll_supply = devm_regulator_get(&pdev->dev, "pll_vdd");
@@ -509,6 +493,11 @@
if (drv->irq < 0)
return drv->irq;
+ drv->xo = devm_clk_get(&pdev->dev, "cxo");
+ if (IS_ERR(drv->xo))
+ return PTR_ERR(drv->xo);
+
+ desc = &drv->pil_desc;
desc->name = "wcnss";
desc->dev = &pdev->dev;
desc->owner = THIS_MODULE;
@@ -521,14 +510,7 @@
desc->ops = &pil_riva_ops;
dev_info(&pdev->dev, "using non-secure boot\n");
}
-
- drv->xo = devm_clk_get(&pdev->dev, "cxo");
- if (IS_ERR(drv->xo))
- return PTR_ERR(drv->xo);
-
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
ret = smsm_state_cb_register(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
@@ -547,7 +529,7 @@
INIT_DELAYED_WORK(&drv->cancel_work, riva_post_bootup);
- drv->ramdump_dev = create_ramdump_device("riva");
+ drv->ramdump_dev = create_ramdump_device("riva", &pdev->dev);
if (!drv->ramdump_dev) {
ret = -ENOMEM;
goto err_ramdump;
@@ -573,7 +555,7 @@
smsm_state_cb_deregister(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
err_smsm:
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return ret;
}
@@ -585,7 +567,7 @@
destroy_ramdump_device(drv->ramdump_dev);
smsm_state_cb_deregister(SMSM_WCNSS_STATE, SMSM_RESET,
smsm_state_cb_hdlr, drv);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-tzapps.c b/arch/arm/mach-msm/pil-tzapps.c
index be78fab..8658e6e 100644
--- a/arch/arm/mach-msm/pil-tzapps.c
+++ b/arch/arm/mach-msm/pil-tzapps.c
@@ -13,17 +13,15 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/elf.h>
#include <linux/err.h>
-#include <mach/peripheral-loader.h>
#include <mach/subsystem_restart.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
struct tzapps_data {
- struct pil_device *pil;
+ struct pil_desc pil_desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
};
@@ -54,44 +52,39 @@
static int tzapps_start(const struct subsys_desc *desc)
{
- void *ret;
+ struct tzapps_data *drv = subsys_to_drv(desc);
- ret = pil_get("tzapps");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->pil_desc);
}
static void tzapps_stop(const struct subsys_desc *desc)
{
struct tzapps_data *drv = subsys_to_drv(desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int __devinit pil_tzapps_driver_probe(struct platform_device *pdev)
{
struct pil_desc *desc;
struct tzapps_data *drv;
+ int ret;
if (pas_supported(PAS_TZAPPS) < 0)
return -ENOSYS;
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
platform_set_drvdata(pdev, drv);
+ desc = &drv->pil_desc;
desc->name = "tzapps";
desc->dev = &pdev->dev;
desc->ops = &pil_tzapps_ops;
desc->owner = THIS_MODULE;
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
drv->subsys_desc.name = "tzapps";
drv->subsys_desc.dev = &pdev->dev;
@@ -101,7 +94,7 @@
drv->subsys = subsys_register(&drv->subsys_desc);
if (IS_ERR(drv->subsys)) {
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return PTR_ERR(drv->subsys);
}
return 0;
@@ -111,7 +104,7 @@
{
struct tzapps_data *drv = platform_get_drvdata(pdev);
subsys_unregister(drv->subsys);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-venus.c b/arch/arm/mach-msm/pil-venus.c
index e3125cf..47799cc 100644
--- a/arch/arm/mach-msm/pil-venus.c
+++ b/arch/arm/mach-msm/pil-venus.c
@@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/elf.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -29,7 +28,6 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/subsystem_restart.h>
-#include <mach/peripheral-loader.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
@@ -67,11 +65,10 @@
struct venus_data {
void __iomem *venus_wrapper_base;
void __iomem *venus_vbif_base;
- struct pil_device *pil;
+ struct pil_desc desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
struct regulator *gdsc;
- phys_addr_t start_addr;
struct clk *clks[ARRAY_SIZE(clk_names)];
struct device *iommu_fw_ctx;
struct iommu_domain *iommu_fw_domain;
@@ -184,22 +181,29 @@
regulator_disable(drv->gdsc);
}
-static int pil_venus_init_image(struct pil_desc *pil, const u8 *metadata,
- size_t size)
+static int pil_venus_mem_setup(struct pil_desc *pil, phys_addr_t addr,
+ size_t size)
{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
+ int domain;
struct venus_data *drv = dev_get_drvdata(pil->dev);
- drv->start_addr = ehdr->e_entry;
-
- if (drv->start_addr < drv->fw_min_paddr ||
- drv->start_addr >= drv->fw_max_paddr) {
- dev_err(pil->dev, "fw start addr is not within valid range\n");
- return -EINVAL;
+ /* TODO: unregister? */
+ if (!drv->venus_domain_num) {
+ size = round_up(size, SZ_4K);
+ domain = venus_register_domain(size);
+ if (domain < 0) {
+ dev_err(pil->dev, "Venus fw iommu domain register failed\n");
+ return -ENODEV;
+ }
+ drv->iommu_fw_domain = msm_get_iommu_domain(domain);
+ if (!drv->iommu_fw_domain) {
+ dev_err(pil->dev, "No iommu fw domain found\n");
+ return -ENODEV;
+ }
+ drv->venus_domain_num = domain;
+ drv->fw_sz = size;
}
- drv->fw_sz = drv->fw_max_paddr - drv->start_addr;
-
return 0;
}
@@ -208,7 +212,7 @@
int rc;
struct venus_data *drv = dev_get_drvdata(pil->dev);
void __iomem *wrapper_base = drv->venus_wrapper_base;
- phys_addr_t pa = drv->start_addr;
+ phys_addr_t pa = pil_get_entry_addr(pil);
unsigned long iova;
/*
@@ -327,7 +331,7 @@
}
static struct pil_reset_ops pil_venus_ops = {
- .init_image = pil_venus_init_image,
+ .mem_setup = pil_venus_mem_setup,
.auth_and_reset = pil_venus_reset,
.shutdown = pil_venus_shutdown,
.proxy_vote = pil_venus_make_proxy_vote,
@@ -389,19 +393,15 @@
static int venus_start(const struct subsys_desc *desc)
{
- void *ret;
struct venus_data *drv = subsys_to_drv(desc);
- ret = pil_get(drv->subsys_desc.name);
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ return pil_boot(&drv->desc);
}
static void venus_stop(const struct subsys_desc *desc)
{
struct venus_data *drv = subsys_to_drv(desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->desc);
}
static int __devinit pil_venus_probe(struct platform_device *pdev)
@@ -411,27 +411,20 @@
struct pil_desc *desc;
int rc;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "wrapper_base");
- if (!res)
- return -EINVAL;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
platform_set_drvdata(pdev, drv);
- drv->venus_wrapper_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "wrapper_base");
+ drv->venus_wrapper_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->venus_wrapper_base)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vbif_base");
- if (!res)
- return -EINVAL;
-
- drv->venus_vbif_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ drv->venus_vbif_base = devm_request_and_ioremap(&pdev->dev, res);
if (!drv->venus_vbif_base)
return -ENOMEM;
@@ -451,45 +444,7 @@
return -ENODEV;
}
- /* Get fw address boundaries */
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,firmware-max-paddr",
- &drv->fw_max_paddr);
- if (rc) {
- dev_err(&pdev->dev, "Failed to get fw max paddr\n");
- return rc;
- }
-
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,firmware-min-paddr",
- &drv->fw_min_paddr);
- if (rc) {
- dev_err(&pdev->dev, "Failed to get fw min paddr\n");
- return rc;
- }
-
- if (drv->fw_max_paddr <= drv->fw_min_paddr) {
- dev_err(&pdev->dev, "Invalid fw max paddr or min paddr\n");
- return -EINVAL;
- }
-
- drv->venus_domain_num =
- venus_register_domain(drv->fw_max_paddr - drv->fw_min_paddr);
- if (drv->venus_domain_num < 0) {
- dev_err(&pdev->dev, "Venus fw iommu domain register failed\n");
- return -ENODEV;
- }
-
- drv->iommu_fw_domain = msm_get_iommu_domain(drv->venus_domain_num);
- if (!drv->iommu_fw_domain) {
- dev_err(&pdev->dev, "No iommu fw domain found\n");
- return -ENODEV;
- }
-
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
+ desc = &drv->desc;
rc = of_property_read_string(pdev->dev.of_node, "qcom,firmware-name",
&desc->name);
if (rc)
@@ -507,9 +462,9 @@
dev_info(&pdev->dev, "using non-secure boot\n");
}
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ rc = pil_desc_init(desc);
+ if (rc)
+ return rc;
drv->subsys_desc.name = desc->name;
drv->subsys_desc.owner = THIS_MODULE;
@@ -519,7 +474,7 @@
drv->subsys = subsys_register(&drv->subsys_desc);
if (IS_ERR(drv->subsys)) {
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return PTR_ERR(drv->subsys);
}
@@ -530,7 +485,7 @@
{
struct venus_data *drv = platform_get_drvdata(pdev);
subsys_unregister(drv->subsys);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->desc);
return 0;
}
diff --git a/arch/arm/mach-msm/pil-vidc.c b/arch/arm/mach-msm/pil-vidc.c
index b2609b1..42bb51c 100644
--- a/arch/arm/mach-msm/pil-vidc.c
+++ b/arch/arm/mach-msm/pil-vidc.c
@@ -13,11 +13,9 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/elf.h>
#include <linux/err.h>
#include <linux/clk.h>
-#include <mach/peripheral-loader.h>
#include <mach/subsystem_restart.h>
#include "peripheral-loader.h"
@@ -26,7 +24,7 @@
struct vidc_data {
struct clk *smmu_iface;
struct clk *core;
- struct pil_device *pil;
+ struct pil_desc pil_desc;
struct subsys_device *subsys;
struct subsys_desc subsys_desc;
};
@@ -72,32 +70,25 @@
static int vidc_start(const struct subsys_desc *desc)
{
- void *ret;
-
- ret = pil_get("vidc");
- if (IS_ERR(ret))
- return PTR_ERR(ret);
- return 0;
+ struct vidc_data *drv = subsys_to_drv(desc);
+ return pil_boot(&drv->pil_desc);
}
static void vidc_stop(const struct subsys_desc *desc)
{
struct vidc_data *drv = subsys_to_drv(desc);
- pil_put(drv->pil);
+ pil_shutdown(&drv->pil_desc);
}
static int __devinit pil_vidc_driver_probe(struct platform_device *pdev)
{
struct pil_desc *desc;
struct vidc_data *drv;
+ int ret;
if (pas_supported(PAS_VIDC) < 0)
return -ENOSYS;
- desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
return -ENOMEM;
@@ -111,13 +102,14 @@
if (IS_ERR(drv->core))
return PTR_ERR(drv->core);
+ desc = &drv->pil_desc;
desc->name = "vidc";
desc->dev = &pdev->dev;
desc->ops = &pil_vidc_ops;
desc->owner = THIS_MODULE;
- drv->pil = msm_pil_register(desc);
- if (IS_ERR(drv->pil))
- return PTR_ERR(drv->pil);
+ ret = pil_desc_init(desc);
+ if (ret)
+ return ret;
drv->subsys_desc.name = "vidc";
drv->subsys_desc.dev = &pdev->dev;
@@ -127,7 +119,7 @@
drv->subsys = subsys_register(&drv->subsys_desc);
if (IS_ERR(drv->subsys)) {
- msm_pil_unregister(drv->pil);
+ pil_desc_release(desc);
return PTR_ERR(drv->subsys);
}
return 0;
@@ -137,7 +129,7 @@
{
struct vidc_data *drv = platform_get_drvdata(pdev);
subsys_unregister(drv->subsys);
- msm_pil_unregister(drv->pil);
+ pil_desc_release(&drv->pil_desc);
return 0;
}
diff --git a/arch/arm/mach-msm/platsmp-8910.c b/arch/arm/mach-msm/platsmp-8910.c
index 5d055bd..af2f496 100644
--- a/arch/arm/mach-msm/platsmp-8910.c
+++ b/arch/arm/mach-msm/platsmp-8910.c
@@ -32,7 +32,7 @@
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
-volatile int __cpuinitdata pen_release = -1;
+volatile int pen_release = -1;
/*
* Write pen_release in a way that is guaranteed to be visible to all
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index f55d509..550bb56 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -35,7 +35,7 @@
#include <asm/hardware/gic.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
-#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
#ifdef CONFIG_VFP
#include <asm/vfp.h>
#endif
@@ -51,7 +51,8 @@
#include "timer.h"
#include "pm-boot.h"
#include <mach/event_timer.h>
-
+#define CREATE_TRACE_POINTS
+#include "trace_msm_low_power.h"
/******************************************************************************
* Debug Definitions
*****************************************************************************/
@@ -114,6 +115,7 @@
"standalone_power_collapse",
};
+static struct msm_pm_init_data_type msm_pm_init_data;
static struct hrtimer pm_hrtimer;
static struct msm_pm_sleep_ops pm_sleep_ops;
/*
@@ -473,7 +475,6 @@
}
static void *msm_pm_idle_rs_limits;
-static bool msm_pm_use_qtimer;
static void msm_pm_swfi(void)
{
@@ -499,24 +500,6 @@
msm_pm_config_hw_after_retention();
}
-#ifdef CONFIG_CACHE_L2X0
-static inline bool msm_pm_l2x0_power_collapse(void)
-{
- bool collapsed = 0;
-
- l2cc_suspend();
- collapsed = msm_pm_collapse();
- l2cc_resume();
-
- return collapsed;
-}
-#else
-static inline bool msm_pm_l2x0_power_collapse(void)
-{
- return msm_pm_collapse();
-}
-#endif
-
static bool __ref msm_pm_spm_power_collapse(
unsigned int cpu, bool from_idle, bool notify_rpm)
{
@@ -547,7 +530,7 @@
#ifdef CONFIG_VFP
vfp_pm_suspend();
#endif
- collapsed = msm_pm_l2x0_power_collapse();
+ collapsed = msm_pm_collapse();
msm_pm_boot_config_after_pc(cpu);
@@ -576,11 +559,13 @@
{
unsigned int cpu = smp_processor_id();
unsigned int avsdscr_setting;
+ unsigned int avscsr_enable;
bool collapsed;
avsdscr_setting = avs_get_avsdscr();
- avs_disable();
+ avscsr_enable = avs_disable();
collapsed = msm_pm_spm_power_collapse(cpu, from_idle, false);
+ avs_enable(avscsr_enable);
avs_reset_delays(avsdscr_setting);
return collapsed;
}
@@ -590,6 +575,7 @@
unsigned int cpu = smp_processor_id();
unsigned long saved_acpuclk_rate;
unsigned int avsdscr_setting;
+ unsigned int avscsr_enable;
bool collapsed;
if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
@@ -601,7 +587,7 @@
pr_info("CPU%u: %s: pre power down\n", cpu, __func__);
avsdscr_setting = avs_get_avsdscr();
- avs_disable();
+ avscsr_enable = avs_disable();
if (cpu_online(cpu))
saved_acpuclk_rate = acpuclk_power_collapse();
@@ -643,6 +629,7 @@
}
+ avs_enable(avscsr_enable);
avs_reset_delays(avsdscr_setting);
msm_pm_config_hw_after_power_up();
if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
@@ -657,14 +644,11 @@
{
if (cpu_is_apq8064())
msm_pm_save_cp15 = true;
-
- if (cpu_is_msm8974())
- msm_pm_use_qtimer = true;
}
static int64_t msm_pm_timer_enter_idle(void)
{
- if (msm_pm_use_qtimer)
+ if (msm_pm_init_data.use_sync_timer)
return ktime_to_ns(tick_nohz_get_sleep_length());
return msm_timer_enter_idle();
@@ -672,7 +656,7 @@
static void msm_pm_timer_exit_idle(bool timer_halted)
{
- if (msm_pm_use_qtimer)
+ if (msm_pm_init_data.use_sync_timer)
return;
msm_timer_exit_idle((int) timer_halted);
@@ -682,7 +666,7 @@
{
int64_t time = 0;
- if (msm_pm_use_qtimer)
+ if (msm_pm_init_data.use_sync_timer)
return sched_clock();
time = msm_timer_get_sclk_time(period);
@@ -694,7 +678,7 @@
static int64_t msm_pm_timer_exit_suspend(int64_t time, int64_t period)
{
- if (msm_pm_use_qtimer)
+ if (msm_pm_init_data.use_sync_timer)
return sched_clock() - time;
if (time != 0) {
@@ -741,6 +725,51 @@
return;
}
+static inline void msm_pm_ftrace_lpm_enter(unsigned int cpu,
+ uint32_t latency, uint32_t sleep_us,
+ uint32_t wake_up,
+ enum msm_pm_sleep_mode mode)
+{
+ switch (mode) {
+ case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
+ trace_msm_pm_enter_wfi(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
+ trace_msm_pm_enter_spc(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
+ trace_msm_pm_enter_pc(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_RETENTION:
+ trace_msm_pm_enter_ret(cpu, latency, sleep_us, wake_up);
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void msm_pm_ftrace_lpm_exit(unsigned int cpu,
+ enum msm_pm_sleep_mode mode,
+ bool success)
+{
+ switch (mode) {
+ case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
+ trace_msm_pm_exit_wfi(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
+ trace_msm_pm_exit_spc(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
+ trace_msm_pm_exit_pc(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_RETENTION:
+ trace_msm_pm_exit_ret(cpu, success);
+ break;
+ default:
+ break;
+ }
+}
+
int msm_pm_idle_prepare(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
@@ -845,6 +874,11 @@
if (modified_time_us && !dev->cpu)
msm_pm_set_timer(modified_time_us);
+
+ msm_pm_ftrace_lpm_enter(dev->cpu, time_param.latency_us,
+ time_param.sleep_us, time_param.next_event_us,
+ ret);
+
return ret;
}
@@ -852,6 +886,7 @@
{
int64_t time;
int exit_stat;
+ bool collapsed = 1;
if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
pr_info("CPU%u: %s: mode %d\n",
@@ -871,7 +906,7 @@
break;
case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- msm_pm_power_collapse_standalone(true);
+ collapsed = msm_pm_power_collapse_standalone(true);
exit_stat = MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE;
break;
@@ -882,8 +917,6 @@
int ret = -ENODEV;
int notify_rpm =
(sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE);
- int collapsed;
-
timer_expiration = msm_pm_timer_enter_idle();
sleep_delay = (uint32_t) msm_pm_convert_and_cap_time(
@@ -918,6 +951,8 @@
time = ktime_to_ns(ktime_get()) - time;
msm_pm_add_stat(exit_stat, time);
+ msm_pm_ftrace_lpm_exit(smp_processor_id(), sleep_mode,
+ collapsed);
do_div(time, 1000);
return (int) time;
@@ -1165,3 +1200,73 @@
}
late_initcall(msm_pm_init);
+
+static void __devinit msm_pm_set_flush_fn(uint32_t pc_mode)
+{
+ msm_pm_disable_l2_fn = NULL;
+ msm_pm_enable_l2_fn = NULL;
+ msm_pm_flush_l2_fn = outer_flush_all;
+
+ if (pc_mode == MSM_PM_PC_NOTZ_L2_EXT) {
+ msm_pm_disable_l2_fn = outer_disable;
+ msm_pm_enable_l2_fn = outer_resume;
+ }
+}
+
+static int __devinit msm_pm_8x60_probe(struct platform_device *pdev)
+{
+ char *key = NULL;
+ uint32_t val = 0;
+ int ret = 0;
+
+ if (!pdev->dev.of_node) {
+ struct msm_pm_init_data_type *d = pdev->dev.platform_data;
+
+ if (!d)
+ goto pm_8x60_probe_done;
+
+ msm_pm_init_data.pc_mode = d->pc_mode;
+ msm_pm_set_flush_fn(msm_pm_init_data.pc_mode);
+ msm_pm_init_data.use_sync_timer = d->use_sync_timer;
+ } else {
+ key = "qcom,pc-mode";
+ ret = of_property_read_u32(pdev->dev.of_node, key, &val);
+
+ if (ret) {
+ pr_debug("%s: Cannot read %s,defaulting to 0",
+ __func__, key);
+ val = MSM_PM_PC_TZ_L2_INT;
+ ret = 0;
+ }
+
+ msm_pm_init_data.pc_mode = val;
+ msm_pm_set_flush_fn(msm_pm_init_data.pc_mode);
+
+ key = "qcom,use-sync-timer";
+ msm_pm_init_data.use_sync_timer =
+ of_property_read_bool(pdev->dev.of_node, key);
+ }
+
+pm_8x60_probe_done:
+ return ret;
+}
+
+static struct of_device_id msm_pm_8x60_table[] = {
+ {.compatible = "qcom,pm-8x60"},
+ {},
+};
+
+static struct platform_driver msm_pm_8x60_driver = {
+ .probe = msm_pm_8x60_probe,
+ .driver = {
+ .name = "pm-8x60",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_pm_8x60_table,
+ },
+};
+
+static int __init msm_pm_8x60_init(void)
+{
+ return platform_driver_register(&msm_pm_8x60_driver);
+}
+module_init(msm_pm_8x60_init);
diff --git a/arch/arm/mach-msm/pm-boot.c b/arch/arm/mach-msm/pm-boot.c
index 7bc4fe0..f32e149 100644
--- a/arch/arm/mach-msm/pm-boot.c
+++ b/arch/arm/mach-msm/pm-boot.c
@@ -158,13 +158,17 @@
msm_pm_boot_after_pc
= msm_pm_config_rst_vector_after_pc;
} else {
+ uint32_t mpa5_boot_remap_addr[2] = {0x34, 0x4C};
+ uint32_t mpa5_cfg_ctl[2] = {0x30, 0x48};
+
warm_boot_ptr = ioremap_nocache(
MSM8625_WARM_BOOT_PHYS, SZ_64);
ret = msm_pm_boot_reset_vector_init(warm_boot_ptr);
entry = virt_to_phys(msm_pm_boot_entry);
- /* Below sequence is a work around for cores
+ /*
+ * Below sequence is a work around for cores
* to come out of GDFS properly on 8625 target.
* On 8625 while cores coming out of GDFS observed
* the memory corruption at very first memory read.
@@ -176,7 +180,8 @@
msm_pm_reset_vector[4] = 0xE12FFF10; /* bx r0 */
msm_pm_reset_vector[5] = entry; /* 0x14 */
- /* Here upper 16bits[16:31] used by CORE1
+ /*
+ * Here upper 16bits[16:31] used by CORE1
* lower 16bits[0:15] used by CORE0
*/
entry = (MSM8625_WARM_BOOT_PHYS |
@@ -184,17 +189,30 @@
/* write 'entry' to boot remapper register */
__raw_writel(entry, (pdata->v_addr +
- MPA5_BOOT_REMAP_ADDR));
+ mpa5_boot_remap_addr[0]));
- /* Enable boot remapper for C0 [bit:25th] */
+ /*
+ * Enable boot remapper for C0 [bit:25th]
+ * Enable boot remapper for C1 [bit:26th]
+ */
__raw_writel(readl_relaxed(pdata->v_addr +
- MPA5_CFG_CTL_REG) | BIT(25),
- pdata->v_addr + MPA5_CFG_CTL_REG);
+ mpa5_cfg_ctl[0]) | (0x3 << 25),
+ pdata->v_addr + mpa5_cfg_ctl[0]);
- /* Enable boot remapper for C1 [bit:26th] */
- __raw_writel(readl_relaxed(pdata->v_addr +
- MPA5_CFG_CTL_REG) | BIT(26),
- pdata->v_addr + MPA5_CFG_CTL_REG);
+ /* 8x25Q changes */
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
+ /* write 'entry' to boot remapper register */
+ __raw_writel(entry, (pdata->v_addr +
+ mpa5_boot_remap_addr[1]));
+
+ /*
+ * Enable boot remapper for C2 [bit:25th]
+ * Enable boot remapper for C3 [bit:26th]
+ */
+ __raw_writel(readl_relaxed(pdata->v_addr +
+ mpa5_cfg_ctl[1]) | (0x3 << 25),
+ pdata->v_addr + mpa5_cfg_ctl[1]);
+ }
msm_pm_boot_before_pc = msm_pm_write_boot_vector;
}
break;
diff --git a/arch/arm/mach-msm/pm-boot.h b/arch/arm/mach-msm/pm-boot.h
index 30b67c21..e39ca75 100644
--- a/arch/arm/mach-msm/pm-boot.h
+++ b/arch/arm/mach-msm/pm-boot.h
@@ -15,7 +15,6 @@
/* 8x25 specific macros */
#define MPA5_CFG_CTL_REG 0x30
-#define MPA5_BOOT_REMAP_ADDR 0x34
/* end */
enum {
diff --git a/arch/arm/mach-msm/pm.h b/arch/arm/mach-msm/pm.h
index 51256ca..faefe34 100644
--- a/arch/arm/mach-msm/pm.h
+++ b/arch/arm/mach-msm/pm.h
@@ -87,6 +87,20 @@
bool notify_rpm, bool collapsed);
};
+enum msm_pm_pc_mode_type {
+ MSM_PM_PC_TZ_L2_INT = 0, /*Power collapse terminates in TZ;
+ integrated L2 cache controller */
+ MSM_PM_PC_NOTZ_L2_EXT = 1, /* Power collapse doesn't terminate in
+ TZ; external L2 cache controller */
+ MSM_PM_PC_TZ_L2_EXT = 2, /* Power collapse terminates in TZ;
+ external L2 cache controller */
+};
+
+struct msm_pm_init_data_type {
+ enum msm_pm_pc_mode_type pc_mode;
+ bool use_sync_timer;
+};
+
struct msm_pm_cpr_ops {
void (*cpr_suspend)(void);
void (*cpr_resume)(void);
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 427e39f..ae2a4bc 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -482,66 +482,71 @@
* Program the top csr from core0 context to put the
* core1 into GDFS, as core1 is not running yet.
*/
-static void configure_top_csr(void)
+static void msm_pm_configure_top_csr(void)
{
+ /*
+ * Enable TCSR for core
+ * Set reset bit for SPM
+ * Set CLK_OFF bit
+ * Set clamps bit
+ * Set power_up bit
+ * Disable TSCR for core
+ */
+ uint32_t bit_pos[][6] = {
+ /* c2 */
+ {17, 15, 13, 16, 14, 17},
+ /* c1 & c3*/
+ {22, 20, 18, 21, 19, 22},
+ };
+ uint32_t mpa5_cfg_ctl[2] = {0x30, 0x48};
void __iomem *base_ptr;
unsigned int value = 0;
+ unsigned int cpu;
+ int i;
- base_ptr = core_reset_base(1);
- if (!base_ptr)
- return;
-
- /* bring the core1 out of reset */
- __raw_writel(0x3, base_ptr);
- mb();
- /*
- * override DBGNOPOWERDN and program the GDFS
- * count val
- */
-
- __raw_writel(0x00030002, (MSM_CFG_CTL_BASE + 0x38));
- mb();
-
- /* Initialize the SPM0 and SPM1 registers */
+ /* Initialize all the SPM registers */
msm_spm_reinit();
- /* enable TCSR for core1 */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value |= BIT(22);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
+ for_each_possible_cpu(cpu) {
+ /* skip for C0 */
+ if (!cpu)
+ continue;
- /* set reset bit for SPM1 */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value |= BIT(20);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
+ base_ptr = core_reset_base(cpu);
+ if (!base_ptr)
+ return;
- /* set CLK_OFF bit */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value |= BIT(18);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
+ /* bring the core out of reset */
+ __raw_writel(0x3, base_ptr);
+ mb();
- /* set clamps bit */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value |= BIT(21);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
+ /*
+ * i == 0, Enable TCSR for core
+ * i == 1, Set reset bit for SPM
+ * i == 2, Set CLK_OFF bit
+ * i == 3, Set clamps bit
+ * i == 4, Set power_up bit
+ */
+ for (i = 0; i < 5; i++) {
+ value = __raw_readl(MSM_CFG_CTL_BASE +
+ mpa5_cfg_ctl[cpu/2]);
+ value |= BIT(bit_pos[cpu%2][i]);
+ __raw_writel(value, MSM_CFG_CTL_BASE +
+ mpa5_cfg_ctl[cpu/2]);
+ mb();
+ }
- /* set power_up bit */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value |= BIT(19);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
+ /* i == 5, Disable TCSR for core */
+ value = __raw_readl(MSM_CFG_CTL_BASE +
+ mpa5_cfg_ctl[cpu/2]);
+ value &= ~BIT(bit_pos[cpu%2][i]);
+ __raw_writel(value, MSM_CFG_CTL_BASE +
+ mpa5_cfg_ctl[cpu/2]);
+ mb();
- /* Disable TSCR for core0 */
- value = __raw_readl((MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG));
- value &= ~BIT(22);
- __raw_writel(value, MSM_CFG_CTL_BASE + MPA5_CFG_CTL_REG);
- mb();
- __raw_writel(0x0, base_ptr);
- mb();
+ __raw_writel(0x0, base_ptr);
+ mb();
+ }
}
/*
@@ -569,7 +574,7 @@
/*
* Program the top csr to put the core1 into GDFS.
*/
- configure_top_csr();
+ msm_pm_configure_top_csr();
}
} else {
__raw_writel(0, APPS_PWRDOWN);
@@ -981,17 +986,38 @@
/*
* on system reset, default value of MPA5_GDFS_CNT_VAL
* is = 0x0, later modem reprogram this value to
- * 0x00030004. Once APPS did a power collapse and
- * coming out of it expected value of this register
- * always be 0x00030004. Incase if APPS sees the value
- * as 0x00030002 consider this case as a modem early
- * exit.
+ * 0x00030004/0x000F0004(8x25Q). Once APPS did
+ * a power collapse and coming out of it expected value
+ * of this register always be 0x00030004/0x000F0004(8x25Q).
+ * Incase if APPS sees the value as 0x00030002/0x000F0002(8x25Q)
+ * consider this case as a modem early exit.
*/
val = __raw_readl(MSM_CFG_CTL_BASE + 0x38);
- if (val != 0x00030002)
- power_collapsed = 1;
- else
- modem_early_exit = 1;
+
+ /* 8x25Q */
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
+ if (val != 0x000F0002) {
+ power_collapsed = 1;
+ /*
+ * override DBGNOPOWERDN and program the GDFS
+ * count val
+ */
+ __raw_writel(0x000F0002,
+ (MSM_CFG_CTL_BASE + 0x38));
+ } else
+ modem_early_exit = 1;
+ } else {
+ if (val != 0x00030002) {
+ power_collapsed = 1;
+ /*
+ * override DBGNOPOWERDN and program the GDFS
+ * count val
+ */
+ __raw_writel(0x00030002,
+ (MSM_CFG_CTL_BASE + 0x38));
+ } else
+ modem_early_exit = 1;
+ }
}
#ifdef CONFIG_CACHE_L2X0
@@ -1684,12 +1710,16 @@
/*
* Configure the MPA5_GDFS_CNT_VAL register for
- * DBGPWRUPEREQ_OVERRIDE[17:16] = Override the
+ * DBGPWRUPEREQ_OVERRIDE[19:16] = Override the
* DBGNOPOWERDN for each cpu.
* MPA5_GDFS_CNT_VAL[9:0] = Delay counter for
* GDFS control.
*/
- val = 0x00030002;
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3)
+ val = 0x000F0002;
+ else
+ val = 0x00030002;
+
__raw_writel(val, (MSM_CFG_CTL_BASE + 0x38));
l2x0_base_addr = MSM_L2CC_BASE;
diff --git a/arch/arm/mach-msm/pmu.c b/arch/arm/mach-msm/pmu.c
index 5e339da..c426ff9 100644
--- a/arch/arm/mach-msm/pmu.c
+++ b/arch/arm/mach-msm/pmu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -11,8 +11,65 @@
*/
#include <linux/platform_device.h>
+#include <linux/irq.h>
#include <asm/pmu.h>
#include <mach/irqs.h>
+#include <mach/socinfo.h>
+
+#if defined(CONFIG_ARCH_MSM_KRAITMP) || defined(CONFIG_ARCH_MSM_SCORPIONMP) \
+ || defined(CONFIG_ARCH_MSM8625)
+static DEFINE_PER_CPU(u32, pmu_irq_cookie);
+
+static void enable_irq_callback(void *info)
+{
+ int irq = *(unsigned int *)info;
+ enable_percpu_irq(irq, IRQ_TYPE_EDGE_RISING);
+}
+
+static void disable_irq_callback(void *info)
+{
+ int irq = *(unsigned int *)info;
+ disable_percpu_irq(irq);
+}
+
+static int
+multicore_request_irq(int irq, irq_handler_t *handle_irq)
+{
+ int err = 0;
+ int cpu;
+
+ err = request_percpu_irq(irq, *handle_irq, "l1-armpmu",
+ &pmu_irq_cookie);
+
+ if (!err) {
+ for_each_cpu(cpu, cpu_online_mask) {
+ smp_call_function_single(cpu,
+ enable_irq_callback, &irq, 1);
+ }
+ }
+
+ return err;
+}
+
+static void
+multicore_free_irq(int irq)
+{
+ int cpu;
+
+ if (irq >= 0) {
+ for_each_cpu(cpu, cpu_online_mask) {
+ smp_call_function_single(cpu,
+ disable_irq_callback, &irq, 1);
+ }
+ free_percpu_irq(irq, &pmu_irq_cookie);
+ }
+}
+
+static struct arm_pmu_platdata multicore_data = {
+ .request_pmu_irq = multicore_request_irq,
+ .free_pmu_irq = multicore_free_irq,
+};
+#endif
static struct resource cpu_pmu_resource[] = {
{
@@ -47,6 +104,29 @@
.num_resources = ARRAY_SIZE(cpu_pmu_resource),
};
+/*
+ * The 8625 is a special case. Due to the requirement of a single
+ * kernel image for the 7x27a and 8625 (which share IRQ headers),
+ * this target breaks the uniformity of IRQ names.
+ * See the file - arch/arm/mach-msm/include/mach/irqs-8625.h
+ */
+#ifdef CONFIG_ARCH_MSM8625
+static struct resource msm8625_cpu_pmu_resource[] = {
+ {
+ .start = MSM8625_INT_ARMQC_PERFMON,
+ .end = MSM8625_INT_ARMQC_PERFMON,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device msm8625_cpu_pmu_device = {
+ .name = "cpu-arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .resource = msm8625_cpu_pmu_resource,
+ .num_resources = ARRAY_SIZE(msm8625_cpu_pmu_resource),
+};
+#endif
+
static struct platform_device *pmu_devices[] = {
&cpu_pmu_device,
#ifdef CONFIG_CPU_HAS_L2_PMU
@@ -56,6 +136,28 @@
static int __init msm_pmu_init(void)
{
+ /*
+ * For the targets we know are multicore's set the request/free IRQ
+ * handlers to call the percpu API.
+ * Defaults to unicore API {request,free}_irq().
+ * See arch/arm/kernel/perf_event.c
+ */
+#if defined(CONFIG_ARCH_MSM_KRAITMP) || defined(CONFIG_ARCH_MSM_SCORPIONMP)
+ cpu_pmu_device.dev.platform_data = &multicore_data;
+#endif
+
+ /*
+ * The 7x27a and 8625 require a single kernel image.
+ * So we need to check if we're on an 8625 at runtime
+ * and point to the appropriate 'struct resource'.
+ */
+#ifdef CONFIG_ARCH_MSM8625
+ if (cpu_is_msm8625()) {
+ pmu_devices[0] = &msm8625_cpu_pmu_device;
+ msm8625_cpu_pmu_device.dev.platform_data = &multicore_data;
+ }
+#endif
+
return platform_add_devices(pmu_devices, ARRAY_SIZE(pmu_devices));
}
diff --git a/arch/arm/mach-msm/qdsp5/audio_acdb.c b/arch/arm/mach-msm/qdsp5/audio_acdb.c
index 16f23f4..d7a4607 100644
--- a/arch/arm/mach-msm/qdsp5/audio_acdb.c
+++ b/arch/arm/mach-msm/qdsp5/audio_acdb.c
@@ -2575,6 +2575,7 @@
memset(&acdb_data, 0, sizeof(acdb_data));
spin_lock_init(&acdb_data.dsp_lock);
+ init_waitqueue_head(&acdb_data.wait);
acdb_data.cb_thread_task = kthread_run(acdb_calibrate_device,
NULL, "acdb_cb_thread");
@@ -2590,7 +2591,6 @@
MM_ERR("RTC ACDB=>INIT Failure\n");
#endif
- init_waitqueue_head(&acdb_data.wait);
return misc_register(&acdb_misc);
err:
diff --git a/arch/arm/mach-msm/qdsp6v2/Makefile b/arch/arm/mach-msm/qdsp6v2/Makefile
index 0f17a0b..66d6bda 100644
--- a/arch/arm/mach-msm/qdsp6v2/Makefile
+++ b/arch/arm/mach-msm/qdsp6v2/Makefile
@@ -27,4 +27,3 @@
obj-$(CONFIG_MSM_QDSP6V2_CODECS) += audio_mp3.o audio_amrnb.o audio_amrwb.o audio_evrc.o audio_qcelp.o amrwb_in.o
obj-$(CONFIG_MSM_ADSP_LOADER) += adsp-loader.o
obj-$(CONFIG_MSM_ULTRASOUND_A) += ultrasound/version_a/
-obj-m += adsprpc.o
diff --git a/arch/arm/mach-msm/qdsp6v2/adsp-loader.c b/arch/arm/mach-msm/qdsp6v2/adsp-loader.c
index 9924b52..c28e403 100644
--- a/arch/arm/mach-msm/qdsp6v2/adsp-loader.c
+++ b/arch/arm/mach-msm/qdsp6v2/adsp-loader.c
@@ -17,7 +17,7 @@
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include <mach/qdsp6v2/apr.h>
#define Q6_PIL_GET_DELAY_MS 100
@@ -37,7 +37,7 @@
platform_set_drvdata(pdev, priv);
- priv->pil_h = pil_get("adsp");
+ priv->pil_h = subsystem_get("adsp");
if (IS_ERR(priv->pil_h)) {
pr_err("%s: pil get adsp failed, error:%d\n", __func__, rc);
devm_kfree(&pdev->dev, priv);
@@ -62,7 +62,7 @@
struct adsp_loader_private *priv;
priv = platform_get_drvdata(pdev);
- pil_put(priv->pil_h);
+ subsystem_put(priv->pil_h);
pr_info("%s: Q6/ADSP image is unloaded\n", __func__);
return 0;
diff --git a/arch/arm/mach-msm/qdsp6v2/apr.c b/arch/arm/mach-msm/qdsp6v2/apr.c
index d494069..39bec8e 100644
--- a/arch/arm/mach-msm/qdsp6v2/apr.c
+++ b/arch/arm/mach-msm/qdsp6v2/apr.c
@@ -27,7 +27,7 @@
#include <linux/device.h>
#include <linux/slab.h>
#include <asm/mach-types.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include <mach/msm_smd.h>
#include <mach/qdsp6v2/apr.h>
#include <mach/qdsp6v2/apr_tal.h>
@@ -223,7 +223,7 @@
int rc = 0;
mutex_lock(&q6.lock);
if (apr_get_q6_state() == APR_SUBSYS_UP) {
- q6.pil = pil_get("q6");
+ q6.pil = subsystem_get("adsp");
if (IS_ERR(q6.pil)) {
rc = PTR_ERR(q6.pil);
pr_err("APR: Unable to load q6 image, error:%d\n", rc);
diff --git a/arch/arm/mach-msm/qdsp6v2/apr_v1.c b/arch/arm/mach-msm/qdsp6v2/apr_v1.c
index 011a73b..870bbb4 100644
--- a/arch/arm/mach-msm/qdsp6v2/apr_v1.c
+++ b/arch/arm/mach-msm/qdsp6v2/apr_v1.c
@@ -19,7 +19,6 @@
#include <mach/qdsp6v2/apr.h>
#include <mach/qdsp6v2/apr_tal.h>
#include <mach/qdsp6v2/dsp_debug.h>
-#include <mach/peripheral-loader.h>
static const char *lpass_subsys_name = "lpass";
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
index d6abdda..fb0ace7 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
@@ -779,6 +779,8 @@
__func__, audio, buf_node, buf_node->paddr,
buf_node->buf.data_len,
audio->buf_cfg.meta_info_enable);
+ pr_debug("%s[%p]: flags = 0x%x\n", __func__, audio,
+ buf_node->meta_info.meta_in.nflags);
ac = audio->ac;
/* Offset with appropriate meta */
@@ -798,6 +800,11 @@
param.flags = 0;
else
param.flags = 0xFF00;
+
+ if ((buf_node != NULL) &&
+ (buf_node->meta_info.meta_in.nflags & AUDIO_DEC_EOF_SET))
+ param.flags |= AUDIO_DEC_EOF_SET;
+
param.uid = param.paddr;
/* Read command will populate paddr as token */
buf_node->token = param.paddr;
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
index b2829c3..dedf991 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
@@ -36,6 +36,7 @@
#define ADRV_STATUS_FSYNC 0x00000008
#define ADRV_STATUS_PAUSE 0x00000010
#define AUDIO_DEC_EOS_SET 0x00000001
+#define AUDIO_DEC_EOF_SET 0x00000010
#define AUDIO_EVENT_NUM 10
#define __CONTAINS(r, v, l) ({ \
diff --git a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
index e4291e7..3bc8454 100644
--- a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
+++ b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
@@ -15,7 +15,7 @@
#ifndef __Q6_AUDIO_COMMON_H__
#define __Q6_AUDIO_COMMON_H__
-#ifdef CONFIG_ARCH_MSM8974
+#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625)
#include <sound/apr_audio-v2.h>
#include <sound/q6asm-v2.h>
#else
diff --git a/arch/arm/mach-msm/qdsp6v2/rtac_v2.c b/arch/arm/mach-msm/qdsp6v2/rtac_v2.c
index 2d0607c..409d796 100644
--- a/arch/arm/mach-msm/qdsp6v2/rtac_v2.c
+++ b/arch/arm/mach-msm/qdsp6v2/rtac_v2.c
@@ -24,6 +24,7 @@
#include <mach/qdsp6v2/rtac.h>
#include "q6audio_common.h"
#include <sound/q6afe-v2.h>
+#include <sound/apr_audio-v2.h>
#ifndef CONFIG_RTAC
@@ -45,10 +46,6 @@
#else
-#define VOICE_CMD_SET_PARAM 0x00011006
-#define VOICE_CMD_GET_PARAM 0x00011007
-#define VOICE_EVT_GET_PARAM_ACK 0x00011008
-
/* Max size of payload (buf size - apr header) */
#define MAX_PAYLOAD_SIZE 4076
#define RTAC_MAX_ACTIVE_DEVICES 4
@@ -353,7 +350,7 @@
return;
}
-static int get_voice_index(u32 cvs_handle)
+static int get_voice_index_cvs(u32 cvs_handle)
{
u32 i;
@@ -367,6 +364,32 @@
return 0;
}
+static int get_voice_index_cvp(u32 cvp_handle)
+{
+ u32 i;
+
+ for (i = 0; i < rtac_voice_data.num_of_voice_combos; i++) {
+ if (rtac_voice_data.voice[i].cvp_handle == cvp_handle)
+ return i;
+ }
+
+ pr_err("%s: No voice index for CVP handle %d found returning 0\n",
+ __func__, cvp_handle);
+ return 0;
+}
+
+static int get_voice_index(u32 mode, u32 handle)
+{
+ if (mode == RTAC_CVP)
+ return get_voice_index_cvp(handle);
+ if (mode == RTAC_CVS)
+ return get_voice_index_cvs(handle);
+
+ pr_err("%s: Invalid mode %d, returning 0\n",
+ __func__, mode);
+ return 0;
+}
+
/* ADM APR */
void rtac_set_adm_handle(void *handle)
@@ -402,6 +425,7 @@
if (payload_size > rtac_adm_user_buf_size) {
pr_err("%s: Buffer set not big enough for returned data, buf size = %d, ret data = %d\n",
__func__, rtac_adm_user_buf_size, payload_size);
+ rtac_adm_payload_size = 0;
goto done;
}
memcpy(rtac_adm_buffer + sizeof(u32), payload, payload_size);
@@ -470,6 +494,7 @@
/* Set globals for copy of returned payload */
rtac_adm_user_buf_size = count;
+
/* Copy buffer to in-band payload */
if (copy_from_user(rtac_adm_buffer + sizeof(adm_params),
buf + 3 * sizeof(u32), payload_size)) {
@@ -572,6 +597,7 @@
if (payload_size > rtac_asm_user_buf_size) {
pr_err("%s: Buffer set not big enough for returned data, buf size = %d, ret data = %d\n",
__func__, rtac_asm_user_buf_size, payload_size);
+ rtac_asm_payload_size = 0;
goto done;
}
memcpy(rtac_asm_buffer + sizeof(u32), payload, payload_size);
@@ -619,6 +645,7 @@
__func__);
goto done;
}
+
if (session_id > (SESSION_MAX + 1)) {
pr_err("%s: Invalid Session = %d\n", __func__, session_id);
goto done;
@@ -739,6 +766,7 @@
if (payload_size > rtac_voice_user_buf_size) {
pr_err("%s: Buffer set not big enough for returned data, buf size = %d, ret data = %d\n",
__func__, rtac_voice_user_buf_size, payload_size);
+ rtac_voice_payload_size = 0;
goto done;
}
memcpy(rtac_voice_buffer + sizeof(u32), payload, payload_size);
@@ -753,7 +781,7 @@
u32 count = 0;
u32 bytes_returned = 0;
u32 payload_size;
- u16 dest_port;
+ u32 dest_port;
struct apr_hdr voice_params;
pr_debug("%s\n", __func__);
@@ -818,10 +846,10 @@
voice_params.src_svc = 0;
voice_params.src_domain = APR_DOMAIN_APPS;
voice_params.src_port = voice_session_id[
- get_voice_index(dest_port)];
+ get_voice_index(mode, dest_port)];
voice_params.dest_svc = 0;
voice_params.dest_domain = APR_DOMAIN_MODEM;
- voice_params.dest_port = dest_port;
+ voice_params.dest_port = (u16)dest_port;
voice_params.token = 0;
voice_params.opcode = opcode;
diff --git a/arch/arm/mach-msm/ramdump.c b/arch/arm/mach-msm/ramdump.c
index 21e81dd..e33ec48 100644
--- a/arch/arm/mach-msm/ramdump.c
+++ b/arch/arm/mach-msm/ramdump.c
@@ -181,7 +181,7 @@
.poll = ramdump_poll
};
-void *create_ramdump_device(const char *dev_name)
+void *create_ramdump_device(const char *dev_name, struct device *parent)
{
int ret;
struct ramdump_device *rd_dev;
@@ -207,6 +207,7 @@
rd_dev->device.minor = MISC_DYNAMIC_MINOR;
rd_dev->device.name = rd_dev->name;
rd_dev->device.fops = &ramdump_file_ops;
+ rd_dev->device.parent = parent;
init_waitqueue_head(&rd_dev->dump_wait_q);
diff --git a/arch/arm/mach-msm/ramdump.h b/arch/arm/mach-msm/ramdump.h
index 9006010..3e5bfaf 100644
--- a/arch/arm/mach-msm/ramdump.h
+++ b/arch/arm/mach-msm/ramdump.h
@@ -13,12 +13,14 @@
#ifndef _RAMDUMP_HEADER
#define _RAMDUMP_HEADER
+struct device;
+
struct ramdump_segment {
unsigned long address;
unsigned long size;
};
-void *create_ramdump_device(const char *dev_name);
+void *create_ramdump_device(const char *dev_name, struct device *parent);
void destroy_ramdump_device(void *dev);
int do_ramdump(void *handle, struct ramdump_segment *segments,
int nsegments);
diff --git a/arch/arm/mach-msm/rpm-notifier.h b/arch/arm/mach-msm/rpm-notifier.h
index 33086c6..b9815a5 100644
--- a/arch/arm/mach-msm/rpm-notifier.h
+++ b/arch/arm/mach-msm/rpm-notifier.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -47,4 +47,12 @@
* msm_rpm_exit_sleep - Notify RPM driver about resuming from power collapse
*/
void msm_rpm_exit_sleep(void);
+
+/**
+ * msm_rpm_waiting_for_ack - Indicate if there is RPM message
+ * pending acknowledgement.
+ * returns true for pending messages and false otherwise
+ */
+bool msm_rpm_waiting_for_ack(void);
+
#endif /*__ARCH_ARM_MACH_MSM_RPM_NOTIF_H */
diff --git a/arch/arm/mach-msm/rpm-regulator-smd.c b/arch/arm/mach-msm/rpm-regulator-smd.c
index d1c61fe..bb33283 100644
--- a/arch/arm/mach-msm/rpm-regulator-smd.c
+++ b/arch/arm/mach-msm/rpm-regulator-smd.c
@@ -659,19 +659,6 @@
return uV;
}
-static int rpm_vreg_list_voltage(struct regulator_dev *rdev, unsigned selector)
-{
- struct rpm_regulator *reg = rdev_get_drvdata(rdev);
- int uV = 0;
-
- if (selector == 0)
- uV = reg->min_uV;
- else if (selector == 1)
- uV = reg->max_uV;
-
- return uV;
-}
-
static int rpm_vreg_set_voltage_corner(struct regulator_dev *rdev, int min_uV,
int max_uV, unsigned *selector)
{
@@ -1030,7 +1017,6 @@
.is_enabled = rpm_vreg_is_enabled,
.set_voltage = rpm_vreg_set_voltage,
.get_voltage = rpm_vreg_get_voltage,
- .list_voltage = rpm_vreg_list_voltage,
.set_mode = rpm_vreg_set_mode,
.get_mode = rpm_vreg_get_mode,
.get_optimum_mode = rpm_vreg_get_optimum_mode,
@@ -1043,7 +1029,6 @@
.is_enabled = rpm_vreg_is_enabled,
.set_voltage = rpm_vreg_set_voltage_corner,
.get_voltage = rpm_vreg_get_voltage_corner,
- .list_voltage = rpm_vreg_list_voltage,
.set_mode = rpm_vreg_set_mode,
.get_mode = rpm_vreg_get_mode,
.get_optimum_mode = rpm_vreg_get_optimum_mode,
@@ -1056,7 +1041,6 @@
.is_enabled = rpm_vreg_is_enabled,
.set_voltage = rpm_vreg_set_voltage,
.get_voltage = rpm_vreg_get_voltage,
- .list_voltage = rpm_vreg_list_voltage,
.set_mode = rpm_vreg_set_mode,
.get_mode = rpm_vreg_get_mode,
.get_optimum_mode = rpm_vreg_get_optimum_mode,
@@ -1069,7 +1053,6 @@
.is_enabled = rpm_vreg_is_enabled,
.set_voltage = rpm_vreg_set_voltage_corner,
.get_voltage = rpm_vreg_get_voltage_corner,
- .list_voltage = rpm_vreg_list_voltage,
.set_mode = rpm_vreg_set_mode,
.get_mode = rpm_vreg_get_mode,
.get_optimum_mode = rpm_vreg_get_optimum_mode,
@@ -1089,7 +1072,6 @@
.is_enabled = rpm_vreg_is_enabled,
.set_voltage = rpm_vreg_set_voltage,
.get_voltage = rpm_vreg_get_voltage,
- .list_voltage = rpm_vreg_list_voltage,
.enable_time = rpm_vreg_enable_time,
};
diff --git a/arch/arm/mach-msm/rpm-smd.c b/arch/arm/mach-msm/rpm-smd.c
index f97eb9a..b6fb88c 100644
--- a/arch/arm/mach-msm/rpm-smd.c
+++ b/arch/arm/mach-msm/rpm-smd.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -36,7 +36,8 @@
#include <mach/msm_smd.h>
#include <mach/rpm-smd.h>
#include "rpm-notifier.h"
-
+#define CREATE_TRACE_POINTS
+#include "trace_rpm_smd.h"
/* Debug Definitions */
enum {
@@ -151,6 +152,8 @@
LIST_HEAD(msm_rpm_ack_list);
+static DECLARE_COMPLETION(data_ready);
+
static void msm_rpm_notify_sleep_chain(struct rpm_message_header *hdr,
struct msm_rpm_kvp_data *kvp)
{
@@ -339,7 +342,7 @@
switch (event) {
case SMD_EVENT_DATA:
- queue_work(msm_rpm_smd_wq, &pdata->work);
+ complete(&data_ready);
break;
case SMD_EVENT_OPEN:
complete(&pdata->smd_open);
@@ -354,6 +357,18 @@
}
}
+bool msm_rpm_waiting_for_ack(void)
+{
+ bool ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&msm_rpm_list_lock, flags);
+ ret = list_empty(&msm_rpm_wait_list);
+ spin_unlock_irqrestore(&msm_rpm_list_lock, flags);
+
+ return !ret;
+}
+
static struct msm_rpm_wait_data *msm_rpm_get_entry_from_msg_id(uint32_t msg_id)
{
struct list_head *ptr;
@@ -517,17 +532,19 @@
int errno;
char buf[MAX_ERR_BUFFER_SIZE] = {0};
- if (!spin_trylock(&msm_rpm_data.smd_lock_read))
- return;
- while (smd_is_pkt_avail(msm_rpm_data.ch_info)) {
- if (msm_rpm_read_smd_data(buf)) {
- break;
+ while (1) {
+ wait_for_completion(&data_ready);
+
+ spin_lock(&msm_rpm_data.smd_lock_read);
+ while (smd_is_pkt_avail(msm_rpm_data.ch_info)) {
+ if (msm_rpm_read_smd_data(buf))
+ break;
+ msg_id = msm_rpm_get_msg_id_from_ack(buf);
+ errno = msm_rpm_get_error_from_ack(buf);
+ msm_rpm_process_ack(msg_id, errno);
}
- msg_id = msm_rpm_get_msg_id_from_ack(buf);
- errno = msm_rpm_get_error_from_ack(buf);
- msm_rpm_process_ack(msg_id, errno);
+ spin_unlock(&msm_rpm_data.smd_lock_read);
}
- spin_unlock(&msm_rpm_data.smd_lock_read);
}
#define DEBUG_PRINT_BUFFER_SIZE 512
@@ -761,6 +778,10 @@
spin_unlock_irqrestore(&msm_rpm_data.smd_lock_write, flags);
if (ret == msg_size) {
+ trace_rpm_send_message(noirq, cdata->msg_hdr.set,
+ cdata->msg_hdr.resource_type,
+ cdata->msg_hdr.resource_id,
+ cdata->msg_hdr.msg_id);
for (i = 0; (i < cdata->write_idx); i++)
cdata->kvp[i].valid = false;
cdata->msg_hdr.data_len = 0;
@@ -816,6 +837,8 @@
return 0;
wait_for_completion(&elem->ack);
+ trace_rpm_ack_recd(0, msg_id);
+
msm_rpm_free_list_entry(elem);
return elem->errno;
}
@@ -868,9 +891,14 @@
}
rc = elem->errno;
+ trace_rpm_ack_recd(1, msg_id);
+
msm_rpm_free_list_entry(elem);
wait_ack_cleanup:
spin_unlock_irqrestore(&msm_rpm_data.smd_lock_read, flags);
+
+ if (smd_is_pkt_avail(msm_rpm_data.ch_info))
+ complete(&data_ready);
return rc;
}
EXPORT_SYMBOL(msm_rpm_wait_for_ack_noirq);
@@ -992,6 +1020,7 @@
msm_rpm_smd_wq = create_singlethread_workqueue("rpm-smd");
if (!msm_rpm_smd_wq)
return -EINVAL;
+ queue_work(msm_rpm_smd_wq, &msm_rpm_data.work);
}
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
diff --git a/arch/arm/mach-msm/rpm_stats.c b/arch/arm/mach-msm/rpm_stats.c
index a831bd5..9a8b8ec 100644
--- a/arch/arm/mach-msm/rpm_stats.c
+++ b/arch/arm/mach-msm/rpm_stats.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -22,11 +22,14 @@
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/mm.h>
+#include <linux/types.h>
+#include <linux/of.h>
#include <asm/uaccess.h>
-
+#include <asm/arch_timer.h>
#include <mach/msm_iomap.h>
#include "rpm_stats.h"
+
enum {
ID_COUNTER,
ID_ACCUM_TIME_SCLK,
@@ -39,21 +42,111 @@
};
#define SCLK_HZ 32768
+#define MSM_ARCH_TIMER_FREQ 19200000
+
struct msm_rpmstats_record{
char name[32];
uint32_t id;
uint32_t val;
};
-
struct msm_rpmstats_private_data{
void __iomem *reg_base;
u32 num_records;
u32 read_idx;
u32 len;
- char buf[128];
+ char buf[256];
struct msm_rpmstats_platform_data *platform_data;
};
+struct msm_rpm_stats_data_v2 {
+ u32 stat_type;
+ u32 count;
+ u64 last_entered_at;
+ u64 last_exited_at;
+};
+
+static inline u64 get_time_in_sec(u64 counter)
+{
+ do_div(counter, MSM_ARCH_TIMER_FREQ);
+ return counter;
+}
+
+static inline u64 get_time_in_msec(u64 counter)
+{
+ do_div(counter, MSM_ARCH_TIMER_FREQ);
+ counter *= MSEC_PER_SEC;
+ return counter;
+}
+
+static inline int msm_rpmstats_append_data_to_buf(char *buf,
+ struct msm_rpm_stats_data_v2 *data, int buflength)
+{
+ char stat_type[5];
+ u64 time_in_last_mode;
+ u64 time_since_last_mode;
+
+ stat_type[4] = 0;
+ memcpy(stat_type, &data->stat_type, sizeof(u32));
+
+ time_in_last_mode = data->last_exited_at - data->last_entered_at;
+ time_in_last_mode = get_time_in_msec(time_in_last_mode);
+ time_since_last_mode = arch_counter_get_cntpct() - data->last_exited_at;
+ time_since_last_mode = get_time_in_sec(time_since_last_mode);
+
+ return snprintf(buf , buflength,
+ "RPM Mode:%s\n\t count:%d\n time in last mode(msec):%llu\n"
+ "time since last mode(sec):%llu\n",
+ stat_type, data->count, time_in_last_mode,
+ time_since_last_mode);
+}
+
+static inline u32 msm_rpmstats_read_long_register_v2(void __iomem *regbase,
+ int index, int offset)
+{
+ return readl_relaxed(regbase + offset +
+ index * sizeof(struct msm_rpm_stats_data_v2));
+}
+
+static inline u64 msm_rpmstats_read_quad_register_v2(void __iomem *regbase,
+ int index, int offset)
+{
+ u64 dst;
+ memcpy_fromio(&dst,
+ regbase + offset + index * sizeof(struct msm_rpm_stats_data_v2),
+ 8);
+ return dst;
+}
+
+static inline int msm_rpmstats_copy_stats_v2(
+ struct msm_rpmstats_private_data *prvdata)
+{
+ void __iomem *reg;
+ struct msm_rpm_stats_data_v2 data;
+ int i, length;
+
+ reg = prvdata->reg_base;
+
+ for (i = 0, length = 0; i < prvdata->num_records; i++) {
+
+ data.stat_type = msm_rpmstats_read_long_register_v2(reg, i,
+ offsetof(struct msm_rpm_stats_data_v2,
+ stat_type));
+ data.count = msm_rpmstats_read_long_register_v2(reg, i,
+ offsetof(struct msm_rpm_stats_data_v2, count));
+ data.last_entered_at = msm_rpmstats_read_quad_register_v2(reg,
+ i, offsetof(struct msm_rpm_stats_data_v2,
+ last_entered_at));
+ data.last_exited_at = msm_rpmstats_read_quad_register_v2(reg,
+ i, offsetof(struct msm_rpm_stats_data_v2,
+ last_exited_at));
+
+ length += msm_rpmstats_append_data_to_buf(prvdata->buf + length,
+ &data, sizeof(prvdata->buf) - length);
+ prvdata->read_idx++;
+ }
+ return length;
+}
+
static inline unsigned long msm_rpmstats_read_register(void __iomem *regbase,
int index, int offset)
{
@@ -133,13 +226,19 @@
if (!bufu || count < 0)
return -EINVAL;
- if (!prvdata->num_records)
- prvdata->num_records = readl_relaxed(prvdata->reg_base);
+ if (prvdata->platform_data->version == 1) {
+ if (!prvdata->num_records)
+ prvdata->num_records = readl_relaxed(prvdata->reg_base);
+ }
if ((*ppos >= prvdata->len)
- && (prvdata->read_idx < prvdata->num_records)) {
- prvdata->len = msm_rpmstats_copy_stats(prvdata);
- *ppos = 0;
+ && (prvdata->read_idx < prvdata->num_records)) {
+ if (prvdata->platform_data->version == 1)
+ prvdata->len = msm_rpmstats_copy_stats(prvdata);
+ else if (prvdata->platform_data->version == 2)
+ prvdata->len = msm_rpmstats_copy_stats_v2(
+ prvdata);
+ *ppos = 0;
}
return simple_read_from_buffer(bufu, count, ppos,
@@ -160,7 +259,8 @@
return -ENOMEM;
prvdata = file->private_data;
- prvdata->reg_base = ioremap(pdata->phys_addr_base, pdata->phys_size);
+ prvdata->reg_base = ioremap_nocache(pdata->phys_addr_base,
+ pdata->phys_size);
if (!prvdata->reg_base) {
kfree(file->private_data);
prvdata = NULL;
@@ -172,6 +272,9 @@
prvdata->read_idx = prvdata->num_records = prvdata->len = 0;
prvdata->platform_data = pdata;
+ if (pdata->version == 2)
+ prvdata->num_records = 2;
+
return 0;
}
@@ -196,18 +299,53 @@
static int __devinit msm_rpmstats_probe(struct platform_device *pdev)
{
- struct dentry *dent;
+ struct dentry *dent = NULL;
struct msm_rpmstats_platform_data *pdata;
+ struct msm_rpmstats_platform_data *pd;
+ struct resource *res = NULL;
+ struct device_node *node = NULL;
+ int ret = 0;
- pdata = pdev->dev.platform_data;
- if (!pdata)
+ if (!pdev)
return -EINVAL;
- dent = debugfs_create_file("rpm_stats", S_IRUGO, NULL,
- pdev->dev.platform_data, &msm_rpmstats_fops);
- if (!dent) {
- pr_err("%s: ERROR debugfs_create_file failed\n", __func__);
+ pdata = kzalloc(sizeof(struct msm_rpmstats_platform_data), GFP_KERNEL);
+
+ if (!pdata)
return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (!res)
+ return -EINVAL;
+
+ pdata->phys_addr_base = res->start;
+
+ pdata->phys_size = resource_size(res);
+ node = pdev->dev.of_node;
+ if (pdev->dev.platform_data) {
+ pd = pdev->dev.platform_data;
+ pdata->version = pd->version;
+
+ } else if (node)
+ ret = of_property_read_u32(node,
+ "qcom,sleep-stats-version", &pdata->version);
+
+ if (!ret) {
+
+ dent = debugfs_create_file("rpm_stats", S_IRUGO, NULL,
+ pdata, &msm_rpmstats_fops);
+
+ if (!dent) {
+ pr_err("%s: ERROR debugfs_create_file failed\n",
+ __func__);
+ kfree(pdata);
+ return -ENOMEM;
+ }
+
+ } else {
+ kfree(pdata);
+ return -EINVAL;
}
platform_set_drvdata(pdev, dent);
return 0;
@@ -222,12 +360,19 @@
platform_set_drvdata(pdev, NULL);
return 0;
}
+
+static struct of_device_id rpm_stats_table[] = {
+ {.compatible = "qcom,rpm-stats"},
+ {},
+};
+
static struct platform_driver msm_rpmstats_driver = {
.probe = msm_rpmstats_probe,
.remove = __devexit_p(msm_rpmstats_remove),
.driver = {
.name = "msm_rpm_stat",
.owner = THIS_MODULE,
+ .of_match_table = rpm_stats_table,
},
};
static int __init msm_rpmstats_init(void)
diff --git a/arch/arm/mach-msm/rpm_stats.h b/arch/arm/mach-msm/rpm_stats.h
index a3beaa4..c1dfe34 100644
--- a/arch/arm/mach-msm/rpm_stats.h
+++ b/arch/arm/mach-msm/rpm_stats.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,7 @@
struct msm_rpmstats_platform_data {
phys_addr_t phys_addr_base;
u32 phys_size;
+ u32 version;
};
struct msm_rpm_master_stats_platform_data {
diff --git a/arch/arm/mach-msm/saw-regulator.c b/arch/arm/mach-msm/saw-regulator.c
index 6762648..0a81a33 100644
--- a/arch/arm/mach-msm/saw-regulator.c
+++ b/arch/arm/mach-msm/saw-regulator.c
@@ -54,11 +54,17 @@
struct regulator_dev *rdev;
char *name;
int uV;
+ int last_set_uV;
+ unsigned vlevel;
+ bool online;
};
/* Minimum core operating voltage */
#define MIN_CORE_VOLTAGE 950000
+/* Specifies an uninitialized voltage */
+#define INVALID_VOLTAGE -1
+
/* Specifies the PMIC internal slew rate in uV/us. */
#define REGULATOR_SLEW_RATE 1250
@@ -69,12 +75,32 @@
return vreg->uV;
}
+static int _set_voltage(struct regulator_dev *rdev)
+{
+ struct saw_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc;
+
+ rc = msm_spm_set_vdd(rdev_get_id(rdev), vreg->vlevel);
+ if (!rc) {
+ if (vreg->uV > vreg->last_set_uV) {
+ /* Wait for voltage to stabalize. */
+ udelay((vreg->uV - vreg->last_set_uV) /
+ REGULATOR_SLEW_RATE);
+ }
+ vreg->last_set_uV = vreg->uV;
+ } else {
+ pr_err("%s: msm_spm_set_vdd failed %d\n", vreg->name, rc);
+ vreg->uV = vreg->last_set_uV;
+ }
+
+ return rc;
+}
+
static int saw_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
unsigned *selector)
{
struct saw_vreg *vreg = rdev_get_drvdata(rdev);
int uV = min_uV;
- int rc;
u8 vprog, band;
if (uV < FTSMPS_BAND1_UV_MIN && max_uV >= FTSMPS_BAND1_UV_MIN)
@@ -119,23 +145,51 @@
return -EINVAL;
}
- rc = msm_spm_set_vdd(rdev_get_id(rdev), band | vprog);
- if (!rc) {
- if (uV > vreg->uV) {
- /* Wait for voltage to stabalize. */
- udelay((uV - vreg->uV) / REGULATOR_SLEW_RATE);
- }
- vreg->uV = uV;
- } else {
- pr_err("%s: msm_spm_set_vdd failed %d\n", vreg->name, rc);
- }
+ vreg->vlevel = band | vprog;
+ vreg->uV = uV;
+
+ if (!vreg->online)
+ return 0;
+
+ return _set_voltage(rdev);
+}
+
+static int saw_enable(struct regulator_dev *rdev)
+{
+ struct saw_vreg *vreg = rdev_get_drvdata(rdev);
+ int rc = 0;
+
+ if (vreg->uV != vreg->last_set_uV)
+ rc = _set_voltage(rdev);
+
+ if (!rc)
+ vreg->online = true;
return rc;
}
+static int saw_disable(struct regulator_dev *rdev)
+{
+ struct saw_vreg *vreg = rdev_get_drvdata(rdev);
+
+ vreg->online = false;
+
+ return 0;
+}
+
+static int saw_is_enabled(struct regulator_dev *rdev)
+{
+ struct saw_vreg *vreg = rdev_get_drvdata(rdev);
+
+ return vreg->online;
+}
+
static struct regulator_ops saw_ops = {
.get_voltage = saw_get_voltage,
.set_voltage = saw_set_voltage,
+ .enable = saw_enable,
+ .disable = saw_disable,
+ .is_enabled = saw_is_enabled,
};
static int __devinit saw_probe(struct platform_device *pdev)
@@ -168,12 +222,13 @@
goto free_vreg;
}
- vreg->desc.name = vreg->name;
- vreg->desc.id = pdev->id;
- vreg->desc.ops = &saw_ops;
- vreg->desc.type = REGULATOR_VOLTAGE;
- vreg->desc.owner = THIS_MODULE;
- vreg->uV = MIN_CORE_VOLTAGE;
+ vreg->desc.name = vreg->name;
+ vreg->desc.id = pdev->id;
+ vreg->desc.ops = &saw_ops;
+ vreg->desc.type = REGULATOR_VOLTAGE;
+ vreg->desc.owner = THIS_MODULE;
+ vreg->uV = INVALID_VOLTAGE;
+ vreg->last_set_uV = MIN_CORE_VOLTAGE;
vreg->rdev = regulator_register(&vreg->desc, &pdev->dev,
init_data, vreg, NULL);
@@ -233,5 +288,4 @@
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("SAW regulator driver");
-MODULE_VERSION("1.0");
MODULE_ALIAS("platform:saw-regulator");
diff --git a/arch/arm/mach-msm/scm-pas.c b/arch/arm/mach-msm/scm-pas.c
index 55ae2f8..e248917 100644
--- a/arch/arm/mach-msm/scm-pas.c
+++ b/arch/arm/mach-msm/scm-pas.c
@@ -24,6 +24,7 @@
#include "scm-pas.h"
#define PAS_INIT_IMAGE_CMD 1
+#define PAS_MEM_SETUP_CMD 2
#define PAS_AUTH_AND_RESET_CMD 5
#define PAS_SHUTDOWN_CMD 6
#define PAS_IS_SUPPORTED_CMD 7
@@ -55,6 +56,28 @@
}
EXPORT_SYMBOL(pas_init_image);
+int pas_mem_setup(enum pas_id id, u32 start_addr, u32 len)
+{
+ int ret;
+ struct pas_init_image_req {
+ u32 proc;
+ u32 start_addr;
+ u32 len;
+ } request;
+ u32 scm_ret = 0;
+
+ request.proc = id;
+ request.start_addr = start_addr;
+ request.len = len;
+
+ ret = scm_call(SCM_SVC_PIL, PAS_MEM_SETUP_CMD, &request,
+ sizeof(request), &scm_ret, sizeof(scm_ret));
+ if (ret)
+ return ret;
+ return scm_ret;
+}
+EXPORT_SYMBOL(pas_mem_setup);
+
static struct msm_bus_paths scm_pas_bw_tbl[] = {
{
.vectors = (struct msm_bus_vectors[]){
diff --git a/arch/arm/mach-msm/scm-pas.h b/arch/arm/mach-msm/scm-pas.h
index 8da1d75..6441a18 100644
--- a/arch/arm/mach-msm/scm-pas.h
+++ b/arch/arm/mach-msm/scm-pas.h
@@ -27,6 +27,7 @@
#ifdef CONFIG_MSM_PIL
extern int pas_init_image(enum pas_id id, const u8 *metadata, size_t size);
+extern int pas_mem_setup(enum pas_id id, u32 start_addr, u32 len);
extern int pas_auth_and_reset(enum pas_id id);
extern int pas_shutdown(enum pas_id id);
extern int pas_supported(enum pas_id id);
@@ -36,6 +37,10 @@
{
return 0;
}
+static inline int pas_mem_setup(enum pas_id id, u32 start_addr, u32 len)
+{
+ return 0;
+}
static inline int pas_auth_and_reset(enum pas_id id)
{
return 0;
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
index 6013efc..f4dae89 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-msm/scm.c
@@ -204,10 +204,13 @@
return ret;
}
-static u32 cacheline_size;
-
static void scm_inv_range(unsigned long start, unsigned long end)
{
+ u32 cacheline_size, ctr;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
start = round_down(start, cacheline_size);
end = round_up(end, cacheline_size);
outer_inv_range(start, end);
@@ -444,13 +447,3 @@
}
EXPORT_SYMBOL(scm_get_feat_version);
-static int scm_init(void)
-{
- u32 ctr;
-
- asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
- cacheline_size = 4 << ((ctr >> 16) & 0xf);
-
- return 0;
-}
-early_initcall(scm_init);
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index c6da910..7427899 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -36,6 +36,8 @@
#include <linux/notifier.h>
#include <linux/sort.h>
#include <linux/suspend.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
#include <mach/msm_smd.h>
#include <mach/msm_iomap.h>
#include <mach/system.h>
@@ -706,7 +708,7 @@
*/
static struct edge_to_pid edge_to_pids[] = {
[SMD_APPS_MODEM] = {SMD_APPS, SMD_MODEM, "modem"},
- [SMD_APPS_QDSP] = {SMD_APPS, SMD_Q6, "q6"},
+ [SMD_APPS_QDSP] = {SMD_APPS, SMD_Q6, "adsp"},
[SMD_MODEM_QDSP] = {SMD_MODEM, SMD_Q6},
[SMD_APPS_DSPS] = {SMD_APPS, SMD_DSPS, "dsps"},
[SMD_MODEM_DSPS] = {SMD_MODEM, SMD_DSPS},
@@ -1016,6 +1018,7 @@
notify_dsp_smd();
notify_dsps_smd();
notify_wcnss_smd();
+ notify_rpm_smd();
/* change all remote states to CLOSED */
mutex_lock(&smd_probe_lock);
@@ -1031,6 +1034,7 @@
notify_dsp_smd();
notify_dsps_smd();
notify_wcnss_smd();
+ notify_rpm_smd();
SMD_DBG("%s: finished reset\n", __func__);
}
@@ -3500,6 +3504,295 @@
return err_ret;
}
+static int __devinit parse_smd_devicetree(struct device_node *node,
+ void *irq_out_base)
+{
+ uint32_t edge;
+ char *key;
+ int ret;
+ uint32_t irq_offset;
+ uint32_t irq_bitmask;
+ uint32_t irq_line;
+ unsigned long irq_flags = IRQF_TRIGGER_RISING;
+ const char *pilstr;
+ struct interrupt_config_item *private_irq;
+
+ key = "qcom,smd-edge";
+ ret = of_property_read_u32(node, key, &edge);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %d", __func__, key, edge);
+
+ key = "qcom,smd-irq-offset";
+ ret = of_property_read_u32(node, key, &irq_offset);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %x", __func__, key, irq_offset);
+
+ key = "qcom,smd-irq-bitmask";
+ ret = of_property_read_u32(node, key, &irq_bitmask);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %x", __func__, key, irq_bitmask);
+
+ key = "interrupts";
+ irq_line = irq_of_parse_and_map(node, 0);
+ if (!irq_line)
+ goto missing_key;
+ SMD_DBG("%s: %s = %d", __func__, key, irq_line);
+
+ key = "qcom,pil-string";
+ pilstr = of_get_property(node, key, NULL);
+ if (pilstr)
+ SMD_DBG("%s: %s = %s", __func__, key, pilstr);
+
+ key = "qcom,irq-no-suspend";
+ ret = of_property_read_bool(node, key);
+ if (ret)
+ irq_flags |= IRQF_NO_SUSPEND;
+
+ private_irq = &private_intr_config[edge_to_pids[edge].remote_pid].smd;
+ private_irq->out_bit_pos = irq_bitmask;
+ private_irq->out_offset = irq_offset;
+ private_irq->out_base = irq_out_base;
+ private_irq->irq_id = irq_line;
+
+ ret = request_irq(irq_line,
+ private_irq->irq_handler,
+ irq_flags,
+ "smd_dev",
+ NULL);
+ if (ret < 0) {
+ pr_err("%s: request_irq() failed on %d\n", __func__, irq_line);
+ return ret;
+ } else {
+ ret = enable_irq_wake(irq_line);
+ if (ret < 0)
+ pr_err("%s: enable_irq_wake() failed on %d\n", __func__,
+ irq_line);
+ }
+
+ if (pilstr)
+ strlcpy(edge_to_pids[edge].subsys_name, pilstr,
+ SMD_MAX_CH_NAME_LEN);
+
+ return 0;
+
+missing_key:
+ pr_err("%s: missing key: %s", __func__, key);
+ return -ENODEV;
+}
+
+static int __devinit parse_smsm_devicetree(struct device_node *node,
+ void *irq_out_base)
+{
+ uint32_t edge;
+ char *key;
+ int ret;
+ uint32_t irq_offset;
+ uint32_t irq_bitmask;
+ uint32_t irq_line;
+ struct interrupt_config_item *private_irq;
+
+ key = "qcom,smsm-edge";
+ ret = of_property_read_u32(node, key, &edge);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %d", __func__, key, edge);
+
+ key = "qcom,smsm-irq-offset";
+ ret = of_property_read_u32(node, key, &irq_offset);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %x", __func__, key, irq_offset);
+
+ key = "qcom,smsm-irq-bitmask";
+ ret = of_property_read_u32(node, key, &irq_bitmask);
+ if (ret)
+ goto missing_key;
+ SMD_DBG("%s: %s = %x", __func__, key, irq_bitmask);
+
+ key = "interrupts";
+ irq_line = irq_of_parse_and_map(node, 0);
+ if (!irq_line)
+ goto missing_key;
+ SMD_DBG("%s: %s = %d", __func__, key, irq_line);
+
+ private_irq = &private_intr_config[edge_to_pids[edge].remote_pid].smsm;
+ private_irq->out_bit_pos = irq_bitmask;
+ private_irq->out_offset = irq_offset;
+ private_irq->out_base = irq_out_base;
+ private_irq->irq_id = irq_line;
+
+ ret = request_irq(irq_line,
+ private_irq->irq_handler,
+ IRQF_TRIGGER_RISING,
+ "smsm_dev",
+ NULL);
+ if (ret < 0) {
+ pr_err("%s: request_irq() failed on %d\n", __func__, irq_line);
+ return ret;
+ } else {
+ ret = enable_irq_wake(irq_line);
+ if (ret < 0)
+ pr_err("%s: enable_irq_wake() failed on %d\n", __func__,
+ irq_line);
+ }
+
+ return 0;
+
+missing_key:
+ pr_err("%s: missing key: %s", __func__, key);
+ return -ENODEV;
+}
+
+static void __devinit unparse_smd_devicetree(struct device_node *node)
+{
+ uint32_t irq_line;
+
+ irq_line = irq_of_parse_and_map(node, 0);
+
+ free_irq(irq_line, NULL);
+}
+
+static void __devinit unparse_smsm_devicetree(struct device_node *node)
+{
+ uint32_t irq_line;
+
+ irq_line = irq_of_parse_and_map(node, 0);
+
+ free_irq(irq_line, NULL);
+}
+
+static int __devinit smd_core_devicetree_init(struct platform_device *pdev)
+{
+ char *key;
+ struct resource *r;
+ void *irq_out_base;
+ void *aux_mem_base;
+ uint32_t aux_mem_size;
+ int temp_string_size = 11; /* max 3 digit count */
+ char temp_string[temp_string_size];
+ int count;
+ struct device_node *node;
+ int ret;
+ const char *compatible;
+ int subnode_num = 0;
+
+ disable_smsm_reset_handshake = 1;
+
+ key = "irq-reg-base";
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, key);
+ if (!r) {
+ pr_err("%s: missing '%s'\n", __func__, key);
+ return -ENODEV;
+ }
+ irq_out_base = (void *)(r->start);
+ SMD_DBG("%s: %s = %p", __func__, key, irq_out_base);
+
+ count = 1;
+ while (1) {
+ scnprintf(temp_string, temp_string_size, "aux-mem%d", count);
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ temp_string);
+ if (!r)
+ break;
+
+ ++num_smem_areas;
+ ++count;
+ if (count > 999) {
+ pr_err("%s: max num aux mem regions reached\n",
+ __func__);
+ break;
+ }
+ }
+
+ if (num_smem_areas) {
+ smem_areas = kmalloc(sizeof(struct smem_area) * num_smem_areas,
+ GFP_KERNEL);
+ if (!smem_areas) {
+ pr_err("%s: smem areas kmalloc failed\n", __func__);
+ num_smem_areas = 0;
+ return -ENOMEM;
+ }
+ count = 1;
+ while (1) {
+ scnprintf(temp_string, temp_string_size, "aux-mem%d",
+ count);
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ temp_string);
+ if (!r)
+ break;
+ aux_mem_base = (void *)(r->start);
+ aux_mem_size = (uint32_t)(resource_size(r));
+ SMD_DBG("%s: %s = %p %x", __func__, temp_string,
+ aux_mem_base, aux_mem_size);
+ smem_areas[count - 1].phys_addr = aux_mem_base;
+ smem_areas[count - 1].size = aux_mem_size;
+ smem_areas[count - 1].virt_addr = ioremap_nocache(
+ (unsigned long)(smem_areas[count-1].phys_addr),
+ smem_areas[count - 1].size);
+ if (!smem_areas[count - 1].virt_addr) {
+ pr_err("%s: ioremap_nocache() of addr:%p size: %x\n",
+ __func__,
+ smem_areas[count - 1].phys_addr,
+ smem_areas[count - 1].size);
+ ret = -ENOMEM;
+ goto free_smem_areas;
+ }
+
+ ++count;
+ if (count > 999) {
+ pr_err("%s: max num aux mem regions reached\n",
+ __func__);
+ break;
+ }
+ }
+ sort(smem_areas, num_smem_areas,
+ sizeof(struct smem_area),
+ sort_cmp_func, NULL);
+ }
+
+ for_each_child_of_node(pdev->dev.of_node, node) {
+ compatible = of_get_property(node, "compatible", NULL);
+ if (!strcmp(compatible, "qcom,smd")) {
+ ret = parse_smd_devicetree(node, irq_out_base);
+ if (ret)
+ goto rollback_subnodes;
+ } else if (!strcmp(compatible, "qcom,smsm")) {
+ ret = parse_smsm_devicetree(node, irq_out_base);
+ if (ret)
+ goto rollback_subnodes;
+ } else {
+ pr_err("%s: invalid child node named: %s\n", __func__,
+ compatible);
+ ret = -ENODEV;
+ goto rollback_subnodes;
+ }
+ ++subnode_num;
+ }
+
+ return 0;
+
+rollback_subnodes:
+ count = 0;
+ for_each_child_of_node(pdev->dev.of_node, node) {
+ if (count >= subnode_num)
+ break;
+ ++count;
+ compatible = of_get_property(node, "compatible", NULL);
+ if (!strcmp(compatible, "qcom,smd"))
+ unparse_smd_devicetree(node);
+ else
+ unparse_smsm_devicetree(node);
+ }
+free_smem_areas:
+ num_smem_areas = 0;
+ kfree(smem_areas);
+ smem_areas = NULL;
+ return ret;
+}
+
static int __devinit msm_smd_probe(struct platform_device *pdev)
{
int ret;
@@ -3520,8 +3813,12 @@
if (pdev) {
if (pdev->dev.of_node) {
- pr_err("SMD: Device tree not currently supported\n");
- return -ENODEV;
+ ret = smd_core_devicetree_init(pdev);
+ if (ret) {
+ pr_err("%s: device tree init failed\n",
+ __func__);
+ return ret;
+ }
} else if (pdev->dev.platform_data) {
ret = smd_core_platform_init(pdev);
if (ret) {
@@ -3598,11 +3895,17 @@
}
late_initcall(modem_restart_late_init);
+static struct of_device_id msm_smem_match_table[] = {
+ { .compatible = "qcom,smem" },
+ {},
+};
+
static struct platform_driver msm_smd_driver = {
.probe = msm_smd_probe,
.driver = {
.name = MODULE_NAME,
.owner = THIS_MODULE,
+ .of_match_table = msm_smem_match_table,
},
};
diff --git a/arch/arm/mach-msm/smd_pkt.c b/arch/arm/mach-msm/smd_pkt.c
index 928e59b..73ebdf6 100644
--- a/arch/arm/mach-msm/smd_pkt.c
+++ b/arch/arm/mach-msm/smd_pkt.c
@@ -34,14 +34,14 @@
#include <linux/wakelock.h>
#include <mach/msm_smd.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include <mach/msm_ipc_logging.h>
#include "smd_private.h"
#ifdef CONFIG_ARCH_FSM9XXX
#define NUM_SMD_PKT_PORTS 4
#else
-#define NUM_SMD_PKT_PORTS 15
+#define NUM_SMD_PKT_PORTS 24
#endif
#define PDRIVER_NAME_MAX_SIZE 32
@@ -711,6 +711,15 @@
"smdcntl6",
"smdcntl7",
"smd22",
+ "smdcnt_rev0",
+ "smdcnt_rev1",
+ "smdcnt_rev2",
+ "smdcnt_rev3",
+ "smdcnt_rev4",
+ "smdcnt_rev5",
+ "smdcnt_rev6",
+ "smdcnt_rev7",
+ "smdcnt_rev8",
"smd_sns_dsps",
"apr_apps2",
"smdcntl8",
@@ -729,6 +738,15 @@
"DATA13_CNTL",
"DATA14_CNTL",
"DATA22",
+ "DATA23_CNTL",
+ "DATA24_CNTL",
+ "DATA25_CNTL",
+ "DATA26_CNTL",
+ "DATA27_CNTL",
+ "DATA28_CNTL",
+ "DATA29_CNTL",
+ "DATA30_CNTL",
+ "DATA31_CNTL",
"SENSOR",
"apr_apps2",
"DATA40_CNTL",
@@ -747,6 +765,15 @@
SMD_APPS_MODEM,
SMD_APPS_MODEM,
SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
+ SMD_APPS_MODEM,
SMD_APPS_DSPS,
SMD_APPS_QDSP,
SMD_APPS_MODEM,
@@ -823,12 +850,11 @@
peripheral = smd_edge_to_subsystem(
smd_ch_edge[smd_pkt_devp->i]);
if (peripheral) {
- smd_pkt_devp->pil = pil_get(peripheral);
+ smd_pkt_devp->pil = subsystem_get(peripheral);
if (IS_ERR(smd_pkt_devp->pil)) {
r = PTR_ERR(smd_pkt_devp->pil);
- pr_err("%s failed on smd_pkt_dev id:%d -"
- " pil_get failed for %s\n", __func__,
- smd_pkt_devp->i, peripheral);
+ pr_err("%s failed on smd_pkt_dev id:%d - subsystem_get failed for %s\n",
+ __func__, smd_pkt_devp->i, peripheral);
goto release_pd;
}
@@ -908,7 +934,7 @@
}
release_pil:
if (peripheral && (r < 0))
- pil_put(smd_pkt_devp->pil);
+ subsystem_put(smd_pkt_devp->pil);
release_pd:
if (r < 0) {
@@ -952,7 +978,7 @@
platform_driver_unregister(&smd_pkt_devp->driver);
smd_pkt_devp->driver.probe = NULL;
if (smd_pkt_devp->pil)
- pil_put(smd_pkt_devp->pil);
+ subsystem_put(smd_pkt_devp->pil);
smd_pkt_devp->has_reset = 0;
smd_pkt_devp->do_reset_notification = 0;
smd_pkt_devp->wakelock_locked = 0;
diff --git a/arch/arm/mach-msm/smd_rpcrouter.c b/arch/arm/mach-msm/smd_rpcrouter.c
index 80a639c..1bea82a 100644
--- a/arch/arm/mach-msm/smd_rpcrouter.c
+++ b/arch/arm/mach-msm/smd_rpcrouter.c
@@ -306,6 +306,10 @@
struct msm_rpc_reply *reply, *reply_tmp;
unsigned long flags;
+ if (!xprt_info) {
+ pr_err("%s: Invalid xprt_info\n", __func__);
+ return;
+ }
spin_lock_irqsave(&local_endpoints_lock, flags);
/* remove all partial packets received */
list_for_each_entry(ept, &local_endpoints, list) {
@@ -2154,6 +2158,7 @@
while (!list_empty(&xprt_info_list)) {
xprt_info = list_first_entry(&xprt_info_list,
struct rpcrouter_xprt_info, list);
+ modem_reset_cleanup(xprt_info);
xprt_info->abort_data_read = 1;
wake_up(&xprt_info->read_wait);
rpcrouter_send_control_msg(xprt_info, &ctl);
@@ -2164,6 +2169,8 @@
flush_workqueue(xprt_info->workqueue);
destroy_workqueue(xprt_info->workqueue);
wake_lock_destroy(&xprt_info->wakelock);
+ /*free memory*/
+ xprt_info->xprt->priv = 0;
kfree(xprt_info);
mutex_lock(&xprt_info_list_lock);
diff --git a/arch/arm/mach-msm/smd_rpcrouter_device.c b/arch/arm/mach-msm/smd_rpcrouter_device.c
index e84d213..7b51beb 100644
--- a/arch/arm/mach-msm/smd_rpcrouter_device.c
+++ b/arch/arm/mach-msm/smd_rpcrouter_device.c
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/smd_rpcrouter_device.c
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
* Author: San Mehat <san@android.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -34,7 +34,7 @@
#include <asm/uaccess.h>
#include <asm/byteorder.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include "smd_rpcrouter.h"
/* Support 64KB of data plus some space for headers */
@@ -61,7 +61,7 @@
static void msm_rpcrouter_unload_modem(void *pil)
{
if (pil)
- pil_put(pil);
+ subsystem_put(pil);
}
static void *msm_rpcrouter_load_modem(void)
@@ -69,7 +69,7 @@
void *pil;
int rc;
- pil = pil_get("modem");
+ pil = subsystem_get("modem");
if (IS_ERR(pil))
pr_err("%s: modem load failed\n", __func__);
else {
diff --git a/arch/arm/mach-msm/smd_tty.c b/arch/arm/mach-msm/smd_tty.c
index 44ef822..881da18 100644
--- a/arch/arm/mach-msm/smd_tty.c
+++ b/arch/arm/mach-msm/smd_tty.c
@@ -30,7 +30,7 @@
#include <linux/tty_flip.h>
#include <mach/msm_smd.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include <mach/socinfo.h>
#include "smd_private.h"
@@ -245,7 +245,7 @@
if (info->open_count++ == 0) {
peripheral = smd_edge_to_subsystem(smd_tty[n].smd->edge);
if (peripheral) {
- info->pil = pil_get(peripheral);
+ info->pil = subsystem_get(peripheral);
if (IS_ERR(info->pil)) {
res = PTR_ERR(info->pil);
goto out;
@@ -325,7 +325,7 @@
release_pil:
if (res < 0)
- pil_put(info->pil);
+ subsystem_put(info->pil);
else
smd_disable_read_intr(info->ch);
out:
@@ -357,7 +357,7 @@
if (info->ch) {
smd_close(info->ch);
info->ch = 0;
- pil_put(info->pil);
+ subsystem_put(info->pil);
}
}
mutex_unlock(&smd_tty_lock);
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 62085f6..2743547 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -260,6 +260,7 @@
[128] = MSM_CPU_8625,
[129] = MSM_CPU_8625,
[137] = MSM_CPU_8625,
+ [167] = MSM_CPU_8625,
/* 8064 MPQ ID */
[130] = MSM_CPU_8064,
@@ -302,7 +303,13 @@
[154] = MSM_CPU_8930AB,
[155] = MSM_CPU_8930AB,
[156] = MSM_CPU_8930AB,
- [157] = MSM_CPU_8930AB
+ [157] = MSM_CPU_8930AB,
+
+ /* 8625Q IDs */
+ [168] = MSM_CPU_8625Q,
+ [169] = MSM_CPU_8625Q,
+ [170] = MSM_CPU_8625Q,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
diff --git a/arch/arm/mach-msm/spm.c b/arch/arm/mach-msm/spm.c
index 8337fd1..ea0b56c 100644
--- a/arch/arm/mach-msm/spm.c
+++ b/arch/arm/mach-msm/spm.c
@@ -132,6 +132,11 @@
/******************************************************************************
* Public functions
*****************************************************************************/
+/**
+ * msm_spm_set_low_power_mode() - Configure SPM start address for low power mode
+ * @mode: SPM LPM mode to enter
+ * @notify_rpm: Notify RPM in this mode
+ */
int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
{
struct msm_spm_device *dev = &__get_cpu_var(msm_spm_devices);
@@ -185,6 +190,11 @@
return 0;
}
+/**
+ * msm_spm_set_vdd(): Set core voltage
+ * @cpu: core id
+ * @vlevel: Encoded PMIC data.
+ */
int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel)
{
struct msm_spm_device *dev;
@@ -235,6 +245,11 @@
return -EIO;
}
+/**
+ * msm_spm_get_vdd(): Get core voltage
+ * @cpu: core id
+ * @return: Returns encoded PMIC data.
+ */
unsigned int msm_spm_get_vdd(unsigned int cpu)
{
struct msm_spm_device *dev = &per_cpu(msm_spm_devices, cpu);
@@ -253,6 +268,11 @@
mb();
}
+/**
+ * msm_spm_init(): Board initalization function
+ * @data: platform specific SPM register configuration data
+ * @nr_devs: Number of SPM devices being initialized
+ */
int __init msm_spm_init(struct msm_spm_platform_data *data, int nr_devs)
{
unsigned int cpu;
diff --git a/arch/arm/mach-msm/spm.h b/arch/arm/mach-msm/spm.h
index 4cdfcf8..a353ce0 100644
--- a/arch/arm/mach-msm/spm.h
+++ b/arch/arm/mach-msm/spm.h
@@ -127,93 +127,29 @@
/* Public functions */
-/**
- * msm_spm_set_low_power_mode() - Configure SPM start address for low power mode
- * @mode: SPM LPM mode to enter
- * @notify_rpm: Notify RPM in this mode
- */
int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm);
-
-/**
- * msm_spm_set_vdd(): Set core voltage
- * @cpu: core id
- * @vlevel: Encoded PMIC data.
- */
int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel);
-
-/**
- * msm_spm_get_vdd(): Get core voltage
- * @cpu: core id
- * @return: Returns encoded PMIC data.
- */
unsigned int msm_spm_get_vdd(unsigned int cpu);
-
-/**
- * msm_spm_turn_on_cpu_rail(): Power on cpu rail before turning on core
- * @cpu: core id
- */
int msm_spm_turn_on_cpu_rail(unsigned int cpu);
/* Internal low power management specific functions */
-/**
- * msm_spm_reinit(): Reinitialize SPM registers
- */
void msm_spm_reinit(void);
-
-/**
- * msm_spm_init(): Board initalization function
- * @data: platform specific SPM register configuration data
- * @nr_devs: Number of SPM devices being initialized
- */
int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs);
-
-/**
- * msm_spm_device_init(): Device tree initialization function
- */
int msm_spm_device_init(void);
#if defined(CONFIG_MSM_L2_SPM)
/* Public functions */
-/**
- * msm_spm_l2_set_low_power_mode(): Configure L2 SPM start address
- * for low power mode
- * @mode: SPM LPM mode to enter
- * @notify_rpm: Notify RPM in this mode
- */
int msm_spm_l2_set_low_power_mode(unsigned int mode, bool notify_rpm);
-
-/**
- * msm_spm_apcs_set_vdd(): Set Apps processor core sub-system voltage
- * @vlevel: Encoded PMIC data.
- */
int msm_spm_apcs_set_vdd(unsigned int vlevel);
-
-/**
- * msm_spm_apcs_set_phase(): Set number of SMPS phases.
- * phase_cnt: Number of phases to be set active
- */
int msm_spm_apcs_set_phase(unsigned int phase_cnt);
-
-/** msm_spm_enable_fts_lpm() : Enable FTS to switch to low power
- * when the cores are in low power modes
- * @mode: The mode configuration for FTS
- */
int msm_spm_enable_fts_lpm(uint32_t mode);
/* Internal low power management specific functions */
-/**
- * msm_spm_l2_init(): Board initialization function
- * @data: SPM target specific register configuration
- */
int msm_spm_l2_init(struct msm_spm_platform_data *data);
-
-/**
- * msm_spm_l2_reinit(): Reinitialize L2 SPM registers
- */
void msm_spm_l2_reinit(void);
#else
diff --git a/arch/arm/mach-msm/spm_devices.c b/arch/arm/mach-msm/spm_devices.c
index 3fe3bd7..b378d3b 100644
--- a/arch/arm/mach-msm/spm_devices.c
+++ b/arch/arm/mach-msm/spm_devices.c
@@ -57,6 +57,11 @@
info->err = msm_spm_drv_set_vdd(&dev->reg_data, info->vlevel);
}
+/**
+ * msm_spm_set_vdd(): Set core voltage
+ * @cpu: core id
+ * @vlevel: Encoded PMIC data.
+ */
int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel)
{
struct msm_spm_vdd_info info;
@@ -91,6 +96,11 @@
}
EXPORT_SYMBOL(msm_spm_set_vdd);
+/**
+ * msm_spm_get_vdd(): Get core voltage
+ * @cpu: core id
+ * @return: Returns encoded PMIC data.
+ */
unsigned int msm_spm_get_vdd(unsigned int cpu)
{
struct msm_spm_device *dev;
@@ -166,6 +176,10 @@
return ret;
}
+/**
+ * msm_spm_turn_on_cpu_rail(): Power on cpu rail before turning on core
+ * @cpu: core id
+ */
int msm_spm_turn_on_cpu_rail(unsigned int cpu)
{
uint32_t val = 0;
@@ -208,6 +222,11 @@
}
EXPORT_SYMBOL(msm_spm_reinit);
+/**
+ * msm_spm_set_low_power_mode() - Configure SPM start address for low power mode
+ * @mode: SPM LPM mode to enter
+ * @notify_rpm: Notify RPM in this mode
+ */
int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
{
struct msm_spm_device *dev = &__get_cpu_var(msm_cpu_spm_device);
@@ -215,7 +234,11 @@
}
EXPORT_SYMBOL(msm_spm_set_low_power_mode);
-/* Board file init function */
+/**
+ * msm_spm_init(): Board initalization function
+ * @data: platform specific SPM register configuration data
+ * @nr_devs: Number of SPM devices being initialized
+ */
int __init msm_spm_init(struct msm_spm_platform_data *data, int nr_devs)
{
unsigned int cpu;
@@ -238,6 +261,12 @@
#ifdef CONFIG_MSM_L2_SPM
+/**
+ * msm_spm_l2_set_low_power_mode(): Configure L2 SPM start address
+ * for low power mode
+ * @mode: SPM LPM mode to enter
+ * @notify_rpm: Notify RPM in this mode
+ */
int msm_spm_l2_set_low_power_mode(unsigned int mode, bool notify_rpm)
{
return msm_spm_dev_set_low_power_mode(
@@ -251,12 +280,20 @@
}
EXPORT_SYMBOL(msm_spm_l2_reinit);
+/**
+ * msm_spm_apcs_set_vdd(): Set Apps processor core sub-system voltage
+ * @vlevel: Encoded PMIC data.
+ */
int msm_spm_apcs_set_vdd(unsigned int vlevel)
{
return msm_spm_drv_set_vdd(&msm_spm_l2_device.reg_data, vlevel);
}
EXPORT_SYMBOL(msm_spm_apcs_set_vdd);
+/**
+ * msm_spm_apcs_set_phase(): Set number of SMPS phases.
+ * phase_cnt: Number of phases to be set active
+ */
int msm_spm_apcs_set_phase(unsigned int phase_cnt)
{
return msm_spm_drv_set_pmic_data(&msm_spm_l2_device.reg_data,
@@ -264,6 +301,10 @@
}
EXPORT_SYMBOL(msm_spm_apcs_set_phase);
+/** msm_spm_enable_fts_lpm() : Enable FTS to switch to low power
+ * when the cores are in low power modes
+ * @mode: The mode configuration for FTS
+ */
int msm_spm_enable_fts_lpm(uint32_t mode)
{
return msm_spm_drv_set_pmic_data(&msm_spm_l2_device.reg_data,
@@ -271,7 +312,10 @@
}
EXPORT_SYMBOL(msm_spm_enable_fts_lpm);
-/* Board file init function */
+/**
+ * msm_spm_l2_init(): Board initialization function
+ * @data: SPM target specific register configuration
+ */
int __init msm_spm_l2_init(struct msm_spm_platform_data *data)
{
return msm_spm_dev_init(&msm_spm_l2_device, data);
@@ -453,6 +497,9 @@
},
};
+/**
+ * msm_spm_device_init(): Device tree initialization function
+ */
int __init msm_spm_device_init(void)
{
return platform_driver_register(&msm_spm_device_driver);
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index e5cc4ec..ea9337d 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -33,7 +33,6 @@
#include <asm/current.h>
-#include <mach/peripheral-loader.h>
#include <mach/socinfo.h>
#include <mach/subsystem_notif.h>
#include <mach/subsystem_restart.h>
@@ -178,6 +177,20 @@
spin_unlock_irqrestore(&subsys->track.s_lock, flags);
}
+/**
+ * subsytem_default_online() - Mark a subsystem as online by default
+ * @dev: subsystem to mark as online
+ *
+ * Marks a subsystem as "online" without increasing the reference count
+ * on the subsystem. This is typically used by subsystems that are already
+ * online when the kernel boots up.
+ */
+void subsys_default_online(struct subsys_device *dev)
+{
+ subsys_set_state(dev, SUBSYS_ONLINE);
+}
+EXPORT_SYMBOL(subsys_default_online);
+
static struct device_attribute subsys_attrs[] = {
__ATTR_RO(name),
__ATTR_RO(state),
@@ -214,7 +227,7 @@
/* MSM 8x60 restart ordering info */
static const char * const _order_8x60_all[] = {
- "external_modem", "modem", "lpass"
+ "external_modem", "modem", "adsp"
};
DEFINE_SINGLE_RESTART_ORDER(orders_8x60_all, _order_8x60_all);
@@ -671,6 +684,18 @@
}
name = dev->desc->name;
+
+ /*
+ * If a system reboot/shutdown is underway, ignore subsystem errors.
+ * However, print a message so that we know that a subsystem behaved
+ * unexpectedly here.
+ */
+ if (system_state == SYSTEM_RESTART
+ || system_state == SYSTEM_POWER_OFF) {
+ pr_err("%s crashed during a system poweroff/shutdown.\n", name);
+ return -EBUSY;
+ }
+
pr_info("Restart sequence requested for %s, restart_level = %d.\n",
name, restart_level);
@@ -813,7 +838,6 @@
subsys->dev.parent = desc->dev;
subsys->dev.bus = &subsys_bus_type;
subsys->dev.release = subsys_device_release;
- subsys->track.state = SUBSYS_ONLINE; /* Until proper refcounting */
subsys->notify = subsys_notif_add_subsys(desc->name);
subsys->restart_order = update_restart_order(subsys);
diff --git a/arch/arm/mach-msm/sysmon.c b/arch/arm/mach-msm/sysmon.c
index 02ba5ea..112daca 100644
--- a/arch/arm/mach-msm/sysmon.c
+++ b/arch/arm/mach-msm/sysmon.c
@@ -43,6 +43,7 @@
struct completion resp_ready;
char rx_buf[RX_BUF_SIZE];
enum transports transport;
+ struct device *dev;
};
static struct sysmon_subsys subsys[SYSMON_NUM_SS] = {
@@ -138,6 +139,9 @@
char tx_buf[TX_BUF_SIZE];
int ret;
+ if (ss->dev == NULL)
+ return -ENODEV;
+
if (dest_ss < 0 || dest_ss >= SYSMON_NUM_SS ||
notif < 0 || notif >= SUBSYS_NOTIF_TYPE_COUNT ||
event_ss == NULL)
@@ -178,6 +182,9 @@
size_t prefix_len = ARRAY_SIZE(expect) - 1;
int ret;
+ if (ss->dev == NULL)
+ return -ENODEV;
+
if (dest_ss < 0 || dest_ss >= SYSMON_NUM_SS)
return -EINVAL;
@@ -214,6 +221,9 @@
size_t prefix_len = ARRAY_SIZE(expect) - 1;
int ret;
+ if (ss->dev == NULL)
+ return -ENODEV;
+
if (dest_ss < 0 || dest_ss >= SYSMON_NUM_SS ||
buf == NULL || len == 0)
return -EINVAL;
@@ -293,6 +303,7 @@
default:
return -EINVAL;
}
+ ss->dev = &pdev->dev;
return 0;
}
@@ -301,6 +312,9 @@
{
struct sysmon_subsys *ss = &subsys[pdev->id];
+ ss->dev = NULL;
+
+ mutex_lock(&ss->lock);
switch (ss->transport) {
case TRANSPORT_SMD:
smd_close(ss->chan);
@@ -309,6 +323,7 @@
hsic_sysmon_close(HSIC_SYSMON_DEV_EXT_MODEM);
break;
}
+ mutex_unlock(&ss->lock);
return 0;
}
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index b61604a..3af066d 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -23,12 +23,14 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/percpu.h>
+#include <linux/mm.h>
#include <asm/localtimer.h>
#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/sched_clock.h>
#include <asm/smp_plat.h>
+#include <asm/user_accessible_timer.h>
#include <mach/msm_iomap.h>
#include <mach/irqs.h>
#include <mach/socinfo.h>
@@ -1161,6 +1163,16 @@
}
msm_sched_clock_init();
+ if (use_user_accessible_timers()) {
+ if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_apq8064()) {
+ struct msm_clock *gtclock = &msm_clocks[MSM_CLOCK_GPT];
+ void __iomem *addr = gtclock->regbase +
+ TIMER_COUNT_VAL + global_timer_offset;
+ setup_user_timer_offset(virt_to_phys(addr)&0xfff);
+ set_user_accessible_timer_flag(true);
+ }
+ }
+
#ifdef ARCH_HAS_READ_CURRENT_TIMER
if (is_smp()) {
__raw_writel(1,
diff --git a/arch/arm/mach-msm/timer_page.c b/arch/arm/mach-msm/timer_page.c
new file mode 100644
index 0000000..24d2a35
--- /dev/null
+++ b/arch/arm/mach-msm/timer_page.c
@@ -0,0 +1,36 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/export.h>
+#include <asm/user_accessible_timer.h>
+#include "mach/socinfo.h"
+#include "mach/msm_iomap.h"
+
+#include "timer.h"
+
+inline int get_timer_page_address(void)
+{
+ if (!use_user_accessible_timers())
+ return ARM_USER_ACCESSIBLE_TIMERS_INVALID_PAGE;
+
+ if (cpu_is_msm8960())
+ return MSM8960_TMR0_PHYS;
+ else if (cpu_is_msm8930())
+ return MSM8930_TMR0_PHYS;
+ else if (cpu_is_apq8064())
+ return APQ8064_TMR0_PHYS;
+ else
+ return ARM_USER_ACCESSIBLE_TIMERS_INVALID_PAGE;
+}
+EXPORT_SYMBOL(get_timer_page_address);
+
diff --git a/arch/arm/mach-msm/trace_msm_low_power.h b/arch/arm/mach-msm/trace_msm_low_power.h
new file mode 100644
index 0000000..4e9da85
--- /dev/null
+++ b/arch/arm/mach-msm/trace_msm_low_power.h
@@ -0,0 +1,154 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM msm_low_power
+
+#if !defined(_TRACE_MSM_LOW_POWER_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_MSM_LOW_POWER_H_
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(msm_pm_enter,
+
+ TP_PROTO(unsigned int cpu, uint32_t latency,
+ uint32_t sleep_us, uint32_t wake_up),
+
+ TP_ARGS(cpu, latency, sleep_us, wake_up),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, cpu)
+ __field(uint32_t, latency)
+ __field(uint32_t, sleep_us)
+ __field(uint32_t, wake_up)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->latency = latency;
+ __entry->sleep_us = sleep_us;
+ __entry->wake_up = wake_up;
+ ),
+
+ TP_printk("cpu: %u latency: %uus sleep: %uus wake_up: %u",
+ __entry->cpu,
+ __entry->latency,
+ __entry->sleep_us,
+ __entry->wake_up)
+);
+
+DEFINE_EVENT(msm_pm_enter, msm_pm_enter_pc,
+
+ TP_PROTO(unsigned int cpu, uint32_t latency,
+ uint32_t sleep_us, uint32_t wake_up),
+
+ TP_ARGS(cpu, latency, sleep_us, wake_up)
+);
+
+DEFINE_EVENT(msm_pm_enter, msm_pm_enter_ret,
+
+ TP_PROTO(unsigned int cpu, uint32_t latency,
+ uint32_t sleep_us, uint32_t wake_up),
+
+ TP_ARGS(cpu, latency, sleep_us, wake_up)
+);
+
+DEFINE_EVENT(msm_pm_enter, msm_pm_enter_spc,
+
+ TP_PROTO(unsigned int cpu, uint32_t latency,
+ uint32_t sleep_us, uint32_t wake_up),
+
+ TP_ARGS(cpu, latency, sleep_us, wake_up)
+);
+
+DEFINE_EVENT(msm_pm_enter, msm_pm_enter_wfi,
+
+ TP_PROTO(unsigned int cpu, uint32_t latency,
+ uint32_t sleep_us, uint32_t wake_up),
+
+ TP_ARGS(cpu, latency, sleep_us, wake_up)
+);
+
+DECLARE_EVENT_CLASS(msm_pm_exit,
+
+ TP_PROTO(unsigned int cpu, bool success),
+
+ TP_ARGS(cpu, success),
+
+ TP_STRUCT__entry(
+ __field(unsigned int , cpu)
+ __field(int, success)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->success = success;
+ ),
+
+ TP_printk("cpu:%u success:%d",
+ __entry->cpu,
+ __entry->success)
+);
+
+DEFINE_EVENT(msm_pm_exit, msm_pm_exit_pc,
+
+ TP_PROTO(unsigned int cpu, bool success),
+
+ TP_ARGS(cpu, success)
+);
+
+DEFINE_EVENT(msm_pm_exit, msm_pm_exit_ret,
+
+ TP_PROTO(unsigned int cpu, bool success),
+
+ TP_ARGS(cpu, success)
+);
+
+DEFINE_EVENT(msm_pm_exit, msm_pm_exit_spc,
+
+ TP_PROTO(unsigned int cpu, bool success),
+
+ TP_ARGS(cpu, success)
+);
+
+DEFINE_EVENT(msm_pm_exit, msm_pm_exit_wfi,
+
+ TP_PROTO(unsigned int cpu, bool success),
+
+ TP_ARGS(cpu, success)
+);
+
+TRACE_EVENT(lpm_resources,
+
+ TP_PROTO(uint32_t sleep_value , char *name),
+
+ TP_ARGS(sleep_value, name),
+
+ TP_STRUCT__entry(
+ __field(uint32_t , sleep_value)
+ __string(name, name)
+ ),
+
+ TP_fast_assign(
+ __entry->sleep_value = sleep_value;
+ __assign_str(name, name);
+ ),
+
+ TP_printk("name:%s sleep_value:%d",
+ __get_str(name),
+ __entry->sleep_value)
+);
+#endif
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE trace_msm_low_power
+#include <trace/define_trace.h>
diff --git a/arch/arm/mach-msm/trace_rpm_smd.h b/arch/arm/mach-msm/trace_rpm_smd.h
new file mode 100644
index 0000000..eff4860
--- /dev/null
+++ b/arch/arm/mach-msm/trace_rpm_smd.h
@@ -0,0 +1,79 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM rpm_smd
+
+#if !defined(_TRACE_RPM_SMD_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_RPM_SMD_H
+
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(rpm_ack_recd,
+
+ TP_PROTO(unsigned int irq, unsigned int msg_id),
+
+ TP_ARGS(irq, msg_id),
+
+ TP_STRUCT__entry(
+ __field(int, irq)
+ __field(int, msg_id)
+ ),
+
+ TP_fast_assign(
+ __entry->irq = irq;
+ __entry->msg_id = msg_id;
+ ),
+
+ TP_printk("ctx:%s id:%d",
+ __entry->irq ? "noslp" : "sleep",
+ __entry->msg_id)
+);
+
+TRACE_EVENT(rpm_send_message,
+
+ TP_PROTO(unsigned int irq, unsigned int set, unsigned int rsc_type,
+ unsigned int rsc_id, unsigned int msg_id),
+
+ TP_ARGS(irq, set, rsc_type, rsc_id, msg_id),
+
+ TP_STRUCT__entry(
+ __field(u32, irq)
+ __field(u32, set)
+ __field(u32, rsc_type)
+ __field(u32, rsc_id)
+ __field(u32, msg_id)
+ __array(char, name, 5)
+ ),
+
+ TP_fast_assign(
+ __entry->irq = irq;
+ __entry->name[4] = 0;
+ __entry->set = set;
+ __entry->rsc_type = rsc_type;
+ __entry->rsc_id = rsc_id;
+ __entry->msg_id = msg_id;
+ memcpy(__entry->name, &rsc_type, sizeof(uint32_t));
+
+ ),
+
+ TP_printk("ctx:%s set:%s rsc_type:0x%08x(%s), rsc_id:0x%08x, id:%d",
+ __entry->irq ? "noslp" : "sleep",
+ __entry->set ? "slp" : "act",
+ __entry->rsc_type, __entry->name,
+ __entry->rsc_id, __entry->msg_id)
+);
+#endif
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE trace_rpm_smd
+#include <trace/define_trace.h>
diff --git a/arch/arm/mach-msm/wdog_debug.c b/arch/arm/mach-msm/wdog_debug.c
index 08dd9ce..8b39d26 100644
--- a/arch/arm/mach-msm/wdog_debug.c
+++ b/arch/arm/mach-msm/wdog_debug.c
@@ -43,6 +43,11 @@
value = readl_relaxed(wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
value &= ~BIT(WDOG_DEBUG_EN);
writel_relaxed(value, wdog_data->base + GCC_WDOG_DEBUG_OFFSET);
+
+ /* Ensure the WDOG_DEBUG_EN status has changed */
+ while (readl_relaxed(wdog_data->base + GCC_WDOG_DEBUG_OFFSET) &
+ BIT(WDOG_DEBUG_EN))
+ ;
}
EXPORT_SYMBOL(msm_disable_wdog_debug);
diff --git a/arch/arm/mm/cache-pl310-erp.c b/arch/arm/mm/cache-pl310-erp.c
index ad75143..191060f 100644
--- a/arch/arm/mm/cache-pl310-erp.c
+++ b/arch/arm/mm/cache-pl310-erp.c
@@ -34,6 +34,7 @@
unsigned int slverr;
unsigned int decerr;
void __iomem *base;
+ unsigned int intr_mask_reg;
};
#define ECNTR BIT(0)
@@ -128,19 +129,20 @@
static void pl310_mask_int(struct pl310_drv_data *p, bool enable)
{
- uint16_t mask;
-
+ /* L2CC register contents needs to be saved
+ * as it's power rail will be removed during suspend
+ */
if (enable)
- mask = 0x1FF;
+ p->intr_mask_reg = 0x1FF;
else
- mask = 0x0;
+ p->intr_mask_reg = 0x0;
- writel_relaxed(mask, p->base + L2X0_INTR_MASK);
+ writel_relaxed(p->intr_mask_reg, p->base + L2X0_INTR_MASK);
/* Make sure Mask is updated */
mb();
- pr_debug("Mask interrupt %x\n",
+ pr_debug("Mask interrupt 0%x\n",
readl_relaxed(p->base + L2X0_INTR_MASK));
}
@@ -258,12 +260,42 @@
return 0;
}
+#ifdef CONFIG_PM
+static int pl310_suspend(struct device *dev)
+{
+ struct pl310_drv_data *p = dev_get_drvdata(dev);
+
+ disable_irq(p->irq);
+
+ return 0;
+}
+
+static int pl310_resume_early(struct device *dev)
+{
+ struct pl310_drv_data *p = dev_get_drvdata(dev);
+
+ pl310_mask_int(p, true);
+
+ enable_irq(p->irq);
+
+ return 0;
+}
+
+static const struct dev_pm_ops pl310_cache_pm_ops = {
+ .suspend = pl310_suspend,
+ .resume_early = pl310_resume_early,
+};
+#endif
+
static struct platform_driver pl310_cache_erp_driver = {
.probe = pl310_cache_erp_probe,
.remove = __devexit_p(pl310_cache_erp_remove),
.driver = {
.name = MODULE_NAME,
.owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &pl310_cache_pm_ops,
+#endif
},
};
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 8404601..afaa39d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -314,7 +314,8 @@
core_initcall(consistent_init);
static void *__alloc_from_contiguous(struct device *dev, size_t size,
- pgprot_t prot, struct page **ret_page);
+ pgprot_t prot, struct page **ret_page,
+ bool no_kernel_mapping);
static struct arm_vmregion_head coherent_head = {
.vm_lock = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock),
@@ -343,7 +344,7 @@
if (!IS_ENABLED(CONFIG_CMA))
return 0;
- ptr = __alloc_from_contiguous(NULL, size, prot, &page);
+ ptr = __alloc_from_contiguous(NULL, size, prot, &page, false);
if (ptr) {
coherent_head.vm_start = (unsigned long) ptr;
coherent_head.vm_end = (unsigned long) ptr + size;
@@ -522,12 +523,27 @@
return 0;
}
-static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
+static int __dma_clear_pte(pte_t *pte, pgtable_t token, unsigned long addr,
+ void *data)
+{
+ pte_clear(&init_mm, addr, pte);
+ return 0;
+}
+
+static void __dma_remap(struct page *page, size_t size, pgprot_t prot,
+ bool no_kernel_map)
{
unsigned long start = (unsigned long) page_address(page);
unsigned end = start + size;
+ int (*func)(pte_t *pte, pgtable_t token, unsigned long addr,
+ void *data);
- apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
+ if (no_kernel_map)
+ func = __dma_clear_pte;
+ else
+ func = __dma_update_pte;
+
+ apply_to_page_range(&init_mm, start, size, func, &prot);
dsb();
flush_tlb_kernel_range(start, end);
}
@@ -604,7 +620,8 @@
}
static void *__alloc_from_contiguous(struct device *dev, size_t size,
- pgprot_t prot, struct page **ret_page)
+ pgprot_t prot, struct page **ret_page,
+ bool no_kernel_mapping)
{
unsigned long order = get_order(size);
size_t count = size >> PAGE_SHIFT;
@@ -615,7 +632,7 @@
return NULL;
__dma_clear_buffer(page, size);
- __dma_remap(page, size, prot);
+ __dma_remap(page, size, prot, no_kernel_mapping);
*ret_page = page;
return page_address(page);
@@ -624,15 +641,20 @@
static void __free_from_contiguous(struct device *dev, struct page *page,
size_t size)
{
- __dma_remap(page, size, pgprot_kernel);
+ __dma_remap(page, size, pgprot_kernel, false);
dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
}
static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
{
- prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
- pgprot_writecombine(prot) :
- pgprot_dmacoherent(prot);
+ if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
+ prot = pgprot_writecombine(prot);
+ else if (dma_get_attr(DMA_ATTR_STRONGLY_ORDERED, attrs))
+ prot = pgprot_stronglyordered(prot);
+ /* if non-consistent just pass back what was given */
+ else if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs))
+ prot = pgprot_dmacoherent(prot);
+
return prot;
}
@@ -644,7 +666,7 @@
#define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
#define __alloc_from_pool(dev, size, ret_page, c) NULL
-#define __alloc_from_contiguous(dev, size, prot, ret) NULL
+#define __alloc_from_contiguous(dev, size, prot, ret, w) NULL
#define __free_from_pool(cpu_addr, size) 0
#define __free_from_contiguous(dev, page, size) do { } while (0)
#define __dma_free_remap(cpu_addr, size) do { } while (0)
@@ -667,7 +689,8 @@
static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
- gfp_t gfp, pgprot_t prot, const void *caller)
+ gfp_t gfp, pgprot_t prot, const void *caller,
+ bool no_kernel_mapping)
{
u64 mask = get_coherent_dma_mask(dev);
struct page *page;
@@ -707,7 +730,8 @@
else if (gfp & GFP_ATOMIC)
addr = __alloc_from_pool(dev, size, &page, caller);
else
- addr = __alloc_from_contiguous(dev, size, prot, &page);
+ addr = __alloc_from_contiguous(dev, size, prot, &page,
+ no_kernel_mapping);
if (addr)
*handle = pfn_to_dma(dev, page_to_pfn(page));
@@ -724,12 +748,14 @@
{
pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
void *memory;
+ bool no_kernel_mapping = dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING,
+ attrs);
if (dma_alloc_from_coherent(dev, size, handle, &memory))
return memory;
return __dma_alloc(dev, size, handle, gfp, prot,
- __builtin_return_address(0));
+ __builtin_return_address(0), no_kernel_mapping);
}
/*
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 57f41ca..e2cd0120 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -771,6 +771,9 @@
printk(KERN_NOTICE "Virtual kernel memory layout:\n"
" vector : 0x%08lx - 0x%08lx (%4ld kB)\n"
+#ifdef CONFIG_ARM_USE_USER_ACCESSIBLE_TIMERS
+ " timers : 0x%08lx - 0x%08lx (%4ld kB)\n"
+#endif
#ifdef CONFIG_HAVE_TCM
" DTCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
" ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
@@ -791,6 +794,11 @@
MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
(PAGE_SIZE)),
+#ifdef CONFIG_ARM_USE_USER_ACCESSIBLE_TIMERS
+ MLK(UL(CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE),
+ UL(CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE)
+ + (PAGE_SIZE)),
+#endif
#ifdef CONFIG_HAVE_TCM
MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
MLK(ITCM_OFFSET, (unsigned long) itcm_end),
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index bae23b0..1cb6cba 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -33,6 +33,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/user_accessible_timer.h>
+
#include "mm.h"
/*
@@ -309,6 +311,13 @@
.prot_l1 = PMD_TYPE_TABLE,
.domain = DOMAIN_KERNEL,
},
+ [MT_DEVICE_USER_ACCESSIBLE] = {
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
+ L_PTE_SHARED | L_PTE_USER | L_PTE_RDONLY,
+ .prot_l1 = PMD_TYPE_TABLE,
+ .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
+ .domain = DOMAIN_IO,
+ },
};
const struct mem_type *get_mem_type(unsigned int type)
@@ -764,7 +773,9 @@
const struct mem_type *type;
pgd_t *pgd;
- if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
+ if ((md->virtual != vectors_base() &&
+ md->virtual != get_user_accessible_timers_base()) &&
+ md->virtual < TASK_SIZE) {
printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
" at 0x%08lx in user region\n",
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
@@ -1203,6 +1214,20 @@
mdesc->map_io();
fill_pmd_gaps();
+ if (use_user_accessible_timers()) {
+ /*
+ * Generate a mapping for the timer page.
+ */
+ int page_addr = get_timer_page_address();
+ if (page_addr != ARM_USER_ACCESSIBLE_TIMERS_INVALID_PAGE) {
+ map.pfn = __phys_to_pfn(page_addr);
+ map.virtual = CONFIG_ARM_USER_ACCESSIBLE_TIMER_BASE;
+ map.length = PAGE_SIZE;
+ map.type = MT_DEVICE_USER_ACCESSIBLE;
+ create_mapping(&map, false);
+ }
+ }
+
/*
* Finally flush the caches and tlb to ensure that we're in a
* consistent state wrt the writebuffer. This also ensures that
diff --git a/block/test-iosched.c b/block/test-iosched.c
index 52070ac..71e8669 100644
--- a/block/test-iosched.c
+++ b/block/test-iosched.c
@@ -663,7 +663,7 @@
test_name = ptd->test_info.get_test_case_str_fn(ptd);
else
test_name = "Unknown testcase";
- test_pr_info("%s: Starting test %s\n", __func__, test_name);
+ test_pr_info("%s: Starting test %s", __func__, test_name);
ret = prepare_test(ptd);
if (ret) {
diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
index b5d38d5..8994d6d 100644
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -571,7 +571,6 @@
pm_callback_t callback = NULL;
char *info = NULL;
int error = 0;
- bool put = false;
TRACE_DEVICE(dev);
TRACE_RESUME(0);
@@ -589,7 +588,6 @@
goto Unlock;
pm_runtime_enable(dev);
- put = true;
if (dev->pm_domain) {
info = "power domain ";
@@ -642,9 +640,6 @@
TRACE_RESUME(error);
- if (put)
- pm_runtime_put_sync(dev);
-
return error;
}
@@ -779,6 +774,8 @@
}
device_unlock(dev);
+
+ pm_runtime_put_sync(dev);
}
/**
@@ -1064,12 +1061,16 @@
if (async_error)
return 0;
- pm_runtime_get_noresume(dev);
+ /*
+ * If a device configured to wake up the system from sleep states
+ * has been suspended at run time and there's a resume request pending
+ * for it, this is equivalent to the device signaling wakeup, so the
+ * system suspend operation should be aborted.
+ */
if (pm_runtime_barrier(dev) && device_may_wakeup(dev))
pm_wakeup_event(dev, 0);
if (pm_wakeup_pending()) {
- pm_runtime_put_sync(dev);
async_error = -EBUSY;
return 0;
}
@@ -1142,12 +1143,10 @@
complete_all(&dev->power.completion);
- if (error) {
- pm_runtime_put_sync(dev);
+ if (error)
async_error = error;
- } else if (dev->power.is_suspended) {
+ else if (dev->power.is_suspended)
__pm_runtime_disable(dev, false);
- }
return error;
}
@@ -1240,6 +1239,14 @@
char *info = NULL;
int error = 0;
+ /*
+ * If a device's parent goes into runtime suspend at the wrong time,
+ * it won't be possible to resume the device. To prevent this we
+ * block runtime suspend here, during the prepare phase, and allow
+ * it again during the complete phase.
+ */
+ pm_runtime_get_noresume(dev);
+
device_lock(dev);
dev->power.wakeup_path = device_may_wakeup(dev);
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 00a07a0..0b3ffef 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -649,6 +649,16 @@
block. Or some systems may want the iMem to be dedicated to a
different function.
+config MSM_ADSPRPC
+ tristate "Qualcomm ADSP RPC driver"
+ depends on MSM_AUDIO_QDSP6 || MSM_AUDIO_QDSP6V2
+ default m
+ help
+ Provides a communication mechanism that allows for clients to
+ make remote method invocations across processor boundary to
+ applications DSP processor. Say M if you want to enable this
+ module.
+
config MMC_GENERIC_CSDIO
tristate "Generic sdio driver"
default n
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index c38c26c..8032f0b 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -66,4 +66,5 @@
obj-$(CONFIG_TILE_SROM) += tile-srom.o
obj-$(CONFIG_MSM_ROTATOR) += msm_rotator.o
obj-$(CONFIG_MMC_GENERIC_CSDIO) += csdio.o
-obj-$(CONFIG_DIAG_CHAR) += diag/
\ No newline at end of file
+obj-$(CONFIG_DIAG_CHAR) += diag/
+obj-$(CONFIG_MSM_ADSPRPC) += adsprpc.o
diff --git a/arch/arm/mach-msm/qdsp6v2/adsprpc.c b/drivers/char/adsprpc.c
similarity index 100%
rename from arch/arm/mach-msm/qdsp6v2/adsprpc.c
rename to drivers/char/adsprpc.c
diff --git a/arch/arm/mach-msm/qdsp6v2/adsprpc.h b/drivers/char/adsprpc.h
similarity index 100%
rename from arch/arm/mach-msm/qdsp6v2/adsprpc.h
rename to drivers/char/adsprpc.h
diff --git a/arch/arm/mach-msm/qdsp6v2/adsprpc_shared.h b/drivers/char/adsprpc_shared.h
similarity index 100%
rename from arch/arm/mach-msm/qdsp6v2/adsprpc_shared.h
rename to drivers/char/adsprpc_shared.h
diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h
index 28d0565..de3cf52 100644
--- a/drivers/char/diag/diagchar.h
+++ b/drivers/char/diag/diagchar.h
@@ -29,6 +29,7 @@
#define IN_BUF_SIZE 16384
#define MAX_IN_BUF_SIZE 32768
#define MAX_SYNC_OBJ_NAME_SIZE 32
+#define UINT32_MAX UINT_MAX
/* Size of the buffer used for deframing a packet
reveived from the PC tool*/
#define HDLC_MAX 4096
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 92efd94..7b17ce4 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -358,7 +358,7 @@
}
void diag_add_reg(int j, struct bindpkt_params *params,
- int *success, int *count_entries)
+ int *success, unsigned int *count_entries)
{
*success = 1;
driver->table[j].cmd_code = params->cmd_code;
@@ -380,82 +380,172 @@
(*count_entries)++;
}
+#ifdef CONFIG_DIAG_BRIDGE_CODE
+uint16_t diag_get_remote_device_mask(void)
+{
+ uint16_t remote_dev = 0;
+
+ if (driver->hsic_inited)
+ remote_dev |= (1 << 0);
+ if (driver->diag_smux_enabled)
+ remote_dev |= (1 << 1);
+
+ return remote_dev;
+}
+#else
+inline uint16_t diag_get_remote_device_mask(void) { return 0; }
+#endif
+
long diagchar_ioctl(struct file *filp,
unsigned int iocmd, unsigned long ioarg)
{
- int i, j, count_entries = 0, temp;
- int success = -1;
+ int i, j, temp, success = -1, status;
+ unsigned int count_entries = 0, interim_count = 0;
void *temp_buf;
uint16_t support_list = 0;
- struct diag_dci_client_tbl *params =
- kzalloc(sizeof(struct diag_dci_client_tbl), GFP_KERNEL);
+ struct diag_dci_client_tbl *dci_params;
struct diag_dci_health_stats stats;
- int status;
if (iocmd == DIAG_IOCTL_COMMAND_REG) {
- struct bindpkt_params_per_process *pkt_params =
- (struct bindpkt_params_per_process *) ioarg;
+ struct bindpkt_params_per_process pkt_params;
+ struct bindpkt_params *params;
+ struct bindpkt_params *head_params;
+ if (copy_from_user(&pkt_params, (void *)ioarg,
+ sizeof(struct bindpkt_params_per_process))) {
+ return -EFAULT;
+ }
+ if ((UINT32_MAX/sizeof(struct bindpkt_params)) <
+ pkt_params.count) {
+ pr_warning("diag: integer overflow while multiply\n");
+ return -EFAULT;
+ }
+ params = kzalloc(pkt_params.count*sizeof(
+ struct bindpkt_params), GFP_KERNEL);
+ if (!params) {
+ pr_err("diag: unable to alloc memory\n");
+ return -ENOMEM;
+ } else
+ head_params = params;
+
+ if (copy_from_user(params, pkt_params.params,
+ pkt_params.count*sizeof(struct bindpkt_params))) {
+ kfree(head_params);
+ return -EFAULT;
+ }
mutex_lock(&driver->diagchar_mutex);
for (i = 0; i < diag_max_reg; i++) {
if (driver->table[i].process_id == 0) {
- diag_add_reg(i, pkt_params->params,
- &success, &count_entries);
- if (pkt_params->count > count_entries) {
- pkt_params->params++;
+ diag_add_reg(i, params, &success,
+ &count_entries);
+ if (pkt_params.count > count_entries) {
+ params++;
} else {
mutex_unlock(&driver->diagchar_mutex);
+ kfree(head_params);
return success;
}
}
}
if (i < diag_threshold_reg) {
/* Increase table size by amount required */
- diag_max_reg += pkt_params->count -
+ if (pkt_params.count >= count_entries) {
+ interim_count = pkt_params.count -
count_entries;
+ } else {
+ pr_warning("diag: error in params count\n");
+ kfree(head_params);
+ mutex_unlock(&driver->diagchar_mutex);
+ return -EFAULT;
+ }
+ if (UINT32_MAX - diag_max_reg >=
+ interim_count) {
+ diag_max_reg += interim_count;
+ } else {
+ pr_warning("diag: Integer overflow\n");
+ kfree(head_params);
+ mutex_unlock(&driver->diagchar_mutex);
+ return -EFAULT;
+ }
/* Make sure size doesnt go beyond threshold */
if (diag_max_reg > diag_threshold_reg) {
diag_max_reg = diag_threshold_reg;
pr_info("diag: best case memory allocation\n");
}
+ if (UINT32_MAX/sizeof(struct diag_master_table) <
+ diag_max_reg) {
+ pr_warning("diag: integer overflow\n");
+ kfree(head_params);
+ mutex_unlock(&driver->diagchar_mutex);
+ return -EFAULT;
+ }
temp_buf = krealloc(driver->table,
diag_max_reg*sizeof(struct
diag_master_table), GFP_KERNEL);
if (!temp_buf) {
- diag_max_reg -= pkt_params->count -
- count_entries;
- pr_alert("diag: Insufficient memory for reg.");
+ pr_alert("diag: Insufficient memory for reg.\n");
mutex_unlock(&driver->diagchar_mutex);
+
+ if (pkt_params.count >= count_entries) {
+ interim_count = pkt_params.count -
+ count_entries;
+ } else {
+ pr_warning("diag: params count error\n");
+ mutex_unlock(&driver->diagchar_mutex);
+ kfree(head_params);
+ return -EFAULT;
+ }
+ if (diag_max_reg >= interim_count) {
+ diag_max_reg -= interim_count;
+ } else {
+ pr_warning("diag: Integer underflow\n");
+ mutex_unlock(&driver->diagchar_mutex);
+ kfree(head_params);
+ return -EFAULT;
+ }
+ kfree(head_params);
return 0;
} else {
driver->table = temp_buf;
}
for (j = i; j < diag_max_reg; j++) {
- diag_add_reg(j, pkt_params->params,
- &success, &count_entries);
- if (pkt_params->count > count_entries) {
- pkt_params->params++;
+ diag_add_reg(j, params, &success,
+ &count_entries);
+ if (pkt_params.count > count_entries) {
+ params++;
} else {
mutex_unlock(&driver->diagchar_mutex);
+ kfree(head_params);
return success;
}
}
+ kfree(head_params);
mutex_unlock(&driver->diagchar_mutex);
} else {
mutex_unlock(&driver->diagchar_mutex);
+ kfree(head_params);
pr_err("Max size reached, Pkt Registration failed for"
" Process %d", current->tgid);
}
success = 0;
} else if (iocmd == DIAG_IOCTL_GET_DELAYED_RSP_ID) {
- struct diagpkt_delay_params *delay_params =
- (struct diagpkt_delay_params *) ioarg;
-
- if ((delay_params->rsp_ptr) &&
- (delay_params->size == sizeof(delayed_rsp_id)) &&
- (delay_params->num_bytes_ptr)) {
- *((uint16_t *)delay_params->rsp_ptr) =
- DIAGPKT_NEXT_DELAYED_RSP_ID(delayed_rsp_id);
- *(delay_params->num_bytes_ptr) = sizeof(delayed_rsp_id);
+ struct diagpkt_delay_params delay_params;
+ uint16_t interim_rsp_id;
+ int interim_size;
+ if (copy_from_user(&delay_params, (void *)ioarg,
+ sizeof(struct diagpkt_delay_params)))
+ return -EFAULT;
+ if ((delay_params.rsp_ptr) &&
+ (delay_params.size == sizeof(delayed_rsp_id)) &&
+ (delay_params.num_bytes_ptr)) {
+ interim_rsp_id = DIAGPKT_NEXT_DELAYED_RSP_ID(
+ delayed_rsp_id);
+ if (copy_to_user((void *)delay_params.rsp_ptr,
+ &interim_rsp_id, sizeof(uint16_t)))
+ return -EFAULT;
+ interim_size = sizeof(delayed_rsp_id);
+ if (copy_to_user((void *)delay_params.num_bytes_ptr,
+ &interim_size, sizeof(int)))
+ return -EFAULT;
success = 0;
}
} else if (iocmd == DIAG_IOCTL_DCI_REG) {
@@ -463,7 +553,13 @@
return DIAG_DCI_NO_REG;
if (driver->num_dci_client >= MAX_DCI_CLIENTS)
return DIAG_DCI_NO_REG;
- if (copy_from_user(params, (void *)ioarg,
+ dci_params = kzalloc(sizeof(struct diag_dci_client_tbl),
+ GFP_KERNEL);
+ if (dci_params == NULL) {
+ pr_err("diag: unable to alloc memory\n");
+ return -ENOMEM;
+ }
+ if (copy_from_user(dci_params, (void *)ioarg,
sizeof(struct diag_dci_client_tbl)))
return -EFAULT;
mutex_lock(&driver->dci_mutex);
@@ -476,9 +572,9 @@
if (driver->dci_client_tbl[i].client == NULL) {
driver->dci_client_tbl[i].client = current;
driver->dci_client_tbl[i].list =
- params->list;
+ dci_params->list;
driver->dci_client_tbl[i].signal_type =
- params->signal_type;
+ dci_params->signal_type;
create_dci_log_mask_tbl(driver->
dci_client_tbl[i].dci_log_mask);
create_dci_event_mask_tbl(driver->
@@ -496,6 +592,7 @@
}
}
mutex_unlock(&driver->dci_mutex);
+ kfree(dci_params);
return driver->dci_client_id;
} else if (iocmd == DIAG_IOCTL_DCI_DEINIT) {
success = -1;
@@ -520,25 +617,29 @@
} else if (iocmd == DIAG_IOCTL_DCI_SUPPORT) {
if (driver->ch_dci)
support_list = support_list | DIAG_CON_MPSS;
- *(uint16_t *)ioarg = support_list;
+ if (copy_to_user((void *)ioarg, &support_list,
+ sizeof(uint16_t)))
+ return -EFAULT;
return DIAG_DCI_NO_ERROR;
} else if (iocmd == DIAG_IOCTL_DCI_HEALTH_STATS) {
if (copy_from_user(&stats, (void *)ioarg,
sizeof(struct diag_dci_health_stats)))
return -EFAULT;
for (i = 0; i < MAX_DCI_CLIENTS; i++) {
- params = &(driver->dci_client_tbl[i]);
- if (params->client &&
- params->client->tgid == current->tgid) {
- stats.dropped_logs = params->dropped_logs;
- stats.dropped_events = params->dropped_events;
- stats.received_logs = params->received_logs;
- stats.received_events = params->received_events;
+ dci_params = &(driver->dci_client_tbl[i]);
+ if (dci_params->client &&
+ dci_params->client->tgid == current->tgid) {
+ stats.dropped_logs = dci_params->dropped_logs;
+ stats.dropped_events =
+ dci_params->dropped_events;
+ stats.received_logs = dci_params->received_logs;
+ stats.received_events =
+ dci_params->received_events;
if (stats.reset_status) {
- params->dropped_logs = 0;
- params->dropped_events = 0;
- params->received_logs = 0;
- params->received_events = 0;
+ dci_params->dropped_logs = 0;
+ dci_params->dropped_events = 0;
+ dci_params->received_logs = 0;
+ dci_params->received_events = 0;
}
break;
}
@@ -551,7 +652,7 @@
for (i = 0; i < driver->num_clients; i++)
if (driver->client_map[i].pid == current->tgid)
break;
- if (i == -1)
+ if (i == driver->num_clients)
return -EINVAL;
driver->data_ready[i] |= DEINIT_TYPE;
wake_up_interruptible(&driver->wait_q);
@@ -583,6 +684,10 @@
}
}
}
+ if (driver->logging_mode == SOCKET_MODE)
+ driver->socket_process = current;
+ if (driver->logging_mode == CALLBACK_MODE)
+ driver->callback_process = current;
if (driver->logging_mode == UART_MODE ||
driver->logging_mode == SOCKET_MODE ||
driver->logging_mode == CALLBACK_MODE) {
@@ -590,10 +695,6 @@
driver->mask_check = 0;
driver->logging_mode = MEMORY_DEVICE_MODE;
}
- if (driver->logging_mode == SOCKET_MODE)
- driver->socket_process = current;
- if (driver->logging_mode == CALLBACK_MODE)
- driver->callback_process = current;
driver->logging_process_id = current->tgid;
mutex_unlock(&driver->diagchar_mutex);
if (temp == MEMORY_DEVICE_MODE && driver->logging_mode
@@ -695,6 +796,13 @@
}
#endif /* DIAG over USB */
success = 1;
+ } else if (iocmd == DIAG_IOCTL_REMOTE_DEV) {
+ uint16_t remote_dev = diag_get_remote_device_mask();
+
+ if (copy_to_user((void *)ioarg, &remote_dev, sizeof(uint16_t)))
+ success = -EFAULT;
+ else
+ success = 1;
}
return success;
@@ -1037,15 +1145,15 @@
static int diagchar_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
- int err, ret = 0, pkt_type;
- bool mdm_mask = false;
+ int err, ret = 0, pkt_type, token_offset = 0;
+ bool remote_data = false;
#ifdef DIAG_DEBUG
int length = 0, i;
#endif
struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 };
struct diag_hdlc_dest_type enc = { NULL, NULL, 0 };
void *buf_copy = NULL;
- int payload_size;
+ unsigned int payload_size;
#ifdef CONFIG_DIAG_OVER_USB
if (((driver->logging_mode == USB_MODE) && (!driver->usb_connected)) ||
(driver->logging_mode == NO_LOGGING_MODE)) {
@@ -1056,8 +1164,17 @@
/* Get the packet type F3/log/event/Pkt response */
err = copy_from_user((&pkt_type), buf, 4);
/* First 4 bytes indicate the type of payload - ignore these */
+ if (count < 4) {
+ pr_err("diag: Client sending short data\n");
+ return -EBADMSG;
+ }
payload_size = count - 4;
-
+ if (payload_size > USER_SPACE_DATA) {
+ pr_err("diag: Dropping packet, packet payload size crosses 8KB limit. Current payload size %d\n",
+ payload_size);
+ driver->dropped_count++;
+ return -EBADMSG;
+ }
if (pkt_type == DCI_DATA_TYPE) {
err = copy_from_user(driver->user_space_data, buf + 4,
payload_size);
@@ -1072,14 +1189,16 @@
if (pkt_type == USER_SPACE_DATA_TYPE) {
err = copy_from_user(driver->user_space_data, buf + 4,
payload_size);
+ /* Check for proc_type */
+ if (*(int *)driver->user_space_data == MDM_TOKEN) {
+ remote_data = true;
+ token_offset = 4;
+ payload_size -= 4;
+ buf += 4;
+ }
+
/* Check masks for On-Device logging */
if (driver->mask_check) {
- /* Check if mask is for MDM or MSM */
- if (*(int *)driver->user_space_data == MDM_TOKEN) {
- mdm_mask = true;
- driver->user_space_data += 4;
- buf += 4;
- }
if (!mask_request_validate(driver->user_space_data)) {
pr_alert("diag: mask request Invalid\n");
return -EFAULT;
@@ -1089,31 +1208,34 @@
#ifdef DIAG_DEBUG
pr_debug("diag: user space data %d\n", payload_size);
for (i = 0; i < payload_size; i++)
- pr_debug("\t %x", *((driver->user_space_data)+i));
+ pr_debug("\t %x", *((driver->user_space_data
+ + token_offset)+i));
#endif
#ifdef CONFIG_DIAG_SDIO_PIPE
/* send masks to 9k too */
- if (driver->sdio_ch && mdm_mask) {
+ if (driver->sdio_ch && remote_data) {
wait_event_interruptible(driver->wait_q,
(sdio_write_avail(driver->sdio_ch) >=
payload_size));
if (driver->sdio_ch && (payload_size > 0)) {
sdio_write(driver->sdio_ch, (void *)
- (driver->user_space_data), payload_size);
+ (driver->user_space_data + token_offset),
+ payload_size);
}
}
#endif
#ifdef CONFIG_DIAG_BRIDGE_CODE
/* send masks to 9k too */
- if (driver->hsic_ch && (payload_size > 0) && mdm_mask) {
+ if (driver->hsic_ch && (payload_size > 0) && remote_data) {
/* wait sending mask updates if HSIC ch not ready */
if (driver->in_busy_hsic_write)
wait_event_interruptible(driver->wait_q,
(driver->in_busy_hsic_write != 1));
driver->in_busy_hsic_write = 1;
driver->in_busy_hsic_read_on_device = 0;
- err = diag_bridge_write(driver->user_space_data,
- payload_size);
+ err = diag_bridge_write(
+ driver->user_space_data + token_offset,
+ payload_size);
if (err) {
pr_err("diag: err sending mask to MDM: %d\n",
err);
@@ -1127,11 +1249,12 @@
driver->in_busy_hsic_write = 0;
}
}
- if (driver->diag_smux_enabled && mdm_mask && driver->lcid) {
+ if (driver->diag_smux_enabled && remote_data
+ && driver->lcid) {
if (payload_size > 0) {
err = msm_smux_write(driver->lcid, NULL,
- driver->user_space_data,
- payload_size);
+ driver->user_space_data + token_offset,
+ payload_size);
if (err) {
pr_err("diag:send mask to MDM err %d",
err);
@@ -1141,9 +1264,10 @@
}
#endif
/* send masks to 8k now */
- if (!mdm_mask)
- diag_process_hdlc((void *)(driver->user_space_data),
- payload_size);
+ if (!remote_data)
+ diag_process_hdlc((void *)
+ (driver->user_space_data + token_offset),
+ payload_size);
return 0;
}
@@ -1199,8 +1323,9 @@
if (err) {
/*Free the buffer right away if write failed */
diagmem_free(driver, buf_hdlc, POOL_TYPE_HDLC);
- diagmem_free(driver, (unsigned char *)driver->
- write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
+ if (driver->logging_mode == USB_MODE)
+ diagmem_free(driver, (unsigned char *)driver->
+ write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
ret = -EIO;
goto fail_free_hdlc;
}
@@ -1227,8 +1352,9 @@
if (err) {
/*Free the buffer right away if write failed */
diagmem_free(driver, buf_hdlc, POOL_TYPE_HDLC);
- diagmem_free(driver, (unsigned char *)driver->
- write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
+ if (driver->logging_mode == USB_MODE)
+ diagmem_free(driver, (unsigned char *)driver->
+ write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
ret = -EIO;
goto fail_free_hdlc;
}
@@ -1252,8 +1378,9 @@
if (err) {
/*Free the buffer right away if write failed */
diagmem_free(driver, buf_hdlc, POOL_TYPE_HDLC);
- diagmem_free(driver, (unsigned char *)driver->
- write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
+ if (driver->logging_mode == USB_MODE)
+ diagmem_free(driver, (unsigned char *)driver->
+ write_ptr_svc, POOL_TYPE_WRITE_STRUCT);
ret = -EIO;
goto fail_free_hdlc;
}
diff --git a/drivers/char/diag/diagfwd_hsic.c b/drivers/char/diag/diagfwd_hsic.c
index 56f2fae..7aef01f 100644
--- a/drivers/char/diag/diagfwd_hsic.c
+++ b/drivers/char/diag/diagfwd_hsic.c
@@ -195,7 +195,7 @@
if (actual_size < 0)
pr_err("DIAG in %s: actual_size: %d\n", __func__, actual_size);
- if (driver->usb_mdm_connected)
+ if (driver->usb_mdm_connected && (driver->logging_mode == USB_MODE))
queue_work(driver->diag_bridge_wq, &driver->diag_read_mdm_work);
}
@@ -462,7 +462,7 @@
* If there is no write of the usb mdm data on the
* hsic channel
*/
- if (!driver->in_busy_hsic_write)
+ if (!driver->in_busy_hsic_write && (driver->logging_mode == USB_MODE))
queue_work(driver->diag_bridge_wq, &driver->diag_read_mdm_work);
return 0;
@@ -552,9 +552,9 @@
* If for some reason there was no mdm channel read initiated,
* queue up the reading of data from the mdm channel
*/
- if (!driver->in_busy_hsic_read_on_device)
- queue_work(driver->diag_bridge_wq,
- &driver->diag_read_mdm_work);
+ if (!driver->in_busy_hsic_read_on_device &&
+ (driver->logging_mode == USB_MODE))
+ queue_work(driver->diag_bridge_wq, &driver->diag_read_mdm_work);
}
static int diag_hsic_probe(struct platform_device *pdev)
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 60ca44f..f2e5439 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -181,7 +181,12 @@
msm_rng_dev->base = base;
/* create a handle for clock control */
- msm_rng_dev->prng_clk = clk_get(&pdev->dev, "core_clk");
+ if ((pdev->dev.of_node) && (of_property_read_bool(pdev->dev.of_node,
+ "qcom,msm-rng-iface-clk")))
+ msm_rng_dev->prng_clk = clk_get(&pdev->dev,
+ "iface_clk");
+ else
+ msm_rng_dev->prng_clk = clk_get(&pdev->dev, "core_clk");
if (IS_ERR(msm_rng_dev->prng_clk)) {
dev_err(&pdev->dev, "failed to register clock source\n");
error = -EPERM;
diff --git a/drivers/coresight/coresight-csr.c b/drivers/coresight/coresight-csr.c
index e9ac904..1f6bd1d 100644
--- a/drivers/coresight/coresight-csr.c
+++ b/drivers/coresight/coresight-csr.c
@@ -86,7 +86,7 @@
CSR_UNLOCK(drvdata);
usbbamctrl = csr_readl(drvdata, CSR_USBBAMCTRL);
- usbbamctrl = (usbbamctrl & ~0x3) | BLKSIZE_256;
+ usbbamctrl = (usbbamctrl & ~0x3) | BLKSIZE_2048;
csr_writel(drvdata, usbbamctrl, CSR_USBBAMCTRL);
usbflshctrl = csr_readl(drvdata, CSR_USBFLSHCTRL);
diff --git a/drivers/coresight/coresight-etm.c b/drivers/coresight/coresight-etm.c
index 50bae55..f3fe70f 100644
--- a/drivers/coresight/coresight-etm.c
+++ b/drivers/coresight/coresight-etm.c
@@ -25,8 +25,9 @@
#include <linux/wakelock.h>
#include <linux/sysfs.h>
#include <linux/stat.h>
-#include <linux/mutex.h>
+#include <linux/spinlock.h>
#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/of_coresight.h>
#include <linux/coresight.h>
#include <asm/sections.h>
@@ -191,10 +192,12 @@
struct device *dev;
struct coresight_device *csdev;
struct clk *clk;
- struct mutex mutex;
+ spinlock_t spinlock;
struct wake_lock wake_lock;
int cpu;
uint8_t arch;
+ bool enable;
+ bool os_unlock;
uint8_t nr_addr_cmp;
uint8_t nr_cntr;
uint8_t nr_ext_inp;
@@ -203,7 +206,6 @@
uint8_t reset;
uint32_t mode;
uint32_t ctrl;
- uint8_t ctrl_pwrdwn;
uint32_t trigger_event;
uint32_t startstop_ctrl;
uint32_t enable_event;
@@ -230,12 +232,22 @@
uint32_t ctxid_mask;
uint32_t sync_freq;
uint32_t timestamp_event;
- uint8_t pdcr_pwrup;
bool pcsave_impl;
bool pcsave_enable;
};
-static struct etm_drvdata *etm0drvdata;
+static struct etm_drvdata *etmdrvdata[NR_CPUS];
+
+/*
+ * Memory mapped writes to clear os lock are not supported on Krait v1, v2
+ * and OS lock must be unlocked before any memory mapped access, otherwise
+ * memory mapped reads/writes will be invalid.
+ */
+static void etm_os_unlock(void *info)
+{
+ etm_writel_cp14(0x0, ETMOSLAR);
+ isb();
+}
/*
* ETM clock is derived from the processor clock and gets enabled on a
@@ -339,48 +351,19 @@
etm_readl(drvdata, ETMSR));
}
-static void etm_save_pwrdwn(struct etm_drvdata *drvdata)
-{
- drvdata->ctrl_pwrdwn = BVAL(etm_readl(drvdata, ETMCR), 0);
-}
-
-static void etm_restore_pwrdwn(struct etm_drvdata *drvdata)
-{
- uint32_t etmcr;
-
- etmcr = etm_readl(drvdata, ETMCR);
- etmcr = (etmcr & ~BIT(0)) | drvdata->ctrl_pwrdwn;
- etm_writel(drvdata, etmcr, ETMCR);
-}
-
-static void etm_save_pwrup(struct etm_drvdata *drvdata)
-{
- drvdata->pdcr_pwrup = BVAL(etm_readl_mm(drvdata, ETMPDCR), 3);
-}
-
-static void etm_restore_pwrup(struct etm_drvdata *drvdata)
-{
- uint32_t etmpdcr;
-
- etmpdcr = etm_readl_mm(drvdata, ETMPDCR);
- etmpdcr = (etmpdcr & ~BIT(3)) | (drvdata->pdcr_pwrup << 3);
- etm_writel_mm(drvdata, etmpdcr, ETMPDCR);
-}
-
static void etm_enable_pcsave(void *info)
{
struct etm_drvdata *drvdata = info;
ETM_UNLOCK(drvdata);
- etm_save_pwrup(drvdata);
/*
* ETMPDCR is only accessible via memory mapped interface and so use
* it first to enable power/clock to allow subsequent cp14 accesses.
*/
etm_set_pwrup(drvdata);
etm_clr_pwrdwn(drvdata);
- etm_restore_pwrup(drvdata);
+ etm_clr_pwrup(drvdata);
ETM_LOCK(drvdata);
}
@@ -391,14 +374,8 @@
ETM_UNLOCK(drvdata);
- etm_save_pwrup(drvdata);
- /*
- * ETMPDCR is only accessible via memory mapped interface and so use
- * it first to enable power/clock to allow subsequent cp14 accesses.
- */
- etm_set_pwrup(drvdata);
- etm_set_pwrdwn(drvdata);
- etm_restore_pwrup(drvdata);
+ if (!drvdata->enable)
+ etm_set_pwrdwn(drvdata);
ETM_LOCK(drvdata);
}
@@ -416,12 +393,13 @@
* to allow subsequent cp14 accesses.
*/
etm_set_pwrup(drvdata);
- etm_save_pwrdwn(drvdata);
/*
* Clear power down bit since when this bit is set writes to
- * certain registers might be ignored.
+ * certain registers might be ignored. This is also a pre-requisite
+ * for trace enable.
*/
etm_clr_pwrdwn(drvdata);
+ etm_clr_pwrup(drvdata);
etm_set_prog(drvdata);
etmcr = etm_readl(drvdata, ETMCR);
@@ -463,7 +441,6 @@
etm_writel(drvdata, 0x00000000, ETMVMIDCVR);
etm_clr_prog(drvdata);
- etm_restore_pwrdwn(drvdata);
ETM_LOCK(drvdata);
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
@@ -480,17 +457,29 @@
if (ret)
goto err_clk;
- mutex_lock(&drvdata->mutex);
- /* executing __etm_enable on the cpu whose ETM is being enabled
+ get_online_cpus();
+ spin_lock(&drvdata->spinlock);
+
+ /*
+ * Executing __etm_enable on the cpu whose ETM is being enabled
* ensures that register writes occur when cpu is powered.
*/
- smp_call_function_single(drvdata->cpu, __etm_enable, drvdata, 1);
- mutex_unlock(&drvdata->mutex);
+ ret = smp_call_function_single(drvdata->cpu, __etm_enable, drvdata, 1);
+ if (ret)
+ goto err;
+ drvdata->enable = true;
+
+ spin_unlock(&drvdata->spinlock);
+ put_online_cpus();
wake_unlock(&drvdata->wake_lock);
dev_info(drvdata->dev, "ETM tracing enabled\n");
return 0;
+err:
+ spin_unlock(&drvdata->spinlock);
+ put_online_cpus();
+ clk_disable_unprepare(drvdata->clk);
err_clk:
wake_unlock(&drvdata->wake_lock);
return ret;
@@ -501,20 +490,13 @@
struct etm_drvdata *drvdata = info;
ETM_UNLOCK(drvdata);
- etm_save_pwrdwn(drvdata);
- /*
- * Clear power down bit since when this bit is set writes to
- * certain registers might be ignored.
- */
- etm_clr_pwrdwn(drvdata);
etm_set_prog(drvdata);
/* program trace enable to low by using always false event */
etm_writel(drvdata, 0x6F | BIT(14), ETMTEEVR);
- etm_restore_pwrdwn(drvdata);
- /* Vote for ETM power/clock disable */
- etm_clr_pwrup(drvdata);
+ if (!drvdata->pcsave_enable)
+ etm_set_pwrdwn(drvdata);
ETM_LOCK(drvdata);
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
@@ -526,12 +508,18 @@
wake_lock(&drvdata->wake_lock);
- mutex_lock(&drvdata->mutex);
- /* executing __etm_disable on the cpu whose ETM is being disabled
+ get_online_cpus();
+ spin_lock(&drvdata->spinlock);
+
+ /*
+ * Executing __etm_disable on the cpu whose ETM is being disabled
* ensures that register writes occur when cpu is powered.
*/
smp_call_function_single(drvdata->cpu, __etm_disable, drvdata, 1);
- mutex_unlock(&drvdata->mutex);
+ drvdata->enable = false;
+
+ spin_unlock(&drvdata->spinlock);
+ put_online_cpus();
clk_disable_unprepare(drvdata->clk);
@@ -600,7 +588,7 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
if (val) {
drvdata->mode = ETM_MODE_EXCLUDE;
drvdata->ctrl = 0x0;
@@ -644,7 +632,7 @@
drvdata->sync_freq = 0x80;
drvdata->timestamp_event = 0x406F;
}
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(reset, S_IRUGO | S_IWUSR, etm_show_reset, etm_store_reset);
@@ -667,7 +655,7 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->mode = val & ETM_MODE_ALL;
if (drvdata->mode & ETM_MODE_EXCLUDE)
@@ -694,7 +682,7 @@
drvdata->ctrl |= (BIT(14) | BIT(15));
else
drvdata->ctrl &= ~(BIT(14) | BIT(15));
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
@@ -796,12 +784,13 @@
if (val >= drvdata->nr_addr_cmp)
return -EINVAL;
- /* Use mutex to ensure index doesn't change while it gets dereferenced
- * multiple times within a mutex block elsewhere.
+ /*
+ * Use spinlock to ensure index doesn't change while it gets
+ * dereferenced multiple times within a spinlock block elsewhere.
*/
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->addr_idx = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_idx, S_IRUGO | S_IWUSR, etm_show_addr_idx,
@@ -814,16 +803,16 @@
unsigned long val;
uint8_t idx;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val = drvdata->addr_val[idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -838,17 +827,17 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
drvdata->addr_val[idx] = val;
drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_single, S_IRUGO | S_IWUSR, etm_show_addr_single,
@@ -861,23 +850,23 @@
unsigned long val1, val2;
uint8_t idx;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (idx % 2 != 0) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
(drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val1 = drvdata->addr_val[idx];
val2 = drvdata->addr_val[idx + 1];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2);
}
@@ -895,17 +884,17 @@
if (val1 > val2)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (idx % 2 != 0) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
(drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -914,7 +903,7 @@
drvdata->addr_val[idx + 1] = val2;
drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
drvdata->enable_ctrl1 |= (1 << (idx/2));
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_range, S_IRUGO | S_IWUSR, etm_show_addr_range,
@@ -927,16 +916,16 @@
unsigned long val;
uint8_t idx;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val = drvdata->addr_val[idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -951,11 +940,11 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -963,7 +952,7 @@
drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
drvdata->startstop_ctrl |= (1 << idx);
drvdata->enable_ctrl1 |= BIT(25);
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_start, S_IRUGO | S_IWUSR, etm_show_addr_start,
@@ -976,16 +965,16 @@
unsigned long val;
uint8_t idx;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val = drvdata->addr_val[idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1000,11 +989,11 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
idx = drvdata->addr_idx;
if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -1012,7 +1001,7 @@
drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
drvdata->startstop_ctrl |= (1 << (idx + 16));
drvdata->enable_ctrl1 |= BIT(25);
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_stop, S_IRUGO | S_IWUSR, etm_show_addr_stop,
@@ -1024,9 +1013,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->addr_acctype[drvdata->addr_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1040,9 +1029,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->addr_acctype[drvdata->addr_idx] = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(addr_acctype, S_IRUGO | S_IWUSR, etm_show_addr_acctype,
@@ -1069,12 +1058,13 @@
if (val >= drvdata->nr_cntr)
return -EINVAL;
- /* Use mutex to ensure index doesn't change while it gets dereferenced
- * multiple times within a mutex block elsewhere.
+ /*
+ * Use spinlock to ensure index doesn't change while it gets
+ * dereferenced multiple times within a spinlock block elsewhere.
*/
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->cntr_idx = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(cntr_idx, S_IRUGO | S_IWUSR, etm_show_cntr_idx,
@@ -1086,9 +1076,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->cntr_rld_val[drvdata->cntr_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1102,9 +1092,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->cntr_rld_val[drvdata->cntr_idx] = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(cntr_rld_val, S_IRUGO | S_IWUSR, etm_show_cntr_rld_val,
@@ -1116,9 +1106,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->cntr_event[drvdata->cntr_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1132,9 +1122,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(cntr_event, S_IRUGO | S_IWUSR, etm_show_cntr_event,
@@ -1146,9 +1136,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->cntr_rld_event[drvdata->cntr_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1162,9 +1152,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(cntr_rld_event, S_IRUGO | S_IWUSR, etm_show_cntr_rld_event,
@@ -1176,9 +1166,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->cntr_val[drvdata->cntr_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1192,9 +1182,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->cntr_val[drvdata->cntr_idx] = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(cntr_val, S_IRUGO | S_IWUSR, etm_show_cntr_val,
@@ -1398,12 +1388,13 @@
if (val >= drvdata->nr_ctxid_cmp)
return -EINVAL;
- /* Use mutex to ensure index doesn't change while it gets dereferenced
- * multiple times within a mutex block elsewhere.
+ /*
+ * Use spinlock to ensure index doesn't change while it gets
+ * dereferenced multiple times within a spinlock block elsewhere.
*/
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->ctxid_idx = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(ctxid_idx, S_IRUGO | S_IWUSR, etm_show_ctxid_idx,
@@ -1415,9 +1406,9 @@
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
val = drvdata->ctxid_val[drvdata->ctxid_idx];
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1431,9 +1422,9 @@
if (sscanf(buf, "%lx", &val) != 1)
return -EINVAL;
- mutex_lock(&drvdata->mutex);
+ spin_lock(&drvdata->spinlock);
drvdata->ctxid_val[drvdata->ctxid_idx] = val;
- mutex_unlock(&drvdata->mutex);
+ spin_unlock(&drvdata->spinlock);
return size;
}
static DEVICE_ATTR(ctxid_val, S_IRUGO | S_IWUSR, etm_show_ctxid_val,
@@ -1527,26 +1518,43 @@
static int __etm_store_pcsave(struct etm_drvdata *drvdata, unsigned long val)
{
- int ret;
+ int ret = 0;
ret = clk_prepare_enable(drvdata->clk);
if (ret)
return ret;
- mutex_lock(&drvdata->mutex);
+ get_online_cpus();
+ spin_lock(&drvdata->spinlock);
if (val) {
- smp_call_function_single(drvdata->cpu, etm_enable_pcsave,
- drvdata, 1);
+ if (drvdata->pcsave_enable)
+ goto out;
+
+ ret = smp_call_function_single(drvdata->cpu, etm_enable_pcsave,
+ drvdata, 1);
+ if (ret)
+ goto out;
drvdata->pcsave_enable = true;
+
+ dev_info(drvdata->dev, "PC save enabled\n");
} else {
- smp_call_function_single(drvdata->cpu, etm_disable_pcsave,
- drvdata, 1);
+ if (!drvdata->pcsave_enable)
+ goto out;
+
+ ret = smp_call_function_single(drvdata->cpu, etm_disable_pcsave,
+ drvdata, 1);
+ if (ret)
+ goto out;
drvdata->pcsave_enable = false;
+
+ dev_info(drvdata->dev, "PC save disabled\n");
}
- mutex_unlock(&drvdata->mutex);
+out:
+ spin_unlock(&drvdata->spinlock);
+ put_online_cpus();
clk_disable_unprepare(drvdata->clk);
- return 0;
+ return ret;
}
static ssize_t etm_store_pcsave(struct device *dev,
@@ -1613,15 +1621,42 @@
NULL,
};
-/* Memory mapped writes to clear os lock not supported */
-static void etm_os_unlock(void *unused)
+static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
+ void *hcpu)
{
- unsigned long value = 0x0;
+ unsigned int cpu = (unsigned long)hcpu;
- asm("mcr p14, 1, %0, c1, c0, 4\n\t" : : "r" (value));
- asm("isb\n\t");
+ switch (action & (~CPU_TASKS_FROZEN)) {
+ case CPU_STARTING:
+ if (etmdrvdata[cpu] && !etmdrvdata[cpu]->os_unlock) {
+ spin_lock(&etmdrvdata[cpu]->spinlock);
+ etm_os_unlock(etmdrvdata[cpu]);
+ etmdrvdata[cpu]->os_unlock = true;
+ spin_unlock(&etmdrvdata[cpu]->spinlock);
+ }
+
+ if (etmdrvdata[cpu] && etmdrvdata[cpu]->enable) {
+ spin_lock(&etmdrvdata[cpu]->spinlock);
+ __etm_enable(etmdrvdata[cpu]);
+ spin_unlock(&etmdrvdata[cpu]->spinlock);
+ }
+ break;
+
+ case CPU_DYING:
+ if (etmdrvdata[cpu] && etmdrvdata[cpu]->enable) {
+ spin_lock(&etmdrvdata[cpu]->spinlock);
+ __etm_disable(etmdrvdata[cpu]);
+ spin_unlock(&etmdrvdata[cpu]->spinlock);
+ }
+ break;
+ }
+ return NOTIFY_OK;
}
+static struct notifier_block etm_cpu_notifier = {
+ .notifier_call = etm_cpu_callback,
+};
+
static bool __devinit etm_arch_supported(uint8_t arch)
{
switch (arch) {
@@ -1633,15 +1668,6 @@
return true;
}
-static void __devinit etm_prepare_arch(struct etm_drvdata *drvdata)
-{
- /* Unlock OS lock first to allow memory mapped reads and writes. This
- * is required for Krait pass1
- * */
- etm_os_unlock(NULL);
- smp_call_function(etm_os_unlock, NULL, 1);
-}
-
static void __devinit etm_init_arch_data(void *info)
{
uint32_t etmidr;
@@ -1660,6 +1686,7 @@
* certain registers might be ignored.
*/
etm_clr_pwrdwn(drvdata);
+ etm_clr_pwrup(drvdata);
/* Set prog bit. It will be set from reset but this is included to
* ensure it is set
*/
@@ -1677,19 +1704,17 @@
drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
etm_set_pwrdwn(drvdata);
- /* Vote for ETM power/clock disable */
- etm_clr_pwrup(drvdata);
ETM_LOCK(drvdata);
}
static void __devinit etm_copy_arch_data(struct etm_drvdata *drvdata)
{
- drvdata->arch = etm0drvdata->arch;
- drvdata->nr_addr_cmp = etm0drvdata->nr_addr_cmp;
- drvdata->nr_cntr = etm0drvdata->nr_cntr;
- drvdata->nr_ext_inp = etm0drvdata->nr_ext_inp;
- drvdata->nr_ext_out = etm0drvdata->nr_ext_out;
- drvdata->nr_ctxid_cmp = etm0drvdata->nr_ctxid_cmp;
+ drvdata->arch = etmdrvdata[0]->arch;
+ drvdata->nr_addr_cmp = etmdrvdata[0]->nr_addr_cmp;
+ drvdata->nr_cntr = etmdrvdata[0]->nr_cntr;
+ drvdata->nr_ext_inp = etmdrvdata[0]->nr_ext_inp;
+ drvdata->nr_ext_out = etmdrvdata[0]->nr_ext_out;
+ drvdata->nr_ctxid_cmp = etmdrvdata[0]->nr_ctxid_cmp;
}
static void __devinit etm_init_default_data(struct etm_drvdata *drvdata)
@@ -1774,7 +1799,7 @@
if (!drvdata->base)
return -ENOMEM;
- mutex_init(&drvdata->mutex);
+ spin_lock_init(&drvdata->spinlock);
wake_lock_init(&drvdata->wake_lock, WAKE_LOCK_SUSPEND, "coresight-etm");
drvdata->clk = devm_clk_get(dev, "core_clk");
@@ -1787,23 +1812,32 @@
if (ret)
goto err0;
- drvdata->cpu = count++;
-
ret = clk_prepare_enable(drvdata->clk);
if (ret)
goto err0;
- /* Use CPU0 to populate read-only configuration data for ETM0. For other
- * ETMs copy it over from ETM0.
+ drvdata->cpu = count++;
+
+ get_online_cpus();
+ etmdrvdata[drvdata->cpu] = drvdata;
+
+ if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, NULL, 1))
+ drvdata->os_unlock = true;
+ /*
+ * Use CPU0 to populate read-only configuration data for ETM0. For
+ * other ETMs copy it over from ETM0.
*/
if (drvdata->cpu == 0) {
- etm_prepare_arch(drvdata);
- smp_call_function_single(drvdata->cpu, etm_init_arch_data,
- drvdata, 1);
- etm0drvdata = drvdata;
+ register_hotcpu_notifier(&etm_cpu_notifier);
+ if (smp_call_function_single(drvdata->cpu, etm_init_arch_data,
+ drvdata, 1))
+ dev_err(dev, "ETM arch init failed\n");
} else {
etm_copy_arch_data(drvdata);
}
+
+ put_online_cpus();
+
if (etm_arch_supported(drvdata->arch) == false) {
ret = -EINVAL;
goto err1;
@@ -1821,7 +1855,7 @@
ret = msm_dump_table_register(&dump);
if (ret) {
devm_kfree(dev, baddr);
- dev_err(dev, "ETM REG dump setup failed\n");
+ dev_err(dev, "ETM REG dump setup failed/unsupported\n");
}
} else {
dev_err(dev, "ETM REG dump space allocation failed\n");
@@ -1830,7 +1864,7 @@
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
if (!desc) {
ret = -ENOMEM;
- goto err0;
+ goto err2;
}
desc->type = CORESIGHT_DEV_TYPE_SOURCE;
desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
@@ -1842,7 +1876,7 @@
drvdata->csdev = coresight_register(desc);
if (IS_ERR(drvdata->csdev)) {
ret = PTR_ERR(drvdata->csdev);
- goto err0;
+ goto err2;
}
if (pdev->dev.of_node)
@@ -1864,11 +1898,17 @@
__etm_store_pcsave(drvdata, true);
return 0;
+err2:
+ if (drvdata->cpu == 0)
+ unregister_hotcpu_notifier(&etm_cpu_notifier);
+ wake_lock_destroy(&drvdata->wake_lock);
+ return ret;
err1:
+ if (drvdata->cpu == 0)
+ unregister_hotcpu_notifier(&etm_cpu_notifier);
clk_disable_unprepare(drvdata->clk);
err0:
wake_lock_destroy(&drvdata->wake_lock);
- mutex_destroy(&drvdata->mutex);
return ret;
}
@@ -1878,8 +1918,9 @@
device_remove_file(&drvdata->csdev->dev, &dev_attr_pcsave);
coresight_unregister(drvdata->csdev);
+ if (drvdata->cpu == 0)
+ unregister_hotcpu_notifier(&etm_cpu_notifier);
wake_lock_destroy(&drvdata->wake_lock);
- mutex_destroy(&drvdata->mutex);
return 0;
}
diff --git a/drivers/coresight/coresight-stm.c b/drivers/coresight/coresight-stm.c
index f6a948b..1379c55 100644
--- a/drivers/coresight/coresight-stm.c
+++ b/drivers/coresight/coresight-stm.c
@@ -24,6 +24,7 @@
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include <linux/bitmap.h>
#include <linux/of_coresight.h>
#include <linux/coresight.h>
#include <linux/coresight-stm.h>
@@ -45,44 +46,47 @@
mb(); \
} while (0)
-#define STMDMASTARTR (0xC04)
-#define STMDMASTOPR (0xC08)
-#define STMDMASTATR (0xC0C)
-#define STMDMACTLR (0xC10)
-#define STMDMAIDR (0xCFC)
-#define STMHEER (0xD00)
-#define STMHETER (0xD20)
-#define STMHEMCR (0xD64)
-#define STMHEMASTR (0xDF4)
-#define STMHEFEAT1R (0xDF8)
-#define STMHEIDR (0xDFC)
-#define STMSPER (0xE00)
-#define STMSPTER (0xE20)
-#define STMSPSCR (0xE60)
-#define STMSPMSCR (0xE64)
-#define STMSPOVERRIDER (0xE68)
-#define STMSPMOVERRIDER (0xE6C)
-#define STMSPTRIGCSR (0xE70)
-#define STMTCSR (0xE80)
-#define STMTSSTIMR (0xE84)
-#define STMTSFREQR (0xE8C)
-#define STMSYNCR (0xE90)
-#define STMAUXCR (0xE94)
-#define STMSPFEAT1R (0xEA0)
-#define STMSPFEAT2R (0xEA4)
-#define STMSPFEAT3R (0xEA8)
-#define STMITTRIGGER (0xEE8)
-#define STMITATBDATA0 (0xEEC)
-#define STMITATBCTR2 (0xEF0)
-#define STMITATBID (0xEF4)
-#define STMITATBCTR0 (0xEF8)
+#define STMDMASTARTR (0xC04)
+#define STMDMASTOPR (0xC08)
+#define STMDMASTATR (0xC0C)
+#define STMDMACTLR (0xC10)
+#define STMDMAIDR (0xCFC)
+#define STMHEER (0xD00)
+#define STMHETER (0xD20)
+#define STMHEMCR (0xD64)
+#define STMHEMASTR (0xDF4)
+#define STMHEFEAT1R (0xDF8)
+#define STMHEIDR (0xDFC)
+#define STMSPER (0xE00)
+#define STMSPTER (0xE20)
+#define STMSPSCR (0xE60)
+#define STMSPMSCR (0xE64)
+#define STMSPOVERRIDER (0xE68)
+#define STMSPMOVERRIDER (0xE6C)
+#define STMSPTRIGCSR (0xE70)
+#define STMTCSR (0xE80)
+#define STMTSSTIMR (0xE84)
+#define STMTSFREQR (0xE8C)
+#define STMSYNCR (0xE90)
+#define STMAUXCR (0xE94)
+#define STMSPFEAT1R (0xEA0)
+#define STMSPFEAT2R (0xEA4)
+#define STMSPFEAT3R (0xEA8)
+#define STMITTRIGGER (0xEE8)
+#define STMITATBDATA0 (0xEEC)
+#define STMITATBCTR2 (0xEF0)
+#define STMITATBID (0xEF4)
+#define STMITATBCTR0 (0xEF8)
-#define NR_STM_CHANNEL (32)
-#define BYTES_PER_CHANNEL (256)
-#define STM_TRACE_BUF_SIZE (1024)
+#define NR_STM_CHANNEL (32)
+#define BYTES_PER_CHANNEL (256)
+#define STM_TRACE_BUF_SIZE (4096)
+#define STM_USERSPACE_HEADER_SIZE (8)
+#define STM_USERSPACE_MAGIC1_VAL (0xf0)
+#define STM_USERSPACE_MAGIC2_VAL (0xf1)
-#define OST_START_TOKEN (0x30)
-#define OST_VERSION (0x1)
+#define OST_START_TOKEN (0x30)
+#define OST_VERSION (0x1)
enum stm_pkt_type {
STM_PKT_TYPE_DATA = 0x98,
@@ -128,7 +132,7 @@
spinlock_t spinlock;
struct channel_space chs;
bool enable;
- uint32_t entity;
+ DECLARE_BITMAP(entities, OST_ENTITY_MAX);
};
static struct stm_drvdata *stmdrvdata;
@@ -482,7 +486,8 @@
struct stm_drvdata *drvdata = stmdrvdata;
/* we don't support sizes more than 24bits (0 to 23) */
- if (!(drvdata && drvdata->enable && (drvdata->entity & entity_id) &&
+ if (!(drvdata && drvdata->enable &&
+ test_bit(entity_id, drvdata->entities) && size &&
(size < 0x1000000)))
return 0;
@@ -496,13 +501,12 @@
struct stm_drvdata *drvdata = container_of(file->private_data,
struct stm_drvdata, miscdev);
char *buf;
+ uint8_t entity_id, proto_id;
+ uint32_t options;
- if (!drvdata->enable)
+ if (!drvdata->enable || !size)
return -EINVAL;
- if (!(drvdata->entity & OST_ENTITY_DEV_NODE))
- return size;
-
if (size > STM_TRACE_BUF_SIZE)
size = STM_TRACE_BUF_SIZE;
@@ -516,7 +520,32 @@
return -EFAULT;
}
- __stm_trace(STM_OPTION_TIMESTAMPED, OST_ENTITY_DEV_NODE, 0, buf, size);
+ if (size >= STM_USERSPACE_HEADER_SIZE &&
+ buf[0] == STM_USERSPACE_MAGIC1_VAL &&
+ buf[1] == STM_USERSPACE_MAGIC2_VAL) {
+
+ entity_id = buf[2];
+ proto_id = buf[3];
+ options = *(uint32_t *)(buf + 4);
+
+ if (!test_bit(entity_id, drvdata->entities) ||
+ !(size - STM_USERSPACE_HEADER_SIZE)) {
+ kfree(buf);
+ return size;
+ }
+
+ __stm_trace(options, entity_id, proto_id,
+ buf + STM_USERSPACE_HEADER_SIZE,
+ size - STM_USERSPACE_HEADER_SIZE);
+ } else {
+ if (!test_bit(OST_ENTITY_DEV_NODE, drvdata->entities)) {
+ kfree(buf);
+ return size;
+ }
+
+ __stm_trace(STM_OPTION_TIMESTAMPED, OST_ENTITY_DEV_NODE, 0,
+ buf, size);
+ }
kfree(buf);
@@ -594,35 +623,50 @@
static DEVICE_ATTR(port_enable, S_IRUGO | S_IWUSR, stm_show_port_enable,
stm_store_port_enable);
-static ssize_t stm_show_entity(struct device *dev,
+static ssize_t stm_show_entities(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- unsigned long val = drvdata->entity;
+ ssize_t len;
- return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+ len = bitmap_scnprintf(buf, PAGE_SIZE, drvdata->entities,
+ OST_ENTITY_MAX);
+
+ if (PAGE_SIZE - len < 2)
+ len = -EINVAL;
+ else
+ len += scnprintf(buf + len, 2, "\n");
+
+ return len;
}
-static ssize_t stm_store_entity(struct device *dev,
+static ssize_t stm_store_entities(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- unsigned long val;
+ unsigned long val1, val2;
- if (sscanf(buf, "%lx", &val) != 1)
+ if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
return -EINVAL;
- drvdata->entity = val;
+ if (val1 >= OST_ENTITY_MAX)
+ return -EINVAL;
+
+ if (val2)
+ __set_bit(val1, drvdata->entities);
+ else
+ __clear_bit(val1, drvdata->entities);
+
return size;
}
-static DEVICE_ATTR(entity, S_IRUGO | S_IWUSR, stm_show_entity,
- stm_store_entity);
+static DEVICE_ATTR(entities, S_IRUGO | S_IWUSR, stm_show_entities,
+ stm_store_entities);
static struct attribute *stm_attrs[] = {
&dev_attr_hwevent_enable.attr,
&dev_attr_port_enable.attr,
- &dev_attr_entity.attr,
+ &dev_attr_entities.attr,
NULL,
};
@@ -698,7 +742,7 @@
if (ret)
return ret;
- drvdata->entity = OST_ENTITY_ALL;
+ bitmap_fill(drvdata->entities, OST_ENTITY_MAX);
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
if (!desc)
diff --git a/drivers/coresight/coresight-tmc.c b/drivers/coresight/coresight-tmc.c
index 13f69cd..3bb9ec7 100644
--- a/drivers/coresight/coresight-tmc.c
+++ b/drivers/coresight/coresight-tmc.c
@@ -1043,8 +1043,7 @@
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
drvdata->size = SZ_1M;
else
- drvdata->size = (tmc_readl(drvdata, TMC_RSZ) * BYTES_PER_WORD)
- + PAGE_SIZE;
+ drvdata->size = tmc_readl(drvdata, TMC_RSZ) * BYTES_PER_WORD;
clk_disable_unprepare(drvdata->clk);
@@ -1067,7 +1066,8 @@
if (ret)
goto err0;
} else {
- baddr = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
+ baddr = devm_kzalloc(dev, PAGE_SIZE + drvdata->size,
+ GFP_KERNEL);
if (!baddr)
return -ENOMEM;
drvdata->buf = baddr + PAGE_SIZE;
@@ -1075,7 +1075,7 @@
TMC_ETFETB_DUMP_VER;
dump.id = MSM_TMC_ETFETB + etfetb_count;
dump.start_addr = virt_to_phys(baddr);
- dump.end_addr = dump.start_addr + drvdata->size;
+ dump.end_addr = dump.start_addr + PAGE_SIZE + drvdata->size;
ret = msm_dump_table_register(&dump);
/* Don't free the buffer in case of error since it can still
* be used to provide dump collection via the device node
diff --git a/drivers/cpufreq/cpufreq_gov_msm.c b/drivers/cpufreq/cpufreq_gov_msm.c
index 6ddbf4e..8f086aa 100644
--- a/drivers/cpufreq/cpufreq_gov_msm.c
+++ b/drivers/cpufreq/cpufreq_gov_msm.c
@@ -253,6 +253,7 @@
msm_dcvs_freq_set,
msm_dcvs_freq_get,
msm_dcvs_idle_notifier,
+ NULL,
sensor);
if (gov->dcvs_core_id < 0) {
pr_err("Unable to register core for %d\n", cpu);
diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c
index f834ea8..63cdc68 100644
--- a/drivers/cpufreq/cpufreq_interactive.c
+++ b/drivers/cpufreq/cpufreq_interactive.c
@@ -972,6 +972,9 @@
spin_lock_init(&down_cpumask_lock);
mutex_init(&set_speed_lock);
+ /* Kick the kthread to idle */
+ wake_up_process(up_task);
+
idle_notifier_register(&cpufreq_interactive_idle_nb);
INIT_WORK(&inputopen.inputopen_work, cpufreq_interactive_input_open);
return cpufreq_register_governor(&cpufreq_gov_interactive);
diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
index 785ba6c..4b03cfd 100644
--- a/drivers/cpufreq/cpufreq_ondemand.c
+++ b/drivers/cpufreq/cpufreq_ondemand.c
@@ -115,7 +115,12 @@
static struct workqueue_struct *input_wq;
-static DEFINE_PER_CPU(struct work_struct, dbs_refresh_work);
+struct dbs_work_struct {
+ struct work_struct work;
+ unsigned int cpu;
+};
+
+static DEFINE_PER_CPU(struct dbs_work_struct, dbs_refresh_work);
static struct dbs_tuners {
unsigned int sampling_rate;
@@ -831,11 +836,15 @@
return 0;
}
-static void dbs_refresh_callback(struct work_struct *unused)
+static void dbs_refresh_callback(struct work_struct *work)
{
struct cpufreq_policy *policy;
struct cpu_dbs_info_s *this_dbs_info;
- unsigned int cpu = smp_processor_id();
+ struct dbs_work_struct *dbs_work;
+ unsigned int cpu;
+
+ dbs_work = container_of(work, struct dbs_work_struct, work);
+ cpu = dbs_work->cpu;
get_online_cpus();
@@ -877,9 +886,8 @@
return;
}
- for_each_online_cpu(i) {
- queue_work_on(i, input_wq, &per_cpu(dbs_refresh_work, i));
- }
+ for_each_online_cpu(i)
+ queue_work_on(i, input_wq, &per_cpu(dbs_refresh_work, i).work);
}
static int dbs_input_connect(struct input_handler *handler,
@@ -1072,8 +1080,12 @@
for_each_possible_cpu(i) {
struct cpu_dbs_info_s *this_dbs_info =
&per_cpu(od_cpu_dbs_info, i);
+ struct dbs_work_struct *dbs_work =
+ &per_cpu(dbs_refresh_work, i);
+
mutex_init(&this_dbs_info->timer_mutex);
- INIT_WORK(&per_cpu(dbs_refresh_work, i), dbs_refresh_callback);
+ INIT_WORK(&dbs_work->work, dbs_refresh_callback);
+ dbs_work->cpu = i;
}
return cpufreq_register_governor(&cpufreq_gov_ondemand);
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 7a229a5..de060cc 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -1844,6 +1844,8 @@
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->ce_data_in);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_byte_count);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_result_20);
*cmd_ptr_vaddr++ = QCE_SET_LAST_CMD_PTR(cmdlist->get_status_ocu);
@@ -1860,6 +1862,8 @@
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->ce_data_in);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_byte_count);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_result_32);
*cmd_ptr_vaddr++ = QCE_SET_LAST_CMD_PTR(cmdlist->get_status_ocu);
@@ -1877,6 +1881,8 @@
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->ce_data_in);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_byte_count);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_result_20);
*cmd_ptr_vaddr++ = QCE_SET_LAST_CMD_PTR(cmdlist->get_status_ocu);
@@ -1894,6 +1900,8 @@
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->ce_data_in);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
+ *cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_status_wait);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_byte_count);
*cmd_ptr_vaddr++ = QCE_SET_CMD_PTR(cmdlist->get_auth_result_32);
*cmd_ptr_vaddr++ = QCE_SET_LAST_CMD_PTR(cmdlist->get_status_ocu);
diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c
index 1312448..4361263 100644
--- a/drivers/crypto/msm/qce50.c
+++ b/drivers/crypto/msm/qce50.c
@@ -487,7 +487,10 @@
pce->data = auth_cfg;
pce = cmdlistinfo->auth_seg_size;
- pce->data = totallen_in;
+ if (creq->dir == QCE_ENCRYPT)
+ pce->data = totallen_in;
+ else
+ pce->data = totallen_in - creq->authsize;
pce = cmdlistinfo->auth_seg_start;
pce->data = 0;
}
@@ -503,7 +506,8 @@
encr_cfg |= (CRYPTO_ENCR_MODE_XTS << CRYPTO_ENCR_MODE);
break;
case QCE_MODE_CCM:
- encr_cfg |= (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE);
+ encr_cfg |= (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE) |
+ (CRYPTO_LAST_CCM_XFR << CRYPTO_LAST_CCM);
break;
case QCE_MODE_CTR:
default:
@@ -1930,7 +1934,9 @@
auth_cfg &= ~(1 << CRYPTO_USE_HW_KEY_AUTH);
encr_cfg = (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) |
(CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) |
- ((CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE));
+ (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE) |
+ (CRYPTO_LAST_CCM_XFR << CRYPTO_LAST_CCM);
+
key_reg = 8;
}
qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG,
@@ -2161,8 +2167,10 @@
struct qce_cmdlist_info *cmdlistinfo = NULL;
struct qce_cmdlist_info *auth_cmdlistinfo = NULL;
- if (q_req->mode != QCE_MODE_CCM)
+ if (q_req->mode != QCE_MODE_CCM) {
ivsize = crypto_aead_ivsize(aead);
+ auth_cmdlistinfo = &pce_dev->ce_sps.cmdlistptr.aead_sha1_hmac;
+ }
ce_burst_size = pce_dev->ce_sps.ce_burst_size;
if (q_req->dir == QCE_ENCRYPT) {
@@ -2770,13 +2778,11 @@
ce_support->aes_xts = true;
ce_support->ota = false;
ce_support->bam = true;
- if (pce_dev->ce_sps.minor_version) {
+ ce_support->aes_ccm = true;
+ if (pce_dev->ce_sps.minor_version)
ce_support->aligned_only = false;
- ce_support->aes_ccm = true;
- } else {
+ else
ce_support->aligned_only = true;
- ce_support->aes_ccm = false;
- }
return 0;
}
EXPORT_SYMBOL(qce_hw_support);
diff --git a/drivers/crypto/msm/qcrypto.c b/drivers/crypto/msm/qcrypto.c
index 7fc5cab..10f83f3 100644
--- a/drivers/crypto/msm/qcrypto.c
+++ b/drivers/crypto/msm/qcrypto.c
@@ -919,7 +919,7 @@
for (sg = areq->dst; bytes != nbytes; sg++) {
memcpy(sg_virt(sg),
- ((char *)rctx->data + rctx->assoclen + bytes),
+ ((char *)rctx->data + areq->assoclen + bytes),
sg->length);
bytes += sg->length;
}
diff --git a/drivers/gpio/qpnp-pin.c b/drivers/gpio/qpnp-pin.c
index 67a2e6b..527fd1b 100644
--- a/drivers/gpio/qpnp-pin.c
+++ b/drivers/gpio/qpnp-pin.c
@@ -128,7 +128,7 @@
Q_PIN_CFG_PULL,
Q_PIN_CFG_VIN_SEL,
Q_PIN_CFG_OUT_STRENGTH,
- Q_PIN_CFG_SELECT,
+ Q_PIN_CFG_SRC_SEL,
Q_PIN_CFG_MASTER_EN,
Q_PIN_CFG_AOUT_REF,
Q_PIN_CFG_AIN_ROUTE,
@@ -289,7 +289,7 @@
val == 0)
return -EINVAL;
break;
- case Q_PIN_CFG_SELECT:
+ case Q_PIN_CFG_SRC_SEL:
if (q_spec->type == Q_MPP_TYPE &&
(val == QPNP_PIN_SEL_FUNC_1 ||
val == QPNP_PIN_SEL_FUNC_2))
@@ -348,9 +348,9 @@
else if (Q_CHK_INVALID(Q_PIN_CFG_INVERT, q_spec, param->invert))
pr_err("invalid invert polarity value %d for %s %d\n",
param->invert, name, pin);
- else if (Q_CHK_INVALID(Q_PIN_CFG_SELECT, q_spec, param->select))
+ else if (Q_CHK_INVALID(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel))
pr_err("invalid source select value %d for %s %d\n",
- param->select, name, pin);
+ param->src_sel, name, pin);
else if (Q_CHK_INVALID(Q_PIN_CFG_OUT_STRENGTH,
q_spec, param->out_strength))
pr_err("invalid out strength value %d for %s %d\n",
@@ -506,10 +506,10 @@
q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL],
Q_REG_OUT_INVERT_SHIFT, Q_REG_OUT_INVERT_MASK,
param->invert);
- if (Q_HAVE_HW_SP(Q_PIN_CFG_SELECT, q_spec, param->select))
+ if (Q_HAVE_HW_SP(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel))
q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL],
Q_REG_SRC_SEL_SHIFT, Q_REG_SRC_SEL_MASK,
- param->select);
+ param->src_sel);
if (Q_HAVE_HW_SP(Q_PIN_CFG_OUT_STRENGTH, q_spec, param->out_strength))
q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_OUT_CTL],
Q_REG_OUT_STRENGTH_SHIFT, Q_REG_OUT_STRENGTH_MASK,
@@ -828,7 +828,7 @@
param.out_strength = q_reg_get(&q_spec->regs[Q_REG_I_DIG_OUT_CTL],
Q_REG_OUT_STRENGTH_SHIFT,
Q_REG_OUT_STRENGTH_MASK);
- param.select = q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL],
+ param.src_sel = q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL],
Q_REG_SRC_SEL_SHIFT, Q_REG_SRC_SEL_MASK);
param.master_en = q_reg_get(&q_spec->regs[Q_REG_I_EN_CTL],
Q_REG_MASTER_EN_SHIFT,
@@ -855,8 +855,8 @@
¶m.vin_sel);
of_property_read_u32(node, "qcom,out-strength",
¶m.out_strength);
- of_property_read_u32(node, "qcom,src-select",
- ¶m.select);
+ of_property_read_u32(node, "qcom,src-sel",
+ ¶m.src_sel);
of_property_read_u32(node, "qcom,master-en",
¶m.master_en);
of_property_read_u32(node, "qcom,aout-ref",
@@ -942,7 +942,7 @@
cfg->shift = Q_REG_OUT_STRENGTH_SHIFT;
cfg->mask = Q_REG_OUT_STRENGTH_MASK;
break;
- case Q_PIN_CFG_SELECT:
+ case Q_PIN_CFG_SRC_SEL:
cfg->addr = Q_REG_MODE_CTL;
cfg->idx = Q_REG_I_MODE_CTL;
cfg->shift = Q_REG_SRC_SEL_SHIFT;
@@ -1036,7 +1036,7 @@
{ Q_PIN_CFG_PULL, "pull" },
{ Q_PIN_CFG_VIN_SEL, "vin_sel" },
{ Q_PIN_CFG_OUT_STRENGTH, "out_strength" },
- { Q_PIN_CFG_SELECT, "select" },
+ { Q_PIN_CFG_SRC_SEL, "src_sel" },
{ Q_PIN_CFG_MASTER_EN, "master_en" },
{ Q_PIN_CFG_AOUT_REF, "aout_ref" },
{ Q_PIN_CFG_AIN_ROUTE, "ain_route" },
diff --git a/drivers/gpu/ion/ion_cp_heap.c b/drivers/gpu/ion/ion_cp_heap.c
index f9a9212..aa3469c 100644
--- a/drivers/gpu/ion/ion_cp_heap.c
+++ b/drivers/gpu/ion/ion_cp_heap.c
@@ -399,14 +399,16 @@
return ION_CP_ALLOCATE_FAIL;
}
- if (secure_allocation &&
- (cp_heap->umap_count > 0 || cp_heap->kmap_cached_count > 0)) {
- mutex_unlock(&cp_heap->lock);
- pr_err("ION cannot allocate secure memory from heap with "
- "outstanding mappings: User space: %lu, kernel space "
- "(cached): %lu\n", cp_heap->umap_count,
- cp_heap->kmap_cached_count);
- return ION_CP_ALLOCATE_FAIL;
+ /*
+ * The check above already checked for non-secure allocations when the
+ * heap is protected. HEAP_PROTECTED implies that this must be a secure
+ * allocation. If the heap is protected and there are userspace or
+ * cached kernel mappings, something has gone wrong in the security
+ * model.
+ */
+ if (cp_heap->heap_protected == HEAP_PROTECTED) {
+ BUG_ON(cp_heap->umap_count != 0);
+ BUG_ON(cp_heap->kmap_cached_count != 0);
}
/*
@@ -569,18 +571,11 @@
if (!table)
return ERR_PTR(-ENOMEM);
- if (buf->is_secure) {
+ if (buf->is_secure && IS_ALIGNED(buffer->size, SZ_1M)) {
int n_chunks;
int i;
struct scatterlist *sg;
- if (!IS_ALIGNED(buffer->size, SZ_1M)) {
- pr_err("%s: buffer is marked as secure but buffer size %x is not aligned to 1MB\n",
- __func__, buffer->size);
-
- return ERR_PTR(-EINVAL);
- }
-
/* Count number of 1MB chunks. Alignment is already checked. */
n_chunks = buffer->size >> 20;
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index 20f84d6..8699178 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -616,18 +616,15 @@
if (end < start)
goto out;
- down_read(&mm->mmap_sem);
vma = find_vma(mm, start);
if (vma && vma->vm_start < end) {
if (start < vma->vm_start)
- goto out_up;
+ goto out;
if (end > vma->vm_end)
- goto out_up;
+ goto out;
ret = 0;
}
-out_up:
- up_read(&mm->mmap_sem);
out:
return ret;
}
@@ -645,20 +642,12 @@
unsigned long start, end;
struct ion_handle *handle = NULL;
int ret;
+ struct mm_struct *mm = current->active_mm;
if (copy_from_user(&data, (void __user *)arg,
sizeof(struct ion_flush_data)))
return -EFAULT;
- start = (unsigned long) data.vaddr;
- end = (unsigned long) data.vaddr + data.length;
-
- if (check_vaddr_bounds(start, end)) {
- pr_err("%s: virtual address %p is out of bounds\n",
- __func__, data.vaddr);
- return -EINVAL;
- }
-
if (!data.handle) {
handle = ion_import_dma_buf(client, data.fd);
if (IS_ERR(handle)) {
@@ -668,11 +657,27 @@
}
}
+ down_read(&mm->mmap_sem);
+
+ start = (unsigned long) data.vaddr;
+ end = (unsigned long) data.vaddr + data.length;
+
+ if (check_vaddr_bounds(start, end)) {
+ up_read(&mm->mmap_sem);
+ pr_err("%s: virtual address %p is out of bounds\n",
+ __func__, data.vaddr);
+ if (!data.handle)
+ ion_free(client, handle);
+ return -EINVAL;
+ }
+
ret = ion_do_cache_op(client,
data.handle ? data.handle : handle,
data.vaddr, data.offset, data.length,
cmd);
+ up_read(&mm->mmap_sem);
+
if (!data.handle)
ion_free(client, handle);
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 67cb34a..0109d26 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -253,6 +253,13 @@
if (result)
goto unmap_memstore_desc;
+ /*
+ * Set the mpu end to the last "normal" global memory we use.
+ * For the IOMMU, this will be used to restrict access to the
+ * mapped registers.
+ */
+ device->mh.mpu_range = device->mmu.setstate_memory.gpuaddr +
+ device->mmu.setstate_memory.size;
return result;
unmap_memstore_desc:
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index bec19e2..f9d0316 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -38,6 +38,7 @@
/* Command identifiers */
#define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0x2EADBEEF
#define KGSL_CMD_IDENTIFIER 0x2EEDFACE
+#define KGSL_CMD_INTERNAL_IDENTIFIER 0x2EEDD00D
#define KGSL_START_OF_IB_IDENTIFIER 0x2EADEABE
#define KGSL_END_OF_IB_IDENTIFIER 0x2ABEDEAD
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index 8de2c70..4e4843b 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1718,9 +1718,15 @@
eoptimestamp));
if (context_id < KGSL_MEMSTORE_MAX) {
- kgsl_sharedmem_writel(&rb->device->memstore,
+ /* reset per context ts_cmp_enable */
+ kgsl_sharedmem_writel(&device->memstore,
KGSL_MEMSTORE_OFFSET(context_id,
ts_cmp_enable), 0);
+ /* Always reset global timestamp ts_cmp_enable */
+ kgsl_sharedmem_writel(&device->memstore,
+ KGSL_MEMSTORE_OFFSET(
+ KGSL_MEMSTORE_GLOBAL,
+ ts_cmp_enable), 0);
wmb();
}
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index 4c7534c..feced43 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -2586,9 +2586,15 @@
eoptimestamp));
if (context_id < KGSL_MEMSTORE_MAX) {
+ /* reset per context ts_cmp_enable */
kgsl_sharedmem_writel(&device->memstore,
KGSL_MEMSTORE_OFFSET(context_id,
ts_cmp_enable), 0);
+ /* Always reset global timestamp ts_cmp_enable */
+ kgsl_sharedmem_writel(&device->memstore,
+ KGSL_MEMSTORE_OFFSET(
+ KGSL_MEMSTORE_GLOBAL,
+ ts_cmp_enable), 0);
wmb();
}
@@ -2766,12 +2772,12 @@
static struct a3xx_vbif_data a330_vbif[] = {
/* Set up 16 deep read/write request queues */
{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818 },
- { A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818 },
- { A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818 },
- { A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818 },
+ { A3XX_VBIF_IN_RD_LIM_CONF1, 0x00001818 },
+ { A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00001818 },
+ { A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00001818 },
{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303 },
{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818 },
- { A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818 },
+ { A3XX_VBIF_IN_WR_LIM_CONF1, 0x00001818 },
/* Enable WR-REQ */
{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003F },
/* Set up round robin arbitration between both AXI ports */
@@ -2779,10 +2785,10 @@
/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001 },
/* Set up AOOO */
- { A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000FFFF },
- { A3XX_VBIF_OUT_AXI_AOOO, 0xFFFFFFFF },
+ { A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003F },
+ { A3XX_VBIF_OUT_AXI_AOOO, 0x003F003F },
/* Enable 1K sort */
- { A3XX_VBIF_ABIT_SORT, 0x1FFFF },
+ { A3XX_VBIF_ABIT_SORT, 0x0001003F },
{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
/* Disable VBIF clock gating. This is to enable AXI running
* higher frequency than GPU.
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index daa78ed..e069fa5 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -70,6 +70,14 @@
{CP_WAIT_FOR_IDLE, "WAIT4IDL"},
};
+static const struct pm_id_name pm3_nop_values[] = {
+ {KGSL_CONTEXT_TO_MEM_IDENTIFIER, "CTX_SWCH"},
+ {KGSL_CMD_IDENTIFIER, "CMD__EXT"},
+ {KGSL_CMD_INTERNAL_IDENTIFIER, "CMD__INT"},
+ {KGSL_START_OF_IB_IDENTIFIER, "IB_START"},
+ {KGSL_END_OF_IB_IDENTIFIER, "IB___END"},
+};
+
static uint32_t adreno_is_pm4_len(uint32_t word)
{
if (word == INVALID_RB_CMD)
@@ -129,6 +137,28 @@
return "????????";
}
+static bool adreno_is_pm3_nop_value(uint32_t word)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pm3_nop_values); ++i) {
+ if (word == pm3_nop_values[i].id)
+ return 1;
+ }
+ return 0;
+}
+
+static const char *adreno_pm3_nop_name(uint32_t word)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pm3_nop_values); ++i) {
+ if (word == pm3_nop_values[i].id)
+ return pm3_nop_values[i].name;
+ }
+ return "????????";
+}
+
static void adreno_dump_regs(struct kgsl_device *device,
const int *registers, int size)
{
@@ -245,8 +275,13 @@
"%s", adreno_pm4_name(ptr4[j]));
*argp = -(adreno_is_pm4_len(ptr4[j])+1);
} else {
- lx += scnprintf(linebuf + lx, linebuflen - lx,
- "%8.8X", ptr4[j]);
+ if (adreno_is_pm3_nop_value(ptr4[j]))
+ lx += scnprintf(linebuf + lx, linebuflen - lx,
+ "%s", adreno_pm3_nop_name(ptr4[j]));
+ else
+ lx += scnprintf(linebuf + lx, linebuflen - lx,
+ "%8.8X", ptr4[j]);
+
if (*argp > 1)
--*argp;
else if (*argp == 1) {
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index da9daf7..9648f27 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -28,6 +28,14 @@
#define GSL_RB_NOP_SIZEDWORDS 2
+/*
+ * CP DEBUG settings for all cores:
+ * DYNAMIC_CLK_DISABLE [27] - turn off the dynamic clock control
+ * PROG_END_PTR_ENABLE [25] - Allow 128 bit writes to the VBIF
+ */
+
+#define CP_DEBUG_DEFAULT ((1 << 27) | (1 << 25))
+
void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb)
{
BUG_ON(rb->wptr == 0);
@@ -231,7 +239,7 @@
KGSL_DRV_INFO(device, "loading pm4 ucode version: %d\n",
adreno_dev->pm4_fw[0]);
- adreno_regwrite(device, REG_CP_DEBUG, 0x02000000);
+ adreno_regwrite(device, REG_CP_DEBUG, CP_DEBUG_DEFAULT);
adreno_regwrite(device, REG_CP_ME_RAM_WADDR, 0);
for (i = 1; i < adreno_dev->pm4_fw_size; i++)
adreno_regwrite(device, REG_CP_ME_RAM_DATA,
@@ -524,16 +532,18 @@
total_sizedwords += flags & KGSL_CMD_FLAGS_PMODE ? 4 : 0;
/* 2 dwords to store the start of command sequence */
total_sizedwords += 2;
- /*
- * Add CP_COND_EXEC commands to generate CP_INTERRUPT only
- * for submissions from userspace.
- */
- total_sizedwords += (context &&
- !(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) ? 7 : 0;
+ /* internal ib command identifier for the ringbuffer */
+ total_sizedwords += (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE) ? 2 : 0;
+
+ /* Add CP_COND_EXEC commands to generate CP_INTERRUPT */
+ total_sizedwords += context ? 7 : 0;
if (adreno_is_a3xx(adreno_dev))
total_sizedwords += 7;
+ if (adreno_is_a2xx(adreno_dev))
+ total_sizedwords += 2; /* CP_WAIT_FOR_IDLE */
+
total_sizedwords += 2; /* scratchpad ts for recovery */
if (context && context->flags & CTXT_FLAGS_PER_CONTEXT_TS &&
!(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) {
@@ -560,6 +570,11 @@
GSL_RB_WRITE(ringcmds, rcmd_gpu, cp_nop_packet(1));
GSL_RB_WRITE(ringcmds, rcmd_gpu, KGSL_CMD_IDENTIFIER);
+ if (flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE) {
+ GSL_RB_WRITE(ringcmds, rcmd_gpu, cp_nop_packet(1));
+ GSL_RB_WRITE(ringcmds, rcmd_gpu, KGSL_CMD_INTERNAL_IDENTIFIER);
+ }
+
if (flags & KGSL_CMD_FLAGS_PMODE) {
/* disable protected mode error checking */
GSL_RB_WRITE(ringcmds, rcmd_gpu,
@@ -594,6 +609,16 @@
}
timestamp = rb->timestamp[context_id];
+ /* HW Workaround for MMU Page fault
+ * due to memory getting free early before
+ * GPU completes it.
+ */
+ if (adreno_is_a2xx(adreno_dev)) {
+ GSL_RB_WRITE(ringcmds, rcmd_gpu,
+ cp_type3_packet(CP_WAIT_FOR_IDLE, 1));
+ GSL_RB_WRITE(ringcmds, rcmd_gpu, 0x00);
+ }
+
/* scratchpad ts for recovery */
GSL_RB_WRITE(ringcmds, rcmd_gpu, cp_type0_packet(REG_CP_TIMESTAMP, 1));
GSL_RB_WRITE(ringcmds, rcmd_gpu, rb->timestamp[KGSL_MEMSTORE_GLOBAL]);
@@ -647,7 +672,7 @@
rb->timestamp[KGSL_MEMSTORE_GLOBAL]);
}
- if (context && !(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE)) {
+ if (context) {
/* Conditional execution based on memory values */
GSL_RB_WRITE(ringcmds, rcmd_gpu,
cp_type3_packet(CP_COND_EXEC, 4));
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index b8adbe67..c040bf3 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -193,6 +193,52 @@
}
EXPORT_SYMBOL(kgsl_cancel_events);
+int kgsl_memfree_hist_init(void)
+{
+ void *base;
+
+ base = kzalloc(KGSL_MEMFREE_HIST_SIZE, GFP_KERNEL);
+ kgsl_driver.memfree_hist.base_hist_rb = base;
+ if (base == NULL)
+ return -ENOMEM;
+ kgsl_driver.memfree_hist.size = KGSL_MEMFREE_HIST_SIZE;
+ kgsl_driver.memfree_hist.wptr = base;
+ return 0;
+}
+
+void kgsl_memfree_hist_exit(void)
+{
+ kfree(kgsl_driver.memfree_hist.base_hist_rb);
+ kgsl_driver.memfree_hist.base_hist_rb = NULL;
+}
+
+void kgsl_memfree_hist_set_event(unsigned int pid, unsigned int gpuaddr,
+ unsigned int size, int flags)
+{
+ struct kgsl_memfree_hist_elem *p;
+
+ void *base = kgsl_driver.memfree_hist.base_hist_rb;
+ int rbsize = kgsl_driver.memfree_hist.size;
+
+ if (base == NULL)
+ return;
+
+ mutex_lock(&kgsl_driver.memfree_hist_mutex);
+ p = kgsl_driver.memfree_hist.wptr;
+ p->pid = pid;
+ p->gpuaddr = gpuaddr;
+ p->size = size;
+ p->flags = flags;
+
+ kgsl_driver.memfree_hist.wptr++;
+ if ((void *)kgsl_driver.memfree_hist.wptr >= base+rbsize) {
+ kgsl_driver.memfree_hist.wptr =
+ (struct kgsl_memfree_hist_elem *)base;
+ }
+ mutex_unlock(&kgsl_driver.memfree_hist_mutex);
+}
+
+
/* kgsl_get_mem_entry - get the mem_entry structure for the specified object
* @device - Pointer to the device structure
* @ptbase - the pagetable base of the object
@@ -853,13 +899,6 @@
dev_priv->device = device;
filep->private_data = dev_priv;
- /* Get file (per process) private struct */
- dev_priv->process_priv = kgsl_get_process_private(dev_priv);
- if (dev_priv->process_priv == NULL) {
- result = -ENOMEM;
- goto err_freedevpriv;
- }
-
mutex_lock(&device->mutex);
kgsl_check_suspended(device);
@@ -871,21 +910,38 @@
if (result) {
mutex_unlock(&device->mutex);
- goto err_putprocess;
+ goto err_freedevpriv;
}
kgsl_pwrctrl_set_state(device, KGSL_STATE_ACTIVE);
}
device->open_count++;
mutex_unlock(&device->mutex);
+ /*
+ * Get file (per process) private struct. This must be done
+ * after the first start so that the global pagetable mappings
+ * are set up before we create the per-process pagetable.
+ */
+ dev_priv->process_priv = kgsl_get_process_private(dev_priv);
+ if (dev_priv->process_priv == NULL) {
+ result = -ENOMEM;
+ goto err_stop;
+ }
+
KGSL_DRV_INFO(device, "Initialized %s: mmu=%s pagetable_count=%d\n",
device->name, kgsl_mmu_enabled() ? "on" : "off",
kgsl_pagetable_count);
return result;
-err_putprocess:
- kgsl_put_process_private(device, dev_priv->process_priv);
+err_stop:
+ mutex_lock(&device->mutex);
+ device->open_count--;
+ if (device->open_count == 0) {
+ result = device->ftbl->stop(device);
+ kgsl_pwrctrl_set_state(device, KGSL_STATE_INIT);
+ }
+ mutex_unlock(&device->mutex);
err_freedevpriv:
filep->private_data = NULL;
kfree(dev_priv);
@@ -1349,6 +1405,13 @@
if (entry) {
trace_kgsl_mem_free(entry);
+
+ kgsl_memfree_hist_set_event(
+ entry->priv->pid,
+ entry->memdesc.gpuaddr,
+ entry->memdesc.size,
+ entry->memdesc.flags);
+
kgsl_mem_entry_detach_process(entry);
} else {
KGSL_CORE_ERR("invalid gpuaddr %08x\n", param->gpuaddr);
@@ -2328,6 +2391,8 @@
.process_mutex = __MUTEX_INITIALIZER(kgsl_driver.process_mutex),
.ptlock = __SPIN_LOCK_UNLOCKED(kgsl_driver.ptlock),
.devlock = __MUTEX_INITIALIZER(kgsl_driver.devlock),
+ .memfree_hist_mutex =
+ __MUTEX_INITIALIZER(kgsl_driver.memfree_hist_mutex),
};
EXPORT_SYMBOL(kgsl_driver);
@@ -2658,6 +2723,7 @@
kgsl_driver.class = NULL;
}
+ kgsl_memfree_hist_exit();
unregister_chrdev_region(kgsl_driver.major, KGSL_DEVICE_MAX);
}
@@ -2729,6 +2795,9 @@
goto err;
}
+ if (kgsl_memfree_hist_init())
+ KGSL_CORE_ERR("failed to init memfree_hist");
+
return 0;
err:
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index 17a5b67..d22cb6d 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -71,6 +71,23 @@
#define KGSL_STATS_ADD(_size, _stat, _max) \
do { _stat += (_size); if (_stat > _max) _max = _stat; } while (0)
+
+#define KGSL_MEMFREE_HIST_SIZE ((int)(PAGE_SIZE * 2))
+
+struct kgsl_memfree_hist_elem {
+ unsigned int pid;
+ unsigned int gpuaddr;
+ unsigned int size;
+ unsigned int flags;
+};
+
+struct kgsl_memfree_hist {
+ void *base_hist_rb;
+ unsigned int size;
+ struct kgsl_memfree_hist_elem *wptr;
+};
+
+
struct kgsl_device;
struct kgsl_driver {
@@ -98,6 +115,9 @@
void *ptpool;
+ struct mutex memfree_hist_mutex;
+ struct kgsl_memfree_hist memfree_hist;
+
struct {
unsigned int vmalloc;
unsigned int vmalloc_max;
diff --git a/drivers/gpu/msm/kgsl_debugfs.c b/drivers/gpu/msm/kgsl_debugfs.c
index 52097dc..07a5ff4 100644
--- a/drivers/gpu/msm/kgsl_debugfs.c
+++ b/drivers/gpu/msm/kgsl_debugfs.c
@@ -106,6 +106,52 @@
KGSL_DEBUGFS_LOG(mem_log);
KGSL_DEBUGFS_LOG(pwr_log);
+static int memfree_hist_print(struct seq_file *s, void *unused)
+{
+ void *base = kgsl_driver.memfree_hist.base_hist_rb;
+
+ struct kgsl_memfree_hist_elem *wptr = kgsl_driver.memfree_hist.wptr;
+ struct kgsl_memfree_hist_elem *p;
+ char str[16];
+
+ seq_printf(s, "%8s %8s %8s %11s\n",
+ "pid", "gpuaddr", "size", "flags");
+
+ mutex_lock(&kgsl_driver.memfree_hist_mutex);
+ p = wptr;
+ for (;;) {
+ kgsl_get_memory_usage(str, sizeof(str), p->flags);
+ /*
+ * if the ring buffer is not filled up yet
+ * all its empty elems have size==0
+ * just skip them ...
+ */
+ if (p->size)
+ seq_printf(s, "%8d %08x %8d %11s\n",
+ p->pid, p->gpuaddr, p->size, str);
+ p++;
+ if ((void *)p >= base + kgsl_driver.memfree_hist.size)
+ p = (struct kgsl_memfree_hist_elem *) base;
+
+ if (p == kgsl_driver.memfree_hist.wptr)
+ break;
+ }
+ mutex_unlock(&kgsl_driver.memfree_hist_mutex);
+ return 0;
+}
+
+static int memfree_hist_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, memfree_hist_print, inode->i_private);
+}
+
+static const struct file_operations memfree_hist_fops = {
+ .open = memfree_hist_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
void kgsl_device_debugfs_init(struct kgsl_device *device)
{
if (kgsl_debugfs_dir && !IS_ERR(kgsl_debugfs_dir))
@@ -131,6 +177,8 @@
&mem_log_fops);
debugfs_create_file("log_level_pwr", 0644, device->d_debugfs, device,
&pwr_log_fops);
+ debugfs_create_file("memfree_history", 0444, device->d_debugfs, device,
+ &memfree_hist_fops);
/* Create postmortem dump control files */
@@ -190,7 +238,7 @@
entry = rb_entry(node, struct kgsl_mem_entry, node);
m = &entry->memdesc;
- flags[0] = m->priv & KGSL_MEMDESC_GLOBAL ? 'g' : '-';
+ flags[0] = kgsl_memdesc_is_global(m) ? 'g' : '-';
flags[1] = m->flags & KGSL_MEMFLAGS_GPUREADONLY ? 'r' : '-';
flags[2] = get_alignflag(m);
flags[3] = '\0';
diff --git a/drivers/gpu/msm/kgsl_drm.c b/drivers/gpu/msm/kgsl_drm.c
index 2003098..98c7434 100644
--- a/drivers/gpu/msm/kgsl_drm.c
+++ b/drivers/gpu/msm/kgsl_drm.c
@@ -17,6 +17,7 @@
#include "drmP.h"
#include "drm.h"
#include <linux/android_pmem.h>
+#include <linux/msm_ion.h>
#include "kgsl.h"
#include "kgsl_device.h"
@@ -27,7 +28,7 @@
#define DRIVER_AUTHOR "Qualcomm"
#define DRIVER_NAME "kgsl"
#define DRIVER_DESC "KGSL DRM"
-#define DRIVER_DATE "20100127"
+#define DRIVER_DATE "20121107"
#define DRIVER_MAJOR 2
#define DRIVER_MINOR 1
@@ -106,6 +107,7 @@
uint32_t type;
struct kgsl_memdesc memdesc;
struct kgsl_pagetable *pagetable;
+ struct ion_handle *ion_handle;
uint64_t mmap_offset;
int bufcount;
int flags;
@@ -129,6 +131,8 @@
struct list_head wait_list;
};
+static struct ion_client *kgsl_drm_ion_phys_client;
+
static int kgsl_drm_inited = DRM_KGSL_NOT_INITED;
/* This is a global list of all the memory currently mapped in the MMU */
@@ -243,15 +247,50 @@
if (TYPE_IS_PMEM(priv->type)) {
if (priv->type == DRM_KGSL_GEM_TYPE_EBI ||
priv->type & DRM_KGSL_GEM_PMEM_EBI) {
- result = kgsl_sharedmem_ebimem_user(
- &priv->memdesc,
- priv->pagetable,
- obj->size * priv->bufcount);
- if (result) {
- DRM_ERROR(
- "Unable to allocate PMEM memory\n");
- return result;
- }
+ priv->ion_handle = ion_alloc(kgsl_drm_ion_phys_client,
+ obj->size * priv->bufcount, PAGE_SIZE,
+ ION_HEAP(ION_SF_HEAP_ID), 0);
+ if (IS_ERR_OR_NULL(priv->ion_handle)) {
+ DRM_ERROR(
+ "Unable to allocate ION Phys memory handle\n");
+ return -ENOMEM;
+ }
+
+ priv->memdesc.pagetable = priv->pagetable;
+
+ result = ion_phys(kgsl_drm_ion_phys_client,
+ priv->ion_handle, (ion_phys_addr_t *)
+ &priv->memdesc.physaddr, &priv->memdesc.size);
+ if (result) {
+ DRM_ERROR(
+ "Unable to get ION Physical memory address\n");
+ ion_free(kgsl_drm_ion_phys_client,
+ priv->ion_handle);
+ priv->ion_handle = NULL;
+ return result;
+ }
+
+ result = memdesc_sg_phys(&priv->memdesc,
+ priv->memdesc.physaddr, priv->memdesc.size);
+ if (result) {
+ DRM_ERROR(
+ "Unable to get sg list\n");
+ ion_free(kgsl_drm_ion_phys_client,
+ priv->ion_handle);
+ priv->ion_handle = NULL;
+ return result;
+ }
+
+ result = kgsl_mmu_map(priv->pagetable, &priv->memdesc,
+ GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
+ if (result) {
+ DRM_ERROR(
+ "Unable to map GPU\n");
+ ion_free(kgsl_drm_ion_phys_client,
+ priv->ion_handle);
+ priv->ion_handle = NULL;
+ return result;
+ }
}
else
return -EINVAL;
@@ -296,7 +335,16 @@
kgsl_gem_mem_flush(&priv->memdesc, priv->type,
DRM_KGSL_GEM_CACHE_OP_FROM_DEV);
- kgsl_sharedmem_free(&priv->memdesc);
+ if (priv->memdesc.gpuaddr)
+ kgsl_mmu_unmap(priv->memdesc.pagetable, &priv->memdesc);
+
+ kgsl_sg_free(priv->memdesc.sg, priv->memdesc.sglen);
+
+ if (priv->ion_handle)
+ ion_free(kgsl_drm_ion_phys_client, priv->ion_handle);
+ priv->ion_handle = NULL;
+
+ memset(&priv->memdesc, 0, sizeof(priv->memdesc));
kgsl_mmu_putpagetable(priv->pagetable);
priv->pagetable = NULL;
@@ -587,6 +635,43 @@
}
int
+kgsl_gem_get_ion_fd_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_kgsl_gem_get_ion_fd *args = data;
+ struct drm_gem_object *obj;
+ struct drm_kgsl_gem_object *priv;
+ int ret = 0;
+
+ obj = drm_gem_object_lookup(dev, file_priv, args->handle);
+
+ if (obj == NULL) {
+ DRM_ERROR("Invalid GEM handle %x\n", args->handle);
+ return -EBADF;
+ }
+
+ mutex_lock(&dev->struct_mutex);
+ priv = obj->driver_private;
+
+ if (TYPE_IS_FD(priv->type))
+ ret = -EINVAL;
+ else {
+ if (priv->ion_handle) {
+ args->ion_fd = ion_share_dma_buf(
+ kgsl_drm_ion_phys_client, priv->ion_handle);
+ } else {
+ DRM_ERROR("GEM object has no ion memory allocated.\n");
+ ret = -EINVAL;
+ }
+ }
+
+ drm_gem_object_unreference(obj);
+ mutex_unlock(&dev->struct_mutex);
+
+ return ret;
+}
+
+int
kgsl_gem_setmemtype_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
@@ -1434,6 +1519,7 @@
DRM_IOCTL_DEF_DRV(KGSL_GEM_ALLOC, kgsl_gem_alloc_ioctl, 0),
DRM_IOCTL_DEF_DRV(KGSL_GEM_MMAP, kgsl_gem_mmap_ioctl, 0),
DRM_IOCTL_DEF_DRV(KGSL_GEM_GET_BUFINFO, kgsl_gem_get_bufinfo_ioctl, 0),
+ DRM_IOCTL_DEF_DRV(KGSL_GEM_GET_ION_FD, kgsl_gem_get_ion_fd_ioctl, 0),
DRM_IOCTL_DEF_DRV(KGSL_GEM_SET_BUFCOUNT,
kgsl_gem_set_bufcount_ioctl, 0),
DRM_IOCTL_DEF_DRV(KGSL_GEM_SET_ACTIVE, kgsl_gem_set_active_ioctl, 0),
@@ -1447,6 +1533,16 @@
DRM_MASTER),
};
+static const struct file_operations kgsl_drm_driver_fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+ .release = drm_release,
+ .unlocked_ioctl = drm_ioctl,
+ .mmap = msm_drm_gem_mmap,
+ .poll = drm_poll,
+ .fasync = drm_fasync,
+};
+
static struct drm_driver driver = {
.driver_features = DRIVER_GEM,
.load = kgsl_drm_load,
@@ -1458,17 +1554,7 @@
.gem_init_object = kgsl_gem_init_object,
.gem_free_object = kgsl_gem_free_object,
.ioctls = kgsl_drm_ioctls,
-
- .fops = {
- .owner = THIS_MODULE,
- .open = drm_open,
- .release = drm_release,
- .unlocked_ioctl = drm_ioctl,
- .mmap = msm_drm_gem_mmap,
- .poll = drm_poll,
- .fasync = drm_fasync,
- },
-
+ .fops = &kgsl_drm_driver_fops,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.date = DRIVER_DATE,
@@ -1497,11 +1583,24 @@
gem_buf_fence[i].fence_id = ENTRY_EMPTY;
}
+ /* Create ION Client */
+ kgsl_drm_ion_phys_client = msm_ion_client_create(
+ ION_HEAP_CARVEOUT_MASK, "kgsl_drm");
+ if (!kgsl_drm_ion_phys_client) {
+ DRM_ERROR("Unable to create ION client\n");
+ return -ENOMEM;
+ }
+
return drm_platform_init(&driver, dev);
}
void kgsl_drm_exit(void)
{
kgsl_drm_inited = DRM_KGSL_NOT_INITED;
+
+ if (kgsl_drm_ion_phys_client)
+ ion_client_destroy(kgsl_drm_ion_phys_client);
+ kgsl_drm_ion_phys_client = NULL;
+
drm_platform_exit(&driver, driver.kdriver.platform_device);
}
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 07ea48e..1bccd4d 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -702,6 +702,70 @@
}
}
+/*
+ * kgsl_iommu_setup_regs - map iommu registers into a pagetable
+ * @mmu: Pointer to mmu structure
+ * @pt: the pagetable
+ *
+ * To do pagetable switches from the GPU command stream, the IOMMU
+ * registers need to be mapped into the GPU's pagetable. This function
+ * is used differently on different targets. On 8960, the registers
+ * are mapped into every pagetable during kgsl_setup_pt(). On
+ * all other targets, the registers are mapped only into the second
+ * context bank.
+ *
+ * Return - 0 on success else error code
+ */
+static int kgsl_iommu_setup_regs(struct kgsl_mmu *mmu,
+ struct kgsl_pagetable *pt)
+{
+ int status;
+ int i = 0;
+ struct kgsl_iommu *iommu = mmu->priv;
+
+ if (!msm_soc_version_supports_iommu_v1())
+ return 0;
+
+ for (i = 0; i < iommu->unit_count; i++) {
+ iommu->iommu_units[i].reg_map.priv |= KGSL_MEMDESC_GLOBAL;
+ status = kgsl_mmu_map(pt,
+ &(iommu->iommu_units[i].reg_map),
+ GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
+ if (status) {
+ iommu->iommu_units[i].reg_map.priv &=
+ ~KGSL_MEMDESC_GLOBAL;
+ goto err;
+ }
+ }
+ return 0;
+err:
+ for (i--; i >= 0; i--) {
+ kgsl_mmu_unmap(pt,
+ &(iommu->iommu_units[i].reg_map));
+ iommu->iommu_units[i].reg_map.priv &= ~KGSL_MEMDESC_GLOBAL;
+ }
+ return status;
+}
+
+/*
+ * kgsl_iommu_cleanup_regs - unmap iommu registers from a pagetable
+ * @mmu: Pointer to mmu structure
+ * @pt: the pagetable
+ *
+ * Removes mappings created by kgsl_iommu_setup_regs().
+ *
+ * Return - 0 on success else error code
+ */
+static void kgsl_iommu_cleanup_regs(struct kgsl_mmu *mmu,
+ struct kgsl_pagetable *pt)
+{
+ struct kgsl_iommu *iommu = mmu->priv;
+ int i;
+ for (i = 0; i < iommu->unit_count; i++)
+ kgsl_mmu_unmap(pt, &(iommu->iommu_units[i].reg_map));
+}
+
+
static int kgsl_iommu_init(struct kgsl_mmu *mmu)
{
/*
@@ -744,6 +808,15 @@
KGSL_IOMMU_SETSTATE_NOP_OFFSET,
cp_nop_packet(1));
+ if (cpu_is_msm8960()) {
+ /*
+ * 8960 doesn't have a second context bank, so the IOMMU
+ * registers must be mapped into every pagetable.
+ */
+ iommu_ops.mmu_setup_pt = kgsl_iommu_setup_regs;
+ iommu_ops.mmu_cleanup_pt = kgsl_iommu_cleanup_regs;
+ }
+
dev_info(mmu->device->dev, "|%s| MMU type set for device is IOMMU\n",
__func__);
done:
@@ -766,9 +839,6 @@
static int kgsl_iommu_setup_defaultpagetable(struct kgsl_mmu *mmu)
{
int status = 0;
- int i = 0;
- struct kgsl_iommu *iommu = mmu->priv;
- struct kgsl_pagetable *pagetable = NULL;
/* If chip is not 8960 then we use the 2nd context bank for pagetable
* switching on the 3D side for which a separate table is allocated */
@@ -779,6 +849,9 @@
status = -ENOMEM;
goto err;
}
+ status = kgsl_iommu_setup_regs(mmu, mmu->priv_bank_table);
+ if (status)
+ goto err;
}
mmu->defaultpagetable = kgsl_mmu_getpagetable(KGSL_MMU_GLOBAL_PT);
/* Return error if the default pagetable doesn't exist */
@@ -786,31 +859,10 @@
status = -ENOMEM;
goto err;
}
- pagetable = mmu->priv_bank_table ? mmu->priv_bank_table :
- mmu->defaultpagetable;
- /* Map the IOMMU regsiters to only defaultpagetable */
- if (msm_soc_version_supports_iommu_v1()) {
- for (i = 0; i < iommu->unit_count; i++) {
- iommu->iommu_units[i].reg_map.priv |=
- KGSL_MEMDESC_GLOBAL;
- status = kgsl_mmu_map(pagetable,
- &(iommu->iommu_units[i].reg_map),
- GSL_PT_PAGE_RV | GSL_PT_PAGE_WV);
- if (status) {
- iommu->iommu_units[i].reg_map.priv &=
- ~KGSL_MEMDESC_GLOBAL;
- goto err;
- }
- }
- }
return status;
err:
- for (i--; i >= 0; i--) {
- kgsl_mmu_unmap(pagetable,
- &(iommu->iommu_units[i].reg_map));
- iommu->iommu_units[i].reg_map.priv &= ~KGSL_MEMDESC_GLOBAL;
- }
if (mmu->priv_bank_table) {
+ kgsl_iommu_cleanup_regs(mmu, mmu->priv_bank_table);
kgsl_mmu_putpagetable(mmu->priv_bank_table);
mmu->priv_bank_table = NULL;
}
@@ -839,10 +891,12 @@
* a225, hence we still keep the MMU active on 8960 */
if (cpu_is_msm8960()) {
struct kgsl_mh *mh = &(mmu->device->mh);
+ BUG_ON(iommu->iommu_units[0].reg_map.gpuaddr != 0 &&
+ mh->mpu_base > iommu->iommu_units[0].reg_map.gpuaddr);
kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000001);
+
kgsl_regwrite(mmu->device, MH_MMU_MPU_END,
- mh->mpu_base +
- iommu->iommu_units[0].reg_map.gpuaddr);
+ mh->mpu_base + mh->mpu_range);
} else {
kgsl_regwrite(mmu->device, MH_MMU_CONFIG, 0x00000000);
}
@@ -915,14 +969,12 @@
"with err: %d\n", iommu_pt->domain, gpuaddr,
range, ret);
-#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
/*
* Flushing only required if per process pagetables are used. With
* global case, flushing will happen inside iommu_map function
*/
- if (!ret && msm_soc_version_supports_iommu_v1())
+ if (!ret && kgsl_mmu_is_perprocess())
*tlb_flags = UINT_MAX;
-#endif
return 0;
}
@@ -1003,22 +1055,23 @@
{
struct kgsl_iommu *iommu = mmu->priv;
int i;
- for (i = 0; i < iommu->unit_count; i++) {
- struct kgsl_pagetable *pagetable = (mmu->priv_bank_table ?
- mmu->priv_bank_table : mmu->defaultpagetable);
- if (iommu->iommu_units[i].reg_map.gpuaddr)
- kgsl_mmu_unmap(pagetable,
- &(iommu->iommu_units[i].reg_map));
- if (iommu->iommu_units[i].reg_map.hostptr)
- iounmap(iommu->iommu_units[i].reg_map.hostptr);
- kgsl_sg_free(iommu->iommu_units[i].reg_map.sg,
- iommu->iommu_units[i].reg_map.sglen);
+
+ if (mmu->priv_bank_table != NULL) {
+ kgsl_iommu_cleanup_regs(mmu, mmu->priv_bank_table);
+ kgsl_mmu_putpagetable(mmu->priv_bank_table);
}
- if (mmu->priv_bank_table)
- kgsl_mmu_putpagetable(mmu->priv_bank_table);
- if (mmu->defaultpagetable)
+ if (mmu->defaultpagetable != NULL)
kgsl_mmu_putpagetable(mmu->defaultpagetable);
+
+ for (i = 0; i < iommu->unit_count; i++) {
+ struct kgsl_memdesc *reg_map = &iommu->iommu_units[i].reg_map;
+
+ if (reg_map->hostptr)
+ iounmap(reg_map->hostptr);
+ kgsl_sg_free(reg_map->sg, reg_map->sglen);
+ }
+
kfree(iommu);
return 0;
@@ -1149,6 +1202,9 @@
.mmu_get_num_iommu_units = kgsl_iommu_get_num_iommu_units,
.mmu_pt_equal = kgsl_iommu_pt_equal,
.mmu_get_pt_base_addr = kgsl_iommu_get_pt_base_addr,
+ /* These callbacks will be set on some chipsets */
+ .mmu_setup_pt = NULL,
+ .mmu_cleanup_pt = NULL,
};
struct kgsl_mmu_pt_ops iommu_pt_ops = {
diff --git a/drivers/gpu/msm/kgsl_mmu.c b/drivers/gpu/msm/kgsl_mmu.c
index 68cd167..6fe119d 100644
--- a/drivers/gpu/msm/kgsl_mmu.c
+++ b/drivers/gpu/msm/kgsl_mmu.c
@@ -36,17 +36,18 @@
static int kgsl_cleanup_pt(struct kgsl_pagetable *pt)
{
int i;
- /* For IOMMU only unmap the global structures to global pt */
- if ((KGSL_MMU_TYPE_NONE != kgsl_mmu_type) &&
- (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_type) &&
- (KGSL_MMU_GLOBAL_PT != pt->name) &&
- (KGSL_MMU_PRIV_BANK_TABLE_NAME != pt->name))
- return 0;
+ struct kgsl_device *device;
+
for (i = 0; i < KGSL_DEVICE_MAX; i++) {
- struct kgsl_device *device = kgsl_driver.devp[i];
+ device = kgsl_driver.devp[i];
if (device)
device->ftbl->cleanup_pt(device, pt);
}
+ /* Only the 3d device needs mmu specific pt entries */
+ device = kgsl_driver.devp[KGSL_DEVICE_3D0];
+ if (device->mmu.mmu_ops->mmu_cleanup_pt != NULL)
+ device->mmu.mmu_ops->mmu_cleanup_pt(&device->mmu, pt);
+
return 0;
}
@@ -55,21 +56,23 @@
{
int i = 0;
int status = 0;
+ struct kgsl_device *device;
- /* For IOMMU only map the global structures to global pt */
- if ((KGSL_MMU_TYPE_NONE != kgsl_mmu_type) &&
- (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_type) &&
- (KGSL_MMU_GLOBAL_PT != pt->name) &&
- (KGSL_MMU_PRIV_BANK_TABLE_NAME != pt->name))
- return 0;
for (i = 0; i < KGSL_DEVICE_MAX; i++) {
- struct kgsl_device *device = kgsl_driver.devp[i];
+ device = kgsl_driver.devp[i];
if (device) {
status = device->ftbl->setup_pt(device, pt);
if (status)
goto error_pt;
}
}
+ /* Only the 3d device needs mmu specific pt entries */
+ device = kgsl_driver.devp[KGSL_DEVICE_3D0];
+ if (device->mmu.mmu_ops->mmu_setup_pt != NULL) {
+ status = device->mmu.mmu_ops->mmu_setup_pt(&device->mmu, pt);
+ if (status)
+ goto error_pt;
+ }
return status;
error_pt:
while (i >= 0) {
@@ -309,22 +312,6 @@
return ret;
}
-unsigned int kgsl_mmu_get_ptsize(void)
-{
- /*
- * For IOMMU, we could do up to 4G virtual range if we wanted to, but
- * it makes more sense to return a smaller range and leave the rest of
- * the virtual range for future improvements
- */
-
- if (KGSL_MMU_TYPE_GPU == kgsl_mmu_type)
- return CONFIG_MSM_KGSL_PAGE_TABLE_SIZE;
- else if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_type)
- return SZ_2G - KGSL_PAGETABLE_BASE;
- else
- return 0;
-}
-
int
kgsl_mmu_get_ptname_from_ptbase(struct kgsl_mmu *mmu, unsigned int pt_base)
{
@@ -480,7 +467,7 @@
goto err_kgsl_pool;
}
- if (gen_pool_add(pagetable->pool, KGSL_PAGETABLE_BASE,
+ if (gen_pool_add(pagetable->pool, kgsl_mmu_get_base_addr(),
ptsize, -1)) {
KGSL_CORE_ERR("gen_pool_add failed\n");
goto err_pool;
@@ -528,11 +515,7 @@
if (KGSL_MMU_TYPE_NONE == kgsl_mmu_type)
return (void *)(-1);
-#ifndef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
- name = KGSL_MMU_GLOBAL_PT;
-#endif
- /* We presently do not support per-process for IOMMU-v2 */
- if (!msm_soc_version_supports_iommu_v1())
+ if (!kgsl_mmu_is_perprocess())
name = KGSL_MMU_GLOBAL_PT;
pt = kgsl_get_pagetable(name);
@@ -589,15 +572,6 @@
*/
}
-static inline struct gen_pool *
-_get_pool(struct kgsl_pagetable *pagetable, unsigned int flags)
-{
- if (pagetable->kgsl_pool &&
- (KGSL_MEMDESC_GLOBAL & flags))
- return pagetable->kgsl_pool;
- return pagetable->pool;
-}
-
int
kgsl_mmu_map(struct kgsl_pagetable *pagetable,
struct kgsl_memdesc *memdesc,
@@ -628,28 +602,48 @@
size = kgsl_sg_size(memdesc->sg, memdesc->sglen);
- /* Allocate from kgsl pool if it exists for global mappings */
- pool = _get_pool(pagetable, memdesc->priv);
+ pool = pagetable->pool;
- /* Allocate aligned virtual addresses for iommu. This allows
- * more efficient pagetable entries if the physical memory
- * is also aligned. Don't do this for GPUMMU, because
- * the address space is so small.
- */
- if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype() &&
- kgsl_memdesc_get_align(memdesc) > 0)
- page_align = kgsl_memdesc_get_align(memdesc);
-
- memdesc->gpuaddr = gen_pool_alloc_aligned(pool, size, page_align);
- if (memdesc->gpuaddr == 0) {
- KGSL_CORE_ERR("gen_pool_alloc(%d) failed from pool: %s\n",
- size,
- (pool == pagetable->kgsl_pool) ?
- "kgsl_pool" : "general_pool");
- KGSL_CORE_ERR(" [%d] allocated=%d, entries=%d\n",
- pagetable->name, pagetable->stats.mapped,
- pagetable->stats.entries);
- return -ENOMEM;
+ if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype()) {
+ /* Allocate aligned virtual addresses for iommu. This allows
+ * more efficient pagetable entries if the physical memory
+ * is also aligned. Don't do this for GPUMMU, because
+ * the address space is so small.
+ */
+ if (kgsl_memdesc_get_align(memdesc) > 0)
+ page_align = kgsl_memdesc_get_align(memdesc);
+ if (kgsl_memdesc_is_global(memdesc)) {
+ /*
+ * Only the default pagetable has a kgsl_pool, and
+ * it is responsible for creating the mapping for
+ * each global buffer. The mapping will be reused
+ * in all other pagetables and it must already exist
+ * when we're creating other pagetables which do not
+ * have a kgsl_pool.
+ */
+ pool = pagetable->kgsl_pool;
+ if (pool == NULL && memdesc->gpuaddr == 0) {
+ KGSL_CORE_ERR(
+ "No address for global mapping into pt %d\n",
+ pagetable->name);
+ return -EINVAL;
+ }
+ }
+ }
+ if (pool) {
+ memdesc->gpuaddr = gen_pool_alloc_aligned(pool, size,
+ page_align);
+ if (memdesc->gpuaddr == 0) {
+ KGSL_CORE_ERR("gen_pool_alloc(%d) failed, pool: %s\n",
+ size,
+ (pool == pagetable->kgsl_pool) ?
+ "kgsl_pool" : "general_pool");
+ KGSL_CORE_ERR(" [%d] allocated=%d, entries=%d\n",
+ pagetable->name,
+ pagetable->stats.mapped,
+ pagetable->stats.entries);
+ return -ENOMEM;
+ }
}
if (KGSL_MMU_TYPE_IOMMU != kgsl_mmu_get_mmutype())
@@ -676,7 +670,8 @@
err_free_gpuaddr:
spin_unlock(&pagetable->lock);
- gen_pool_free(pool, memdesc->gpuaddr, size);
+ if (pool)
+ gen_pool_free(pool, memdesc->gpuaddr, size);
memdesc->gpuaddr = 0;
return ret;
}
@@ -711,14 +706,20 @@
spin_unlock(&pagetable->lock);
- pool = _get_pool(pagetable, memdesc->priv);
- gen_pool_free(pool, memdesc->gpuaddr, size);
+ pool = pagetable->pool;
+
+ if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype()
+ && kgsl_memdesc_is_global(memdesc)) {
+ pool = pagetable->kgsl_pool;
+ }
+ if (pool)
+ gen_pool_free(pool, memdesc->gpuaddr, size);
/*
* Don't clear the gpuaddr on global mappings because they
* may be in use by other pagetables
*/
- if (!(memdesc->priv & KGSL_MEMDESC_GLOBAL))
+ if (!kgsl_memdesc_is_global(memdesc))
memdesc->gpuaddr = 0;
return 0;
}
diff --git a/drivers/gpu/msm/kgsl_mmu.h b/drivers/gpu/msm/kgsl_mmu.h
index b8b9149..b8eff60 100644
--- a/drivers/gpu/msm/kgsl_mmu.h
+++ b/drivers/gpu/msm/kgsl_mmu.h
@@ -13,13 +13,14 @@
#ifndef __KGSL_MMU_H
#define __KGSL_MMU_H
+#include <mach/iommu.h>
+
/*
- * These defines control the split between ttbr1 and ttbr0 pagetables of IOMMU
- * and what ranges of memory we map to them
+ * These defines control the address range for allocations that
+ * are mapped into all pagetables.
*/
#define KGSL_IOMMU_GLOBAL_MEM_BASE 0xC0000000
#define KGSL_IOMMU_GLOBAL_MEM_SIZE SZ_4M
-#define KGSL_IOMMU_TTBR1_SPLIT 2
#define KGSL_MMU_ALIGN_SHIFT 13
#define KGSL_MMU_ALIGN_MASK (~((1 << KGSL_MMU_ALIGN_SHIFT) - 1))
@@ -148,6 +149,10 @@
unsigned int (*mmu_get_pt_base_addr)
(struct kgsl_mmu *mmu,
struct kgsl_pagetable *pt);
+ int (*mmu_setup_pt) (struct kgsl_mmu *mmu,
+ struct kgsl_pagetable *pt);
+ void (*mmu_cleanup_pt) (struct kgsl_mmu *mmu,
+ struct kgsl_pagetable *pt);
};
struct kgsl_mmu_pt_ops {
@@ -209,7 +214,6 @@
int kgsl_mmu_enabled(void);
void kgsl_mmu_set_mmutype(char *mmutype);
enum kgsl_mmutype kgsl_mmu_get_mmutype(void);
-unsigned int kgsl_mmu_get_ptsize(void);
int kgsl_mmu_gpuaddr_in_range(unsigned int gpuaddr);
/*
@@ -321,4 +325,58 @@
return 0;
}
+/*
+ * kgsl_mmu_is_perprocess() - Runtime check for per-process
+ * pagetables.
+ *
+ * Returns non-zero if per-process pagetables are enabled,
+ * 0 if not.
+ */
+#ifdef CONFIG_KGSL_PER_PROCESS_PAGE_TABLE
+static inline int kgsl_mmu_is_perprocess(void)
+{
+
+ /* We presently do not support per-process for IOMMU-v2 */
+ return (kgsl_mmu_get_mmutype() != KGSL_MMU_TYPE_IOMMU)
+ || msm_soc_version_supports_iommu_v1();
+}
+#else
+static inline int kgsl_mmu_is_perprocess(void)
+{
+ return 0;
+}
+#endif
+
+/*
+ * kgsl_mmu_base_addr() - Get gpu virtual address base.
+ *
+ * Returns the start address of the gpu
+ * virtual address space.
+ */
+static inline unsigned int kgsl_mmu_get_base_addr(void)
+{
+ return KGSL_PAGETABLE_BASE;
+}
+
+/*
+ * kgsl_mmu_get_ptsize() - Get gpu pagetable size
+ *
+ * Returns the usable size of the gpu address space.
+ */
+static inline unsigned int kgsl_mmu_get_ptsize(void)
+{
+ /*
+ * For IOMMU, we could do up to 4G virtual range if we wanted to, but
+ * it makes more sense to return a smaller range and leave the rest of
+ * the virtual range for future improvements
+ */
+ enum kgsl_mmutype mmu_type = kgsl_mmu_get_mmutype();
+
+ if (KGSL_MMU_TYPE_GPU == mmu_type)
+ return CONFIG_MSM_KGSL_PAGE_TABLE_SIZE;
+ else if (KGSL_MMU_TYPE_IOMMU == mmu_type)
+ return SZ_2G;
+ return 0;
+}
+
#endif /* __KGSL_MMU_H */
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 422bd55..7a7a8dc 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -169,7 +169,7 @@
if (pwr->pwrlevels[pwr->active_pwrlevel].gpu_freq >
pwr->pwrlevels[pwr->thermal_pwrlevel].gpu_freq)
kgsl_pwrctrl_pwrlevel_change(device, pwr->thermal_pwrlevel);
- else if (!max)
+ else if (!max || (NULL == device->pwrscale.policy))
kgsl_pwrctrl_pwrlevel_change(device, i);
done:
diff --git a/drivers/gpu/msm/kgsl_pwrscale_msm.c b/drivers/gpu/msm/kgsl_pwrscale_msm.c
index b302bee..c680d57 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_msm.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_msm.c
@@ -23,6 +23,8 @@
struct kgsl_device *device;
int enabled;
unsigned int cur_freq;
+ unsigned int req_level;
+ int floor_level;
struct msm_dcvs_core_info *core_info;
int gpu_busy;
int dcvs_core_id;
@@ -69,7 +71,39 @@
return 0;
mutex_lock(&device->mutex);
- kgsl_pwrctrl_pwrlevel_change(device, i);
+ priv->req_level = i;
+ if (priv->req_level <= priv->floor_level) {
+ kgsl_pwrctrl_pwrlevel_change(device, priv->req_level);
+ priv->cur_freq = pwr->pwrlevels[pwr->active_pwrlevel].gpu_freq;
+ }
+ mutex_unlock(&device->mutex);
+
+ /* return current frequency in kHz */
+ return priv->cur_freq / 1000;
+}
+
+static int msm_set_min_freq(int core_num, unsigned int freq)
+{
+ int i, delta = 5000000;
+ struct msm_priv *priv = the_msm_priv;
+ struct kgsl_device *device = priv->device;
+ struct kgsl_pwrctrl *pwr = &device->pwrctrl;
+
+ /* msm_dcvs manager uses frequencies in kHz */
+ freq *= 1000;
+ for (i = 0; i < pwr->num_pwrlevels; i++)
+ if (abs(pwr->pwrlevels[i].gpu_freq - freq) < delta)
+ break;
+ if (i == pwr->num_pwrlevels)
+ return 0;
+
+ mutex_lock(&device->mutex);
+ priv->floor_level = i;
+ if (priv->floor_level <= priv->req_level)
+ kgsl_pwrctrl_pwrlevel_change(device, priv->floor_level);
+ else if (priv->floor_level > priv->req_level)
+ kgsl_pwrctrl_pwrlevel_change(device, priv->req_level);
+
priv->cur_freq = pwr->pwrlevels[pwr->active_pwrlevel].gpu_freq;
mutex_unlock(&device->mutex);
@@ -170,6 +204,7 @@
priv->core_info = pdata->core_info;
tbl = priv->core_info->freq_tbl;
+ priv->floor_level = pwr->num_pwrlevels - 1;
/* Fill in frequency table from low to high, reversing order. */
low_level = pwr->num_pwrlevels - KGSL_PWRLEVEL_LAST_OFFSET;
for (i = 0; i <= low_level; i++)
@@ -180,6 +215,7 @@
0,
priv->core_info,
msm_set_freq, msm_get_freq, msm_idle_enable,
+ msm_set_min_freq,
priv->core_info->sensors[0]);
if (priv->dcvs_core_id < 0) {
KGSL_PWR_ERR(device, "msm_dcvs_register_core failed");
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index a70647a..be51c11 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -541,27 +541,8 @@
struct page **pages = NULL;
pgprot_t page_prot = pgprot_writecombine(PAGE_KERNEL);
void *ptr;
- struct sysinfo si;
unsigned int align;
- /*
- * Get the current memory information to be used in deciding if we
- * should go ahead with this allocation
- */
-
- si_meminfo(&si);
-
- /*
- * Limit the size of the allocation to the amount of free memory minus
- * 32MB. Why 32MB? Because thats the buffer that page_alloc uses and
- * it just seems like a reasonable limit that won't make the OOM killer
- * go all serial on us. Of course, if we are down this low all bets
- * are off but above all do no harm.
- */
-
- if (size >= ((si.freeram << PAGE_SHIFT) - SZ_32M))
- return -ENOMEM;
-
align = (memdesc->flags & KGSL_MEMALIGN_MASK) >> KGSL_MEMALIGN_SHIFT;
page_size = (align >= ilog2(SZ_64K) && size >= SZ_64K)
@@ -623,7 +604,7 @@
while (len > 0) {
struct page *page;
unsigned int gfp_mask = GFP_KERNEL | __GFP_HIGHMEM |
- __GFP_NOWARN;
+ __GFP_NOWARN | __GFP_NORETRY;
int j;
/* don't waste space at the end of the allocation*/
@@ -640,6 +621,13 @@
page_size = PAGE_SIZE;
continue;
}
+
+ KGSL_CORE_ERR(
+ "Out of memory: only allocated %dKB of %dKB requested\n",
+ (size - len) >> 10, size >> 10);
+
+ ret = -ENOMEM;
+ goto done;
}
for (j = 0; j < page_size >> PAGE_SHIFT; j++)
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index 92a6f27..53e88be 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -157,6 +157,17 @@
return 0;
}
+/*
+ * kgsl_memdesc_is_global - is this a globally mapped buffer?
+ * @memdesc: the memdesc
+ *
+ * Returns nonzero if this is a global mapping, 0 otherwise
+ */
+static inline int kgsl_memdesc_is_global(const struct kgsl_memdesc *memdesc)
+{
+ return (memdesc->priv & KGSL_MEMDESC_GLOBAL) != 0;
+}
+
static inline int
kgsl_allocate(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index 712bc60..258dcfa 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -260,6 +260,13 @@
GSL_PT_PAGE_RV);
if (result)
goto error_unmap_memstore;
+ /*
+ * Set the mpu end to the last "normal" global memory we use.
+ * For the IOMMU, this will be used to restrict access to the
+ * mapped registers.
+ */
+ device->mh.mpu_range = z180_dev->ringbuffer.cmdbufdesc.gpuaddr +
+ z180_dev->ringbuffer.cmdbufdesc.size;
return result;
error_unmap_dummy:
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index 0a85b93..0e82cf7 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -54,28 +54,6 @@
#define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0)
#define QPNP_CONV_TIMEOUT_ERR 2
-#define QPNP_INT_RT_ST 0x10
-#define QPNP_INT_SET_TYPE 0x11
-#define QPNP_INT_SET_TYPE_LOW_THR_INT_SET BIT(4)
-#define QPNP_INT_SET_TYPE_HIGH_THR_INT_SET BIT(3)
-#define QPNP_INT_SET_TYPE_CONV_SEQ_TIMEOUT_INT_SET BIT(2)
-#define QPNP_INT_SET_TYPE_FIFO_NOT_EMPTY_INT_SET BIT(1)
-#define QPNP_INT_SET_TYPE_EOC_SET_INT_TYPE BIT(0)
-#define QPNP_INT_POLARITY_HIGH 0x12
-#define QPNP_INT_POLARITY_LOW 0x13
-#define QPNP_INT_EN_SET 0x15
-#define QPNP_INT_EN_SET_LOW_THR_INT_EN_SET BIT(4)
-#define QPNP_INT_EN_SET_HIGH_THR_INT_EN_SET BIT(3)
-#define QPNP_INT_EN_SET_CONV_SEQ_TIMEOUT_INT_EN BIT(2)
-#define QPNP_INT_EN_SET_FIFO_NOT_EMPTY_INT_EN BIT(1)
-#define QPNP_INT_EN_SET_EOC_INT_EN_SET BIT(0)
-#define QPNP_INT_CLR 0x16
-#define QPNP_INT_CLR_LOW_THR_INT_EN_CLR BIT(4)
-#define QPNP_INT_CLR_HIGH_THR_INT_EN_CLKR BIT(3)
-#define QPNP_INT_CLR_CONV_SEQ_TIMEOUT_INT_EN BIT(2)
-#define QPNP_INT_CLR_FIFO_NOT_EMPTY_INT_EN BIT(1)
-#define QPNP_INT_CLR_EOC_INT_EN_CLR BIT(0)
-#define QPNP_INT_CLR_MASK 0x1f
#define QPNP_IADC_MODE_CTL 0x40
#define QPNP_OP_MODE_SHIFT 4
#define QPNP_USE_BMS_DATA BIT(4)
@@ -146,6 +124,7 @@
#define QPNP_RAW_CODE_16_BIT_LSB_MASK 0xff
#define QPNP_BIT_SHIFT_8 8
#define QPNP_RSENSE_MSB_SIGN_CHECK 0x80
+#define QPNP_ADC_COMPLETION_TIMEOUT HZ
struct qpnp_iadc_drv {
struct qpnp_adc_drv *adc;
@@ -192,47 +171,9 @@
return 0;
}
-static int32_t qpnp_iadc_configure_interrupt(void)
-{
- int rc = 0;
- u8 data = 0;
-
- /* Configure interrupt as an Edge trigger */
- rc = qpnp_iadc_write_reg(QPNP_INT_SET_TYPE,
- QPNP_INT_CLR_MASK);
- if (rc < 0) {
- pr_err("%s Interrupt configure failed\n", __func__);
- return rc;
- }
-
- /* Configure interrupt for rising edge trigger */
- rc = qpnp_iadc_write_reg(QPNP_INT_POLARITY_HIGH,
- QPNP_INT_CLR_MASK);
- if (rc < 0) {
- pr_err("%s Rising edge trigger configure failed\n", __func__);
- return rc;
- }
-
- /* Disable low level interrupt triggering */
- data = QPNP_INT_CLR_MASK;
- rc = qpnp_iadc_write_reg(QPNP_INT_POLARITY_LOW,
- (~data & QPNP_INT_CLR_MASK));
- if (rc < 0) {
- pr_err("%s Setting level low to disable failed\n", __func__);
- return rc;
- }
-
- return 0;
-}
-
static void trigger_iadc_completion(struct work_struct *work)
{
struct qpnp_iadc_drv *iadc = qpnp_iadc;
- int rc;
-
- rc = qpnp_iadc_write_reg(QPNP_INT_CLR, QPNP_INT_CLR_MASK);
- if (rc < 0)
- pr_err("qpnp iadc interrupt mask failed with %d\n", rc);
complete(&iadc->adc->adc_rslt_completion);
@@ -315,13 +256,6 @@
qpnp_iadc_conv_req = QPNP_IADC_CONV_REQ;
- rc = qpnp_iadc_write_reg(QPNP_INT_EN_SET,
- QPNP_INT_EN_SET_EOC_INT_EN_SET);
- if (rc < 0) {
- pr_err("qpnp adc configure error for interrupt setup\n");
- return rc;
- }
-
rc = qpnp_iadc_write_reg(QPNP_IADC_MODE_CTL, qpnp_iadc_mode_reg);
if (rc) {
pr_err("qpnp adc read adc failed with %d\n", rc);
@@ -366,7 +300,22 @@
return rc;
}
- wait_for_completion(&iadc->adc->adc_rslt_completion);
+ rc = wait_for_completion_timeout(&iadc->adc->adc_rslt_completion,
+ QPNP_ADC_COMPLETION_TIMEOUT);
+ if (!rc) {
+ u8 status1 = 0;
+ rc = qpnp_iadc_read_reg(QPNP_STATUS1, &status1);
+ if (rc < 0)
+ return rc;
+ status1 &= (QPNP_STATUS1_REQ_STS | QPNP_STATUS1_EOC);
+ if (status1 == QPNP_STATUS1_EOC)
+ pr_debug("End of conversion status set\n");
+ else {
+ pr_err("EOC interrupt not received\n");
+ return -EINVAL;
+ }
+ }
+
rc = qpnp_iadc_read_conversion_result(raw_code);
if (rc) {
@@ -672,9 +621,9 @@
qpnp_adc_attr.index = iadc->adc->adc_channels[i].channel_num;
qpnp_adc_attr.dev_attr.attr.name =
iadc->adc->adc_channels[i].name;
- sysfs_attr_init(&iadc->sens_attr[i].dev_attr.attr);
memcpy(&iadc->sens_attr[i], &qpnp_adc_attr,
sizeof(qpnp_adc_attr));
+ sysfs_attr_init(&iadc->sens_attr[i].dev_attr.attr);
rc = device_create_file(&spmi->dev,
&iadc->sens_attr[i].dev_attr);
if (rc) {
@@ -766,12 +715,6 @@
}
iadc->iadc_hwmon = hwmon_device_register(&iadc->adc->spmi->dev);
- rc = qpnp_iadc_configure_interrupt();
- if (rc) {
- dev_err(&spmi->dev, "failed to configure interrupt\n");
- return rc;
- }
-
rc = qpnp_iadc_version_check();
if (rc) {
dev_err(&spmi->dev, "IADC version not supported\n");
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index 5690c88..c59aa5b 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -54,18 +54,6 @@
#define QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT 4
#define QPNP_VADC_CONV_TIMEOUT_ERR 2
-#define QPNP_VADC_INT_SET_TYPE 0x11
-#define QPNP_VADC_INT_POLARITY_HIGH 0x12
-#define QPNP_VADC_INT_POLARITY_LOW 0x13
-#define QPNP_VADC_INT_LATCHED_CLR 0x14
-#define QPNP_VADC_INT_EN_SET 0x15
-#define QPNP_VADC_INT_CLR 0x16
-#define QPNP_VADC_INT_LOW_THR_BIT BIT(4)
-#define QPNP_VADC_INT_HIGH_THR_BIT BIT(3)
-#define QPNP_VADC_INT_CONV_SEQ_TIMEOUT_BIT BIT(2)
-#define QPNP_VADC_INT_FIFO_NOT_EMPTY_BIT BIT(1)
-#define QPNP_VADC_INT_EOC_BIT BIT(0)
-#define QPNP_VADC_INT_CLR_MASK 0x1f
#define QPNP_VADC_MODE_CTL 0x40
#define QPNP_VADC_OP_MODE_SHIFT 4
#define QPNP_VADC_VREF_XO_THM_FORCE BIT(2)
@@ -101,6 +89,7 @@
#define QPNP_VADC_CONV_TIMEOUT_ERR 2
#define QPNP_VADC_CONV_TIME_MIN 2000
#define QPNP_VADC_CONV_TIME_MAX 2100
+#define QPNP_ADC_COMPLETION_TIMEOUT HZ
struct qpnp_vadc_drv {
struct qpnp_adc_drv *adc;
@@ -156,39 +145,6 @@
return 0;
}
-static int32_t qpnp_vadc_configure_interrupt(void)
-{
- int rc = 0;
- u8 data = 0;
-
- /* Configure interrupt as an Edge trigger */
- rc = qpnp_vadc_write_reg(QPNP_VADC_INT_SET_TYPE,
- QPNP_VADC_INT_CLR_MASK);
- if (rc < 0) {
- pr_err("%s Interrupt configure failed\n", __func__);
- return rc;
- }
-
- /* Configure interrupt for rising edge trigger */
- rc = qpnp_vadc_write_reg(QPNP_VADC_INT_POLARITY_HIGH,
- QPNP_VADC_INT_CLR_MASK);
- if (rc < 0) {
- pr_err("%s Rising edge trigger configure failed\n", __func__);
- return rc;
- }
-
- /* Disable low level interrupt triggering */
- data = QPNP_VADC_INT_CLR_MASK;
- rc = qpnp_vadc_write_reg(QPNP_VADC_INT_POLARITY_LOW,
- (~data & QPNP_VADC_INT_CLR_MASK));
- if (rc < 0) {
- pr_err("%s Setting level low to disable failed\n", __func__);
- return rc;
- }
-
- return 0;
-}
-
static int32_t qpnp_vadc_enable(bool state)
{
int rc = 0;
@@ -222,13 +178,6 @@
u8 mode_ctrl = 0;
int rc = 0;
- rc = qpnp_vadc_write_reg(QPNP_VADC_INT_EN_SET,
- QPNP_VADC_INT_EOC_BIT);
- if (rc < 0) {
- pr_err("Configure error for interrupt setup\n");
- return rc;
- }
-
/* Mode selection */
mode_ctrl = chan_prop->mode_sel << QPNP_VADC_OP_MODE_SHIFT;
rc = qpnp_vadc_write_reg(QPNP_VADC_MODE_CTL, mode_ctrl);
@@ -389,11 +338,6 @@
static void qpnp_vadc_work(struct work_struct *work)
{
struct qpnp_vadc_drv *vadc = qpnp_vadc;
- int rc;
-
- rc = qpnp_vadc_write_reg(QPNP_VADC_INT_CLR, QPNP_VADC_INT_EOC_BIT);
- if (rc)
- pr_err("qpnp_vadc clear mask interrupt failed with %d\n", rc);
complete(&vadc->adc->adc_rslt_completion);
@@ -606,8 +550,11 @@
!= channel || dt_index > vadc->max_channels_available)
dt_index++;
- if (dt_index > vadc->max_channels_available)
+ if (dt_index > vadc->max_channels_available) {
+ pr_err("not a valid VADC channel\n");
+ rc = -EINVAL;
goto fail_unlock;
+ }
vadc->adc->amux_prop->decimation =
vadc->adc->adc_channels[dt_index].adc_decimation;
@@ -635,7 +582,22 @@
goto fail_unlock;
}
- wait_for_completion(&vadc->adc->adc_rslt_completion);
+ rc = wait_for_completion_timeout(&vadc->adc->adc_rslt_completion,
+ QPNP_ADC_COMPLETION_TIMEOUT);
+ if (!rc) {
+ u8 status1 = 0;
+ rc = qpnp_vadc_read_reg(QPNP_VADC_STATUS1, &status1);
+ if (rc < 0)
+ goto fail_unlock;
+ status1 &= (QPNP_VADC_STATUS1_REQ_STS | QPNP_VADC_STATUS1_EOC);
+ if (status1 == QPNP_VADC_STATUS1_EOC)
+ pr_debug("End of conversion status set\n");
+ else {
+ pr_err("EOC interrupt not received\n");
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+ }
if (trigger_channel < ADC_SEQ_NONE) {
rc = qpnp_vadc_read_status(vadc->adc->amux_prop->mode_sel);
@@ -714,9 +676,9 @@
qpnp_adc_attr.index = vadc->adc->adc_channels[i].channel_num;
qpnp_adc_attr.dev_attr.attr.name =
vadc->adc->adc_channels[i].name;
- sysfs_attr_init(&vadc->sens_attr[i].dev_attr.attr);
memcpy(&vadc->sens_attr[i], &qpnp_adc_attr,
sizeof(qpnp_adc_attr));
+ sysfs_attr_init(&vadc->sens_attr[i].dev_attr.attr);
rc = device_create_file(&spmi->dev,
&vadc->sens_attr[i].dev_attr);
if (rc) {
@@ -797,25 +759,14 @@
rc = qpnp_vadc_init_hwmon(spmi);
if (rc) {
dev_err(&spmi->dev, "failed to initialize qpnp hwmon adc\n");
- goto fail_free_irq;
+ return rc;
}
vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->spmi->dev);
vadc->vadc_init_calib = false;
- vadc->vadc_initialized = true;
vadc->max_channels_available = count_adc_channel_list;
-
- rc = qpnp_vadc_configure_interrupt();
- if (rc) {
- dev_err(&spmi->dev, "failed to configure interrupt");
- goto fail_free_irq;
- }
+ vadc->vadc_initialized = true;
return 0;
-
-fail_free_irq:
- free_irq(vadc->adc->adc_irq, vadc);
-
- return rc;
}
static int __devexit qpnp_vadc_remove(struct spmi_device *spmi)
@@ -830,7 +781,6 @@
&vadc->sens_attr[i].dev_attr);
i++;
}
- free_irq(vadc->adc->adc_irq, vadc);
vadc->vadc_initialized = false;
dev_set_drvdata(&spmi->dev, NULL);
diff --git a/drivers/input/misc/lis3dh_acc.c b/drivers/input/misc/lis3dh_acc.c
index af96d3f..cc4ee9f 100644
--- a/drivers/input/misc/lis3dh_acc.c
+++ b/drivers/input/misc/lis3dh_acc.c
@@ -1086,26 +1086,26 @@
static struct device_attribute attributes[] = {
- __ATTR(pollrate_ms, 0666, attr_get_polling_rate,
+ __ATTR(pollrate_ms, 0664, attr_get_polling_rate,
attr_set_polling_rate),
- __ATTR(range, 0666, attr_get_range, attr_set_range),
- __ATTR(enable, 0666, attr_get_enable, attr_set_enable),
- __ATTR(int1_config, 0666, attr_get_intconfig1, attr_set_intconfig1),
- __ATTR(int1_duration, 0666, attr_get_duration1, attr_set_duration1),
- __ATTR(int1_threshold, 0666, attr_get_thresh1, attr_set_thresh1),
+ __ATTR(range, 0664, attr_get_range, attr_set_range),
+ __ATTR(enable, 0664, attr_get_enable, attr_set_enable),
+ __ATTR(int1_config, 0664, attr_get_intconfig1, attr_set_intconfig1),
+ __ATTR(int1_duration, 0664, attr_get_duration1, attr_set_duration1),
+ __ATTR(int1_threshold, 0664, attr_get_thresh1, attr_set_thresh1),
__ATTR(int1_source, 0444, attr_get_source1, NULL),
- __ATTR(click_config, 0666, attr_get_click_cfg, attr_set_click_cfg),
+ __ATTR(click_config, 0664, attr_get_click_cfg, attr_set_click_cfg),
__ATTR(click_source, 0444, attr_get_click_source, NULL),
- __ATTR(click_threshold, 0666, attr_get_click_ths, attr_set_click_ths),
- __ATTR(click_timelimit, 0666, attr_get_click_tlim,
+ __ATTR(click_threshold, 0664, attr_get_click_ths, attr_set_click_ths),
+ __ATTR(click_timelimit, 0664, attr_get_click_tlim,
attr_set_click_tlim),
- __ATTR(click_timelatency, 0666, attr_get_click_tlat,
+ __ATTR(click_timelatency, 0664, attr_get_click_tlat,
attr_set_click_tlat),
- __ATTR(click_timewindow, 0666, attr_get_click_tw, attr_set_click_tw),
+ __ATTR(click_timewindow, 0664, attr_get_click_tw, attr_set_click_tw),
#ifdef DEBUG
- __ATTR(reg_value, 0666, attr_reg_get, attr_reg_set),
- __ATTR(reg_addr, 0222, NULL, attr_addr_set),
+ __ATTR(reg_value, 0664, attr_reg_get, attr_reg_set),
+ __ATTR(reg_addr, 0220, NULL, attr_addr_set),
#endif
};
diff --git a/drivers/input/misc/mpu3050.c b/drivers/input/misc/mpu3050.c
index 04a7598..db6f93c 100644
--- a/drivers/input/misc/mpu3050.c
+++ b/drivers/input/misc/mpu3050.c
@@ -288,7 +288,7 @@
static struct device_attribute attributes[] = {
- __ATTR(pollrate_ms, 0666,
+ __ATTR(pollrate_ms, 0664,
mpu3050_attr_get_polling_rate,
mpu3050_attr_set_polling_rate),
};
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index f671806..b3bd8a0 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -363,6 +363,7 @@
int t38_start_addr;
bool update_cfg;
const char *fw_name;
+ bool no_force_update;
};
static struct dentry *debug_base;
@@ -984,9 +985,9 @@
continue;
}
- /* check whether report id is part of T9 or T15 */
id = reportid - data->t9_min_reportid;
+ /* check whether report id is part of T9,T15 or T42*/
if (reportid >= data->t9_min_reportid &&
reportid <= data->t9_max_reportid)
mxt_input_touchevent(data, &message, id);
@@ -1273,25 +1274,18 @@
data->cfg_version[0], data->cfg_version[1],
data->cfg_version[2]);
- /* It is possible that the config data on the controller is not
- * versioned and the version number returns 0. In this case,
- * find a match without the config version checking.
- */
- error = mxt_search_config_array(data,
- data->cfg_version[0] != 0 ? true : false);
+ /* configuration update requires major match */
+ error = mxt_search_config_array(data, true);
+
+ /* if no_force_update is false , try again with false
+ as the second parameter to mxt_search_config_array */
+ if (error && (data->no_force_update == false))
+ error = mxt_search_config_array(data, false);
+
if (error) {
- /* If a match wasn't found for a non-zero config version,
- * it means the controller has the wrong config data. Search
- * for a best match based on controller and firmware version,
- * but not config version.
- */
- if (data->cfg_version[0])
- error = mxt_search_config_array(data, false);
- if (error) {
- dev_err(dev,
- "Unable to find matching config in pdata\n");
- return error;
- }
+ dev_err(dev,
+ "Unable to find matching config in pdata\n");
+ return error;
}
return 0;
@@ -1418,13 +1412,62 @@
return 0;
}
+static int mxt_update_cfg(struct mxt_data *data)
+{
+ int error;
+ const u8 *cfg_ver;
+
+ /* Get config data from platform data */
+ error = mxt_get_config(data);
+ if (error)
+ dev_dbg(&data->client->dev, "Config info not found.\n");
+
+ /* Check register init values */
+ if (data->config_info && data->config_info->config) {
+ if (data->update_cfg) {
+ error = mxt_check_reg_init(data);
+ if (error) {
+ dev_err(&data->client->dev,
+ "Failed to check reg init value\n");
+ return error;
+ }
+
+ error = mxt_backup_nv(data);
+ if (error) {
+ dev_err(&data->client->dev, "Failed to back up NV\n");
+ return error;
+ }
+
+ cfg_ver = data->config_info->config +
+ data->cfg_version_idx;
+ dev_info(&data->client->dev,
+ "Config updated from %d.%d.%d to %d.%d.%d\n",
+ data->cfg_version[0], data->cfg_version[1],
+ data->cfg_version[2],
+ cfg_ver[0], cfg_ver[1], cfg_ver[2]);
+
+ memcpy(data->cfg_version, cfg_ver, MXT_CFG_VERSION_LEN);
+ }
+ } else {
+ dev_info(&data->client->dev,
+ "No cfg data defined, skipping check reg init\n");
+ }
+
+ error = mxt_save_objects(data);
+ if (error)
+ return error;
+
+ return 0;
+}
+
+
+
static int mxt_initialize(struct mxt_data *data)
{
struct i2c_client *client = data->client;
struct mxt_info *info = &data->info;
int error;
u8 val;
- const u8 *cfg_ver;
error = mxt_get_info(data);
if (error) {
@@ -1465,46 +1508,9 @@
if (error)
goto free_object_table;
- /* Get config data from platform data */
- error = mxt_get_config(data);
- if (error)
- dev_dbg(&client->dev, "Config info not found.\n");
-
- /* Check register init values */
- if (data->config_info && data->config_info->config) {
- if (data->update_cfg) {
- error = mxt_check_reg_init(data);
- if (error) {
- dev_err(&client->dev,
- "Failed to check reg init value\n");
- goto free_object_table;
- }
-
- error = mxt_backup_nv(data);
- if (error) {
- dev_err(&client->dev, "Failed to back up NV\n");
- goto free_object_table;
- }
-
- cfg_ver = data->config_info->config +
- data->cfg_version_idx;
- dev_info(&client->dev,
- "Config updated from %d.%d.%d to %d.%d.%d\n",
- data->cfg_version[0], data->cfg_version[1],
- data->cfg_version[2],
- cfg_ver[0], cfg_ver[1], cfg_ver[2]);
-
- memcpy(data->cfg_version, cfg_ver, MXT_CFG_VERSION_LEN);
- }
- } else {
- dev_info(&client->dev,
- "No cfg data defined, skipping check reg init\n");
- }
-
- error = mxt_save_objects(data);
+ error = mxt_update_cfg(data);
if (error)
goto free_object_table;
-
/* Update matrix size at info struct */
error = mxt_read_reg(client, MXT_MATRIX_X_SIZE, &val);
if (error)
@@ -1732,6 +1738,30 @@
return fw_name;
}
+static ssize_t mxt_force_cfg_update_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mxt_data *data = dev_get_drvdata(dev);
+ int flag = buf[0]-'0';
+ int error;
+ data->no_force_update = !flag;
+
+ if (data->state == APPMODE) {
+ disable_irq(data->irq);
+ error = mxt_update_cfg(data);
+ enable_irq(data->irq);
+ if (error)
+ return error;
+ } else {
+ dev_err(dev,
+ "Not in APPMODE, Unable to force cfg update\n");
+ return -EINVAL;
+ }
+
+ return count;
+}
+
static ssize_t mxt_update_fw_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
@@ -1742,7 +1772,7 @@
u8 bootldr_id;
u8 cfg_version[MXT_CFG_VERSION_LEN] = {0};
-
+ data->no_force_update = false;
/* If fw_name is set, then the existing firmware has an upgrade */
if (!data->fw_name) {
/*
@@ -1824,10 +1854,12 @@
static DEVICE_ATTR(object, 0444, mxt_object_show, NULL);
static DEVICE_ATTR(update_fw, 0664, NULL, mxt_update_fw_store);
+static DEVICE_ATTR(force_cfg_update, 0664, NULL, mxt_force_cfg_update_store);
static struct attribute *mxt_attrs[] = {
&dev_attr_object.attr,
&dev_attr_update_fw.attr,
+ &dev_attr_force_cfg_update.attr,
NULL
};
@@ -2433,6 +2465,10 @@
pdata->i2c_pull_up = of_property_read_bool(np, "atmel,i2c-pull-up");
pdata->digital_pwr_regulator = of_property_read_bool(np,
"atmel,dig-reg-support");
+
+ pdata->no_force_update = of_property_read_bool(np,
+ "atmel,no-force-update");
+
/* reset, irq gpio info */
pdata->reset_gpio = of_get_named_gpio_flags(np, "atmel,reset-gpio",
0, &pdata->reset_gpio_flags);
@@ -2583,6 +2619,7 @@
data->client = client;
data->input_dev = input_dev;
data->pdata = pdata;
+ data->no_force_update = pdata->no_force_update;
__set_bit(EV_ABS, input_dev->evbit);
__set_bit(EV_KEY, input_dev->evbit);
diff --git a/drivers/iommu/msm_iommu-v2.c b/drivers/iommu/msm_iommu-v2.c
index 9d88fdd..425eb8a 100644
--- a/drivers/iommu/msm_iommu-v2.c
+++ b/drivers/iommu/msm_iommu-v2.c
@@ -148,6 +148,9 @@
return ret;
}
+/*
+ * May only be called for non-secure iommus
+ */
static void __reset_iommu(void __iomem *base)
{
int i, smt_size;
@@ -170,6 +173,9 @@
mb();
}
+/*
+ * May only be called for non-secure iommus
+ */
static void __program_iommu(void __iomem *base,
struct msm_iommu_bfb_settings *bfb_settings)
{
@@ -223,14 +229,14 @@
static void __program_context(void __iomem *base, int ctx, int ncb,
phys_addr_t pgtable, int redirect,
- u32 *sids, int len)
+ u32 *sids, int len, bool is_secure)
{
unsigned int prrr, nmrr;
unsigned int pn;
int i, j, found, num = 0, smt_size;
__reset_context(base, ctx);
- smt_size = GET_IDR0_NUMSMRG(base);
+
pn = pgtable >> CB_TTBR0_ADDR_SHIFT;
SET_TTBCR(base, ctx, 0);
SET_CB_TTBR0_ADDR(base, ctx, pn);
@@ -266,41 +272,44 @@
SET_CB_TTBR0_RGN(base, ctx, 1); /* WB, WA */
}
- /* Program the M2V tables for this context */
- for (i = 0; i < len / sizeof(*sids); i++) {
- for (; num < smt_size; num++)
- if (GET_SMR_VALID(base, num) == 0)
- break;
- BUG_ON(num >= smt_size);
+ if (!is_secure) {
+ smt_size = GET_IDR0_NUMSMRG(base);
+ /* Program the M2V tables for this context */
+ for (i = 0; i < len / sizeof(*sids); i++) {
+ for (; num < smt_size; num++)
+ if (GET_SMR_VALID(base, num) == 0)
+ break;
+ BUG_ON(num >= smt_size);
- SET_SMR_VALID(base, num, 1);
- SET_SMR_MASK(base, num, 0);
- SET_SMR_ID(base, num, sids[i]);
+ SET_SMR_VALID(base, num, 1);
+ SET_SMR_MASK(base, num, 0);
+ SET_SMR_ID(base, num, sids[i]);
- SET_S2CR_N(base, num, 0);
- SET_S2CR_CBNDX(base, num, ctx);
- SET_S2CR_MEMATTR(base, num, 0x0A);
- /* Set security bit override to be Non-secure */
- SET_S2CR_NSCFG(base, num, 3);
+ SET_S2CR_N(base, num, 0);
+ SET_S2CR_CBNDX(base, num, ctx);
+ SET_S2CR_MEMATTR(base, num, 0x0A);
+ /* Set security bit override to be Non-secure */
+ SET_S2CR_NSCFG(base, num, 3);
+ }
+ SET_CBAR_N(base, ctx, 0);
+
+ /* Stage 1 Context with Stage 2 bypass */
+ SET_CBAR_TYPE(base, ctx, 1);
+
+ /* Route page faults to the non-secure interrupt */
+ SET_CBAR_IRPTNDX(base, ctx, 1);
+
+ /* Set VMID to non-secure HLOS */
+ SET_CBAR_VMID(base, ctx, 3);
+
+ /* Bypass is treated as inner-shareable */
+ SET_CBAR_BPSHCFG(base, ctx, 2);
+
+ /* Do not downgrade memory attributes */
+ SET_CBAR_MEMATTR(base, ctx, 0x0A);
+
}
- SET_CBAR_N(base, ctx, 0);
-
- /* Stage 1 Context with Stage 2 bypass */
- SET_CBAR_TYPE(base, ctx, 1);
-
- /* Route page faults to the non-secure interrupt */
- SET_CBAR_IRPTNDX(base, ctx, 1);
-
- /* Set VMID to non-secure HLOS */
- SET_CBAR_VMID(base, ctx, 3);
-
- /* Bypass is treated as inner-shareable */
- SET_CBAR_BPSHCFG(base, ctx, 2);
-
- /* Do not downgrade memory attributes */
- SET_CBAR_MEMATTR(base, ctx, 0x0A);
-
/* Find if this page table is used elsewhere, and re-use ASID */
found = 0;
for (i = 0; i < ncb; i++)
@@ -399,6 +408,7 @@
struct msm_iommu_ctx_drvdata *ctx_drvdata;
struct msm_iommu_ctx_drvdata *tmp_drvdata;
int ret;
+ int is_secure;
mutex_lock(&msm_iommu_lock);
@@ -426,6 +436,8 @@
goto fail;
}
+ is_secure = iommu_drvdata->sec_id != -1;
+
ret = regulator_enable(iommu_drvdata->gdsc);
if (ret)
goto fail;
@@ -436,13 +448,25 @@
goto fail;
}
- if (!msm_iommu_ctx_attached(dev->parent))
- __program_iommu(iommu_drvdata->base,
+ if (!msm_iommu_ctx_attached(dev->parent)) {
+ if (!is_secure) {
+ __program_iommu(iommu_drvdata->base,
iommu_drvdata->bfb_settings);
+ } else {
+ ret = msm_iommu_sec_program_iommu(
+ iommu_drvdata->sec_id);
+ if (ret) {
+ regulator_disable(iommu_drvdata->gdsc);
+ __disable_clocks(iommu_drvdata);
+ goto fail;
+ }
+ }
+ }
__program_context(iommu_drvdata->base, ctx_drvdata->num,
iommu_drvdata->ncb, __pa(priv->pt.fl_table),
- priv->pt.redirect, ctx_drvdata->sids, ctx_drvdata->nsid);
+ priv->pt.redirect, ctx_drvdata->sids, ctx_drvdata->nsid,
+ is_secure);
__disable_clocks(iommu_drvdata);
list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
@@ -460,6 +484,7 @@
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
int ret;
+ int is_secure;
mutex_lock(&msm_iommu_lock);
priv = domain->priv;
@@ -475,11 +500,14 @@
if (ret)
goto fail;
+ is_secure = iommu_drvdata->sec_id != -1;
+
SET_TLBIASID(iommu_drvdata->base, ctx_drvdata->num,
GET_CB_CONTEXTIDR_ASID(iommu_drvdata->base, ctx_drvdata->num));
__reset_context(iommu_drvdata->base, ctx_drvdata->num);
- __release_smg(iommu_drvdata->base, ctx_drvdata->num);
+ if (!is_secure)
+ __release_smg(iommu_drvdata->base, ctx_drvdata->num);
__disable_clocks(iommu_drvdata);
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
index bf173b3..f8c9809 100644
--- a/drivers/iommu/msm_iommu.c
+++ b/drivers/iommu/msm_iommu.c
@@ -772,6 +772,55 @@
&& (len >= align);
}
+static int check_range(unsigned long *fl_table, unsigned int va,
+ unsigned int len)
+{
+ unsigned int offset = 0;
+ unsigned long *fl_pte;
+ unsigned long fl_offset;
+ unsigned long *sl_table;
+ unsigned long sl_start, sl_end;
+ int i;
+
+ fl_offset = FL_OFFSET(va); /* Upper 12 bits */
+ fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
+
+ while (offset < len) {
+ if (*fl_pte & FL_TYPE_TABLE) {
+ sl_start = SL_OFFSET(va);
+ sl_table = __va(((*fl_pte) & FL_BASE_MASK));
+ sl_end = ((len - offset) / SZ_4K) + sl_start;
+
+ if (sl_end > NUM_SL_PTE)
+ sl_end = NUM_SL_PTE;
+
+ for (i = sl_start; i < sl_end; i++) {
+ if (sl_table[i] != 0) {
+ pr_err("%08x - %08x already mapped\n",
+ va, va + SZ_4K);
+ return -EBUSY;
+ }
+ offset += SZ_4K;
+ va += SZ_4K;
+ }
+
+
+ sl_start = 0;
+ } else {
+ if (*fl_pte != 0) {
+ pr_err("%08x - %08x already mapped\n",
+ va, va + SZ_1M);
+ return -EBUSY;
+ }
+ va += SZ_1M;
+ offset += SZ_1M;
+ sl_start = 0;
+ }
+ fl_pte++;
+ }
+ return 0;
+}
+
static int msm_iommu_map_range(struct iommu_domain *domain, unsigned int va,
struct scatterlist *sg, unsigned int len,
int prot)
@@ -804,6 +853,9 @@
ret = -EINVAL;
goto fail;
}
+ ret = check_range(fl_table, va, len);
+ if (ret)
+ goto fail;
fl_offset = FL_OFFSET(va); /* Upper 12 bits */
fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
diff --git a/drivers/iommu/msm_iommu_dev-v2.c b/drivers/iommu/msm_iommu_dev-v2.c
index ea6c87c..5a0b593 100644
--- a/drivers/iommu/msm_iommu_dev-v2.c
+++ b/drivers/iommu/msm_iommu_dev-v2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012 Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -21,7 +21,6 @@
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/slab.h>
-#include <linux/atomic.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
@@ -95,9 +94,8 @@
struct device_node *child;
int ret = 0;
- ret = device_move(&pdev->dev, &msm_iommu_root_dev->dev, DPM_ORDER_NONE);
- if (ret)
- goto fail;
+ drvdata->dev = &pdev->dev;
+ msm_iommu_add_drv(drvdata);
ret = msm_iommu_parse_bfb_settings(pdev, drvdata);
if (ret)
@@ -118,20 +116,12 @@
return ret;
}
-static atomic_t msm_iommu_next_id = ATOMIC_INIT(-1);
-
static int __devinit msm_iommu_probe(struct platform_device *pdev)
{
struct msm_iommu_drvdata *drvdata;
struct resource *r;
int ret, needs_alt_core_clk;
- if (msm_iommu_root_dev == pdev)
- return 0;
-
- if (pdev->id == -1)
- pdev->id = atomic_inc_return(&msm_iommu_next_id) - 1;
-
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
@@ -192,6 +182,7 @@
drv = platform_get_drvdata(pdev);
if (drv) {
+ msm_iommu_remove_drv(drv);
if (drv->clk)
clk_put(drv->clk);
clk_put(drv->pclk);
@@ -315,25 +306,8 @@
static int __init msm_iommu_driver_init(void)
{
- struct device_node *node;
int ret;
- node = of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v2");
- if (!node)
- return -ENODEV;
-
- of_node_put(node);
-
- msm_iommu_root_dev = platform_device_register_simple(
- "msm_iommu", -1, 0, 0);
- if (!msm_iommu_root_dev) {
- pr_err("Failed to create root IOMMU device\n");
- ret = -ENODEV;
- goto error;
- }
-
- atomic_inc(&msm_iommu_next_id);
-
ret = platform_driver_register(&msm_iommu_driver);
if (ret != 0) {
pr_err("Failed to register IOMMU driver\n");
@@ -354,7 +328,6 @@
{
platform_driver_unregister(&msm_iommu_ctx_driver);
platform_driver_unregister(&msm_iommu_driver);
- platform_device_unregister(msm_iommu_root_dev);
}
subsys_initcall(msm_iommu_driver_init);
diff --git a/drivers/iommu/msm_iommu_dev.c b/drivers/iommu/msm_iommu_dev.c
index 967283d..d9eddcd 100644
--- a/drivers/iommu/msm_iommu_dev.c
+++ b/drivers/iommu/msm_iommu_dev.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -21,62 +21,63 @@
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
#include <mach/iommu_hw-8xxx.h>
#include <mach/iommu.h>
-struct iommu_ctx_iter_data {
- /* input */
- const char *name;
+static DEFINE_MUTEX(iommu_list_lock);
+static LIST_HEAD(iommu_list);
- /* output */
- struct device *dev;
-};
-
-struct platform_device *msm_iommu_root_dev;
-
-static int each_iommu_ctx(struct device *dev, void *data)
+void msm_iommu_add_drv(struct msm_iommu_drvdata *drv)
{
- struct iommu_ctx_iter_data *res = data;
+ mutex_lock(&iommu_list_lock);
+ list_add(&drv->list, &iommu_list);
+ mutex_unlock(&iommu_list_lock);
+}
+
+void msm_iommu_remove_drv(struct msm_iommu_drvdata *drv)
+{
+ mutex_lock(&iommu_list_lock);
+ list_del(&drv->list);
+ mutex_unlock(&iommu_list_lock);
+}
+
+static int find_iommu_ctx(struct device *dev, void *data)
+{
struct msm_iommu_ctx_drvdata *c;
c = dev_get_drvdata(dev);
- if (!res || !c || !c->name || !res->name)
- return -EINVAL;
+ if (!c || !c->name)
+ return 0;
- if (!strcmp(res->name, c->name)) {
- res->dev = dev;
- return 1;
- }
- return 0;
+ return !strcmp(data, c->name);
}
-static int each_iommu(struct device *dev, void *data)
+static struct device *find_context(struct device *dev, const char *name)
{
- return device_for_each_child(dev, data, each_iommu_ctx);
+ return device_find_child(dev, (void *)name, find_iommu_ctx);
}
struct device *msm_iommu_get_ctx(const char *ctx_name)
{
- struct iommu_ctx_iter_data r;
- int found;
+ struct msm_iommu_drvdata *drv;
+ struct device *dev = NULL;
- if (!msm_iommu_root_dev) {
- pr_err("No root IOMMU device.\n");
- goto fail;
+ mutex_lock(&iommu_list_lock);
+ list_for_each_entry(drv, &iommu_list, list) {
+ dev = find_context(drv->dev, ctx_name);
+ if (dev)
+ break;
}
+ mutex_unlock(&iommu_list_lock);
- r.name = ctx_name;
- found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
-
- if (found <= 0 || !dev_get_drvdata(r.dev)) {
+ if (!dev || !dev_get_drvdata(dev))
pr_err("Could not find context <%s>\n", ctx_name);
- goto fail;
- }
+ put_device(dev);
- return r.dev;
-fail:
- return NULL;
+ return dev;
}
EXPORT_SYMBOL(msm_iommu_get_ctx);
@@ -134,11 +135,6 @@
resource_size_t len;
int ret, par;
- if (pdev->id == -1) {
- msm_iommu_root_dev = pdev;
- return 0;
- }
-
drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
if (!drvdata) {
@@ -227,6 +223,9 @@
drvdata->ncb = iommu_dev->ncb;
drvdata->ttbr_split = iommu_dev->ttbr_split;
drvdata->name = iommu_dev->name;
+ drvdata->dev = &pdev->dev;
+
+ msm_iommu_add_drv(drvdata);
pr_info("device %s mapped at %p, with %d ctx banks\n",
iommu_dev->name, regs_base, iommu_dev->ncb);
@@ -263,6 +262,7 @@
drv = platform_get_drvdata(pdev);
if (drv) {
+ msm_iommu_remove_drv(drv);
if (drv->clk)
clk_put(drv->clk);
clk_put(drv->pclk);
diff --git a/drivers/iommu/msm_iommu_sec.c b/drivers/iommu/msm_iommu_sec.c
index a89c4a8..72ec4a6 100644
--- a/drivers/iommu/msm_iommu_sec.c
+++ b/drivers/iommu/msm_iommu_sec.c
@@ -128,7 +128,7 @@
return ret;
}
-static int msm_iommu_sec_program_iommu(int sec_id)
+int msm_iommu_sec_program_iommu(int sec_id)
{
struct msm_scm_sec_cfg {
unsigned int id;
diff --git a/drivers/leds/leds-qpnp.c b/drivers/leds/leds-qpnp.c
index 696c9f9..d658217 100644
--- a/drivers/leds/leds-qpnp.c
+++ b/drivers/leds/leds-qpnp.c
@@ -21,6 +21,7 @@
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/spmi.h>
+#include <linux/qpnp/pwm.h>
#define WLED_MOD_EN_REG(base, n) (base + 0x60 + n*0x10)
#define WLED_IDAC_DLY_REG(base, n) (WLED_MOD_EN_REG(base, n) + 0x01)
@@ -75,14 +76,85 @@
#define WLED_CTRL_DLY_DEFAULT 0x00
#define WLED_SWITCH_FREQ_DEFAULT 0x02
+#define FLASH_SAFETY_TIMER(base) (base + 0x40)
+#define FLASH_MAX_CURR(base) (base + 0x41)
+#define FLASH_LED_0_CURR(base) (base + 0x42)
+#define FLASH_LED_1_CURR(base) (base + 0x43)
+#define FLASH_CLAMP_CURR(base) (base + 0x44)
+#define FLASH_LED_TMR_CTRL(base) (base + 0x48)
+#define FLASH_HEADROOM(base) (base + 0x49)
+#define FLASH_STARTUP_DELAY(base) (base + 0x4B)
+#define FLASH_MASK_ENABLE(base) (base + 0x4C)
+#define FLASH_VREG_OK_FORCE(base) (base + 0x4F)
+#define FLASH_ENABLE_CONTROL(base) (base + 0x46)
+#define FLASH_LED_STROBE_CTRL(base) (base + 0x47)
+
+#define FLASH_MAX_LEVEL 0x4F
+#define FLASH_NO_MASK 0x00
+
+#define FLASH_MASK_1 0x20
+#define FLASH_MASK_REG_MASK 0xE0
+#define FLASH_HEADROOM_MASK 0x03
+#define FLASH_SAFETY_TIMER_MASK 0x7F
+#define FLASH_CURRENT_MASK 0xFF
+#define FLASH_TMR_MASK 0x03
+#define FLASH_TMR_WATCHDOG 0x03
+#define FLASH_TMR_SAFETY 0x00
+
+#define FLASH_HW_VREG_OK 0x80
+#define FLASH_VREG_MASK 0xC0
+
+#define FLASH_STARTUP_DLY_MASK 0x02
+
+#define FLASH_ENABLE_ALL 0xE0
+#define FLASH_ENABLE_MODULE 0x80
+#define FLASH_ENABLE_MODULE_MASK 0x80
+#define FLASH_DISABLE_ALL 0x00
+#define FLASH_ENABLE_MASK 0x60
+#define FLASH_ENABLE_LED_0 0x40
+#define FLASH_ENABLE_LED_1 0x20
+#define FLASH_INIT_MASK 0xE0
+
+#define FLASH_STROBE_ALL 0xC0
+#define FLASH_STROBE_MASK 0xC0
+#define FLASH_LED_0_OUTPUT 0x80
+#define FLASH_LED_1_OUTPUT 0x40
+
+#define FLASH_CURRENT_PRGM_MIN 1
+#define FLASH_CURRENT_PRGM_SHIFT 1
+
+#define FLASH_DURATION_200ms 0x13
+#define FLASH_CLAMP_200mA 0x0F
+
#define LED_TRIGGER_DEFAULT "none"
+#define RGB_LED_SRC_SEL(base) (base + 0x45)
+#define RGB_LED_EN_CTL(base) (base + 0x46)
+#define RGB_LED_ATC_CTL(base) (base + 0x47)
+
+#define RGB_MAX_LEVEL LED_FULL
+#define RGB_LED_ENABLE_RED 0x80
+#define RGB_LED_ENABLE_GREEN 0x40
+#define RGB_LED_ENABLE_BLUE 0x20
+#define RGB_LED_SOURCE_VPH_PWR 0x01
+#define RGB_LED_ENABLE_MASK 0xE0
+#define RGB_LED_SRC_MASK 0x03
+#define QPNP_LED_PWM_FLAGS (PM_PWM_LUT_LOOP | PM_PWM_LUT_RAMP_UP)
+#define PWM_LUT_MAX_SIZE 63
+#define RGB_LED_DISABLE 0x00
+
/**
* enum qpnp_leds - QPNP supported led ids
* @QPNP_ID_WLED - White led backlight
*/
enum qpnp_leds {
- QPNP_ID_WLED,
+ QPNP_ID_WLED = 0,
+ QPNP_ID_FLASH1_LED0,
+ QPNP_ID_FLASH1_LED1,
+ QPNP_ID_RGB_RED,
+ QPNP_ID_RGB_GREEN,
+ QPNP_ID_RGB_BLUE,
+ QPNP_ID_MAX,
};
/* current boost limit */
@@ -113,6 +185,25 @@
WLED_3200kHz,
};
+enum flash_headroom {
+ HEADROOM_250mV = 0,
+ HEADROOM_300mV,
+ HEADROOM_400mV,
+ HEADROOM_500mV,
+};
+
+enum flash_startup_dly {
+ DELAY_10us = 0,
+ DELAY_32us,
+ DELAY_64us,
+ DELAY_128us,
+};
+
+enum rgb_mode {
+ RGB_MODE_PWM = 0,
+ RGB_MODE_LPG,
+};
+
static u8 wled_debug_regs[] = {
/* common registers */
0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4d, 0x4e, 0x4f,
@@ -125,6 +216,14 @@
0x80, 0x81, 0x82, 0x83, 0x86,
};
+static u8 flash_debug_regs[] = {
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x48, 0x49, 0x4b, 0x4c,
+ 0x4f, 0x46, 0x47,
+};
+
+static u8 rgb_pwm_debug_regs[] = {
+ 0x45, 0x46, 0x47,
+};
/**
* wled_config_data - wled configuration data
* @num_strings - number of wled strings supported
@@ -149,6 +248,50 @@
};
/**
+ * flash_config_data - flash configuration data
+ * @current_prgm - current to be programmed, scaled by max level
+ * @clamp_curr - clamp current to use
+ * @headroom - headroom value to use
+ * @duration - duration of the flash
+ * @enable_module - enable address for particular flash
+ * @trigger_flash - trigger flash
+ * @startup_dly - startup delay for flash
+ * @current_addr - address to write for current
+ * @second_addr - address of secondary flash to be written
+ * @safety_timer - enable safety timer or watchdog timer
+ */
+struct flash_config_data {
+ u8 current_prgm;
+ u8 clamp_curr;
+ u8 headroom;
+ u8 duration;
+ u8 enable_module;
+ u8 trigger_flash;
+ u8 startup_dly;
+ u16 current_addr;
+ u16 second_addr;
+ bool safety_timer;
+};
+
+/**
+ * rgb_config_data - rgb configuration data
+ * @lut_params - lut parameters to be used by pwm driver
+ * @pwm_device - pwm device
+ * @pwm_channel - pwm channel to be configured for led
+ * @pwm_period_us - period for pwm, in us
+ * @mode - mode the led operates in
+ */
+struct rgb_config_data {
+ struct lut_params lut_params;
+ struct pwm_device *pwm_dev;
+ int pwm_channel;
+ u32 pwm_period_us;
+ struct pwm_duty_cycles *duty_cycles;
+ u8 mode;
+ u8 enable;
+};
+
+/**
* struct qpnp_led_data - internal led data structure
* @led_classdev - led class device
* @id - led index
@@ -168,6 +311,8 @@
u8 num_leds;
spinlock_t lock;
struct wled_config_data *wled_cfg;
+ struct flash_config_data *flash_cfg;
+ struct rgb_config_data *rgb_cfg;
int max_current;
bool default_on;
};
@@ -289,6 +434,123 @@
return 0;
}
+static int qpnp_flash_set(struct qpnp_led_data *led)
+{
+ int rc;
+ int val = led->cdev.brightness;
+
+ led->flash_cfg->current_prgm = (val * FLASH_MAX_LEVEL /
+ led->max_current);
+
+ led->flash_cfg->current_prgm =
+ led->flash_cfg->current_prgm >> FLASH_CURRENT_PRGM_SHIFT;
+ if (!led->flash_cfg->current_prgm)
+ led->flash_cfg->current_prgm = FLASH_CURRENT_PRGM_MIN;
+
+ /* Set led current */
+ if (val > 0) {
+ rc = qpnp_led_masked_write(led, led->flash_cfg->current_addr,
+ FLASH_CURRENT_MASK, led->flash_cfg->current_prgm);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Current reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_led_masked_write(led, led->flash_cfg->second_addr,
+ FLASH_CURRENT_MASK, led->flash_cfg->current_prgm);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Current reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_led_masked_write(led, FLASH_ENABLE_CONTROL(led->base),
+ FLASH_ENABLE_MASK,
+ FLASH_ENABLE_ALL);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Enable reg write failed(%d)\n", rc);
+ return rc;
+ }
+ rc = qpnp_led_masked_write(led,
+ FLASH_LED_STROBE_CTRL(led->base),
+ FLASH_STROBE_MASK, FLASH_STROBE_ALL);
+
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "LED %d flash write failed(%d)\n", led->id, rc);
+ return rc;
+ }
+ } else {
+ rc = qpnp_led_masked_write(led, FLASH_ENABLE_CONTROL(led->base),
+ FLASH_ENABLE_MASK,
+ FLASH_DISABLE_ALL);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Enable reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_led_masked_write(led,
+ FLASH_LED_STROBE_CTRL(led->base),
+ FLASH_STROBE_MASK,
+ FLASH_DISABLE_ALL);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "LED %d flash write failed(%d)\n", led->id, rc);
+ return rc;
+ }
+ }
+
+ qpnp_dump_regs(led, flash_debug_regs, ARRAY_SIZE(flash_debug_regs));
+
+ return 0;
+}
+
+static int qpnp_rgb_set(struct qpnp_led_data *led)
+{
+ int duty_us;
+ int rc;
+
+ if (led->cdev.brightness) {
+ if (led->rgb_cfg->mode == RGB_MODE_PWM) {
+ duty_us = (led->rgb_cfg->pwm_period_us *
+ led->cdev.brightness) / LED_FULL;
+ rc = pwm_config(led->rgb_cfg->pwm_dev, duty_us,
+ led->rgb_cfg->pwm_period_us);
+ if (rc < 0) {
+ dev_err(&led->spmi_dev->dev, "Failed to " \
+ "configure pwm for new values\n");
+ return rc;
+ }
+ }
+ rc = qpnp_led_masked_write(led,
+ RGB_LED_EN_CTL(led->base),
+ led->rgb_cfg->enable, led->rgb_cfg->enable);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Failed to write led enable reg\n");
+ return rc;
+ }
+ rc = pwm_enable(led->rgb_cfg->pwm_dev);
+ } else {
+ pwm_disable(led->rgb_cfg->pwm_dev);
+ rc = qpnp_led_masked_write(led,
+ RGB_LED_EN_CTL(led->base),
+ led->rgb_cfg->enable, RGB_LED_DISABLE);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Failed to write led enable reg\n");
+ return rc;
+ }
+ }
+
+ qpnp_dump_regs(led, rgb_pwm_debug_regs, ARRAY_SIZE(rgb_pwm_debug_regs));
+
+ return 0;
+}
+
static void qpnp_led_set(struct led_classdev *led_cdev,
enum led_brightness value)
{
@@ -311,6 +573,21 @@
dev_err(&led->spmi_dev->dev,
"WLED set brightness failed (%d)\n", rc);
break;
+ case QPNP_ID_FLASH1_LED0:
+ case QPNP_ID_FLASH1_LED1:
+ rc = qpnp_flash_set(led);
+ if (rc < 0)
+ dev_err(&led->spmi_dev->dev,
+ "FLASH set brightness failed (%d)\n", rc);
+ break;
+ case QPNP_ID_RGB_RED:
+ case QPNP_ID_RGB_GREEN:
+ case QPNP_ID_RGB_BLUE:
+ rc = qpnp_rgb_set(led);
+ if (rc < 0)
+ dev_err(&led->spmi_dev->dev,
+ "RGB set brightness failed (%d)\n", rc);
+ break;
default:
dev_err(&led->spmi_dev->dev, "Invalid LED(%d)\n", led->id);
break;
@@ -324,6 +601,15 @@
case QPNP_ID_WLED:
led->cdev.max_brightness = WLED_MAX_LEVEL;
break;
+ case QPNP_ID_FLASH1_LED0:
+ case QPNP_ID_FLASH1_LED1:
+ led->cdev.max_brightness = led->max_current;
+ break;
+ case QPNP_ID_RGB_RED:
+ case QPNP_ID_RGB_GREEN:
+ case QPNP_ID_RGB_BLUE:
+ led->cdev.max_brightness = RGB_MAX_LEVEL;
+ break;
default:
dev_err(&led->spmi_dev->dev, "Invalid LED(%d)\n", led->id);
return -EINVAL;
@@ -471,6 +757,189 @@
return 0;
}
+static int __devinit qpnp_flash_init(struct qpnp_led_data *led)
+{
+ int rc;
+
+ rc = qpnp_led_masked_write(led,
+ FLASH_LED_STROBE_CTRL(led->base),
+ FLASH_STROBE_MASK, FLASH_DISABLE_ALL);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "LED %d flash write failed(%d)\n", led->id, rc);
+ return rc;
+ }
+ rc = qpnp_led_masked_write(led, FLASH_ENABLE_CONTROL(led->base),
+ FLASH_INIT_MASK, FLASH_ENABLE_MODULE);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Enable reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set flash safety timer */
+ rc = qpnp_led_masked_write(led, FLASH_SAFETY_TIMER(led->base),
+ FLASH_SAFETY_TIMER_MASK, led->flash_cfg->duration);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Safety timer reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set max current */
+ rc = qpnp_led_masked_write(led, FLASH_MAX_CURR(led->base),
+ FLASH_CURRENT_MASK, FLASH_MAX_LEVEL);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Max current reg write failed(%d)\n", rc);
+ return rc;
+ }
+ /* Set clamp current */
+ rc = qpnp_led_masked_write(led, FLASH_CLAMP_CURR(led->base),
+ FLASH_CURRENT_MASK, led->flash_cfg->clamp_curr);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Clamp current reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set timer control - safety or watchdog */
+ if (led->flash_cfg->safety_timer)
+ rc = qpnp_led_masked_write(led, FLASH_LED_TMR_CTRL(led->base),
+ FLASH_TMR_MASK, FLASH_TMR_SAFETY);
+ else
+ rc = qpnp_led_masked_write(led, FLASH_LED_TMR_CTRL(led->base),
+ FLASH_TMR_MASK, FLASH_TMR_WATCHDOG);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "LED timer ctrl reg write failed(%d)\n", rc);
+ return rc;
+ }
+ /* Set headroom */
+ rc = qpnp_led_masked_write(led, FLASH_HEADROOM(led->base),
+ FLASH_HEADROOM_MASK, led->flash_cfg->headroom);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Headroom reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set mask enable */
+ rc = qpnp_led_masked_write(led, FLASH_MASK_ENABLE(led->base),
+ FLASH_MASK_REG_MASK, FLASH_MASK_1);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Mask enable reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set startup delay */
+ rc = qpnp_led_masked_write(led, FLASH_STARTUP_DELAY(led->base),
+ FLASH_STARTUP_DLY_MASK, led->flash_cfg->startup_dly);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Startup delay reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_led_masked_write(led, FLASH_VREG_OK_FORCE(led->base),
+ FLASH_VREG_MASK, FLASH_HW_VREG_OK);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Vreg OK reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ /* Set led current and enable module */
+ rc = qpnp_led_masked_write(led, led->flash_cfg->current_addr,
+ FLASH_CURRENT_MASK, led->flash_cfg->current_prgm);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Current reg write failed(%d)\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_led_masked_write(led, FLASH_ENABLE_CONTROL(led->base),
+ FLASH_ENABLE_MODULE_MASK, FLASH_ENABLE_MODULE);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Enable reg write failed(%d)\n", rc);
+ return rc;
+ }
+ /* dump flash registers */
+ qpnp_dump_regs(led, flash_debug_regs, ARRAY_SIZE(flash_debug_regs));
+
+ return 0;
+}
+
+static int __devinit qpnp_rgb_init(struct qpnp_led_data *led)
+{
+ int rc, start_idx, idx_len;
+
+ rc = qpnp_led_masked_write(led, RGB_LED_SRC_SEL(led->base),
+ RGB_LED_SRC_MASK, RGB_LED_SOURCE_VPH_PWR);
+ if (rc) {
+ dev_err(&led->spmi_dev->dev,
+ "Failed to write led source select register\n");
+ return rc;
+ }
+
+ if (led->rgb_cfg->pwm_channel != -1) {
+ led->rgb_cfg->pwm_dev =
+ pwm_request(led->rgb_cfg->pwm_channel,
+ led->cdev.name);
+
+ if (IS_ERR_OR_NULL(led->rgb_cfg->pwm_dev)) {
+ dev_err(&led->spmi_dev->dev,
+ "could not acquire PWM Channel %d, " \
+ "error %ld\n",
+ led->rgb_cfg->pwm_channel,
+ PTR_ERR(led->rgb_cfg->pwm_dev));
+ led->rgb_cfg->pwm_dev = NULL;
+ return -ENODEV;
+ }
+
+ if (led->rgb_cfg->mode == RGB_MODE_LPG) {
+ start_idx =
+ led->rgb_cfg->duty_cycles->start_idx;
+ idx_len =
+ led->rgb_cfg->duty_cycles->num_duty_pcts;
+
+ if (idx_len >= PWM_LUT_MAX_SIZE &&
+ start_idx) {
+ dev_err(&led->spmi_dev->dev,
+ "Wrong LUT size or index\n");
+ return -EINVAL;
+ }
+ if ((start_idx + idx_len) >
+ PWM_LUT_MAX_SIZE) {
+ dev_err(&led->spmi_dev->dev,
+ "Exceed LUT limit\n");
+ return -EINVAL;
+ }
+ rc = pwm_lut_config(led->rgb_cfg->pwm_dev,
+ led->rgb_cfg->pwm_period_us,
+ led->rgb_cfg->duty_cycles->duty_pcts,
+ led->rgb_cfg->lut_params);
+ if (rc < 0) {
+ dev_err(&led->spmi_dev->dev, "Failed to " \
+ "configure pwm LUT\n");
+ return rc;
+ }
+ }
+ } else {
+ dev_err(&led->spmi_dev->dev,
+ "Invalid PWM channel\n");
+ return -EINVAL;
+ }
+
+ /* Initialize led for use in auto trickle charging mode */
+ rc = qpnp_led_masked_write(led, RGB_LED_ATC_CTL(led->base),
+ led->rgb_cfg->enable, led->rgb_cfg->enable);
+
+ return 0;
+}
+
static int __devinit qpnp_led_initialize(struct qpnp_led_data *led)
{
int rc;
@@ -482,12 +951,27 @@
dev_err(&led->spmi_dev->dev,
"WLED initialize failed(%d)\n", rc);
break;
+ case QPNP_ID_FLASH1_LED0:
+ case QPNP_ID_FLASH1_LED1:
+ rc = qpnp_flash_init(led);
+ if (rc)
+ dev_err(&led->spmi_dev->dev,
+ "FLASH initialize failed(%d)\n", rc);
+ break;
+ case QPNP_ID_RGB_RED:
+ case QPNP_ID_RGB_GREEN:
+ case QPNP_ID_RGB_BLUE:
+ rc = qpnp_rgb_init(led);
+ if (rc)
+ dev_err(&led->spmi_dev->dev,
+ "RGB initialize failed(%d)\n", rc);
+ break;
default:
dev_err(&led->spmi_dev->dev, "Invalid LED(%d)\n", led->id);
- rc = -EINVAL;
+ return -EINVAL;
}
- return rc;
+ return 0;
}
static int __devinit qpnp_get_common_configs(struct qpnp_led_data *led,
@@ -586,6 +1070,194 @@
return 0;
}
+static int __devinit qpnp_get_config_flash(struct qpnp_led_data *led,
+ struct device_node *node)
+{
+ int rc;
+ u32 val;
+
+ led->flash_cfg = devm_kzalloc(&led->spmi_dev->dev,
+ sizeof(struct flash_config_data), GFP_KERNEL);
+ if (!led->flash_cfg) {
+ dev_err(&led->spmi_dev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ if (led->id == QPNP_ID_FLASH1_LED0) {
+ led->flash_cfg->enable_module = FLASH_ENABLE_ALL;
+ led->flash_cfg->current_addr = FLASH_LED_0_CURR(led->base);
+ led->flash_cfg->second_addr = FLASH_LED_1_CURR(led->base);
+ led->flash_cfg->trigger_flash = FLASH_LED_0_OUTPUT;
+ } else if (led->id == QPNP_ID_FLASH1_LED1) {
+ led->flash_cfg->enable_module = FLASH_ENABLE_ALL;
+ led->flash_cfg->current_addr = FLASH_LED_1_CURR(led->base);
+ led->flash_cfg->second_addr = FLASH_LED_0_CURR(led->base);
+ led->flash_cfg->trigger_flash = FLASH_LED_1_OUTPUT;
+ } else {
+ dev_err(&led->spmi_dev->dev, "Unknown flash LED name given\n");
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(node, "qcom,current", &val);
+ if (!rc)
+ led->flash_cfg->current_prgm = (val *
+ FLASH_MAX_LEVEL / led->max_current);
+ else
+ return -EINVAL;
+
+ rc = of_property_read_u32(node, "qcom,headroom", &val);
+ if (!rc)
+ led->flash_cfg->headroom = (u8) val;
+ else if (rc == -EINVAL)
+ led->flash_cfg->headroom = HEADROOM_300mV;
+ else
+ return rc;
+
+ rc = of_property_read_u32(node, "qcom,duration", &val);
+ if (!rc)
+ led->flash_cfg->duration = (((u8) val) - 10) / 10;
+ else if (rc == -EINVAL)
+ led->flash_cfg->duration = FLASH_DURATION_200ms;
+ else
+ return rc;
+
+ rc = of_property_read_u32(node, "qcom,clamp-curr", &val);
+ if (!rc)
+ led->flash_cfg->clamp_curr = (val *
+ FLASH_MAX_LEVEL / led->max_current);
+ else if (rc == -EINVAL)
+ led->flash_cfg->clamp_curr = FLASH_CLAMP_200mA;
+ else
+ return rc;
+
+ rc = of_property_read_u32(node, "qcom,startup-dly", &val);
+ if (!rc)
+ led->flash_cfg->startup_dly = (u8) val;
+ else if (rc == -EINVAL)
+ led->flash_cfg->startup_dly = DELAY_32us;
+ else
+ return rc;
+
+ led->flash_cfg->safety_timer =
+ of_property_read_bool(node, "qcom,safety-timer");
+
+ return 0;
+}
+
+static int __devinit qpnp_get_config_rgb(struct qpnp_led_data *led,
+ struct device_node *node)
+{
+ struct property *prop;
+ int rc, i;
+ u32 val;
+ u8 *temp_cfg;
+
+ led->rgb_cfg = devm_kzalloc(&led->spmi_dev->dev,
+ sizeof(struct rgb_config_data), GFP_KERNEL);
+ if (!led->rgb_cfg) {
+ dev_err(&led->spmi_dev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ if (led->id == QPNP_ID_RGB_RED)
+ led->rgb_cfg->enable = RGB_LED_ENABLE_RED;
+ else if (led->id == QPNP_ID_RGB_GREEN)
+ led->rgb_cfg->enable = RGB_LED_ENABLE_GREEN;
+ else if (led->id == QPNP_ID_RGB_BLUE)
+ led->rgb_cfg->enable = RGB_LED_ENABLE_BLUE;
+ else
+ return -EINVAL;
+
+ rc = of_property_read_u32(node, "qcom,mode", &val);
+ if (!rc)
+ led->rgb_cfg->mode = (u8) val;
+ else
+ return rc;
+
+ rc = of_property_read_u32(node, "qcom,pwm-channel", &val);
+ if (!rc)
+ led->rgb_cfg->pwm_channel = (u8) val;
+ else
+ return rc;
+
+ rc = of_property_read_u32(node, "qcom,pwm-us", &val);
+ if (!rc)
+ led->rgb_cfg->pwm_period_us = val;
+ else
+ return rc;
+
+ if (led->rgb_cfg->mode == RGB_MODE_LPG) {
+ led->rgb_cfg->duty_cycles =
+ devm_kzalloc(&led->spmi_dev->dev,
+ sizeof(struct pwm_duty_cycles), GFP_KERNEL);
+ if (!led->rgb_cfg->duty_cycles) {
+ dev_err(&led->spmi_dev->dev,
+ "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ rc = of_property_read_u32(node, "qcom,duty-ms", &val);
+ if (!rc)
+ led->rgb_cfg->duty_cycles->duty_ms = (u8) val;
+ else
+ return rc;
+
+ prop = of_find_property(node, "qcom,duty-pcts",
+ &led->rgb_cfg->duty_cycles->num_duty_pcts);
+ if (!prop) {
+ dev_err(&led->spmi_dev->dev, "Looking up property " \
+ "node qcom,duty-pcts failed\n");
+ return -ENODEV;
+ } else if (!led->rgb_cfg->duty_cycles->num_duty_pcts) {
+ dev_err(&led->spmi_dev->dev, "Invalid length of " \
+ "duty pcts\n");
+ return -EINVAL;
+ }
+
+ led->rgb_cfg->duty_cycles->duty_pcts =
+ devm_kzalloc(&led->spmi_dev->dev,
+ sizeof(int) * led->rgb_cfg->duty_cycles->num_duty_pcts,
+ GFP_KERNEL);
+ if (!led->rgb_cfg->duty_cycles->duty_pcts) {
+ dev_err(&led->spmi_dev->dev,
+ "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ temp_cfg = devm_kzalloc(&led->spmi_dev->dev,
+ led->rgb_cfg->duty_cycles->num_duty_pcts *
+ sizeof(u8), GFP_KERNEL);
+ if (!temp_cfg) {
+ dev_err(&led->spmi_dev->dev, "Failed to allocate " \
+ "memory for duty pcts\n");
+ return -ENOMEM;
+ }
+
+ memcpy(temp_cfg, prop->value,
+ led->rgb_cfg->duty_cycles->num_duty_pcts);
+
+ for (i = 0; i < led->rgb_cfg->duty_cycles->num_duty_pcts; i++)
+ led->rgb_cfg->duty_cycles->duty_pcts[i] =
+ (int) temp_cfg[i];
+
+ rc = of_property_read_u32(node, "qcom,start-idx", &val);
+ if (!rc) {
+ led->rgb_cfg->lut_params.start_idx = (u8) val;
+ led->rgb_cfg->duty_cycles->start_idx = (u8) val;
+ } else
+ return rc;
+
+ led->rgb_cfg->lut_params.idx_len =
+ led->rgb_cfg->duty_cycles->num_duty_pcts;
+ led->rgb_cfg->lut_params.lut_pause_hi = 0;
+ led->rgb_cfg->lut_params.lut_pause_lo = 0;
+ led->rgb_cfg->lut_params.ramp_step_ms = 255;
+ led->rgb_cfg->lut_params.flags = QPNP_LED_PWM_FLAGS;
+ }
+
+ return 0;
+}
+
static int __devinit qpnp_leds_probe(struct spmi_device *spmi)
{
struct qpnp_led_data *led;
@@ -673,6 +1345,21 @@
"Unable to read wled config data\n");
return rc;
}
+ } else if (strncmp(led_label, "flash", sizeof("flash"))
+ == 0) {
+ rc = qpnp_get_config_flash(led, temp);
+ if (rc < 0) {
+ dev_err(&led->spmi_dev->dev,
+ "Unable to read flash config data\n");
+ return rc;
+ }
+ } else if (strncmp(led_label, "rgb", sizeof("rgb")) == 0) {
+ rc = qpnp_get_config_rgb(led, temp);
+ if (rc < 0) {
+ dev_err(&led->spmi_dev->dev,
+ "Unable to read rgb config data\n");
+ return rc;
+ }
} else {
dev_err(&led->spmi_dev->dev, "No LED matching label\n");
return -EINVAL;
@@ -751,3 +1438,4 @@
MODULE_DESCRIPTION("QPNP LEDs driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("leds:leds-qpnp");
+
diff --git a/drivers/media/dvb/dvb-core/demux.h b/drivers/media/dvb/dvb-core/demux.h
index 7190af8..b7ace53 100644
--- a/drivers/media/dvb/dvb-core/demux.h
+++ b/drivers/media/dvb/dvb-core/demux.h
@@ -336,6 +336,8 @@
void* priv; /* Pointer to private data of the API client */
struct data_buffer dvr_input; /* DVR input buffer */
+ struct dentry *debugfs_demux_dir; /* debugfs dir */
+
int (*open) (struct dmx_demux* demux);
int (*close) (struct dmx_demux* demux);
int (*write) (struct dmx_demux *demux, const char *buf, size_t count);
diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c
index cbd3b38..71642a5 100644
--- a/drivers/media/dvb/dvb-core/dmxdev.c
+++ b/drivers/media/dvb/dvb-core/dmxdev.c
@@ -32,6 +32,8 @@
#include <linux/wait.h>
#include <linux/mm.h>
#include <asm/uaccess.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
#include "dmxdev.h"
static int debug;
@@ -617,7 +619,8 @@
dmxdev->dvr_input_buffer.data = NULL;
spin_unlock_irq(&dmxdev->dvr_in_lock);
- if (dmxdev->dvr_buffer_mode == DMX_BUFFER_MODE_INTERNAL)
+ if (dmxdev->dvr_input_buffer_mode ==
+ DMX_BUFFER_MODE_INTERNAL)
vfree(mem);
}
@@ -963,6 +966,12 @@
static int dvb_dvr_set_buffer_mode(struct dmxdev *dmxdev,
unsigned int f_flags, enum dmx_buffer_mode mode)
{
+ struct dvb_ringbuffer *buf;
+ spinlock_t *lock;
+ enum dmx_buffer_mode *buffer_mode;
+ void **buff_handle;
+ void *oldmem;
+
if ((mode != DMX_BUFFER_MODE_INTERNAL) &&
(mode != DMX_BUFFER_MODE_EXTERNAL))
return -EINVAL;
@@ -975,10 +984,42 @@
(!dmxdev->demux->map_buffer || !dmxdev->demux->unmap_buffer))
return -EINVAL;
- if ((f_flags & O_ACCMODE) == O_RDONLY)
- dmxdev->dvr_buffer_mode = mode;
- else
- dmxdev->dvr_input_buffer_mode = mode;
+ if ((f_flags & O_ACCMODE) == O_RDONLY) {
+ buf = &dmxdev->dvr_buffer;
+ lock = &dmxdev->lock;
+ buffer_mode = &dmxdev->dvr_buffer_mode;
+ buff_handle = &dmxdev->dvr_priv_buff_handle;
+ } else {
+ buf = &dmxdev->dvr_input_buffer;
+ lock = &dmxdev->dvr_in_lock;
+ buffer_mode = &dmxdev->dvr_input_buffer_mode;
+ buff_handle = &dmxdev->demux->dvr_input.priv_handle;
+ }
+
+ if (mode == *buffer_mode)
+ return 0;
+
+ oldmem = buf->data;
+ spin_lock_irq(lock);
+ buf->data = NULL;
+ spin_unlock_irq(lock);
+
+ *buffer_mode = mode;
+
+ if (mode == DMX_BUFFER_MODE_INTERNAL) {
+ /* switched from external to internal */
+ if (*buff_handle) {
+ dmxdev->demux->unmap_buffer(dmxdev->demux,
+ *buff_handle);
+ *buff_handle = NULL;
+ }
+
+ /* set default internal buffer */
+ dvb_dvr_set_buffer_size(dmxdev, f_flags, DVR_BUFFER_SIZE);
+ } else if (oldmem) {
+ /* switched from internal to external */
+ vfree(oldmem);
+ }
return 0;
}
@@ -3125,6 +3166,73 @@
.fops = &dvb_dvr_fops
};
+
+/**
+ * debugfs service to print active filters information.
+ */
+static int dvb_dmxdev_dbgfs_print(struct seq_file *s, void *p)
+{
+ int i;
+ struct dmxdev *dmxdev = s->private;
+ struct dmxdev_filter *filter;
+ int active_count = 0;
+ struct dmx_buffer_status buffer_status;
+ const char *pes_feeds[] = {"DEC", "PES", "DVR", "REC"};
+
+ if (!dmxdev)
+ return 0;
+
+ for (i = 0; i < dmxdev->filternum; i++) {
+ filter = &dmxdev->filter[i];
+ if (filter->state >= DMXDEV_STATE_GO) {
+ active_count++;
+
+ seq_printf(s, "filter_%02d - ", i);
+
+ if (filter->type == DMXDEV_TYPE_SEC) {
+ seq_printf(s, "type: SEC, ");
+ seq_printf(s, "PID %04d ",
+ filter->params.sec.pid);
+ } else {
+ seq_printf(s, "type: %s, ",
+ pes_feeds[filter->params.pes.output]);
+ seq_printf(s, "PID: %04d ",
+ filter->params.pes.pid);
+ }
+
+ if (0 == dvb_dmxdev_get_buffer_status(
+ filter, &buffer_status)) {
+ seq_printf(s, "buffer size: %08d, ",
+ buffer_status.size);
+ seq_printf(s, "buffer fullness: %08d\n",
+ buffer_status.fullness);
+ seq_printf(s, "buffer error: %08d\n",
+ buffer_status.error);
+ }
+ }
+ }
+
+ if (!active_count)
+ seq_printf(s, "No active filters\n");
+
+ seq_printf(s, "\n");
+
+ return 0;
+}
+
+static int dvb_dmxdev_dbgfs_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, dvb_dmxdev_dbgfs_print, inode->i_private);
+}
+
+static const struct file_operations dbgfs_filters_fops = {
+ .open = dvb_dmxdev_dbgfs_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .owner = THIS_MODULE,
+};
+
int dvb_dmxdev_init(struct dmxdev *dmxdev, struct dvb_adapter *dvb_adapter)
{
int i;
@@ -3167,6 +3275,11 @@
INIT_WORK(&dmxdev->dvr_input_work,
dvr_input_work_func);
+ if (dmxdev->demux->debugfs_demux_dir)
+ debugfs_create_file("filters", S_IRUGO,
+ dmxdev->demux->debugfs_demux_dir, dmxdev,
+ &dbgfs_filters_fops);
+
return 0;
}
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c
index de7b28d..2c5294f 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.c
+++ b/drivers/media/dvb/dvb-core/dvb_demux.c
@@ -1732,19 +1732,20 @@
"demux%d",
dvb_demux_index++);
- dvbdemux->debugfs_demux_dir = debugfs_create_dir(dvbdemux->alias, NULL);
+ dvbdemux->dmx.debugfs_demux_dir =
+ debugfs_create_dir(dvbdemux->alias, NULL);
- if (dvbdemux->debugfs_demux_dir != NULL) {
+ if (dvbdemux->dmx.debugfs_demux_dir != NULL) {
debugfs_create_u32(
"total_processing_time",
S_IRUGO|S_IWUGO,
- dvbdemux->debugfs_demux_dir,
+ dvbdemux->dmx.debugfs_demux_dir,
&dvbdemux->total_process_time);
debugfs_create_u32(
"total_crc_time",
S_IRUGO|S_IWUGO,
- dvbdemux->debugfs_demux_dir,
+ dvbdemux->dmx.debugfs_demux_dir,
&dvbdemux->total_crc_time);
}
@@ -1817,9 +1818,10 @@
void dvb_dmx_release(struct dvb_demux *dvbdemux)
{
- if (dvbdemux->debugfs_demux_dir != NULL)
- debugfs_remove_recursive(dvbdemux->debugfs_demux_dir);
+ if (dvbdemux->dmx.debugfs_demux_dir != NULL)
+ debugfs_remove_recursive(dvbdemux->dmx.debugfs_demux_dir);
+ dvb_demux_index--;
vfree(dvbdemux->cnt_storage);
vfree(dvbdemux->filter);
vfree(dvbdemux->feed);
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.h b/drivers/media/dvb/dvb-core/dvb_demux.h
index 5a32363..706cd0c 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.h
+++ b/drivers/media/dvb/dvb-core/dvb_demux.h
@@ -174,7 +174,6 @@
u32 total_process_time;
u32 total_crc_time;
- struct dentry *debugfs_demux_dir;
};
int dvb_dmx_init(struct dvb_demux *dvbdemux);
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
index 18c3767..51d66cd 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
@@ -477,29 +477,29 @@
mpq_demux->hw_notification_size = 0;
mpq_demux->decoder_tsp_drop_count = 0;
- if (mpq_demux->demux.debugfs_demux_dir != NULL) {
+ if (mpq_demux->demux.dmx.debugfs_demux_dir != NULL) {
debugfs_create_u32(
"hw_notification_rate",
S_IRUGO|S_IWUGO,
- mpq_demux->demux.debugfs_demux_dir,
+ mpq_demux->demux.dmx.debugfs_demux_dir,
&mpq_demux->hw_notification_rate);
debugfs_create_u32(
"hw_notification_count",
S_IRUGO|S_IWUGO,
- mpq_demux->demux.debugfs_demux_dir,
+ mpq_demux->demux.dmx.debugfs_demux_dir,
&mpq_demux->hw_notification_count);
debugfs_create_u32(
"hw_notification_size",
S_IRUGO|S_IWUGO,
- mpq_demux->demux.debugfs_demux_dir,
+ mpq_demux->demux.dmx.debugfs_demux_dir,
&mpq_demux->hw_notification_size);
debugfs_create_u32(
"decoder_tsp_drop_count",
S_IRUGO|S_IWUGO,
- mpq_demux->demux.debugfs_demux_dir,
+ mpq_demux->demux.dmx.debugfs_demux_dir,
&mpq_demux->decoder_tsp_drop_count);
}
}
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
index 191a0c4..360d96a 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_tspp_v1.c
@@ -18,15 +18,15 @@
#include "mpq_dmx_plugin_common.h"
-#define TSIF_COUNT 2
+#define TSIF_COUNT 2
#define TSPP_MAX_PID_FILTER_NUM 16
/* Max number of section filters */
-#define TSPP_MAX_SECTION_FILTER_NUM 64
+#define TSPP_MAX_SECTION_FILTER_NUM 64
/* For each TSIF we allocate two pipes, one for PES and one for sections */
-#define TSPP_PES_CHANNEL 0
+#define TSPP_PES_CHANNEL 0
#define TSPP_SECTION_CHANNEL 1
/* the channel_id set to TSPP driver based on TSIF number and channel type */
@@ -35,7 +35,7 @@
#define TSPP_GET_TSIF_NUM(ch_id) (ch_id >> 1)
/* mask that set to care for all bits in pid filter */
-#define TSPP_PID_MASK 0x1FFF
+#define TSPP_PID_MASK 0x1FFF
/* dvb-demux defines pid 0x2000 as full capture pid */
#define TSPP_PASS_THROUGH_PID 0x2000
@@ -47,15 +47,25 @@
#define TSPP_RAW_TTS_SIZE 192
-/* Size of single descriptor. Using max descriptor size (170 packets).
+#define MAX_BAM_DESCRIPTOR_SIZE (32*1024 - 1)
+
+/* Size of single descriptor for PES/rec pipe.
+ * Using max descriptor size (170 packets).
* Assuming 20MBit/sec stream, with 170 packets
* per descriptor there would be about 82 descriptors,
* Meanning about 82 notifications per second.
*/
-#define MAX_BAM_DESCRIPTOR_SIZE (32*1024 - 1)
-#define TSPP_BUFFER_SIZE \
+#define TSPP_PES_BUFFER_SIZE \
((MAX_BAM_DESCRIPTOR_SIZE / TSPP_RAW_TTS_SIZE) * TSPP_RAW_TTS_SIZE)
+/* Size of single descriptor for section pipe.
+ * Assuming 8MBit/sec section rate, with 65 packets
+ * per descriptor there would be about 85 descriptors,
+ * Meanning about 85 notifications per second.
+ */
+#define TSPP_SECTION_BUFFER_SIZE \
+ (65 * TSPP_RAW_TTS_SIZE)
+
/* Number of descriptors, total size: TSPP_BUFFER_SIZE*TSPP_BUFFER_COUNT */
#define TSPP_BUFFER_COUNT (32)
@@ -65,11 +75,18 @@
/* Channel timeout in msec */
#define TSPP_CHANNEL_TIMEOUT 16
+enum mem_buffer_allocation_mode {
+ MPQ_DMX_TSPP_INTERNAL_ALLOC = 0,
+ MPQ_DMX_TSPP_CONTIGUOUS_PHYS_ALLOC = 1
+};
+
/* module parameters for load time configuration */
static int clock_inv;
static int tsif_mode = 2;
+static int allocation_mode = MPQ_DMX_TSPP_INTERNAL_ALLOC;
module_param(tsif_mode, int, S_IRUGO);
module_param(clock_inv, int, S_IRUGO);
+module_param(allocation_mode, int, S_IRUGO);
/*
* Work scheduled each time TSPP notifies dmx
@@ -97,6 +114,15 @@
/* work used to submit to workqueue to process pes channel */
struct tspp_work pes_work;
+ /* ION handle used for TSPP data buffer allocation */
+ struct ion_handle *pes_mem_heap_handle;
+ /* TSPP data buffer heap virtual base address */
+ void *pes_mem_heap_virt_base;
+ /* TSPP data buffer heap physical base address */
+ ion_phys_addr_t pes_mem_heap_phys_base;
+ /* buffer allocation index */
+ int pes_index;
+
/*
* TSPP pipe holding all TS packets with section data.
* The following is reference count for number of feeds
@@ -107,6 +133,15 @@
/* work used to submit to workqueue to process pes channel */
struct tspp_work section_work;
+ /* ION handle used for TSPP data buffer allocation */
+ struct ion_handle *section_mem_heap_handle;
+ /* TSPP data buffer heap virtual base address */
+ void *section_mem_heap_virt_base;
+ /* TSPP data buffer heap physical base address */
+ ion_phys_addr_t section_mem_heap_phys_base;
+ /* buffer allocation index */
+ int section_index;
+
/*
* Holds PIDs of allocated TSPP filters along with
* how many feeds are opened on same PID.
@@ -128,8 +163,65 @@
/* mutex protecting the data-structure */
struct mutex mutex;
} tsif[TSIF_COUNT];
+
+ /* ION client used for TSPP data buffer allocation */
+ struct ion_client *ion_client;
} mpq_dmx_tspp_info;
+static void *tspp_mem_allocator(int channel_id, u32 size,
+ u32 *phys_base, void *user)
+{
+ void *virt_addr = NULL;
+ int i = TSPP_GET_TSIF_NUM(channel_id);
+
+ if (TSPP_IS_PES_CHANNEL(channel_id)) {
+ if (mpq_dmx_tspp_info.tsif[i].pes_index == TSPP_BUFFER_COUNT)
+ return NULL;
+ virt_addr =
+ (mpq_dmx_tspp_info.tsif[i].pes_mem_heap_virt_base +
+ (mpq_dmx_tspp_info.tsif[i].pes_index * size));
+ *phys_base =
+ (mpq_dmx_tspp_info.tsif[i].pes_mem_heap_phys_base +
+ (mpq_dmx_tspp_info.tsif[i].pes_index * size));
+ mpq_dmx_tspp_info.tsif[i].pes_index++;
+ } else {
+ if (mpq_dmx_tspp_info.tsif[i].section_index ==
+ TSPP_BUFFER_COUNT)
+ return NULL;
+ virt_addr =
+ (mpq_dmx_tspp_info.tsif[i].section_mem_heap_virt_base +
+ (mpq_dmx_tspp_info.tsif[i].section_index * size));
+ *phys_base =
+ (mpq_dmx_tspp_info.tsif[i].section_mem_heap_phys_base +
+ (mpq_dmx_tspp_info.tsif[i].section_index * size));
+ mpq_dmx_tspp_info.tsif[i].section_index++;
+ }
+
+ return virt_addr;
+}
+
+static void tspp_mem_free(int channel_id, u32 size,
+ void *virt_base, u32 phys_base, void *user)
+{
+ int i = TSPP_GET_TSIF_NUM(channel_id);
+
+ /*
+ * actual buffer heap free is done in mpq_dmx_tspp_plugin_exit().
+ * we update index here, so if this function is called repetitively
+ * for all the buffers, then afterwards tspp_mem_allocator()
+ * can be called again.
+ * Note: it would be incorrect to call tspp_mem_allocator()
+ * a few times, then call tspp_mem_free(), then call
+ * tspp_mem_allocator() again.
+ */
+ if (TSPP_IS_PES_CHANNEL(channel_id)) {
+ if (mpq_dmx_tspp_info.tsif[i].pes_index > 0)
+ mpq_dmx_tspp_info.tsif[i].pes_index--;
+ } else {
+ if (mpq_dmx_tspp_info.tsif[i].section_index > 0)
+ mpq_dmx_tspp_info.tsif[i].section_index--;
+ }
+}
/**
* Returns a free filter slot that can be used.
@@ -278,6 +370,7 @@
int ret;
int channel_id;
int *channel_ref_count;
+ u32 buffer_size;
tspp_source.clk_inverse = clock_inv;
tspp_source.data_inverse = 0;
@@ -334,10 +427,12 @@
channel_id = TSPP_CHANNEL_ID(tsif, TSPP_PES_CHANNEL);
channel_ref_count =
&mpq_dmx_tspp_info.tsif[tsif].pes_channel_ref;
+ buffer_size = TSPP_PES_BUFFER_SIZE;
} else {
channel_id = TSPP_CHANNEL_ID(tsif, TSPP_SECTION_CHANNEL);
channel_ref_count =
&mpq_dmx_tspp_info.tsif[tsif].section_channel_ref;
+ buffer_size = TSPP_SECTION_BUFFER_SIZE;
}
/* check if required TSPP pipe is already allocated or not */
@@ -374,20 +469,34 @@
(void *)tsif,
TSPP_CHANNEL_TIMEOUT);
- /* TODO: register allocater and provide allocation function
- * that allocate from continous memory so that we can have
+ /* register allocater and provide allocation function
+ * that allocates from continous memory so that we can have
* big notification size, smallest descriptor, and still provide
* TZ with single big buffer based on notification size.
*/
- /* set buffer/descriptor size and count */
- ret = tspp_allocate_buffers(0,
- channel_id,
- TSPP_BUFFER_COUNT,
- TSPP_BUFFER_SIZE,
- TSPP_NOTIFICATION_SIZE,
- NULL,
- NULL);
+ /* set buffer/descriptor size and count,
+ * allocate TSPP data buffers
+ */
+ if (allocation_mode == MPQ_DMX_TSPP_CONTIGUOUS_PHYS_ALLOC) {
+ ret = tspp_allocate_buffers(0,
+ channel_id,
+ TSPP_BUFFER_COUNT,
+ buffer_size,
+ TSPP_NOTIFICATION_SIZE,
+ tspp_mem_allocator,
+ tspp_mem_free,
+ NULL);
+ } else {
+ ret = tspp_allocate_buffers(0,
+ channel_id,
+ TSPP_BUFFER_COUNT,
+ buffer_size,
+ TSPP_NOTIFICATION_SIZE,
+ NULL,
+ NULL,
+ NULL);
+ }
if (ret < 0) {
MPQ_DVB_ERR_PRINT(
"%s: tspp_allocate_buffers(%d) failed (%d)\n",
@@ -745,20 +854,154 @@
return 0;
}
+static void mpq_dmx_tsif_ion_cleanup(int i)
+{
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_phys_base = 0;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_phys_base = 0;
+
+ if (!IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle)) {
+ if (!IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ pes_mem_heap_virt_base))
+ ion_unmap_kernel(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle);
+
+ ion_free(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle);
+ }
+
+ if (!IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_handle)) {
+ if (!IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_virt_base))
+ ion_unmap_kernel(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_handle);
+
+ ion_free(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_handle);
+ }
+
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_virt_base = NULL;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_virt_base = NULL;
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle = NULL;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_handle = NULL;
+}
+
+static void mpq_dmx_tspp_ion_cleanup(void)
+{
+ int i;
+
+ for (i = 0; i < TSIF_COUNT; i++)
+ mpq_dmx_tsif_ion_cleanup(i);
+}
+
static int mpq_tspp_dmx_init(
struct dvb_adapter *mpq_adapter,
struct mpq_demux *mpq_demux)
{
- int result;
+ int i, result;
+ size_t len;
MPQ_DVB_DBG_PRINT("%s executed\n", __func__);
+ if (allocation_mode == MPQ_DMX_TSPP_CONTIGUOUS_PHYS_ALLOC) {
+ /*
+ * Save ION client, used to allocate memory
+ * for TSPP's buffers.
+ */
+ mpq_dmx_tspp_info.ion_client = mpq_demux->ion_client;
+
+ if (IS_ERR_OR_NULL(mpq_dmx_tspp_info.ion_client))
+ return -EINVAL;
+
+ for (i = 0; i < TSIF_COUNT; i++) {
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle =
+ ion_alloc(mpq_dmx_tspp_info.ion_client,
+ (TSPP_BUFFER_COUNT *
+ TSPP_PES_BUFFER_SIZE),
+ TSPP_RAW_TTS_SIZE,
+ ION_HEAP(ION_CP_MM_HEAP_ID),
+ 0); /* non-cached */
+ if (IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ pes_mem_heap_handle)) {
+ MPQ_DVB_ERR_PRINT("%s: ion_alloc() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+ /* save virtual base address of heap */
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_virt_base =
+ ion_map_kernel(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].
+ pes_mem_heap_handle);
+ if (IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ pes_mem_heap_virt_base)) {
+ MPQ_DVB_ERR_PRINT(
+ "%s: ion_map_kernel() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+ /* save physical base address of heap */
+ result = ion_phys(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle,
+ &(mpq_dmx_tspp_info.tsif[i].
+ pes_mem_heap_phys_base), &len);
+ if (result < 0) {
+ MPQ_DVB_ERR_PRINT("%s: ion_phys() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_handle =
+ ion_alloc(mpq_dmx_tspp_info.ion_client,
+ (TSPP_BUFFER_COUNT *
+ TSPP_SECTION_BUFFER_SIZE),
+ TSPP_RAW_TTS_SIZE,
+ ION_HEAP(ION_CP_MM_HEAP_ID),
+ 0); /* non-cached */
+ if (IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_handle)) {
+ MPQ_DVB_ERR_PRINT("%s: ion_alloc() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+ /* save virtual base address of heap */
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_virt_base =
+ ion_map_kernel(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_handle);
+ if (IS_ERR_OR_NULL(mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_virt_base)) {
+ MPQ_DVB_ERR_PRINT(
+ "%s: ion_map_kernel() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+ /* save physical base address of heap */
+ result = ion_phys(mpq_dmx_tspp_info.ion_client,
+ mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_handle,
+ &(mpq_dmx_tspp_info.tsif[i].
+ section_mem_heap_phys_base), &len);
+ if (result < 0) {
+ MPQ_DVB_ERR_PRINT("%s: ion_phys() failed\n",
+ __func__);
+ mpq_dmx_tspp_ion_cleanup();
+ return -ENOMEM;
+ }
+ }
+ }
+
/* Set the kernel-demux object capabilities */
mpq_demux->demux.dmx.capabilities =
DMX_TS_FILTERING |
DMX_PES_FILTERING |
- DMX_SECTION_FILTERING |
- DMX_MEMORY_BASED_FILTERING |
+ DMX_SECTION_FILTERING |
+ DMX_MEMORY_BASED_FILTERING |
DMX_CRC_CHECKING |
DMX_TS_DESCRAMBLING;
@@ -818,6 +1061,7 @@
init_failed_dmx_release:
dvb_dmx_release(&mpq_demux->demux);
init_failed:
+ mpq_dmx_tspp_ion_cleanup();
return result;
}
@@ -831,6 +1075,10 @@
for (i = 0; i < TSIF_COUNT; i++) {
mpq_dmx_tspp_info.tsif[i].pes_channel_ref = 0;
+ mpq_dmx_tspp_info.tsif[i].pes_index = 0;
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_handle = NULL;
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_virt_base = NULL;
+ mpq_dmx_tspp_info.tsif[i].pes_mem_heap_phys_base = 0;
mpq_dmx_tspp_info.tsif[i].pes_work.channel_id =
TSPP_CHANNEL_ID(i, TSPP_PES_CHANNEL);
@@ -839,6 +1087,10 @@
mpq_dmx_tspp_work);
mpq_dmx_tspp_info.tsif[i].section_channel_ref = 0;
+ mpq_dmx_tspp_info.tsif[i].section_index = 0;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_handle = NULL;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_virt_base = NULL;
+ mpq_dmx_tspp_info.tsif[i].section_mem_heap_phys_base = 0;
mpq_dmx_tspp_info.tsif[i].section_work.channel_id =
TSPP_CHANNEL_ID(i, TSPP_SECTION_CHANNEL);
@@ -861,14 +1113,12 @@
mpq_dmx_tspp_info.tsif[i].name);
if (mpq_dmx_tspp_info.tsif[i].workqueue == NULL) {
-
for (j = 0; j < i; j++) {
destroy_workqueue(
mpq_dmx_tspp_info.tsif[j].workqueue);
mutex_destroy(&mpq_dmx_tspp_info.tsif[j].mutex);
}
-
MPQ_DVB_ERR_PRINT(
"%s: create_singlethread_workqueue failed\n",
__func__);
@@ -905,6 +1155,11 @@
for (i = 0; i < TSIF_COUNT; i++) {
mutex_lock(&mpq_dmx_tspp_info.tsif[i].mutex);
+ /*
+ * Note: tspp_close_channel will also free the TSPP buffers
+ * even if we allocated them ourselves,
+ * using our free function.
+ */
if (mpq_dmx_tspp_info.tsif[i].pes_channel_ref) {
tspp_unregister_notification(0, TSPP_PES_CHANNEL);
tspp_close_channel(0,
@@ -917,9 +1172,11 @@
TSPP_CHANNEL_ID(i, TSPP_SECTION_CHANNEL));
}
- /* TODO: if we allocate buffer
- * to TSPP ourself, need to free those as well
+ /* if we allocated buffer pools
+ * to TSPP, need to free those as well
*/
+ if (allocation_mode == MPQ_DMX_TSPP_CONTIGUOUS_PHYS_ALLOC)
+ mpq_dmx_tsif_ion_cleanup(i);
mutex_unlock(&mpq_dmx_tspp_info.tsif[i].mutex);
flush_workqueue(mpq_dmx_tspp_info.tsif[i].workqueue);
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index ac143b1..fde7cb7 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -39,6 +39,17 @@
#include <asm/unaligned.h>
static unsigned int rds_buf = 100;
+static int oda_agt;
+static int grp_mask;
+static int rt_plus_carrier = -1;
+static int ert_carrier = -1;
+static unsigned char ert_buf[256];
+static unsigned char ert_len;
+static unsigned char c_byt_pair_index;
+static char utf_8_flag;
+static char rt_ert_flag;
+static char formatting_dir;
+
module_param(rds_buf, uint, 0);
MODULE_PARM_DESC(rds_buf, "RDS buffer entries: *100*");
@@ -108,7 +119,11 @@
static struct video_device *priv_videodev;
static int iris_do_calibration(struct iris_device *radio);
-
+static void hci_buff_ert(struct iris_device *radio,
+ struct rds_grp_data *rds_buf);
+static void hci_ev_rt_plus(struct iris_device *radio,
+ struct rds_grp_data rds_buf);
+static void hci_ev_ert(struct iris_device *radio);
static int update_spur_table(struct iris_device *radio);
static struct v4l2_queryctrl iris_v4l2_queryctrl[] = {
{
@@ -921,6 +936,20 @@
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
+static int hci_fm_rds_grp_mask_req(struct radio_hci_dev *hdev,
+ unsigned long param)
+{
+ __u16 opcode = 0;
+
+ struct hci_fm_rds_grp_req *fm_grp_mask =
+ (struct hci_fm_rds_grp_req *)param;
+
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ HCI_OCF_FM_RDS_GRP);
+ return radio_hci_send_cmd(hdev, opcode, sizeof(*fm_grp_mask),
+ fm_grp_mask);
+}
+
static int hci_fm_rds_grp_process_req(struct radio_hci_dev *hdev,
unsigned long param)
{
@@ -1313,7 +1342,13 @@
static int hci_fm_rds_grp(struct hci_fm_rds_grp_req *arg,
struct radio_hci_dev *hdev)
{
- return 0;
+ int ret = 0;
+ struct hci_fm_rds_grp_req *fm_grp_mask = arg;
+
+ ret = radio_hci_request(hdev, hci_fm_rds_grp_mask_req, (unsigned
+ long)fm_grp_mask, RADIO_HCI_TIMEOUT);
+
+ return ret;
}
static int hci_fm_rds_grps_process(__u32 *arg, struct radio_hci_dev *hdev)
@@ -2078,6 +2113,234 @@
iris_q_event(radio, IRIS_EVT_MONO);
}
+static void hci_ev_raw_rds_group_data(struct radio_hci_dev *hdev,
+ struct sk_buff *skb)
+{
+ struct iris_device *radio;
+ unsigned char blocknum, index;
+ struct rds_grp_data temp;
+ unsigned int mask_bit;
+ unsigned short int aid, agt, gtc;
+ unsigned short int carrier;
+
+ radio = video_get_drvdata(video_get_dev());
+ index = RDSGRP_DATA_OFFSET;
+
+ for (blocknum = 0; blocknum < RDS_BLOCKS_NUM; blocknum++) {
+ temp.rdsBlk[blocknum].rdsLsb =
+ (skb->data[index]);
+ temp.rdsBlk[blocknum].rdsMsb =
+ (skb->data[index+1]);
+ index = index + 2;
+ }
+
+ aid = AID(temp.rdsBlk[3].rdsLsb, temp.rdsBlk[3].rdsMsb);
+ gtc = GTC(temp.rdsBlk[1].rdsMsb);
+ agt = AGT(temp.rdsBlk[1].rdsLsb);
+
+ if (gtc == GRP_3A) {
+ switch (aid) {
+ case ERT_AID:
+ /* calculate the grp mask for RDS grp
+ * which will contain actual eRT text
+ *
+ * Bit Pos 0 1 2 3 4 5 6 7
+ * Grp Type 0A 0B 1A 1B 2A 2B 3A 3B
+ *
+ * similary for rest grps
+ */
+ mask_bit = (((agt >> 1) << 1) + (agt & 1));
+ oda_agt = (1 << mask_bit);
+ utf_8_flag = (temp.rdsBlk[2].rdsLsb & 1);
+ formatting_dir = EXTRACT_BIT(temp.rdsBlk[2].rdsLsb,
+ ERT_FORMAT_DIR_BIT);
+ if (ert_carrier != agt)
+ iris_q_event(radio, IRIS_EVT_NEW_ODA);
+ ert_carrier = agt;
+ break;
+ case RT_PLUS_AID:
+ /* calculate the grp mask for RDS grp
+ * which will contain actual eRT text
+ *
+ * Bit Pos 0 1 2 3 4 5 6 7
+ * Grp Type 0A 0B 1A 1B 2A 2B 3A 3B
+ *
+ * similary for rest grps
+ */
+ mask_bit = (((agt >> 1) << 1) + (agt & 1));
+ oda_agt = (1 << mask_bit);
+ /*Extract 5th bit of MSB (b7b6b5b4b3b2b1b0)*/
+ rt_ert_flag = EXTRACT_BIT(temp.rdsBlk[2].rdsMsb,
+ RT_ERT_FLAG_BIT);
+ if (rt_plus_carrier != agt)
+ iris_q_event(radio, IRIS_EVT_NEW_ODA);
+ rt_plus_carrier = agt;
+ break;
+ default:
+ oda_agt = 0;
+ break;
+ }
+ } else {
+ carrier = gtc;
+ if ((carrier == rt_plus_carrier))
+ hci_ev_rt_plus(radio, temp);
+ else if (carrier == ert_carrier)
+ hci_buff_ert(radio, &temp);
+ }
+}
+
+static void hci_buff_ert(struct iris_device *radio,
+ struct rds_grp_data *rds_buf)
+{
+ int i;
+ unsigned short int info_byte = 0;
+ unsigned short int byte_pair_index;
+
+ byte_pair_index = AGT(rds_buf->rdsBlk[1].rdsLsb);
+ if (byte_pair_index == 0) {
+ c_byt_pair_index = 0;
+ ert_len = 0;
+ }
+ if (c_byt_pair_index == byte_pair_index) {
+ c_byt_pair_index++;
+ for (i = 2; i <= 3; i++) {
+ info_byte = rds_buf->rdsBlk[i].rdsLsb;
+ info_byte |= (rds_buf->rdsBlk[i].rdsMsb << 8);
+ ert_buf[ert_len++] = rds_buf->rdsBlk[i].rdsMsb;
+ ert_buf[ert_len++] = rds_buf->rdsBlk[i].rdsLsb;
+ if ((utf_8_flag == 0)
+ && (info_byte == CARRIAGE_RETURN)) {
+ ert_len -= 2;
+ break;
+ } else if ((utf_8_flag == 1)
+ &&
+ (rds_buf->rdsBlk[i].rdsMsb
+ == CARRIAGE_RETURN)) {
+ info_byte = CARRIAGE_RETURN;
+ ert_len -= 2;
+ break;
+ } else if ((utf_8_flag == 1)
+ &&
+ (rds_buf->rdsBlk[i].rdsLsb
+ == CARRIAGE_RETURN)) {
+ info_byte = CARRIAGE_RETURN;
+ ert_len--;
+ break;
+ }
+ }
+ if ((byte_pair_index == MAX_ERT_SEGMENT) ||
+ (info_byte == CARRIAGE_RETURN)) {
+ hci_ev_ert(radio);
+ c_byt_pair_index = 0;
+ ert_len = 0;
+ }
+ } else {
+ ert_len = 0;
+ c_byt_pair_index = 0;
+ }
+}
+static void hci_ev_ert(struct iris_device *radio)
+
+{
+ char *data = NULL;
+
+ if (ert_len <= 0)
+ return;
+ data = kmalloc((ert_len + 3), GFP_ATOMIC);
+ if (data != NULL) {
+ data[0] = ert_len;
+ data[1] = utf_8_flag;
+ data[2] = formatting_dir;
+ memcpy((data + 3), ert_buf, ert_len);
+ iris_q_evt_data(radio, data, (ert_len + 3), IRIS_BUF_ERT);
+ iris_q_event(radio, IRIS_EVT_NEW_ERT);
+ kfree(data);
+ }
+}
+
+static void hci_ev_rt_plus(struct iris_device *radio,
+ struct rds_grp_data rds_buf)
+{
+ char tag_type1, tag_type2;
+ char *data = NULL;
+ int len = 0;
+ unsigned short int agt;
+
+ agt = AGT(rds_buf.rdsBlk[1].rdsLsb);
+ /*right most 3 bits of Lsb of block 2
+ * and left most 3 bits of Msb of block 3
+ */
+ tag_type1 = (((agt & TAG1_MSB_MASK) << TAG1_MSB_OFFSET) |
+ (rds_buf.rdsBlk[2].rdsMsb >> TAG1_LSB_OFFSET));
+
+ /*right most 1 bit of lsb of 3rd block
+ * and left most 5 bits of Msb of 4th block
+ */
+ tag_type2 = (((rds_buf.rdsBlk[2].rdsLsb & TAG2_MSB_MASK)
+ << TAG2_MSB_OFFSET) |
+ (rds_buf.rdsBlk[3].rdsMsb >> TAG2_LSB_OFFSET));
+
+ if (tag_type1 != DUMMY_CLASS)
+ len += RT_PLUS_LEN_1_TAG;
+ if (tag_type2 != DUMMY_CLASS)
+ len += RT_PLUS_LEN_1_TAG;
+
+ if (len != 0) {
+ len += 2;
+ data = kmalloc(len, GFP_ATOMIC);
+ } else {
+ FMDERR("Len is zero\n");
+ return ;
+ }
+ if (data != NULL) {
+ data[0] = len;
+ len = 1;
+ data[len++] = rt_ert_flag;
+ if (tag_type1 != DUMMY_CLASS) {
+ data[len++] = tag_type1;
+ /*start position of tag1
+ *right most 5 bits of msb of 3rd block
+ *and left most bit of lsb of 3rd block
+ */
+ data[len++] = (((rds_buf.rdsBlk[2].rdsMsb &
+ TAG1_POS_MSB_MASK)
+ << TAG1_POS_MSB_OFFSET)
+ |
+ (rds_buf.rdsBlk[2].rdsLsb >>
+ TAG1_POS_LSB_OFFSET));
+ /*length of tag1
+ *left most 6 bits of lsb of 3rd block
+ */
+ data[len++] = ((rds_buf.rdsBlk[2].rdsLsb
+ >> TAG1_LEN_OFFSET)
+ &
+ TAG1_LEN_MASK) + 1;
+ }
+ if (tag_type2 != DUMMY_CLASS) {
+ data[len++] = tag_type2;
+ /*start position of tag2
+ *right most 3 bit of msb of 4th block
+ *and left most 3 bits of lsb of 4th block
+ */
+ data[len++] = (((rds_buf.rdsBlk[3].rdsMsb
+ & TAG2_POS_MSB_MASK)
+ << TAG2_POS_MSB_OFFSET)
+ |
+ (rds_buf.rdsBlk[3].rdsLsb
+ >> TAG2_POS_LSB_OFFSET));
+ /*length of tag2
+ *right most 5 bits of lsb of 4th block
+ */
+ data[len++] = (rds_buf.rdsBlk[3].rdsLsb
+ & TAG2_LEN_MASK) + 1;
+ }
+ iris_q_evt_data(radio, data, len, IRIS_BUF_RT_PLUS);
+ iris_q_event(radio, IRIS_EVT_NEW_RT_PLUS);
+ kfree(data);
+ } else {
+ FMDERR("memory allocation failed\n");
+ }
+}
static inline void hci_ev_program_service(struct radio_hci_dev *hdev,
struct sk_buff *skb)
@@ -2217,6 +2480,7 @@
hci_ev_service_available(hdev, skb);
break;
case HCI_EV_RDS_RX_DATA:
+ hci_ev_raw_rds_group_data(hdev, skb);
break;
case HCI_EV_PROGRAM_SERVICE:
hci_ev_program_service(hdev, skb);
@@ -2984,8 +3248,13 @@
}
break;
case V4L2_CID_PRIVATE_IRIS_RDSGROUP_MASK:
- radio->rds_grp.rds_grp_enable_mask = ctrl->value;
+ grp_mask = (grp_mask | oda_agt | ctrl->value);
+ radio->rds_grp.rds_grp_enable_mask = grp_mask;
+ radio->rds_grp.rds_buf_size = 1;
+ radio->rds_grp.en_rds_change_filter = 0;
retval = hci_fm_rds_grp(&radio->rds_grp, radio->fm_hdev);
+ if (retval < 0)
+ FMDERR("error in setting group mask\n");
break;
case V4L2_CID_PRIVATE_IRIS_RDSGROUP_PROC:
rds_grps_proc = radio->g_rds_grp_proc_ps | ctrl->value;
diff --git a/drivers/media/video/msm/Makefile b/drivers/media/video/msm/Makefile
index 5921632..56d3e0c 100644
--- a/drivers/media/video/msm/Makefile
+++ b/drivers/media/video/msm/Makefile
@@ -10,18 +10,19 @@
EXTRA_CFLAGS += -Idrivers/media/video/msm/sensors
EXTRA_CFLAGS += -Idrivers/media/video/msm/actuators
EXTRA_CFLAGS += -Idrivers/media/video/msm/server
+ EXTRA_CFLAGS += -Idrivers/media/video/msm/flash
obj-$(CONFIG_MSM_CAMERA) += msm_isp.o msm.o msm_mem.o msm_mctl.o msm_mctl_buf.o msm_mctl_pp.o
obj-$(CONFIG_MSM_CAMERA) += server/
obj-$(CONFIG_MSM_CAM_IRQ_ROUTER) += msm_camirq_router.o
obj-$(CONFIG_MSM_CAMERA) += cci/ eeprom/ sensors/ actuators/ csi/
obj-$(CONFIG_MSM_CPP) += cpp/
obj-$(CONFIG_MSM_CAMERA) += msm_gesture.o
+ obj-$(CONFIG_MSM_CAMERA) += flash/
else
obj-$(CONFIG_MSM_CAMERA) += msm_camera.o
endif
obj-$(CONFIG_MSM_CAMERA) += vfe/
obj-$(CONFIG_MSM_CAMERA) += msm_axi_qos.o gemini/ mercury/ jpeg_10/
-obj-$(CONFIG_MSM_CAMERA_FLASH) += flash.o
ifeq ($(CONFIG_MSM_CAMERA_V4L2),y)
obj-$(CONFIG_ARCH_MSM8X60) += msm_vpe.o
obj-$(CONFIG_ARCH_MSM7X30) += msm_vpe.o msm_axi_qos.o
diff --git a/drivers/media/video/msm/flash.c b/drivers/media/video/msm/flash.c
deleted file mode 100644
index 54c59f8..0000000
--- a/drivers/media/video/msm/flash.c
+++ /dev/null
@@ -1,763 +0,0 @@
-
-/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/leds-pmic8058.h>
-#include <linux/pwm.h>
-#include <linux/pmic8058-pwm.h>
-#include <linux/hrtimer.h>
-#include <linux/export.h>
-#include <mach/pmic.h>
-#include <mach/camera.h>
-#include <mach/gpio.h>
-#include "msm_camera_i2c.h"
-
-struct i2c_client *sx150x_client;
-struct timer_list timer_flash;
-static struct msm_camera_sensor_info *sensor_data;
-static struct msm_camera_i2c_client i2c_client;
-enum msm_cam_flash_stat{
- MSM_CAM_FLASH_OFF,
- MSM_CAM_FLASH_ON,
-};
-
-static struct i2c_client *sc628a_client;
-
-static const struct i2c_device_id sc628a_i2c_id[] = {
- {"sc628a", 0},
- { }
-};
-
-static int sc628a_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("sc628a_probe called!\n");
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- pr_err("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- sc628a_client = client;
-
- CDBG("sc628a_probe success rc = %d\n", rc);
- return 0;
-
-probe_failure:
- pr_err("sc628a_probe failed! rc = %d\n", rc);
- return rc;
-}
-
-static struct i2c_driver sc628a_i2c_driver = {
- .id_table = sc628a_i2c_id,
- .probe = sc628a_i2c_probe,
- .remove = __exit_p(sc628a_i2c_remove),
- .driver = {
- .name = "sc628a",
- },
-};
-
-static struct i2c_client *tps61310_client;
-
-static const struct i2c_device_id tps61310_i2c_id[] = {
- {"tps61310", 0},
- { }
-};
-
-static int tps61310_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("%s enter\n", __func__);
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- pr_err("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- tps61310_client = client;
- i2c_client.client = tps61310_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x01, 0x00,
- MSM_CAMERA_I2C_BYTE_DATA);
- if (rc < 0) {
- tps61310_client = NULL;
- goto probe_failure;
- }
-
- CDBG("%s success! rc = %d\n", __func__, rc);
- return 0;
-
-probe_failure:
- pr_err("%s failed! rc = %d\n", __func__, rc);
- return rc;
-}
-
-static struct i2c_driver tps61310_i2c_driver = {
- .id_table = tps61310_i2c_id,
- .probe = tps61310_i2c_probe,
- .remove = __exit_p(tps61310_i2c_remove),
- .driver = {
- .name = "tps61310",
- },
-};
-
-static int config_flash_gpio_table(enum msm_cam_flash_stat stat,
- struct msm_camera_sensor_strobe_flash_data *sfdata)
-{
- int rc = 0, i = 0;
- int msm_cam_flash_gpio_tbl[][2] = {
- {sfdata->flash_trigger, 1},
- {sfdata->flash_charge, 1},
- {sfdata->flash_charge_done, 0}
- };
-
- if (stat == MSM_CAM_FLASH_ON) {
- for (i = 0; i < ARRAY_SIZE(msm_cam_flash_gpio_tbl); i++) {
- rc = gpio_request(msm_cam_flash_gpio_tbl[i][0],
- "CAM_FLASH_GPIO");
- if (unlikely(rc < 0)) {
- pr_err("%s not able to get gpio\n", __func__);
- for (i--; i >= 0; i--)
- gpio_free(msm_cam_flash_gpio_tbl[i][0]);
- break;
- }
- if (msm_cam_flash_gpio_tbl[i][1])
- gpio_direction_output(
- msm_cam_flash_gpio_tbl[i][0], 0);
- else
- gpio_direction_input(
- msm_cam_flash_gpio_tbl[i][0]);
- }
- } else {
- for (i = 0; i < ARRAY_SIZE(msm_cam_flash_gpio_tbl); i++) {
- gpio_direction_input(msm_cam_flash_gpio_tbl[i][0]);
- gpio_free(msm_cam_flash_gpio_tbl[i][0]);
- }
- }
- return rc;
-}
-
-int msm_camera_flash_current_driver(
- struct msm_camera_sensor_flash_current_driver *current_driver,
- unsigned led_state)
-{
- int rc = 0;
-#if defined CONFIG_LEDS_PMIC8058
- int idx;
- const struct pmic8058_leds_platform_data *driver_channel =
- current_driver->driver_channel;
- int num_leds = driver_channel->num_leds;
-
- CDBG("%s: led_state = %d\n", __func__, led_state);
-
- /* Evenly distribute current across all channels */
- switch (led_state) {
- case MSM_CAMERA_LED_OFF:
- for (idx = 0; idx < num_leds; ++idx) {
- rc = pm8058_set_led_current(
- driver_channel->leds[idx].id, 0);
- if (rc < 0)
- pr_err(
- "%s: FAIL name = %s, rc = %d\n",
- __func__,
- driver_channel->leds[idx].name,
- rc);
- }
- break;
-
- case MSM_CAMERA_LED_LOW:
- for (idx = 0; idx < num_leds; ++idx) {
- rc = pm8058_set_led_current(
- driver_channel->leds[idx].id,
- current_driver->low_current/num_leds);
- if (rc < 0)
- pr_err(
- "%s: FAIL name = %s, rc = %d\n",
- __func__,
- driver_channel->leds[idx].name,
- rc);
- }
- break;
-
- case MSM_CAMERA_LED_HIGH:
- for (idx = 0; idx < num_leds; ++idx) {
- rc = pm8058_set_led_current(
- driver_channel->leds[idx].id,
- current_driver->high_current/num_leds);
- if (rc < 0)
- pr_err(
- "%s: FAIL name = %s, rc = %d\n",
- __func__,
- driver_channel->leds[idx].name,
- rc);
- }
- break;
- case MSM_CAMERA_LED_INIT:
- case MSM_CAMERA_LED_RELEASE:
- break;
-
- default:
- rc = -EFAULT;
- break;
- }
- CDBG("msm_camera_flash_led_pmic8058: return %d\n", rc);
-#endif /* CONFIG_LEDS_PMIC8058 */
- return rc;
-}
-
-int msm_camera_flash_led(
- struct msm_camera_sensor_flash_external *external,
- unsigned led_state)
-{
- int rc = 0;
-
- CDBG("msm_camera_flash_led: %d\n", led_state);
- switch (led_state) {
- case MSM_CAMERA_LED_INIT:
- rc = gpio_request(external->led_en, "sgm3141");
- CDBG("MSM_CAMERA_LED_INIT: gpio_req: %d %d\n",
- external->led_en, rc);
- if (!rc)
- gpio_direction_output(external->led_en, 0);
- else
- return 0;
-
- rc = gpio_request(external->led_flash_en, "sgm3141");
- CDBG("MSM_CAMERA_LED_INIT: gpio_req: %d %d\n",
- external->led_flash_en, rc);
- if (!rc)
- gpio_direction_output(external->led_flash_en, 0);
-
- break;
-
- case MSM_CAMERA_LED_RELEASE:
- CDBG("MSM_CAMERA_LED_RELEASE\n");
- gpio_set_value_cansleep(external->led_en, 0);
- gpio_free(external->led_en);
- gpio_set_value_cansleep(external->led_flash_en, 0);
- gpio_free(external->led_flash_en);
- break;
-
- case MSM_CAMERA_LED_OFF:
- CDBG("MSM_CAMERA_LED_OFF\n");
- gpio_set_value_cansleep(external->led_en, 0);
- gpio_set_value_cansleep(external->led_flash_en, 0);
- break;
-
- case MSM_CAMERA_LED_LOW:
- CDBG("MSM_CAMERA_LED_LOW\n");
- gpio_set_value_cansleep(external->led_en, 1);
- gpio_set_value_cansleep(external->led_flash_en, 1);
- break;
-
- case MSM_CAMERA_LED_HIGH:
- CDBG("MSM_CAMERA_LED_HIGH\n");
- gpio_set_value_cansleep(external->led_en, 1);
- gpio_set_value_cansleep(external->led_flash_en, 1);
- break;
-
- default:
- rc = -EFAULT;
- break;
- }
-
- return rc;
-}
-
-int msm_camera_flash_external(
- struct msm_camera_sensor_flash_external *external,
- unsigned led_state)
-{
- int rc = 0;
-
- switch (led_state) {
-
- case MSM_CAMERA_LED_INIT:
- if (external->flash_id == MAM_CAMERA_EXT_LED_FLASH_SC628A) {
- if (!sc628a_client) {
- rc = i2c_add_driver(&sc628a_i2c_driver);
- if (rc < 0 || sc628a_client == NULL) {
- pr_err("sc628a_i2c_driver add failed\n");
- rc = -ENOTSUPP;
- return rc;
- }
- }
- } else if (external->flash_id ==
- MAM_CAMERA_EXT_LED_FLASH_TPS61310) {
- if (!tps61310_client) {
- rc = i2c_add_driver(&tps61310_i2c_driver);
- if (rc < 0 || tps61310_client == NULL) {
- pr_err("tps61310_i2c_driver add failed\n");
- rc = -ENOTSUPP;
- return rc;
- }
- }
- } else {
- pr_err("Flash id not supported\n");
- rc = -ENOTSUPP;
- return rc;
- }
-
-#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
- if (external->expander_info && !sx150x_client) {
- struct i2c_adapter *adapter =
- i2c_get_adapter(external->expander_info->bus_id);
- if (adapter)
- sx150x_client = i2c_new_device(adapter,
- external->expander_info->board_info);
- if (!sx150x_client || !adapter) {
- pr_err("sx150x_client is not available\n");
- rc = -ENOTSUPP;
- if (sc628a_client) {
- i2c_del_driver(&sc628a_i2c_driver);
- sc628a_client = NULL;
- }
- if (tps61310_client) {
- i2c_del_driver(&tps61310_i2c_driver);
- tps61310_client = NULL;
- }
- return rc;
- }
- i2c_put_adapter(adapter);
- }
-#endif
- if (sc628a_client)
- rc = gpio_request(external->led_en, "sc628a");
- if (tps61310_client)
- rc = gpio_request(external->led_en, "tps61310");
-
- if (!rc) {
- gpio_direction_output(external->led_en, 0);
- } else {
- goto error;
- }
-
- if (sc628a_client)
- rc = gpio_request(external->led_flash_en, "sc628a");
- if (tps61310_client)
- rc = gpio_request(external->led_flash_en, "tps61310");
-
- if (!rc) {
- gpio_direction_output(external->led_flash_en, 0);
- break;
- }
-
- gpio_set_value_cansleep(external->led_en, 0);
- gpio_free(external->led_en);
-error:
- pr_err("%s gpio request failed\n", __func__);
- if (sc628a_client) {
- i2c_del_driver(&sc628a_i2c_driver);
- sc628a_client = NULL;
- }
- if (tps61310_client) {
- i2c_del_driver(&tps61310_i2c_driver);
- tps61310_client = NULL;
- }
- break;
-
- case MSM_CAMERA_LED_RELEASE:
- if (sc628a_client || tps61310_client) {
- gpio_set_value_cansleep(external->led_en, 0);
- gpio_free(external->led_en);
- gpio_set_value_cansleep(external->led_flash_en, 0);
- gpio_free(external->led_flash_en);
- if (sc628a_client) {
- i2c_del_driver(&sc628a_i2c_driver);
- sc628a_client = NULL;
- }
- if (tps61310_client) {
- i2c_del_driver(&tps61310_i2c_driver);
- tps61310_client = NULL;
- }
- }
-#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
- if (external->expander_info && sx150x_client) {
- i2c_unregister_device(sx150x_client);
- sx150x_client = NULL;
- }
-#endif
- break;
-
- case MSM_CAMERA_LED_OFF:
- if (sc628a_client) {
- i2c_client.client = sc628a_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x02, 0x00,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- if (tps61310_client) {
- i2c_client.client = tps61310_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x01, 0x00,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- gpio_set_value_cansleep(external->led_en, 0);
- gpio_set_value_cansleep(external->led_flash_en, 0);
- break;
-
- case MSM_CAMERA_LED_LOW:
- gpio_set_value_cansleep(external->led_en, 1);
- gpio_set_value_cansleep(external->led_flash_en, 1);
- usleep_range(2000, 3000);
- if (sc628a_client) {
- i2c_client.client = sc628a_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x02, 0x06,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- if (tps61310_client) {
- i2c_client.client = tps61310_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x01, 0x86,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- break;
-
- case MSM_CAMERA_LED_HIGH:
- gpio_set_value_cansleep(external->led_en, 1);
- gpio_set_value_cansleep(external->led_flash_en, 1);
- usleep_range(2000, 3000);
- if (sc628a_client) {
- i2c_client.client = sc628a_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x02, 0x49,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- if (tps61310_client) {
- i2c_client.client = tps61310_client;
- i2c_client.addr_type = MSM_CAMERA_I2C_BYTE_ADDR;
- rc = msm_camera_i2c_write(&i2c_client, 0x01, 0x8B,
- MSM_CAMERA_I2C_BYTE_DATA);
- }
- break;
-
- default:
- rc = -EFAULT;
- break;
- }
- return rc;
-}
-
-static int msm_camera_flash_pwm(
- struct msm_camera_sensor_flash_pwm *pwm,
- unsigned led_state)
-{
- int rc = 0;
- int PWM_PERIOD = USEC_PER_SEC / pwm->freq;
-
- static struct pwm_device *flash_pwm;
-
- if (!flash_pwm) {
- flash_pwm = pwm_request(pwm->channel, "camera-flash");
- if (flash_pwm == NULL || IS_ERR(flash_pwm)) {
- pr_err("%s: FAIL pwm_request(): flash_pwm=%p\n",
- __func__, flash_pwm);
- flash_pwm = NULL;
- return -ENXIO;
- }
- }
-
- switch (led_state) {
- case MSM_CAMERA_LED_LOW:
- rc = pwm_config(flash_pwm,
- (PWM_PERIOD/pwm->max_load)*pwm->low_load,
- PWM_PERIOD);
- if (rc >= 0)
- rc = pwm_enable(flash_pwm);
- break;
-
- case MSM_CAMERA_LED_HIGH:
- rc = pwm_config(flash_pwm,
- (PWM_PERIOD/pwm->max_load)*pwm->high_load,
- PWM_PERIOD);
- if (rc >= 0)
- rc = pwm_enable(flash_pwm);
- break;
-
- case MSM_CAMERA_LED_OFF:
- pwm_disable(flash_pwm);
- break;
- case MSM_CAMERA_LED_INIT:
- case MSM_CAMERA_LED_RELEASE:
- break;
-
- default:
- rc = -EFAULT;
- break;
- }
- return rc;
-}
-
-int msm_camera_flash_pmic(
- struct msm_camera_sensor_flash_pmic *pmic,
- unsigned led_state)
-{
- int rc = 0;
-
- switch (led_state) {
- case MSM_CAMERA_LED_OFF:
- rc = pmic->pmic_set_current(pmic->led_src_1, 0);
- if (pmic->num_of_src > 1)
- rc = pmic->pmic_set_current(pmic->led_src_2, 0);
- break;
-
- case MSM_CAMERA_LED_LOW:
- rc = pmic->pmic_set_current(pmic->led_src_1,
- pmic->low_current);
- if (pmic->num_of_src > 1)
- rc = pmic->pmic_set_current(pmic->led_src_2, 0);
- break;
-
- case MSM_CAMERA_LED_HIGH:
- rc = pmic->pmic_set_current(pmic->led_src_1,
- pmic->high_current);
- if (pmic->num_of_src > 1)
- rc = pmic->pmic_set_current(pmic->led_src_2,
- pmic->high_current);
- break;
-
- case MSM_CAMERA_LED_INIT:
- case MSM_CAMERA_LED_RELEASE:
- break;
-
- default:
- rc = -EFAULT;
- break;
- }
- CDBG("flash_set_led_state: return %d\n", rc);
-
- return rc;
-}
-
-int32_t msm_camera_flash_set_led_state(
- struct msm_camera_sensor_flash_data *fdata, unsigned led_state)
-{
- int32_t rc;
-
- if (fdata->flash_type != MSM_CAMERA_FLASH_LED ||
- fdata->flash_src == NULL)
- return -ENODEV;
-
- switch (fdata->flash_src->flash_sr_type) {
- case MSM_CAMERA_FLASH_SRC_PMIC:
- rc = msm_camera_flash_pmic(&fdata->flash_src->_fsrc.pmic_src,
- led_state);
- break;
-
- case MSM_CAMERA_FLASH_SRC_PWM:
- rc = msm_camera_flash_pwm(&fdata->flash_src->_fsrc.pwm_src,
- led_state);
- break;
-
- case MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER:
- rc = msm_camera_flash_current_driver(
- &fdata->flash_src->_fsrc.current_driver_src,
- led_state);
- break;
-
- case MSM_CAMERA_FLASH_SRC_EXT:
- rc = msm_camera_flash_external(
- &fdata->flash_src->_fsrc.ext_driver_src,
- led_state);
- break;
-
- case MSM_CAMERA_FLASH_SRC_LED1:
- rc = msm_camera_flash_led(
- &fdata->flash_src->_fsrc.ext_driver_src,
- led_state);
- break;
-
- default:
- rc = -ENODEV;
- break;
- }
-
- return rc;
-}
-
-static int msm_strobe_flash_xenon_charge(int32_t flash_charge,
- int32_t charge_enable, uint32_t flash_recharge_duration)
-{
- gpio_set_value_cansleep(flash_charge, charge_enable);
- if (charge_enable) {
- timer_flash.expires = jiffies +
- msecs_to_jiffies(flash_recharge_duration);
- /* add timer for the recharge */
- if (!timer_pending(&timer_flash))
- add_timer(&timer_flash);
- } else
- del_timer_sync(&timer_flash);
- return 0;
-}
-
-static void strobe_flash_xenon_recharge_handler(unsigned long data)
-{
- unsigned long flags;
- struct msm_camera_sensor_strobe_flash_data *sfdata =
- (struct msm_camera_sensor_strobe_flash_data *)data;
-
- spin_lock_irqsave(&sfdata->timer_lock, flags);
- msm_strobe_flash_xenon_charge(sfdata->flash_charge, 1,
- sfdata->flash_recharge_duration);
- spin_unlock_irqrestore(&sfdata->timer_lock, flags);
-
- return;
-}
-
-static irqreturn_t strobe_flash_charge_ready_irq(int irq_num, void *data)
-{
- struct msm_camera_sensor_strobe_flash_data *sfdata =
- (struct msm_camera_sensor_strobe_flash_data *)data;
-
- /* put the charge signal to low */
- gpio_set_value_cansleep(sfdata->flash_charge, 0);
-
- return IRQ_HANDLED;
-}
-
-static int msm_strobe_flash_xenon_init(
- struct msm_camera_sensor_strobe_flash_data *sfdata)
-{
- unsigned long flags;
- int rc = 0;
-
- spin_lock_irqsave(&sfdata->spin_lock, flags);
- if (!sfdata->state) {
-
- rc = config_flash_gpio_table(MSM_CAM_FLASH_ON, sfdata);
- if (rc < 0) {
- pr_err("%s: gpio_request failed\n", __func__);
- goto go_out;
- }
- rc = request_irq(sfdata->irq, strobe_flash_charge_ready_irq,
- IRQF_TRIGGER_RISING, "charge_ready", sfdata);
- if (rc < 0) {
- pr_err("%s: request_irq failed %d\n", __func__, rc);
- goto go_out;
- }
-
- spin_lock_init(&sfdata->timer_lock);
- /* setup timer */
- init_timer(&timer_flash);
- timer_flash.function = strobe_flash_xenon_recharge_handler;
- timer_flash.data = (unsigned long)sfdata;
- }
- sfdata->state++;
-go_out:
- spin_unlock_irqrestore(&sfdata->spin_lock, flags);
-
- return rc;
-}
-
-static int msm_strobe_flash_xenon_release
-(struct msm_camera_sensor_strobe_flash_data *sfdata, int32_t final_release)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&sfdata->spin_lock, flags);
- if (sfdata->state > 0) {
- if (final_release)
- sfdata->state = 0;
- else
- sfdata->state--;
-
- if (!sfdata->state) {
- free_irq(sfdata->irq, sfdata);
- config_flash_gpio_table(MSM_CAM_FLASH_OFF, sfdata);
- if (timer_pending(&timer_flash))
- del_timer_sync(&timer_flash);
- }
- }
- spin_unlock_irqrestore(&sfdata->spin_lock, flags);
- return 0;
-}
-
-static void msm_strobe_flash_xenon_fn_init
- (struct msm_strobe_flash_ctrl *strobe_flash_ptr)
-{
- strobe_flash_ptr->strobe_flash_init =
- msm_strobe_flash_xenon_init;
- strobe_flash_ptr->strobe_flash_charge =
- msm_strobe_flash_xenon_charge;
- strobe_flash_ptr->strobe_flash_release =
- msm_strobe_flash_xenon_release;
-}
-
-int msm_strobe_flash_init(struct msm_sync *sync, uint32_t sftype)
-{
- int rc = 0;
- switch (sftype) {
- case MSM_CAMERA_STROBE_FLASH_XENON:
- if (sync->sdata->strobe_flash_data) {
- msm_strobe_flash_xenon_fn_init(&sync->sfctrl);
- rc = sync->sfctrl.strobe_flash_init(
- sync->sdata->strobe_flash_data);
- } else
- return -ENODEV;
- break;
- default:
- rc = -ENODEV;
- }
- return rc;
-}
-
-int msm_strobe_flash_ctrl(struct msm_camera_sensor_strobe_flash_data *sfdata,
- struct strobe_flash_ctrl_data *strobe_ctrl)
-{
- int rc = 0;
- switch (strobe_ctrl->type) {
- case STROBE_FLASH_CTRL_INIT:
- if (!sfdata)
- return -ENODEV;
- rc = msm_strobe_flash_xenon_init(sfdata);
- break;
- case STROBE_FLASH_CTRL_CHARGE:
- rc = msm_strobe_flash_xenon_charge(sfdata->flash_charge,
- strobe_ctrl->charge_en,
- sfdata->flash_recharge_duration);
- break;
- case STROBE_FLASH_CTRL_RELEASE:
- if (sfdata)
- rc = msm_strobe_flash_xenon_release(sfdata, 0);
- break;
- default:
- pr_err("Invalid Strobe Flash State\n");
- rc = -EINVAL;
- }
- return rc;
-}
-
-int msm_flash_ctrl(struct msm_camera_sensor_info *sdata,
- struct flash_ctrl_data *flash_info)
-{
- int rc = 0;
- sensor_data = sdata;
- switch (flash_info->flashtype) {
- case LED_FLASH:
- rc = msm_camera_flash_set_led_state(sdata->flash_data,
- flash_info->ctrl_data.led_state);
- break;
- case STROBE_FLASH:
- rc = msm_strobe_flash_ctrl(sdata->strobe_flash_data,
- &(flash_info->ctrl_data.strobe_ctrl));
- break;
- default:
- pr_err("Invalid Flash MODE\n");
- rc = -EINVAL;
- }
- return rc;
-}
diff --git a/drivers/media/video/msm/flash/Makefile b/drivers/media/video/msm/flash/Makefile
new file mode 100644
index 0000000..e83f052
--- /dev/null
+++ b/drivers/media/video/msm/flash/Makefile
@@ -0,0 +1,9 @@
+GCC_VERSION := $(shell $(CONFIG_SHELL) $(PWD)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
+ccflags-y += -Idrivers/media/video/msm
+ccflags-y += -Idrivers/media/video/msm/io
+obj-$(CONFIG_MSM_CAMERA_FLASH) += msm_flash.o
+obj-$(CONFIG_MSM_CAMERA_FLASH_SC628A) += sc628a.o
+obj-$(CONFIG_MSM_CAMERA_FLASH_TPS61310) += tps61310.o
+obj-$(CONFIG_MSM_CAMERA_FLASH_PMIC_FLASH) += pmic8058_flash.o
+obj-$(CONFIG_MSM_CAMERA_FLASH_SGM3141) += sgm3141.o
+obj-$(CONFIG_MSM_CAMERA_FLASH_PMIC8058_PWM) += pmic8058_pwm.o
diff --git a/drivers/media/video/msm/flash/msm_flash.c b/drivers/media/video/msm/flash/msm_flash.c
new file mode 100644
index 0000000..6639a4b
--- /dev/null
+++ b/drivers/media/video/msm/flash/msm_flash.c
@@ -0,0 +1,514 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/hrtimer.h>
+#include <linux/export.h>
+#include <linux/of.h>
+#include <mach/pmic.h>
+#include <mach/camera.h>
+#include <mach/gpio.h>
+#include "msm_flash.h"
+#include "msm.h"
+
+static struct timer_list timer_flash;
+
+enum msm_cam_flash_stat {
+ MSM_CAM_FLASH_OFF,
+ MSM_CAM_FLASH_ON,
+};
+
+static int config_flash_gpio_table(enum msm_cam_flash_stat stat,
+ struct msm_camera_sensor_strobe_flash_data *sfdata)
+{
+ int rc = 0, i = 0;
+ int msm_cam_flash_gpio_tbl[][2] = {
+ {sfdata->flash_trigger, 1},
+ {sfdata->flash_charge, 1},
+ {sfdata->flash_charge_done, 0}
+ };
+
+ if (stat == MSM_CAM_FLASH_ON) {
+ for (i = 0; i < ARRAY_SIZE(msm_cam_flash_gpio_tbl); i++) {
+ rc = gpio_request(msm_cam_flash_gpio_tbl[i][0],
+ "CAM_FLASH_GPIO");
+ if (unlikely(rc < 0)) {
+ pr_err("%s not able to get gpio\n", __func__);
+ for (i--; i >= 0; i--)
+ gpio_free(msm_cam_flash_gpio_tbl[i][0]);
+ break;
+ }
+ if (msm_cam_flash_gpio_tbl[i][1])
+ gpio_direction_output(
+ msm_cam_flash_gpio_tbl[i][0], 0);
+ else
+ gpio_direction_input(
+ msm_cam_flash_gpio_tbl[i][0]);
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm_cam_flash_gpio_tbl); i++) {
+ gpio_direction_input(msm_cam_flash_gpio_tbl[i][0]);
+ gpio_free(msm_cam_flash_gpio_tbl[i][0]);
+ }
+ }
+ return rc;
+}
+
+static int msm_strobe_flash_xenon_charge(int32_t flash_charge,
+ int32_t charge_enable, uint32_t flash_recharge_duration)
+{
+ gpio_set_value_cansleep(flash_charge, charge_enable);
+ if (charge_enable) {
+ timer_flash.expires = jiffies +
+ msecs_to_jiffies(flash_recharge_duration);
+ /* add timer for the recharge */
+ if (!timer_pending(&timer_flash))
+ add_timer(&timer_flash);
+ } else
+ del_timer_sync(&timer_flash);
+ return 0;
+}
+
+static void strobe_flash_xenon_recharge_handler(unsigned long data)
+{
+ unsigned long flags;
+ struct msm_camera_sensor_strobe_flash_data *sfdata =
+ (struct msm_camera_sensor_strobe_flash_data *)data;
+
+ spin_lock_irqsave(&sfdata->timer_lock, flags);
+ msm_strobe_flash_xenon_charge(sfdata->flash_charge, 1,
+ sfdata->flash_recharge_duration);
+ spin_unlock_irqrestore(&sfdata->timer_lock, flags);
+
+ return;
+}
+
+static irqreturn_t strobe_flash_charge_ready_irq(int irq_num, void *data)
+{
+ struct msm_camera_sensor_strobe_flash_data *sfdata =
+ (struct msm_camera_sensor_strobe_flash_data *)data;
+
+ /* put the charge signal to low */
+ gpio_set_value_cansleep(sfdata->flash_charge, 0);
+
+ return IRQ_HANDLED;
+}
+
+static int msm_strobe_flash_xenon_init(
+ struct msm_camera_sensor_strobe_flash_data *sfdata)
+{
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&sfdata->spin_lock, flags);
+ if (!sfdata->state) {
+
+ rc = config_flash_gpio_table(MSM_CAM_FLASH_ON, sfdata);
+ if (rc < 0) {
+ pr_err("%s: gpio_request failed\n", __func__);
+ goto go_out;
+ }
+ rc = request_irq(sfdata->irq, strobe_flash_charge_ready_irq,
+ IRQF_TRIGGER_RISING, "charge_ready", sfdata);
+ if (rc < 0) {
+ pr_err("%s: request_irq failed %d\n", __func__, rc);
+ goto go_out;
+ }
+
+ spin_lock_init(&sfdata->timer_lock);
+ /* setup timer */
+ init_timer(&timer_flash);
+ timer_flash.function = strobe_flash_xenon_recharge_handler;
+ timer_flash.data = (unsigned long)sfdata;
+ }
+ sfdata->state++;
+go_out:
+ spin_unlock_irqrestore(&sfdata->spin_lock, flags);
+
+ return rc;
+}
+
+static int msm_strobe_flash_xenon_release
+(struct msm_camera_sensor_strobe_flash_data *sfdata, int32_t final_release)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&sfdata->spin_lock, flags);
+ if (sfdata->state > 0) {
+ if (final_release)
+ sfdata->state = 0;
+ else
+ sfdata->state--;
+
+ if (!sfdata->state) {
+ free_irq(sfdata->irq, sfdata);
+ config_flash_gpio_table(MSM_CAM_FLASH_OFF, sfdata);
+ if (timer_pending(&timer_flash))
+ del_timer_sync(&timer_flash);
+ }
+ }
+ spin_unlock_irqrestore(&sfdata->spin_lock, flags);
+ return 0;
+}
+
+static int msm_strobe_flash_ctrl(
+ struct msm_camera_sensor_strobe_flash_data *sfdata,
+ struct strobe_flash_ctrl_data *strobe_ctrl)
+{
+ int rc = 0;
+ switch (strobe_ctrl->type) {
+ case STROBE_FLASH_CTRL_INIT:
+ if (!sfdata)
+ return -ENODEV;
+ rc = msm_strobe_flash_xenon_init(sfdata);
+ break;
+ case STROBE_FLASH_CTRL_CHARGE:
+ rc = msm_strobe_flash_xenon_charge(sfdata->flash_charge,
+ strobe_ctrl->charge_en,
+ sfdata->flash_recharge_duration);
+ break;
+ case STROBE_FLASH_CTRL_RELEASE:
+ if (sfdata)
+ rc = msm_strobe_flash_xenon_release(sfdata, 0);
+ break;
+ default:
+ pr_err("Invalid Strobe Flash State\n");
+ rc = -EINVAL;
+ }
+ return rc;
+}
+
+int msm_flash_led_init(struct msm_flash_ctrl_t *fctrl)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_external *external = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ external = &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+ if (external->expander_info && !fctrl->expander_client) {
+ struct i2c_adapter *adapter =
+ i2c_get_adapter(external->expander_info->bus_id);
+ if (adapter)
+ fctrl->expander_client = i2c_new_device(adapter,
+ external->expander_info->board_info);
+ if (!fctrl->expander_client || !adapter) {
+ pr_err("fctrl->expander_client is not available\n");
+ rc = -ENOTSUPP;
+ return rc;
+ }
+ i2c_put_adapter(adapter);
+ }
+ rc = msm_camera_init_gpio_table(
+ fctrl->flash_data->flash_src->init_gpio_tbl,
+ fctrl->flash_data->flash_src->init_gpio_tbl_size, 1);
+ if (rc < 0)
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ return rc;
+}
+
+int msm_flash_led_release(struct msm_flash_ctrl_t *fctrl)
+{
+ struct msm_camera_sensor_flash_external *external = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ external = &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+ msm_camera_set_gpio_table(
+ fctrl->flash_data->flash_src->set_gpio_tbl,
+ fctrl->flash_data->flash_src->set_gpio_tbl_size, 0);
+ msm_camera_init_gpio_table(
+ fctrl->flash_data->flash_src->init_gpio_tbl,
+ fctrl->flash_data->flash_src->init_gpio_tbl_size, 0);
+ if (external->expander_info && fctrl->expander_client) {
+ i2c_unregister_device(fctrl->expander_client);
+ fctrl->expander_client = NULL;
+ }
+ return 0;
+}
+
+int msm_flash_led_off(struct msm_flash_ctrl_t *fctrl)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_external *external = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ external = &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+ if (fctrl->flash_i2c_client && fctrl->reg_setting) {
+ rc = msm_camera_i2c_write_tbl(
+ fctrl->flash_i2c_client,
+ fctrl->reg_setting->off_setting,
+ fctrl->reg_setting->off_setting_size,
+ fctrl->reg_setting->default_data_type);
+ if (rc < 0)
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ }
+ msm_camera_set_gpio_table(
+ fctrl->flash_data->flash_src->set_gpio_tbl,
+ fctrl->flash_data->flash_src->set_gpio_tbl_size, 0);
+
+ return rc;
+}
+
+int msm_flash_led_low(struct msm_flash_ctrl_t *fctrl)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_external *external = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ external = &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+ msm_camera_set_gpio_table(
+ fctrl->flash_data->flash_src->set_gpio_tbl,
+ fctrl->flash_data->flash_src->set_gpio_tbl_size, 1);
+ if (fctrl->flash_i2c_client && fctrl->reg_setting) {
+ rc = msm_camera_i2c_write_tbl(
+ fctrl->flash_i2c_client,
+ fctrl->reg_setting->low_setting,
+ fctrl->reg_setting->low_setting_size,
+ fctrl->reg_setting->default_data_type);
+ if (rc < 0)
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ }
+ return rc;
+}
+
+int msm_flash_led_high(struct msm_flash_ctrl_t *fctrl)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_external *external = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ external = &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+ msm_camera_set_gpio_table(
+ fctrl->flash_data->flash_src->set_gpio_tbl,
+ fctrl->flash_data->flash_src->set_gpio_tbl_size, 1);
+ if (fctrl->flash_i2c_client && fctrl->reg_setting) {
+ rc = msm_camera_i2c_write_tbl(
+ fctrl->flash_i2c_client,
+ fctrl->reg_setting->high_setting,
+ fctrl->reg_setting->high_setting_size,
+ fctrl->reg_setting->default_data_type);
+ if (rc < 0)
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ }
+ return rc;
+}
+
+int msm_camera_flash_led_config(struct msm_flash_ctrl_t *fctrl,
+ uint8_t led_state)
+{
+ int rc = 0;
+
+ CDBG("%s:%d called\n", __func__, __LINE__);
+ if (!fctrl->func_tbl) {
+ pr_err("%s flash func tbl NULL\n", __func__);
+ return 0;
+ }
+ switch (led_state) {
+ case MSM_CAMERA_LED_INIT:
+ if (fctrl->func_tbl->flash_led_init)
+ rc = fctrl->func_tbl->flash_led_init(fctrl);
+ break;
+
+ case MSM_CAMERA_LED_RELEASE:
+ if (fctrl->func_tbl->flash_led_release)
+ rc = fctrl->func_tbl->
+ flash_led_release(fctrl);
+ break;
+
+ case MSM_CAMERA_LED_OFF:
+ if (fctrl->func_tbl->flash_led_off)
+ rc = fctrl->func_tbl->flash_led_off(fctrl);
+ break;
+
+ case MSM_CAMERA_LED_LOW:
+ if (fctrl->func_tbl->flash_led_low)
+ rc = fctrl->func_tbl->flash_led_low(fctrl);
+ break;
+
+ case MSM_CAMERA_LED_HIGH:
+ if (fctrl->func_tbl->flash_led_high)
+ rc = fctrl->func_tbl->flash_led_high(fctrl);
+ break;
+
+ default:
+ rc = -EFAULT;
+ break;
+ }
+ return rc;
+}
+
+static struct msm_flash_ctrl_t *get_fctrl(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct msm_flash_ctrl_t, v4l2_sdev);
+}
+
+static long msm_flash_config(struct msm_flash_ctrl_t *fctrl, void __user *argp)
+{
+ long rc = 0;
+ struct flash_ctrl_data flash_info;
+ if (!argp) {
+ pr_err("%s argp NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (copy_from_user(&flash_info, argp, sizeof(flash_info))) {
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ return -EFAULT;
+ }
+ switch (flash_info.flashtype) {
+ case LED_FLASH:
+ if (fctrl->func_tbl->flash_led_config)
+ rc = fctrl->func_tbl->flash_led_config(fctrl,
+ flash_info.ctrl_data.led_state);
+ if (rc < 0)
+ pr_err("%s:%d failed\n", __func__, __LINE__);
+ break;
+ case STROBE_FLASH:
+ rc = msm_strobe_flash_ctrl(fctrl->strobe_flash_data,
+ &(flash_info.ctrl_data.strobe_ctrl));
+ break;
+ default:
+ pr_err("Invalid Flash MODE\n");
+ rc = -EINVAL;
+ }
+ return rc;
+}
+
+static long msm_flash_subdev_ioctl(struct v4l2_subdev *sd,
+ unsigned int cmd, void *arg)
+{
+ struct msm_flash_ctrl_t *fctrl = NULL;
+ void __user *argp = (void __user *)arg;
+ if (!sd) {
+ pr_err("%s:%d sd NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ fctrl = get_fctrl(sd);
+ if (!fctrl) {
+ pr_err("%s:%d fctrl NULL\n", __func__, __LINE__);
+ return -EINVAL;
+ }
+ switch (cmd) {
+ case VIDIOC_MSM_FLASH_LED_DATA_CFG:
+ fctrl->flash_data = (struct msm_camera_sensor_flash_data *)argp;
+ return 0;
+ case VIDIOC_MSM_FLASH_STROBE_DATA_CFG:
+ fctrl->strobe_flash_data =
+ (struct msm_camera_sensor_strobe_flash_data *)argp;
+ return 0;
+ case VIDIOC_MSM_FLASH_CFG:
+ return msm_flash_config(fctrl, argp);
+ default:
+ return -ENOIOCTLCMD;
+ }
+}
+
+static struct v4l2_subdev_core_ops msm_flash_subdev_core_ops = {
+ .ioctl = msm_flash_subdev_ioctl,
+};
+
+static struct v4l2_subdev_ops msm_flash_subdev_ops = {
+ .core = &msm_flash_subdev_core_ops,
+};
+
+int msm_flash_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int rc = 0;
+ struct msm_flash_ctrl_t *fctrl = NULL;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ pr_err("i2c_check_functionality failed\n");
+ goto probe_failure;
+ }
+
+ fctrl = (struct msm_flash_ctrl_t *)(id->driver_data);
+ if (fctrl->flash_i2c_client)
+ fctrl->flash_i2c_client->client = client;
+
+ /* Assign name for sub device */
+ snprintf(fctrl->v4l2_sdev.name, sizeof(fctrl->v4l2_sdev.name),
+ "%s", id->name);
+
+ /* Initialize sub device */
+ v4l2_i2c_subdev_init(&fctrl->v4l2_sdev, client, &msm_flash_subdev_ops);
+
+ CDBG("%s:%d probe success\n", __func__, __LINE__);
+ return 0;
+
+probe_failure:
+ CDBG("%s:%d probe failed\n", __func__, __LINE__);
+ return rc;
+}
+
+int msm_flash_platform_probe(struct platform_device *pdev, void *data)
+{
+ struct msm_flash_ctrl_t *fctrl = (struct msm_flash_ctrl_t *)data;
+ struct msm_cam_subdev_info sd_info;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+
+ if (!fctrl) {
+ pr_err("%s fctrl NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Initialize sub device */
+ v4l2_subdev_init(&fctrl->v4l2_sdev, &msm_flash_subdev_ops);
+
+ /* Assign name for sub device */
+ snprintf(fctrl->v4l2_sdev.name, sizeof(fctrl->v4l2_sdev.name),
+ "%s", "msm_flash");
+
+ fctrl->pdev = pdev;
+ sd_info.sdev_type = FLASH_DEV;
+ sd_info.sd_index = pdev->id;
+ msm_cam_register_subdev_node(&fctrl->v4l2_sdev, &sd_info);
+
+ CDBG("%s:%d probe success\n", __func__, __LINE__);
+ return 0;
+}
+
+int msm_flash_create_v4l2_subdev(void *data, uint8_t sd_index)
+{
+ struct msm_flash_ctrl_t *fctrl = (struct msm_flash_ctrl_t *)data;
+ struct msm_cam_subdev_info sd_info;
+ CDBG("%s:%d called\n", __func__, __LINE__);
+
+ /* Initialize sub device */
+ v4l2_subdev_init(&fctrl->v4l2_sdev, &msm_flash_subdev_ops);
+
+ /* Assign name for sub device */
+ snprintf(fctrl->v4l2_sdev.name, sizeof(fctrl->v4l2_sdev.name),
+ "%s", "msm_flash");
+
+ sd_info.sdev_type = FLASH_DEV;
+ sd_info.sd_index = sd_index;
+ msm_cam_register_subdev_node(&fctrl->v4l2_sdev, &sd_info);
+
+ CDBG("%s:%d probe success\n", __func__, __LINE__);
+ return 0;
+}
diff --git a/drivers/media/video/msm/flash/msm_flash.h b/drivers/media/video/msm/flash/msm_flash.h
new file mode 100644
index 0000000..a7c8846
--- /dev/null
+++ b/drivers/media/video/msm/flash/msm_flash.h
@@ -0,0 +1,91 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef MSM_FLASH_H
+#define MSM_FLASH_H
+
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <media/v4l2-subdev.h>
+#include <mach/board.h>
+#include "msm_camera_i2c.h"
+
+#define MAX_LED_TRIGGERS 2
+
+struct msm_flash_ctrl_t;
+
+struct msm_flash_reg_t {
+ enum msm_camera_i2c_data_type default_data_type;
+ struct msm_camera_i2c_reg_conf *init_setting;
+ uint8_t init_setting_size;
+ struct msm_camera_i2c_reg_conf *off_setting;
+ uint8_t off_setting_size;
+ struct msm_camera_i2c_reg_conf *low_setting;
+ uint8_t low_setting_size;
+ struct msm_camera_i2c_reg_conf *high_setting;
+ uint8_t high_setting_size;
+};
+
+struct msm_flash_fn_t {
+ int (*flash_led_config)(struct msm_flash_ctrl_t *, uint8_t);
+ int (*flash_led_init)(struct msm_flash_ctrl_t *);
+ int (*flash_led_release)(struct msm_flash_ctrl_t *);
+ int (*flash_led_off)(struct msm_flash_ctrl_t *);
+ int (*flash_led_low)(struct msm_flash_ctrl_t *);
+ int (*flash_led_high)(struct msm_flash_ctrl_t *);
+};
+
+struct msm_flash_ctrl_t {
+ struct msm_camera_i2c_client *flash_i2c_client;
+ struct platform_device *pdev;
+ struct i2c_client *expander_client;
+ struct v4l2_subdev v4l2_sdev;
+ struct msm_camera_sensor_flash_data *flash_data;
+ struct msm_camera_sensor_strobe_flash_data *strobe_flash_data;
+ struct msm_flash_fn_t *func_tbl;
+ struct msm_flash_reg_t *reg_setting;
+ const char *led_trigger_name[MAX_LED_TRIGGERS];
+ struct led_trigger *led_trigger[MAX_LED_TRIGGERS];
+ uint32_t max_brightness[MAX_LED_TRIGGERS];
+ void *data;
+};
+
+int msm_flash_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id);
+
+int msm_flash_platform_probe(struct platform_device *pdev, void *data);
+
+int msm_flash_create_v4l2_subdev(void *data, uint8_t sd_index);
+
+int msm_camera_flash_led_config(struct msm_flash_ctrl_t *fctrl,
+ uint8_t led_state);
+
+int msm_flash_led_init(struct msm_flash_ctrl_t *fctrl);
+
+int msm_flash_led_release(struct msm_flash_ctrl_t *fctrl);
+
+int msm_flash_led_off(struct msm_flash_ctrl_t *fctrl);
+
+int msm_flash_led_low(struct msm_flash_ctrl_t *fctrl);
+
+int msm_flash_led_high(struct msm_flash_ctrl_t *fctrl);
+
+#define VIDIOC_MSM_FLASH_LED_DATA_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void __user *)
+
+#define VIDIOC_MSM_FLASH_STROBE_DATA_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void __user *)
+
+#define VIDIOC_MSM_FLASH_CFG \
+ _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void __user *)
+
+#endif
diff --git a/drivers/media/video/msm/flash/pmic8058_flash.c b/drivers/media/video/msm/flash/pmic8058_flash.c
new file mode 100644
index 0000000..2017bcb
--- /dev/null
+++ b/drivers/media/video/msm/flash/pmic8058_flash.c
@@ -0,0 +1,79 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/export.h>
+#include "msm_flash.h"
+
+#define SD_INDEX 0
+
+static struct msm_flash_ctrl_t fctrl;
+
+static int msm_camera_pmic_flash(struct msm_flash_ctrl_t *fctrl,
+ uint8_t led_state)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_pmic *pmic =
+ &fctrl->flash_data->flash_src->_fsrc.pmic_src;
+
+ switch (led_state) {
+ case MSM_CAMERA_LED_OFF:
+ rc = pmic->pmic_set_current(pmic->led_src_1, 0);
+ if (pmic->num_of_src > 1)
+ rc = pmic->pmic_set_current(pmic->led_src_2, 0);
+ break;
+
+ case MSM_CAMERA_LED_LOW:
+ rc = pmic->pmic_set_current(pmic->led_src_1,
+ pmic->low_current);
+ if (pmic->num_of_src > 1)
+ rc = pmic->pmic_set_current(pmic->led_src_2, 0);
+ break;
+
+ case MSM_CAMERA_LED_HIGH:
+ rc = pmic->pmic_set_current(pmic->led_src_1,
+ pmic->high_current);
+ if (pmic->num_of_src > 1)
+ rc = pmic->pmic_set_current(pmic->led_src_2,
+ pmic->high_current);
+ break;
+
+ case MSM_CAMERA_LED_INIT:
+ case MSM_CAMERA_LED_RELEASE:
+ break;
+
+ default:
+ rc = -EFAULT;
+ break;
+ }
+ CDBG("flash_set_led_state: return %d\n", rc);
+
+ return rc;
+}
+
+static int __init msm_flash_i2c_add_driver(void)
+{
+ CDBG("%s called\n", __func__);
+ return msm_flash_create_v4l2_subdev(&fctrl, SD_INDEX);
+}
+
+static struct msm_flash_fn_t pmic_flash_func_tbl = {
+ .flash_led_config = msm_camera_pmic_flash,
+};
+
+static struct msm_flash_ctrl_t fctrl = {
+ .func_tbl = &pmic_flash_func_tbl,
+};
+
+module_init(msm_flash_i2c_add_driver);
+MODULE_DESCRIPTION("PMIC FLASH");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/flash/pmic8058_pwm.c b/drivers/media/video/msm/flash/pmic8058_pwm.c
new file mode 100644
index 0000000..2215340
--- /dev/null
+++ b/drivers/media/video/msm/flash/pmic8058_pwm.c
@@ -0,0 +1,89 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/export.h>
+#include <linux/pwm.h>
+
+#include "msm_flash.h"
+#define SD_INDEX 0
+
+static struct msm_flash_ctrl_t fctrl;
+
+static int msm_camera_flash_pwm(struct msm_flash_ctrl_t *fctrl,
+ uint8_t led_state)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_pwm *pwm =
+ &fctrl->flash_data->flash_src->_fsrc.pwm_src;
+ int PWM_PERIOD = USEC_PER_SEC / pwm->freq;
+
+ struct pwm_device *flash_pwm = (struct pwm_device *)fctrl->data;
+
+ if (!flash_pwm) {
+ flash_pwm = pwm_request(pwm->channel, "camera-flash");
+ if (flash_pwm == NULL || IS_ERR(flash_pwm)) {
+ pr_err("%s: FAIL pwm_request(): flash_pwm=%p\n",
+ __func__, flash_pwm);
+ flash_pwm = NULL;
+ return -ENXIO;
+ }
+ }
+
+ switch (led_state) {
+ case MSM_CAMERA_LED_LOW:
+ rc = pwm_config(flash_pwm,
+ (PWM_PERIOD/pwm->max_load)*pwm->low_load,
+ PWM_PERIOD);
+ if (rc >= 0)
+ rc = pwm_enable(flash_pwm);
+ break;
+
+ case MSM_CAMERA_LED_HIGH:
+ rc = pwm_config(flash_pwm,
+ (PWM_PERIOD/pwm->max_load)*pwm->high_load,
+ PWM_PERIOD);
+ if (rc >= 0)
+ rc = pwm_enable(flash_pwm);
+ break;
+
+ case MSM_CAMERA_LED_OFF:
+ pwm_disable(flash_pwm);
+ break;
+ case MSM_CAMERA_LED_INIT:
+ case MSM_CAMERA_LED_RELEASE:
+ break;
+
+ default:
+ rc = -EFAULT;
+ break;
+ }
+ return rc;
+}
+
+static int __init msm_flash_i2c_add_driver(void)
+{
+ CDBG("%s called\n", __func__);
+ return msm_flash_create_v4l2_subdev(&fctrl, SD_INDEX);
+}
+
+static struct msm_flash_fn_t pmic8058_pwm_func_tbl = {
+ .flash_led_config = msm_camera_flash_pwm,
+};
+
+static struct msm_flash_ctrl_t fctrl = {
+ .func_tbl = &pmic8058_pwm_func_tbl,
+};
+
+module_init(msm_flash_i2c_add_driver);
+MODULE_DESCRIPTION("PMIC FLASH");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/flash/sc628a.c b/drivers/media/video/msm/flash/sc628a.c
new file mode 100644
index 0000000..58824e1
--- /dev/null
+++ b/drivers/media/video/msm/flash/sc628a.c
@@ -0,0 +1,91 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/export.h>
+#include "msm_flash.h"
+
+#define FLASH_NAME "sc628a"
+
+static struct msm_flash_ctrl_t fctrl;
+static struct i2c_driver sc628a_i2c_driver;
+
+static struct msm_camera_i2c_reg_conf sc628a_off_setting[] = {
+ {0x02, 0x00},
+};
+
+static struct msm_camera_i2c_reg_conf sc628a_low_setting[] = {
+ {0x02, 0x06},
+};
+
+static struct msm_camera_i2c_reg_conf sc628a_high_setting[] = {
+ {0x02, 0x49},
+};
+
+static int __exit msm_flash_i2c_remove(struct i2c_client *client)
+{
+ i2c_del_driver(&sc628a_i2c_driver);
+ return 0;
+}
+
+static const struct i2c_device_id sc628a_i2c_id[] = {
+ {FLASH_NAME, (kernel_ulong_t)&fctrl},
+ { }
+};
+
+static struct i2c_driver sc628a_i2c_driver = {
+ .id_table = sc628a_i2c_id,
+ .probe = msm_flash_i2c_probe,
+ .remove = __exit_p(msm_flash_i2c_remove),
+ .driver = {
+ .name = FLASH_NAME,
+ },
+};
+
+static int __init msm_flash_i2c_add_driver(void)
+{
+ CDBG("%s called\n", __func__);
+ return i2c_add_driver(&sc628a_i2c_driver);
+}
+
+static struct msm_camera_i2c_client sc628a_i2c_client = {
+ .addr_type = MSM_CAMERA_I2C_BYTE_ADDR,
+};
+
+static struct msm_flash_reg_t sc628a_regs = {
+ .default_data_type = MSM_CAMERA_I2C_BYTE_DATA,
+ .off_setting = sc628a_off_setting,
+ .off_setting_size = ARRAY_SIZE(sc628a_off_setting),
+ .low_setting = sc628a_low_setting,
+ .low_setting_size = ARRAY_SIZE(sc628a_low_setting),
+ .high_setting = sc628a_high_setting,
+ .high_setting_size = ARRAY_SIZE(sc628a_high_setting),
+};
+
+static struct msm_flash_fn_t sc628a_func_tbl = {
+ .flash_led_config = msm_camera_flash_led_config,
+ .flash_led_init = msm_flash_led_init,
+ .flash_led_release = msm_flash_led_release,
+ .flash_led_off = msm_flash_led_off,
+ .flash_led_low = msm_flash_led_low,
+ .flash_led_high = msm_flash_led_high,
+};
+
+static struct msm_flash_ctrl_t fctrl = {
+ .flash_i2c_client = &sc628a_i2c_client,
+ .reg_setting = &sc628a_regs,
+ .func_tbl = &sc628a_func_tbl,
+};
+
+subsys_initcall(msm_flash_i2c_add_driver);
+MODULE_DESCRIPTION("SC628A FLASH");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/flash/sgm3141.c b/drivers/media/video/msm/flash/sgm3141.c
new file mode 100644
index 0000000..a8f8ca0
--- /dev/null
+++ b/drivers/media/video/msm/flash/sgm3141.c
@@ -0,0 +1,98 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/export.h>
+#include <mach/gpio.h>
+#include "msm_flash.h"
+
+#define SD_INDEX 0
+
+static struct msm_flash_ctrl_t fctrl;
+
+static int msm_camera_flash_led(struct msm_flash_ctrl_t *fctrl,
+ uint8_t led_state)
+{
+ int rc = 0;
+ struct msm_camera_sensor_flash_external *external =
+ &fctrl->flash_data->flash_src->_fsrc.ext_driver_src;
+
+ CDBG("msm_camera_flash_led: %d\n", led_state);
+ switch (led_state) {
+ case MSM_CAMERA_LED_INIT:
+ rc = gpio_request(external->led_en, "sgm3141");
+ CDBG("MSM_CAMERA_LED_INIT: gpio_req: %d %d\n",
+ external->led_en, rc);
+ if (!rc)
+ gpio_direction_output(external->led_en, 0);
+ else
+ return 0;
+
+ rc = gpio_request(external->led_flash_en, "sgm3141");
+ CDBG("MSM_CAMERA_LED_INIT: gpio_req: %d %d\n",
+ external->led_flash_en, rc);
+ if (!rc)
+ gpio_direction_output(external->led_flash_en, 0);
+
+ break;
+
+ case MSM_CAMERA_LED_RELEASE:
+ CDBG("MSM_CAMERA_LED_RELEASE\n");
+ gpio_set_value_cansleep(external->led_en, 0);
+ gpio_free(external->led_en);
+ gpio_set_value_cansleep(external->led_flash_en, 0);
+ gpio_free(external->led_flash_en);
+ break;
+
+ case MSM_CAMERA_LED_OFF:
+ CDBG("MSM_CAMERA_LED_OFF\n");
+ gpio_set_value_cansleep(external->led_en, 0);
+ gpio_set_value_cansleep(external->led_flash_en, 0);
+ break;
+
+ case MSM_CAMERA_LED_LOW:
+ CDBG("MSM_CAMERA_LED_LOW\n");
+ gpio_set_value_cansleep(external->led_en, 1);
+ gpio_set_value_cansleep(external->led_flash_en, 1);
+ break;
+
+ case MSM_CAMERA_LED_HIGH:
+ CDBG("MSM_CAMERA_LED_HIGH\n");
+ gpio_set_value_cansleep(external->led_en, 1);
+ gpio_set_value_cansleep(external->led_flash_en, 1);
+ break;
+
+ default:
+ rc = -EFAULT;
+ break;
+ }
+
+ return rc;
+}
+
+static int __init msm_flash_i2c_add_driver(void)
+{
+ CDBG("%s called\n", __func__);
+ return msm_flash_create_v4l2_subdev(&fctrl, SD_INDEX);
+}
+
+static struct msm_flash_fn_t sgm3141_func_tbl = {
+ .flash_led_config = msm_camera_flash_led,
+};
+
+static struct msm_flash_ctrl_t fctrl = {
+ .func_tbl = &sgm3141_func_tbl,
+};
+
+module_init(msm_flash_i2c_add_driver);
+MODULE_DESCRIPTION("SGM3141 FLASH");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/flash/tps61310.c b/drivers/media/video/msm/flash/tps61310.c
new file mode 100644
index 0000000..63e6955
--- /dev/null
+++ b/drivers/media/video/msm/flash/tps61310.c
@@ -0,0 +1,97 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/module.h>
+#include <linux/export.h>
+#include "msm_flash.h"
+
+#define FLASH_NAME "tps61310"
+
+static struct msm_flash_ctrl_t fctrl;
+static struct i2c_driver tps61310_i2c_driver;
+
+static struct msm_camera_i2c_reg_conf tps61310_init_setting[] = {
+ {0x01, 0x00},
+};
+
+static struct msm_camera_i2c_reg_conf tps61310_off_setting[] = {
+ {0x01, 0x00},
+};
+
+static struct msm_camera_i2c_reg_conf tps61310_low_setting[] = {
+ {0x01, 0x86},
+};
+
+static struct msm_camera_i2c_reg_conf tps61310_high_setting[] = {
+ {0x01, 0x8B},
+};
+
+static int __exit msm_flash_i2c_remove(struct i2c_client *client)
+{
+ i2c_del_driver(&tps61310_i2c_driver);
+ return 0;
+}
+
+static const struct i2c_device_id tps61310_i2c_id[] = {
+ {FLASH_NAME, (kernel_ulong_t)&fctrl},
+ { }
+};
+
+static struct i2c_driver tps61310_i2c_driver = {
+ .id_table = tps61310_i2c_id,
+ .probe = msm_flash_i2c_probe,
+ .remove = __exit_p(msm_flash_i2c_remove),
+ .driver = {
+ .name = FLASH_NAME,
+ },
+};
+
+static int __init msm_flash_i2c_add_driver(void)
+{
+ CDBG("%s called\n", __func__);
+ return i2c_add_driver(&tps61310_i2c_driver);
+}
+
+static struct msm_camera_i2c_client tps61310_i2c_client = {
+ .addr_type = MSM_CAMERA_I2C_BYTE_ADDR,
+};
+
+static struct msm_flash_reg_t tps61310_regs = {
+ .default_data_type = MSM_CAMERA_I2C_BYTE_DATA,
+ .init_setting = tps61310_init_setting,
+ .init_setting_size = ARRAY_SIZE(tps61310_init_setting),
+ .off_setting = tps61310_off_setting,
+ .off_setting_size = ARRAY_SIZE(tps61310_off_setting),
+ .low_setting = tps61310_low_setting,
+ .low_setting_size = ARRAY_SIZE(tps61310_low_setting),
+ .high_setting = tps61310_high_setting,
+ .high_setting_size = ARRAY_SIZE(tps61310_high_setting),
+};
+
+static struct msm_flash_fn_t tps61310_func_tbl = {
+ .flash_led_config = msm_camera_flash_led_config,
+ .flash_led_init = msm_flash_led_init,
+ .flash_led_release = msm_flash_led_release,
+ .flash_led_off = msm_flash_led_off,
+ .flash_led_low = msm_flash_led_low,
+ .flash_led_high = msm_flash_led_high,
+};
+
+static struct msm_flash_ctrl_t fctrl = {
+ .flash_i2c_client = &tps61310_i2c_client,
+ .reg_setting = &tps61310_regs,
+ .func_tbl = &tps61310_func_tbl,
+};
+
+subsys_initcall(msm_flash_i2c_add_driver);
+MODULE_DESCRIPTION("TPS61310 FLASH");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/io/msm_camera_io_util.c b/drivers/media/video/msm/io/msm_camera_io_util.c
index 613850b..1e0a013 100644
--- a/drivers/media/video/msm/io/msm_camera_io_util.c
+++ b/drivers/media/video/msm/io/msm_camera_io_util.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundataion. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -494,3 +494,42 @@
pr_warning("%s: INVALID CASE\n", __func__);
}
}
+
+int msm_camera_init_gpio_table(struct gpio *gpio_tbl, uint8_t gpio_tbl_size,
+ int gpio_en)
+{
+ int rc = 0;
+
+ if (gpio_en) {
+ rc = gpio_request_array(gpio_tbl, gpio_tbl_size);
+ if (rc < 0) {
+ pr_err("%s:%d failed\n" , __func__, __LINE__);
+ return rc;
+ }
+ } else {
+ gpio_free_array(gpio_tbl, gpio_tbl_size);
+ }
+ return rc;
+}
+
+int msm_camera_set_gpio_table(struct msm_gpio_set_tbl *gpio_tbl,
+ uint8_t gpio_tbl_size, int gpio_en)
+{
+ int rc = 0, i;
+
+ if (gpio_en) {
+ for (i = 0; i < gpio_tbl_size; i++) {
+ gpio_set_value_cansleep(gpio_tbl[i].gpio,
+ gpio_tbl[i].flags);
+ usleep_range(gpio_tbl[i].delay,
+ gpio_tbl[i].delay + 1000);
+ }
+ } else {
+ for (i = gpio_tbl_size - 1; i >= 0; i--) {
+ if (gpio_tbl[i].flags)
+ gpio_set_value_cansleep(gpio_tbl[i].gpio,
+ GPIOF_OUT_INIT_LOW);
+ }
+ }
+ return rc;
+}
diff --git a/drivers/media/video/msm/io/msm_io_8960.c b/drivers/media/video/msm/io/msm_io_8960.c
index 808cc32..1b56578 100644
--- a/drivers/media/video/msm/io/msm_io_8960.c
+++ b/drivers/media/video/msm/io/msm_io_8960.c
@@ -103,6 +103,14 @@
} else
CDBG("%s: Bus Client NOT Registered!!!\n", __func__);
break;
+ case S_ADV_VIDEO:
+ if (bus_perf_client) {
+ rc = msm_bus_scale_client_update_request(
+ bus_perf_client, 7);
+ CDBG("%s: S_ADV_VIDEO rc = %d\n", __func__, rc);
+ } else
+ CDBG("%s: Bus Client NOT Registered!!!\n", __func__);
+ break;
case S_DEFAULT:
break;
default:
diff --git a/drivers/media/video/msm/jpeg_10/msm_jpeg_dev.c b/drivers/media/video/msm/jpeg_10/msm_jpeg_dev.c
index 0662f54..3e6e0d5 100644
--- a/drivers/media/video/msm/jpeg_10/msm_jpeg_dev.c
+++ b/drivers/media/video/msm/jpeg_10/msm_jpeg_dev.c
@@ -265,6 +265,7 @@
static const struct of_device_id msm_jpeg_dt_match[] = {
{.compatible = "qcom,jpeg"},
+ {},
};
MODULE_DEVICE_TABLE(of, msm_jpeg_dt_match);
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 50a9776..ef1edae 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1396,6 +1396,7 @@
}
}
+ i2c_put_adapter(adapter);
return act_sdev;
client_fail:
@@ -1431,6 +1432,7 @@
if (eeprom_sdev == NULL)
goto client_fail;
+ i2c_put_adapter(adapter);
return eeprom_sdev;
client_fail:
pr_err("%s client_fail\n", __func__);
@@ -1444,6 +1446,45 @@
return NULL;
}
+static struct v4l2_subdev *msm_flash_probe(
+ struct msm_camera_sensor_flash_data *flash_info)
+{
+ struct v4l2_subdev *flash_sdev = NULL;
+ struct i2c_adapter *adapter = NULL;
+ void *flash_client = NULL;
+
+ D("%s called\n", __func__);
+
+ if (!flash_info || !flash_info->board_info)
+ goto probe_fail;
+
+ adapter = i2c_get_adapter(flash_info->bus_id);
+ if (!adapter)
+ goto probe_fail;
+
+ flash_client = i2c_new_device(adapter, flash_info->board_info);
+ if (!flash_client)
+ goto device_fail;
+
+ flash_sdev = (struct v4l2_subdev *)i2c_get_clientdata(flash_client);
+ if (flash_sdev == NULL)
+ goto client_fail;
+
+ i2c_put_adapter(adapter);
+ return flash_sdev;
+
+client_fail:
+ pr_err("%s client_fail\n", __func__);
+ i2c_unregister_device(flash_client);
+device_fail:
+ pr_err("%s device_fail\n", __func__);
+ i2c_put_adapter(adapter);
+ adapter = NULL;
+probe_fail:
+ pr_err("%s probe_fail\n", __func__);
+ return NULL;
+}
+
/* register a msm sensor into the msm device, which will probe the
* sensor HW. if the HW exist then create a video device (/dev/videoX/)
* to represent this sensor */
@@ -1471,6 +1512,7 @@
pcam->act_sdev = msm_actuator_probe(sdata->actuator_info);
pcam->eeprom_sdev = msm_eeprom_probe(sdata->eeprom_info);
+ pcam->flash_sdev = msm_flash_probe(sdata->flash_data);
D("%s: pcam =0x%p\n", __func__, pcam);
@@ -1528,6 +1570,15 @@
}
}
+ if (pcam->flash_sdev) {
+ rc = v4l2_device_register_subdev(&pcam->v4l2_dev,
+ pcam->flash_sdev);
+ if (rc < 0) {
+ D("%s flash sub device register failed\n", __func__);
+ goto failure;
+ }
+ }
+
pcam->vnode_id = vnode_count++;
return rc;
diff --git a/drivers/media/video/msm/msm.h b/drivers/media/video/msm/msm.h
index 17303dd..1198f17 100644
--- a/drivers/media/video/msm/msm.h
+++ b/drivers/media/video/msm/msm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -75,6 +75,7 @@
#define MAX_NUM_JPEG_DEV 3
#define MAX_NUM_CPP_DEV 1
#define MAX_NUM_CCI_DEV 1
+#define MAX_NUM_FLASH_DEV 4
/* msm queue management APIs*/
@@ -293,6 +294,7 @@
struct v4l2_subdev *vfe_sdev; /* vfe sub device */
struct v4l2_subdev *eeprom_sdev; /* eeprom sub device */
struct v4l2_subdev *cpp_sdev;/*cpp sub device*/
+ struct v4l2_subdev *flash_sdev;/*flash sub device*/
struct msm_cam_config_dev *config_device;
@@ -398,6 +400,7 @@
struct v4l2_subdev *sensor_sdev; /* sensor sub device */
struct v4l2_subdev *act_sdev; /* actuator sub device */
struct v4l2_subdev *eeprom_sdev; /* actuator sub device */
+ struct v4l2_subdev *flash_sdev; /* flash sub device */
struct msm_camera_sensor_info *sdata;
struct msm_device_queue eventData_q; /*payload for events sent to app*/
@@ -580,6 +583,7 @@
struct v4l2_subdev *cpp_device[MAX_NUM_CPP_DEV];
struct v4l2_subdev *irqr_device;
struct v4l2_subdev *cci_device;
+ struct v4l2_subdev *flash_device[MAX_NUM_FLASH_DEV];
spinlock_t intr_table_lock;
struct irqmgr_intr_lkup_table irq_lkup_table;
@@ -723,6 +727,8 @@
struct msm_cam_subdev_info *sd_info);
int msm_mctl_find_sensor_subdevs(struct msm_cam_media_controller *p_mctl,
uint8_t csiphy_core_index, uint8_t csid_core_index);
+int msm_mctl_find_flash_subdev(struct msm_cam_media_controller *p_mctl,
+ uint8_t index);
int msm_server_open_client(int *p_qidx);
int msm_server_send_ctrl(struct msm_ctrl_cmd *out, int ctrl_id);
int msm_server_close_client(int idx);
diff --git a/drivers/media/video/msm/msm_camera.c b/drivers/media/video/msm/msm_camera.c
index dce3630..c40711d 100644
--- a/drivers/media/video/msm/msm_camera.c
+++ b/drivers/media/video/msm/msm_camera.c
@@ -2855,61 +2855,6 @@
rc = pmsm->sync->sctrl.s_config(argp);
break;
- case MSM_CAM_IOCTL_FLASH_LED_CFG: {
- uint32_t led_state;
- if (copy_from_user(&led_state, argp, sizeof(led_state))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else
- rc = msm_camera_flash_set_led_state(pmsm->sync->
- sdata->flash_data, led_state);
- break;
- }
-
- case MSM_CAM_IOCTL_STROBE_FLASH_CFG: {
- uint32_t flash_type;
- if (copy_from_user(&flash_type, argp, sizeof(flash_type))) {
- pr_err("msm_strobe_flash_init failed");
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else {
- CDBG("msm_strobe_flash_init enter");
- rc = msm_strobe_flash_init(pmsm->sync, flash_type);
- }
- break;
- }
-
- case MSM_CAM_IOCTL_STROBE_FLASH_RELEASE:
- if (pmsm->sync->sdata->strobe_flash_data) {
- rc = pmsm->sync->sfctrl.strobe_flash_release(
- pmsm->sync->sdata->strobe_flash_data, 0);
- }
- break;
-
- case MSM_CAM_IOCTL_STROBE_FLASH_CHARGE: {
- uint32_t charge_en;
- if (copy_from_user(&charge_en, argp, sizeof(charge_en))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else
- rc = pmsm->sync->sfctrl.strobe_flash_charge(
- pmsm->sync->sdata->strobe_flash_data->flash_charge,
- charge_en, pmsm->sync->sdata->strobe_flash_data->
- flash_recharge_duration);
- break;
- }
-
- case MSM_CAM_IOCTL_FLASH_CTRL: {
- struct flash_ctrl_data flash_info;
- if (copy_from_user(&flash_info, argp, sizeof(flash_info))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else
- rc = msm_flash_ctrl(pmsm->sync->sdata, &flash_info);
-
- break;
- }
-
case MSM_CAM_IOCTL_ERROR_CONFIG:
rc = msm_error_config(pmsm->sync, argp);
break;
diff --git a/drivers/media/video/msm/msm_mctl.c b/drivers/media/video/msm/msm_mctl.c
index 36fb849..0210d23 100644
--- a/drivers/media/video/msm/msm_mctl.c
+++ b/drivers/media/video/msm/msm_mctl.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundataion. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -40,6 +40,7 @@
#include "msm_vfe32.h"
#include "msm_camera_eeprom.h"
#include "msm_csi_register.h"
+#include "msm_flash.h"
#ifdef CONFIG_MSM_CAMERA_DEBUG
#define D(fmt, args...) pr_debug("msm_mctl: " fmt, ##args)
@@ -414,14 +415,9 @@
}
case MSM_CAM_IOCTL_FLASH_CTRL: {
- struct flash_ctrl_data flash_info;
- if (copy_from_user(&flash_info, argp, sizeof(flash_info))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else {
- if (msm_sensor_state_check(p_mctl))
- rc = msm_flash_ctrl(p_mctl->sdata, &flash_info);
- }
+ if (p_mctl->flash_sdev && msm_sensor_state_check(p_mctl))
+ rc = v4l2_subdev_call(p_mctl->flash_sdev,
+ core, ioctl, VIDIOC_MSM_FLASH_CFG, argp);
break;
}
case MSM_CAM_IOCTL_PICT_PP:
@@ -520,6 +516,7 @@
struct msm_camera_sensor_info *sinfo =
(struct msm_camera_sensor_info *) s_ctrl->sensordata;
struct msm_camera_device_platform_data *camdev = sinfo->pdata;
+ struct msm_camera_sensor_flash_data *flash_data = sinfo->flash_data;
uint8_t csid_core;
D("%s\n", __func__);
if (!p_mctl) {
@@ -569,6 +566,35 @@
goto msm_csi_version;
}
+ if (!p_mctl->flash_sdev && flash_data) {
+ if ((flash_data->flash_type == MSM_CAMERA_FLASH_LED) &&
+ (flash_data->flash_src_index >= 0))
+ msm_mctl_find_flash_subdev(p_mctl,
+ flash_data->flash_src_index);
+ }
+
+ if (p_mctl->flash_sdev && p_mctl->sdata->flash_data &&
+ p_mctl->sdata->flash_data->flash_type !=
+ MSM_CAMERA_FLASH_NONE) {
+ rc = v4l2_subdev_call(p_mctl->flash_sdev, core, ioctl,
+ VIDIOC_MSM_FLASH_LED_DATA_CFG,
+ p_mctl->sdata->flash_data);
+ if (rc < 0) {
+ pr_err("%s: set flash led failed %d\n",
+ __func__, rc);
+ }
+ }
+
+ if (p_mctl->flash_sdev && p_mctl->sdata->strobe_flash_data) {
+ rc = v4l2_subdev_call(p_mctl->flash_sdev, core, ioctl,
+ VIDIOC_MSM_FLASH_STROBE_DATA_CFG,
+ p_mctl->sdata->strobe_flash_data);
+ if (rc < 0) {
+ pr_err("%s: set strobe flash led failed %d\n",
+ __func__, rc);
+ }
+ }
+
pm_qos_add_request(&p_mctl->pm_qos_req_list,
PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
pm_qos_update_request(&p_mctl->pm_qos_req_list,
@@ -739,6 +765,7 @@
pmctl->vfe_output_mode = 0;
spin_lock_init(&pmctl->pp_info.lock);
+ pmctl->flash_sdev = pcam->flash_sdev;
pmctl->act_sdev = pcam->act_sdev;
pmctl->eeprom_sdev = pcam->eeprom_sdev;
pmctl->sensor_sdev = pcam->sensor_sdev;
diff --git a/drivers/media/video/msm/server/msm_cam_server.c b/drivers/media/video/msm/server/msm_cam_server.c
index b8b1d51..b2a7f71 100644
--- a/drivers/media/video/msm/server/msm_cam_server.c
+++ b/drivers/media/video/msm/server/msm_cam_server.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1645,6 +1645,7 @@
static const struct v4l2_ioctl_ops msm_ioctl_ops_server = {
.vidioc_subscribe_event = msm_server_v4l2_subscribe_event,
+ .vidioc_unsubscribe_event = msm_server_v4l2_unsubscribe_event,
.vidioc_default = msm_ioctl_server,
};
@@ -1853,6 +1854,14 @@
return rc;
}
+int msm_mctl_find_flash_subdev(struct msm_cam_media_controller *p_mctl,
+ uint8_t index)
+{
+ if (index < MAX_NUM_FLASH_DEV)
+ p_mctl->flash_sdev = g_server_dev.flash_device[index];
+ return 0;
+}
+
static irqreturn_t msm_camera_server_parse_irq(int irq_num, void *data)
{
unsigned long flags;
@@ -2327,6 +2336,16 @@
sd_info->irq_num);
}
break;
+
+ case FLASH_DEV:
+ if (index >= MAX_NUM_FLASH_DEV) {
+ pr_err("%s Invalid flash idx %d", __func__, index);
+ err = -EINVAL;
+ break;
+ }
+ g_server_dev.flash_device[index] = sd;
+ break;
+
default:
break;
}
diff --git a/drivers/media/video/msm/server/msm_cam_server.h b/drivers/media/video/msm/server/msm_cam_server.h
index 5e39d25..387c254 100644
--- a/drivers/media/video/msm/server/msm_cam_server.h
+++ b/drivers/media/video/msm/server/msm_cam_server.h
@@ -17,7 +17,7 @@
#include <linux/proc_fs.h>
#include <linux/ioctl.h>
#include <mach/camera.h>
-#include "msm.h"
+#include "../msm.h"
uint32_t msm_cam_server_get_mctl_handle(void);
struct iommu_domain *msm_cam_server_get_domain(void);
diff --git a/drivers/media/video/msm/vfe/msm_vfe32.c b/drivers/media/video/msm/vfe/msm_vfe32.c
index db0db36..a382d53 100644
--- a/drivers/media/video/msm/vfe/msm_vfe32.c
+++ b/drivers/media/video/msm/vfe/msm_vfe32.c
@@ -1464,8 +1464,10 @@
CDBG("VFE opertaion mode = 0x%x, output mode = 0x%x\n",
vfe32_ctrl->share_ctrl->operation_mode,
vfe32_ctrl->share_ctrl->outpath.output_mode);
- msm_camera_io_w_mb(1, vfe32_ctrl->share_ctrl->vfebase +
- VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(1, vfe32_ctrl->share_ctrl->vfebase +
+ VFE_CAMIF_COMMAND);
+ msm_camera_io_w_mb(VFE_AXI_CFG_MASK,
+ vfe32_ctrl->share_ctrl->vfebase + VFE_AXI_CFG);
}
static int vfe32_start_recording(
@@ -5789,7 +5791,7 @@
void axi_start(struct msm_cam_media_controller *pmctl,
struct axi_ctrl_t *axi_ctrl, struct msm_camera_vfe_params_t vfe_params)
{
- int rc = 0;
+ int rc = 0, bus_vector_idx = 0;
uint32_t reg_update = 0;
uint32_t vfe_mode =
(axi_ctrl->share_ctrl->current_mode &
@@ -5811,9 +5813,22 @@
pmctl->sdata->pdata->cam_bus_scale_table, S_CAPTURE);
break;
case AXI_CMD_RECORD:
+ if (cpu_is_msm8930() || cpu_is_msm8930aa() ||
+ cpu_is_msm8930ab()) {
+ if (axi_ctrl->share_ctrl->current_mode &
+ VFE_OUTPUTS_PREVIEW_AND_VIDEO
+ || axi_ctrl->share_ctrl->current_mode &
+ VFE_OUTPUTS_VIDEO_AND_PREVIEW)
+ bus_vector_idx = S_VIDEO;
+ else
+ bus_vector_idx = S_ADV_VIDEO;
+ } else {
+ bus_vector_idx = S_VIDEO;
+ }
if (!axi_ctrl->share_ctrl->dual_enabled)
msm_camio_bus_scale_cfg(
- pmctl->sdata->pdata->cam_bus_scale_table, S_VIDEO);
+ pmctl->sdata->pdata->cam_bus_scale_table,
+ bus_vector_idx);
return;
case AXI_CMD_ZSL:
if (!axi_ctrl->share_ctrl->dual_enabled)
@@ -6046,6 +6061,8 @@
uint32_t vfe_mode =
axi_ctrl->share_ctrl->current_mode & ~(VFE_OUTPUTS_RDI0|
VFE_OUTPUTS_RDI1);
+ int bus_vector_idx = 0;
+
switch (vfe_params.cmd_type) {
case AXI_CMD_PREVIEW:
case AXI_CMD_CAPTURE:
@@ -6059,9 +6076,17 @@
pmctl->sdata->pdata->cam_bus_scale_table, S_PREVIEW);
return;
case AXI_CMD_LIVESHOT:
- if (!axi_ctrl->share_ctrl->dual_enabled)
+ if (!axi_ctrl->share_ctrl->dual_enabled) {
+ bus_vector_idx = S_VIDEO;
+
+ if (cpu_is_msm8930() || cpu_is_msm8930aa() ||
+ cpu_is_msm8930ab())
+ bus_vector_idx = S_ADV_VIDEO;
+
msm_camio_bus_scale_cfg(
- pmctl->sdata->pdata->cam_bus_scale_table, S_VIDEO);
+ pmctl->sdata->pdata->cam_bus_scale_table,
+ bus_vector_idx);
+ }
return;
default:
return;
diff --git a/drivers/media/video/msm/vfe/msm_vfe32.h b/drivers/media/video/msm/vfe/msm_vfe32.h
index f985221..169c34e 100644
--- a/drivers/media/video/msm/vfe/msm_vfe32.h
+++ b/drivers/media/video/msm/vfe/msm_vfe32.h
@@ -913,6 +913,7 @@
#define VFE_DMI_ADDR 0x0000059C
#define VFE_DMI_DATA_HI 0x000005A0
#define VFE_DMI_DATA_LO 0x000005A4
+#define VFE_AXI_CFG 0x00000600
#define VFE_BUS_IO_FORMAT_CFG 0x000006F8
#define VFE_PIXEL_IF_CFG 0x000006FC
#define VFE_RDI0_CFG 0x00000734
@@ -923,6 +924,8 @@
#define VFE33_DMI_DATA_HI 0x000005A0
#define VFE33_DMI_DATA_LO 0x000005A4
+#define VFE_AXI_CFG_MASK 0xFFFFFFFF
+
#define VFE32_OUTPUT_MODE_PT BIT(0)
#define VFE32_OUTPUT_MODE_S BIT(1)
#define VFE32_OUTPUT_MODE_V BIT(2)
diff --git a/drivers/media/video/msm_vidc/msm_smem.c b/drivers/media/video/msm_vidc/msm_smem.c
index 3dd2193..83f33a1 100644
--- a/drivers/media/video/msm_vidc/msm_smem.c
+++ b/drivers/media/video/msm_vidc/msm_smem.c
@@ -24,7 +24,7 @@
static int get_device_address(struct ion_client *clnt,
struct ion_handle *hndl, int domain_num, int partition_num,
unsigned long align, unsigned long *iova,
- unsigned long *buffer_size)
+ unsigned long *buffer_size, int flags)
{
int rc;
if (!iova || !buffer_size || !hndl || !clnt) {
@@ -36,25 +36,39 @@
align = 4096;
dprintk(VIDC_DBG, "domain: %d, partition: %d\n",
domain_num, partition_num);
+ if (flags & SMEM_SECURE) {
+ if (flags & SMEM_INPUT)
+ rc = msm_ion_secure_buffer(clnt, hndl, 0x1, 0);
+ else
+ rc = msm_ion_secure_buffer(clnt, hndl, 0x2, 0);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to secure memory\n");
+ goto mem_secure_failed;
+ }
+ }
rc = ion_map_iommu(clnt, hndl, domain_num, partition_num, align,
0, iova, buffer_size, 0, 0);
if (rc)
dprintk(VIDC_ERR,
"ion_map_iommu failed(%d).domain: %d,partition: %d\n",
rc, domain_num, partition_num);
-
+mem_secure_failed:
return rc;
}
static void put_device_address(struct ion_client *clnt,
- struct ion_handle *hndl, int domain_num, int partition_num)
+ struct ion_handle *hndl, int domain_num, int partition_num, int flags)
{
ion_unmap_iommu(clnt, hndl, domain_num, partition_num);
+ if (flags & SMEM_SECURE) {
+ if (msm_ion_unsecure_buffer(clnt, hndl))
+ dprintk(VIDC_ERR, "Failed to unsecure memory\n");
+ }
}
static int ion_user_to_kernel(struct smem_client *client,
int fd, u32 offset, int domain, int partition,
- struct msm_smem *mem)
+ struct msm_smem *mem, int flags)
{
struct ion_handle *hndl;
unsigned long iova = 0;
@@ -70,8 +84,9 @@
mem->kvaddr = NULL;
mem->domain = domain;
mem->partition_num = partition;
+ mem->flags = flags;
rc = get_device_address(client->clnt, hndl, mem->domain,
- mem->partition_num, 4096, &iova, &buffer_size);
+ mem->partition_num, 4096, &iova, &buffer_size, flags);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n", rc);
goto fail_device_address;
@@ -101,11 +116,16 @@
unsigned long ionflags = 0;
unsigned long heap_mask = 0;
int rc = 0;
- if (flags == SMEM_CACHED)
+ if (flags & SMEM_CACHED)
ionflags = ION_SET_CACHED(ionflags);
else
ionflags = ION_SET_UNCACHED(ionflags);
+ if (flags & SMEM_SECURE) {
+ ionflags |= ION_SECURE;
+ size = (size + 0xfffff) & (~0xfffff);
+ }
+
heap_mask = ION_HEAP(ION_CP_MM_HEAP_ID);
if (align < 4096)
align = 4096;
@@ -124,6 +144,7 @@
mem->smem_priv = hndl;
mem->domain = domain;
mem->partition_num = partition;
+ mem->flags = flags;
if (map_kernel) {
mem->kvaddr = ion_map_kernel(client->clnt, hndl);
if (!mem->kvaddr) {
@@ -136,7 +157,7 @@
mem->kvaddr = NULL;
rc = get_device_address(client->clnt, hndl, mem->domain,
- mem->partition_num, align, &iova, &buffer_size);
+ mem->partition_num, align, &iova, &buffer_size, flags);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n",
rc);
@@ -160,7 +181,8 @@
{
if (mem->device_addr)
put_device_address(client->clnt,
- mem->smem_priv, mem->domain, mem->partition_num);
+ mem->smem_priv, mem->domain,
+ mem->partition_num, mem->flags);
if (mem->kvaddr)
ion_unmap_kernel(client->clnt, mem->smem_priv);
if (mem->smem_priv)
@@ -182,7 +204,7 @@
}
struct msm_smem *msm_smem_user_to_kernel(void *clt, int fd, u32 offset,
- int domain, int partition)
+ int domain, int partition, int flags)
{
struct smem_client *client = clt;
int rc = 0;
@@ -199,7 +221,7 @@
switch (client->mem_type) {
case SMEM_ION:
rc = ion_user_to_kernel(clt, fd, offset,
- domain, partition, mem);
+ domain, partition, mem, flags);
break;
default:
dprintk(VIDC_ERR, "Mem type not supported\n");
diff --git a/drivers/media/video/msm_vidc/msm_smem.h b/drivers/media/video/msm_vidc/msm_smem.h
index c109abd..8241fdd 100644
--- a/drivers/media/video/msm_vidc/msm_smem.h
+++ b/drivers/media/video/msm_vidc/msm_smem.h
@@ -20,9 +20,10 @@
SMEM_ION,
};
-enum smem_cache_prop {
- SMEM_CACHED,
- SMEM_UNCACHED,
+enum smem_prop {
+ SMEM_CACHED = 0x1,
+ SMEM_SECURE = 0x2,
+ SMEM_INPUT = 0x4,
};
struct msm_smem {
@@ -32,6 +33,7 @@
unsigned long device_addr;
int domain;
int partition_num;
+ int flags;
void *smem_priv;
};
@@ -41,6 +43,6 @@
void msm_smem_free(void *clt, struct msm_smem *mem);
void msm_smem_delete_client(void *clt);
struct msm_smem *msm_smem_user_to_kernel(void *clt, int fd, u32 offset, int
- domain, int partition);
+ domain, int partition, int flags);
int msm_smem_clean_invalidate(void *clt, struct msm_smem *mem);
#endif
diff --git a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
index 80fdac5..4f2373e 100644
--- a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
@@ -29,7 +29,6 @@
#include "msm_vidc_debug.h"
#include "vidc_hal_api.h"
#include "msm_smem.h"
-#include "msm_vidc_ssr.h"
#define BASE_DEVICE_NUMBER 32
#define SHARED_QSIZE 0x1000000
@@ -757,6 +756,8 @@
struct msm_v4l2_vid_inst *v4l2_inst;
int plane = 0;
int i, rc = 0;
+ int smem_flags = 0;
+ int domain;
vidc_inst = get_vidc_inst(file, fh);
v4l2_inst = get_v4l2_inst(file, fh);
if (!v4l2_inst->mem_client) {
@@ -777,6 +778,7 @@
goto exit;
}
for (i = 0; i < b->length; ++i) {
+ smem_flags = 0;
if (EXTRADATA_IDX(b->length) &&
(i == EXTRADATA_IDX(b->length)) &&
!b->m.planes[i].length) {
@@ -793,8 +795,22 @@
kfree(binfo);
goto exit;
}
+ if ((vidc_inst->mode == VIDC_SECURE)
+ && (!EXTRADATA_IDX(b->length)
+ || (i != EXTRADATA_IDX(b->length)))) {
+ smem_flags |= SMEM_SECURE;
+ domain =
+ vidc_inst->core->resources.io_map[CP_MAP].domain;
+ } else
+ domain =
+ vidc_inst->core->resources.io_map[NS_MAP].domain;
+
+ if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+ smem_flags |= SMEM_INPUT;
+
temp = get_same_fd_buffer(&v4l2_inst->registered_bufs,
b->m.planes[i].reserved[0], &plane);
+
if (temp) {
binfo->type = b->type;
binfo->fd[i] = b->m.planes[i].reserved[0];
@@ -808,8 +824,7 @@
handle = msm_smem_user_to_kernel(v4l2_inst->mem_client,
b->m.planes[i].reserved[0],
b->m.planes[i].reserved[1],
- vidc_inst->core->resources.io_map[NS_MAP].domain,
- 0);
+ domain, 0, smem_flags);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to get device buffer address\n");
@@ -1120,9 +1135,11 @@
- SHARED_QSIZE;
partition[1].size = SHARED_QSIZE;
layout.npartitions = 2;
+ layout.is_secure = 0;
} else {
partition[0].size = io_map[i].addr_range[1];
layout.npartitions = 1;
+ layout.is_secure = 1;
}
layout.partitions = &partition[0];
layout.client_name = io_map[i].name;
@@ -1383,9 +1400,6 @@
core->debugfs_root = msm_vidc_debugfs_init_core(
core, vidc_driver->debugfs_root);
pdev->dev.platform_data = core;
- rc = msm_vidc_ssr_init(core);
- if (rc < 0)
- dprintk(VIDC_ERR, "msm_vidc : Sub Systrem Restart failed\n");
return rc;
err_cores_exceeded:
@@ -1414,7 +1428,6 @@
vidc_hal_delete_device(core->device);
video_unregister_device(&core->vdev[MSM_VIDC_ENCODER].vdev);
video_unregister_device(&core->vdev[MSM_VIDC_DECODER].vdev);
- rc = msm_vidc_ssr_uninit(core);
v4l2_device_unregister(&core->v4l2_dev);
if (core->resources.ocmem.handle)
ocmem_notifier_unregister(core->resources.ocmem.handle,
diff --git a/drivers/media/video/msm_vidc/msm_vdec.c b/drivers/media/video/msm_vidc/msm_vdec.c
index b476e39..c4bfaf4 100644
--- a/drivers/media/video/msm_vidc/msm_vdec.c
+++ b/drivers/media/video/msm_vidc/msm_vdec.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -156,7 +156,15 @@
.minimum = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE,
.maximum = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE,
.default_value = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE,
- .step = 1,
+ },
+ {
+ .id = V4L2_CID_MPEG_VIDC_VIDEO_SECURE,
+ .name = "Secure mode",
+ .type = V4L2_CTRL_TYPE_BUTTON,
+ .minimum = 0,
+ .maximum = 0,
+ .default_value = 0,
+ .step = 0,
.menu_skip_mask = 0,
.qmenu = NULL,
},
@@ -167,23 +175,7 @@
static u32 get_frame_size_nv12(int plane,
u32 height, u32 width)
{
- int size;
- int luma_h, luma_w, luma_stride, luma_scanl, luma_size;
- int chroma_h, chroma_w, chroma_stride, chroma_scanl, chroma_size;
-
- luma_w = width;
- luma_h = height;
-
- chroma_w = luma_w;
- chroma_h = luma_h/2;
- NV12_IL_CALC_Y_STRIDE(luma_stride, luma_w, 32);
- NV12_IL_CALC_Y_BUFHEIGHT(luma_scanl, luma_h, 32);
- NV12_IL_CALC_UV_STRIDE(chroma_stride, chroma_w, 32);
- NV12_IL_CALC_UV_BUFHEIGHT(chroma_scanl, luma_h, 32);
- NV12_IL_CALC_BUF_SIZE(size, luma_size, luma_stride,
- luma_scanl, chroma_size, chroma_stride, chroma_scanl, 32);
- size = ALIGN(size, SZ_4K);
- return size;
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height);
}
static u32 get_frame_size_compressed(int plane,
@@ -534,6 +526,9 @@
fmt->get_frame_size(i,
f->fmt.pix_mp.height,
f->fmt.pix_mp.width);
+ inst->bufq[OUTPUT_PORT].
+ vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
}
} else {
f->fmt.pix_mp.plane_fmt[0].sizeimage =
@@ -543,6 +538,11 @@
f->fmt.pix_mp.plane_fmt[extra_idx].sizeimage =
inst->buff_req.buffer[HAL_BUFFER_EXTRADATA_OUTPUT].buffer_size;
}
+ for (i = 0; i < fmt->num_planes; ++i)
+ inst->bufq[CAPTURE_PORT].
+ vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+
}
} else {
dprintk(VIDC_ERR,
@@ -640,6 +640,10 @@
}
}
f->fmt.pix_mp.num_planes = fmt->num_planes;
+ for (i = 0; i < fmt->num_planes; ++i) {
+ inst->bufq[CAPTURE_PORT].vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+ }
} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
inst->prop.width = f->fmt.pix_mp.width;
inst->prop.height = f->fmt.pix_mp.height;
@@ -668,6 +672,10 @@
fmt->get_frame_size(0, f->fmt.pix_mp.height,
f->fmt.pix_mp.width);
f->fmt.pix_mp.num_planes = fmt->num_planes;
+ for (i = 0; i < fmt->num_planes; ++i) {
+ inst->bufq[OUTPUT_PORT].vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+ }
}
err_invalid_fmt:
return rc;
@@ -949,7 +957,8 @@
case V4L2_DEC_CMD_STOP:
rc = msm_comm_release_scratch_buffers(inst);
if (rc)
- pr_err("Failed to release scratch buffers: %d\n", rc);
+ dprintk(VIDC_ERR,
+ "Failed to release scratch buffers: %d\n", rc);
rc = msm_comm_release_persist_buffers(inst);
if (rc)
pr_err("Failed to release persist buffers: %d\n", rc);
@@ -1018,17 +1027,8 @@
void *pdata;
struct msm_vidc_inst *inst = container_of(ctrl->handler,
struct msm_vidc_inst, ctrl_handler);
- rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
-
- if (rc) {
- dprintk(VIDC_ERR,
- "Failed to move inst: %p to start done state\n", inst);
- goto failed_open_done;
- }
-
control.id = ctrl->id;
control.value = ctrl->val;
-
switch (control.id) {
case V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT:
property_id =
@@ -1083,10 +1083,20 @@
hal_property.enable = control.value;
pdata = &hal_property;
break;
+ case V4L2_CID_MPEG_VIDC_VIDEO_SECURE:
+ inst->mode = VIDC_SECURE;
+ dprintk(VIDC_DBG, "Setting secure mode to :%d\n", inst->mode);
+ break;
default:
break;
- }
+ }
if (property_id) {
+ rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
+ if (rc) {
+ dprintk(VIDC_ERR,
+ "Failed to move inst: %p to start done state\n", inst);
+ goto failed_open_done;
+ }
dprintk(VIDC_DBG,
"Control: HAL property=%d,ctrl_id=%d,ctrl_value=%d\n",
property_id,
@@ -1098,9 +1108,7 @@
}
if (rc)
dprintk(VIDC_ERR, "Failed to set hal property for framesize\n");
-
failed_open_done:
-
return rc;
}
static int msm_vdec_op_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
diff --git a/drivers/media/video/msm_vidc/msm_venc.c b/drivers/media/video/msm_vidc/msm_venc.c
index 3f892b1..d01841d 100644
--- a/drivers/media/video/msm_vidc/msm_venc.c
+++ b/drivers/media/video/msm_vidc/msm_venc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -136,11 +136,11 @@
{
.id = V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME,
.name = "Request I Frame",
- .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .type = V4L2_CTRL_TYPE_BUTTON,
.minimum = 0,
- .maximum = 1,
+ .maximum = 0,
.default_value = 0,
- .step = 1,
+ .step = 0,
.menu_skip_mask = 0,
.qmenu = NULL,
},
@@ -461,23 +461,7 @@
static u32 get_frame_size_nv12(int plane, u32 height, u32 width)
{
- int size;
- int luma_h, luma_w, luma_stride, luma_scanl, luma_size;
- int chroma_h, chroma_w, chroma_stride, chroma_scanl, chroma_size;
-
- luma_w = width;
- luma_h = height;
-
- chroma_w = luma_w;
- chroma_h = luma_h/2;
- NV12_IL_CALC_Y_STRIDE(luma_stride, luma_w, 32);
- NV12_IL_CALC_Y_BUFHEIGHT(luma_scanl, luma_h, 32);
- NV12_IL_CALC_UV_STRIDE(chroma_stride, chroma_w, 32);
- NV12_IL_CALC_UV_BUFHEIGHT(chroma_scanl, luma_h, 32);
- NV12_IL_CALC_BUF_SIZE(size, luma_size, luma_stride,
- luma_scanl, chroma_size, chroma_stride, chroma_scanl, 32);
- size = ALIGN(size, SZ_4K);
- return size;
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height);
}
static u32 get_frame_size_nv21(int plane, u32 height, u32 width)
@@ -574,6 +558,8 @@
{
int i, rc = 0;
struct msm_vidc_inst *inst;
+ struct hal_buffer_count_actual new_buf_count;
+ enum hal_property property_id;
unsigned long flags;
if (!q || !q->drv_priv) {
dprintk(VIDC_ERR, "Invalid input, q = %p\n", q);
@@ -607,8 +593,13 @@
spin_lock_irqsave(&inst->lock, flags);
*num_buffers = inst->buff_req.buffer[0].buffer_count_actual =
max(*num_buffers, inst->buff_req.buffer[0].
- buffer_count_actual);
+ buffer_count_actual);
spin_unlock_irqrestore(&inst->lock, flags);
+ property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
+ new_buf_count.buffer_type = HAL_BUFFER_INPUT;
+ new_buf_count.buffer_count_actual = *num_buffers;
+ rc = vidc_hal_session_set_property(inst->session,
+ property_id, &new_buf_count);
dprintk(VIDC_DBG, "size = %d, alignment = %d, count = %d\n",
inst->buff_req.buffer[0].buffer_size,
inst->buff_req.buffer[0].buffer_alignment,
@@ -824,7 +815,7 @@
case V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME:
property_id =
HAL_CONFIG_VENC_REQUEST_IFRAME;
- request_iframe.enable = control.value;
+ request_iframe.enable = true;
pdata = &request_iframe;
break;
case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL:
diff --git a/drivers/media/video/msm_vidc/msm_vidc.c b/drivers/media/video/msm_vidc/msm_vidc.c
index 1d0124f..64897c7 100644
--- a/drivers/media/video/msm_vidc/msm_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_vidc.c
@@ -413,7 +413,7 @@
inst = kzalloc(sizeof(*inst), GFP_KERNEL);
if (!inst) {
- pr_err("Failed to allocate memory\n") ;
+ dprintk(VIDC_ERR, "Failed to allocate memory\n");
rc = -ENOMEM;
goto err_invalid_core;
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_common.c b/drivers/media/video/msm_vidc/msm_vidc_common.c
index 56bcf65..e85389e 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_common.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_common.c
@@ -17,7 +17,8 @@
#include <asm/div64.h>
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
+#include <mach/scm.h>
#include "msm_vidc_common.h"
#include "vidc_hal_api.h"
@@ -50,6 +51,18 @@
__mbs;\
})
+#define TZBSP_MEM_PROTECT_VIDEO_VAR 0x8
+struct tzbsp_memprot {
+ u32 cp_start;
+ u32 cp_size;
+ u32 cp_nonpixel_start;
+ u32 cp_nonpixel_size;
+};
+
+struct tzbsp_resp {
+ int ret;
+};
+
static const u32 bus_table[] = {
0,
36000,
@@ -140,6 +153,31 @@
return rc;
}
+static int protect_cp_mem(struct msm_vidc_core *core)
+{
+ struct tzbsp_memprot memprot;
+ unsigned int resp = 0;
+ int rc = 0;
+ struct msm_vidc_iommu_info *io_map = core->resources.io_map;
+ if (!io_map) {
+ dprintk(VIDC_ERR, "invalid params: %p\n", io_map);
+ return -EINVAL;
+ }
+ memprot.cp_start = 0x0;
+ memprot.cp_size = io_map[CP_MAP].addr_range[0] +
+ io_map[CP_MAP].addr_range[1];
+ memprot.cp_nonpixel_start = 0;
+ memprot.cp_nonpixel_size = 0;
+
+ rc = scm_call(SCM_SVC_CP, TZBSP_MEM_PROTECT_VIDEO_VAR, &memprot,
+ sizeof(memprot), &resp, sizeof(resp));
+ if (rc)
+ dprintk(VIDC_ERR,
+ "Failed to protect memory , rc is :%d, response : %d\n",
+ rc, resp);
+ return rc;
+}
+
struct msm_vidc_core *get_vidc_core(int core_id)
{
struct msm_vidc_core *core;
@@ -388,7 +426,9 @@
struct msm_vidc_cb_cmd_done *response = data;
struct msm_vidc_inst *inst;
struct v4l2_event dqevent;
+ struct v4l2_control control = {0};
struct msm_vidc_cb_event *event_notify;
+ int rc = 0;
if (response) {
inst = (struct msm_vidc_inst *)response->session_id;
dqevent.id = 0;
@@ -396,7 +436,16 @@
switch (event_notify->hal_event_type) {
case HAL_EVENT_SEQ_CHANGED_SUFFICIENT_RESOURCES:
dqevent.type =
- V4L2_EVENT_SEQ_CHANGED_SUFFICIENT;
+ V4L2_EVENT_SEQ_CHANGED_INSUFFICIENT;
+ control.id =
+ V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER;
+ rc = v4l2_g_ctrl(&inst->ctrl_handler, &control);
+ if (rc)
+ dprintk(VIDC_WARN,
+ "Failed to get Smooth streamng flag\n");
+ if (!rc && control.value == true)
+ dqevent.type =
+ V4L2_EVENT_SEQ_CHANGED_SUFFICIENT;
break;
case HAL_EVENT_SEQ_CHANGED_INSUFFICIENT_RESOURCES:
dqevent.type =
@@ -509,9 +558,73 @@
}
}
+static void handle_session_error(enum command_response cmd, void *data)
+{
+ struct msm_vidc_cb_cmd_done *response = data;
+ struct msm_vidc_inst *inst = NULL;
+ struct v4l2_event dqevent;
+ if (response) {
+ inst = (struct msm_vidc_inst *)response->session_id;
+ if (inst) {
+ dprintk(VIDC_WARN,
+ "Session error receivd for session %p\n", inst);
+ mutex_lock(&inst->sync_lock);
+ inst->state = MSM_VIDC_CORE_INVALID;
+ mutex_unlock(&inst->sync_lock);
+ dqevent.type = V4L2_EVENT_MSM_VIDC_SYS_ERROR;
+ dqevent.id = 0;
+ v4l2_event_queue_fh(&inst->event_handler, &dqevent);
+ wake_up(&inst->kernel_event_queue);
+ }
+ } else {
+ dprintk(VIDC_ERR,
+ "Failed to get valid response for session error\n");
+ }
+}
+static void handle_sys_error(enum command_response cmd, void *data)
+{
+ struct msm_vidc_cb_cmd_done *response = data;
+ struct msm_vidc_inst *inst = NULL ;
+ struct msm_vidc_core *core = NULL;
+ struct v4l2_event dqevent;
+ unsigned long flags;
+ if (response) {
+ inst = (struct msm_vidc_inst *)response->session_id;
+ dprintk(VIDC_WARN,
+ "Sys error received for session %p\n", inst);
+ if (inst) {
+ core = inst->core;
+ if (core) {
+ spin_lock_irqsave(&core->lock, flags);
+ core->state = VIDC_CORE_INVALID;
+ spin_unlock_irqrestore(&core->lock, flags);
+ dqevent.type = V4L2_EVENT_MSM_VIDC_SYS_ERROR;
+ dqevent.id = 0;
+ list_for_each_entry(inst, &core->instances,
+ list) {
+ if (inst) {
+ v4l2_event_queue_fh(
+ &inst->event_handler,
+ &dqevent);
+ spin_lock_irqsave(&inst->lock,
+ flags);
+ inst->state =
+ MSM_VIDC_CORE_INVALID;
+ spin_unlock_irqrestore(
+ &inst->lock, flags);
+ }
+ }
+ wake_up(&inst->kernel_event_queue);
+ }
+ }
+ } else {
+ dprintk(VIDC_ERR,
+ "Failed to get valid response for sys error\n");
+ }
+}
+
static void handle_sys_watchdog_timeout(enum command_response cmd, void *data)
{
- subsystem_restart("msm_vidc");
dprintk(VIDC_ERR,
"msm_vidc: Sub System Restart initiated\n");
}
@@ -601,7 +714,6 @@
(u32)fill_buf_done->packet_buffer1);
if (vb) {
vb->v4l2_planes[0].bytesused = fill_buf_done->filled_len1;
-
if (!(fill_buf_done->flags1 &
HAL_BUFFERFLAG_TIMESTAMPINVALID)) {
int64_t time_usec = fill_buf_done->timestamp_hi;
@@ -639,6 +751,10 @@
default:
break;
}
+ inst->count.fbd++;
+ if (fill_buf_done->filled_len1)
+ msm_vidc_debugfs_update(inst,
+ MSM_VIDC_DEBUGFS_EVENT_FBD);
dprintk(VIDC_DBG, "Filled length = %d; flags %x\n",
vb->v4l2_planes[0].bytesused,
@@ -647,7 +763,6 @@
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
mutex_unlock(&inst->bufq[CAPTURE_PORT].lock);
wake_up(&inst->kernel_event_queue);
- msm_vidc_debugfs_update(inst, MSM_VIDC_DEBUGFS_EVENT_FBD);
} else {
/*
* FIXME:
@@ -755,6 +870,12 @@
case SYS_WATCHDOG_TIMEOUT:
handle_sys_watchdog_timeout(cmd, data);
break;
+ case SYS_ERROR:
+ handle_sys_error(cmd, data);
+ break;
+ case SESSION_ERROR:
+ handle_session_error(cmd, data);
+ break;
default:
dprintk(VIDC_ERR, "response unhandled\n");
break;
@@ -837,20 +958,23 @@
}
if (!core->resources.fw.cookie)
- core->resources.fw.cookie = pil_get("venus");
+ core->resources.fw.cookie = subsystem_get("venus");
if (IS_ERR_OR_NULL(core->resources.fw.cookie)) {
dprintk(VIDC_ERR, "Failed to download firmware\n");
rc = -ENOMEM;
- goto fail_pil_get;
+ goto fail_subsystem_get;
}
-
rc = msm_comm_enable_clks(core);
if (rc) {
dprintk(VIDC_ERR, "Failed to enable clocks: %d\n", rc);
goto fail_enable_clks;
}
-
+ rc = protect_cp_mem(core);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to protect memory\n");
+ goto fail_iommu_attach;
+ }
rc = msm_comm_iommu_attach(core);
if (rc) {
dprintk(VIDC_ERR, "Failed to attach iommu");
@@ -860,9 +984,9 @@
fail_iommu_attach:
msm_comm_disable_clks(core);
fail_enable_clks:
- pil_put(core->resources.fw.cookie);
+ subsystem_put(core->resources.fw.cookie);
core->resources.fw.cookie = NULL;
-fail_pil_get:
+fail_subsystem_get:
return rc;
}
@@ -873,10 +997,10 @@
return;
}
if (core->resources.fw.cookie) {
- pil_put(core->resources.fw.cookie);
- core->resources.fw.cookie = NULL;
msm_comm_iommu_detach(core);
msm_comm_disable_clks(core);
+ subsystem_put(core->resources.fw.cookie);
+ core->resources.fw.cookie = NULL;
}
}
@@ -1351,6 +1475,25 @@
return rc;
}
+static int get_flipped_state(int present_state,
+ int desired_state)
+{
+ int flipped_state = present_state;
+ if (flipped_state < MSM_VIDC_STOP
+ && desired_state > MSM_VIDC_STOP) {
+ flipped_state = MSM_VIDC_STOP + (MSM_VIDC_STOP - flipped_state);
+ flipped_state &= 0xFFFE;
+ flipped_state = flipped_state - 1;
+ } else if (flipped_state > MSM_VIDC_STOP
+ && desired_state < MSM_VIDC_STOP) {
+ flipped_state = MSM_VIDC_STOP -
+ (flipped_state - MSM_VIDC_STOP + 1);
+ flipped_state &= 0xFFFE;
+ flipped_state = flipped_state - 1;
+ }
+ return flipped_state;
+}
+
int msm_comm_try_state(struct msm_vidc_inst *inst, int state)
{
int rc = 0;
@@ -1377,89 +1520,77 @@
"Core is in bad state can't change the state");
goto exit;
}
- flipped_state = inst->state;
- if (flipped_state < MSM_VIDC_STOP
- && state > MSM_VIDC_STOP) {
- flipped_state = MSM_VIDC_STOP + (MSM_VIDC_STOP - flipped_state);
- flipped_state &= 0xFFFE;
- flipped_state = flipped_state - 1;
- } else if (flipped_state > MSM_VIDC_STOP
- && state < MSM_VIDC_STOP) {
- flipped_state = MSM_VIDC_STOP -
- (flipped_state - MSM_VIDC_STOP + 1);
- flipped_state &= 0xFFFE;
- flipped_state = flipped_state - 1;
- }
+ flipped_state = get_flipped_state(inst->state, state);
dprintk(VIDC_DBG,
"flipped_state = 0x%x\n", flipped_state);
switch (flipped_state) {
case MSM_VIDC_CORE_UNINIT_DONE:
case MSM_VIDC_CORE_INIT:
rc = msm_comm_init_core(inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CORE_INIT_DONE:
rc = msm_comm_init_core_done(inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_OPEN:
rc = msm_comm_session_init(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_OPEN_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_OPEN_DONE,
SESSION_INIT_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_LOAD_RESOURCES:
rc = msm_vidc_load_resources(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_LOAD_RESOURCES_DONE:
case MSM_VIDC_START:
rc = msm_vidc_start(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_START_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_START_DONE,
SESSION_START_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_STOP:
rc = msm_vidc_stop(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_STOP_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_STOP_DONE,
SESSION_STOP_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
dprintk(VIDC_DBG, "Moving to Stop Done state\n");
case MSM_VIDC_RELEASE_RESOURCES:
rc = msm_vidc_release_res(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_RELEASE_RESOURCES_DONE:
rc = wait_for_state(inst, flipped_state,
MSM_VIDC_RELEASE_RESOURCES_DONE,
SESSION_RELEASE_RESOURCE_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
dprintk(VIDC_DBG,
"Moving to release resources done state\n");
case MSM_VIDC_CLOSE:
rc = msm_comm_session_close(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CLOSE_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_CLOSE_DONE,
SESSION_END_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CORE_UNINIT:
dprintk(VIDC_DBG, "Sending core uninit\n");
rc = msm_vidc_deinit_core(inst);
- if (rc || state == inst->state)
+ if (rc || state == get_flipped_state(inst->state, state))
break;
default:
dprintk(VIDC_ERR, "State not recognized\n");
@@ -1548,6 +1679,8 @@
struct vidc_seq_hdr seq_hdr;
int extra_idx = 0;
frame_data.filled_len = 0;
+ frame_data.offset = 0;
+ frame_data.alloc_len = vb->v4l2_planes[0].length;
frame_data.buffer_type = HAL_BUFFER_OUTPUT;
extra_idx =
EXTRADATA_IDX(inst->fmts[CAPTURE_PORT]->num_planes);
@@ -1759,6 +1892,8 @@
struct internal_buf *binfo;
struct vidc_buffer_addr_info buffer_info;
unsigned long flags;
+ int domain;
+ unsigned long smem_flags = 0;
struct hal_buffer_requirements *scratch_buf =
&inst->buff_req.buffer[HAL_BUFFER_INTERNAL_SCRATCH];
int i;
@@ -1768,14 +1903,18 @@
scratch_buf->buffer_size);
if (msm_comm_release_scratch_buffers(inst))
dprintk(VIDC_WARN, "Failed to release scratch buffers\n");
+ if (inst->mode == VIDC_SECURE) {
+ domain = inst->core->resources.io_map[CP_MAP].domain;
+ smem_flags |= SMEM_SECURE;
+ } else
+ domain = inst->core->resources.io_map[NS_MAP].domain;
if (scratch_buf->buffer_size) {
for (i = 0; i < scratch_buf->buffer_count_actual;
i++) {
handle = msm_smem_alloc(inst->mem_client,
- scratch_buf->buffer_size, 1, SMEM_UNCACHED,
- inst->core->resources.io_map[NS_MAP].domain,
- 0, 0);
+ scratch_buf->buffer_size, 1, smem_flags,
+ domain, 0, 0);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to allocate scratch memory\n");
@@ -1821,6 +1960,8 @@
struct internal_buf *binfo;
struct vidc_buffer_addr_info buffer_info;
unsigned long flags;
+ unsigned long smem_flags = 0;
+ int domain;
struct hal_buffer_requirements *persist_buf =
&inst->buff_req.buffer[HAL_BUFFER_INTERNAL_PERSIST];
int i;
@@ -1834,12 +1975,17 @@
return rc;
}
+ if (inst->mode == VIDC_SECURE) {
+ domain = inst->core->resources.io_map[CP_MAP].domain;
+ flags |= SMEM_SECURE;
+ } else
+ domain = inst->core->resources.io_map[NS_MAP].domain;
+
if (persist_buf->buffer_size) {
for (i = 0; i < persist_buf->buffer_count_actual; i++) {
handle = msm_smem_alloc(inst->mem_client,
- persist_buf->buffer_size, 1, SMEM_UNCACHED,
- inst->core->resources.io_map[NS_MAP].domain,
- 0, 0);
+ persist_buf->buffer_size, 1, smem_flags,
+ domain, 0, 0);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to allocate persist memory\n");
diff --git a/drivers/media/video/msm_vidc/msm_vidc_debug.c b/drivers/media/video/msm_vidc/msm_vidc_debug.c
index 914c422..f91d0dd 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_debug.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_debug.c
@@ -202,28 +202,27 @@
switch (e) {
case MSM_VIDC_DEBUGFS_EVENT_ETB:
inst->count.etb++;
- if (inst->count.ftb > inst->count.fbd) {
+ if (inst->count.ebd && inst->count.ftb > inst->count.fbd) {
d->pdata[FRAME_PROCESSING].name[0] = '\0';
tic(inst, FRAME_PROCESSING, a);
}
break;
case MSM_VIDC_DEBUGFS_EVENT_EBD:
inst->count.ebd++;
- if (inst->count.ebd == inst->count.etb)
+ if (inst->count.ebd && inst->count.ebd == inst->count.etb)
toc(inst, FRAME_PROCESSING);
break;
case MSM_VIDC_DEBUGFS_EVENT_FTB: {
inst->count.ftb++;
- if (inst->count.etb > inst->count.ebd) {
+ if (inst->count.ebd && inst->count.etb > inst->count.ebd) {
d->pdata[FRAME_PROCESSING].name[0] = '\0';
tic(inst, FRAME_PROCESSING, a);
}
}
break;
case MSM_VIDC_DEBUGFS_EVENT_FBD:
- inst->count.fbd++;
- inst->debug.counter++;
- if (inst->count.fbd == inst->count.ftb)
+ inst->debug.samples++;
+ if (inst->count.ebd && inst->count.fbd == inst->count.ftb)
toc(inst, FRAME_PROCESSING);
break;
default:
diff --git a/drivers/media/video/msm_vidc/msm_vidc_debug.h b/drivers/media/video/msm_vidc/msm_vidc_debug.h
index 1a51173..995daf0 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_debug.h
+++ b/drivers/media/video/msm_vidc/msm_vidc_debug.h
@@ -81,23 +81,8 @@
do_gettimeofday(&__ddl_tv);
i->debug.pdata[p].stop = (__ddl_tv.tv_sec * 1000)
+ (__ddl_tv.tv_usec / 1000);
- i->debug.pdata[p].cumulative =
+ i->debug.pdata[p].cumulative +=
(i->debug.pdata[p].stop - i->debug.pdata[p].start);
- if (i->count.fbd) {
- if (i->debug.pdata[p].average != 0) {
- i->debug.pdata[p].average = ((i->debug.pdata[p].
- average * (i->count.fbd -
- i->debug.counter) +
- i->debug.pdata[p].cumulative)
- / i->count.fbd);
- } else {
- i->debug.pdata[p].average =
- i->debug.pdata[p].cumulative
- / i->count.fbd;
- }
- }
- i->debug.counter = 0;
- i->debug.pdata[p].cumulative = 0;
i->debug.pdata[p].sampling = true;
}
}
@@ -110,9 +95,11 @@
(msm_vidc_debug & VIDC_PROF)) {
dprintk(VIDC_PROF, "%s averaged %d ms/sample\n",
i->debug.pdata[x].name,
- i->debug.pdata[x].average);
+ i->debug.pdata[x].cumulative /
+ i->debug.samples);
dprintk(VIDC_PROF, "%s Samples: %d",
- i->debug.pdata[x].name, i->count.fbd);
+ i->debug.pdata[x].name,
+ i->debug.samples);
}
}
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_internal.h b/drivers/media/video/msm_vidc/msm_vidc_internal.h
index f288cc6..e9295a6 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_internal.h
+++ b/drivers/media/video/msm_vidc/msm_vidc_internal.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -30,6 +30,7 @@
#include <media/v4l2-ctrls.h>
#include <media/videobuf2-core.h>
#include <media/msm_vidc.h>
+#include <media/msm_media_info.h>
#include "vidc_hal_api.h"
@@ -49,33 +50,7 @@
#define MAX_NAME_LENGTH 64
-#define NV12_IL_CALC_Y_STRIDE(stride, frame_width, stride_multiple) \
- { stride = (frame_width + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1)); }
-
-#define NV12_IL_CALC_Y_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = (frame_height + min_buf_height_multiple - 1) & \
- (0xffffffff - (min_buf_height_multiple - 1)); }
-
-#define NV12_IL_CALC_UV_STRIDE(stride, frame_width, stride_multiple) \
- { stride = ((((frame_width + 1) >> 1) + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1))) << 1; }
-
-#define NV12_IL_CALC_UV_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = ((((frame_height + 1) >> 1) + \
- min_buf_height_multiple - 1) & (0xffffffff - \
- (min_buf_height_multiple - 1))); }
-
-#define NV12_IL_CALC_BUF_SIZE(buf_size, y_buf_size, y_stride, \
- y_buf_height, uv_buf_size, uv_stride, uv_buf_height, uv_alignment) \
- { y_buf_size = (y_stride * y_buf_height); \
- uv_buf_size = (uv_stride * uv_buf_height) + uv_alignment; \
- buf_size = y_buf_size + uv_buf_size; }
-
#define EXTRADATA_IDX(__num_planes) (__num_planes - 1)
-
enum vidc_ports {
OUTPUT_PORT,
CAPTURE_PORT,
@@ -225,7 +200,7 @@
struct msm_vidc_debug {
struct profile_data pdata[MAX_PROFILING_POINTS];
int profile;
- int counter;
+ int samples;
};
struct msm_vidc_ssr_info {
@@ -235,6 +210,11 @@
bool ssr_in_progress;
};
+enum msm_vidc_mode {
+ VIDC_NON_SECURE,
+ VIDC_SECURE,
+};
+
struct msm_vidc_core {
struct list_head list;
struct mutex sync_lock;
@@ -285,6 +265,7 @@
void *priv;
struct msm_vidc_debug debug;
struct buf_count count;
+ enum msm_vidc_mode mode;
};
extern struct msm_vidc_drv *vidc_driver;
diff --git a/drivers/media/video/msm_vidc/msm_vidc_ssr.c b/drivers/media/video/msm_vidc/msm_vidc_ssr.c
index e8a6745..33464c6f 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_ssr.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_ssr.c
@@ -157,7 +157,8 @@
dprintk(VIDC_ERR, "msm_vidc Sub System registration failed\n");
rc = -ENODEV;
}
- core->ssr_info.msm_vidc_ramdump_dev = create_ramdump_device("msm_vidc");
+ core->ssr_info.msm_vidc_ramdump_dev = create_ramdump_device("msm_vidc",
+ msm_vidc_subsystem.dev);
if (!core->ssr_info.msm_vidc_ramdump_dev) {
dprintk(VIDC_ERR, "Unable to create msm_vidc ramdump device\n");
rc = -ENODEV;
diff --git a/drivers/media/video/msm_vidc/vidc_hal.c b/drivers/media/video/msm_vidc/vidc_hal.c
index 190e132..f44be4d 100644
--- a/drivers/media/video/msm_vidc/vidc_hal.c
+++ b/drivers/media/video/msm_vidc/vidc_hal.c
@@ -501,18 +501,27 @@
static void vidc_hal_interface_queues_release(struct hal_device *device)
{
int i;
+
+ vidc_hal_free(device->hal_client, device->mem_addr.mem_data);
+
for (i = 0; i < VIDC_IFACEQ_NUMQ; i++) {
- vidc_hal_free(device->hal_client,
- device->iface_queues[i].q_array.mem_data);
device->iface_queues[i].q_hdr = NULL;
device->iface_queues[i].q_array.mem_data = NULL;
device->iface_queues[i].q_array.align_virtual_addr = NULL;
device->iface_queues[i].q_array.align_device_addr = NULL;
}
- vidc_hal_free(device->hal_client,
- device->iface_q_table.mem_data);
device->iface_q_table.align_virtual_addr = NULL;
device->iface_q_table.align_device_addr = NULL;
+
+ device->qdss.align_virtual_addr = NULL;
+ device->qdss.align_device_addr = NULL;
+
+ device->sfr.align_virtual_addr = NULL;
+ device->sfr.align_device_addr = NULL;
+
+ device->mem_addr.align_virtual_addr = NULL;
+ device->mem_addr.align_device_addr = NULL;
+
msm_smem_delete_client(device->hal_client);
device->hal_client = NULL;
}
@@ -524,14 +533,51 @@
u8 i;
int rc = 0;
struct vidc_iface_q_info *iface_q;
-
- rc = vidc_hal_alloc((void *) &dev->iface_q_table,
- dev->hal_client,
- VIDC_IFACEQ_TABLE_SIZE, 1, SMEM_UNCACHED, domain);
+ struct hfi_sfr_struct *vsfr;
+ struct vidc_mem_addr *mem_addr;
+ int offset = 0;
+ int size_1m = 1024 * 1024;
+ int uc_size = (UC_SIZE + size_1m - 1) & (~(size_1m - 1));
+ mem_addr = &dev->mem_addr;
+ rc = vidc_hal_alloc((void *) mem_addr,
+ dev->hal_client, uc_size, 1,
+ 0, domain);
if (rc) {
dprintk(VIDC_ERR, "iface_q_table_alloc_fail");
return -ENOMEM;
}
+ dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
+ dev->iface_q_table.align_device_addr = mem_addr->align_device_addr;
+ dev->iface_q_table.mem_size = VIDC_IFACEQ_TABLE_SIZE;
+ dev->iface_q_table.mem_data = NULL;
+ offset += dev->iface_q_table.mem_size;
+
+ for (i = 0; i < VIDC_IFACEQ_NUMQ; i++) {
+ iface_q = &dev->iface_queues[i];
+ iface_q->q_array.align_device_addr =
+ mem_addr->align_device_addr + offset;
+ iface_q->q_array.align_virtual_addr =
+ mem_addr->align_virtual_addr + offset;
+ iface_q->q_array.mem_size = VIDC_IFACEQ_QUEUE_SIZE;
+ iface_q->q_array.mem_data = NULL;
+ offset += iface_q->q_array.mem_size;
+ iface_q->q_hdr = VIDC_IFACEQ_GET_QHDR_START_ADDR(
+ dev->iface_q_table.align_virtual_addr, i);
+ vidc_hal_set_queue_hdr_defaults(iface_q->q_hdr);
+ }
+
+ dev->qdss.align_device_addr = mem_addr->align_device_addr + offset;
+ dev->qdss.align_virtual_addr = mem_addr->align_virtual_addr + offset;
+ dev->qdss.mem_size = QDSS_SIZE;
+ dev->qdss.mem_data = NULL;
+ offset += dev->qdss.mem_size;
+
+ dev->sfr.align_device_addr = mem_addr->align_device_addr + offset;
+ dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr + offset;
+ dev->sfr.mem_size = SFR_SIZE;
+ dev->sfr.mem_data = NULL;
+ offset += dev->sfr.mem_size;
+
q_tbl_hdr = (struct hfi_queue_table_header *)
dev->iface_q_table.align_virtual_addr;
q_tbl_hdr->qtbl_version = 0;
@@ -543,23 +589,6 @@
q_tbl_hdr->qtbl_num_q = VIDC_IFACEQ_NUMQ;
q_tbl_hdr->qtbl_num_active_q = VIDC_IFACEQ_NUMQ;
- for (i = 0; i < VIDC_IFACEQ_NUMQ; i++) {
- iface_q = &dev->iface_queues[i];
- rc = vidc_hal_alloc((void *) &iface_q->q_array,
- dev->hal_client, VIDC_IFACEQ_QUEUE_SIZE,
- 1, SMEM_UNCACHED, domain);
- if (rc) {
- dprintk(VIDC_ERR, "iface_q_table_alloc[%d]_fail", i);
- vidc_hal_interface_queues_release(dev);
- return -ENOMEM;
- } else {
- iface_q->q_hdr =
- VIDC_IFACEQ_GET_QHDR_START_ADDR(
- dev->iface_q_table.align_virtual_addr, i);
- vidc_hal_set_queue_hdr_defaults(iface_q->q_hdr);
- }
- }
-
iface_q = &dev->iface_queues[VIDC_IFACEQ_CMDQ_IDX];
q_hdr = iface_q->q_hdr;
q_hdr->qhdr_start_addr = (u32)
@@ -577,6 +606,12 @@
q_hdr->qhdr_start_addr = (u32)
iface_q->q_array.align_device_addr;
q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
+
+ write_register(dev->hal_data->register_base_addr,
+ VIDC_UC_REGION_ADDR,
+ (u32) mem_addr->align_device_addr, 0);
+ write_register(dev->hal_data->register_base_addr,
+ VIDC_UC_REGION_SIZE, mem_addr->mem_size, 0);
write_register(dev->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG2,
(u32) dev->iface_q_table.align_device_addr,
@@ -584,6 +619,15 @@
write_register(dev->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG1, 0x01,
dev->iface_q_table.align_virtual_addr);
+ write_register(dev->hal_data->register_base_addr,
+ VIDC_MMAP_ADDR,
+ (u32) dev->qdss.align_device_addr, 0);
+
+ vsfr = (struct hfi_sfr_struct *) dev->sfr.align_virtual_addr;
+ vsfr->bufSize = SFR_SIZE;
+
+ write_register(dev->hal_data->register_base_addr,
+ VIDC_SFR_ADDR, (u32)dev->sfr.align_device_addr , 0);
return 0;
}
@@ -595,10 +639,15 @@
VIDC_WRAPPER_INTR_MASK, 0x8, 0);
write_register(device->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG3, 1, 0);
+
while (!ctrl_status && count < max_tries) {
ctrl_status = read_register(
device->hal_data->register_base_addr,
VIDC_CPU_CS_SCIACMDARG0);
+ if ((ctrl_status & 0xFE) == 0x4) {
+ dprintk(VIDC_ERR, "invalid setting for UC_REGION\n");
+ break;
+ }
usleep_range(500, 1000);
count++;
}
@@ -613,11 +662,9 @@
write_register(device->hal_data->register_base_addr,
VIDC_VENUS_VBIF_CLK_ON, 1, 0);
write_register(device->hal_data->register_base_addr,
- VIDC_VBIF_OUT_AXI_AOOO_EN, 0x00000FFF, 0);
+ VIDC_VBIF_OUT_AXI_AOOO_EN, 0x00001FFF, 0);
write_register(device->hal_data->register_base_addr,
- VIDC_VBIF_OUT_AXI_AOOO, 0x0FFF0FFF, 0);
- write_register(device->hal_data->register_base_addr,
- VIDC_VENUS_VBIF_CLK_ON, 1, 0);
+ VIDC_VBIF_OUT_AXI_AOOO, 0x1FFF1FFF, 0);
write_register(device->hal_data->register_base_addr,
VIDC_VBIF_IN_RD_LIM_CONF0, 0x10101001, 0);
write_register(device->hal_data->register_base_addr,
@@ -641,7 +688,15 @@
write_register(device->hal_data->register_base_addr,
VIDC_VBIF_ARB_CTL, 0x00000030, 0);
write_register(device->hal_data->register_base_addr,
+ VIDC_VENUS_VBIF_DDR_OUT_MAX_BURST, 0x00000707, 0);
+ write_register(device->hal_data->register_base_addr,
+ VIDC_VENUS_VBIF_OCMEM_OUT_MAX_BURST, 0x00000707, 0);
+ write_register(device->hal_data->register_base_addr,
+ VIDC_VENUS_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000001, 0);
+ write_register(device->hal_data->register_base_addr,
VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY, 0x5555556, 0);
+ write_register(device->hal_data->register_base_addr,
+ VIDC_VENUS0_WRAPPER_VBIF_PRIORITY_LEVEL, 0, 0);
}
static int vidc_hal_sys_set_debug(struct hal_device *device, int debug)
@@ -679,6 +734,7 @@
spin_lock_init(&dev->read_lock);
spin_lock_init(&dev->write_lock);
set_vbif_registers(dev);
+
if (!dev->hal_client) {
dev->hal_client = msm_smem_new_client(SMEM_ION);
if (dev->hal_client == NULL) {
@@ -687,8 +743,7 @@
goto err_no_mem;
}
- dprintk(VIDC_DBG, "Device_Virt_Address : 0x%x,"
- "Register_Virt_Addr: 0x%x",
+ dprintk(VIDC_DBG, "Dev_Virt: 0x%x, Reg_Virt: 0x%x",
dev->hal_data->device_base_addr,
(u32) dev->hal_data->register_base_addr);
@@ -703,12 +758,15 @@
rc = -EEXIST;
goto err_no_mem;
}
+ write_register(dev->hal_data->register_base_addr,
+ VIDC_CTRL_INIT, 0x1, 0);
rc = vidc_hal_core_start_cpu(dev);
if (rc) {
dprintk(VIDC_ERR, "Failed to start core");
rc = -ENODEV;
goto err_no_dev;
}
+
pkt.size = sizeof(struct hfi_cmd_sys_init_packet);
pkt.packet_type = HFI_CMD_SYS_INIT;
pkt.arch_type = HFI_ARCH_OX_OFFSET;
@@ -1202,7 +1260,7 @@
{
struct hfi_enable *hfi;
pkt->rg_property_data[0] =
- HFI_PROPERTY_PARAM_VENC_SYNC_FRAME_SEQUENCE_HEADER;
+ HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER;
hfi = (struct hfi_enable *) &pkt->rg_property_data[1];
hfi->enable = ((struct hfi_enable *) pdata)->enable;
pkt->size += sizeof(u32) * 2;
@@ -1728,7 +1786,6 @@
((buffer_info->num_buffers - 1) * sizeof(u32));
pkt->packet_type = HFI_CMD_SESSION_SET_BUFFERS;
pkt->session_id = (u32) session;
- pkt->buffer_mode = HFI_BUFFER_MODE_STATIC;
pkt->buffer_size = buffer_info->buffer_size;
pkt->min_buffer_size = buffer_info->buffer_size;
pkt->num_buffers = buffer_info->num_buffers;
@@ -1943,8 +2000,11 @@
pkt.packet_buffer = (u8 *) output_frame->device_addr;
pkt.extra_data_buffer =
(u8 *) output_frame->extradata_addr;
-
- dprintk(VIDC_INFO, "### Q OUTPUT BUFFER ###");
+ pkt.alloc_len = output_frame->alloc_len;
+ pkt.filled_len = output_frame->filled_len;
+ pkt.offset = output_frame->offset;
+ dprintk(VIDC_DBG, "### Q OUTPUT BUFFER ###: %d, %d, %d\n",
+ pkt.alloc_len, pkt.filled_len, pkt.offset);
if (vidc_hal_iface_cmdq_write(session->device, &pkt))
rc = -ENOTEMPTY;
return rc;
@@ -2121,8 +2181,8 @@
dprintk(VIDC_INFO, " GOT INTERRUPT () ");
if (!device->callback) {
- dprintk(VIDC_ERR, "No callback function "
- "to process interrupt: %p\n", device);
+ dprintk(VIDC_ERR, "No interrupt callback function: %p\n",
+ device);
return;
}
vidc_hal_core_clear_interrupt(device);
@@ -2230,7 +2290,7 @@
list_for_each_entry(close, &hal_ctxt.dev_head, list) {
if (close->hal_data->irq == dev->hal_data->irq) {
hal_ctxt.dev_count--;
- free_irq(dev->hal_data->irq, NULL);
+ free_irq(dev->hal_data->irq, close);
list_del(&close->list);
destroy_workqueue(close->vidc_workq);
kfree(close->hal_data);
diff --git a/drivers/media/video/msm_vidc/vidc_hal.h b/drivers/media/video/msm_vidc/vidc_hal.h
index 0e70e30..57d685b 100644
--- a/drivers/media/video/msm_vidc/vidc_hal.h
+++ b/drivers/media/video/msm_vidc/vidc_hal.h
@@ -81,6 +81,12 @@
(void *)((((u32)ptr) + sizeof(struct hfi_queue_table_header)) + \
(i * sizeof(struct hfi_queue_header)))
+#define QDSS_SIZE 4096
+#define SFR_SIZE 4096
+
+#define UC_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
+ (VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ) + QDSS_SIZE + SFR_SIZE)
+
enum vidc_hw_reg {
VIDC_HWREG_CTRL_STATUS = 0x1,
VIDC_HWREG_QTBL_INFO = 0x2,
@@ -113,6 +119,9 @@
#define HFI_BUFFERFLAG_TIMESTAMPINVALID 0x00000100
#define HFI_BUFFERFLAG_READONLY 0x00000200
#define HFI_BUFFERFLAG_ENDOFSUBFRAME 0x00000400
+#define HFI_BUFFERFLAG_EOSEQ 0x00200000
+#define HFI_BUFFERFLAG_DISCONTINUITY 0x80000000
+#define HFI_BUFFERFLAG_TEI 0x40000000
#define HFI_ERR_SESSION_EMPTY_BUFFER_DONE_OUTPUT_PENDING \
(HFI_OX_BASE + 0x1001)
@@ -120,6 +129,8 @@
(HFI_OX_BASE + 0x1002)
#define HFI_ERR_SESSION_SYNC_FRAME_NOT_DETECTED \
(HFI_OX_BASE + 0x1003)
+#define HFI_ERR_SESSION_START_CODE_NOT_FOUND \
+ (HFI_OX_BASE + 0x1004)
#define HFI_BUFFER_INTERNAL_SCRATCH (HFI_OX_BASE + 0x1)
#define HFI_BUFFER_EXTRADATA_INPUT (HFI_OX_BASE + 0x2)
@@ -129,6 +140,11 @@
#define HFI_BUFFER_MODE_STATIC (HFI_OX_BASE + 0x1)
#define HFI_BUFFER_MODE_RING (HFI_OX_BASE + 0x2)
+struct hfi_buffer_alloc_mode {
+ u32 buffer_type;
+ u32 buffer_mode;
+};
+
#define HFI_FLUSH_INPUT (HFI_OX_BASE + 0x1)
#define HFI_FLUSH_OUTPUT (HFI_OX_BASE + 0x2)
#define HFI_FLUSH_OUTPUT2 (HFI_OX_BASE + 0x3)
@@ -141,7 +157,11 @@
#define HFI_EXTRADATA_VC1_SEQDISP 0x00000004
#define HFI_EXTRADATA_TIMESTAMP 0x00000005
#define HFI_EXTRADATA_S3D_FRAME_PACKING 0x00000006
-#define HFI_EXTRADATA_EOSNAL_DETECTED 0x00000007
+#define HFI_EXTRADATA_FRAME_RATE 0x00000007
+#define HFI_EXTRADATA_PANSCAN_WINDOW 0x00000008
+#define HFI_EXTRADATA_RECOVERY_POINT_SEI 0x00000009
+#define HFI_EXTRADATA_CLOSED_CAPTION_UD 0x0000000A
+#define HFI_EXTRADATA_AFD_UD 0x0000000B
#define HFI_EXTRADATA_MULTISLICE_INFO 0x7F100000
#define HFI_EXTRADATA_NUM_CONCEALED_MB 0x7F100001
#define HFI_EXTRADATA_INDEX 0x7F100002
@@ -151,7 +171,7 @@
#define HFI_INDEX_EXTRADATA_DIGITAL_ZOOM 0x07000010
#define HFI_INDEX_EXTRADATA_ASPECT_RATIO 0x7F100003
-struct HFI_INDEX_EXTRADATA_CONFIG_TYPE {
+struct hfi_index_extradata_config {
int enable;
u32 index_extra_data_id;
};
@@ -188,10 +208,14 @@
(HFI_PROPERTY_PARAM_OX_START + 0x004)
#define HFI_PROPERTY_PARAM_EXTRA_DATA_HEADER_CONFIG \
(HFI_PROPERTY_PARAM_OX_START + 0x005)
-#define HFI_PROPERTY_PARAM_INDEX_EXTRADATA \
+#define HFI_PROPERTY_PARAM_INDEX_EXTRADATA \
(HFI_PROPERTY_PARAM_OX_START + 0x006)
#define HFI_PROPERTY_PARAM_DIVX_FORMAT \
(HFI_PROPERTY_PARAM_OX_START + 0x007)
+#define HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE \
+ (HFI_PROPERTY_PARAM_OX_START + 0x008)
+#define HFI_PROPERTY_PARAM_S3D_FRAME_PACKING_EXTRADATA \
+ (HFI_PROPERTY_PARAM_OX_START + 0x009)
#define HFI_PROPERTY_CONFIG_OX_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x02000)
@@ -233,6 +257,20 @@
#define HFI_PROPERTY_PARAM_VDEC_THUMBNAIL_MODE \
(HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00D)
+#define HFI_PROPERTY_PARAM_VDEC_FRAME_ASSEMBLY \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00E)
+#define HFI_PROPERTY_PARAM_VDEC_CLOSED_CAPTION_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x00F)
+#define HFI_PROPERTY_PARAM_VDEC_AFD_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x010)
+#define HFI_PROPERTY_PARAM_VDEC_VC1_FRAMEDISP_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x011)
+#define HFI_PROPERTY_PARAM_VDEC_VC1_SEQDISP_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x012)
+#define HFI_PROPERTY_PARAM_VDEC_TIMESTAMP_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x013)
+#define HFI_PROPERTY_PARAM_VDEC_INTERLACE_VIDEO_EXTRADATA \
+ (HFI_PROPERTY_PARAM_VDEC_OX_START + 0x014)
#define HFI_PROPERTY_CONFIG_VDEC_OX_START \
(HFI_DOMAIN_BASE_VDEC + HFI_ARCH_OX_OFFSET + 0x0000)
@@ -249,8 +287,11 @@
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x001)
#define HFI_PROPERTY_PARAM_VENC_H264_IDR_S3D_FRAME_PACKING_NAL \
(HFI_PROPERTY_PARAM_VENC_OX_START + 0x002)
+
#define HFI_PROPERTY_CONFIG_VENC_OX_START \
(HFI_DOMAIN_BASE_VENC + HFI_ARCH_OX_OFFSET + 0x6000)
+#define HFI_PROPERTY_CONFIG_VENC_FRAME_QP \
+ (HFI_PROPERTY_CONFIG_VENC_OX_START + 0x001)
#define HFI_PROPERTY_PARAM_VPE_OX_START \
(HFI_DOMAIN_BASE_VPE + HFI_ARCH_OX_OFFSET + 0x7000)
@@ -346,12 +387,12 @@
};
#define HFI_CMD_SYS_OX_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x0000)
+(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_CMD_START_OFFSET + 0x0000)
#define HFI_CMD_SYS_SESSION_ABORT (HFI_CMD_SYS_OX_START + 0x001)
#define HFI_CMD_SYS_PING (HFI_CMD_SYS_OX_START + 0x002)
#define HFI_CMD_SESSION_OX_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x1000)
+(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_CMD_START_OFFSET + 0x1000)
#define HFI_CMD_SESSION_LOAD_RESOURCES (HFI_CMD_SESSION_OX_START + 0x001)
#define HFI_CMD_SESSION_START (HFI_CMD_SESSION_OX_START + 0x002)
#define HFI_CMD_SESSION_STOP (HFI_CMD_SESSION_OX_START + 0x003)
@@ -369,14 +410,14 @@
(HFI_CMD_SESSION_OX_START + 0x00C)
#define HFI_MSG_SYS_OX_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x0000)
+(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_MSG_START_OFFSET + 0x0000)
#define HFI_MSG_SYS_IDLE (HFI_MSG_SYS_OX_START + 0x1)
#define HFI_MSG_SYS_PING_ACK (HFI_MSG_SYS_OX_START + 0x2)
#define HFI_MSG_SYS_PROPERTY_INFO (HFI_MSG_SYS_OX_START + 0x3)
#define HFI_MSG_SYS_SESSION_ABORT_DONE (HFI_MSG_SYS_OX_START + 0x4)
#define HFI_MSG_SESSION_OX_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + 0x1000)
+(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_OX_OFFSET + HFI_MSG_START_OFFSET + 0x1000)
#define HFI_MSG_SESSION_LOAD_RESOURCES_DONE (HFI_MSG_SESSION_OX_START + 0x1)
#define HFI_MSG_SESSION_START_DONE (HFI_MSG_SESSION_OX_START + 0x2)
#define HFI_MSG_SESSION_STOP_DONE (HFI_MSG_SESSION_OX_START + 0x3)
@@ -386,9 +427,12 @@
#define HFI_MSG_SESSION_EMPTY_BUFFER_DONE (HFI_MSG_SESSION_OX_START + 0x7)
#define HFI_MSG_SESSION_FILL_BUFFER_DONE (HFI_MSG_SESSION_OX_START + 0x8)
#define HFI_MSG_SESSION_PROPERTY_INFO (HFI_MSG_SESSION_OX_START + 0x9)
-#define HFI_MSG_SESSION_RELEASE_RESOURCES_DONE (HFI_MSG_SESSION_OX_START + 0xA)
+#define HFI_MSG_SESSION_RELEASE_RESOURCES_DONE \
+ (HFI_MSG_SESSION_OX_START + 0xA)
#define HFI_MSG_SESSION_PARSE_SEQUENCE_HEADER_DONE \
(HFI_MSG_SESSION_OX_START + 0xB)
+#define HFI_MSG_SESSION_RELEASE_BUFFERS_DONE \
+ (HFI_MSG_SESSION_OX_START + 0xC)
struct hfi_cmd_sys_session_abort_packet {
u32 size;
@@ -476,6 +520,9 @@
u32 packet_type;
u32 session_id;
u32 stream_id;
+ u32 offset;
+ u32 alloc_len;
+ u32 filled_len;
u32 output_tag;
u8 *packet_buffer;
u8 *extra_data_buffer;
@@ -515,6 +562,7 @@
u32 buffer_type;
u32 buffer_size;
u32 extra_data_size;
+ int response_req;
u32 num_buffers;
u32 rg_buffer_info[1];
};
@@ -702,6 +750,15 @@
u32 error_type;
};
+struct hfi_msg_session_release_buffers_done_packet {
+ u32 size;
+ u32 packet_type;
+ u32 session_id;
+ u32 error_type;
+ u32 num_buffers;
+ u32 rg_buffer_info[1];
+};
+
struct hfi_extradata_mb_quantization_payload {
u8 rg_mb_qp[1];
};
@@ -740,41 +797,26 @@
u32 time_stamp_high;
};
-enum HFI_S3D_FP_LAYOUT {
- HFI_S3D_FP_LAYOUT_NONE,
- HFI_S3D_FP_LAYOUT_INTRLV_CHECKERBOARD,
- HFI_S3D_FP_LAYOUT_INTRLV_COLUMN,
- HFI_S3D_FP_LAYOUT_INTRLV_ROW,
- HFI_S3D_FP_LAYOUT_SIDEBYSIDE,
- HFI_S3D_FP_LAYOUT_TOPBOTTOM,
- HFI_S3D_FP_LAYOUT_UNUSED = 0x10000000
-};
-
-enum HFI_S3D_FP_VIEW_ORDER {
- HFI_S3D_FP_LEFTVIEW_FIRST,
- HFI_S3D_FP_RIGHTVIEW_FIRST,
- HFI_S3D_FP_UNKNOWN,
- HFI_S3D_FP_VIEWORDER_UNUSED = 0x10000000
-};
-
-enum HFI_S3D_FP_FLIP {
- HFI_S3D_FP_FLIP_NONE,
- HFI_S3D_FP_FLIP_LEFT_HORIZ,
- HFI_S3D_FP_FLIP_LEFT_VERT,
- HFI_S3D_FP_FLIP_RIGHT_HORIZ,
- HFI_S3D_FP_FLIP_RIGHT_VERT,
- HFI_S3D_FP_FLIP_UNUSED = 0x10000000
-};
struct hfi_extradata_s3d_frame_packing_payload {
- enum HFI_S3D_FP_LAYOUT layout;
- enum HFI_S3D_FP_VIEW_ORDER order;
- enum HFI_S3D_FP_FLIP flip;
- int quin_cunx;
- u32 left_view_luma_site_x;
- u32 left_view_luma_site_y;
- u32 right_view_luma_site_x;
- u32 right_view_luma_site_y;
+ u32 fpa_id;
+ int cancel_flag;
+ u32 fpa_type;
+ int quin_cunx_flag;
+ u32 content_interprtation_type;
+ int spatial_flipping_flag;
+ int frame0_flipped_flag;
+ int field_views_flag;
+ int current_frame_isFrame0_flag;
+ int frame0_self_contained_flag;
+ int frame1_self_contained_flag;
+ u32 frame0_graid_pos_x;
+ u32 frame0_graid_pos_y;
+ u32 frame1_graid_pos_x;
+ u32 frame1_graid_pos_y;
+ u32 fpa_reserved_byte;
+ u32 fpa_repetition_period;
+ int fpa_extension_flag;
};
struct hfi_extradata_interlace_video_payload {
@@ -813,6 +855,26 @@
int height;
};
+struct hfi_index_extradata_aspect_ratio_payload {
+ u32 size;
+ u32 version;
+ u32 port_index;
+ u32 aspect_width;
+ u32 aspect_height;
+};
+struct hfi_extradata_panscan_wndw_payload {
+ u32 num_window;
+ struct hfi_extradata_vc1_pswnd wnd[1];
+};
+
+struct hfi_extradata_frame_type_payload {
+ u32 frame_rate;
+};
+
+struct hfi_extradata_recovery_point_sei_payload {
+ u32 flag;
+};
+
struct vidc_mem_addr {
u8 *align_device_addr;
u8 *align_virtual_addr;
@@ -842,6 +904,9 @@
spinlock_t write_lock;
void (*callback) (u32 response, void *callback);
struct vidc_mem_addr iface_q_table;
+ struct vidc_mem_addr qdss;
+ struct vidc_mem_addr sfr;
+ struct vidc_mem_addr mem_addr;
struct vidc_iface_q_info iface_queues[VIDC_IFACEQ_NUMQ];
struct smem_client *hal_client;
struct hal_data *hal_data;
@@ -862,14 +927,6 @@
int dev_count;
};
-struct hfi_index_extradata_aspect_ratio_payload {
- u32 size;
- u32 version;
- u32 port_index;
- u32 saspect_width;
- u32 saspect_height;
-};
-
extern struct hal_device_data hal_ctxt;
int vidc_hal_iface_msgq_read(struct hal_device *device, void *pkt);
diff --git a/drivers/media/video/msm_vidc/vidc_hal_api.h b/drivers/media/video/msm_vidc/vidc_hal_api.h
index d3fa1d0..8aff5af 100644
--- a/drivers/media/video/msm_vidc/vidc_hal_api.h
+++ b/drivers/media/video/msm_vidc/vidc_hal_api.h
@@ -814,6 +814,7 @@
SYS_IDLE,
SYS_DEBUG,
SYS_WATCHDOG_TIMEOUT,
+ SYS_ERROR,
/* SESSION COMMANDS_DONE */
SESSION_LOAD_RESOURCE_DONE,
SESSION_INIT_DONE,
@@ -833,6 +834,7 @@
SESSION_RELEASE_BUFFER_DONE,
SESSION_RELEASE_RESOURCE_DONE,
SESSION_PROPERTY_INFO,
+ SESSION_ERROR,
RESPONSE_UNUSED = 0x10000000,
};
diff --git a/drivers/media/video/msm_vidc/vidc_hal_helper.h b/drivers/media/video/msm_vidc/vidc_hal_helper.h
index 43995eb..9412eed 100644
--- a/drivers/media/video/msm_vidc/vidc_hal_helper.h
+++ b/drivers/media/video/msm_vidc/vidc_hal_helper.h
@@ -14,55 +14,6 @@
#ifndef __H_VIDC_HAL_HELPER_H__
#define __H_VIDC_HAL_HELPER_H__
-#define HFI_NV12_IL_CALC_Y_STRIDE(stride, frame_width, stride_multiple) \
- { stride = (frame_width + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1))}
-
-#define HFI_NV12_IL_CALC_Y_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = (frame_height + min_buf_height_multiple - 1) & \
- (0xffffffff - (min_buf_height_multiple - 1)) }
-
-#define HFI_NV12_IL_CALC_UV_STRIDE(stride, frame_width, stride_multiple) \
- { stride = ((((frame_width + 1) >> 1) + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1))) << 1 }
-
-#define HFI_NV12_IL_CALC_UV_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = ((((frame_height + 1) >> 1) + \
- min_buf_height_multiple - 1) & (0xffffffff - \
- (min_buf_height_multiple - 1))) }
-
-#define HFI_NV12_IL_CALC_BUF_SIZE(buf_size, y_buf_size, y_stride, \
- y_buf_height, uv_buf_size, uv_stride, uv_buf_height, uv_alignment) \
- { y_buf_size = (y_stride * y_buf_height); \
- uv_buf_size = (uv_stride * uv_buf_height) + uv_alignment; \
- buf_size = y_buf_size + uv_buf_size }
-
-#define HFI_YUYV_CALC_STRIDE(stride, frame_width, stride_multiple) \
- { stride = ((frame_width << 1) + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1)) }
-
-#define HFI_YUYV_CALC_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = ((frame_height + min_buf_height_multiple - 1) & \
- (0xffffffff - (min_buf_height_multiple - 1))) }
-
-#define HFI_YUYV_CALC_BUF_SIZE(buf_size, stride, buf_height) \
- { buf_size = stride * buf_height }
-
-#define HFI_RGB888_CALC_STRIDE(stride, frame_width, stride_multiple) \
- { stride = ((frame_width * 3) + stride_multiple - 1) & \
- (0xffffffff - (stride_multiple - 1)) }
-
-#define HFI_RGB888_CALC_BUFHEIGHT(buf_height, frame_height,\
- min_buf_height_multiple) \
- { buf_height = ((frame_height + min_buf_height_multiple - 1) & \
- (0xffffffff - (min_buf_height_multiple - 1))) }
-
-#define HFI_RGB888_CALC_BUF_SIZE(buf_size, stride, buf_height) \
- { buf_size = (stride * buf_height) }
-
#define HFI_COMMON_BASE (0)
#define HFI_OX_BASE (0x01000000)
@@ -81,6 +32,9 @@
#define HFI_ARCH_COMMON_OFFSET (0)
#define HFI_ARCH_OX_OFFSET (0x00200000)
+#define HFI_CMD_START_OFFSET (0x00010000)
+#define HFI_MSG_START_OFFSET (0x00020000)
+
#define HFI_ERR_NONE HFI_COMMON_BASE
#define HFI_ERR_SYS_FATAL (HFI_COMMON_BASE + 0x1)
#define HFI_ERR_SYS_INVALID_PARAMETER (HFI_COMMON_BASE + 0x2)
@@ -110,6 +64,7 @@
#define HFI_ERR_SESSION_STREAM_CORRUPT (HFI_COMMON_BASE + 0x100B)
#define HFI_ERR_SESSION_ENC_OVERFLOW (HFI_COMMON_BASE + 0x100C)
+#define HFI_ERR_SESSION_UNSUPPORTED_STREAM (HFI_COMMON_BASE + 0x100D)
#define HFI_EVENT_SYS_ERROR (HFI_COMMON_BASE + 0x1)
#define HFI_EVENT_SESSION_ERROR (HFI_COMMON_BASE + 0x2)
@@ -130,8 +85,8 @@
#define HFI_H264_PROFILE_HIGH 0x00000004
#define HFI_H264_PROFILE_STEREO_HIGH 0x00000008
#define HFI_H264_PROFILE_MULTIVIEW_HIGH 0x00000010
-#define HFI_H264_PROFILE_CONSTRAINED_HIGH 0x00000020
-#define HFI_H264_PROFILE_CONSTRAINED_BASE 0x00000040
+#define HFI_H264_PROFILE_CONSTRAINED_BASE 0x00000020
+#define HFI_H264_PROFILE_CONSTRAINED_HIGH 0x00000040
#define HFI_H264_LEVEL_1 0x00000001
#define HFI_H264_LEVEL_1b 0x00000002
@@ -235,8 +190,11 @@
#define HFI_PROPERTY_SYS_DEBUG_CONFIG \
(HFI_PROPERTY_SYS_COMMON_START + 0x001)
#define HFI_PROPERTY_SYS_RESOURCE_OCMEM_REQUIREMENT_INFO \
-(HFI_PROPERTY_SYS_COMMON_START + 0x002)
-#define HFI_PROPERTY_PARAM_COMMON_START \
+ (HFI_PROPERTY_SYS_COMMON_START + 0x002)
+#define HFI_PROPERTY_SYS_CONFIG_VCODEC_CLKFREQ \
+ (HFI_PROPERTY_SYS_COMMON_START + 0x003)
+
+#define HFI_PROPERTY_PARAM_COMMON_START \
(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
#define HFI_PROPERTY_PARAM_FRAME_SIZE \
(HFI_PROPERTY_PARAM_COMMON_START + 0x001)
@@ -316,16 +274,25 @@
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x00F)
#define HFI_PROPERTY_PARAM_VENC_QUALITY_VS_SPEED \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x010)
-#define HFI_PROPERTY_PARAM_VENC_MPEG4_QPEL \
- (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x011)
#define HFI_PROPERTY_PARAM_VENC_ADVANCED \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x012)
-#define HFI_PROPERTY_PARAM_VENC_SYNC_FRAME_SEQUENCE_HEADER \
- (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x013)
#define HFI_PROPERTY_PARAM_VENC_H264_SPS_ID \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x014)
#define HFI_PROPERTY_PARAM_VENC_H264_PPS_ID \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x015)
+#define HFI_PROPERTY_PARAM_VENC_H264_GENERATE_AUDNAL \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x016)
+#define HFI_PROPERTY_PARAM_VENC_ASPECT_RATIO \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x017)
+#define HFI_PROPERTY_PARAM_VENC_NUMREF \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x018)
+#define HFI_PROPERTY_PARAM_VENC_MULTIREF_P \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x019)
+#define HFI_PROPERTY_PARAM_VENC_HIER_P_NUM_ENH_LAYER \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01A)
+
+#define HFI_PROPERTY_PARAM_VENC_H264_NAL_SVC_EXT \
+ (HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01B)
#define HFI_PROPERTY_CONFIG_VENC_COMMON_START \
(HFI_DOMAIN_BASE_VENC + HFI_ARCH_COMMON_OFFSET + 0x6000)
@@ -339,13 +306,13 @@
(HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x004)
#define HFI_PROPERTY_CONFIG_VENC_SLICE_SIZE \
(HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x005)
-#define HFI_PROPERTY_CONFIG_VENC_FRAME_QP \
- (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x006)
#define HFI_PROPERTY_CONFIG_VENC_MAX_BITRATE \
(HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x007)
#define HFI_PROPERTY_PARAM_VPE_COMMON_START \
(HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x7000)
+#define HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER \
+ (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x008)
#define HFI_PROPERTY_CONFIG_VPE_COMMON_START \
(HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000)
@@ -356,6 +323,7 @@
struct hfi_bitrate {
u32 bit_rate;
+ u32 layer_id;
};
#define HFI_CAPABILITY_FRAME_WIDTH (HFI_COMMON_BASE + 0x1)
@@ -367,7 +335,7 @@
#define HFI_CAPABILITY_SCALE_Y (HFI_COMMON_BASE + 0x7)
#define HFI_CAPABILITY_BITRATE (HFI_COMMON_BASE + 0x8)
#define HFI_CAPABILITY_BFRAME (HFI_COMMON_BASE + 0x9)
-#define HFI_CAPABILITY_HIERARCHICAL_P_LAYERS (HFI_COMMON_BASE + 0x10)
+#define HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS (HFI_COMMON_BASE + 0x10)
struct hfi_capability_supported {
u32 capability_type;
@@ -386,9 +354,14 @@
#define HFI_DEBUG_MSG_HIGH 0x00000004
#define HFI_DEBUG_MSG_ERROR 0x00000008
#define HFI_DEBUG_MSG_FATAL 0x00000010
+#define HFI_DEBUG_MSG_PERF 0x00000020
+
+#define HFI_DEBUG_MODE_QUEUE 0x00000001
+#define HFI_DEBUG_MODE_QDSS 0x00000002
struct hfi_debug_config {
u32 debug_config;
+ u32 debug_mode;
};
struct hfi_enable {
@@ -396,8 +369,9 @@
};
#define HFI_H264_DB_MODE_DISABLE (HFI_COMMON_BASE + 0x1)
-#define HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY (HFI_COMMON_BASE + 0x2)
-#define HFI_H264_DB_MODE_ALL_BOUNDARY (HFI_COMMON_BASE + 0x3)
+#define HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY \
+ (HFI_COMMON_BASE + 0x2)
+#define HFI_H264_DB_MODE_ALL_BOUNDARY (HFI_COMMON_BASE + 0x3)
struct hfi_h264_db_control {
u32 mode;
@@ -465,8 +439,8 @@
};
#define HFI_MULTI_SLICE_OFF (HFI_COMMON_BASE + 0x1)
-#define HFI_MULTI_SLICE_BY_MB_COUNT (HFI_COMMON_BASE + 0x2)
-#define HFI_MULTI_SLICE_BY_BYTE_COUNT (HFI_COMMON_BASE + 0x3)
+#define HFI_MULTI_SLICE_BY_MB_COUNT (HFI_COMMON_BASE + 0x2)
+#define HFI_MULTI_SLICE_BY_BYTE_COUNT (HFI_COMMON_BASE + 0x3)
#define HFI_MULTI_SLICE_GOB (HFI_COMMON_BASE + 0x4)
struct hfi_multi_slice_control {
@@ -654,9 +628,14 @@
struct hfi_seq_header_info {
u32 max_hader_len;
};
+struct hfi_aspect_ratio {
+ u32 aspect_width;
+ u32 aspect_height;
+};
#define HFI_CMD_SYS_COMMON_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x0000)
+(HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + HFI_CMD_START_OFFSET \
+ + 0x0000)
#define HFI_CMD_SYS_INIT (HFI_CMD_SYS_COMMON_START + 0x001)
#define HFI_CMD_SYS_PC_PREP (HFI_CMD_SYS_COMMON_START + 0x002)
#define HFI_CMD_SYS_SET_RESOURCE (HFI_CMD_SYS_COMMON_START + 0x003)
@@ -666,9 +645,11 @@
#define HFI_CMD_SYS_SESSION_INIT (HFI_CMD_SYS_COMMON_START + 0x007)
#define HFI_CMD_SYS_SESSION_END (HFI_CMD_SYS_COMMON_START + 0x008)
#define HFI_CMD_SYS_SET_BUFFERS (HFI_CMD_SYS_COMMON_START + 0x009)
+#define HFI_CMD_SYS_TEST_START (HFI_CMD_SYS_COMMON_START + 0x100)
#define HFI_CMD_SESSION_COMMON_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
+ (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
+ HFI_CMD_START_OFFSET + 0x1000)
#define HFI_CMD_SESSION_SET_PROPERTY \
(HFI_CMD_SESSION_COMMON_START + 0x001)
#define HFI_CMD_SESSION_SET_BUFFERS \
@@ -677,7 +658,8 @@
(HFI_CMD_SESSION_COMMON_START + 0x003)
#define HFI_MSG_SYS_COMMON_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x0000)
+ (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
+ HFI_MSG_START_OFFSET + 0x0000)
#define HFI_MSG_SYS_INIT_DONE (HFI_MSG_SYS_COMMON_START + 0x1)
#define HFI_MSG_SYS_PC_PREP_DONE (HFI_MSG_SYS_COMMON_START + 0x2)
#define HFI_MSG_SYS_RELEASE_RESOURCE (HFI_MSG_SYS_COMMON_START + 0x3)
@@ -686,7 +668,8 @@
#define HFI_MSG_SYS_SESSION_END_DONE (HFI_MSG_SYS_COMMON_START + 0x7)
#define HFI_MSG_SESSION_COMMON_START \
- (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + 0x1000)
+ (HFI_DOMAIN_BASE_COMMON + HFI_ARCH_COMMON_OFFSET + \
+ HFI_MSG_START_OFFSET + 0x1000)
#define HFI_MSG_EVENT_NOTIFY (HFI_MSG_SESSION_COMMON_START + 0x1)
#define HFI_MSG_SESSION_GET_SEQUENCE_HEADER_DONE \
(HFI_MSG_SESSION_COMMON_START + 0x2)
@@ -778,7 +761,6 @@
u32 packet_type;
u32 session_id;
u32 buffer_type;
- u32 buffer_mode;
u32 buffer_size;
u32 extra_data_size;
u32 min_buffer_size;
@@ -860,4 +842,22 @@
u8 rg_msg_data[1];
};
+enum HFI_VENUS_QTBL_STATUS {
+ HFI_VENUS_QTBL_DISABLED = 0x00,
+ HFI_VENUS_QTBL_ENABLED = 0x01,
+ HFI_VENUS_QTBL_INITIALIZING = 0x02,
+ HFI_VENUS_QTBL_DEINITIALIZING = 0x03
+};
+
+enum HFI_VENUS_CTRL_INIT_STATUS {
+ HFI_VENUS_CTRL_NOT_INIT = 0x0,
+ HFI_VENUS_CTRL_READY = 0x1,
+ HFI_VENUS_CTRL_ERROR_FATAL = 0x2
+};
+
+struct hfi_sfr_struct {
+ u32 bufSize;
+ u8 rg_data[1];
+};
+
#endif
diff --git a/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c b/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
index 7eb0ae1..200f5d3 100644
--- a/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
+++ b/drivers/media/video/msm_vidc/vidc_hal_interrupt_handler.c
@@ -146,6 +146,21 @@
cmd_done.device_id = device->device_id;
device->callback(SYS_WATCHDOG_TIMEOUT, &cmd_done);
}
+static void hal_process_sys_error(struct hal_device *device)
+{
+ struct msm_vidc_cb_cmd_done cmd_done;
+ disable_irq_nosync(device->hal_data->irq);
+ memset(&cmd_done, 0, sizeof(struct msm_vidc_cb_cmd_done));
+ cmd_done.device_id = device->device_id;
+ device->callback(SYS_ERROR, &cmd_done);
+}
+static void hal_process_session_error(struct hal_device *device)
+{
+ struct msm_vidc_cb_cmd_done cmd_done;
+ memset(&cmd_done, 0, sizeof(struct msm_vidc_cb_cmd_done));
+ cmd_done.device_id = device->device_id;
+ device->callback(SESSION_ERROR, &cmd_done);
+}
static void hal_process_event_notify(struct hal_device *device,
struct hfi_msg_event_notify_packet *pkt)
{
@@ -160,10 +175,11 @@
switch (pkt->event_id) {
case HFI_EVENT_SYS_ERROR:
dprintk(VIDC_INFO, "HFI_EVENT_SYS_ERROR");
- hal_process_sys_watchdog_timeout(device);
+ hal_process_sys_error(device);
break;
case HFI_EVENT_SESSION_ERROR:
dprintk(VIDC_INFO, "HFI_EVENT_SESSION_ERROR");
+ hal_process_session_error(device);
break;
case HFI_EVENT_SESSION_SEQUENCE_CHANGED:
dprintk(VIDC_INFO, "HFI_EVENT_SESSION_SEQUENCE_CHANGED");
@@ -299,16 +315,22 @@
{
struct hfi_buffer_requirements *hfi_buf_req;
u32 req_bytes;
- enum vidc_status rc = VIDC_ERR_NONE;
dprintk(VIDC_DBG, "Entered ");
+ if (!prop) {
+ dprintk(VIDC_ERR,
+ "hal_process_sess_get_prop_buf_req:bad_prop: %p",
+ prop);
+ return;
+ }
req_bytes = prop->size - sizeof(
struct hfi_msg_session_property_info_packet);
- if (req_bytes == 0 || (req_bytes % sizeof(
- struct hfi_buffer_requirements))) {
+ if (!req_bytes || (req_bytes % sizeof(
+ struct hfi_buffer_requirements)) ||
+ (!prop->rg_property_data[1])) {
dprintk(VIDC_ERR,
- "hal_process_sess_get_prop_buf_req:bad_pkt_size: %d",
+ "hal_process_sess_get_prop_buf_req:bad_pkt: %d",
req_bytes);
return;
}
@@ -316,15 +338,14 @@
hfi_buf_req = (struct hfi_buffer_requirements *)
&prop->rg_property_data[1];
- while (req_bytes != 0) {
- if ((hfi_buf_req->buffer_count_min > hfi_buf_req->
- buffer_count_actual)
- || (hfi_buf_req->buffer_alignment == 0)
- || (hfi_buf_req->buffer_size == 0)) {
- dprintk(VIDC_ERR, "hal_process_sess_get_prop_buf_req:"
- "bad_buf_req");
- rc = VIDC_ERR_FAIL;
- }
+ while (req_bytes) {
+ if ((hfi_buf_req->buffer_size) &&
+ ((hfi_buf_req->buffer_count_min > hfi_buf_req->
+ buffer_count_actual)))
+ dprintk(VIDC_WARN,
+ "hal_process_sess_get_prop_buf_req:"
+ "bad_buf_req");
+
dprintk(VIDC_DBG, "got buffer requirements for: %d",
hfi_buf_req->buffer_type);
switch (hfi_buf_req->buffer_type) {
diff --git a/drivers/media/video/msm_vidc/vidc_hal_io.h b/drivers/media/video/msm_vidc/vidc_hal_io.h
index b85e015..9888adb 100644
--- a/drivers/media/video/msm_vidc/vidc_hal_io.h
+++ b/drivers/media/video/msm_vidc/vidc_hal_io.h
@@ -22,6 +22,12 @@
#define VIDC_VBIF_BASE_OFFS 0x00080000
#define VIDC_VBIF_VERSION (VIDC_VBIF_BASE_OFFS + 0x00)
+#define VIDC_VENUS_VBIF_DDR_OUT_MAX_BURST \
+ (VIDC_VBIF_BASE_OFFS + 0xD8)
+#define VIDC_VENUS_VBIF_OCMEM_OUT_MAX_BURST \
+ (VIDC_VBIF_BASE_OFFS + 0xDC)
+#define VIDC_VENUS_VBIF_ROUND_ROBIN_QOS_ARB \
+ (VIDC_VBIF_BASE_OFFS + 0x124)
#define VIDC_CPU_BASE_OFFS 0x000C0000
#define VIDC_CPU_CS_BASE_OFFS (VIDC_CPU_BASE_OFFS + 0x00012000)
@@ -128,7 +134,42 @@
(VIDC_WRAPPER_BASE_OFFS + 0x20)
#define VIDC_VENUS0_WRAPPER_VBIF_PRIORITY_LEVEL \
(VIDC_WRAPPER_BASE_OFFS + 0x24)
-#define VIDC_VENUS_VBIF_REQ_PRIORITY (VIDC_WRAPPER_BASE_OFFS + 0x20)
-#define VIDC_VENUS_VBIF_PRIORITY_LEVEL (VIDC_WRAPPER_BASE_OFFS + 0x24)
+
+#define VIDC_CTRL_INIT 0x000D2048
+#define VIDC_CTRL_INIT_RESERVED_BITS31_1__M 0xFFFFFFFE
+#define VIDC_CTRL_INIT_RESERVED_BITS31_1__S 1
+#define VIDC_CTRL_INIT_CTRL__M 0x00000001
+#define VIDC_CTRL_INIT_CTRL__S 0
+
+#define VIDC_CTRL_STATUS 0x000D204C
+#define VIDC_CTRL_STATUS_RESERVED_BITS31_8__M 0xFFFFFF00
+#define VIDC_CTRL_STATUS_RESERVED_BITS31_8__S 8
+#define VIDC_CTRL_ERROR_STATUS__M 0x000000FE
+#define VIDC_CTRL_ERROR_STATUS__S 1
+#define VIDC_CTRL_INIT_STATUS__M 0x00000001
+#define VIDC_CTRL_INIT_STATUS__S 0
+
+#define VIDC_QTBL_INFO 0x000D2050
+#define VIDC_QTBL_HOSTID__M 0xFF000000
+#define VIDC_QTBL_HOSTID__S 24
+#define VIDC_QTBL_INFO_RESERVED_BITS23_8__M 0x00FFFF00
+#define VIDC_QTBL_INFO_RESERVED_BITS23_8__S 8
+#define VIDC_QTBL_STATUS__M 0x000000FF
+#define VIDC_QTBL_STATUS__S 0
+
+#define VIDC_QTBL_ADDR 0x000D2054
+
+#define VIDC_VERSION_INFO 0x000D2058
+#define VIDC_VERSION_INFO_MAJOR__M 0xF0000000
+#define VIDC_VERSION_INFO_MAJOR__S 28
+#define VIDC_VERSION_INFO_MINOR__M 0x0FFFFFE0
+#define VIDC_VERSION_INFO_MINOR__S 5
+#define VIDC_VERSION_INFO_BRANCH__M 0x0000001F
+#define VIDC_VERSION_INFO_BRANCH__S 0
+
+#define VIDC_SFR_ADDR 0x000D205C
+#define VIDC_MMAP_ADDR 0x000D2060
+#define VIDC_UC_REGION_ADDR 0x000D2064
+#define VIDC_UC_REGION_SIZE 0x000D2068
#endif
diff --git a/drivers/media/video/msm_wfd/enc-mfc-subdev.c b/drivers/media/video/msm_wfd/enc-mfc-subdev.c
index 09a5e32..d839be3 100644
--- a/drivers/media/video/msm_wfd/enc-mfc-subdev.c
+++ b/drivers/media/video/msm_wfd/enc-mfc-subdev.c
@@ -194,6 +194,9 @@
break;
}
+ if (frame_data->flags & VCD_FRAME_FLAG_CODECCONFIG)
+ vbuf->v4l2_buf.flags |= V4L2_QCOM_BUF_FLAG_CODECCONFIG;
+
vbuf->v4l2_buf.timestamp =
ns_to_timeval(frame_data->time_stamp * NSEC_PER_USEC);
@@ -1975,6 +1978,7 @@
unsigned long phy_addr;
int i = 0;
int heap_mask = 0;
+ u32 ion_flags = 0;
u32 len;
control.width = inst->width;
control.height = inst->height;
@@ -1988,7 +1992,8 @@
goto err;
}
heap_mask = ION_HEAP(ION_CP_MM_HEAP_ID);
- heap_mask |= inst->secure ? ION_SECURE : ION_HEAP(ION_IOMMU_HEAP_ID);
+ heap_mask |= inst->secure ? 0 : ION_HEAP(ION_IOMMU_HEAP_ID);
+ ion_flags |= inst->secure ? ION_SECURE : 0;
if (vcd_get_ion_status()) {
for (i = 0; i < 4; ++i) {
@@ -1999,7 +2004,7 @@
ctrl->user_virtual_addr = (void *)i;
client_ctx->recon_buffer_ion_handle[i]
= ion_alloc(client_ctx->user_ion_client,
- control.size, SZ_8K, heap_mask, 0);
+ control.size, SZ_8K, heap_mask, ion_flags);
ctrl->kernel_virtual_addr = ion_map_kernel(
client_ctx->user_ion_client,
diff --git a/drivers/media/video/msm_wfd/enc-venus-subdev.c b/drivers/media/video/msm_wfd/enc-venus-subdev.c
index 89ad6c7..150c667 100644
--- a/drivers/media/video/msm_wfd/enc-venus-subdev.c
+++ b/drivers/media/video/msm_wfd/enc-venus-subdev.c
@@ -178,7 +178,7 @@
rc = msm_vidc_dqbuf(inst->vidc_context, &buffer);
if (rc) {
- WFD_MSG_ERR("Error dequeuing buffer" \
+ WFD_MSG_ERR("Error dequeuing buffer " \
"from vidc: %d", rc);
goto abort_dequeue;
}
@@ -1010,7 +1010,8 @@
inst = (struct venc_inst *)sd->dev_priv;
enc_cmd.cmd = V4L2_ENC_QCOM_CMD_FLUSH;
- enc_cmd.flags = BUF_TYPE_INPUT | BUF_TYPE_OUTPUT;
+ enc_cmd.flags = V4L2_QCOM_CMD_FLUSH_OUTPUT |
+ V4L2_QCOM_CMD_FLUSH_CAPTURE;
msm_vidc_encoder_cmd(inst->vidc_context, &enc_cmd);
wait_for_completion(&inst->cmd_complete);
diff --git a/drivers/media/video/msm_wfd/wfd-ioctl.c b/drivers/media/video/msm_wfd/wfd-ioctl.c
index d8080dd..5f67a96 100644
--- a/drivers/media/video/msm_wfd/wfd-ioctl.c
+++ b/drivers/media/video/msm_wfd/wfd-ioctl.c
@@ -155,13 +155,15 @@
struct ion_handle *handle = NULL;
void *kvaddr = NULL;
unsigned int alloc_regions = 0;
+ unsigned int ion_flags = 0;
int rc = 0;
alloc_regions = ION_HEAP(ION_CP_MM_HEAP_ID);
- alloc_regions |= secure ? ION_SECURE :
+ alloc_regions |= secure ? 0 :
ION_HEAP(ION_IOMMU_HEAP_ID);
+ ion_flags |= secure ? ION_SECURE : 0;
handle = ion_alloc(client,
- mregion->size, SZ_4K, alloc_regions, 0);
+ mregion->size, SZ_4K, alloc_regions, ion_flags);
if (IS_ERR_OR_NULL(handle)) {
WFD_MSG_ERR("Failed to allocate input buffer\n");
@@ -269,8 +271,9 @@
goto alloc_fail;
}
- WFD_MSG_ERR("NOTE: enc paddr = %p, kvaddr = %p\n",
- enc_mregion->paddr,
+ WFD_MSG_DBG("NOTE: enc paddr = [%p->%p], kvaddr = %p\n",
+ enc_mregion->paddr, (int8_t *)
+ enc_mregion->paddr + enc_mregion->size,
enc_mregion->kvaddr);
rc = v4l2_subdev_call(&wfd_dev->enc_sdev, core, ioctl,
diff --git a/drivers/media/video/msm_wfd/wfd-util.c b/drivers/media/video/msm_wfd/wfd-util.c
index 233668b0..5c00e5c 100644
--- a/drivers/media/video/msm_wfd/wfd-util.c
+++ b/drivers/media/video/msm_wfd/wfd-util.c
@@ -159,10 +159,10 @@
}
case WFD_STAT_EVENT_MDP_QUEUE:
stats->mdp_buf_count++;
- stats->mdp_updates++;
break;
case WFD_STAT_EVENT_MDP_DEQUEUE:
stats->mdp_buf_count--;
+ stats->mdp_updates++;
break;
case WFD_STAT_EVENT_ENC_QUEUE: {
struct wfd_stats_encode_sample *sample = NULL;
diff --git a/drivers/media/video/vcap_v4l2.c b/drivers/media/video/vcap_v4l2.c
index 72a3f3b..f009e06 100644
--- a/drivers/media/video/vcap_v4l2.c
+++ b/drivers/media/video/vcap_v4l2.c
@@ -82,7 +82,7 @@
static int vcap_reg_powerup(struct vcap_dev *dev)
{
- dev->fs_vcap = regulator_get(NULL, "fs_vcap");
+ dev->fs_vcap = regulator_get(dev->ddev, "fs_vcap");
if (IS_ERR(dev->fs_vcap)) {
pr_err("%s: Regulator FS_VCAP get failed %ld\n", __func__,
PTR_ERR(dev->fs_vcap));
@@ -569,6 +569,17 @@
}
/* VC Videobuf operations */
+static void wait_prepare(struct vb2_queue *q)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(q);
+ mutex_unlock(&c_data->mutex);
+}
+
+static void wait_finish(struct vb2_queue *q)
+{
+ struct vcap_client_data *c_data = vb2_get_drv_priv(q);
+ mutex_lock(&c_data->mutex);
+}
static int capture_queue_setup(struct vb2_queue *vq,
const struct v4l2_format *fmt,
@@ -651,6 +662,8 @@
static struct vb2_ops capture_video_qops = {
.queue_setup = capture_queue_setup,
+ .wait_finish = wait_finish,
+ .wait_prepare = wait_prepare,
.buf_init = capture_buffer_init,
.buf_prepare = capture_buffer_prepare,
.buf_queue = capture_buffer_queue,
@@ -749,6 +762,8 @@
static struct vb2_ops vp_in_video_qops = {
.queue_setup = vp_in_queue_setup,
+ .wait_finish = wait_finish,
+ .wait_prepare = wait_prepare,
.buf_init = vp_in_buffer_init,
.buf_prepare = vp_in_buffer_prepare,
.buf_queue = vp_in_buffer_queue,
@@ -847,6 +862,8 @@
static struct vb2_ops vp_out_video_qops = {
.queue_setup = vp_out_queue_setup,
+ .wait_finish = wait_finish,
+ .wait_prepare = wait_prepare,
.buf_init = vp_out_buffer_init,
.buf_prepare = vp_out_buffer_prepare,
.buf_queue = vp_out_buffer_queue,
@@ -905,10 +922,15 @@
case VC_TYPE:
vc_format = (struct v4l2_format_vc_ext *) &priv_fmt->u.timing;
c_data->vc_format = *vc_format;
+ c_data->stride = priv_fmt->stride;
size = (c_data->vc_format.hactive_end -
c_data->vc_format.hactive_start);
- size = VCAP_STRIDE_CALC(size);
+ if (c_data->stride == VC_STRIDE_32)
+ size = VCAP_STRIDE_CALC(size, VCAP_STRIDE_ALIGN_32);
+ else
+ size = VCAP_STRIDE_CALC(size, VCAP_STRIDE_ALIGN_16);
+
if (c_data->vc_format.color_space)
size *= 3;
@@ -1072,7 +1094,9 @@
rc = get_phys_addr(c_data->dev, &c_data->vc_vidq, p);
if (rc < 0)
return rc;
+ mutex_lock(&c_data->mutex);
rc = vb2_qbuf(&c_data->vc_vidq, p);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
free_ion_handle(c_data, &c_data->vc_vidq, p);
return rc;
@@ -1082,7 +1106,9 @@
rc = get_phys_addr(c_data->dev, &c_data->vp_in_vidq, p);
if (rc < 0)
return rc;
+ mutex_lock(&c_data->mutex);
rc = vb2_qbuf(&c_data->vp_in_vidq, p);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
free_ion_handle(c_data, &c_data->vp_in_vidq, p);
return rc;
@@ -1090,7 +1116,9 @@
rc = get_phys_addr(c_data->dev, &c_data->vp_out_vidq, p);
if (rc < 0)
return rc;
+ mutex_lock(&c_data->mutex);
rc = vb2_qbuf(&c_data->vp_out_vidq, p);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
free_ion_handle(c_data, &c_data->vp_out_vidq, p);
return rc;
@@ -1114,21 +1142,27 @@
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
if (c_data->op_mode == VC_AND_VP_VCAP_OP)
return -EINVAL;
+ mutex_lock(&c_data->mutex);
rc = vb2_dqbuf(&c_data->vc_vidq, p, file->f_flags & O_NONBLOCK);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
return rc;
return free_ion_handle(c_data, &c_data->vc_vidq, p);
case V4L2_BUF_TYPE_INTERLACED_IN_DECODER:
if (c_data->op_mode == VC_AND_VP_VCAP_OP)
return -EINVAL;
+ mutex_lock(&c_data->mutex);
rc = vb2_dqbuf(&c_data->vp_in_vidq, p, file->f_flags &
O_NONBLOCK);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
return rc;
return free_ion_handle(c_data, &c_data->vp_in_vidq, p);
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ mutex_lock(&c_data->mutex);
rc = vb2_dqbuf(&c_data->vp_out_vidq, p, file->f_flags &
O_NONBLOCK);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
return rc;
return free_ion_handle(c_data, &c_data->vp_out_vidq, p);
@@ -1488,8 +1522,10 @@
dev->vc_resource = 0;
mutex_unlock(&dev->dev_mutex);
c_data->streaming = 0;
+ mutex_lock(&c_data->mutex);
rc = vb2_streamoff(&c_data->vc_vidq,
V4L2_BUF_TYPE_VIDEO_CAPTURE);
+ mutex_unlock(&c_data->mutex);
if (rc >= 0)
atomic_set(&c_data->dev->vc_enabled, 0);
return rc;
@@ -1515,14 +1551,18 @@
return rc;
c_data->streaming = 0;
+ mutex_unlock(&dev->dev_mutex);
/* These stream on calls should not fail */
rc = vb2_streamoff(&c_data->vp_in_vidq,
V4L2_BUF_TYPE_INTERLACED_IN_DECODER);
- if (rc < 0)
+ if (rc < 0) {
+ mutex_unlock(&c_data->mutex);
return rc;
+ }
rc = vb2_streamoff(&c_data->vp_out_vidq,
V4L2_BUF_TYPE_VIDEO_OUTPUT);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
return rc;
@@ -1557,20 +1597,26 @@
if (rc < 0)
return rc;
- /* These stream on calls should not fail */
c_data->streaming = 0;
+ mutex_lock(&c_data->mutex);
+ /* These stream on calls should not fail */
rc = vb2_streamoff(&c_data->vc_vidq,
V4L2_BUF_TYPE_VIDEO_CAPTURE);
- if (rc < 0)
+ if (rc < 0) {
+ mutex_unlock(&c_data->mutex);
return rc;
+ }
rc = vb2_streamoff(&c_data->vp_in_vidq,
V4L2_BUF_TYPE_INTERLACED_IN_DECODER);
- if (rc < 0)
+ if (rc < 0) {
+ mutex_unlock(&c_data->mutex);
return rc;
+ }
rc = vb2_streamoff(&c_data->vp_out_vidq,
V4L2_BUF_TYPE_VIDEO_OUTPUT);
+ mutex_unlock(&c_data->mutex);
if (rc < 0)
return rc;
@@ -1716,6 +1762,7 @@
c_data->dev = dev;
spin_lock_init(&c_data->cap_slock);
+ mutex_init(&c_data->mutex);
/* initialize vc queue */
q = &c_data->vc_vidq;
@@ -1799,6 +1846,7 @@
vp_in_q_failed:
vb2_queue_release(&c_data->vc_vidq);
vc_q_failed:
+ mutex_destroy(&c_data->mutex);
kfree(c_data);
return ret;
}
@@ -1833,6 +1881,7 @@
c_data->dev->vc_client = NULL;
if (c_data->dev->vp_client == c_data)
c_data->dev->vp_client = NULL;
+ mutex_destroy(&c_data->mutex);
kfree(c_data);
return 0;
}
@@ -2267,7 +2316,7 @@
ret = request_irq(dev->vcirq->start, vcap_vc_handler,
- IRQF_TRIGGER_RISING, "vc_irq", 0);
+ IRQF_TRIGGER_HIGH, "vc_irq", 0);
if (ret < 0) {
pr_err("%s: vc irq request fail\n", __func__);
ret = -EBUSY;
diff --git a/drivers/media/video/vcap_vc.c b/drivers/media/video/vcap_vc.c
index f3c9362..642074f 100644
--- a/drivers/media/video/vcap_vc.c
+++ b/drivers/media/video/vcap_vc.c
@@ -37,7 +37,10 @@
} else {
int size = (c_data->vc_format.hactive_end -
c_data->vc_format.hactive_start);
- size = VCAP_STRIDE_CALC(size);
+ if (c_data->stride == VC_STRIDE_32)
+ size = VCAP_STRIDE_CALC(size, VCAP_STRIDE_ALIGN_32);
+ else
+ size = VCAP_STRIDE_CALC(size, VCAP_STRIDE_ALIGN_16);
size *= (c_data->vc_format.vactive_end -
c_data->vc_format.vactive_start);
writel_relaxed(buf->paddr, y_addr);
@@ -126,28 +129,9 @@
return tv;
}
-irqreturn_t vc_handler(struct vcap_dev *dev)
+inline void vc_isr_error_checking(struct vcap_dev *dev,
+ struct v4l2_event v4l2_evt, uint32_t irq)
{
- uint32_t irq, timestamp;
- struct vcap_buffer *buf;
- struct vb2_buffer *vb = NULL;
- struct vcap_client_data *c_data;
- struct v4l2_event v4l2_evt;
- uint8_t i, idx, buf_num, tot, done_count = 0;
- bool work_todo = false;
-
- irq = readl_relaxed(VCAP_VC_INT_STATUS);
-
- pr_debug("%s: irq=0x%08x\n", __func__, irq);
-
- c_data = dev->vc_client;
- if (!c_data->streaming) {
- writel_iowmb(irq, VCAP_VC_INT_CLEAR);
- pr_err("VC no longer streaming\n");
- return IRQ_HANDLED;
- }
-
- v4l2_evt.id = 0;
if (irq & 0x8000200) {
writel_iowmb(0x00000102, VCAP_VC_NPL_CTRL);
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
@@ -166,6 +150,12 @@
VCAP_VC_VSYNC_ERR_EVENT;
v4l2_event_queue(dev->vfd, &v4l2_evt);
}
+ if (irq & 0x00001000) {
+ writel_iowmb(0x00000102, VCAP_VC_NPL_CTRL);
+ v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
+ VCAP_VC_VSYNC_SEQ_ERR;
+ v4l2_event_queue(dev->vfd, &v4l2_evt);
+ }
if (irq & 0x00000800) {
writel_iowmb(0x00000102, VCAP_VC_NPL_CTRL);
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
@@ -178,33 +168,26 @@
VCAP_VC_LBUF_OFLOW_ERR_EVENT;
v4l2_event_queue(dev->vfd, &v4l2_evt);
}
+}
- if (!(irq & VC_BUFFER_MASK)) {
- writel_relaxed(irq, VCAP_VC_INT_CLEAR);
- pr_err("VC IRQ shows some error\n");
- return IRQ_HANDLED;
- }
-
- if (dev->vc_client == NULL) {
- /* This should never happen */
- writel_relaxed(irq, VCAP_VC_INT_CLEAR);
- pr_err("VC: There is no active vc client\n");
- return IRQ_HANDLED;
- }
- c_data = dev->vc_client;
-
+inline uint8_t vc_isr_buffer_done_count(struct vcap_dev *dev,
+ struct vcap_client_data *c_data, uint32_t irq)
+{
+ int i;
+ uint8_t done_count = 0;
for (i = 0; i < VCAP_VC_MAX_BUF; i++) {
if (0x2 & (irq >> i))
done_count++;
}
+ return done_count;
+}
- /* Assign field value in case somehow got out of sync */
- if (c_data->vc_format.mode == HAL_VCAP_MODE_INT && done_count == 1)
- c_data->vc_action.top_field = !(irq & 0x1);
-
+inline bool vc_isr_verify_expect_buf_rdy(struct vcap_dev *dev,
+ struct vcap_client_data *c_data, struct v4l2_event v4l2_evt,
+ uint32_t irq, uint8_t done_count, uint8_t tot, uint8_t buf_num)
+{
+ int i;
/* Double check expected buffers are done */
- buf_num = c_data->vc_action.buf_num;
- tot = c_data->vc_action.tot_buf;
for (i = 0; i < done_count; i++) {
if (!(irq & (0x1 << (((buf_num + i) % tot) + 1)))) {
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
@@ -213,12 +196,17 @@
pr_debug("Unexpected buffer done\n");
c_data->vc_action.buf_num =
correct_buf_num(irq) % tot;
- writel_relaxed(irq, VCAP_VC_INT_CLEAR);
- return IRQ_HANDLED;
+ return true;
}
}
+ return false;
+}
- /* If here we know which buffers are done */
+inline void vc_isr_update_timestamp(struct vcap_dev *dev,
+ struct vcap_client_data *c_data)
+{
+ uint32_t timestamp;
+
timestamp = readl_relaxed(VCAP_VC_TIMESTAMP);
if (timestamp < c_data->vc_action.last_ts) {
c_data->vc_action.vc_ts.tv_usec +=
@@ -234,65 +222,142 @@
c_data->vc_action.vc_ts.tv_usec =
c_data->vc_action.vc_ts.tv_usec % VCAP_USEC;
c_data->vc_action.last_ts = timestamp;
+}
- c_data->vc_action.buf_num = (buf_num + done_count) % tot;
+inline void vc_isr_no_new_buffer(struct vcap_dev *dev,
+ struct vcap_client_data *c_data, struct v4l2_event v4l2_evt)
+{
+ v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
+ VCAP_VC_BUF_OVERWRITE_EVENT;
+ v4l2_event_queue(dev->vfd, &v4l2_evt);
+
+ c_data->vc_action.field_dropped =
+ !c_data->vc_action.field_dropped;
+
+ c_data->vc_action.field1 =
+ !c_data->vc_action.field1;
+ atomic_inc(&dev->dbg_p.vc_drop_count);
+}
+
+inline void vc_isr_switch_buffers(struct vcap_dev *dev,
+ struct vcap_client_data *c_data, struct vcap_buffer *buf,
+ struct vb2_buffer *vb, uint8_t idx, int done_count, int i)
+{
+ /* Config vc with this new buffer */
+ config_buffer(c_data, buf, VCAP_VC_Y_ADDR_1 + 0x8 * idx,
+ VCAP_VC_C_ADDR_1 + 0x8 * idx);
+ vb->v4l2_buf.timestamp = interpolate_ts(
+ c_data->vc_action.vc_ts,
+ 1000000 / c_data->vc_format.frame_rate *
+ (done_count - 1 - i));
+ if (c_data->vc_format.mode == HAL_VCAP_MODE_INT) {
+ if (c_data->vc_action.field1)
+ vb->v4l2_buf.field = V4L2_FIELD_TOP;
+ else
+ vb->v4l2_buf.field = V4L2_FIELD_BOTTOM;
+
+ c_data->vc_action.field1 =
+ !c_data->vc_action.field1;
+ }
+ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
+ c_data->vc_action.buf[idx] = buf;
+}
+
+inline bool vc_isr_change_buffers(struct vcap_dev *dev,
+ struct vcap_client_data *c_data, struct v4l2_event v4l2_evt,
+ int done_count, uint8_t tot, uint8_t buf_num)
+{
+ struct vb2_buffer *vb = NULL;
+ struct vcap_buffer *buf;
+ bool schedule_work = false;
+ uint8_t idx;
+ int i;
+
for (i = 0; i < done_count; i++) {
idx = (buf_num + i) % tot;
vb = &c_data->vc_action.buf[idx]->vb;
spin_lock(&c_data->cap_slock);
if (list_empty(&c_data->vc_action.active)) {
spin_unlock(&c_data->cap_slock);
- v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
- VCAP_VC_BUF_OVERWRITE_EVENT;
- v4l2_event_queue(dev->vfd, &v4l2_evt);
- c_data->vc_action.top_field =
- !c_data->vc_action.top_field;
-
- if (c_data->vc_format.mode == HAL_VCAP_MODE_INT)
- c_data->vc_action.field_dropped =
- !c_data->vc_action.field_dropped;
-
- atomic_inc(&dev->dbg_p.vc_drop_count);
+ vc_isr_no_new_buffer(dev, c_data, v4l2_evt);
continue;
}
if (c_data->vc_format.mode == HAL_VCAP_MODE_INT &&
c_data->vc_action.field_dropped) {
spin_unlock(&c_data->cap_slock);
- c_data->vc_action.field_dropped =
- !c_data->vc_action.field_dropped;
- c_data->vc_action.top_field =
- !c_data->vc_action.top_field;
- atomic_inc(&dev->dbg_p.vc_drop_count);
+ vc_isr_no_new_buffer(dev, c_data, v4l2_evt);
continue;
}
buf = list_entry(c_data->vc_action.active.next,
struct vcap_buffer, list);
list_del(&buf->list);
spin_unlock(&c_data->cap_slock);
- /* Config vc with this new buffer */
- config_buffer(c_data, buf, VCAP_VC_Y_ADDR_1 + 0x8 * idx,
- VCAP_VC_C_ADDR_1 + 0x8 * idx);
- vb->v4l2_buf.timestamp = interpolate_ts(
- c_data->vc_action.vc_ts,
- 1000000 / c_data->vc_format.frame_rate *
- (done_count - 1 - i));
- if (c_data->vc_format.mode == HAL_VCAP_MODE_INT) {
- if (c_data->vc_action.top_field)
- vb->v4l2_buf.field = V4L2_FIELD_TOP;
- else
- vb->v4l2_buf.field = V4L2_FIELD_BOTTOM;
- c_data->vc_action.top_field =
- !c_data->vc_action.top_field;
- }
- vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
- work_todo = true;
- c_data->vc_action.buf[idx] = buf;
+ vc_isr_switch_buffers(dev, c_data, buf, vb, idx, done_count, i);
+ schedule_work = true;
+ }
+ return schedule_work;
+}
+
+irqreturn_t vc_handler(struct vcap_dev *dev)
+{
+ uint32_t irq;
+ struct vcap_client_data *c_data;
+ struct v4l2_event v4l2_evt;
+ uint8_t done_count = 0, buf_num, tot;
+ bool schedule_work = false;
+
+ v4l2_evt.id = 0;
+ irq = readl_relaxed(VCAP_VC_INT_STATUS);
+ writel_relaxed(irq, VCAP_VC_INT_CLEAR);
+
+ pr_debug("%s: irq=0x%08x\n", __func__, irq);
+
+ if (dev->vc_client == NULL) {
+ /* This should never happen */
+ pr_err("VC: There is no active vc client\n");
+ return IRQ_HANDLED;
}
- if (work_todo && c_data->op_mode == VC_AND_VP_VCAP_OP)
+ c_data = dev->vc_client;
+ if (!c_data->streaming) {
+ pr_err("VC no longer streaming\n");
+ return IRQ_HANDLED;
+ }
+
+ if (irq == VC_VSYNC_MASK) {
+ if (c_data->vc_format.mode == HAL_VCAP_MODE_INT)
+ c_data->vc_action.field1 = irq & 0x1;
+ return IRQ_HANDLED;
+ }
+
+ if (irq & VC_ERR_MASK) {
+ vc_isr_error_checking(dev, v4l2_evt, irq);
+ return IRQ_HANDLED;
+ }
+
+ if (!(irq & VC_BUFFER_MASK)) {
+ pr_debug("No frames done\n");
+ return IRQ_HANDLED;
+ }
+
+ done_count = vc_isr_buffer_done_count(dev, c_data, irq);
+ buf_num = c_data->vc_action.buf_num;
+ tot = c_data->vc_action.tot_buf;
+
+ if (vc_isr_verify_expect_buf_rdy(dev, c_data,
+ v4l2_evt, irq, done_count, tot, buf_num))
+ return IRQ_HANDLED;
+
+ vc_isr_update_timestamp(dev, c_data);
+
+ c_data->vc_action.buf_num = (buf_num + done_count) % tot;
+
+ schedule_work = vc_isr_change_buffers(dev, c_data, v4l2_evt,
+ done_count, tot, buf_num);
+
+ if (schedule_work && c_data->op_mode == VC_AND_VP_VCAP_OP)
queue_work(dev->vcap_wq, &dev->vc_to_vp_work.work);
- writel_relaxed(irq, VCAP_VC_INT_CLEAR);
return IRQ_HANDLED;
}
@@ -362,6 +427,8 @@
rc = 0;
for (i = 0; i < c_data->vc_action.tot_buf; i++)
rc = rc << 1 | 0x2;
+ rc |= VC_ERR_MASK;
+ rc |= VC_VSYNC_MASK;
writel_relaxed(rc, VCAP_VC_INT_MASK);
enable_irq(dev->vcirq->start);
@@ -463,7 +530,10 @@
writel_iowmb(0x000033FF, VCAP_VC_BUF_CTRL);
rc = vc_format->hactive_end - vc_format->hactive_start;
- rc = VCAP_STRIDE_CALC(rc);
+ if (c_data->stride == VC_STRIDE_32)
+ rc = VCAP_STRIDE_CALC(rc, VCAP_STRIDE_ALIGN_32);
+ else
+ rc = VCAP_STRIDE_CALC(rc, VCAP_STRIDE_ALIGN_16);
if (vc_format->color_space)
rc *= 3;
diff --git a/drivers/media/video/vcap_vc.h b/drivers/media/video/vcap_vc.h
index 7f42c7f..9c3f5a7 100644
--- a/drivers/media/video/vcap_vc.h
+++ b/drivers/media/video/vcap_vc.h
@@ -63,6 +63,8 @@
#define VC_BUFFER_WRITTEN (0x3 << 1)
#define VC_BUFFER_MASK 0x7E
+#define VC_ERR_MASK 0xE0001E00
+#define VC_VSYNC_MASK 0x1
int vc_start_capture(struct vcap_client_data *c_data);
int vc_hw_kick_off(struct vcap_client_data *c_data);
diff --git a/drivers/media/video/vcap_vp.c b/drivers/media/video/vcap_vp.c
index 57813f5..5161b7b 100644
--- a/drivers/media/video/vcap_vp.c
+++ b/drivers/media/video/vcap_vp.c
@@ -267,7 +267,7 @@
}
/* Config VP */
- if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_TOP)
+ if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_BOTTOM)
top_field = 1;
writel_iowmb(0x00000000 | top_field, VCAP_VP_CTRL);
@@ -396,6 +396,7 @@
if (rc == 0 && atomic_read(&dev->vp_enabled) == 1) {
/* This should not happen, if it does hw is stuck */
disable_irq_nosync(dev->vpirq->start);
+ atomic_set(&dev->vp_enabled, 0);
pr_err("%s: VP Timeout and VP still running\n",
__func__);
}
@@ -832,7 +833,7 @@
chroma_fmt << 11 | 0x1 << 4, VCAP_VP_OUT_CONFIG);
/* Enable Interrupt */
- if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_TOP)
+ if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_BOTTOM)
top_field = 1;
vp_act->vp_state = VP_FRAME2;
writel_relaxed(0x01100001, VCAP_VP_INTERRUPT_ENABLE);
@@ -875,7 +876,7 @@
if (rc < 0)
return rc;
- if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_TOP)
+ if (vp_act->bufT2->vb.v4l2_buf.field == V4L2_FIELD_BOTTOM)
top_field = 1;
/* Config VP & Enable Interrupt */
diff --git a/drivers/mfd/marimba-core.c b/drivers/mfd/marimba-core.c
index d84bb7b..26f3ece 100644
--- a/drivers/mfd/marimba-core.c
+++ b/drivers/mfd/marimba-core.c
@@ -857,8 +857,7 @@
ssbi_adap = NULL;
if (!marimba->client) {
- dev_err(&marimba->client->dev,
- "can't attach client %d\n", i);
+ pr_err("can't attach client %d\n", i);
status = -ENOMEM;
goto fail;
}
diff --git a/drivers/mfd/pm8038-core.c b/drivers/mfd/pm8038-core.c
index 48bc92d..4996279 100644
--- a/drivers/mfd/pm8038-core.c
+++ b/drivers/mfd/pm8038-core.c
@@ -373,6 +373,11 @@
.num_resources = ARRAY_SIZE(ccadc_cell_resources),
};
+static struct mfd_cell vibrator_cell __devinitdata = {
+ .name = PM8XXX_VIBRATOR_DEV_NAME,
+ .id = -1,
+};
+
static struct pm8xxx_vreg regulator_data[] = {
/* name pc_name ctrl test hpm_min */
NLDO1200("8038_l1", 0x0AE, 0x0AF, LDO_1200),
@@ -609,6 +614,17 @@
}
}
+ if (pdata->vibrator_pdata) {
+ vibrator_cell.platform_data = pdata->vibrator_pdata;
+ vibrator_cell.pdata_size =
+ sizeof(struct pm8xxx_vibrator_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &vibrator_cell, 1, NULL, 0);
+ if (ret) {
+ pr_err("Failed to add vibrator ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
if (pdata->spk_pdata) {
spk_cell.platform_data = pdata->spk_pdata;
spk_cell.pdata_size = sizeof(struct pm8xxx_spk_platform_data);
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index 1f7b67a..fa7c116 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -35,6 +35,8 @@
#define MAX_WCD9XXX_DEVICE 4
#define TABLA_I2C_MODE 0x03
#define SITAR_I2C_MODE 0x01
+#define CODEC_DT_MAX_PROP_SIZE 40
+#define WCD9XXX_I2C_GSBI_SLAVE_ID "3-000d"
struct wcd9xxx_i2c {
struct i2c_client *client;
@@ -43,6 +45,17 @@
int mod_id;
};
+static char *taiko_supplies[] = {
+ "cdc-vdd-buck", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vddpx-1",
+ "cdc-vdd-a-1p2v", "cdc-vddcx-1", "cdc-vddcx-2",
+};
+
+static int wcd9xxx_dt_parse_vreg_info(struct device *dev,
+ struct wcd9xxx_regulator *vreg, const char *vreg_name);
+static int wcd9xxx_dt_parse_micbias_info(struct device *dev,
+ struct wcd9xxx_micbias_setting *micbias);
+static struct wcd9xxx_pdata *wcd9xxx_populate_dt_pdata(struct device *dev);
+
struct wcd9xxx_i2c wcd9xxx_modules[MAX_WCD9XXX_DEVICE];
static int wcd9xxx_intf = -1;
@@ -764,19 +777,31 @@
int ret = 0;
int i2c_mode = 0;
static int device_id;
+ struct device *dev;
pr_info("%s\n", __func__);
if (wcd9xxx_intf == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
- pr_info("tabla card is already detected in slimbus mode\n");
+ dev_dbg(&client->dev, "%s:Codec is detected in slimbus mode\n",
+ __func__);
return -ENODEV;
}
- pdata = client->dev.platform_data;
if (device_id > 0) {
wcd9xxx_modules[device_id++].client = client;
- pr_info("probe for other slaves devices of tabla\n");
+ dev_dbg(&client->dev, "%s:probe for other slaves\n"
+ "devices of codec\n", __func__);
return ret;
}
-
+ dev = &client->dev;
+ if (client->dev.of_node) {
+ dev_dbg(&client->dev, "%s:Platform data from device tree\n",
+ __func__);
+ pdata = wcd9xxx_populate_dt_pdata(&client->dev);
+ client->dev.platform_data = pdata;
+ } else {
+ dev_dbg(&client->dev, "%s:Platform data from board file\n",
+ __func__);
+ pdata = client->dev.platform_data;
+ }
wcd9xxx = kzalloc(sizeof(struct wcd9xxx), GFP_KERNEL);
if (wcd9xxx == NULL) {
pr_err("%s: error, allocation failed\n", __func__);
@@ -858,7 +883,6 @@
return 0;
}
-#define CODEC_DT_MAX_PROP_SIZE 40
static int wcd9xxx_dt_parse_vreg_info(struct device *dev,
struct wcd9xxx_regulator *vreg, const char *vreg_name)
{
@@ -1057,11 +1081,6 @@
return 0;
}
-static char *taiko_supplies[] = {
- "cdc-vdd-buck", "cdc-vdd-tx-h", "cdc-vdd-rx-h", "cdc-vddpx-1",
- "cdc-vdd-a-1p2v", "cdc-vddcx-1", "cdc-vddcx-2",
-};
-
static struct wcd9xxx_pdata *wcd9xxx_populate_dt_pdata(struct device *dev)
{
struct wcd9xxx_pdata *pdata;
@@ -1071,12 +1090,11 @@
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
- dev_err(dev,
- "could not allocate memory for platform data\n");
+ dev_err(dev, "could not allocate memory for platform data\n");
return NULL;
}
-
- if (!strcmp(dev_name(dev), "taiko-slim-pgd")) {
+ if (!strcmp(dev_name(dev), "taiko-slim-pgd") ||
+ (!strcmp(dev_name(dev), WCD9XXX_I2C_GSBI_SLAVE_ID))) {
codec_supplies = taiko_supplies;
num_of_supplies = ARRAY_SIZE(taiko_supplies);
} else {
@@ -1111,11 +1129,7 @@
pdata->reset_gpio);
goto err;
}
-
- ret = wcd9xxx_dt_parse_slim_interface_dev_info(dev,
- &pdata->slimbus_slave_device);
- if (ret)
- goto err;
+ dev_dbg(dev, "%s: reset gpio %d", __func__, pdata->reset_gpio);
return pdata;
err:
devm_kfree(dev, pdata);
@@ -1151,6 +1165,14 @@
if (slim->dev.of_node) {
dev_info(&slim->dev, "Platform data from device tree\n");
pdata = wcd9xxx_populate_dt_pdata(&slim->dev);
+ ret = wcd9xxx_dt_parse_slim_interface_dev_info(&slim->dev,
+ &pdata->slimbus_slave_device);
+ if (ret) {
+ dev_err(&slim->dev, "Error, parsing slim interface\n");
+ devm_kfree(&slim->dev, pdata);
+ ret = -EINVAL;
+ goto err;
+ }
slim->dev.platform_data = pdata;
} else {
@@ -1460,6 +1482,14 @@
#define WCD9XXX_I2C_DIGITAL_1 2
#define WCD9XXX_I2C_DIGITAL_2 3
+static struct i2c_device_id wcd9xxx_id_table[] = {
+ {"wcd9xxx-i2c", WCD9XXX_I2C_TOP_LEVEL},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_ANALOG},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_DIGITAL_1},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_DIGITAL_2},
+ {}
+};
+
static struct i2c_device_id tabla_id_table[] = {
{"tabla top level", WCD9XXX_I2C_TOP_LEVEL},
{"tabla analog", WCD9XXX_I2C_ANALOG},
@@ -1481,9 +1511,22 @@
.suspend = wcd9xxx_i2c_suspend,
};
+static struct i2c_driver wcd9xxx_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "wcd9xxx-i2c-core",
+ },
+ .id_table = wcd9xxx_id_table,
+ .probe = wcd9xxx_i2c_probe,
+ .remove = __devexit_p(wcd9xxx_i2c_remove),
+ .resume = wcd9xxx_i2c_resume,
+ .suspend = wcd9xxx_i2c_suspend,
+};
+
+
static int __init wcd9xxx_init(void)
{
- int ret1, ret2, ret3, ret4, ret5, ret6;
+ int ret1, ret2, ret3, ret4, ret5, ret6, ret7;
ret1 = slim_driver_register(&tabla_slim_driver);
if (ret1 != 0)
@@ -1495,7 +1538,7 @@
ret3 = i2c_add_driver(&tabla_i2c_driver);
if (ret3 != 0)
- pr_err("failed to add the I2C driver\n");
+ pr_err("failed to add the tabla2x I2C driver\n");
ret4 = slim_driver_register(&sitar_slim_driver);
if (ret4 != 0)
@@ -1509,7 +1552,11 @@
if (ret6 != 0)
pr_err("Failed to register taiko SB driver: %d\n", ret6);
- return (ret1 && ret2 && ret3 && ret4 && ret5 && ret6) ? -1 : 0;
+ ret7 = i2c_add_driver(&wcd9xxx_i2c_driver);
+ if (ret7 != 0)
+ pr_err("failed to add the wcd9xxx I2C driver\n");
+
+ return (ret1 && ret2 && ret3 && ret4 && ret5 && ret6 && ret7) ? -1 : 0;
}
module_init(wcd9xxx_init);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6ab3a66..93a3237 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -664,6 +664,17 @@
This adds support for connecting devices like mouse in HSIC
Host mode.
+config TI_DRV2667
+ tristate "TI's DRV2667 haptic controller support"
+ depends on I2C
+ help
+ The DRV2667 is a piezo haptic controller chip. It can drive
+ piezo haptics either in digital mode or analog mode. This chip
+ can be used in variety of devices to provide haptic support.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ti_drv2667.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e92e119..8395ef4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -72,3 +72,4 @@
obj-$(CONFIG_PMIC8058_XOADC) += pmic8058-xoadc.o
obj-$(CONFIG_QSEECOM) += qseecom.o
obj-$(CONFIG_QFP_FUSE) += qfp_fuse.o
+obj-$(CONFIG_TI_DRV2667) += ti_drv2667.o
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 12f896e..46015b0 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -1,6 +1,6 @@
-/* Qualcomm Secure Execution Environment Communicator (QSEECOM) driver
+/*Qualcomm Secure Execution Environment Communicator (QSEECOM) driver
*
* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
@@ -32,19 +32,30 @@
#include <linux/types.h>
#include <linux/clk.h>
#include <linux/qseecom.h>
+#include <linux/elf.h>
+#include <linux/firmware.h>
#include <linux/freezer.h>
+#include <linux/scatterlist.h>
#include <mach/board.h>
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
#include <mach/scm.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include <mach/socinfo.h>
#include "qseecom_legacy.h"
+#include "qseecom_kernel.h"
#define QSEECOM_DEV "qseecom"
#define QSEOS_VERSION_13 0x13
#define QSEOS_VERSION_14 0x14
-#define QSEOS_CHECK_VERSION_CMD 0x00001803;
+#define QSEEE_VERSION_00 0x400000
+
+#define QSEOS_CHECK_VERSION_CMD 0x00001803
+
+#define QSEE_CE_CLK_100MHZ 100000000
+#define QSEE_CE_CLK_50MHZ 50000000
+
+#define QSEECOM_MAX_SG_ENTRY 10
enum qseecom_command_scm_resp_type {
QSEOS_APP_ID = 0xEE01,
@@ -61,6 +72,9 @@
QSEOS_LISTENER_DATA_RSP_COMMAND,
QSEOS_LOAD_EXTERNAL_ELF_COMMAND,
QSEOS_UNLOAD_EXTERNAL_ELF_COMMAND,
+ QSEOS_GET_APP_STATE_COMMAND,
+ QSEOS_LOAD_SERV_IMAGE_COMMAND,
+ QSEOS_UNLOAD_SERV_IMAGE_COMMAND,
QSEOS_CMD_MAX = 0xEFFFFFFF
};
@@ -93,6 +107,17 @@
uint32_t app_id;
};
+__packed struct qseecom_load_lib_image_ireq {
+ uint32_t qsee_cmd_id;
+ uint32_t mdt_len;
+ uint32_t img_len;
+ uint32_t phy_addr;
+};
+
+__packed struct qseecom_unload_lib_image_ireq {
+ uint32_t qsee_cmd_id;
+};
+
__packed struct qseecom_register_listener_ireq {
uint32_t qsee_cmd_id;
uint32_t listener_id;
@@ -168,6 +193,11 @@
u32 ref_cnt;
};
+struct qseecom_registered_kclient_list {
+ struct list_head list;
+ struct qseecom_handle *handle;
+};
+
struct qseecom_control {
struct ion_client *ion_clnt; /* Ion client */
struct list_head registered_listener_list_head;
@@ -176,11 +206,16 @@
struct list_head registered_app_list_head;
spinlock_t registered_app_list_lock;
+ struct list_head registered_kclient_list_head;
+ spinlock_t registered_kclient_list_lock;
+
wait_queue_head_t send_resp_wq;
int send_resp_flag;
uint32_t qseos_version;
+ uint32_t qsee_version;
struct device *pdev;
+ bool commonlib_loaded;
};
struct qseecom_client_handle {
@@ -215,11 +250,14 @@
struct clk *ce_core_src_clk;
struct clk *ce_bus_clk;
+struct qseecom_sg_entry {
+ uint32_t phys_addr;
+ uint32_t len;
+};
+
/* Function proto types */
static int qsee_vote_for_clock(int32_t);
static void qsee_disable_clock_vote(int32_t);
-static int __qseecom_init_clk(void);
-static void __qseecom_disable_clk(void);
static int __qseecom_is_svc_unique(struct qseecom_dev_handle *data,
struct qseecom_register_listener_req *svc)
@@ -642,7 +680,6 @@
ion_phys_addr_t pa = 0;
uint32_t len;
struct qseecom_command_scm_resp resp;
- struct qseecom_check_app_ireq req;
struct qseecom_load_app_ireq load_req;
/* Copy the relevant information needed for loading the image */
@@ -657,11 +694,8 @@
if (ret)
pr_warning("Unable to vote for SFPB clock");
- req.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND;
- memcpy(req.app_name, load_img_req.img_name, MAX_APP_NAME_SIZE);
-
pr_warn("App (%s) does not exist, loading apps for first time\n",
- (char *)(req.app_name));
+ (char *)(load_img_req.img_name));
/* Get the handle of the shared fd */
ihandle = ion_import_dma_buf(qseecom.ion_clnt,
load_img_req.ifd_data_fd);
@@ -675,6 +709,7 @@
ret = ion_phys(qseecom.ion_clnt, ihandle, &pa, &len);
/* Populate the structure for sending scm call to load image */
+ memcpy(load_req.app_name, load_img_req.img_name, MAX_APP_NAME_SIZE);
load_req.qsee_cmd_id = QSEOS_APP_START_COMMAND;
load_req.mdt_len = load_img_req.mdt_len;
load_req.img_len = load_img_req.img_len;
@@ -738,7 +773,7 @@
spin_unlock_irqrestore(&qseecom.registered_app_list_lock, flags);
pr_warn("App with id %d (%s) now loaded\n", app_id,
- (char *)(req.app_name));
+ (char *)(load_img_req.img_name));
data->client.app_id = app_id;
load_img_req.app_id = app_id;
@@ -1066,13 +1101,11 @@
{
struct ion_handle *ihandle;
char *field;
- uint32_t *update;
- ion_phys_addr_t pa;
int ret = 0;
int i = 0;
- uint32_t length;
for (i = 0; i < MAX_ION_FD; i++) {
+ struct sg_table *sg_ptr = NULL;
if (req->ifd_data[i].fd > 0) {
/* Get the handle of the shared fd */
ihandle = ion_import_dma_buf(qseecom.ion_clnt,
@@ -1083,20 +1116,51 @@
}
field = (char *) req->cmd_req_buf +
req->ifd_data[i].cmd_buf_offset;
- update = (uint32_t *) field;
/* Populate the cmd data structure with the phys_addr */
- ret = ion_phys(qseecom.ion_clnt, ihandle, &pa, &length);
- if (ret)
- return -ENOMEM;
-
- *update = (uint32_t)pa;
+ sg_ptr = ion_sg_table(qseecom.ion_clnt, ihandle);
+ if (sg_ptr == NULL) {
+ pr_err("IOn client could not retrieve sg table\n");
+ goto err;
+ }
+ if (sg_ptr->nents == 0) {
+ pr_err("Num of scattered entries is 0\n");
+ goto err;
+ }
+ if (sg_ptr->nents > QSEECOM_MAX_SG_ENTRY) {
+ pr_err("Num of scattered entries");
+ pr_err(" (%d) is greater than max supported %d\n",
+ sg_ptr->nents, QSEECOM_MAX_SG_ENTRY);
+ goto err;
+ }
+ if (sg_ptr->nents == 1) {
+ uint32_t *update;
+ update = (uint32_t *) field;
+ *update = (uint32_t)sg_dma_address(sg_ptr->sgl);
+ } else {
+ struct qseecom_sg_entry *update;
+ struct scatterlist *sg;
+ int j = 0;
+ update = (struct qseecom_sg_entry *) field;
+ sg = sg_ptr->sgl;
+ for (j = 0; j < sg_ptr->nents; j++) {
+ update->phys_addr = (uint32_t)
+ sg_dma_address(sg);
+ update->len = (uint32_t)sg->length;
+ update++;
+ sg = sg_next(sg);
+ }
+ }
/* Deallocate the handle */
if (!IS_ERR_OR_NULL(ihandle))
ion_free(qseecom.ion_clnt, ihandle);
}
}
return ret;
+err:
+ if (!IS_ERR_OR_NULL(ihandle))
+ ion_free(qseecom.ion_clnt, ihandle);
+ return -ENOMEM;
}
static int qseecom_send_modfd_cmd(struct qseecom_dev_handle *data,
@@ -1171,6 +1235,514 @@
return ret;
}
+static bool __qseecom_is_fw_image_valid(const struct firmware *fw_entry)
+{
+ struct elf32_hdr *ehdr;
+
+ if (fw_entry->size < sizeof(*ehdr)) {
+ pr_err("%s: Not big enough to be an elf header\n",
+ qseecom.pdev->init_name);
+ return false;
+ }
+ ehdr = (struct elf32_hdr *)fw_entry->data;
+ if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
+ pr_err("%s: Not an elf header\n",
+ qseecom.pdev->init_name);
+ return false;
+ }
+
+ if (ehdr->e_phnum == 0) {
+ pr_err("%s: No loadable segments\n",
+ qseecom.pdev->init_name);
+ return false;
+ }
+ if (sizeof(struct elf32_phdr) * ehdr->e_phnum +
+ sizeof(struct elf32_hdr) > fw_entry->size) {
+ pr_err("%s: Program headers not within mdt\n",
+ qseecom.pdev->init_name);
+ return false;
+ }
+ return true;
+}
+
+static int __qseecom_get_fw_size(char *appname, uint32_t *fw_size)
+{
+ int ret = -1;
+ int i = 0, rc = 0;
+ const struct firmware *fw_entry = NULL;
+ struct elf32_phdr *phdr;
+ char fw_name[MAX_APP_NAME_SIZE];
+ struct elf32_hdr *ehdr;
+ int num_images = 0;
+
+ snprintf(fw_name, sizeof(fw_name), "%s.mdt", appname);
+ rc = request_firmware(&fw_entry, fw_name, qseecom.pdev);
+ if (rc) {
+ pr_err("error with request_firmware\n");
+ ret = -EIO;
+ goto err;
+ }
+ if (!__qseecom_is_fw_image_valid(fw_entry)) {
+ ret = -EIO;
+ goto err;
+ }
+ *fw_size = fw_entry->size;
+ phdr = (struct elf32_phdr *)(fw_entry->data + sizeof(struct elf32_hdr));
+ ehdr = (struct elf32_hdr *)fw_entry->data;
+ num_images = ehdr->e_phnum;
+ release_firmware(fw_entry);
+ for (i = 0; i < num_images; i++, phdr++) {
+ memset(fw_name, 0, sizeof(fw_name));
+ snprintf(fw_name, ARRAY_SIZE(fw_name), "%s.b%02d", appname, i);
+ ret = request_firmware(&fw_entry, fw_name, qseecom.pdev);
+ if (ret)
+ goto err;
+ *fw_size += fw_entry->size;
+ release_firmware(fw_entry);
+ }
+ return ret;
+err:
+ if (fw_entry)
+ release_firmware(fw_entry);
+ *fw_size = 0;
+ return ret;
+}
+
+static int __qseecom_get_fw_data(char *appname, u8 *img_data,
+ struct qseecom_load_app_ireq *load_req)
+{
+ int ret = -1;
+ int i = 0, rc = 0;
+ const struct firmware *fw_entry = NULL;
+ char fw_name[MAX_APP_NAME_SIZE];
+ u8 *img_data_ptr = img_data;
+ struct elf32_hdr *ehdr;
+ int num_images = 0;
+
+ snprintf(fw_name, sizeof(fw_name), "%s.mdt", appname);
+ rc = request_firmware(&fw_entry, fw_name, qseecom.pdev);
+ if (rc) {
+ ret = -EIO;
+ goto err;
+ }
+ load_req->img_len = fw_entry->size;
+ memcpy(img_data_ptr, fw_entry->data, fw_entry->size);
+ img_data_ptr = img_data_ptr + fw_entry->size;
+ load_req->mdt_len = fw_entry->size; /*Get MDT LEN*/
+ ehdr = (struct elf32_hdr *)fw_entry->data;
+ num_images = ehdr->e_phnum;
+ release_firmware(fw_entry);
+ for (i = 0; i < num_images; i++) {
+ snprintf(fw_name, ARRAY_SIZE(fw_name), "%s.b%02d", appname, i);
+ ret = request_firmware(&fw_entry, fw_name, qseecom.pdev);
+ if (ret) {
+ pr_err("Failed to locate blob %s\n", fw_name);
+ goto err;
+ }
+ memcpy(img_data_ptr, fw_entry->data, fw_entry->size);
+ img_data_ptr = img_data_ptr + fw_entry->size;
+ load_req->img_len += fw_entry->size;
+ release_firmware(fw_entry);
+ }
+ load_req->phy_addr = virt_to_phys(img_data);
+ return ret;
+err:
+ release_firmware(fw_entry);
+ return ret;
+}
+
+static int __qseecom_load_fw(struct qseecom_dev_handle *data, char *appname)
+{
+ int ret = -1;
+ uint32_t fw_size = 0;
+ struct qseecom_load_app_ireq load_req = {0, 0, 0, 0};
+ struct qseecom_command_scm_resp resp;
+ u8 *img_data = NULL;
+
+ if (__qseecom_get_fw_size(appname, &fw_size))
+ return -EIO;
+
+ img_data = kzalloc(fw_size, GFP_KERNEL);
+ if (!img_data) {
+ pr_err("Failied to allocate memory for copying image data\n");
+ return -ENOMEM;
+ }
+ ret = __qseecom_get_fw_data(appname, img_data, &load_req);
+ if (ret) {
+ kzfree(img_data);
+ return -EIO;
+ }
+
+ /* Populate the remaining parameters */
+ load_req.qsee_cmd_id = QSEOS_APP_START_COMMAND;
+ memcpy(load_req.app_name, appname, MAX_APP_NAME_SIZE);
+ ret = qsee_vote_for_clock(CLK_SFPB);
+ if (ret) {
+ kzfree(img_data);
+ pr_warning("Unable to vote for SFPB clock");
+ return -EIO;
+ }
+
+ /* SCM_CALL to load the image */
+ ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &load_req,
+ sizeof(struct qseecom_load_app_ireq),
+ &resp, sizeof(resp));
+ kzfree(img_data);
+ if (ret) {
+ pr_err("scm_call to load failed : ret %d\n", ret);
+ qsee_disable_clock_vote(CLK_SFPB);
+ return -EIO;
+ }
+
+ switch (resp.result) {
+ case QSEOS_RESULT_SUCCESS:
+ ret = resp.data;
+ break;
+ case QSEOS_RESULT_INCOMPLETE:
+ ret = __qseecom_process_incomplete_cmd(data, &resp);
+ if (ret)
+ pr_err("process_incomplete_cmd FAILED\n");
+ else
+ ret = resp.data;
+ break;
+ case QSEOS_RESULT_FAILURE:
+ pr_err("scm call failed with response QSEOS_RESULT FAILURE\n");
+ break;
+ default:
+ pr_err("scm call return unknown response %d\n", resp.result);
+ ret = -EINVAL;
+ break;
+ }
+ qsee_disable_clock_vote(CLK_SFPB);
+
+ return ret;
+}
+
+static int qseecom_load_commonlib_image(void)
+{
+ int32_t ret = 0;
+ uint32_t fw_size = 0;
+ struct qseecom_load_app_ireq load_req = {0, 0, 0, 0};
+ struct qseecom_command_scm_resp resp;
+ u8 *img_data = NULL;
+
+ if (__qseecom_get_fw_size("commonlib", &fw_size))
+ return -EIO;
+
+ img_data = kzalloc(fw_size, GFP_KERNEL);
+ if (!img_data) {
+ pr_err("Mem allocation for lib image data failed\n");
+ return -ENOMEM;
+ }
+ ret = __qseecom_get_fw_data("commonlib", img_data, &load_req);
+ if (ret) {
+ kzfree(img_data);
+ return -EIO;
+ }
+ /* Populate the remaining parameters */
+ load_req.qsee_cmd_id = QSEOS_LOAD_SERV_IMAGE_COMMAND;
+ /* SCM_CALL to load the image */
+ ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &load_req,
+ sizeof(struct qseecom_load_lib_image_ireq),
+ &resp, sizeof(resp));
+ kzfree(img_data);
+ if (ret) {
+ pr_err("scm_call to load failed : ret %d\n", ret);
+ ret = -EIO;
+ } else {
+ switch (resp.result) {
+ case QSEOS_RESULT_SUCCESS:
+ break;
+ case QSEOS_RESULT_FAILURE:
+ pr_err("scm call failed w/response result%d\n",
+ resp.result);
+ ret = -EINVAL;
+ break;
+ default:
+ pr_err("scm call return unknown response %d\n",
+ resp.result);
+ ret = -EINVAL;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int qseecom_unload_commonlib_image(void)
+{
+ int ret = -EINVAL;
+ struct qseecom_unload_lib_image_ireq unload_req = {0};
+ struct qseecom_command_scm_resp resp;
+
+ /* Populate the remaining parameters */
+ unload_req.qsee_cmd_id = QSEOS_UNLOAD_SERV_IMAGE_COMMAND;
+ /* SCM_CALL to load the image */
+ ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &unload_req,
+ sizeof(struct qseecom_unload_lib_image_ireq),
+ &resp, sizeof(resp));
+ if (ret) {
+ pr_err("scm_call to unload lib failed : ret %d\n", ret);
+ ret = -EIO;
+ } else {
+ switch (resp.result) {
+ case QSEOS_RESULT_SUCCESS:
+ break;
+ case QSEOS_RESULT_FAILURE:
+ pr_err("scm fail resp.result QSEOS_RESULT FAILURE\n");
+ break;
+ default:
+ pr_err("scm call return unknown response %d\n",
+ resp.result);
+ ret = -EINVAL;
+ break;
+ }
+ }
+ return ret;
+}
+
+int qseecom_start_app(struct qseecom_handle **handle,
+ char *app_name, uint32_t size)
+{
+ int32_t ret = 0;
+ unsigned long flags = 0;
+ struct qseecom_dev_handle *data = NULL;
+ struct qseecom_check_app_ireq app_ireq;
+ struct qseecom_registered_app_list *entry = NULL;
+ struct qseecom_registered_kclient_list *kclient_entry = NULL;
+ bool found_app = false;
+ uint32_t len;
+ ion_phys_addr_t pa;
+
+ if (qseecom.qseos_version == QSEOS_VERSION_13) {
+ pr_err("This functionality is UNSUPPORTED in version 1.3\n");
+ return -EINVAL;
+ }
+
+ if (qseecom.qsee_version > QSEEE_VERSION_00) {
+ mutex_lock(&app_access_lock);
+ if (qseecom.commonlib_loaded == false) {
+ ret = qseecom_load_commonlib_image();
+ if (ret == 0)
+ qseecom.commonlib_loaded = true;
+ }
+ mutex_unlock(&app_access_lock);
+ }
+
+ if (ret)
+ return -EIO;
+
+ *handle = kzalloc(sizeof(struct qseecom_handle), GFP_KERNEL);
+ if (!(*handle)) {
+ pr_err("failed to allocate memory for kernel client handle\n");
+ return -ENOMEM;
+ }
+
+ app_ireq.qsee_cmd_id = QSEOS_APP_LOOKUP_COMMAND;
+ memcpy(app_ireq.app_name, app_name, MAX_APP_NAME_SIZE);
+ ret = __qseecom_check_app_exists(app_ireq);
+ if (ret < 0)
+ return -EINVAL;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ pr_err("kmalloc failed\n");
+ if (ret == 0) {
+ kfree(*handle);
+ *handle = NULL;
+ }
+ return -ENOMEM;
+ }
+ data->abort = 0;
+ data->service = false;
+ data->released = false;
+ data->client.app_id = ret;
+ data->client.sb_length = size;
+ data->client.user_virt_sb_base = 0;
+ data->client.ihandle = NULL;
+
+ init_waitqueue_head(&data->abort_wq);
+ atomic_set(&data->ioctl_count, 0);
+
+ data->client.ihandle = ion_alloc(qseecom.ion_clnt, size, 4096,
+ ION_HEAP(ION_QSECOM_HEAP_ID), 0);
+ if (IS_ERR_OR_NULL(data->client.ihandle)) {
+ pr_err("Ion client could not retrieve the handle\n");
+ kfree(data);
+ kfree(*handle);
+ *handle = NULL;
+ return -EINVAL;
+ }
+
+ if (ret > 0) {
+ pr_warn("App id %d for [%s] app exists\n", ret,
+ (char *)app_ireq.app_name);
+ spin_lock_irqsave(&qseecom.registered_app_list_lock, flags);
+ list_for_each_entry(entry,
+ &qseecom.registered_app_list_head, list){
+ if (entry->app_id == ret) {
+ entry->ref_cnt++;
+ found_app = true;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(
+ &qseecom.registered_app_list_lock, flags);
+ if (!found_app)
+ pr_warn("App_id %d [%s] was loaded but not registered\n",
+ ret, (char *)app_ireq.app_name);
+ } else {
+ /* load the app and get the app_id */
+ pr_debug("%s: Loading app for the first time'\n",
+ qseecom.pdev->init_name);
+ mutex_lock(&app_access_lock);
+ ret = __qseecom_load_fw(data, app_name);
+ mutex_unlock(&app_access_lock);
+
+ if (ret < 0) {
+ kfree(*handle);
+ *handle = NULL;
+ return ret;
+ }
+ data->client.app_id = ret;
+ }
+ if (!found_app) {
+ entry = kmalloc(sizeof(*entry), GFP_KERNEL);
+ if (!entry) {
+ pr_err("kmalloc failed\n");
+ return -ENOMEM;
+ }
+ entry->app_id = ret;
+ entry->ref_cnt = 1;
+
+ spin_lock_irqsave(&qseecom.registered_app_list_lock, flags);
+ list_add_tail(&entry->list, &qseecom.registered_app_list_head);
+ spin_unlock_irqrestore(&qseecom.registered_app_list_lock,
+ flags);
+ }
+
+ /* Get the physical address of the ION BUF */
+ ret = ion_phys(qseecom.ion_clnt, data->client.ihandle, &pa, &len);
+ /* Populate the structure for sending scm call to load image */
+ data->client.sb_virt = (char *) ion_map_kernel(qseecom.ion_clnt,
+ data->client.ihandle);
+ data->client.sb_phys = pa;
+ (*handle)->dev = (void *)data;
+ (*handle)->sbuf = (unsigned char *)data->client.sb_virt;
+ (*handle)->sbuf_len = data->client.sb_length;
+
+ kclient_entry = kzalloc(sizeof(*kclient_entry), GFP_KERNEL);
+ if (!kclient_entry) {
+ pr_err("kmalloc failed\n");
+ return -ENOMEM;
+ }
+ kclient_entry->handle = *handle;
+
+ spin_lock_irqsave(&qseecom.registered_kclient_list_lock, flags);
+ list_add_tail(&kclient_entry->list,
+ &qseecom.registered_kclient_list_head);
+ spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(qseecom_start_app);
+
+int qseecom_shutdown_app(struct qseecom_handle **handle)
+{
+ int ret = -EINVAL;
+ struct qseecom_dev_handle *data =
+ (struct qseecom_dev_handle *) ((*handle)->dev);
+ struct qseecom_registered_kclient_list *kclient = NULL;
+ unsigned long flags = 0;
+ bool found_handle = false;
+
+ if (qseecom.qseos_version == QSEOS_VERSION_13) {
+ pr_err("This functionality is UNSUPPORTED in version 1.3\n");
+ return -EINVAL;
+ }
+ if (*handle == NULL) {
+ pr_err("Handle is not initialized\n");
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&qseecom.registered_kclient_list_lock, flags);
+ list_for_each_entry(kclient, &qseecom.registered_kclient_list_head,
+ list) {
+ if (kclient->handle == (*handle)) {
+ list_del(&kclient->list);
+ found_handle = true;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock, flags);
+ if (!found_handle)
+ pr_err("Unable to find the handle, exiting\n");
+ else
+ ret = qseecom_unload_app(data);
+ if (ret == 0) {
+ kzfree(data);
+ kzfree(*handle);
+ kzfree(kclient);
+ *handle = NULL;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(qseecom_shutdown_app);
+
+int qseecom_send_command(struct qseecom_handle *handle, void *send_buf,
+ uint32_t sbuf_len, void *resp_buf, uint32_t rbuf_len)
+{
+ int ret = 0;
+ struct qseecom_send_cmd_req req = {0, 0, 0, 0};
+ struct qseecom_dev_handle *data;
+
+ if (qseecom.qseos_version == QSEOS_VERSION_13) {
+ pr_err("This functionality is UNSUPPORTED in version 1.3\n");
+ return -EINVAL;
+ }
+
+ if (handle == NULL) {
+ pr_err("Handle is not initialized\n");
+ return -EINVAL;
+ }
+ data = handle->dev;
+
+ req.cmd_req_len = sbuf_len;
+ req.resp_len = rbuf_len;
+ req.cmd_req_buf = send_buf;
+ req.resp_buf = resp_buf;
+
+ mutex_lock(&app_access_lock);
+ atomic_inc(&data->ioctl_count);
+
+ ret = __qseecom_send_cmd(data, &req);
+
+ atomic_dec(&data->ioctl_count);
+ mutex_unlock(&app_access_lock);
+
+ if (ret)
+ return ret;
+
+ pr_debug("sending cmd_req->rsp size: %u, ptr: 0x%p\n",
+ req.resp_len, req.resp_buf);
+ return ret;
+}
+EXPORT_SYMBOL(qseecom_send_command);
+
+int qseecom_set_bandwidth(struct qseecom_handle *handle, bool high)
+{
+ if ((handle == NULL) || (handle->dev == NULL)) {
+ pr_err("No valid kernel client\n");
+ return -EINVAL;
+ }
+ if (high)
+ return qsee_vote_for_clock(CLK_DFAB);
+ else {
+ qsee_disable_clock_vote(CLK_DFAB);
+ return 0;
+ }
+}
+EXPORT_SYMBOL(qseecom_set_bandwidth);
+
static int qseecom_send_resp(void)
{
qseecom.send_resp_flag = 1;
@@ -1209,9 +1781,13 @@
if (qsee_sfpb_bw_count > 0)
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 3);
- else
+ else {
+ if (ce_core_src_clk != NULL)
+ clk_set_rate(ce_core_src_clk,
+ QSEE_CE_CLK_100MHZ);
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 1);
+ }
if (ret)
pr_err("DFAB Bandwidth req failed (%d)\n",
ret);
@@ -1228,9 +1804,13 @@
if (qsee_bw_count > 0)
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 3);
- else
+ else {
+ if (ce_core_src_clk != NULL)
+ clk_set_rate(ce_core_src_clk,
+ QSEE_CE_CLK_100MHZ);
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 2);
+ }
if (ret)
pr_err("SFPB Bandwidth req failed (%d)\n",
@@ -1269,9 +1849,13 @@
if (qsee_sfpb_bw_count > 0)
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 2);
- else
+ else {
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 0);
+ if (ce_core_src_clk != NULL)
+ clk_set_rate(ce_core_src_clk,
+ QSEE_CE_CLK_50MHZ);
+ }
if (ret)
pr_err("SFPB Bandwidth req fail (%d)\n",
ret);
@@ -1289,9 +1873,13 @@
if (qsee_bw_count > 0)
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 1);
- else
+ else {
ret = msm_bus_scale_client_update_request(
qsee_perf_client, 0);
+ if (ce_core_src_clk != NULL)
+ clk_set_rate(ce_core_src_clk,
+ QSEE_CE_CLK_50MHZ);
+ }
if (ret)
pr_err("SFPB Bandwidth req fail (%d)\n",
ret);
@@ -1588,7 +2176,15 @@
case QSEECOM_IOCTL_LOAD_APP_REQ: {
mutex_lock(&app_access_lock);
atomic_inc(&data->ioctl_count);
- ret = qseecom_load_app(data, argp);
+ if (qseecom.qsee_version > QSEEE_VERSION_00) {
+ if (qseecom.commonlib_loaded == false) {
+ ret = qseecom_load_commonlib_image();
+ if (ret == 0)
+ qseecom.commonlib_loaded = true;
+ }
+ }
+ if (ret == 0)
+ ret = qseecom_load_app(data, argp);
atomic_dec(&data->ioctl_count);
mutex_unlock(&app_access_lock);
if (ret)
@@ -1693,7 +2289,7 @@
int pil_error;
mutex_lock(&pil_access_lock);
if (pil_ref_cnt == 0) {
- pil = pil_get("tzapps");
+ pil = subsystem_get("tzapps");
if (IS_ERR(pil)) {
pr_err("Playready PIL image load failed\n");
pil_error = PTR_ERR(pil);
@@ -1728,7 +2324,7 @@
if (qseecom.qseos_version == QSEOS_VERSION_13) {
mutex_lock(&pil_access_lock);
if (pil_ref_cnt == 1)
- pil_put(pil);
+ subsystem_put(pil);
pil_ref_cnt--;
mutex_unlock(&pil_access_lock);
}
@@ -1744,7 +2340,47 @@
.release = qseecom_release
};
-static int __qseecom_init_clk()
+static int __qseecom_enable_clk(void)
+{
+ int rc = 0;
+
+ /* Enable CE core clk */
+ rc = clk_prepare_enable(ce_core_clk);
+ if (rc) {
+ pr_err("Unable to enable/prepare CE core clk\n");
+ return -EIO;
+ } else {
+ /* Enable CE clk */
+ rc = clk_prepare_enable(ce_clk);
+ if (rc) {
+ pr_err("Unable to enable/prepare CE iface clk\n");
+ clk_disable_unprepare(ce_core_clk);
+ return -EIO;
+ } else {
+ /* Enable AXI clk */
+ rc = clk_prepare_enable(ce_bus_clk);
+ if (rc) {
+ pr_err("Unable to enable/prepare CE iface clk\n");
+ clk_disable_unprepare(ce_core_clk);
+ clk_disable_unprepare(ce_clk);
+ return -EIO;
+ }
+ }
+ }
+ return rc;
+}
+
+static void __qseecom_disable_clk(void)
+{
+ if (ce_clk != NULL)
+ clk_disable_unprepare(ce_clk);
+ if (ce_core_clk != NULL)
+ clk_disable_unprepare(ce_core_clk);
+ if (ce_bus_clk != NULL)
+ clk_disable_unprepare(ce_bus_clk);
+}
+
+static int __qseecom_init_clk(void)
{
int rc = 0;
struct device *pdev;
@@ -1753,14 +2389,12 @@
/* Get CE3 src core clk. */
ce_core_src_clk = clk_get(pdev, "core_clk_src");
if (!IS_ERR(ce_core_src_clk)) {
- ce_core_src_clk = ce_core_src_clk;
-
- /* Set the core src clk @100Mhz */
- rc = clk_set_rate(ce_core_src_clk, 100000000);
+ /* Set the core src clk @50Mhz */
+ rc = clk_set_rate(ce_core_src_clk, QSEE_CE_CLK_50MHZ);
if (rc) {
clk_put(ce_core_src_clk);
pr_err("Unable to set the core src clk @100Mhz.\n");
- goto err_clk;
+ return -EIO;
}
} else {
pr_warn("Unable to get CE core src clk, set to NULL\n");
@@ -1774,7 +2408,7 @@
pr_err("Unable to get CE core clk\n");
if (ce_core_src_clk != NULL)
clk_put(ce_core_src_clk);
- goto err_clk;
+ return -EIO;
}
/* Get CE Interface clk */
@@ -1785,7 +2419,7 @@
if (ce_core_src_clk != NULL)
clk_put(ce_core_src_clk);
clk_put(ce_core_clk);
- goto err_clk;
+ return -EIO;
}
/* Get CE AXI clk */
@@ -1797,85 +2431,48 @@
clk_put(ce_core_src_clk);
clk_put(ce_core_clk);
clk_put(ce_clk);
- goto err_clk;
+ return -EIO;
}
-
- /* Enable CE core clk */
- rc = clk_prepare_enable(ce_core_clk);
- if (rc) {
- pr_err("Unable to enable/prepare CE core clk\n");
- if (ce_core_src_clk != NULL)
- clk_put(ce_core_src_clk);
- clk_put(ce_core_clk);
- clk_put(ce_clk);
- goto err_clk;
- } else {
- /* Enable CE clk */
- rc = clk_prepare_enable(ce_clk);
- if (rc) {
- pr_err("Unable to enable/prepare CE iface clk\n");
- clk_disable_unprepare(ce_core_clk);
- if (ce_core_src_clk != NULL)
- clk_put(ce_core_src_clk);
- clk_put(ce_core_clk);
- clk_put(ce_clk);
- goto err_clk;
- } else {
- /* Enable AXI clk */
- rc = clk_prepare_enable(ce_bus_clk);
- if (rc) {
- pr_err("Unable to enable/prepare CE iface clk\n");
- clk_disable_unprepare(ce_core_clk);
- clk_disable_unprepare(ce_clk);
- if (ce_core_src_clk != NULL)
- clk_put(ce_core_src_clk);
- clk_put(ce_core_clk);
- clk_put(ce_clk);
- goto err_clk;
- }
- }
- }
- return rc;
-
-err_clk:
- if (rc)
- pr_err("Unable to init CE clks, rc = %d\n", rc);
- clk_disable_unprepare(ce_clk);
- clk_disable_unprepare(ce_core_clk);
- clk_disable_unprepare(ce_bus_clk);
- if (ce_core_src_clk != NULL)
- clk_put(ce_core_src_clk);
- clk_put(ce_clk);
- clk_put(ce_core_clk);
- clk_put(ce_bus_clk);
return rc;
}
-
-
-static void __qseecom_disable_clk()
+static void __qseecom_deinit_clk(void)
{
- clk_disable_unprepare(ce_clk);
- clk_disable_unprepare(ce_core_clk);
- clk_disable_unprepare(ce_bus_clk);
- if (ce_core_src_clk != NULL)
+ if (ce_clk != NULL) {
+ clk_put(ce_clk);
+ ce_clk = NULL;
+ }
+ if (ce_core_clk != NULL) {
+ clk_put(ce_core_clk);
+ ce_clk = NULL;
+ }
+ if (ce_bus_clk != NULL) {
+ clk_put(ce_bus_clk);
+ ce_clk = NULL;
+ }
+ if (ce_core_src_clk != NULL) {
clk_put(ce_core_src_clk);
- clk_put(ce_clk);
- clk_put(ce_core_clk);
- clk_put(ce_bus_clk);
+ ce_core_src_clk = NULL;
+ }
}
static int __devinit qseecom_probe(struct platform_device *pdev)
{
int rc;
- int ret;
+ int ret = 0;
struct device *class_dev;
char qsee_not_legacy = 0;
- struct msm_bus_scale_pdata *qseecom_platform_support;
+ struct msm_bus_scale_pdata *qseecom_platform_support = NULL;
uint32_t system_call_id = QSEOS_CHECK_VERSION_CMD;
qsee_bw_count = 0;
qsee_perf_client = 0;
+ qsee_sfpb_bw_count = 0;
+
+ ce_core_clk = NULL;
+ ce_clk = NULL;
+ ce_core_src_clk = NULL;
+ ce_bus_clk = NULL;
rc = alloc_chrdev_region(&qseecom_device_no, 0, 1, QSEECOM_DEV);
if (rc < 0) {
@@ -1911,26 +2508,38 @@
spin_lock_init(&qseecom.registered_listener_list_lock);
INIT_LIST_HEAD(&qseecom.registered_app_list_head);
spin_lock_init(&qseecom.registered_app_list_lock);
+ INIT_LIST_HEAD(&qseecom.registered_kclient_list_head);
+ spin_lock_init(&qseecom.registered_kclient_list_lock);
init_waitqueue_head(&qseecom.send_resp_wq);
qseecom.send_resp_flag = 0;
rc = scm_call(6, 1, &system_call_id, sizeof(system_call_id),
&qsee_not_legacy, sizeof(qsee_not_legacy));
if (rc) {
- pr_err("Failed to retrieve QSEE version information %d\n", rc);
+ pr_err("Failed to retrieve QSEOS version information %d\n", rc);
goto err;
}
- if (qsee_not_legacy)
+ if (qsee_not_legacy) {
+ uint32_t feature = 10;
+
+ qseecom.qsee_version = QSEEE_VERSION_00;
+ rc = scm_call(6, 3, &feature, sizeof(feature),
+ &qseecom.qsee_version, sizeof(qseecom.qsee_version));
+ if (rc) {
+ pr_err("Failed to get QSEE version info %d\n", rc);
+ goto err;
+ }
qseecom.qseos_version = QSEOS_VERSION_14;
- else {
+ } else {
qseecom.qseos_version = QSEOS_VERSION_13;
+ qseecom.qsee_version = 0;
pil = NULL;
pil_ref_cnt = 0;
}
-
+ qseecom.commonlib_loaded = false;
qseecom.pdev = class_dev;
/* Create ION msm client */
- qseecom.ion_clnt = msm_ion_client_create(0x03, "qseecom-kernel");
+ qseecom.ion_clnt = msm_ion_client_create(-1, "qseecom-kernel");
if (qseecom.ion_clnt == NULL) {
pr_err("Ion client cannot be created\n");
rc = -ENOMEM;
@@ -1942,6 +2551,11 @@
ret = __qseecom_init_clk();
if (ret)
goto err;
+ ret = __qseecom_enable_clk();
+ if (ret) {
+ __qseecom_deinit_clk();
+ goto err;
+ }
qseecom_platform_support = (struct msm_bus_scale_pdata *)
msm_bus_cl_get_pdata(pdev);
} else {
@@ -1966,9 +2580,70 @@
static int __devinit qseecom_remove(struct platform_device *pdev)
{
+ struct qseecom_registered_kclient_list *kclient = NULL;
+ unsigned long flags = 0;
+ int ret = 0;
+
if (pdev->dev.platform_data != NULL)
msm_bus_scale_unregister_client(qsee_perf_client);
- return 0;
+
+ spin_lock_irqsave(&qseecom.registered_kclient_list_lock, flags);
+ kclient = list_entry((&qseecom.registered_kclient_list_head)->next,
+ struct qseecom_registered_kclient_list, list);
+ if (list_empty(&kclient->list)) {
+ spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock,
+ flags);
+ return 0;
+ }
+ list_for_each_entry(kclient, &qseecom.registered_kclient_list_head,
+ list) {
+ if (kclient)
+ list_del(&kclient->list);
+ break;
+ }
+ spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock, flags);
+
+
+ while (kclient->handle != NULL) {
+ ret = qseecom_unload_app(kclient->handle->dev);
+ if (ret == 0) {
+ kzfree(kclient->handle->dev);
+ kzfree(kclient->handle);
+ kzfree(kclient);
+ }
+ spin_lock_irqsave(&qseecom.registered_kclient_list_lock, flags);
+ kclient = list_entry(
+ (&qseecom.registered_kclient_list_head)->next,
+ struct qseecom_registered_kclient_list, list);
+ if (list_empty(&kclient->list)) {
+ spin_unlock_irqrestore(
+ &qseecom.registered_kclient_list_lock, flags);
+ return 0;
+ }
+ list_for_each_entry(kclient,
+ &qseecom.registered_kclient_list_head, list) {
+ if (kclient)
+ list_del(&kclient->list);
+ break;
+ }
+ spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock,
+ flags);
+ if (!kclient) {
+ ret = 0;
+ break;
+ }
+ }
+ if (qseecom.qseos_version > QSEEE_VERSION_00)
+ qseecom_unload_commonlib_image();
+
+ if (qsee_perf_client)
+ msm_bus_scale_client_update_request(qsee_perf_client, 0);
+ /* register client for bus scaling */
+ if (pdev->dev.of_node) {
+ __qseecom_disable_clk();
+ __qseecom_deinit_clk();
+ }
+ return ret;
};
static struct of_device_id qseecom_match[] = {
@@ -1995,9 +2670,6 @@
static void __devexit qseecom_exit(void)
{
-
- __qseecom_disable_clk();
-
device_destroy(driver_class, qseecom_device_no);
class_destroy(driver_class);
unregister_chrdev_region(qseecom_device_no, 1);
diff --git a/drivers/misc/qseecom_kernel.h b/drivers/misc/qseecom_kernel.h
new file mode 100644
index 0000000..0c93ef2
--- /dev/null
+++ b/drivers/misc/qseecom_kernel.h
@@ -0,0 +1,36 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QSEECOM_KERNEL_H_
+#define __QSEECOM_KERNEL_H_
+
+#include <linux/types.h>
+/*
+ * struct qseecom_handle -
+ * Handle to the qseecom device for kernel clients
+ * @sbuf - shared buffer pointer
+ * @sbbuf_len - shared buffer size
+ */
+struct qseecom_handle {
+ void *dev; /* in/out */
+ unsigned char *sbuf; /* in/out */
+ uint32_t sbuf_len; /* in/out */
+};
+
+int qseecom_start_app(struct qseecom_handle **handle,
+ char *app_name, uint32_t size);
+int qseecom_shutdown_app(struct qseecom_handle **handle);
+int qseecom_send_command(struct qseecom_handle *handle, void *send_buf,
+ uint32_t sbuf_len, void *resp_buf, uint32_t rbuf_len);
+int qseecom_set_bandwidth(struct qseecom_handle *handle, bool high);
+
+#endif /* __QSEECOM_KERNEL_H_ */
diff --git a/drivers/misc/ti_drv2667.c b/drivers/misc/ti_drv2667.c
new file mode 100644
index 0000000..554799c
--- /dev/null
+++ b/drivers/misc/ti_drv2667.c
@@ -0,0 +1,679 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/pm.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+#include <linux/i2c/ti_drv2667.h>
+#include "../staging/android/timed_output.h"
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#define DRV2667_SUS_LEVEL 1
+#endif
+
+#define DRV2667_STATUS_REG 0x00
+#define DRV2667_CNTL1_REG 0x01
+#define DRV2667_CNTL2_REG 0x02
+#define DRV2667_WAV_SEQ3_REG 0x03
+#define DRV2667_FIFO_REG 0x0B
+#define DRV2667_PAGE_REG 0xFF
+
+#define DRV2667_STANDBY_MASK 0xBF
+#define DRV2667_INPUT_MUX_MASK 0x04
+#define DRV2667_GAIN_MASK 0xFC
+#define DRV2667_GAIN_SHIFT 0
+#define DRV2667_TIMEOUT_MASK 0xF3
+#define DRV2667_TIMEOUT_SHIFT 2
+#define DRV2667_GO_MASK 0x01
+#define DRV2667_FIFO_SIZE 100
+#define DRV2667_VIB_START_VAL 0x7F
+#define DRV2667_REG_PAGE_ID 0x00
+#define DRV2667_FIFO_CHUNK_MS 10
+#define DRV2667_BYTES_PER_MS 8
+
+#define DRV2667_WAV_SEQ_ID_IDX 1
+#define DRV2667_WAV_SEQ_REP_IDX 6
+#define DRV2667_WAV_SEQ_FREQ_IDX 8
+#define DRV2667_WAV_SEQ_FREQ_MIN 8
+#define DRV2667_WAV_SEQ_DUR_IDX 9
+
+#define DRV2667_MIN_IDLE_TIMEOUT_MS 5
+#define DRV2667_MAX_IDLE_TIMEOUT_MS 20
+
+#define DRV2667_VTG_MIN_UV 3000000
+#define DRV2667_VTG_MAX_UV 5500000
+#define DRV2667_VTG_CURR_UA 24000
+#define DRV2667_I2C_VTG_MIN_UV 1800000
+#define DRV2667_I2C_VTG_MAX_UV 1800000
+#define DRV2667_I2C_CURR_UA 9630
+
+/* supports 3 modes in digital - fifo, ram and wave */
+enum drv2667_modes {
+ FIFO_MODE = 0,
+ RAM_SEQ_MODE,
+ WAV_SEQ_MODE,
+ ANALOG_MODE,
+};
+
+struct drv2667_data {
+ struct i2c_client *client;
+ struct timed_output_dev dev;
+ struct hrtimer timer;
+ struct work_struct work;
+ struct mutex lock;
+ struct regulator *vdd;
+ struct regulator *vdd_i2c;
+ u32 max_runtime_ms;
+ u32 runtime_left;
+ u8 buf[DRV2667_FIFO_SIZE + 1];
+ u8 cntl2_val;
+ enum drv2667_modes mode;
+ u32 time_chunk_ms;
+#ifdef CONFIG_HAS_EARLYSUSPEND
+ struct early_suspend es;
+#endif
+};
+
+static int drv2667_read_reg(struct i2c_client *client, u32 reg)
+{
+ int rc;
+
+ rc = i2c_smbus_read_byte_data(client, reg);
+ if (rc < 0)
+ dev_err(&client->dev, "i2c reg read for 0x%x failed\n", reg);
+ return rc;
+}
+
+static int drv2667_write_reg(struct i2c_client *client, u32 reg, u8 val)
+{
+ int rc;
+
+ rc = i2c_smbus_write_byte_data(client, reg, val);
+ if (rc < 0)
+ dev_err(&client->dev, "i2c reg write for 0x%xfailed\n", reg);
+
+ return rc;
+}
+
+static void drv2667_dump_regs(struct drv2667_data *data, char *label)
+{
+ dev_dbg(&data->client->dev,
+ "%s: reg0x00 = 0x%x, reg0x01 = 0x%x reg0x02 = 0x%x", label,
+ drv2667_read_reg(data->client, DRV2667_STATUS_REG),
+ drv2667_read_reg(data->client, DRV2667_CNTL1_REG),
+ drv2667_read_reg(data->client, DRV2667_CNTL2_REG));
+}
+
+static void drv2667_worker(struct work_struct *work)
+{
+ struct drv2667_data *data;
+ int rc = 0;
+ u8 val;
+
+ data = container_of(work, struct drv2667_data, work);
+
+ if (data->mode == WAV_SEQ_MODE) {
+ if (data->runtime_left)
+ val = data->cntl2_val | DRV2667_GO_MASK;
+ else
+ val = data->cntl2_val & ~DRV2667_GO_MASK;
+ rc = drv2667_write_reg(data->client, DRV2667_CNTL2_REG, val);
+ } else if (data->mode == FIFO_MODE) {
+ /* data is played at 8khz */
+ if (data->runtime_left < data->time_chunk_ms)
+ val = data->runtime_left * DRV2667_BYTES_PER_MS;
+ else
+ val = data->time_chunk_ms * DRV2667_BYTES_PER_MS;
+
+ rc = i2c_master_send(data->client, data->buf, val + 1);
+ }
+
+ if (rc < 0)
+ dev_err(&data->client->dev, "i2c send message failed\n");
+}
+
+static void drv2667_enable(struct timed_output_dev *dev, int runtime)
+{
+ struct drv2667_data *data = container_of(dev, struct drv2667_data, dev);
+ unsigned long time_ms;
+
+ if (runtime > data->max_runtime_ms) {
+ dev_dbg(&data->client->dev, "Invalid runtime\n");
+ runtime = data->max_runtime_ms;
+ }
+
+ mutex_lock(&data->lock);
+ hrtimer_cancel(&data->timer);
+ data->runtime_left = runtime;
+ if (data->runtime_left < data->time_chunk_ms)
+ time_ms = runtime * NSEC_PER_MSEC;
+ else
+ time_ms = data->time_chunk_ms * NSEC_PER_MSEC;
+ hrtimer_start(&data->timer, ktime_set(0, time_ms), HRTIMER_MODE_REL);
+ schedule_work(&data->work);
+ mutex_unlock(&data->lock);
+}
+
+static int drv2667_get_time(struct timed_output_dev *dev)
+{
+ struct drv2667_data *data = container_of(dev, struct drv2667_data, dev);
+
+ if (hrtimer_active(&data->timer))
+ return data->runtime_left +
+ ktime_to_ms(hrtimer_get_remaining(&data->timer));
+ return 0;
+}
+
+static enum hrtimer_restart drv2667_timer(struct hrtimer *timer)
+{
+ struct drv2667_data *data;
+ int time_ms;
+
+ data = container_of(timer, struct drv2667_data, timer);
+ if (data->runtime_left <= data->time_chunk_ms) {
+ data->runtime_left = 0;
+ schedule_work(&data->work);
+ return HRTIMER_NORESTART;
+ }
+
+ data->runtime_left -= data->time_chunk_ms;
+ if (data->runtime_left < data->time_chunk_ms)
+ time_ms = data->runtime_left * NSEC_PER_MSEC;
+ else
+ time_ms = data->time_chunk_ms * NSEC_PER_MSEC;
+
+ hrtimer_forward_now(&data->timer, ktime_set(0, time_ms));
+ schedule_work(&data->work);
+ return HRTIMER_RESTART;
+}
+
+static int drv2667_vreg_config(struct drv2667_data *data, bool on)
+{
+ int rc = 0;
+
+ if (!on)
+ goto deconfig_vreg;
+
+ data->vdd = regulator_get(&data->client->dev, "vdd");
+ if (IS_ERR(data->vdd)) {
+ rc = PTR_ERR(data->vdd);
+ dev_err(&data->client->dev, "unable to request vdd\n");
+ return rc;
+ }
+
+ if (regulator_count_voltages(data->vdd) > 0) {
+ rc = regulator_set_voltage(data->vdd,
+ DRV2667_VTG_MIN_UV, DRV2667_VTG_MAX_UV);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "vdd set voltage failed(%d)\n", rc);
+ goto put_vdd;
+ }
+ }
+
+ data->vdd_i2c = regulator_get(&data->client->dev, "vdd-i2c");
+ if (IS_ERR(data->vdd_i2c)) {
+ rc = PTR_ERR(data->vdd_i2c);
+ dev_err(&data->client->dev, "unable to request vdd for i2c\n");
+ goto reset_vdd_volt;
+ }
+
+ if (regulator_count_voltages(data->vdd_i2c) > 0) {
+ rc = regulator_set_voltage(data->vdd_i2c,
+ DRV2667_I2C_VTG_MIN_UV, DRV2667_I2C_VTG_MAX_UV);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "vdd_i2c set voltage failed(%d)\n", rc);
+ goto put_vdd_i2c;
+ }
+ }
+
+ return rc;
+
+deconfig_vreg:
+ if (regulator_count_voltages(data->vdd_i2c) > 0)
+ regulator_set_voltage(data->vdd_i2c, 0, DRV2667_I2C_VTG_MAX_UV);
+put_vdd_i2c:
+ regulator_put(data->vdd_i2c);
+reset_vdd_volt:
+ if (regulator_count_voltages(data->vdd) > 0)
+ regulator_set_voltage(data->vdd, 0, DRV2667_VTG_MAX_UV);
+put_vdd:
+ regulator_put(data->vdd);
+ return rc;
+}
+
+static int reg_set_optimum_mode_check(struct regulator *reg, int load_uA)
+{
+ return (regulator_count_voltages(reg) > 0) ?
+ regulator_set_optimum_mode(reg, load_uA) : 0;
+}
+
+
+static int drv2667_vreg_on(struct drv2667_data *data, bool on)
+{
+ int rc = 0;
+
+ if (!on)
+ goto vreg_off;
+
+ rc = reg_set_optimum_mode_check(data->vdd, DRV2667_VTG_CURR_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator vdd set_opt failed rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = regulator_enable(data->vdd);
+ if (rc < 0) {
+ dev_err(&data->client->dev, "enable vdd failed\n");
+ return rc;
+ }
+
+ rc = reg_set_optimum_mode_check(data->vdd_i2c, DRV2667_I2C_CURR_UA);
+ if (rc < 0) {
+ dev_err(&data->client->dev,
+ "Regulator vdd_i2c set_opt failed rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = regulator_enable(data->vdd_i2c);
+ if (rc < 0) {
+ dev_err(&data->client->dev, "enable vdd_i2c failed\n");
+ goto disable_vdd;
+ }
+
+ return rc;
+vreg_off:
+ regulator_disable(data->vdd_i2c);
+disable_vdd:
+ regulator_disable(data->vdd);
+ return rc;
+}
+
+#ifdef CONFIG_PM
+static int drv2667_suspend(struct device *dev)
+{
+ struct drv2667_data *data = dev_get_drvdata(dev);
+ u8 val;
+ int rc;
+
+ hrtimer_cancel(&data->timer);
+ cancel_work_sync(&data->work);
+
+ /* set standby */
+ val = data->cntl2_val | ~DRV2667_STANDBY_MASK;
+ rc = drv2667_write_reg(data->client, DRV2667_CNTL2_REG, val);
+ if (rc < 0)
+ dev_err(dev, "unable to set standby\n");
+
+ /* turn regulators off */
+ drv2667_vreg_on(data, false);
+ return 0;
+}
+
+static int drv2667_resume(struct device *dev)
+{
+ struct drv2667_data *data = dev_get_drvdata(dev);
+ int rc;
+
+ /* turn regulators on */
+ rc = drv2667_vreg_on(data, true);
+ if (rc < 0) {
+ dev_err(dev, "unable to turn regulators on\n");
+ return rc;
+ }
+
+ /* clear standby */
+ rc = drv2667_write_reg(data->client,
+ DRV2667_CNTL2_REG, data->cntl2_val);
+ if (rc < 0) {
+ dev_err(dev, "unable to clear standby\n");
+ goto vreg_off;
+ }
+
+ return 0;
+vreg_off:
+ drv2667_vreg_on(data, false);
+ return rc;
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void drv2667_early_suspend(struct early_suspend *es)
+{
+ struct drv2667_data *data = container_of(es, struct drv2667_data, es);
+
+ drv2667_suspend(&data->client->dev);
+}
+
+static void drv2667_late_resume(struct early_suspend *es)
+{
+ struct drv2667_data *data = container_of(es, struct drv2667_data, es);
+
+ drv2667_resume(&data->client->dev);
+}
+#endif
+
+static const struct dev_pm_ops drv2667_pm_ops = {
+#ifndef CONFIG_HAS_EARLYSUSPEND
+ .suspend = drv2667_suspend,
+ .resume = drv2667_resume,
+#endif
+};
+#endif
+
+#ifdef CONFIG_OF
+static int drv2667_parse_dt(struct device *dev, struct drv2667_pdata *pdata)
+{
+ struct property *prop;
+ int rc;
+ u32 temp;
+
+ rc = of_property_read_string(dev->of_node, "ti,label", &pdata->name);
+ /* set vibrator as default name */
+ if (rc < 0)
+ pdata->name = "vibrator";
+
+ rc = of_property_read_u32(dev->of_node, "ti,gain", &temp);
+ /* set gain as 0 */
+ if (rc < 0)
+ pdata->gain = 0;
+ else
+ pdata->gain = (u8) temp;
+
+ rc = of_property_read_u32(dev->of_node, "ti,mode", &temp);
+ /* set FIFO mode as default */
+ if (rc < 0)
+ pdata->mode = FIFO_MODE;
+ else
+ pdata->mode = (u8) temp;
+
+ /* read wave sequence */
+ if (pdata->mode == WAV_SEQ_MODE) {
+ prop = of_find_property(dev->of_node, "ti,wav-seq", &temp);
+ if (!prop) {
+ dev_err(dev, "wav seq data not found");
+ return -ENODEV;
+ } else if (temp != DRV2667_WAV_SEQ_LEN) {
+ dev_err(dev, "Invalid length of wav seq data\n");
+ return -EINVAL;
+ }
+ memcpy(pdata->wav_seq, prop->value, DRV2667_WAV_SEQ_LEN);
+ }
+
+ rc = of_property_read_u32(dev->of_node, "ti,idle-timeout-ms", &temp);
+ /* configure minimum idle timeout */
+ if (rc < 0)
+ pdata->idle_timeout_ms = DRV2667_MIN_IDLE_TIMEOUT_MS;
+ else
+ pdata->idle_timeout_ms = (u8) temp;
+
+ rc = of_property_read_u32(dev->of_node, "ti,max-runtime-ms",
+ &pdata->max_runtime_ms);
+ /* configure one sec as default time */
+ if (rc < 0)
+ pdata->max_runtime_ms = MSEC_PER_SEC;
+
+ return 0;
+}
+#else
+static int drv2667_parse_dt(struct device *dev, struct drv2667_pdata *pdata)
+{
+ return -ENODEV;
+}
+#endif
+
+static int __devinit drv2667_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct drv2667_data *data;
+ struct drv2667_pdata *pdata;
+ int rc, i;
+ u8 val, fifo_seq_val, reg;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ dev_err(&client->dev, "i2c is not supported\n");
+ return -EIO;
+ }
+
+ if (client->dev.of_node) {
+ pdata = devm_kzalloc(&client->dev,
+ sizeof(struct drv2667_pdata), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(&client->dev, "unable to allocate pdata\n");
+ return -ENOMEM;
+ }
+ /* parse DT */
+ rc = drv2667_parse_dt(&client->dev, pdata);
+ if (rc) {
+ dev_err(&client->dev, "DT parsing failed\n");
+ return rc;
+ }
+ } else {
+ pdata = client->dev.platform_data;
+ if (!pdata) {
+ dev_err(&client->dev, "invalid pdata\n");
+ return -EINVAL;
+ }
+ }
+
+ data = devm_kzalloc(&client->dev, sizeof(struct drv2667_data),
+ GFP_KERNEL);
+ if (!data) {
+ dev_err(&client->dev, "unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ i2c_set_clientdata(client, data);
+
+ data->client = client;
+ data->max_runtime_ms = pdata->max_runtime_ms;
+ mutex_init(&data->lock);
+ INIT_WORK(&data->work, drv2667_worker);
+ hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ data->timer.function = drv2667_timer;
+ data->mode = pdata->mode;
+
+ /* configure voltage regulators */
+ rc = drv2667_vreg_config(data, true);
+ if (rc) {
+ dev_err(&client->dev, "unable to configure regulators\n");
+ goto destroy_mutex;
+ }
+
+ /* turn on voltage regulators */
+ rc = drv2667_vreg_on(data, true);
+ if (rc) {
+ dev_err(&client->dev, "unable to turn on regulators\n");
+ goto deconfig_vreg;
+ }
+
+ rc = drv2667_read_reg(client, DRV2667_CNTL2_REG);
+ if (rc < 0)
+ goto vreg_off;
+
+ /* set timeout, clear standby */
+ val = (u8) rc;
+
+ if (pdata->idle_timeout_ms < DRV2667_MIN_IDLE_TIMEOUT_MS ||
+ pdata->idle_timeout_ms > DRV2667_MAX_IDLE_TIMEOUT_MS ||
+ (pdata->idle_timeout_ms % DRV2667_MIN_IDLE_TIMEOUT_MS)) {
+ dev_err(&client->dev, "Invalid idle timeout\n");
+ goto vreg_off;
+ }
+
+ val = (val & DRV2667_TIMEOUT_MASK) |
+ ((pdata->idle_timeout_ms / DRV2667_MIN_IDLE_TIMEOUT_MS - 1) <<
+ DRV2667_TIMEOUT_SHIFT);
+
+ val &= DRV2667_STANDBY_MASK;
+
+ rc = drv2667_write_reg(client, DRV2667_CNTL2_REG, val);
+ if (rc < 0)
+ goto vreg_off;
+
+ /* cache control2 val */
+ data->cntl2_val = val;
+
+ /* program drv2667 registers */
+ rc = drv2667_read_reg(client, DRV2667_CNTL1_REG);
+ if (rc < 0)
+ goto vreg_off;
+
+ /* gain and input mode */
+ val = (u8) rc;
+
+ /* remove this check after adding support for these modes */
+ if (data->mode == ANALOG_MODE || data->mode == RAM_SEQ_MODE) {
+ dev_err(&data->client->dev, "Mode not supported\n");
+ goto vreg_off;
+ } else
+ val &= ~DRV2667_INPUT_MUX_MASK; /* set digital mode */
+
+ val = (val & DRV2667_GAIN_MASK) | (pdata->gain << DRV2667_GAIN_SHIFT);
+
+ rc = drv2667_write_reg(client, DRV2667_CNTL1_REG, val);
+ if (rc < 0)
+ goto vreg_off;
+
+ if (data->mode == FIFO_MODE) {
+ /* Load a predefined pattern for FIFO mode */
+ data->buf[0] = DRV2667_FIFO_REG;
+ fifo_seq_val = DRV2667_VIB_START_VAL;
+
+ for (i = 1; i < DRV2667_FIFO_SIZE - 1; i++, fifo_seq_val++)
+ data->buf[i] = fifo_seq_val;
+
+ data->time_chunk_ms = DRV2667_FIFO_CHUNK_MS;
+ } else if (data->mode == WAV_SEQ_MODE) {
+ u8 freq, rep, dur;
+
+ /* program wave sequence from pdata */
+ /* id to wave sequence 3, set page */
+ rc = drv2667_write_reg(client, DRV2667_WAV_SEQ3_REG,
+ pdata->wav_seq[DRV2667_WAV_SEQ_ID_IDX]);
+ if (rc < 0)
+ goto vreg_off;
+
+ /* set page to wave form sequence */
+ rc = drv2667_write_reg(client, DRV2667_PAGE_REG,
+ pdata->wav_seq[DRV2667_WAV_SEQ_ID_IDX]);
+ if (rc < 0)
+ goto vreg_off;
+
+ /* program waveform sequence */
+ for (reg = 0, i = 1; i < DRV2667_WAV_SEQ_LEN - 1; i++, reg++) {
+ rc = drv2667_write_reg(client, reg, pdata->wav_seq[i]);
+ if (rc < 0)
+ goto vreg_off;
+ }
+
+ /* set page back to normal register space */
+ rc = drv2667_write_reg(client, DRV2667_PAGE_REG,
+ DRV2667_REG_PAGE_ID);
+ if (rc < 0)
+ goto vreg_off;
+
+ freq = pdata->wav_seq[DRV2667_WAV_SEQ_FREQ_IDX];
+ rep = pdata->wav_seq[DRV2667_WAV_SEQ_REP_IDX];
+ dur = pdata->wav_seq[DRV2667_WAV_SEQ_DUR_IDX];
+
+ data->time_chunk_ms = (rep * dur * MSEC_PER_SEC) /
+ (freq * DRV2667_WAV_SEQ_FREQ_MIN);
+ }
+
+ drv2667_dump_regs(data, "new");
+
+ /* register with timed output class */
+ data->dev.name = pdata->name;
+ data->dev.get_time = drv2667_get_time;
+ data->dev.enable = drv2667_enable;
+
+ rc = timed_output_dev_register(&data->dev);
+ if (rc) {
+ dev_err(&client->dev, "unable to register with timed_output\n");
+ goto vreg_off;
+ }
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+ data->es.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + DRV2667_SUS_LEVEL;
+ data->es.suspend = drv2667_early_suspend;
+ data->es.resume = drv2667_late_resume;
+ register_early_suspend(&data->es);
+#endif
+ return 0;
+
+vreg_off:
+ drv2667_vreg_on(data, false);
+deconfig_vreg:
+ drv2667_vreg_config(data, false);
+destroy_mutex:
+ mutex_destroy(&data->lock);
+ return rc;
+}
+
+static int __devexit drv2667_remove(struct i2c_client *client)
+{
+ struct drv2667_data *data = i2c_get_clientdata(client);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+ unregister_early_suspend(&data->es);
+#endif
+ mutex_destroy(&data->lock);
+ timed_output_dev_unregister(&data->dev);
+ hrtimer_cancel(&data->timer);
+ cancel_work_sync(&data->work);
+ drv2667_vreg_on(data, false);
+ drv2667_vreg_config(data, false);
+
+ return 0;
+}
+
+static const struct i2c_device_id drv2667_id_table[] = {
+ {"drv2667", 0},
+ { },
+};
+MODULE_DEVICE_TABLE(i2c, drv2667_id_table);
+
+#ifdef CONFIG_OF
+static const struct of_device_id drv2667_of_id_table[] = {
+ {.compatible = "ti, drv2667"},
+ { },
+};
+#else
+#define drv2667_of_id_table NULL
+#endif
+
+static struct i2c_driver drv2667_i2c_driver = {
+ .driver = {
+ .name = "drv2667",
+ .owner = THIS_MODULE,
+ .of_match_table = drv2667_of_id_table,
+#ifdef CONFIG_PM
+ .pm = &drv2667_pm_ops,
+#endif
+ },
+ .probe = drv2667_probe,
+ .remove = __devexit_p(drv2667_remove),
+ .id_table = drv2667_id_table,
+};
+
+module_i2c_driver(drv2667_i2c_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("TI DRV2667 chip driver");
diff --git a/drivers/misc/tspp.c b/drivers/misc/tspp.c
index 8a1e0da..3b678c5 100644
--- a/drivers/misc/tspp.c
+++ b/drivers/misc/tspp.c
@@ -103,29 +103,29 @@
/*
* TSPP register offsets
*/
-#define TSPP_RST 0x00
+#define TSPP_RST 0x00
#define TSPP_CLK_CONTROL 0x04
-#define TSPP_CONFIG 0x08
-#define TSPP_CONTROL 0x0C
+#define TSPP_CONFIG 0x08
+#define TSPP_CONTROL 0x0C
#define TSPP_PS_DISABLE 0x10
-#define TSPP_MSG_IRQ_STATUS 0x14
+#define TSPP_MSG_IRQ_STATUS 0x14
#define TSPP_MSG_IRQ_MASK 0x18
#define TSPP_IRQ_STATUS 0x1C
#define TSPP_IRQ_MASK 0x20
#define TSPP_IRQ_CLEAR 0x24
#define TSPP_PIPE_ERROR_STATUS(_n) (0x28 + (_n << 2))
-#define TSPP_STATUS 0x68
-#define TSPP_CURR_TSP_HEADER 0x6C
-#define TSPP_CURR_PID_FILTER 0x70
-#define TSPP_SYSTEM_KEY(_n) (0x74 + (_n << 2))
-#define TSPP_CBC_INIT_VAL(_n) (0x94 + (_n << 2))
-#define TSPP_DATA_KEY_RESET 0x9C
+#define TSPP_STATUS 0x68
+#define TSPP_CURR_TSP_HEADER 0x6C
+#define TSPP_CURR_PID_FILTER 0x70
+#define TSPP_SYSTEM_KEY(_n) (0x74 + (_n << 2))
+#define TSPP_CBC_INIT_VAL(_n) (0x94 + (_n << 2))
+#define TSPP_DATA_KEY_RESET 0x9C
#define TSPP_KEY_VALID 0xA0
#define TSPP_KEY_ERROR 0xA4
#define TSPP_TEST_CTRL 0xA8
-#define TSPP_VERSION 0xAC
+#define TSPP_VERSION 0xAC
#define TSPP_GENERICS 0xB0
-#define TSPP_NOP 0xB4
+#define TSPP_NOP 0xB4
/*
* Register bit definitions
@@ -172,30 +172,30 @@
#define TSPP_MSG_TSIF_0_IRQ BIT(0)
/* TSPP_IRQ_STATUS + TSPP_IRQ_MASK + TSPP_IRQ_CLEAR */
-#define TSPP_IRQ_STATUS_TSP_RD_CMPL BIT(19)
-#define TSPP_IRQ_STATUS_KEY_ERROR BIT(18)
+#define TSPP_IRQ_STATUS_TSP_RD_CMPL BIT(19)
+#define TSPP_IRQ_STATUS_KEY_ERROR BIT(18)
#define TSPP_IRQ_STATUS_KEY_SWITCHED_BAD BIT(17)
#define TSPP_IRQ_STATUS_KEY_SWITCHED BIT(16)
#define TSPP_IRQ_STATUS_PS_BROKEN(_n) BIT((_n))
/* TSPP_PIPE_ERROR_STATUS */
-#define TSPP_PIPE_PES_SYNC_ERROR BIT(3)
-#define TSPP_PIPE_PS_LENGTH_ERROR BIT(2)
+#define TSPP_PIPE_PES_SYNC_ERROR BIT(3)
+#define TSPP_PIPE_PS_LENGTH_ERROR BIT(2)
#define TSPP_PIPE_PS_CONTINUITY_ERROR BIT(1)
-#define TSPP_PIP_PS_LOST_START BIT(0)
+#define TSPP_PIP_PS_LOST_START BIT(0)
/* TSPP_STATUS */
-#define TSPP_STATUS_TSP_PKT_AVAIL BIT(10)
-#define TSPP_STATUS_TSIF1_DM_REQ BIT(6)
-#define TSPP_STATUS_TSIF0_DM_REQ BIT(2)
-#define TSPP_CURR_FILTER_TABLE BIT(0)
+#define TSPP_STATUS_TSP_PKT_AVAIL BIT(10)
+#define TSPP_STATUS_TSIF1_DM_REQ BIT(6)
+#define TSPP_STATUS_TSIF0_DM_REQ BIT(2)
+#define TSPP_CURR_FILTER_TABLE BIT(0)
/* TSPP_GENERICS */
-#define TSPP_GENERICS_CRYPTO_GEN BIT(12)
+#define TSPP_GENERICS_CRYPTO_GEN BIT(12)
#define TSPP_GENERICS_MAX_CONS_PIPES BIT(7)
-#define TSPP_GENERICS_MAX_PIPES BIT(2)
-#define TSPP_GENERICS_TSIF_1_GEN BIT(1)
-#define TSPP_GENERICS_TSIF_0_GEN BIT(0)
+#define TSPP_GENERICS_MAX_PIPES BIT(2)
+#define TSPP_GENERICS_TSIF_1_GEN BIT(1)
+#define TSPP_GENERICS_TSIF_0_GEN BIT(0)
/*
* TSPP memory regions
@@ -375,6 +375,8 @@
tspp_notifier *notifier; /* used only with kernel api */
void *notify_data; /* data to be passed with the notifier */
u32 notify_timer; /* notification for partially filled buffers */
+ tspp_memfree *memfree; /* user defined memory free function */
+ void *user_info; /* user cookie passed to memory alloc/free function */
};
struct tspp_pid_filter_table {
@@ -584,8 +586,7 @@
g = table + i;
tmp = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_DISABLE);
if (tmp) {
- pr_err("tspp_gpios_disable(0x%08x, GPIO_CFG_DISABLE)"
- " <%s> failed: %d\n",
+ pr_err("tspp_gpios_disable(0x%08x, GPIO_CFG_DISABLE) <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("tspp: pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
@@ -608,8 +609,7 @@
g = table + i;
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_ENABLE);
if (rc) {
- pr_err("tspp: gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE)"
- " <%s> failed: %d\n",
+ pr_err("tspp: gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE) <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("tspp: pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
@@ -820,12 +820,12 @@
desc->virt_base = alloc(channel_id, size,
&desc->phys_base, user);
} else {
- desc->virt_base = dma_alloc_coherent(NULL, size,
- &desc->phys_base, GFP_KERNEL);
- if (desc->virt_base == 0) {
- pr_err("tspp dma alloc coherent failed %i", size);
- return -ENOMEM;
- }
+ desc->virt_base = dma_alloc_coherent(NULL, size,
+ &desc->phys_base, GFP_KERNEL);
+ if (desc->virt_base == 0) {
+ pr_err("tspp dma alloc coherent failed %i", size);
+ return -ENOMEM;
+ }
}
desc->size = size;
@@ -977,9 +977,13 @@
channel->buffer_count = 0;
channel->filter_count = 0;
channel->int_freq = 1;
+ channel->src = TSPP_SOURCE_NONE;
+ channel->mode = TSPP_MODE_DISABLED;
channel->notifier = NULL;
channel->notify_data = NULL;
channel->notify_timer = 0;
+ channel->memfree = NULL;
+ channel->user_info = NULL;
init_waitqueue_head(&channel->in_queue);
if (cdev_add(&channel->cdev, tspp_minor++, 1) != 0) {
@@ -1002,6 +1006,11 @@
static int tspp_set_buffer_size(struct tspp_channel *channel,
struct tspp_buffer *buf)
{
+ if (channel->buffer_count > 0) {
+ pr_err("tspp: cannot set buffer size - buffers already allocated\n");
+ return -EPERM;
+ }
+
if (buf->size < TSPP_MIN_BUFFER_SIZE)
channel->buffer_size = TSPP_MIN_BUFFER_SIZE;
else if (buf->size > TSPP_MAX_BUFFER_SIZE)
@@ -1033,8 +1042,8 @@
}
static void tspp_set_signal_inversion(struct tspp_channel *channel,
- int clock_inverse, int data_inverse,
- int sync_inverse, int enable_inverse)
+ int clock_inverse, int data_inverse,
+ int sync_inverse, int enable_inverse)
{
int index;
@@ -1054,8 +1063,106 @@
channel->pdev->tsif[index].enable_inverse = enable_inverse;
}
+static int tspp_is_buffer_size_aligned(u32 size, enum tspp_mode mode)
+{
+ u32 alignment;
+
+ switch (mode) {
+ case TSPP_MODE_RAW:
+ /* must be a multiple of 192 */
+ alignment = (TSPP_PACKET_LENGTH + 4);
+ if (size % alignment)
+ return 0;
+ return 1;
+
+ case TSPP_MODE_RAW_NO_SUFFIX:
+ /* must be a multiple of 188 */
+ alignment = TSPP_PACKET_LENGTH;
+ if (size % alignment)
+ return 0;
+ return 1;
+
+ case TSPP_MODE_DISABLED:
+ case TSPP_MODE_PES:
+ default:
+ /* no alignment requirement */
+ return 1;
+ }
+
+}
+
+static u32 tspp_align_buffer_size_by_mode(u32 size, enum tspp_mode mode)
+{
+ u32 new_size;
+ u32 alignment;
+
+ switch (mode) {
+ case TSPP_MODE_RAW:
+ /* must be a multiple of 192 */
+ alignment = (TSPP_PACKET_LENGTH + 4);
+ break;
+
+ case TSPP_MODE_RAW_NO_SUFFIX:
+ /* must be a multiple of 188 */
+ alignment = TSPP_PACKET_LENGTH;
+ break;
+
+ case TSPP_MODE_DISABLED:
+ case TSPP_MODE_PES:
+ default:
+ /* no alignment requirement - give the user what he asks for */
+ alignment = 1;
+ break;
+ }
+ /* align up */
+ new_size = (((size + alignment - 1) / alignment) * alignment);
+ return new_size;
+}
+
+static void tspp_destroy_buffers(u32 channel_id, struct tspp_channel *channel)
+{
+ int i;
+ struct tspp_mem_buffer *pbuf, *temp;
+
+ pbuf = channel->data;
+ for (i = 0; i < channel->buffer_count; i++) {
+ if (pbuf->desc.phys_base) {
+ if (channel->memfree) {
+ channel->memfree(channel_id,
+ pbuf->desc.size,
+ pbuf->desc.virt_base,
+ pbuf->desc.phys_base,
+ channel->user_info);
+ } else {
+ dma_free_coherent(NULL,
+ pbuf->desc.size,
+ pbuf->desc.virt_base,
+ pbuf->desc.phys_base);
+ }
+ pbuf->desc.phys_base = 0;
+ }
+ pbuf->desc.virt_base = 0;
+ pbuf->state = TSPP_BUF_STATE_EMPTY;
+ temp = pbuf;
+ pbuf = pbuf->next;
+ kfree(temp);
+ }
+}
+
/*** TSPP API functions ***/
-int tspp_open_stream(u32 dev, u32 channel_id, struct tspp_select_source *source)
+
+/**
+ * tspp_open_stream - open a TSPP stream for use.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @source: stream source parameters.
+ *
+ * Return error status
+ *
+ */
+int tspp_open_stream(u32 dev, u32 channel_id,
+ struct tspp_select_source *source)
{
u32 val;
struct tspp_device *pdev;
@@ -1063,6 +1170,7 @@
TSPP_DEBUG("tspp_open_stream %i %i %i %i",
dev, channel_id, source->source, source->mode);
+
if (dev >= TSPP_MAX_DEVICES) {
pr_err("tspp: device id out of range");
return -ENODEV;
@@ -1082,8 +1190,8 @@
channel->src = source->source;
tspp_set_tsif_mode(channel, source->mode);
tspp_set_signal_inversion(channel, source->clk_inverse,
- source->data_inverse, source->sync_inverse,
- source->enable_inverse);
+ source->data_inverse, source->sync_inverse,
+ source->enable_inverse);
switch (source->source) {
case TSPP_SOURCE_TSIF0:
@@ -1120,6 +1228,15 @@
}
EXPORT_SYMBOL(tspp_open_stream);
+/**
+ * tspp_close_stream - close a TSPP stream.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ *
+ * Return error status
+ *
+ */
int tspp_close_stream(u32 dev, u32 channel_id)
{
u32 val;
@@ -1162,6 +1279,15 @@
}
EXPORT_SYMBOL(tspp_close_stream);
+/**
+ * tspp_open_channel - open a TSPP channel.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ *
+ * Return error status
+ *
+ */
int tspp_open_channel(u32 dev, u32 channel_id)
{
int rc = 0;
@@ -1269,6 +1395,15 @@
}
EXPORT_SYMBOL(tspp_open_channel);
+/**
+ * tspp_close_channel - close a TSPP channel.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ *
+ * Return error status
+ *
+ */
int tspp_close_channel(u32 dev, u32 channel_id)
{
int i;
@@ -1278,7 +1413,6 @@
struct sps_connect *config;
struct tspp_device *pdev;
struct tspp_channel *channel;
- struct tspp_mem_buffer *pbuf, *temp;
if (channel_id >= TSPP_NUM_CHANNELS) {
pr_err("tspp: channel id out of range");
@@ -1333,21 +1467,12 @@
dma_free_coherent(NULL, config->desc.size, config->desc.base,
config->desc.phys_base);
- pbuf = channel->data;
- for (i = 0; i < channel->buffer_count; i++) {
- if (pbuf->desc.phys_base) {
- dma_free_coherent(NULL,
- pbuf->desc.size,
- pbuf->desc.virt_base,
- pbuf->desc.phys_base);
- pbuf->desc.phys_base = 0;
- }
- pbuf->desc.virt_base = 0;
- pbuf->state = TSPP_BUF_STATE_EMPTY;
- temp = pbuf;
- pbuf = pbuf->next;
- kfree(temp);
- }
+ tspp_destroy_buffers(channel_id, channel);
+
+ channel->src = TSPP_SOURCE_NONE;
+ channel->mode = TSPP_MODE_DISABLED;
+ channel->memfree = NULL;
+ channel->user_info = NULL;
channel->buffer_count = 0;
channel->data = NULL;
channel->read = NULL;
@@ -1363,10 +1488,20 @@
}
EXPORT_SYMBOL(tspp_close_channel);
+/**
+ * tspp_add_filter - add a TSPP filter to a channel.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @filter: TSPP filter parameters
+ *
+ * Return error status
+ *
+ */
int tspp_add_filter(u32 dev, u32 channel_id,
struct tspp_filter *filter)
{
- int i;
+ int i, rc;
int other_channel;
int entry;
u32 val, pid, enabled;
@@ -1397,19 +1532,14 @@
return -ENOSR;
}
- /* make sure this filter mode matches the channel mode */
- switch (channel->mode) {
- case TSPP_MODE_DISABLED:
- channel->mode = filter->mode;
- break;
- case TSPP_MODE_RAW:
- case TSPP_MODE_PES:
- case TSPP_MODE_RAW_NO_SUFFIX:
- if (filter->mode != channel->mode) {
- pr_err("tspp: wrong filter mode");
- return -EBADSLT;
- }
- }
+ channel->mode = filter->mode;
+ /*
+ * if buffers are already allocated, verify they fulfil
+ * the alignment requirements.
+ */
+ if ((channel->buffer_count > 0) &&
+ (!tspp_is_buffer_size_aligned(channel->buffer_size, channel->mode)))
+ pr_warn("tspp: buffers allocated with incorrect alignment\n");
if (filter->mode == TSPP_MODE_PES) {
for (i = 0; i < TSPP_NUM_PRIORITIES; i++) {
@@ -1468,13 +1598,22 @@
pdev->filters[channel->src]->
filter[filter->priority].filter = p.filter;
- /* allocate buffers if needed */
- tspp_allocate_buffers(dev, channel->id, channel->max_buffers,
- channel->buffer_size, channel->int_freq, 0, 0);
- if (channel->buffer_count < MIN_ACCEPTABLE_BUFFER_COUNT) {
- pr_err("tspp: failed to allocate at least %i buffers",
- MIN_ACCEPTABLE_BUFFER_COUNT);
- return -ENOMEM;
+ /*
+ * allocate buffers if needed (i.e. if user did has not already called
+ * tspp_allocate_buffers() explicitly).
+ */
+ if (channel->buffer_count == 0) {
+ channel->buffer_size =
+ tspp_align_buffer_size_by_mode(channel->buffer_size,
+ channel->mode);
+ rc = tspp_allocate_buffers(dev, channel->id,
+ channel->max_buffers,
+ channel->buffer_size,
+ channel->int_freq, NULL, NULL, NULL);
+ if (rc != 0) {
+ pr_err("tspp: tspp_allocate_buffers failed\n");
+ return rc;
+ }
}
/* reenable pipe */
@@ -1489,6 +1628,16 @@
}
EXPORT_SYMBOL(tspp_add_filter);
+/**
+ * tspp_remove_filter - remove a TSPP filter from a channel.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @filter: TSPP filter parameters
+ *
+ * Return error status
+ *
+ */
int tspp_remove_filter(u32 dev, u32 channel_id,
struct tspp_filter *filter)
{
@@ -1541,6 +1690,16 @@
}
EXPORT_SYMBOL(tspp_remove_filter);
+/**
+ * tspp_set_key - set TSPP key in key table.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @key: TSPP key parameters
+ *
+ * Return error status
+ *
+ */
int tspp_set_key(u32 dev, u32 channel_id, struct tspp_key *key)
{
int i;
@@ -1591,6 +1750,18 @@
}
EXPORT_SYMBOL(tspp_set_key);
+/**
+ * tspp_register_notification - register TSPP channel notification function.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @pNotify: notification function
+ * @userdata: user data to pass to notification function
+ * @timer_ms: notification for partially filled buffers
+ *
+ * Return error status
+ *
+ */
int tspp_register_notification(u32 dev, u32 channel_id,
tspp_notifier *pNotify, void *userdata, u32 timer_ms)
{
@@ -1614,6 +1785,15 @@
}
EXPORT_SYMBOL(tspp_register_notification);
+/**
+ * tspp_unregister_notification - unregister TSPP channel notification function.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ *
+ * Return error status
+ *
+ */
int tspp_unregister_notification(u32 dev, u32 channel_id)
{
struct tspp_channel *channel;
@@ -1635,6 +1815,15 @@
}
EXPORT_SYMBOL(tspp_unregister_notification);
+/**
+ * tspp_get_buffer - get TSPP data buffer.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ *
+ * Return error status
+ *
+ */
const struct tspp_data_descriptor *tspp_get_buffer(u32 dev, u32 channel_id)
{
struct tspp_mem_buffer *buffer;
@@ -1675,6 +1864,16 @@
}
EXPORT_SYMBOL(tspp_get_buffer);
+/**
+ * tspp_release_buffer - release TSPP data buffer back to TSPP.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @descriptor_id: buffer descriptor ID
+ *
+ * Return error status
+ *
+ */
int tspp_release_buffer(u32 dev, u32 channel_id, u32 descriptor_id)
{
int i, found = 0;
@@ -1726,8 +1925,27 @@
}
EXPORT_SYMBOL(tspp_release_buffer);
-int tspp_allocate_buffers(u32 dev, u32 channel_id, u32 count,
- u32 size, u32 int_freq, tspp_allocator *alloc, void *user)
+/**
+ * tspp_allocate_buffers - allocate TSPP data buffers.
+ *
+ * @dev: TSPP device (up to TSPP_MAX_DEVICES)
+ * @channel_id: Channel ID number (up to TSPP_NUM_CHANNELS)
+ * @count: number of buffers to allocate
+ * @size: size of each buffer to allocate
+ * @int_freq: interrupt frequency
+ * @alloc: user defined memory allocator function. Pass NULL for default.
+ * @memfree: user defined memory free function. Pass NULL for default.
+ * @user: user data to pass to the memory allocator/free function
+ *
+ * Return error status
+ *
+ * The user can optionally call this function explicitly to allocate the TSPP
+ * data buffers. Alternatively, if the user did not call this function, it
+ * is called implicitly by tspp_add_filter().
+ */
+int tspp_allocate_buffers(u32 dev, u32 channel_id, u32 count, u32 size,
+ u32 int_freq, tspp_allocator *alloc,
+ tspp_memfree *memfree, void *user)
{
struct tspp_channel *channel;
struct tspp_device *pdev;
@@ -1736,56 +1954,62 @@
TSPP_DEBUG("tspp_allocate_buffers");
if (channel_id >= TSPP_NUM_CHANNELS) {
- pr_err("tspp: channel id out of range");
+ pr_err("%s: channel id out of range", __func__);
return -ECHRNG;
}
+
pdev = tspp_find_by_id(dev);
if (!pdev) {
- pr_err("tspp_alloc: can't find device %i", dev);
+ pr_err("%s: can't find device %i", __func__, dev);
return -ENODEV;
}
+
+ if (count < MIN_ACCEPTABLE_BUFFER_COUNT) {
+ pr_err("%s: tspp requires a minimum of %i buffers\n",
+ __func__, MIN_ACCEPTABLE_BUFFER_COUNT);
+ return -EINVAL;
+ }
+
channel = &pdev->channels[channel_id];
+ /* allow buffer allocation only if there was no previous buffer
+ * allocation for this channel.
+ */
+ if (channel->buffer_count > 0) {
+ pr_err("%s: buffers already allocated for channel %u",
+ __func__, channel_id);
+ return -EINVAL;
+ }
channel->max_buffers = count;
/* set up interrupt frequency */
- if (int_freq > channel->max_buffers)
+ if (int_freq > channel->max_buffers) {
int_freq = channel->max_buffers;
- channel->int_freq = int_freq;
-
- switch (channel->mode) {
- case TSPP_MODE_DISABLED:
- case TSPP_MODE_PES:
- /* give the user what he asks for */
- channel->buffer_size = size;
- break;
-
- case TSPP_MODE_RAW:
- /* must be a multiple of 192 */
- if (size < (TSPP_PACKET_LENGTH+4))
- channel->buffer_size = (TSPP_PACKET_LENGTH+4);
- else
- channel->buffer_size = (size /
- (TSPP_PACKET_LENGTH+4)) *
- (TSPP_PACKET_LENGTH+4);
- break;
-
- case TSPP_MODE_RAW_NO_SUFFIX:
- /* must be a multiple of 188 */
- channel->buffer_size = (size / TSPP_PACKET_LENGTH) *
- TSPP_PACKET_LENGTH;
- break;
+ pr_warn("%s: setting interrupt frequency to %u\n",
+ __func__, int_freq);
}
+ channel->int_freq = int_freq;
+ /*
+ * it is the responsibility of the caller to tspp_allocate_buffers(),
+ * whether it's the user or the driver, to make sure the size parameter
+ * is compatible to the channel mode.
+ */
+ channel->buffer_size = size;
- for (; channel->buffer_count < channel->max_buffers;
+ /* save user defined memory free function for later use */
+ channel->memfree = memfree;
+ channel->user_info = user;
+
+ for (channel->buffer_count = 0;
+ channel->buffer_count < channel->max_buffers;
channel->buffer_count++) {
/* allocate the descriptor */
struct tspp_mem_buffer *desc = (struct tspp_mem_buffer *)
kmalloc(sizeof(struct tspp_mem_buffer), GFP_KERNEL);
if (!desc) {
- pr_warn("tspp: Can't allocate desc %i",
- channel->buffer_count);
+ pr_warn("%s: Can't allocate desc %i",
+ __func__, channel->buffer_count);
break;
}
@@ -1794,8 +2018,8 @@
if (tspp_alloc_buffer(channel_id, &desc->desc,
channel->buffer_size, alloc, user) != 0) {
kfree(desc);
- pr_warn("tspp: Can't allocate buffer %i",
- channel->buffer_count);
+ pr_warn("%s: Can't allocate buffer %i",
+ __func__, channel->buffer_count);
break;
}
@@ -1818,12 +2042,24 @@
/* start the transfer */
if (tspp_queue_buffer(channel, desc))
- pr_err("tspp: can't queue buffer %i", desc->desc.id);
+ pr_err("%s: can't queue buffer %i",
+ __func__, desc->desc.id);
+ }
+
+ if (channel->buffer_count < channel->max_buffers) {
+ /*
+ * we failed to allocate the requested number of buffers.
+ * we don't allow a partial success, so need to clean up here.
+ */
+ tspp_destroy_buffers(channel_id, channel);
+ channel->buffer_count = 0;
+ return -ENOMEM;
}
channel->waiting = channel->data;
channel->read = channel->data;
channel->locked = channel->data;
+
return 0;
}
EXPORT_SYMBOL(tspp_allocate_buffers);
@@ -1942,8 +2178,10 @@
transferred += size;
buffer->read_index += size;
- /* after reading the end of the buffer, requeue it,
- and set up for reading the next one */
+ /*
+ * after reading the end of the buffer, requeue it,
+ * and set up for reading the next one
+ */
if (buffer->read_index == buffer->filled) {
buffer->state = TSPP_BUF_STATE_WAITING;
if (tspp_queue_buffer(channel, buffer))
@@ -2042,8 +2280,10 @@
pr_err("tspp: Unknown ioctl %i", param0);
}
- /* normalize the return code in case one of the subfunctions does
- something weird */
+ /*
+ * normalize the return code in case one of the subfunctions does
+ * something weird
+ */
if (rc != 0)
rc = -ENOIOCTLCMD;
@@ -2136,13 +2376,14 @@
{
int rc = -ENODEV;
u32 version;
- u32 i;
+ u32 i, j;
struct msm_tspp_platform_data *data;
struct tspp_device *device;
struct resource *mem_tsif0;
struct resource *mem_tsif1;
struct resource *mem_tspp;
struct resource *mem_bam;
+ struct tspp_channel *channel;
/* must have platform data */
data = pdev->dev.platform_data;
@@ -2338,6 +2579,12 @@
return 0;
err_channel:
+ /* uninitialize channels */
+ for (j = 0; j < i; j++) {
+ channel = &(device->channels[i]);
+ device_destroy(tspp_class, channel->cdev.dev);
+ cdev_del(&channel->cdev);
+ }
err_clock:
sps_deregister_bam_device(device->bam_handle);
err_bam:
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 91253ff..8810b46 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -1472,64 +1472,6 @@
}
EXPORT_SYMBOL(mmc_blk_init_packed_statistics);
-void print_mmc_packing_stats(struct mmc_card *card)
-{
- int i;
- int max_num_of_packed_reqs = 0;
-
- if ((!card) || (!card->wr_pack_stats.packing_events))
- return;
-
- max_num_of_packed_reqs = card->ext_csd.max_packed_writes;
-
- spin_lock(&card->wr_pack_stats.lock);
-
- pr_info("%s: write packing statistics:\n",
- mmc_hostname(card->host));
-
- for (i = 1 ; i <= max_num_of_packed_reqs ; ++i) {
- if (card->wr_pack_stats.packing_events[i] != 0)
- pr_info("%s: Packed %d reqs - %d times\n",
- mmc_hostname(card->host), i,
- card->wr_pack_stats.packing_events[i]);
- }
-
- pr_info("%s: stopped packing due to the following reasons:\n",
- mmc_hostname(card->host));
-
- if (card->wr_pack_stats.pack_stop_reason[EXCEEDS_SEGMENTS])
- pr_info("%s: %d times: exceedmax num of segments\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[EXCEEDS_SEGMENTS]);
- if (card->wr_pack_stats.pack_stop_reason[EXCEEDS_SECTORS])
- pr_info("%s: %d times: exceeding the max num of sectors\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[EXCEEDS_SECTORS]);
- if (card->wr_pack_stats.pack_stop_reason[WRONG_DATA_DIR])
- pr_info("%s: %d times: wrong data direction\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[WRONG_DATA_DIR]);
- if (card->wr_pack_stats.pack_stop_reason[FLUSH_OR_DISCARD])
- pr_info("%s: %d times: flush or discard\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[FLUSH_OR_DISCARD]);
- if (card->wr_pack_stats.pack_stop_reason[EMPTY_QUEUE])
- pr_info("%s: %d times: empty queue\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[EMPTY_QUEUE]);
- if (card->wr_pack_stats.pack_stop_reason[REL_WRITE])
- pr_info("%s: %d times: rel write\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[REL_WRITE]);
- if (card->wr_pack_stats.pack_stop_reason[THRESHOLD])
- pr_info("%s: %d times: Threshold\n",
- mmc_hostname(card->host),
- card->wr_pack_stats.pack_stop_reason[THRESHOLD]);
-
- spin_unlock(&card->wr_pack_stats.lock);
-}
-EXPORT_SYMBOL(print_mmc_packing_stats);
-
static u8 mmc_blk_prep_packed_list(struct mmc_queue *mq, struct request *req)
{
struct request_queue *q = mq->queue;
@@ -2059,7 +2001,8 @@
/* complete ongoing async transfer before issuing discard */
if (card->host->areq)
mmc_blk_issue_rw_rq(mq, NULL);
- if (req->cmd_flags & REQ_SECURE)
+ if (req->cmd_flags & REQ_SECURE &&
+ !(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN))
ret = mmc_blk_issue_secdiscard_rq(mq, req);
else
ret = mmc_blk_issue_discard_rq(mq, req);
@@ -2361,7 +2304,7 @@
ret = device_create_file(disk_to_dev(md->disk),
&md->num_wr_reqs_to_start_packing);
if (ret)
- goto power_ro_lock_fail;
+ goto num_wr_reqs_to_start_packing_fail;
md->min_sectors_to_check_bkops_status.show =
min_sectors_to_check_bkops_status_show;
@@ -2374,14 +2317,19 @@
ret = device_create_file(disk_to_dev(md->disk),
&md->min_sectors_to_check_bkops_status);
if (ret)
- goto power_ro_lock_fail;
+ goto min_sectors_to_check_bkops_status_fails;
return ret;
+min_sectors_to_check_bkops_status_fails:
+ device_remove_file(disk_to_dev(md->disk),
+ &md->num_wr_reqs_to_start_packing);
+num_wr_reqs_to_start_packing_fail:
+ device_remove_file(disk_to_dev(md->disk), &md->power_ro_lock);
power_ro_lock_fail:
- device_remove_file(disk_to_dev(md->disk), &md->force_ro);
+ device_remove_file(disk_to_dev(md->disk), &md->force_ro);
force_ro_fail:
- del_gendisk(md->disk);
+ del_gendisk(md->disk);
return ret;
}
@@ -2389,6 +2337,7 @@
#define CID_MANFID_SANDISK 0x2
#define CID_MANFID_TOSHIBA 0x11
#define CID_MANFID_MICRON 0x13
+#define CID_MANFID_SAMSUNG 0x15
static const struct mmc_fixup blk_fixups[] =
{
@@ -2429,6 +2378,28 @@
MMC_FIXUP("SEM04G", 0x45, CID_OEMID_ANY, add_quirk_mmc,
MMC_QUIRK_INAND_DATA_TIMEOUT),
+ /*
+ * On these Samsung MoviNAND parts, performing secure erase or
+ * secure trim can result in unrecoverable corruption due to a
+ * firmware bug.
+ */
+ MMC_FIXUP("M8G2FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("MAG4FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("MBG8FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("MCGAFA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("VAL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("VYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("KYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+ MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+
END_FIXUP
};
diff --git a/drivers/mmc/card/mmc_block_test.c b/drivers/mmc/card/mmc_block_test.c
index 2307d7a..35bb4ac 100644
--- a/drivers/mmc/card/mmc_block_test.c
+++ b/drivers/mmc/card/mmc_block_test.c
@@ -221,6 +221,63 @@
static struct mmc_block_test_data *mbtd;
+void print_mmc_packing_stats(struct mmc_card *card)
+{
+ int i;
+ int max_num_of_packed_reqs = 0;
+
+ if ((!card) || (!card->wr_pack_stats.packing_events))
+ return;
+
+ max_num_of_packed_reqs = card->ext_csd.max_packed_writes;
+
+ spin_lock(&card->wr_pack_stats.lock);
+
+ pr_info("%s: write packing statistics:\n",
+ mmc_hostname(card->host));
+
+ for (i = 1 ; i <= max_num_of_packed_reqs ; ++i) {
+ if (card->wr_pack_stats.packing_events[i] != 0)
+ pr_info("%s: Packed %d reqs - %d times\n",
+ mmc_hostname(card->host), i,
+ card->wr_pack_stats.packing_events[i]);
+ }
+
+ pr_info("%s: stopped packing due to the following reasons:\n",
+ mmc_hostname(card->host));
+
+ if (card->wr_pack_stats.pack_stop_reason[EXCEEDS_SEGMENTS])
+ pr_info("%s: %d times: exceedmax num of segments\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[EXCEEDS_SEGMENTS]);
+ if (card->wr_pack_stats.pack_stop_reason[EXCEEDS_SECTORS])
+ pr_info("%s: %d times: exceeding the max num of sectors\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[EXCEEDS_SECTORS]);
+ if (card->wr_pack_stats.pack_stop_reason[WRONG_DATA_DIR])
+ pr_info("%s: %d times: wrong data direction\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[WRONG_DATA_DIR]);
+ if (card->wr_pack_stats.pack_stop_reason[FLUSH_OR_DISCARD])
+ pr_info("%s: %d times: flush or discard\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[FLUSH_OR_DISCARD]);
+ if (card->wr_pack_stats.pack_stop_reason[EMPTY_QUEUE])
+ pr_info("%s: %d times: empty queue\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[EMPTY_QUEUE]);
+ if (card->wr_pack_stats.pack_stop_reason[REL_WRITE])
+ pr_info("%s: %d times: rel write\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[REL_WRITE]);
+ if (card->wr_pack_stats.pack_stop_reason[THRESHOLD])
+ pr_info("%s: %d times: Threshold\n",
+ mmc_hostname(card->host),
+ card->wr_pack_stats.pack_stop_reason[THRESHOLD]);
+
+ spin_unlock(&card->wr_pack_stats.lock);
+}
+
/*
* A callback assigned to the packed_test_fn field.
* Called from block layer in mmc_blk_packed_hdr_wrq_prep.
@@ -497,105 +554,105 @@
return NULL;
}
- switch (td->test_info.testcase) {
+switch (td->test_info.testcase) {
case TEST_STOP_DUE_TO_FLUSH:
- return "Test stop due to flush";
+ return "\"stop due to flush\"";
case TEST_STOP_DUE_TO_FLUSH_AFTER_MAX_REQS:
- return "Test stop due to flush after max-1 reqs";
+ return "\"stop due to flush after max-1 reqs\"";
case TEST_STOP_DUE_TO_READ:
- return "Test stop due to read";
+ return "\"stop due to read\"";
case TEST_STOP_DUE_TO_READ_AFTER_MAX_REQS:
- return "Test stop due to read after max-1 reqs";
+ return "\"stop due to read after max-1 reqs\"";
case TEST_STOP_DUE_TO_EMPTY_QUEUE:
- return "Test stop due to empty queue";
+ return "\"stop due to empty queue\"";
case TEST_STOP_DUE_TO_MAX_REQ_NUM:
- return "Test stop due to max req num";
+ return "\"stop due to max req num\"";
case TEST_STOP_DUE_TO_THRESHOLD:
- return "Test stop due to exceeding threshold";
+ return "\"stop due to exceeding threshold\"";
case TEST_RET_ABORT:
- return "Test err_check return abort";
+ return "\"err_check return abort\"";
case TEST_RET_PARTIAL_FOLLOWED_BY_SUCCESS:
- return "Test err_check return partial followed by success";
+ return "\"err_check return partial followed by success\"";
case TEST_RET_PARTIAL_FOLLOWED_BY_ABORT:
- return "Test err_check return partial followed by abort";
+ return "\"err_check return partial followed by abort\"";
case TEST_RET_PARTIAL_MULTIPLE_UNTIL_SUCCESS:
- return "Test err_check return partial multiple until success";
+ return "\"err_check return partial multiple until success\"";
case TEST_RET_PARTIAL_MAX_FAIL_IDX:
- return "Test err_check return partial max fail index";
+ return "\"err_check return partial max fail index\"";
case TEST_RET_RETRY:
- return "Test err_check return retry";
+ return "\"err_check return retry\"";
case TEST_RET_CMD_ERR:
- return "Test err_check return cmd error";
+ return "\"err_check return cmd error\"";
case TEST_RET_DATA_ERR:
- return "Test err_check return data error";
+ return "\"err_check return data error\"";
case TEST_HDR_INVALID_VERSION:
- return "Test invalid - wrong header version";
+ return "\"invalid - wrong header version\"";
case TEST_HDR_WRONG_WRITE_CODE:
- return "Test invalid - wrong write code";
+ return "\"invalid - wrong write code\"";
case TEST_HDR_INVALID_RW_CODE:
- return "Test invalid - wrong R/W code";
+ return "\"invalid - wrong R/W code\"";
case TEST_HDR_DIFFERENT_ADDRESSES:
- return "Test invalid - header different addresses";
+ return "\"invalid - header different addresses\"";
case TEST_HDR_REQ_NUM_SMALLER_THAN_ACTUAL:
- return "Test invalid - header req num smaller than actual";
+ return "\"invalid - header req num smaller than actual\"";
case TEST_HDR_REQ_NUM_LARGER_THAN_ACTUAL:
- return "Test invalid - header req num larger than actual";
+ return "\"invalid - header req num larger than actual\"";
case TEST_HDR_CMD23_PACKED_BIT_SET:
- return "Test invalid - header cmd23 packed bit set";
+ return "\"invalid - header cmd23 packed bit set\"";
case TEST_CMD23_MAX_PACKED_WRITES:
- return "Test invalid - cmd23 max packed writes";
+ return "\"invalid - cmd23 max packed writes\"";
case TEST_CMD23_ZERO_PACKED_WRITES:
- return "Test invalid - cmd23 zero packed writes";
+ return "\"invalid - cmd23 zero packed writes\"";
case TEST_CMD23_PACKED_BIT_UNSET:
- return "Test invalid - cmd23 packed bit unset";
+ return "\"invalid - cmd23 packed bit unset\"";
case TEST_CMD23_REL_WR_BIT_SET:
- return "Test invalid - cmd23 rel wr bit set";
+ return "\"invalid - cmd23 rel wr bit set\"";
case TEST_CMD23_BITS_16TO29_SET:
- return "Test invalid - cmd23 bits [16-29] set";
+ return "\"invalid - cmd23 bits [16-29] set\"";
case TEST_CMD23_HDR_BLK_NOT_IN_COUNT:
- return "Test invalid - cmd23 header block not in count";
+ return "\"invalid - cmd23 header block not in count\"";
case TEST_PACKING_EXP_N_OVER_TRIGGER:
- return "\nTest packing control - pack n";
+ return "\"packing control - pack n\"";
case TEST_PACKING_EXP_N_OVER_TRIGGER_FB_READ:
- return "\nTest packing control - pack n followed by read";
+ return "\"packing control - pack n followed by read\"";
case TEST_PACKING_EXP_N_OVER_TRIGGER_FLUSH_N:
- return "\nTest packing control - pack n followed by flush";
+ return "\"packing control - pack n followed by flush\"";
case TEST_PACKING_EXP_ONE_OVER_TRIGGER_FB_READ:
- return "\nTest packing control - pack one followed by read";
+ return "\"packing control - pack one followed by read\"";
case TEST_PACKING_EXP_THRESHOLD_OVER_TRIGGER:
- return "\nTest packing control - pack threshold";
+ return "\"packing control - pack threshold\"";
case TEST_PACKING_NOT_EXP_LESS_THAN_TRIGGER_REQUESTS:
- return "\nTest packing control - no packing";
+ return "\"packing control - no packing\"";
case TEST_PACKING_NOT_EXP_TRIGGER_REQUESTS:
- return "\nTest packing control - no packing, trigger requests";
+ return "\"packing control - no packing, trigger requests\"";
case TEST_PACKING_NOT_EXP_TRIGGER_READ_TRIGGER:
- return "\nTest packing control - no pack, trigger-read-trigger";
+ return "\"packing control - no pack, trigger-read-trigger\"";
case TEST_PACKING_NOT_EXP_TRIGGER_FLUSH_TRIGGER:
- return "\nTest packing control- no pack, trigger-flush-trigger";
+ return "\"packing control- no pack, trigger-flush-trigger\"";
case TEST_PACK_MIX_PACKED_NO_PACKED_PACKED:
- return "\nTest packing control - mix: pack -> no pack -> pack";
+ return "\"packing control - mix: pack -> no pack -> pack\"";
case TEST_PACK_MIX_NO_PACKED_PACKED_NO_PACKED:
- return "\nTest packing control - mix: no pack->pack->no pack";
+ return "\"packing control - mix: no pack->pack->no pack\"";
case TEST_WRITE_DISCARD_SANITIZE_READ:
- return "\nTest write, discard, sanitize";
+ return "\"write, discard, sanitize\"";
case BKOPS_DELAYED_WORK_LEVEL_1:
- return "\nTest delayed work BKOPS level 1";
+ return "\"delayed work BKOPS level 1\"";
case BKOPS_DELAYED_WORK_LEVEL_1_HPI:
- return "\nTest delayed work BKOPS level 1 with HPI";
+ return "\"delayed work BKOPS level 1 with HPI\"";
case BKOPS_CANCEL_DELAYED_WORK:
- return "\nTest cancel delayed BKOPS work";
+ return "\"cancel delayed BKOPS work\"";
case BKOPS_URGENT_LEVEL_2:
- return "\nTest urgent BKOPS level 2";
+ return "\"urgent BKOPS level 2\"";
case BKOPS_URGENT_LEVEL_2_TWO_REQS:
- return "\nTest urgent BKOPS level 2, followed by a request";
+ return "\"urgent BKOPS level 2, followed by a request\"";
case BKOPS_URGENT_LEVEL_3:
- return "\nTest urgent BKOPS level 3";
+ return "\"urgent BKOPS level 3\"";
case TEST_LONG_SEQUENTIAL_READ:
- return "Test long sequential read";
+ return "\"long sequential read\"";
case TEST_LONG_SEQUENTIAL_WRITE:
- return "Test long sequential write";
+ return "\"long sequential write\"";
default:
- return "Unknown testcase";
+ return " Unknown testcase";
}
return NULL;
diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index 85d2737..de87e82 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -25,6 +25,7 @@
int (*power_save)(struct mmc_host *);
int (*power_restore)(struct mmc_host *);
int (*alive)(struct mmc_host *);
+ int (*change_bus_speed)(struct mmc_host *, unsigned long *);
};
void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops);
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index ddb562e..84a26a1 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -186,6 +186,46 @@
DEFINE_SIMPLE_ATTRIBUTE(mmc_clock_fops, mmc_clock_opt_get, mmc_clock_opt_set,
"%llu\n");
+static int mmc_max_clock_get(void *data, u64 *val)
+{
+ struct mmc_host *host = data;
+
+ if (!host)
+ return -EINVAL;
+
+ *val = host->f_max;
+
+ return 0;
+}
+
+static int mmc_max_clock_set(void *data, u64 val)
+{
+ struct mmc_host *host = data;
+ int err = -EINVAL;
+ unsigned long freq = val;
+ unsigned int old_freq;
+
+ if (!host || (val < host->f_min))
+ goto out;
+
+ mmc_claim_host(host);
+ if (host->bus_ops && host->bus_ops->change_bus_speed) {
+ old_freq = host->f_max;
+ host->f_max = freq;
+
+ err = host->bus_ops->change_bus_speed(host, &freq);
+
+ if (err)
+ host->f_max = old_freq;
+ }
+ mmc_release_host(host);
+out:
+ return err;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(mmc_max_clock_fops, mmc_max_clock_get,
+ mmc_max_clock_set, "%llu\n");
+
void mmc_add_host_debugfs(struct mmc_host *host)
{
struct dentry *root;
@@ -208,6 +248,10 @@
&mmc_clock_fops))
goto err_node;
+ if (!debugfs_create_file("max_clock", S_IRUSR | S_IWUSR, root, host,
+ &mmc_max_clock_fops))
+ goto err_node;
+
#ifdef CONFIG_MMC_CLKGATE
if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR),
root, &host->clk_delay))
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 47fd9b9..a98ed3d 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -479,11 +479,11 @@
else
card->ext_csd.bkops_en = 1;
}
- if (!card->ext_csd.bkops_en)
- pr_info("%s: BKOPS_EN bit is not set\n",
- mmc_hostname(card->host));
}
+ pr_info("%s: BKOPS_EN bit = %d\n",
+ mmc_hostname(card->host), card->ext_csd.bkops_en);
+
/* check whether the eMMC card supports HPI */
if (ext_csd[EXT_CSD_HPI_FEATURES] & 0x1) {
card->ext_csd.hpi = 1;
@@ -821,6 +821,69 @@
return err;
}
+/**
+ * mmc_change_bus_speed() - Change MMC card bus frequency at runtime
+ * @host: pointer to mmc host structure
+ * @freq: pointer to desired frequency to be set
+ *
+ * Change the MMC card bus frequency at runtime after the card is
+ * initialized. Callers are expected to make sure of the card's
+ * state (DATA/RCV/TRANSFER) beforing changing the frequency at runtime.
+ *
+ * If the frequency to change is greater than max. supported by card,
+ * *freq is changed to max. supported by card and if it is less than min.
+ * supported by host, *freq is changed to min. supported by host.
+ */
+static int mmc_change_bus_speed(struct mmc_host *host, unsigned long *freq)
+{
+ int err = 0;
+ struct mmc_card *card;
+
+ mmc_claim_host(host);
+ /*
+ * Assign card pointer after claiming host to avoid race
+ * conditions that may arise during removal of the card.
+ */
+ card = host->card;
+
+ if (!card || !freq) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (mmc_card_highspeed(card) || mmc_card_hs200(card)
+ || mmc_card_ddr_mode(card)) {
+ if (*freq > card->ext_csd.hs_max_dtr)
+ *freq = card->ext_csd.hs_max_dtr;
+ } else if (*freq > card->csd.max_dtr) {
+ *freq = card->csd.max_dtr;
+ }
+
+ if (*freq < host->f_min)
+ *freq = host->f_min;
+
+ mmc_set_clock(host, (unsigned int) (*freq));
+
+ if (mmc_card_hs200(card) && card->host->ops->execute_tuning) {
+ /*
+ * We try to probe host driver for tuning for any
+ * frequency, it is host driver responsibility to
+ * perform actual tuning only when required.
+ */
+ mmc_host_clk_hold(card->host);
+ err = card->host->ops->execute_tuning(card->host,
+ MMC_SEND_TUNING_BLOCK_HS200);
+ mmc_host_clk_release(card->host);
+
+ if (err)
+ pr_warn("%s: %s: tuning execution failed %d\n",
+ mmc_hostname(card->host), __func__, err);
+ }
+out:
+ mmc_release_host(host);
+ return err;
+}
+
/*
* Handle the detection and initialisation of a card.
*
@@ -1531,6 +1594,7 @@
.resume = NULL,
.power_restore = mmc_power_restore,
.alive = mmc_alive,
+ .change_bus_speed = mmc_change_bus_speed,
};
static const struct mmc_bus_ops mmc_ops_unsafe = {
@@ -1542,6 +1606,7 @@
.resume = mmc_resume,
.power_restore = mmc_power_restore,
.alive = mmc_alive,
+ .change_bus_speed = mmc_change_bus_speed,
};
static void mmc_attach_bus_ops(struct mmc_host *host)
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index ff5821b..8661929 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -609,6 +609,72 @@
return 0;
}
+/**
+ * mmc_sd_change_bus_speed() - Change SD card bus frequency at runtime
+ * @host: pointer to mmc host structure
+ * @freq: pointer to desired frequency to be set
+ *
+ * Change the SD card bus frequency at runtime after the card is
+ * initialized. Callers are expected to make sure of the card's
+ * state (DATA/RCV/TRANSFER) beforing changing the frequency at runtime.
+ *
+ * If the frequency to change is greater than max. supported by card,
+ * *freq is changed to max. supported by card and if it is less than min.
+ * supported by host, *freq is changed to min. supported by host.
+ */
+static int mmc_sd_change_bus_speed(struct mmc_host *host, unsigned long *freq)
+{
+ int err = 0;
+ struct mmc_card *card;
+
+ mmc_claim_host(host);
+ /*
+ * Assign card pointer after claiming host to avoid race
+ * conditions that may arise during removal of the card.
+ */
+ card = host->card;
+
+ /* sanity checks */
+ if (!card || !freq) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (mmc_card_uhs(card)) {
+ if (*freq > card->sw_caps.uhs_max_dtr)
+ *freq = card->sw_caps.uhs_max_dtr;
+ } else {
+ if (*freq > mmc_sd_get_max_clock(card))
+ *freq = mmc_sd_get_max_clock(card);
+ }
+
+ if (*freq < host->f_min)
+ *freq = host->f_min;
+
+ mmc_set_clock(host, (unsigned int) (*freq));
+
+ if (!mmc_host_is_spi(card->host) && mmc_sd_card_uhs(card)
+ && card->host->ops->execute_tuning) {
+ /*
+ * We try to probe host driver for tuning for any
+ * frequency, it is host driver responsibility to
+ * perform actual tuning only when required.
+ */
+ mmc_host_clk_hold(card->host);
+ err = card->host->ops->execute_tuning(card->host,
+ MMC_SEND_TUNING_BLOCK);
+ mmc_host_clk_release(card->host);
+
+ if (err)
+ pr_warn("%s: %s: tuning execution failed %d\n",
+ mmc_hostname(card->host), __func__, err);
+ }
+
+out:
+ mmc_release_host(host);
+ return err;
+}
+
/*
* UHS-I specific initialization procedure
*/
@@ -1191,6 +1257,7 @@
.resume = NULL,
.power_restore = mmc_sd_power_restore,
.alive = mmc_sd_alive,
+ .change_bus_speed = mmc_sd_change_bus_speed,
};
static const struct mmc_bus_ops mmc_sd_ops_unsafe = {
@@ -1200,6 +1267,7 @@
.resume = mmc_sd_resume,
.power_restore = mmc_sd_power_restore,
.alive = mmc_sd_alive,
+ .change_bus_speed = mmc_sd_change_bus_speed,
};
static void mmc_sd_attach_bus_ops(struct mmc_host *host)
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 49bbe09..de7e5bc 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -76,6 +76,7 @@
#define SPS_MIN_XFER_SIZE MCI_FIFOSIZE
#define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */
+#define INVALID_TUNING_PHASE -1
#if defined(CONFIG_DEBUG_FS)
static void msmsdcc_dbg_createhost(struct msmsdcc_host *);
@@ -158,6 +159,8 @@
static void msmsdcc_sg_start(struct msmsdcc_host *host);
static int msmsdcc_vreg_reset(struct msmsdcc_host *host);
static int msmsdcc_runtime_resume(struct device *dev);
+static int msmsdcc_dt_get_array(struct device *dev, const char *prop_name,
+ u32 **out_array, int *len, int size);
static inline unsigned short msmsdcc_get_nr_sg(struct msmsdcc_host *host)
{
@@ -944,7 +947,7 @@
if ((host->dma.channel == -1) || (host->dma.crci == -1))
return -ENOENT;
- BUG_ON((host->pdev_id < 1) || (host->pdev_id > 5));
+ BUG_ON((host->pdev->id < 1) || (host->pdev->id > 5));
host->dma.sg = data->sg;
host->dma.num_ents = data->sg_len;
@@ -1379,6 +1382,9 @@
(host->tuning_in_progress &&
(opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
opcode == MMC_SEND_TUNING_BLOCK)))) {
+ /* Execute full tuning in case of CRC/timeout errors */
+ host->saved_tuning_phase = INVALID_TUNING_PHASE;
+
if (status & MCI_DATACRCFAIL) {
pr_err("%s: Data CRC error\n",
mmc_hostname(host->mmc));
@@ -1757,6 +1763,8 @@
pr_err("%s: CMD%d: Command CRC error\n",
mmc_hostname(host->mmc), cmd->opcode);
msmsdcc_dump_sdcc_state(host);
+ /* Execute full tuning in case of CRC errors */
+ host->saved_tuning_phase = INVALID_TUNING_PHASE;
cmd->error = -EILSEQ;
}
@@ -2215,7 +2223,9 @@
}
if ((mrq->cmd->opcode == MMC_WRITE_BLOCK) ||
- (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK))
+ (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) ||
+ ((mrq->cmd->opcode == SD_IO_RW_EXTENDED) &&
+ is_data_pend_for_cmd53(host)))
host->curr.use_wr_data_pend = true;
}
@@ -2347,7 +2357,7 @@
rc = msmsdcc_vreg_reset(host);
if (rc)
pr_err("msmsdcc.%d vreg reset failed (%d)\n",
- host->pdev_id, rc);
+ host->pdev->id, rc);
goto out;
} else {
/* Deregister all regulators from regulator framework */
@@ -2977,6 +2987,27 @@
int rc = 0;
struct msm_bus_scale_pdata *use_cases;
+ if (host->pdev->dev.of_node) {
+ struct msm_mmc_bus_voting_data *data;
+ struct device *dev = &host->pdev->dev;
+
+ data = devm_kzalloc(dev,
+ sizeof(struct msm_mmc_bus_voting_data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&host->pdev->dev,
+ "%s: failed to allocate memory\n", __func__);
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ rc = msmsdcc_dt_get_array(dev, "qcom,bus-bw-vectors-bps",
+ &data->bw_vecs, &data->bw_vecs_size, 0);
+ if (!rc) {
+ data->use_cases = msm_bus_cl_get_pdata(host->pdev);
+ host->plat->msm_bus_voting_data = data;
+ }
+ }
+
if (host->plat->msm_bus_voting_data &&
host->plat->msm_bus_voting_data->use_cases &&
host->plat->msm_bus_voting_data->bw_vecs &&
@@ -2999,7 +3030,7 @@
host->msm_bus_vote.max_bw_vote =
msmsdcc_msm_bus_get_vote_for_bw(host, UINT_MAX);
}
-
+out:
return rc;
}
@@ -4030,6 +4061,7 @@
u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
const u32 *tuning_block_pattern = tuning_block_64;
int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */
+ bool is_tuning_all_phases;
pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__);
@@ -4063,7 +4095,13 @@
goto out;
}
- phase = 0;
+ is_tuning_all_phases = !(host->mmc->card &&
+ (host->saved_tuning_phase != INVALID_TUNING_PHASE));
+retry:
+ if (is_tuning_all_phases)
+ phase = 0; /* start from phase 0 during init */
+ else
+ phase = (u8)host->saved_tuning_phase;
do {
struct mmc_command cmd = {0};
struct mmc_data data = {0};
@@ -4095,9 +4133,16 @@
if (!cmd.error && !data.error &&
!memcmp(data_buf, tuning_block_pattern, size)) {
/* tuning is successful at this tuning point */
+ if (!is_tuning_all_phases)
+ goto kfree;
tuned_phases[tuned_phase_cnt++] = phase;
pr_debug("%s: %s: found good phase = %d\n",
mmc_hostname(mmc), __func__, phase);
+ } else if (!is_tuning_all_phases) {
+ pr_debug("%s: tuning failed at saved phase (%d), retrying\n",
+ mmc_hostname(mmc), (u32)phase);
+ is_tuning_all_phases = true;
+ goto retry;
}
} while (++phase < 16);
@@ -4116,6 +4161,8 @@
rc = msmsdcc_config_cm_sdc4_dll_phase(host, phase);
if (rc)
goto kfree;
+ else
+ host->saved_tuning_phase = phase;
pr_debug("%s: %s: finally setting the tuning phase to %d\n",
mmc_hostname(mmc), __func__, phase);
} else {
@@ -5224,7 +5271,7 @@
pull_data->on = pull;
pull_data->off = pull + pull_data->size;
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-pad-pull-on",
+ ret = msmsdcc_dt_get_array(dev, "qcom,pad-pull-on",
&tmp, &len, pull_data->size);
if (!ret) {
for (i = 0; i < len; i++) {
@@ -5237,7 +5284,7 @@
goto err;
}
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-pad-pull-off",
+ ret = msmsdcc_dt_get_array(dev, "qcom,pad-pull-off",
&tmp, &len, pull_data->size);
if (!ret) {
for (i = 0; i < len; i++) {
@@ -5302,7 +5349,7 @@
drv_data->on = drv;
drv_data->off = drv + drv_data->size;
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-pad-drv-on",
+ ret = msmsdcc_dt_get_array(dev, "qcom,pad-drv-on",
&tmp, &len, drv_data->size);
if (!ret) {
for (i = 0; i < len; i++) {
@@ -5315,7 +5362,7 @@
goto err;
}
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-pad-drv-off",
+ ret = msmsdcc_dt_get_array(dev, "qcom,pad-drv-off",
&tmp, &len, drv_data->size);
if (!ret) {
for (i = 0; i < len; i++) {
@@ -5395,7 +5442,7 @@
char result[32];
pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i);
of_property_read_string_index(np,
- "qcom,sdcc-gpio-names", i, &name);
+ "qcom,gpio-names", i, &name);
snprintf(result, 32, "%s-%s",
dev_name(dev), name ? name : "?");
@@ -5454,17 +5501,17 @@
vreg->name = vreg_name;
snprintf(prop_name, MAX_PROP_SIZE,
- "qcom,sdcc-%s-always_on", vreg_name);
+ "qcom,%s-always-on", vreg_name);
if (of_get_property(np, prop_name, NULL))
vreg->always_on = true;
snprintf(prop_name, MAX_PROP_SIZE,
- "qcom,sdcc-%s-lpm_sup", vreg_name);
+ "qcom,%s-lpm-sup", vreg_name);
if (of_get_property(np, prop_name, NULL))
vreg->lpm_sup = true;
snprintf(prop_name, MAX_PROP_SIZE,
- "qcom,sdcc-%s-voltage_level", vreg_name);
+ "qcom,%s-voltage-level", vreg_name);
prop = of_get_property(np, prop_name, &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_warn(dev, "%s %s property\n",
@@ -5475,7 +5522,7 @@
}
snprintf(prop_name, MAX_PROP_SIZE,
- "qcom,sdcc-%s-current_level", vreg_name);
+ "qcom,%s-current-level", vreg_name);
prop = of_get_property(np, prop_name, &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_warn(dev, "%s %s property\n",
@@ -5511,7 +5558,7 @@
goto err;
}
- of_property_read_u32(np, "qcom,sdcc-bus-width", &bus_width);
+ of_property_read_u32(np, "qcom,bus-width", &bus_width);
if (bus_width == 8) {
pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA;
} else if (bus_width == 4) {
@@ -5521,7 +5568,7 @@
pdata->mmc_bus_width = 0;
}
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-sup-voltages",
+ ret = msmsdcc_dt_get_array(dev, "qcom,sup-voltages",
&sup_voltages, &sup_volt_len, 0);
if (!ret) {
for (i = 0; i < sup_volt_len; i += 2) {
@@ -5536,7 +5583,7 @@
dev_dbg(dev, "OCR mask=0x%x\n", pdata->ocr_mask);
}
- ret = msmsdcc_dt_get_array(dev, "qcom,sdcc-clk-rates",
+ ret = msmsdcc_dt_get_array(dev, "qcom,clk-rates",
&clk_table, &clk_table_len, 0);
if (!ret) {
pdata->sup_clk_table = clk_table;
@@ -5561,13 +5608,13 @@
if (msmsdcc_dt_parse_gpio_info(dev, pdata))
goto err;
- len = of_property_count_strings(np, "qcom,sdcc-bus-speed-mode");
+ len = of_property_count_strings(np, "qcom,bus-speed-mode");
for (i = 0; i < len; i++) {
const char *name = NULL;
of_property_read_string_index(np,
- "qcom,sdcc-bus-speed-mode", i, &name);
+ "qcom,bus-speed-mode", i, &name);
if (!name)
continue;
@@ -5593,7 +5640,7 @@
| MMC_CAP_UHS_DDR50;
}
- of_property_read_u32(np, "qcom,sdcc-current-limit", ¤t_limit);
+ of_property_read_u32(np, "qcom,current-limit", ¤t_limit);
if (current_limit == 800)
pdata->uhs_caps |= MMC_CAP_MAX_CURRENT_800;
else if (current_limit == 600)
@@ -5603,12 +5650,14 @@
else if (current_limit == 200)
pdata->uhs_caps |= MMC_CAP_MAX_CURRENT_200;
- if (of_get_property(np, "qcom,sdcc-xpc", NULL))
+ if (of_get_property(np, "qcom,xpc", NULL))
pdata->xpc_cap = true;
- if (of_get_property(np, "qcom,sdcc-nonremovable", NULL))
+ if (of_get_property(np, "qcom,nonremovable", NULL))
pdata->nonremovable = true;
- if (of_get_property(np, "qcom,sdcc-disable_cmd23", NULL))
+ if (of_get_property(np, "qcom,disable-cmd23", NULL))
pdata->disable_cmd23 = true;
+ of_property_read_u32(np, "qcom,dat1-mpm-int",
+ &pdata->mpm_sdiowakeup_int);
return pdata;
err:
@@ -5700,7 +5749,7 @@
}
host = mmc_priv(mmc);
- host->pdev_id = pdev->id;
+ host->pdev = pdev;
host->plat = plat;
host->mmc = mmc;
host->curr.cmd = NULL;
@@ -5801,6 +5850,7 @@
dev_err(&pdev->dev, "Failed to read MCLK\n");
set_default_hw_caps(host);
+ host->saved_tuning_phase = INVALID_TUNING_PHASE;
/*
* Set the register write delay according to min. clock frequency
@@ -5937,6 +5987,14 @@
disable_irq(core_irqres->start);
host->sdcc_irq_disabled = 1;
+ if (!plat->sdiowakeup_irq) {
+ /* Check if registered as IORESOURCE_IRQ */
+ plat->sdiowakeup_irq =
+ platform_get_irq_byname(pdev, "sdiowakeup_irq");
+ if (plat->sdiowakeup_irq < 0)
+ plat->sdiowakeup_irq = 0;
+ }
+
if (plat->sdiowakeup_irq) {
wake_lock_init(&host->sdio_wlock, WAKE_LOCK_SUSPEND,
mmc_hostname(mmc));
@@ -6183,7 +6241,7 @@
vreg_deinit:
msmsdcc_vreg_init(host, false);
clk_disable:
- clk_disable(host->clk);
+ clk_disable_unprepare(host->clk);
msmsdcc_msm_bus_unregister(host);
pm_qos_remove:
if (host->cpu_dma_latency)
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index af5498e..bb1b211 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -346,7 +346,7 @@
void __iomem *dml_base;
void __iomem *bam_base;
- int pdev_id;
+ struct platform_device *pdev;
struct msmsdcc_curr_req curr;
@@ -427,6 +427,7 @@
struct dentry *debugfs_idle_tout;
struct dentry *debugfs_pio_mode;
struct dentry *debugfs_pm_stats;
+ int saved_tuning_phase;
};
#define MSMSDCC_VERSION_STEP_MASK 0x0000FFFF
@@ -446,6 +447,7 @@
#define MSMSDCC_AUTO_CMD19 (1 << 9)
#define MSMSDCC_AUTO_CMD21 (1 << 10)
#define MSMSDCC_SW_RST_CFG_BROKEN (1 << 11)
+#define MSMSDCC_DATA_PEND_FOR_CMD53 (1 << 12)
#define set_hw_caps(h, val) ((h)->hw_caps |= val)
#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
@@ -461,6 +463,7 @@
#define is_auto_cmd21(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD21)
#define is_sw_reset_save_config_broken(h) \
((h)->hw_caps & MSMSDCC_SW_RST_CFG_BROKEN)
+#define is_data_pend_for_cmd53(h) ((h)->hw_caps & MSMSDCC_DATA_PEND_FOR_CMD53)
/* Set controller capabilities based on version */
static inline void set_default_hw_caps(struct msmsdcc_host *host)
@@ -493,7 +496,8 @@
if (step >= 0x2b) /* SDCC v4 2.1.0 and greater */
host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG |
- MSMSDCC_AUTO_CMD21;
+ MSMSDCC_AUTO_CMD21 |
+ MSMSDCC_DATA_PEND_FOR_CMD53;
if (step == 0x2b)
host->hw_caps |= MSMSDCC_SW_RST_CFG_BROKEN;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index b34b069..e7a3741 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -23,8 +23,9 @@
#include <linux/scatterlist.h>
#include <linux/io.h>
#include <linux/gpio.h>
-#include <linux/pm_runtime.h>
#include <linux/mmc/sdhci-pci-data.h>
+#include <linux/sfi.h>
+#include <linux/pm_runtime.h>
#include "sdhci.h"
@@ -1451,6 +1452,8 @@
int i;
struct sdhci_pci_chip *chip;
+ sdhci_pci_runtime_pm_forbid(&pdev->dev);
+
chip = pci_get_drvdata(pdev);
if (chip) {
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 55a164f..425d092 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -672,6 +672,7 @@
}
#ifdef CONFIG_PM_SLEEP
+
static int sdhci_s3c_suspend(struct device *dev)
{
struct sdhci_host *host = dev_get_drvdata(dev);
@@ -712,6 +713,13 @@
#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
+static const struct dev_pm_ops sdhci_s3c_pmops = {
+ .suspend = sdhci_s3c_suspend,
+ .resume = sdhci_s3c_resume,
+};
+
+#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
+
#else
#define SDHCI_S3C_PMOPS NULL
#endif
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 43f7e77..6451d62 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -21,6 +21,7 @@
#include <linux/slab.h>
#include <linux/scatterlist.h>
#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
#include <linux/leds.h>
@@ -42,14 +43,29 @@
#define MAX_TUNING_LOOP 40
static unsigned int debug_quirks = 0;
+static unsigned int debug_quirks2;
static void sdhci_finish_data(struct sdhci_host *);
static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
static void sdhci_finish_command(struct sdhci_host *);
-static int sdhci_execute_tuning(struct mmc_host *mmc);
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
static void sdhci_tuning_timer(unsigned long data);
+#ifdef CONFIG_PM_RUNTIME
+static int sdhci_runtime_pm_get(struct sdhci_host *host);
+static int sdhci_runtime_pm_put(struct sdhci_host *host);
+#else
+static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
+{
+ return 0;
+}
+static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
+{
+ return 0;
+}
+#endif
+
static void sdhci_dumpregs(struct sdhci_host *host)
{
printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
@@ -134,6 +150,9 @@
(host->mmc->caps & MMC_CAP_NONREMOVABLE))
return;
+ if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
+ return;
+
if (enable)
sdhci_unmask_irqs(host, irqs);
else
@@ -249,11 +268,14 @@
spin_lock_irqsave(&host->lock, flags);
+ if (host->runtime_suspended)
+ goto out;
+
if (brightness == LED_OFF)
sdhci_deactivate_led(host);
else
sdhci_activate_led(host);
-
+out:
spin_unlock_irqrestore(&host->lock, flags);
}
#endif
@@ -398,12 +420,12 @@
static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
{
local_irq_save(*flags);
- return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
+ return kmap_atomic(sg_page(sg)) + sg->offset;
}
static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
{
- kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+ kunmap_atomic(buffer);
local_irq_restore(*flags);
}
@@ -653,9 +675,7 @@
break;
}
- if (count >= 0xF) {
- printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
- mmc_hostname(host->mmc), cmd->opcode);
+ if (count >= 0xF)
count = 0xE;
return count;
@@ -992,7 +1012,8 @@
flags |= SDHCI_CMD_INDEX;
/* CMD19 is special in that the Data Present Select should be set */
- if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
+ if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+ cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
@@ -1208,6 +1229,8 @@
host = mmc_priv(mmc);
+ sdhci_runtime_pm_get(host);
+
spin_lock_irqsave(&host->lock, flags);
WARN_ON(host->mrq != NULL);
@@ -1251,7 +1274,7 @@
if ((host->flags & SDHCI_NEEDS_RETUNING) &&
!(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
spin_unlock_irqrestore(&host->lock, flags);
- sdhci_execute_tuning(mmc);
+ sdhci_execute_tuning(mmc, mrq->cmd->opcode);
spin_lock_irqsave(&host->lock, flags);
/* Restore original mmc_request structure */
@@ -1268,14 +1291,11 @@
spin_unlock_irqrestore(&host->lock, flags);
}
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
{
- struct sdhci_host *host;
unsigned long flags;
u8 ctrl;
- host = mmc_priv(mmc);
-
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_DEVICE_DEAD)
@@ -1338,7 +1358,8 @@
unsigned int clock;
/* In case of UHS-I modes, set High Speed Enable */
- if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
+ if ((ios->timing == MMC_TIMING_MMC_HS200) ||
+ (ios->timing == MMC_TIMING_UHS_SDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR104) ||
(ios->timing == MMC_TIMING_UHS_DDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR25))
@@ -1391,7 +1412,9 @@
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
- if (ios->timing == MMC_TIMING_UHS_SDR12)
+ if (ios->timing == MMC_TIMING_MMC_HS200)
+ ctrl_2 |= SDHCI_CTRL_HS_SDR200;
+ else if (ios->timing == MMC_TIMING_UHS_SDR12)
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
else if (ios->timing == MMC_TIMING_UHS_SDR25)
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
@@ -1424,7 +1447,16 @@
spin_unlock_irqrestore(&host->lock, flags);
}
-static int check_ro(struct sdhci_host *host)
+static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ sdhci_runtime_pm_get(host);
+ sdhci_do_set_ios(host, ios);
+ sdhci_runtime_pm_put(host);
+}
+
+static int sdhci_check_ro(struct sdhci_host *host)
{
unsigned long flags;
int is_readonly;
@@ -1448,19 +1480,16 @@
#define SAMPLE_COUNT 5
-static int sdhci_get_ro(struct mmc_host *mmc)
+static int sdhci_do_get_ro(struct sdhci_host *host)
{
- struct sdhci_host *host;
int i, ro_count;
- host = mmc_priv(mmc);
-
if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
- return check_ro(host);
+ return sdhci_check_ro(host);
ro_count = 0;
for (i = 0; i < SAMPLE_COUNT; i++) {
- if (check_ro(host)) {
+ if (sdhci_check_ro(host)) {
if (++ro_count > SAMPLE_COUNT / 2)
return 1;
}
@@ -1469,38 +1498,64 @@
return 0;
}
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+static void sdhci_hw_reset(struct mmc_host *mmc)
{
- struct sdhci_host *host;
- unsigned long flags;
+ struct sdhci_host *host = mmc_priv(mmc);
- host = mmc_priv(mmc);
+ if (host->ops && host->ops->hw_reset)
+ host->ops->hw_reset(host);
+}
- spin_lock_irqsave(&host->lock, flags);
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int ret;
+ sdhci_runtime_pm_get(host);
+ ret = sdhci_do_get_ro(host);
+ sdhci_runtime_pm_put(host);
+ return ret;
+}
+
+static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
+{
if (host->flags & SDHCI_DEVICE_DEAD)
goto out;
if (enable)
+ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
+ else
+ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
+
+ /* SDIO IRQ will be enabled as appropriate in runtime resume */
+ if (host->runtime_suspended)
+ goto out;
+
+ if (enable)
sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
else
sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
out:
mmiowb();
+}
+static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(&host->lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
- struct mmc_ios *ios)
+static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
+ struct mmc_ios *ios)
{
- struct sdhci_host *host;
u8 pwr;
u16 clk, ctrl;
u32 present_state;
- host = mmc_priv(mmc);
-
/*
* Signal Voltage Switching is only applicable for Host Controllers
* v3.00 and above.
@@ -1593,7 +1648,21 @@
return 0;
}
-static int sdhci_execute_tuning(struct mmc_host *mmc)
+static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int err;
+
+ if (host->version < SDHCI_SPEC_300)
+ return 0;
+ sdhci_runtime_pm_get(host);
+ err = sdhci_do_start_signal_voltage_switch(host, ios);
+ sdhci_runtime_pm_put(host);
+ return err;
+}
+
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host;
u16 ctrl;
@@ -1601,26 +1670,35 @@
int tuning_loop_counter = MAX_TUNING_LOOP;
unsigned long timeout;
int err = 0;
+ bool requires_tuning_nonuhs = false;
host = mmc_priv(mmc);
+ sdhci_runtime_pm_get(host);
disable_irq(host->irq);
spin_lock(&host->lock);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/*
- * Host Controller needs tuning only in case of SDR104 mode
- * and for SDR50 mode when Use Tuning for SDR50 is set in
+ * The Host Controller needs tuning only in case of SDR104 mode
+ * and for SDR50 mode when Use Tuning for SDR50 is set in the
* Capabilities register.
+ * If the Host Controller supports the HS200 mode then the
+ * tuning function has to be executed.
*/
+ if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+ (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
+ host->flags & SDHCI_HS200_NEEDS_TUNING))
+ requires_tuning_nonuhs = true;
+
if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
- (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
- (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
+ requires_tuning_nonuhs)
ctrl |= SDHCI_CTRL_EXEC_TUNING;
else {
spin_unlock(&host->lock);
enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
return 0;
}
@@ -1646,12 +1724,12 @@
timeout = 150;
do {
struct mmc_command cmd = {0};
- struct mmc_request mrq = {0};
+ struct mmc_request mrq = {NULL};
if (!tuning_loop_counter && !timeout)
break;
- cmd.opcode = MMC_SEND_TUNING_BLOCK;
+ cmd.opcode = opcode;
cmd.arg = 0;
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
cmd.retries = 0;
@@ -1666,7 +1744,17 @@
* block to the Host Controller. So we set the block size
* to 64 here.
*/
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
+ if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
+ SDHCI_BLOCK_SIZE);
+ else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ } else {
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ }
/*
* The tuning block is sent by the card to the host controller.
@@ -1764,18 +1852,16 @@
sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
spin_unlock(&host->lock);
enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
return err;
}
-static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
{
- struct sdhci_host *host;
u16 ctrl;
unsigned long flags;
- host = mmc_priv(mmc);
-
/* Host Controller v3.00 defines preset value registers */
if (host->version < SDHCI_SPEC_300)
return;
@@ -1791,18 +1877,30 @@
if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ host->flags |= SDHCI_PV_ENABLED;
} else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ host->flags &= ~SDHCI_PV_ENABLED;
}
spin_unlock_irqrestore(&host->lock, flags);
}
+static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ sdhci_runtime_pm_get(host);
+ sdhci_do_enable_preset_value(host, enable);
+ sdhci_runtime_pm_put(host);
+}
+
static const struct mmc_host_ops sdhci_ops = {
.request = sdhci_request,
.set_ios = sdhci_set_ios,
.get_ro = sdhci_get_ro,
+ .hw_reset = sdhci_hw_reset,
.enable_sdio_irq = sdhci_enable_sdio_irq,
.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
.execute_tuning = sdhci_execute_tuning,
@@ -1824,19 +1922,19 @@
spin_lock_irqsave(&host->lock, flags);
- if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
- if (host->mrq) {
- printk(KERN_ERR "%s: Card removed during transfer!\n",
- mmc_hostname(host->mmc));
- printk(KERN_ERR "%s: Resetting controller.\n",
- mmc_hostname(host->mmc));
+ /* Check host->mrq first in case we are runtime suspended */
+ if (host->mrq &&
+ !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
+ printk(KERN_ERR "%s: Card removed during transfer!\n",
+ mmc_hostname(host->mmc));
+ printk(KERN_ERR "%s: Resetting controller.\n",
+ mmc_hostname(host->mmc));
- sdhci_reset(host, SDHCI_RESET_CMD);
- sdhci_reset(host, SDHCI_RESET_DATA);
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ sdhci_reset(host, SDHCI_RESET_DATA);
- host->mrq->cmd->error = -ENOMEDIUM;
- tasklet_schedule(&host->finish_tasklet);
- }
+ host->mrq->cmd->error = -ENOMEDIUM;
+ tasklet_schedule(&host->finish_tasklet);
}
spin_unlock_irqrestore(&host->lock, flags);
@@ -1852,14 +1950,16 @@
host = (struct sdhci_host*)param;
+ spin_lock_irqsave(&host->lock, flags);
+
/*
* If this tasklet gets rescheduled while running, it will
* be run again afterwards but without any active request.
*/
- if (!host->mrq)
+ if (!host->mrq) {
+ spin_unlock_irqrestore(&host->lock, flags);
return;
-
- spin_lock_irqsave(&host->lock, flags);
+ }
del_timer(&host->timer);
@@ -1903,6 +2003,7 @@
spin_unlock_irqrestore(&host->lock, flags);
mmc_request_done(host->mmc, mrq);
+ sdhci_runtime_pm_put(host);
}
static void sdhci_timeout_timer(unsigned long data)
@@ -2036,12 +2137,14 @@
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
+ u32 command;
BUG_ON(intmask == 0);
/* CMD19 generates _only_ Buffer Read Ready interrupt */
if (intmask & SDHCI_INT_DATA_AVAIL) {
- if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
- MMC_SEND_TUNING_BLOCK) {
+ command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
+ if (command == MMC_SEND_TUNING_BLOCK ||
+ command == MMC_SEND_TUNING_BLOCK_HS200) {
host->tuning_done = 1;
wake_up(&host->buf_ready_int);
return;
@@ -2140,6 +2243,13 @@
spin_lock(&host->lock);
+ if (host->runtime_suspended) {
+ spin_unlock(&host->lock);
+ printk(KERN_WARNING "%s: got irq while runtime suspended\n",
+ mmc_hostname(host->mmc));
+ return IRQ_HANDLED;
+ }
+
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
if (!intmask || intmask == 0xffffffff) {
@@ -2226,7 +2336,7 @@
#ifdef CONFIG_PM
-int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
+int sdhci_suspend_host(struct sdhci_host *host)
{
int ret;
@@ -2266,7 +2376,6 @@
return ret;
}
-
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma)
host->ops->enable_dma(host);
@@ -2317,6 +2426,90 @@
#endif /* CONFIG_PM */
+#ifdef CONFIG_PM_RUNTIME
+
+static int sdhci_runtime_pm_get(struct sdhci_host *host)
+{
+ return pm_runtime_get_sync(host->mmc->parent);
+}
+
+static int sdhci_runtime_pm_put(struct sdhci_host *host)
+{
+ pm_runtime_mark_last_busy(host->mmc->parent);
+ return pm_runtime_put_autosuspend(host->mmc->parent);
+}
+
+int sdhci_runtime_suspend_host(struct sdhci_host *host)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ /* Disable tuning since we are suspending */
+ if (host->version >= SDHCI_SPEC_300 &&
+ host->tuning_mode == SDHCI_TUNING_MODE_1) {
+ del_timer_sync(&host->tuning_timer);
+ host->flags &= ~SDHCI_NEEDS_RETUNING;
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ synchronize_irq(host->irq);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->runtime_suspended = true;
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
+
+int sdhci_runtime_resume_host(struct sdhci_host *host)
+{
+ unsigned long flags;
+ int ret = 0, host_flags = host->flags;
+
+ if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->enable_dma)
+ host->ops->enable_dma(host);
+ }
+
+ sdhci_init(host, 0);
+
+ /* Force clock and power re-program */
+ host->pwr = 0;
+ host->clock = 0;
+ sdhci_do_set_ios(host, &host->mmc->ios);
+
+ sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
+ if (host_flags & SDHCI_PV_ENABLED)
+ sdhci_do_enable_preset_value(host, true);
+
+ /* Set the re-tuning expiration flag */
+ if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
+ (host->tuning_mode == SDHCI_TUNING_MODE_1))
+ host->flags |= SDHCI_NEEDS_RETUNING;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->runtime_suspended = false;
+
+ /* Enable SDIO IRQ */
+ if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
+ sdhci_enable_sdio_irq_nolock(host, true);
+
+ /* Enable Card Detection */
+ sdhci_enable_card_detection(host);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
+
+#endif
+
/*****************************************************************************\
* *
* Device allocation/registration *
@@ -2359,6 +2552,8 @@
if (debug_quirks)
host->quirks = debug_quirks;
+ if (debug_quirks2)
+ host->quirks2 = debug_quirks2;
sdhci_reset(host, SDHCI_RESET_ALL);
@@ -2569,10 +2764,14 @@
if (caps[1] & SDHCI_SUPPORT_DDR50)
mmc->caps |= MMC_CAP_UHS_DDR50;
- /* Does the host needs tuning for SDR50? */
+ /* Does the host need tuning for SDR50? */
if (caps[1] & SDHCI_USE_SDR50_TUNING)
host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+ /* Does the host need tuning for HS200? */
+ if (mmc->caps2 & MMC_CAP2_HS200)
+ host->flags |= SDHCI_HS200_NEEDS_TUNING;
+
/* Driver Type(s) (A, C, D) supported by the host */
if (caps[1] & SDHCI_DRIVER_TYPE_A)
mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
@@ -2893,9 +3092,11 @@
module_exit(sdhci_drv_exit);
module_param(debug_quirks, uint, 0444);
+module_param(debug_quirks2, uint, 0444);
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
MODULE_LICENSE("GPL");
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
+MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 0c634ca..4ee18c75 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -536,15 +536,6 @@
#ifndef CONFIG_MTD_LAZYECCSTATS
part_fill_badblockstats(&(slave->mtd));
#endif
- if (master->_block_isbad) {
- uint64_t offs = 0;
-
- while (offs < slave->mtd.size) {
- if (mtd_block_isbad(master, offs + slave->offset))
- slave->mtd.ecc_stats.badblocks++;
- offs += slave->mtd.erasesize;
- }
- }
out_register:
return slave;
diff --git a/drivers/net/ethernet/msm/msm_rmnet.c b/drivers/net/ethernet/msm/msm_rmnet.c
index 41ad8af..4af2d8c 100644
--- a/drivers/net/ethernet/msm/msm_rmnet.c
+++ b/drivers/net/ethernet/msm/msm_rmnet.c
@@ -3,7 +3,7 @@
* Virtual Ethernet Interface for MSM7K Networking
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -37,7 +37,7 @@
#endif
#include <mach/msm_smd.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
/* Debug message support */
static int msm_rmnet_debug_mask;
@@ -403,7 +403,7 @@
static void msm_rmnet_unload_modem(void *pil)
{
if (pil)
- pil_put(pil);
+ subsystem_put(pil);
}
static void *msm_rmnet_load_modem(struct net_device *dev)
@@ -412,7 +412,7 @@
int rc;
struct rmnet_private *p = netdev_priv(dev);
- pil = pil_get("modem");
+ pil = subsystem_get("modem");
if (IS_ERR(pil))
pr_err("[%s] %s: modem load failed\n",
dev->name, __func__);
diff --git a/drivers/net/usb/rmnet_usb_ctrl.c b/drivers/net/usb/rmnet_usb_ctrl.c
index 7ed8ffa..f87b3b9 100644
--- a/drivers/net/usb/rmnet_usb_ctrl.c
+++ b/drivers/net/usb/rmnet_usb_ctrl.c
@@ -339,8 +339,10 @@
int rmnet_usb_ctrl_suspend(struct rmnet_ctrl_dev *dev)
{
- if (!flush_work_sync(&dev->get_encap_work))
- usb_kill_anchored_urbs(&dev->rx_submitted);
+ if (work_busy(&dev->get_encap_work))
+ return -EBUSY;
+
+ usb_kill_anchored_urbs(&dev->rx_submitted);
return 0;
}
diff --git a/drivers/net/wireless/wcnss/wcnss_wlan.c b/drivers/net/wireless/wcnss/wcnss_wlan.c
index 2bf857c..6e42fdb 100644
--- a/drivers/net/wireless/wcnss/wcnss_wlan.c
+++ b/drivers/net/wireless/wcnss/wcnss_wlan.c
@@ -25,9 +25,12 @@
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
-#include <mach/peripheral-loader.h>
+#include <linux/clk.h>
+
#include <mach/msm_smd.h>
#include <mach/msm_iomap.h>
+#include <mach/subsystem_restart.h>
+
#ifdef CONFIG_WCNSS_MEM_PRE_ALLOC
#include "wcnss_prealloc.h"
#endif
@@ -43,6 +46,21 @@
module_param(has_48mhz_xo, int, S_IWUSR | S_IRUGO);
MODULE_PARM_DESC(has_48mhz_xo, "Is an external 48 MHz XO present");
+static DEFINE_SPINLOCK(reg_spinlock);
+
+#define MSM_RIVA_PHYS 0x03204000
+#define MSM_PRONTO_PHYS 0xfb21b000
+
+#define RIVA_SPARE_OFFSET 0x0b4
+#define RIVA_SUSPEND_BIT BIT(24)
+
+#define MSM_RIVA_CCU_BASE 0x03200800
+
+#define CCU_INVALID_ADDR_OFFSET 0x100
+#define CCU_LAST_ADDR0_OFFSET 0x104
+#define CCU_LAST_ADDR1_OFFSET 0x108
+#define CCU_LAST_ADDR2_OFFSET 0x10c
+
#define WCNSS_CTRL_CHANNEL "WCNSS_CTRL"
#define WCNSS_MAX_FRAME_SIZE 500
#define WCNSS_VERSION_LEN 30
@@ -89,6 +107,7 @@
struct work_struct wcnssctrl_version_work;
struct work_struct wcnssctrl_rx_work;
struct wake_lock wcnss_wake_lock;
+ void __iomem *msm_wcnss_base;
} *penv = NULL;
static ssize_t wcnss_serial_number_show(struct device *dev,
@@ -160,15 +179,50 @@
static DEVICE_ATTR(wcnss_version, S_IRUSR,
wcnss_version_show, NULL);
+/* wcnss_reset_intr() is invoked when host drivers fails to
+ * communicate with WCNSS over SMD; so logging these registers
+ * helps to know WCNSS failure reason */
+static void wcnss_log_ccpu_regs(void)
+{
+ void __iomem *ccu_base;
+ void __iomem *ccu_reg;
+ u32 reg = 0;
+
+ ccu_base = ioremap(MSM_RIVA_CCU_BASE, SZ_512);
+ if (!ccu_base) {
+ pr_err("%s: ioremap WCNSS CCU reg failed\n", __func__);
+ return;
+ }
+
+ ccu_reg = ccu_base + CCU_INVALID_ADDR_OFFSET;
+ reg = readl_relaxed(ccu_reg);
+ pr_info("%s: CCU_CCPU_INVALID_ADDR %08x\n", __func__, reg);
+
+ ccu_reg = ccu_base + CCU_LAST_ADDR0_OFFSET;
+ reg = readl_relaxed(ccu_reg);
+ pr_info("%s: CCU_CCPU_LAST_ADDR0 %08x\n", __func__, reg);
+
+ ccu_reg = ccu_base + CCU_LAST_ADDR1_OFFSET;
+ reg = readl_relaxed(ccu_reg);
+ pr_info("%s: CCU_CCPU_LAST_ADDR1 %08x\n", __func__, reg);
+
+ ccu_reg = ccu_base + CCU_LAST_ADDR2_OFFSET;
+ reg = readl_relaxed(ccu_reg);
+ pr_info("%s: CCU_CCPU_LAST_ADDR2 %08x\n", __func__, reg);
+
+ iounmap(ccu_base);
+}
+
/* interface to reset Riva by sending the reset interrupt */
void wcnss_reset_intr(void)
{
- if (wcnss_hardware_type() == WCNSS_RIVA_HW) {
- wmb();
- __raw_writel(1 << 24, MSM_APCS_GCC_BASE + 0x8);
- } else {
+ if (wcnss_hardware_type() != WCNSS_RIVA_HW) {
pr_err("%s: reset interrupt not supported\n", __func__);
+ return;
}
+ wcnss_log_ccpu_regs();
+ wmb();
+ __raw_writel(1 << 24, MSM_APCS_GCC_BASE + 0x8);
}
EXPORT_SYMBOL(wcnss_reset_intr);
@@ -487,6 +541,87 @@
}
EXPORT_SYMBOL(wcnss_get_serial_number);
+static int enable_wcnss_suspend_notify;
+
+static int enable_wcnss_suspend_notify_set(const char *val,
+ struct kernel_param *kp)
+{
+ int ret;
+
+ ret = param_set_int(val, kp);
+ if (ret)
+ return ret;
+
+ if (enable_wcnss_suspend_notify)
+ pr_debug("Suspend notification activated for wcnss\n");
+
+ return 0;
+}
+module_param_call(enable_wcnss_suspend_notify, enable_wcnss_suspend_notify_set,
+ param_get_int, &enable_wcnss_suspend_notify, S_IRUGO | S_IWUSR);
+
+
+void wcnss_suspend_notify(void)
+{
+ void __iomem *pmu_spare_reg;
+ u32 reg = 0;
+ unsigned long flags;
+ struct clk *cxo = clk_get(&penv->pdev->dev, "cxo");
+ int rc = 0;
+
+ if (!enable_wcnss_suspend_notify)
+ return;
+
+ if (wcnss_hardware_type() == WCNSS_PRONTO_HW)
+ return;
+
+ /* For Riva */
+ rc = clk_prepare_enable(cxo);
+ if (rc) {
+ pr_err("cxo enable failed\n");
+ return;
+ }
+ pmu_spare_reg = penv->msm_wcnss_base + RIVA_SPARE_OFFSET;
+ spin_lock_irqsave(®_spinlock, flags);
+ reg = readl_relaxed(pmu_spare_reg);
+ reg |= RIVA_SUSPEND_BIT;
+ writel_relaxed(reg, pmu_spare_reg);
+ spin_unlock_irqrestore(®_spinlock, flags);
+ clk_disable_unprepare(cxo);
+}
+EXPORT_SYMBOL(wcnss_suspend_notify);
+
+void wcnss_resume_notify(void)
+{
+ void __iomem *pmu_spare_reg;
+ u32 reg = 0;
+ unsigned long flags;
+ struct clk *cxo = clk_get(&penv->pdev->dev, "cxo");
+ int rc = 0;
+
+ if (!enable_wcnss_suspend_notify)
+ return;
+
+ if (wcnss_hardware_type() == WCNSS_PRONTO_HW)
+ return;
+
+ /* For Riva */
+ pmu_spare_reg = penv->msm_wcnss_base + RIVA_SPARE_OFFSET;
+
+ rc = clk_prepare_enable(cxo);
+ if (rc) {
+ pr_err("cxo enable failed\n");
+ return;
+ }
+ spin_lock_irqsave(®_spinlock, flags);
+ reg = readl_relaxed(pmu_spare_reg);
+ reg &= ~RIVA_SUSPEND_BIT;
+ writel_relaxed(reg, pmu_spare_reg);
+ spin_unlock_irqrestore(®_spinlock, flags);
+ clk_disable_unprepare(cxo);
+}
+EXPORT_SYMBOL(wcnss_resume_notify);
+
static int wcnss_wlan_suspend(struct device *dev)
{
if (penv && dev && (dev == &penv->pdev->dev) &&
@@ -610,6 +745,8 @@
{
int ret;
struct qcom_wcnss_opts *pdata;
+ unsigned long wcnss_phys_addr;
+ int size = 0;
int has_pronto_hw = of_property_read_bool(pdev->dev.of_node,
"qcom,has_pronto_hw");
@@ -664,7 +801,7 @@
}
/* trigger initialization of the WCNSS */
- penv->pil = pil_get(WCNSS_PIL_DEVICE);
+ penv->pil = subsystem_get(WCNSS_PIL_DEVICE);
if (IS_ERR(penv->pil)) {
dev_err(&pdev->dev, "Peripheral Loader failed on WCNSS.\n");
ret = PTR_ERR(penv->pil);
@@ -690,17 +827,34 @@
wake_lock_init(&penv->wcnss_wake_lock, WAKE_LOCK_SUSPEND, "wcnss");
+ if (wcnss_hardware_type() == WCNSS_PRONTO_HW) {
+ size = 0x3000;
+ wcnss_phys_addr = MSM_PRONTO_PHYS;
+ } else {
+ wcnss_phys_addr = MSM_RIVA_PHYS;
+ size = SZ_256;
+ }
+
+ penv->msm_wcnss_base = ioremap(wcnss_phys_addr, size);
+ if (!penv->msm_wcnss_base) {
+ ret = -ENOMEM;
+ pr_err("%s: ioremap wcnss physical failed\n", __func__);
+ goto fail_wake;
+ }
+
return 0;
+fail_wake:
+ wake_lock_destroy(&penv->wcnss_wake_lock);
fail_res:
if (penv->pil)
- pil_put(penv->pil);
+ subsystem_put(penv->pil);
fail_pil:
wcnss_wlan_power(&pdev->dev, &penv->wlan_config,
WCNSS_WLAN_SWITCH_OFF);
fail_power:
if (has_pronto_hw)
- ret = wcnss_pronto_gpios_config(&pdev->dev, false);
+ wcnss_pronto_gpios_config(&pdev->dev, false);
else
wcnss_gpios_config(penv->gpios_5wire, false);
fail_gpio_res:
@@ -840,7 +994,7 @@
{
if (penv) {
if (penv->pil)
- pil_put(penv->pil);
+ subsystem_put(penv->pil);
kfree(penv);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 6b54b23..9a18a97 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -617,21 +617,6 @@
int error = 0;
/*
- * If a PCI device configured to wake up the system from sleep states
- * has been suspended at run time and there's a resume request pending
- * for it, this is equivalent to the device signaling wakeup, so the
- * system suspend operation should be aborted.
- */
- pm_runtime_get_noresume(dev);
- if (pm_runtime_barrier(dev) && device_may_wakeup(dev))
- pm_wakeup_event(dev, 0);
-
- if (pm_wakeup_pending()) {
- pm_runtime_put_sync(dev);
- return -EBUSY;
- }
-
- /*
* PCI devices suspended at run time need to be resumed at this
* point, because in general it is necessary to reconfigure them for
* system suspend. Namely, if the device is supposed to wake up the
@@ -654,8 +639,6 @@
if (drv && drv->pm && drv->pm->complete)
drv->pm->complete(dev);
-
- pm_runtime_put_sync(dev);
}
#else /* !CONFIG_PM_SLEEP */
diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig
index 34e1d40..75cc086 100644
--- a/drivers/platform/msm/Kconfig
+++ b/drivers/platform/msm/Kconfig
@@ -76,4 +76,18 @@
PNP PMIC. It configures the frequency of clkdiv outputs on the
PMIC. These clocks are typically wired through alternate functions
on gpio pins.
+
+config IPA
+ tristate "IPA support"
+ depends on SPS
+ help
+ This driver supports the Internet Packet Accelerator (IPA) core.
+ IPA is a programmable protocol processor HW block.
+ It is designed to support generic HW processing of UL/DL IP packets
+ for various use cases independent of radio technology.
+ The driver support client connection and configuration
+ for the IPA core.
+ Kernel and user-space processes can call the IPA driver
+ to configure IPA core.
+
endmenu
diff --git a/drivers/platform/msm/Makefile b/drivers/platform/msm/Makefile
index 35efd91..0a755d3 100644
--- a/drivers/platform/msm/Makefile
+++ b/drivers/platform/msm/Makefile
@@ -3,6 +3,7 @@
#
obj-$(CONFIG_MSM_SSBI) += ssbi.o
obj-$(CONFIG_USB_BAM) += usb_bam.o
+obj-$(CONFIG_IPA) += ipa/
obj-$(CONFIG_SPS) += sps/
obj-$(CONFIG_QPNP_PWM) += qpnp-pwm.o
obj-$(CONFIG_QPNP_POWER_ON) += qpnp-power-on.o
diff --git a/drivers/platform/msm/ipa/Makefile b/drivers/platform/msm/ipa/Makefile
new file mode 100644
index 0000000..ded5b50
--- /dev/null
+++ b/drivers/platform/msm/ipa/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_IPA) += ipat.o
+ipat-y := ipa.o ipa_debugfs.o ipa_hdr.o ipa_flt.o ipa_rt.o ipa_dp.o ipa_client.o \
+ ipa_utils.o ipa_nat.o rmnet_bridge.o a2_service.o ipa_bridge.o
diff --git a/drivers/platform/msm/ipa/a2_service.c b/drivers/platform/msm/ipa/a2_service.c
new file mode 100644
index 0000000..0ae2552
--- /dev/null
+++ b/drivers/platform/msm/ipa/a2_service.c
@@ -0,0 +1,276 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <mach/bam_dmux.h>
+#include <mach/ipa.h>
+#include <mach/sps.h>
+#include "ipa_i.h"
+
+static struct a2_service_cb_type {
+ void *tx_complete_cb;
+ void *rx_cb;
+ u32 producer_handle;
+ u32 consumer_handle;
+} a2_service_cb;
+
+static struct sps_mem_buffer data_mem_buf[2];
+static struct sps_mem_buffer desc_mem_buf[2];
+
+static int connect_pipe_ipa(enum a2_mux_pipe_direction pipe_dir,
+ u8 *usb_pipe_idx,
+ u32 *clnt_hdl,
+ struct sps_pipe *pipe);
+
+static int a2_ipa_connect_pipe(struct ipa_connect_params *in_params,
+ struct ipa_sps_params *out_params, u32 *clnt_hdl);
+
+/**
+ * a2_mux_initialize() - initialize A2 MUX module
+ *
+ * Return codes:
+ * 0: success
+ */
+int a2_mux_initialize(void)
+{
+ (void) msm_bam_dmux_ul_power_vote();
+
+ return 0;
+}
+
+/**
+ * a2_mux_close() - close A2 MUX module
+ *
+ * Return codes:
+ * 0: success
+ * -EINVAL: invalid parameters
+ */
+int a2_mux_close(void)
+{
+ int ret = 0;
+
+ (void) msm_bam_dmux_ul_power_unvote();
+
+ ret = ipa_disconnect(a2_service_cb.consumer_handle);
+ if (0 != ret) {
+ pr_err("%s: ipa_disconnect failure\n", __func__);
+ goto bail;
+ }
+
+ ret = ipa_disconnect(a2_service_cb.producer_handle);
+ if (0 != ret) {
+ pr_err("%s: ipa_disconnect failure\n", __func__);
+ goto bail;
+ }
+
+ ret = 0;
+
+bail:
+
+ return ret;
+}
+
+/**
+ * a2_mux_open_port() - open connection to A2
+ * @wwan_logical_channel_id: WWAN logical channel ID
+ * @rx_cb: Rx callback
+ * @tx_complete_cb: Tx completed callback
+ *
+ * Return codes:
+ * 0: success
+ * -EINVAL: invalid parameters
+ */
+int a2_mux_open_port(int wwan_logical_channel_id, void *rx_cb,
+ void *tx_complete_cb)
+{
+ int ret = 0;
+ u8 src_pipe = 0;
+ u8 dst_pipe = 0;
+ struct sps_pipe *a2_to_ipa_pipe = NULL;
+ struct sps_pipe *ipa_to_a2_pipe = NULL;
+
+ (void) wwan_logical_channel_id;
+
+ a2_service_cb.rx_cb = rx_cb;
+ a2_service_cb.tx_complete_cb = tx_complete_cb;
+
+ ret = connect_pipe_ipa(A2_TO_IPA,
+ &src_pipe,
+ &(a2_service_cb.consumer_handle),
+ a2_to_ipa_pipe);
+ if (ret) {
+ pr_err("%s: A2 to IPA pipe connection failure\n", __func__);
+ goto bail;
+ }
+
+ ret = connect_pipe_ipa(IPA_TO_A2,
+ &dst_pipe,
+ &(a2_service_cb.producer_handle),
+ ipa_to_a2_pipe);
+ if (ret) {
+ pr_err("%s: IPA to A2 pipe connection failure\n", __func__);
+ sps_disconnect(a2_to_ipa_pipe);
+ sps_free_endpoint(a2_to_ipa_pipe);
+ (void) ipa_disconnect(a2_service_cb.consumer_handle);
+ goto bail;
+ }
+
+ ret = 0;
+
+bail:
+
+ return ret;
+}
+
+static int connect_pipe_ipa(enum a2_mux_pipe_direction pipe_dir,
+ u8 *usb_pipe_idx,
+ u32 *clnt_hdl,
+ struct sps_pipe *pipe)
+{
+ int ret;
+ struct sps_connect connection = {0, };
+ u32 a2_handle = 0;
+ u32 a2_phy_addr = 0;
+ struct a2_mux_pipe_connection pipe_connection = { 0, };
+ struct ipa_connect_params ipa_in_params;
+ struct ipa_sps_params sps_out_params;
+
+ memset(&ipa_in_params, 0, sizeof(ipa_in_params));
+ memset(&sps_out_params, 0, sizeof(sps_out_params));
+
+ if (!usb_pipe_idx || !clnt_hdl) {
+ pr_err("connect_pipe_ipa :: null arguments\n");
+ ret = -EINVAL;
+ goto bail;
+ }
+
+ ret = ipa_get_a2_mux_pipe_info(pipe_dir, &pipe_connection);
+ if (ret) {
+ pr_err("ipa_get_a2_mux_pipe_info failed\n");
+ goto bail;
+ }
+
+ if (pipe_dir == A2_TO_IPA) {
+ a2_phy_addr = pipe_connection.src_phy_addr;
+ ipa_in_params.client = IPA_CLIENT_A2_TETHERED_PROD;
+ ipa_in_params.ipa_ep_cfg.mode.mode = IPA_DMA;
+ ipa_in_params.ipa_ep_cfg.mode.dst = IPA_CLIENT_USB_CONS;
+ pr_err("-*&- pipe_connection->src_pipe_index = %d\n",
+ pipe_connection.src_pipe_index);
+ ipa_in_params.client_ep_idx = pipe_connection.src_pipe_index;
+ } else {
+ a2_phy_addr = pipe_connection.dst_phy_addr;
+ ipa_in_params.client = IPA_CLIENT_A2_TETHERED_CONS;
+ ipa_in_params.client_ep_idx = pipe_connection.dst_pipe_index;
+ }
+
+ ret = sps_phy2h(a2_phy_addr, &a2_handle);
+ if (ret) {
+ pr_err("%s: sps_phy2h failed (A2 BAM) %d\n", __func__, ret);
+ goto bail;
+ }
+
+ ipa_in_params.client_bam_hdl = a2_handle;
+ ipa_in_params.desc_fifo_sz = pipe_connection.desc_fifo_size;
+ ipa_in_params.data_fifo_sz = pipe_connection.data_fifo_size;
+
+ if (pipe_connection.mem_type == IPA_SPS_PIPE_MEM) {
+ pr_debug("%s: A2 BAM using SPS pipe memory\n", __func__);
+ ret = sps_setup_bam2bam_fifo(&data_mem_buf[pipe_dir],
+ pipe_connection.data_fifo_base_offset,
+ pipe_connection.data_fifo_size, 1);
+ if (ret) {
+ pr_err("%s: data fifo setup failure %d\n",
+ __func__, ret);
+ goto bail;
+ }
+
+ ret = sps_setup_bam2bam_fifo(&desc_mem_buf[pipe_dir],
+ pipe_connection.desc_fifo_base_offset,
+ pipe_connection.desc_fifo_size, 1);
+ if (ret) {
+ pr_err("%s: desc. fifo setup failure %d\n",
+ __func__, ret);
+ goto bail;
+ }
+
+ ipa_in_params.data = data_mem_buf[pipe_dir];
+ ipa_in_params.desc = desc_mem_buf[pipe_dir];
+ }
+
+ ret = a2_ipa_connect_pipe(&ipa_in_params,
+ &sps_out_params,
+ clnt_hdl);
+ if (ret) {
+ pr_err("-**- USB-IPA info: ipa_connect failed\n");
+ pr_err("%s: usb_ipa_connect_pipe failed\n", __func__);
+ goto bail;
+ }
+
+ pipe = sps_alloc_endpoint();
+ if (pipe == NULL) {
+ pr_err("%s: sps_alloc_endpoint failed\n", __func__);
+ ret = -ENOMEM;
+ goto a2_ipa_connect_pipe_failed;
+ }
+
+ ret = sps_get_config(pipe, &connection);
+ if (ret) {
+ pr_err("%s: tx get config failed %d\n", __func__, ret);
+ goto get_config_failed;
+ }
+
+ if (pipe_dir == A2_TO_IPA) {
+ connection.mode = SPS_MODE_SRC;
+ *usb_pipe_idx = connection.src_pipe_index;
+ connection.source = a2_handle;
+ connection.destination = sps_out_params.ipa_bam_hdl;
+ connection.src_pipe_index = pipe_connection.src_pipe_index;
+ connection.dest_pipe_index = sps_out_params.ipa_ep_idx;
+ } else {
+ connection.mode = SPS_MODE_DEST;
+ *usb_pipe_idx = connection.dest_pipe_index;
+ connection.source = sps_out_params.ipa_bam_hdl;
+ connection.destination = a2_handle;
+ connection.src_pipe_index = sps_out_params.ipa_ep_idx;
+ connection.dest_pipe_index = pipe_connection.dst_pipe_index;
+ }
+
+ connection.event_thresh = 16;
+ connection.data = sps_out_params.data;
+ connection.desc = sps_out_params.desc;
+
+ ret = sps_connect(pipe, &connection);
+ if (ret < 0) {
+ pr_err("%s: tx connect error %d\n", __func__, ret);
+ goto error;
+ }
+
+ ret = 0;
+ goto bail;
+error:
+ sps_disconnect(pipe);
+get_config_failed:
+ sps_free_endpoint(pipe);
+a2_ipa_connect_pipe_failed:
+ (void) ipa_disconnect(*clnt_hdl);
+bail:
+ return ret;
+}
+
+static int a2_ipa_connect_pipe(struct ipa_connect_params *in_params,
+ struct ipa_sps_params *out_params, u32 *clnt_hdl)
+{
+ return ipa_connect(in_params, out_params, clnt_hdl);
+}
+
diff --git a/drivers/platform/msm/ipa/a2_service.h b/drivers/platform/msm/ipa/a2_service.h
new file mode 100644
index 0000000..80885da
--- /dev/null
+++ b/drivers/platform/msm/ipa/a2_service.h
@@ -0,0 +1,24 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _A2_SERVICE_H_
+#define _A2_SERVICE_H_
+
+int a2_mux_initialize(void);
+
+int a2_mux_close(void);
+
+int a2_mux_open_port(int wwan_logical_channel_id, void *rx_cb,
+ void *tx_complete_cb);
+
+#endif /* _A2_SERVICE_H_ */
+
diff --git a/drivers/platform/msm/ipa/ipa.c b/drivers/platform/msm/ipa/ipa.c
new file mode 100644
index 0000000..8f68ef5
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa.c
@@ -0,0 +1,1790 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/fs.h>
+#include <linux/genalloc.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/rbtree.h>
+#include <linux/uaccess.h>
+#include "ipa_i.h"
+
+#define IPA_SUMMING_THRESHOLD (0x10)
+#define IPA_PIPE_MEM_START_OFST (0x0)
+#define IPA_PIPE_MEM_SIZE (0x0)
+#define IPA_READ_MAX (16)
+#define IPA_MOBILE_AP_MODE(x) (x == IPA_MODE_MOBILE_AP_ETH || \
+ x == IPA_MODE_MOBILE_AP_WAN || \
+ x == IPA_MODE_MOBILE_AP_WLAN)
+#define IPA_CNOC_CLK_RATE (75 * 1000 * 1000UL)
+#define IPA_V1_CLK_RATE (92.31 * 1000 * 1000UL)
+#define IPA_DMA_POOL_SIZE (512)
+#define IPA_DMA_POOL_ALIGNMENT (4)
+#define IPA_DMA_POOL_BOUNDARY (1024)
+#define WLAN_AMPDU_TX_EP (15)
+#define IPA_ROUTING_RULE_BYTE_SIZE (4)
+#define IPA_BAM_CNFG_BITS_VAL (0x7FFFE004)
+
+#define IPA_AGGR_MAX_STR_LENGTH (10)
+
+#define IPA_AGGR_STR_IN_BYTES(str) \
+ (strnlen((str), IPA_AGGR_MAX_STR_LENGTH - 1) + 1)
+
+struct ipa_plat_drv_res {
+ u32 ipa_mem_base;
+ u32 ipa_mem_size;
+ u32 bam_mem_base;
+ u32 bam_mem_size;
+ u32 ipa_irq;
+ u32 bam_irq;
+ u32 ipa_pipe_mem_start_ofst;
+ u32 ipa_pipe_mem_size;
+ struct a2_mux_pipe_connection a2_to_ipa_pipe;
+ struct a2_mux_pipe_connection ipa_to_a2_pipe;
+};
+
+static struct ipa_plat_drv_res ipa_res = {0, };
+static struct of_device_id ipa_plat_drv_match[] = {
+ {
+ .compatible = "qcom,ipa",
+ },
+
+ {
+ }
+};
+
+static struct clk *ipa_clk_src;
+static struct clk *ipa_clk;
+static struct clk *sys_noc_ipa_axi_clk;
+static struct clk *ipa_cnoc_clk;
+static struct device *ipa_dev;
+
+struct ipa_context *ipa_ctx;
+
+static bool polling_mode;
+module_param(polling_mode, bool, 0644);
+MODULE_PARM_DESC(polling_mode,
+ "1 - pure polling mode; 0 - interrupt+polling mode");
+static uint polling_delay_ms = 50;
+module_param(polling_delay_ms, uint, 0644);
+MODULE_PARM_DESC(polling_delay_ms, "set to desired delay between polls");
+static bool hdr_tbl_lcl = 1;
+module_param(hdr_tbl_lcl, bool, 0644);
+MODULE_PARM_DESC(hdr_tbl_lcl, "where hdr tbl resides 1-local; 0-system");
+static bool ip4_rt_tbl_lcl = 1;
+module_param(ip4_rt_tbl_lcl, bool, 0644);
+MODULE_PARM_DESC(ip4_rt_tbl_lcl,
+ "where ip4 rt tables reside 1-local; 0-system");
+static bool ip6_rt_tbl_lcl = 1;
+module_param(ip6_rt_tbl_lcl, bool, 0644);
+MODULE_PARM_DESC(ip6_rt_tbl_lcl,
+ "where ip6 rt tables reside 1-local; 0-system");
+static bool ip4_flt_tbl_lcl = 1;
+module_param(ip4_flt_tbl_lcl, bool, 0644);
+MODULE_PARM_DESC(ip4_flt_tbl_lcl,
+ "where ip4 flt tables reside 1-local; 0-system");
+static bool ip6_flt_tbl_lcl = 1;
+module_param(ip6_flt_tbl_lcl, bool, 0644);
+MODULE_PARM_DESC(ip6_flt_tbl_lcl,
+ "where ip6 flt tables reside 1-local; 0-system");
+
+static int ipa_load_pipe_connection(struct platform_device *pdev,
+ enum a2_mux_pipe_direction pipe_dir,
+ struct a2_mux_pipe_connection *pdata);
+
+static int ipa_update_connections_info(struct device_node *node,
+ struct a2_mux_pipe_connection *pipe_connection);
+
+static void ipa_set_aggregation_params(void);
+
+static ssize_t ipa_read(struct file *filp, char __user *buf, size_t count,
+ loff_t *f_pos)
+{
+ u32 reg_val = 0xfeedface;
+ char str[IPA_READ_MAX];
+ int result;
+ static int read_cnt;
+
+ if (read_cnt) {
+ IPAERR("only supports one call to read\n");
+ return 0;
+ }
+
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_COMP_HW_VERSION_OFST);
+ result = scnprintf(str, IPA_READ_MAX, "%x\n", reg_val);
+ if (copy_to_user(buf, str, result))
+ return -EFAULT;
+ read_cnt = 1;
+
+ return result;
+}
+
+static int ipa_open(struct inode *inode, struct file *filp)
+{
+ struct ipa_context *ctx = NULL;
+
+ IPADBG("ENTER\n");
+ ctx = container_of(inode->i_cdev, struct ipa_context, cdev);
+ filp->private_data = ctx;
+
+ return 0;
+}
+
+static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ int retval = 0;
+ u32 pyld_sz;
+ u8 header[128] = { 0 };
+ u8 *param = NULL;
+ struct ipa_ioc_nat_alloc_mem nat_mem;
+ struct ipa_ioc_v4_nat_init nat_init;
+ struct ipa_ioc_v4_nat_del nat_del;
+
+ IPADBG("cmd=%x nr=%d\n", cmd, _IOC_NR(cmd));
+
+ if (_IOC_TYPE(cmd) != IPA_IOC_MAGIC)
+ return -ENOTTY;
+ if (_IOC_NR(cmd) >= IPA_IOCTL_MAX)
+ return -ENOTTY;
+
+ switch (cmd) {
+ case IPA_IOC_ALLOC_NAT_MEM:
+ if (copy_from_user((u8 *)&nat_mem, (u8 *)arg,
+ sizeof(struct ipa_ioc_nat_alloc_mem))) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if (allocate_nat_device(&nat_mem)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, (u8 *)&nat_mem,
+ sizeof(struct ipa_ioc_nat_alloc_mem))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+ case IPA_IOC_V4_INIT_NAT:
+ if (copy_from_user((u8 *)&nat_init, (u8 *)arg,
+ sizeof(struct ipa_ioc_v4_nat_init))) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_nat_init_cmd(&nat_init)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_NAT_DMA:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_nat_dma_cmd))) {
+ retval = -EFAULT;
+ break;
+ }
+
+ pyld_sz =
+ sizeof(struct ipa_ioc_nat_dma_cmd) +
+ ((struct ipa_ioc_nat_dma_cmd *)header)->entries *
+ sizeof(struct ipa_ioc_nat_dma_one);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if (ipa_nat_dma_cmd((struct ipa_ioc_nat_dma_cmd *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_V4_DEL_NAT:
+ if (copy_from_user((u8 *)&nat_del, (u8 *)arg,
+ sizeof(struct ipa_ioc_v4_nat_del))) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_nat_del_cmd(&nat_del)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_ADD_HDR:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_add_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_add_hdr) +
+ ((struct ipa_ioc_add_hdr *)header)->num_hdrs *
+ sizeof(struct ipa_hdr_add);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_add_hdr((struct ipa_ioc_add_hdr *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_DEL_HDR:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_del_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_del_hdr) +
+ ((struct ipa_ioc_del_hdr *)header)->num_hdls *
+ sizeof(struct ipa_hdr_del);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_del_hdr((struct ipa_ioc_del_hdr *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_ADD_RT_RULE:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_add_rt_rule))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_add_rt_rule) +
+ ((struct ipa_ioc_add_rt_rule *)header)->num_rules *
+ sizeof(struct ipa_rt_rule_add);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_add_rt_rule((struct ipa_ioc_add_rt_rule *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_DEL_RT_RULE:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_del_rt_rule))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_del_rt_rule) +
+ ((struct ipa_ioc_del_rt_rule *)header)->num_hdls *
+ sizeof(struct ipa_rt_rule_del);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_del_rt_rule((struct ipa_ioc_del_rt_rule *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_ADD_FLT_RULE:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_add_flt_rule))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_add_flt_rule) +
+ ((struct ipa_ioc_add_flt_rule *)header)->num_rules *
+ sizeof(struct ipa_flt_rule_add);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_add_flt_rule((struct ipa_ioc_add_flt_rule *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_DEL_FLT_RULE:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_del_flt_rule))) {
+ retval = -EFAULT;
+ break;
+ }
+ pyld_sz =
+ sizeof(struct ipa_ioc_del_flt_rule) +
+ ((struct ipa_ioc_del_flt_rule *)header)->num_hdls *
+ sizeof(struct ipa_flt_rule_del);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_del_flt_rule((struct ipa_ioc_del_flt_rule *)param)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
+ case IPA_IOC_COMMIT_HDR:
+ retval = ipa_commit_hdr();
+ break;
+ case IPA_IOC_RESET_HDR:
+ retval = ipa_reset_hdr();
+ break;
+ case IPA_IOC_COMMIT_RT:
+ retval = ipa_commit_rt(arg);
+ break;
+ case IPA_IOC_RESET_RT:
+ retval = ipa_reset_rt(arg);
+ break;
+ case IPA_IOC_COMMIT_FLT:
+ retval = ipa_commit_flt(arg);
+ break;
+ case IPA_IOC_RESET_FLT:
+ retval = ipa_reset_flt(arg);
+ break;
+ case IPA_IOC_DUMP:
+ ipa_dump();
+ break;
+ case IPA_IOC_GET_RT_TBL:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_get_rt_tbl))) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_get_rt_tbl((struct ipa_ioc_get_rt_tbl *)header)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, header,
+ sizeof(struct ipa_ioc_get_rt_tbl))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+ case IPA_IOC_PUT_RT_TBL:
+ retval = ipa_put_rt_tbl(arg);
+ break;
+ case IPA_IOC_GET_HDR:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_get_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_get_hdr((struct ipa_ioc_get_hdr *)header)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, header,
+ sizeof(struct ipa_ioc_get_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+ case IPA_IOC_PUT_HDR:
+ retval = ipa_put_hdr(arg);
+ break;
+ case IPA_IOC_SET_FLT:
+ retval = ipa_cfg_filter(arg);
+ break;
+ case IPA_IOC_COPY_HDR:
+ if (copy_from_user(header, (u8 *)arg,
+ sizeof(struct ipa_ioc_copy_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ if (ipa_copy_hdr((struct ipa_ioc_copy_hdr *)header)) {
+ retval = -EFAULT;
+ break;
+ }
+ if (copy_to_user((u8 *)arg, header,
+ sizeof(struct ipa_ioc_copy_hdr))) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+ default: /* redundant, as cmd was checked against MAXNR */
+ return -ENOTTY;
+ }
+ kfree(param);
+
+ return retval;
+}
+
+/**
+* ipa_setup_dflt_rt_tables() - Setup default routing tables
+*
+* Return codes:
+* 0: success
+* -ENOMEM: failed to allocate memory
+* -EPERM: failed to add the tables
+*/
+int ipa_setup_dflt_rt_tables(void)
+{
+ struct ipa_ioc_add_rt_rule *rt_rule;
+ struct ipa_rt_rule_add *rt_rule_entry;
+
+ rt_rule =
+ kzalloc(sizeof(struct ipa_ioc_add_rt_rule) + 1 *
+ sizeof(struct ipa_rt_rule_add), GFP_KERNEL);
+ if (!rt_rule) {
+ IPAERR("fail to alloc mem\n");
+ return -ENOMEM;
+ }
+ /* setup a default v4 route to point to A5 */
+ rt_rule->num_rules = 1;
+ rt_rule->commit = 1;
+ rt_rule->ip = IPA_IP_v4;
+ strlcpy(rt_rule->rt_tbl_name, IPA_DFLT_RT_TBL_NAME,
+ IPA_RESOURCE_NAME_MAX);
+
+ rt_rule_entry = &rt_rule->rules[0];
+ rt_rule_entry->at_rear = 1;
+ rt_rule_entry->rule.dst = IPA_CLIENT_A5_LAN_WAN_CONS;
+ rt_rule_entry->rule.hdr_hdl = ipa_ctx->excp_hdr_hdl;
+
+ if (ipa_add_rt_rule(rt_rule)) {
+ IPAERR("fail to add dflt v4 rule\n");
+ kfree(rt_rule);
+ return -EPERM;
+ }
+ IPADBG("dflt v4 rt rule hdl=%x\n", rt_rule_entry->rt_rule_hdl);
+ ipa_ctx->dflt_v4_rt_rule_hdl = rt_rule_entry->rt_rule_hdl;
+
+ /* setup a default v6 route to point to A5 */
+ rt_rule->ip = IPA_IP_v6;
+ if (ipa_add_rt_rule(rt_rule)) {
+ IPAERR("fail to add dflt v6 rule\n");
+ kfree(rt_rule);
+ return -EPERM;
+ }
+ IPADBG("dflt v6 rt rule hdl=%x\n", rt_rule_entry->rt_rule_hdl);
+ ipa_ctx->dflt_v6_rt_rule_hdl = rt_rule_entry->rt_rule_hdl;
+
+ /*
+ * because these tables are the very first to be added, they will both
+ * have the same index (0) which is essential for programming the
+ * "route" end-point config
+ */
+
+ kfree(rt_rule);
+
+ return 0;
+}
+
+static int ipa_setup_exception_path(void)
+{
+ struct ipa_ioc_add_hdr *hdr;
+ struct ipa_hdr_add *hdr_entry;
+ struct ipa_route route = { 0 };
+ int ret;
+
+ /* install the basic exception header */
+ hdr = kzalloc(sizeof(struct ipa_ioc_add_hdr) + 1 *
+ sizeof(struct ipa_hdr_add), GFP_KERNEL);
+ if (!hdr) {
+ IPAERR("fail to alloc exception hdr\n");
+ return -ENOMEM;
+ }
+ hdr->num_hdrs = 1;
+ hdr->commit = 1;
+ hdr_entry = &hdr->hdr[0];
+ strlcpy(hdr_entry->name, IPA_DFLT_HDR_NAME, IPA_RESOURCE_NAME_MAX);
+
+ /*
+ * only single stream for MBIM supported and no exception packets
+ * expected so set default header to zero
+ */
+ hdr_entry->hdr_len = 1;
+ hdr_entry->hdr[0] = 0;
+
+ /*
+ * SW does not know anything about default exception header so
+ * we don't set it. IPA HW will use it as a template
+ */
+ if (ipa_add_hdr(hdr)) {
+ IPAERR("fail to add exception hdr\n");
+ ret = -EPERM;
+ goto bail;
+ }
+
+ if (hdr_entry->status) {
+ IPAERR("fail to add exception hdr\n");
+ ret = -EPERM;
+ goto bail;
+ }
+
+ ipa_ctx->excp_hdr_hdl = hdr_entry->hdr_hdl;
+
+ /* exception packets goto LAN-WAN pipe from IPA to A5 */
+ route.route_def_pipe = IPA_A5_LAN_WAN_IN;
+ route.route_def_hdr_table = !ipa_ctx->hdr_tbl_lcl;
+
+ if (ipa_cfg_route(&route)) {
+ IPAERR("fail to add exception hdr\n");
+ ret = -EPERM;
+ goto bail;
+ }
+
+ ret = 0;
+bail:
+ kfree(hdr);
+ return ret;
+}
+
+static void ipa_handle_tx_poll_for_pipe(struct ipa_sys_context *sys)
+{
+ struct ipa_tx_pkt_wrapper *tx_pkt, *t;
+ struct sps_iovec iov;
+ unsigned long irq_flags;
+ int ret;
+
+ while (1) {
+ iov.addr = 0;
+ ret = sps_get_iovec(sys->ep->ep_hdl, &iov);
+ if (ret) {
+ pr_err("%s: sps_get_iovec failed %d\n", __func__, ret);
+ break;
+ }
+ if (!iov.addr)
+ break;
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ tx_pkt = list_first_entry(&sys->head_desc_list,
+ struct ipa_tx_pkt_wrapper, link);
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ switch (tx_pkt->cnt) {
+ case 1:
+ ipa_write_done(&tx_pkt->work);
+ break;
+ case 0xFFFF:
+ /* reached end of set */
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_for_each_entry_safe(tx_pkt, t,
+ &sys->wait_desc_list, link) {
+ list_del(&tx_pkt->link);
+ list_add(&tx_pkt->link, &sys->head_desc_list);
+ }
+ tx_pkt =
+ list_first_entry(&sys->head_desc_list,
+ struct ipa_tx_pkt_wrapper, link);
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+ ipa_write_done(&tx_pkt->work);
+ break;
+ default:
+ /* keep looping till reach the end of the set */
+ spin_lock_irqsave(&sys->spinlock,
+ irq_flags);
+ list_del(&tx_pkt->link);
+ list_add_tail(&tx_pkt->link,
+ &sys->wait_desc_list);
+ spin_unlock_irqrestore(&sys->spinlock,
+ irq_flags);
+ break;
+ }
+ }
+}
+
+static void ipa_poll_function(struct work_struct *work)
+{
+ int ret;
+ int tx_pipes[] = { IPA_A5_CMD, IPA_A5_LAN_WAN_OUT,
+ IPA_A5_WLAN_AMPDU_OUT };
+ int i;
+ int num_tx_pipes;
+
+ /* check all the system pipes for tx completions and rx available */
+ if (ipa_ctx->sys[IPA_A5_LAN_WAN_IN].ep->valid)
+ ipa_handle_rx_core();
+
+ num_tx_pipes = sizeof(tx_pipes) / sizeof(tx_pipes[0]);
+
+ if (!IPA_MOBILE_AP_MODE(ipa_ctx->mode))
+ num_tx_pipes--;
+
+ for (i = 0; i < num_tx_pipes; i++)
+ if (ipa_ctx->sys[tx_pipes[i]].ep->valid)
+ ipa_handle_tx_poll_for_pipe(&ipa_ctx->sys[tx_pipes[i]]);
+
+ /* re-post the poll work */
+ INIT_DELAYED_WORK(&ipa_ctx->poll_work, ipa_poll_function);
+ ret = schedule_delayed_work_on(smp_processor_id(), &ipa_ctx->poll_work,
+ msecs_to_jiffies(polling_delay_ms));
+
+ return;
+}
+
+static int ipa_setup_a5_pipes(void)
+{
+ struct ipa_sys_connect_params sys_in;
+ int result = 0;
+
+ /* CMD OUT (A5->IPA) */
+ memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params));
+ sys_in.client = IPA_CLIENT_A5_CMD_PROD;
+ sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ;
+ sys_in.ipa_ep_cfg.mode.mode = IPA_DMA;
+ sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_A5_LAN_WAN_CONS;
+ if (ipa_setup_sys_pipe(&sys_in, &ipa_ctx->clnt_hdl_cmd)) {
+ IPAERR(":setup sys pipe failed.\n");
+ result = -EPERM;
+ goto fail;
+ }
+
+ if (ipa_setup_exception_path()) {
+ IPAERR(":fail to setup excp path\n");
+ result = -EPERM;
+ goto fail_cmd;
+ }
+
+ /* LAN-WAN IN (IPA->A5) */
+ memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params));
+ sys_in.client = IPA_CLIENT_A5_LAN_WAN_CONS;
+ sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ;
+ sys_in.ipa_ep_cfg.hdr.hdr_a5_mux = 1;
+ sys_in.ipa_ep_cfg.hdr.hdr_len = 8; /* size of A5 exception hdr */
+ if (ipa_setup_sys_pipe(&sys_in, &ipa_ctx->clnt_hdl_data_in)) {
+ IPAERR(":setup sys pipe failed.\n");
+ result = -EPERM;
+ goto fail_cmd;
+ }
+ /* LAN-WAN OUT (A5->IPA) */
+ memset(&sys_in, 0, sizeof(struct ipa_sys_connect_params));
+ sys_in.client = IPA_CLIENT_A5_LAN_WAN_PROD;
+ sys_in.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ;
+ sys_in.ipa_ep_cfg.mode.mode = IPA_BASIC;
+ sys_in.ipa_ep_cfg.mode.dst = IPA_CLIENT_A5_LAN_WAN_CONS;
+ if (ipa_setup_sys_pipe(&sys_in, &ipa_ctx->clnt_hdl_data_out)) {
+ IPAERR(":setup sys pipe failed.\n");
+ result = -EPERM;
+ goto fail_data_out;
+ }
+ if (ipa_ctx->polling_mode) {
+ INIT_DELAYED_WORK(&ipa_ctx->poll_work, ipa_poll_function);
+ result =
+ schedule_delayed_work_on(smp_processor_id(),
+ &ipa_ctx->poll_work,
+ msecs_to_jiffies(polling_delay_ms));
+ if (!result) {
+ IPAERR(":schedule delayed work failed.\n");
+ goto fail_schedule_delayed_work;
+ }
+ }
+
+ return 0;
+
+fail_schedule_delayed_work:
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_data_out);
+fail_data_out:
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_data_in);
+fail_cmd:
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_cmd);
+fail:
+ return result;
+}
+
+static void ipa_teardown_a5_pipes(void)
+{
+ cancel_delayed_work(&ipa_ctx->poll_work);
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_data_out);
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_data_in);
+ ipa_teardown_sys_pipe(ipa_ctx->clnt_hdl_cmd);
+}
+
+static int ipa_load_pipe_connection(struct platform_device *pdev,
+ enum a2_mux_pipe_direction pipe_dir,
+ struct a2_mux_pipe_connection *pdata)
+{
+ struct device_node *node = pdev->dev.of_node;
+ int rc = 0;
+
+ if (!pdata || !pdev)
+ goto err;
+
+ /* retrieve device tree parameters */
+ for_each_child_of_node(pdev->dev.of_node, node)
+ {
+ const char *str;
+
+ rc = of_property_read_string(node, "label", &str);
+ if (rc) {
+ IPAERR("Cannot read string\n");
+ goto err;
+ }
+
+ /* Check if connection type is supported */
+ if (strncmp(str, "a2-to-ipa", 10)
+ && strncmp(str, "ipa-to-a2", 10))
+ goto err;
+
+ if (strnstr(str, "a2-to-ipa", strnlen("a2-to-ipa", 10))
+ && IPA_TO_A2 == pipe_dir)
+ continue; /* skip to the next pipe */
+ else if (strnstr(str, "ipa-to-a2", strnlen("ipa-to-a2", 10))
+ && A2_TO_IPA == pipe_dir)
+ continue; /* skip to the next pipe */
+
+
+ rc = ipa_update_connections_info(node, pdata);
+ if (rc)
+ goto err;
+ }
+
+ return 0;
+err:
+ IPAERR("%s: failed\n", __func__);
+
+ return rc;
+}
+
+static int ipa_update_connections_info(struct device_node *node,
+ struct a2_mux_pipe_connection *pipe_connection)
+{
+ u32 rc;
+ char *key;
+ uint32_t val;
+ enum ipa_pipe_mem_type mem_type;
+
+ if (!pipe_connection || !node)
+ goto err;
+
+ key = "qcom,src-bam-physical-address";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->src_phy_addr = val;
+
+ key = "qcom,ipa-bam-mem-type";
+ rc = of_property_read_u32(node, key, &mem_type);
+ if (rc)
+ goto err;
+ pipe_connection->mem_type = mem_type;
+
+ key = "qcom,src-bam-pipe-index";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->src_pipe_index = val;
+
+ key = "qcom,dst-bam-physical-address";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->dst_phy_addr = val;
+
+ key = "qcom,dst-bam-pipe-index";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->dst_pipe_index = val;
+
+ key = "qcom,data-fifo-offset";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->data_fifo_base_offset = val;
+
+ key = "qcom,data-fifo-size";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->data_fifo_size = val;
+
+ key = "qcom,descriptor-fifo-offset";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+ pipe_connection->desc_fifo_base_offset = val;
+
+ key = "qcom,descriptor-fifo-size";
+ rc = of_property_read_u32(node, key, &val);
+ if (rc)
+ goto err;
+
+ pipe_connection->desc_fifo_size = val;
+
+ return 0;
+err:
+ IPAERR("%s: Error in name %s key %s\n", __func__, node->full_name, key);
+
+ return rc;
+}
+
+/**
+* ipa_get_a2_mux_pipe_info() - Exposes A2 parameters fetched from DTS
+*
+* @pipe_dir: pipe direction
+* @pipe_connect: connect structure containing the parameters fetched from DTS
+*
+* Return codes:
+* 0: success
+* -EFAULT: invalid parameters
+*/
+int ipa_get_a2_mux_pipe_info(enum a2_mux_pipe_direction pipe_dir,
+ struct a2_mux_pipe_connection *pipe_connect)
+{
+ if (!pipe_connect) {
+ IPAERR("ipa_get_a2_mux_pipe_info switch null args\n");
+ return -EFAULT;
+ }
+
+ switch (pipe_dir) {
+ case A2_TO_IPA:
+ *pipe_connect = ipa_res.a2_to_ipa_pipe;
+ break;
+ case IPA_TO_A2:
+ *pipe_connect = ipa_res.ipa_to_a2_pipe;
+ break;
+ default:
+ IPAERR("ipa_get_a2_mux_pipe_info switch in default\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void ipa_set_aggregation_params(void)
+{
+ struct ipa_ep_cfg_aggr agg_params;
+ u32 producer_hdl = 0;
+ u32 consumer_hdl = 0;
+
+ rmnet_bridge_get_client_handles(&producer_hdl, &consumer_hdl);
+
+ agg_params.aggr = ipa_ctx->aggregation_type;
+ agg_params.aggr_byte_limit = ipa_ctx->aggregation_byte_limit;
+ agg_params.aggr_time_limit = ipa_ctx->aggregation_time_limit;
+
+ /* configure aggregation on producer */
+ agg_params.aggr_en = IPA_ENABLE_AGGR;
+ ipa_cfg_ep_aggr(producer_hdl, &agg_params);
+
+ /* configure deaggregation on consumer */
+ agg_params.aggr_en = IPA_ENABLE_DEAGGR;
+ ipa_cfg_ep_aggr(consumer_hdl, &agg_params);
+
+}
+
+/*
+ * The following device attributes are for configuring the aggregation
+ * attributes when the driver is already running.
+ * The attributes are for configuring the aggregation type
+ * (MBIM_16/MBIM_32/TLP), the aggregation byte limit and the aggregation
+ * time limit.
+ */
+static ssize_t ipa_show_aggregation_type(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ ssize_t ret_val;
+ char str[IPA_AGGR_MAX_STR_LENGTH];
+
+ if (!buf) {
+ IPAERR("buffer for ipa_show_aggregation_type is NULL\n");
+ return -EINVAL;
+ }
+
+ memset(str, 0, sizeof(str));
+
+ switch (ipa_ctx->aggregation_type) {
+ case IPA_MBIM_16:
+ strlcpy(str, "MBIM_16", IPA_AGGR_STR_IN_BYTES("MBIM_16"));
+ break;
+ case IPA_MBIM_32:
+ strlcpy(str, "MBIM_32", IPA_AGGR_STR_IN_BYTES("MBIM_32"));
+ break;
+ case IPA_TLP:
+ strlcpy(str, "TLP", IPA_AGGR_STR_IN_BYTES("TLP"));
+ break;
+ default:
+ strlcpy(str, "NONE", IPA_AGGR_STR_IN_BYTES("NONE"));
+ break;
+ }
+
+ ret_val = scnprintf(buf, PAGE_SIZE, "%s\n", str);
+
+ return ret_val;
+}
+
+static ssize_t ipa_store_aggregation_type(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ char str[IPA_AGGR_MAX_STR_LENGTH], *pstr;
+
+ if (!buf) {
+ IPAERR("buffer for ipa_store_aggregation_type is NULL\n");
+ return -EINVAL;
+ }
+
+ strlcpy(str, buf, sizeof(str));
+ pstr = strim(str);
+
+ if (!strncmp(pstr, "MBIM_16", IPA_AGGR_STR_IN_BYTES("MBIM_16")))
+ ipa_ctx->aggregation_type = IPA_MBIM_16;
+ else if (!strncmp(pstr, "MBIM_32", IPA_AGGR_STR_IN_BYTES("MBIM_32")))
+ ipa_ctx->aggregation_type = IPA_MBIM_32;
+ else if (!strncmp(pstr, "TLP", IPA_AGGR_STR_IN_BYTES("TLP")))
+ ipa_ctx->aggregation_type = IPA_TLP;
+ else {
+ IPAERR("ipa_store_aggregation_type wrong input\n");
+ return -EINVAL;
+ }
+
+ ipa_set_aggregation_params();
+
+ return count;
+}
+
+static DEVICE_ATTR(aggregation_type, S_IWUSR | S_IRUSR,
+ ipa_show_aggregation_type,
+ ipa_store_aggregation_type);
+
+static ssize_t ipa_show_aggregation_byte_limit(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ ssize_t ret_val;
+
+ if (!buf) {
+ IPAERR("buffer for ipa_show_aggregation_byte_limit is NULL\n");
+ return -EINVAL;
+ }
+
+ ret_val = scnprintf(buf, PAGE_SIZE, "%u\n",
+ ipa_ctx->aggregation_byte_limit);
+
+ return ret_val;
+}
+
+static ssize_t ipa_store_aggregation_byte_limit(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ char str[IPA_AGGR_MAX_STR_LENGTH];
+ char *pstr;
+ u32 ret = 0;
+
+ if (!buf) {
+ IPAERR("buffer for ipa_store_aggregation_byte_limit is NULL\n");
+ return -EINVAL;
+ }
+
+ strlcpy(str, buf, sizeof(str));
+ pstr = strim(str);
+
+ if (kstrtouint(pstr, IPA_AGGR_MAX_STR_LENGTH, &ret)) {
+ IPAERR("ipa_store_aggregation_byte_limit wrong input\n");
+ return -EINVAL;
+ }
+
+ ipa_ctx->aggregation_byte_limit = ret;
+
+ ipa_set_aggregation_params();
+
+ return count;
+}
+
+static DEVICE_ATTR(aggregation_byte_limit, S_IWUSR | S_IRUSR,
+ ipa_show_aggregation_byte_limit,
+ ipa_store_aggregation_byte_limit);
+
+static ssize_t ipa_show_aggregation_time_limit(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ ssize_t ret_val;
+
+ if (!buf) {
+ IPAERR("buffer for ipa_show_aggregation_time_limit is NULL\n");
+ return -EINVAL;
+ }
+
+ ret_val = scnprintf(buf,
+ PAGE_SIZE,
+ "%u\n",
+ ipa_ctx->aggregation_time_limit);
+
+ return ret_val;
+}
+
+static ssize_t ipa_store_aggregation_time_limit(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ char str[IPA_AGGR_MAX_STR_LENGTH], *pstr;
+ u32 ret = 0;
+
+ if (!buf) {
+ IPAERR("buffer for ipa_store_aggregation_time_limit is NULL\n");
+ return -EINVAL;
+ }
+
+ strlcpy(str, buf, sizeof(str));
+ pstr = strim(str);
+
+ if (kstrtouint(pstr, IPA_AGGR_MAX_STR_LENGTH, &ret)) {
+ IPAERR("ipa_store_aggregation_time_limit wrong input\n");
+ return -EINVAL;
+ }
+
+ ipa_ctx->aggregation_time_limit = ret;
+
+ ipa_set_aggregation_params();
+
+ return count;
+}
+
+static DEVICE_ATTR(aggregation_time_limit, S_IWUSR | S_IRUSR,
+ ipa_show_aggregation_time_limit,
+ ipa_store_aggregation_time_limit);
+
+static const struct file_operations ipa_drv_fops = {
+ .owner = THIS_MODULE,
+ .open = ipa_open,
+ .read = ipa_read,
+ .unlocked_ioctl = ipa_ioctl,
+};
+
+static int ipa_get_clks(struct device *dev)
+{
+ ipa_cnoc_clk = clk_get(dev, "iface_clk");
+ if (IS_ERR(ipa_cnoc_clk)) {
+ ipa_cnoc_clk = NULL;
+ IPAERR("fail to get cnoc clk\n");
+ return -ENODEV;
+ }
+
+ ipa_clk_src = clk_get(dev, "core_src_clk");
+ if (IS_ERR(ipa_clk_src)) {
+ ipa_clk_src = NULL;
+ IPAERR("fail to get ipa clk src\n");
+ return -ENODEV;
+ }
+
+ ipa_clk = clk_get(dev, "core_clk");
+ if (IS_ERR(ipa_clk)) {
+ ipa_clk = NULL;
+ IPAERR("fail to get ipa clk\n");
+ return -ENODEV;
+ }
+
+ sys_noc_ipa_axi_clk = clk_get(dev, "bus_clk");
+ if (IS_ERR(sys_noc_ipa_axi_clk)) {
+ sys_noc_ipa_axi_clk = NULL;
+ IPAERR("fail to get sys_noc_ipa_axi clk\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/**
+* ipa_enable_clks() - Turn on IPA clocks
+*
+* Return codes:
+* None
+*/
+void ipa_enable_clks(void)
+{
+ if (ipa_cnoc_clk) {
+ clk_prepare(ipa_cnoc_clk);
+ clk_enable(ipa_cnoc_clk);
+ clk_set_rate(ipa_cnoc_clk, IPA_CNOC_CLK_RATE);
+ } else {
+ WARN_ON(1);
+ }
+
+ if (ipa_clk_src)
+ clk_set_rate(ipa_clk_src, IPA_V1_CLK_RATE);
+ else
+ WARN_ON(1);
+
+ if (ipa_clk)
+ clk_prepare(ipa_clk);
+ else
+ WARN_ON(1);
+
+ if (sys_noc_ipa_axi_clk)
+ clk_prepare(sys_noc_ipa_axi_clk);
+ else
+ WARN_ON(1);
+
+ if (ipa_clk)
+ clk_enable(ipa_clk);
+ else
+ WARN_ON(1);
+
+ if (sys_noc_ipa_axi_clk)
+ clk_enable(sys_noc_ipa_axi_clk);
+ else
+ WARN_ON(1);
+}
+
+/**
+* ipa_disable_clks() - Turn off IPA clocks
+*
+* Return codes:
+* None
+*/
+void ipa_disable_clks(void)
+{
+ if (sys_noc_ipa_axi_clk)
+ clk_disable_unprepare(sys_noc_ipa_axi_clk);
+ else
+ WARN_ON(1);
+
+ if (ipa_clk)
+ clk_disable_unprepare(ipa_clk);
+ else
+ WARN_ON(1);
+
+ if (ipa_cnoc_clk)
+ clk_disable_unprepare(ipa_cnoc_clk);
+ else
+ WARN_ON(1);
+}
+
+static int ipa_setup_bam_cfg(const struct ipa_plat_drv_res *res)
+{
+ void *bam_cnfg_bits;
+
+ bam_cnfg_bits = ioremap(res->ipa_mem_base + IPA_BAM_REG_BASE_OFST,
+ IPA_BAM_REMAP_SIZE);
+ if (!bam_cnfg_bits)
+ return -ENOMEM;
+ ipa_write_reg(bam_cnfg_bits, IPA_BAM_CNFG_BITS_OFST,
+ IPA_BAM_CNFG_BITS_VAL);
+ iounmap(bam_cnfg_bits);
+
+ return 0;
+}
+/**
+* ipa_init() - Initialize the IPA Driver
+*@resource_p: contain platform specific values from DST file
+*
+* Function initialization process:
+* - Allocate memory for the driver context data struct
+* - Initializing the ipa_ctx with:
+* 1)parsed values from the dts file
+* 2)parameters passed to the module initialization
+* 3)read HW values(such as core memory size)
+* - Map IPA core registers to CPU memory
+* - Restart IPA core(HW reset)
+* - Register IPA BAM to SPS driver and get a BAM handler
+* - Set configuration for IPA BAM via BAM_CNFG_BITS
+* - Initialize the look-aside caches(kmem_cache/slab) for filter,
+* routing and IPA-tree
+* - Create memory pool with 4 objects for DMA operations(each object
+* is 512Bytes long), this object will be use for tx(A5->IPA)
+* - Initialize lists head(routing,filter,hdr,system pipes)
+* - Initialize mutexes (for ipa_ctx and NAT memory mutexes)
+* - Initialize spinlocks (for list related to A5<->IPA pipes)
+* - Initialize 2 single-threaded work-queue named "ipa rx wq" and "ipa tx wq"
+* - Initialize Red-Black-Tree(s) for handles of header,routing rule,
+* routing table ,filtering rule
+* - Setup all A5<->IPA pipes by calling to ipa_setup_a5_pipes
+* - Preparing the descriptors for System pipes
+* - Initialize the filter block by committing IPV4 and IPV6 default rules
+* - Create empty routing table in system memory(no committing)
+* - Initialize pipes memory pool with ipa_pipe_mem_init for supported platforms
+* - Create a char-device for IPA
+*/
+static int ipa_init(const struct ipa_plat_drv_res *resource_p)
+{
+ int result = 0;
+ int i;
+ struct sps_bam_props bam_props = { 0 };
+ struct ipa_flt_tbl *flt_tbl;
+ struct ipa_rt_tbl_set *rset;
+
+ IPADBG("IPA init\n");
+
+ ipa_ctx = kzalloc(sizeof(*ipa_ctx), GFP_KERNEL);
+ if (!ipa_ctx) {
+ IPAERR(":kzalloc err.\n");
+ result = -ENOMEM;
+ goto fail_mem;
+ }
+
+ IPADBG("polling_mode=%u delay_ms=%u\n", polling_mode, polling_delay_ms);
+ ipa_ctx->polling_mode = polling_mode;
+ IPADBG("hdr_lcl=%u ip4_rt=%u ip6_rt=%u ip4_flt=%u ip6_flt=%u\n",
+ hdr_tbl_lcl, ip4_rt_tbl_lcl, ip6_rt_tbl_lcl, ip4_flt_tbl_lcl,
+ ip6_flt_tbl_lcl);
+ ipa_ctx->hdr_tbl_lcl = hdr_tbl_lcl;
+ ipa_ctx->ip4_rt_tbl_lcl = ip4_rt_tbl_lcl;
+ ipa_ctx->ip6_rt_tbl_lcl = ip6_rt_tbl_lcl;
+ ipa_ctx->ip4_flt_tbl_lcl = ip4_flt_tbl_lcl;
+ ipa_ctx->ip6_flt_tbl_lcl = ip6_flt_tbl_lcl;
+
+ ipa_ctx->ipa_wrapper_base = resource_p->ipa_mem_base;
+
+ /* setup IPA register access */
+ ipa_ctx->mmio = ioremap(resource_p->ipa_mem_base + IPA_REG_BASE_OFST,
+ resource_p->ipa_mem_size);
+ if (!ipa_ctx->mmio) {
+ IPAERR(":ipa-base ioremap err.\n");
+ result = -EFAULT;
+ goto fail_remap;
+ }
+ /* do POR programming to setup HW */
+ result = ipa_init_hw();
+ if (result) {
+ IPAERR(":error initializing driver.\n");
+ result = -ENODEV;
+ goto fail_init_hw;
+ }
+ /* read how much SRAM is available for SW use */
+ ipa_ctx->smem_sz = ipa_read_reg(ipa_ctx->mmio,
+ IPA_SHARED_MEM_SIZE_OFST);
+
+ if (IPA_RAM_END_OFST > ipa_ctx->smem_sz) {
+ IPAERR("SW expect more core memory, needed %d, avail %d\n",
+ IPA_RAM_END_OFST, ipa_ctx->smem_sz);
+ result = -ENOMEM;
+ goto fail_init_hw;
+ }
+ /* register IPA with SPS driver */
+ bam_props.phys_addr = resource_p->bam_mem_base;
+ bam_props.virt_addr = ioremap(resource_p->bam_mem_base,
+ resource_p->bam_mem_size);
+ if (!bam_props.virt_addr) {
+ IPAERR(":bam-base ioremap err.\n");
+ result = -EFAULT;
+ goto fail_bam_remap;
+ }
+ bam_props.virt_size = resource_p->bam_mem_size;
+ bam_props.irq = resource_p->bam_irq;
+ bam_props.num_pipes = IPA_NUM_PIPES;
+ bam_props.summing_threshold = IPA_SUMMING_THRESHOLD;
+ bam_props.event_threshold = IPA_EVENT_THRESHOLD;
+
+ result = sps_register_bam_device(&bam_props, &ipa_ctx->bam_handle);
+ if (result) {
+ IPAERR(":bam register err.\n");
+ result = -ENODEV;
+ goto fail_bam_register;
+ }
+
+ if (ipa_setup_bam_cfg(resource_p)) {
+ IPAERR(":bam cfg err.\n");
+ result = -ENODEV;
+ goto fail_flt_rule_cache;
+ }
+
+ /* set up the default op mode */
+ ipa_ctx->mode = IPA_MODE_USB_DONGLE;
+
+ /* init the lookaside cache */
+ ipa_ctx->flt_rule_cache = kmem_cache_create("IPA FLT",
+ sizeof(struct ipa_flt_entry), 0, 0, NULL);
+ if (!ipa_ctx->flt_rule_cache) {
+ IPAERR(":ipa flt cache create failed\n");
+ result = -ENOMEM;
+ goto fail_flt_rule_cache;
+ }
+ ipa_ctx->rt_rule_cache = kmem_cache_create("IPA RT",
+ sizeof(struct ipa_rt_entry), 0, 0, NULL);
+ if (!ipa_ctx->rt_rule_cache) {
+ IPAERR(":ipa rt cache create failed\n");
+ result = -ENOMEM;
+ goto fail_rt_rule_cache;
+ }
+ ipa_ctx->hdr_cache = kmem_cache_create("IPA HDR",
+ sizeof(struct ipa_hdr_entry), 0, 0, NULL);
+ if (!ipa_ctx->hdr_cache) {
+ IPAERR(":ipa hdr cache create failed\n");
+ result = -ENOMEM;
+ goto fail_hdr_cache;
+ }
+ ipa_ctx->hdr_offset_cache =
+ kmem_cache_create("IPA HDR OFF", sizeof(struct ipa_hdr_offset_entry),
+ 0, 0, NULL);
+ if (!ipa_ctx->hdr_offset_cache) {
+ IPAERR(":ipa hdr off cache create failed\n");
+ result = -ENOMEM;
+ goto fail_hdr_offset_cache;
+ }
+ ipa_ctx->rt_tbl_cache = kmem_cache_create("IPA RT TBL",
+ sizeof(struct ipa_rt_tbl), 0, 0, NULL);
+ if (!ipa_ctx->rt_tbl_cache) {
+ IPAERR(":ipa rt tbl cache create failed\n");
+ result = -ENOMEM;
+ goto fail_rt_tbl_cache;
+ }
+ ipa_ctx->tx_pkt_wrapper_cache =
+ kmem_cache_create("IPA TX PKT WRAPPER",
+ sizeof(struct ipa_tx_pkt_wrapper), 0, 0, NULL);
+ if (!ipa_ctx->tx_pkt_wrapper_cache) {
+ IPAERR(":ipa tx pkt wrapper cache create failed\n");
+ result = -ENOMEM;
+ goto fail_tx_pkt_wrapper_cache;
+ }
+ ipa_ctx->rx_pkt_wrapper_cache =
+ kmem_cache_create("IPA RX PKT WRAPPER",
+ sizeof(struct ipa_rx_pkt_wrapper), 0, 0, NULL);
+ if (!ipa_ctx->rx_pkt_wrapper_cache) {
+ IPAERR(":ipa rx pkt wrapper cache create failed\n");
+ result = -ENOMEM;
+ goto fail_rx_pkt_wrapper_cache;
+ }
+ ipa_ctx->tree_node_cache =
+ kmem_cache_create("IPA TREE", sizeof(struct ipa_tree_node), 0, 0,
+ NULL);
+ if (!ipa_ctx->tree_node_cache) {
+ IPAERR(":ipa tree node cache create failed\n");
+ result = -ENOMEM;
+ goto fail_tree_node_cache;
+ }
+
+ /*
+ * setup DMA pool 4 byte aligned, don't cross 1k boundaries, nominal
+ * size 512 bytes
+ */
+ ipa_ctx->one_kb_no_straddle_pool = dma_pool_create("ipa_1k", NULL,
+ IPA_DMA_POOL_SIZE, IPA_DMA_POOL_ALIGNMENT,
+ IPA_DMA_POOL_BOUNDARY);
+ if (!ipa_ctx->one_kb_no_straddle_pool) {
+ IPAERR("cannot setup 1kb alloc DMA pool.\n");
+ result = -ENOMEM;
+ goto fail_dma_pool;
+ }
+
+ ipa_ctx->glob_flt_tbl[IPA_IP_v4].in_sys = !ipa_ctx->ip4_flt_tbl_lcl;
+ ipa_ctx->glob_flt_tbl[IPA_IP_v6].in_sys = !ipa_ctx->ip6_flt_tbl_lcl;
+
+ /* init the various list heads */
+ INIT_LIST_HEAD(&ipa_ctx->glob_flt_tbl[IPA_IP_v4].head_flt_rule_list);
+ INIT_LIST_HEAD(&ipa_ctx->glob_flt_tbl[IPA_IP_v6].head_flt_rule_list);
+ INIT_LIST_HEAD(&ipa_ctx->hdr_tbl.head_hdr_entry_list);
+ for (i = 0; i < IPA_HDR_BIN_MAX; i++) {
+ INIT_LIST_HEAD(&ipa_ctx->hdr_tbl.head_offset_list[i]);
+ INIT_LIST_HEAD(&ipa_ctx->hdr_tbl.head_free_offset_list[i]);
+ }
+ INIT_LIST_HEAD(&ipa_ctx->rt_tbl_set[IPA_IP_v4].head_rt_tbl_list);
+ INIT_LIST_HEAD(&ipa_ctx->rt_tbl_set[IPA_IP_v6].head_rt_tbl_list);
+ for (i = 0; i < IPA_NUM_PIPES; i++) {
+ flt_tbl = &ipa_ctx->flt_tbl[i][IPA_IP_v4];
+ INIT_LIST_HEAD(&flt_tbl->head_flt_rule_list);
+ flt_tbl->in_sys = !ipa_ctx->ip4_flt_tbl_lcl;
+
+ flt_tbl = &ipa_ctx->flt_tbl[i][IPA_IP_v6];
+ INIT_LIST_HEAD(&flt_tbl->head_flt_rule_list);
+ flt_tbl->in_sys = !ipa_ctx->ip6_flt_tbl_lcl;
+ }
+
+ rset = &ipa_ctx->reap_rt_tbl_set[IPA_IP_v4];
+ INIT_LIST_HEAD(&rset->head_rt_tbl_list);
+ rset = &ipa_ctx->reap_rt_tbl_set[IPA_IP_v6];
+ INIT_LIST_HEAD(&rset->head_rt_tbl_list);
+
+ mutex_init(&ipa_ctx->lock);
+ mutex_init(&ipa_ctx->nat_mem.lock);
+
+ for (i = 0; i < IPA_A5_SYS_MAX; i++) {
+ INIT_LIST_HEAD(&ipa_ctx->sys[i].head_desc_list);
+ spin_lock_init(&ipa_ctx->sys[i].spinlock);
+ if (i != IPA_A5_WLAN_AMPDU_OUT)
+ ipa_ctx->sys[i].ep = &ipa_ctx->ep[i];
+ else
+ ipa_ctx->sys[i].ep = &ipa_ctx->ep[WLAN_AMPDU_TX_EP];
+ INIT_LIST_HEAD(&ipa_ctx->sys[i].wait_desc_list);
+ }
+
+ ipa_ctx->rx_wq = create_singlethread_workqueue("ipa rx wq");
+ if (!ipa_ctx->rx_wq) {
+ IPAERR(":fail to create rx wq\n");
+ result = -ENOMEM;
+ goto fail_rx_wq;
+ }
+
+ ipa_ctx->tx_wq = create_singlethread_workqueue("ipa tx wq");
+ if (!ipa_ctx->tx_wq) {
+ IPAERR(":fail to create tx wq\n");
+ result = -ENOMEM;
+ goto fail_tx_wq;
+ }
+
+ ipa_ctx->hdr_hdl_tree = RB_ROOT;
+ ipa_ctx->rt_rule_hdl_tree = RB_ROOT;
+ ipa_ctx->rt_tbl_hdl_tree = RB_ROOT;
+ ipa_ctx->flt_rule_hdl_tree = RB_ROOT;
+
+ atomic_set(&ipa_ctx->ipa_active_clients, 0);
+
+ result = ipa_bridge_init();
+ if (result) {
+ IPAERR("ipa bridge init err.\n");
+ result = -ENODEV;
+ goto fail_bridge_init;
+ }
+
+ /* setup the A5-IPA pipes */
+ if (ipa_setup_a5_pipes()) {
+ IPAERR(":failed to setup IPA-A5 pipes.\n");
+ result = -ENODEV;
+ goto fail_a5_pipes;
+ }
+
+ ipa_replenish_rx_cache();
+
+ /* init the filtering block */
+ ipa_commit_flt(IPA_IP_v4);
+ ipa_commit_flt(IPA_IP_v6);
+
+ /*
+ * setup an empty routing table in system memory, this will be used
+ * to delete a routing table cleanly and safely
+ */
+ ipa_ctx->empty_rt_tbl_mem.size = IPA_ROUTING_RULE_BYTE_SIZE;
+
+ ipa_ctx->empty_rt_tbl_mem.base =
+ dma_alloc_coherent(NULL, ipa_ctx->empty_rt_tbl_mem.size,
+ &ipa_ctx->empty_rt_tbl_mem.phys_base,
+ GFP_KERNEL);
+ if (!ipa_ctx->empty_rt_tbl_mem.base) {
+ IPAERR("DMA buff alloc fail %d bytes for empty routing tbl\n",
+ ipa_ctx->empty_rt_tbl_mem.size);
+ result = -ENOMEM;
+ goto fail_empty_rt_tbl;
+ }
+ memset(ipa_ctx->empty_rt_tbl_mem.base, 0,
+ ipa_ctx->empty_rt_tbl_mem.size);
+
+ /* setup the IPA pipe mem pool */
+ ipa_pipe_mem_init(resource_p->ipa_pipe_mem_start_ofst,
+ resource_p->ipa_pipe_mem_size);
+
+ ipa_ctx->class = class_create(THIS_MODULE, DRV_NAME);
+
+ result = alloc_chrdev_region(&ipa_ctx->dev_num, 0, 1, DRV_NAME);
+ if (result) {
+ IPAERR("alloc_chrdev_region err.\n");
+ result = -ENODEV;
+ goto fail_alloc_chrdev_region;
+ }
+
+ ipa_ctx->dev = device_create(ipa_ctx->class, NULL, ipa_ctx->dev_num,
+ ipa_ctx, DRV_NAME);
+ if (IS_ERR(ipa_ctx->dev)) {
+ IPAERR(":device_create err.\n");
+ result = -ENODEV;
+ goto fail_device_create;
+ }
+
+ cdev_init(&ipa_ctx->cdev, &ipa_drv_fops);
+ ipa_ctx->cdev.owner = THIS_MODULE;
+ ipa_ctx->cdev.ops = &ipa_drv_fops; /* from LDD3 */
+
+ result = cdev_add(&ipa_ctx->cdev, ipa_ctx->dev_num, 1);
+ if (result) {
+ IPAERR(":cdev_add err=%d\n", -result);
+ result = -ENODEV;
+ goto fail_cdev_add;
+ }
+
+ /* default aggregation parameters */
+ ipa_ctx->aggregation_type = IPA_MBIM_16;
+ ipa_ctx->aggregation_byte_limit = 1;
+ ipa_ctx->aggregation_time_limit = 0;
+ IPADBG(":IPA driver init OK.\n");
+
+ /* gate IPA clocks */
+ ipa_disable_clks();
+
+ return 0;
+
+fail_cdev_add:
+ device_destroy(ipa_ctx->class, ipa_ctx->dev_num);
+fail_device_create:
+ unregister_chrdev_region(ipa_ctx->dev_num, 1);
+fail_alloc_chrdev_region:
+ if (ipa_ctx->pipe_mem_pool)
+ gen_pool_destroy(ipa_ctx->pipe_mem_pool);
+ dma_free_coherent(NULL,
+ ipa_ctx->empty_rt_tbl_mem.size,
+ ipa_ctx->empty_rt_tbl_mem.base,
+ ipa_ctx->empty_rt_tbl_mem.phys_base);
+fail_empty_rt_tbl:
+ ipa_cleanup_rx();
+ ipa_teardown_a5_pipes();
+fail_a5_pipes:
+ ipa_bridge_cleanup();
+fail_bridge_init:
+ destroy_workqueue(ipa_ctx->tx_wq);
+fail_tx_wq:
+ destroy_workqueue(ipa_ctx->rx_wq);
+fail_rx_wq:
+ dma_pool_destroy(ipa_ctx->one_kb_no_straddle_pool);
+fail_dma_pool:
+ kmem_cache_destroy(ipa_ctx->tree_node_cache);
+fail_tree_node_cache:
+ kmem_cache_destroy(ipa_ctx->rx_pkt_wrapper_cache);
+fail_rx_pkt_wrapper_cache:
+ kmem_cache_destroy(ipa_ctx->tx_pkt_wrapper_cache);
+fail_tx_pkt_wrapper_cache:
+ kmem_cache_destroy(ipa_ctx->rt_tbl_cache);
+fail_rt_tbl_cache:
+ kmem_cache_destroy(ipa_ctx->hdr_offset_cache);
+fail_hdr_offset_cache:
+ kmem_cache_destroy(ipa_ctx->hdr_cache);
+fail_hdr_cache:
+ kmem_cache_destroy(ipa_ctx->rt_rule_cache);
+fail_rt_rule_cache:
+ kmem_cache_destroy(ipa_ctx->flt_rule_cache);
+fail_flt_rule_cache:
+ sps_deregister_bam_device(ipa_ctx->bam_handle);
+fail_bam_register:
+ iounmap(bam_props.virt_addr);
+fail_bam_remap:
+fail_init_hw:
+ iounmap(ipa_ctx->mmio);
+fail_remap:
+ kfree(ipa_ctx);
+ ipa_ctx = NULL;
+fail_mem:
+ /* gate IPA clocks */
+ ipa_disable_clks();
+ return result;
+}
+
+static int ipa_plat_drv_probe(struct platform_device *pdev_p)
+{
+ int result = 0;
+ struct resource *resource_p;
+ IPADBG("IPA plat drv probe\n");
+
+ /* initialize ipa_res */
+ ipa_res.ipa_pipe_mem_start_ofst = IPA_PIPE_MEM_START_OFST;
+ ipa_res.ipa_pipe_mem_size = IPA_PIPE_MEM_SIZE;
+
+ result = ipa_load_pipe_connection(pdev_p,
+ A2_TO_IPA,
+ &ipa_res.a2_to_ipa_pipe);
+ if (0 != result)
+ IPAERR(":ipa_load_pipe_connection failed!\n");
+
+ result = ipa_load_pipe_connection(pdev_p, IPA_TO_A2,
+ &ipa_res.ipa_to_a2_pipe);
+ if (0 != result)
+ IPAERR(":ipa_load_pipe_connection failed!\n");
+
+ /* Get IPA wrapper address */
+ resource_p = platform_get_resource_byname(pdev_p, IORESOURCE_MEM,
+ "ipa-base");
+
+ if (!resource_p) {
+ IPAERR(":get resource failed for ipa-base!\n");
+ return -ENODEV;
+ } else {
+ ipa_res.ipa_mem_base = resource_p->start;
+ ipa_res.ipa_mem_size = resource_size(resource_p);
+ }
+
+ /* Get IPA BAM address */
+ resource_p = platform_get_resource_byname(pdev_p, IORESOURCE_MEM,
+ "bam-base");
+
+ if (!resource_p) {
+ IPAERR(":get resource failed for bam-base!\n");
+ return -ENODEV;
+ } else {
+ ipa_res.bam_mem_base = resource_p->start;
+ ipa_res.bam_mem_size = resource_size(resource_p);
+ }
+
+ /* Get IPA pipe mem start ofst */
+ resource_p = platform_get_resource_byname(pdev_p, IORESOURCE_MEM,
+ "ipa-pipe-mem");
+
+ if (!resource_p) {
+ IPADBG(":get resource failed for ipa-pipe-mem\n");
+ } else {
+ ipa_res.ipa_pipe_mem_start_ofst = resource_p->start;
+ ipa_res.ipa_pipe_mem_size = resource_size(resource_p);
+ }
+
+ /* Get IPA IRQ number */
+ resource_p = platform_get_resource_byname(pdev_p, IORESOURCE_IRQ,
+ "ipa-irq");
+
+ if (!resource_p) {
+ IPAERR(":get resource failed for ipa-irq!\n");
+ return -ENODEV;
+ } else {
+ ipa_res.ipa_irq = resource_p->start;
+ }
+
+ /* Get IPA BAM IRQ number */
+ resource_p = platform_get_resource_byname(pdev_p, IORESOURCE_IRQ,
+ "bam-irq");
+
+ if (!resource_p) {
+ IPAERR(":get resource failed for bam-irq!\n");
+ return -ENODEV;
+ } else {
+ ipa_res.bam_irq = resource_p->start;
+ }
+
+ IPADBG(":ipa_mem_base = 0x%x, ipa_mem_size = 0x%x\n",
+ ipa_res.ipa_mem_base, ipa_res.ipa_mem_size);
+ IPADBG(":bam_mem_base = 0x%x, bam_mem_size = 0x%x\n",
+ ipa_res.bam_mem_base, ipa_res.bam_mem_size);
+ IPADBG(":pipe_mem_start_ofst = 0x%x, pipe_mem_size = 0x%x\n",
+ ipa_res.ipa_pipe_mem_start_ofst, ipa_res.ipa_pipe_mem_size);
+
+ IPADBG(":ipa_irq = %d\n", ipa_res.ipa_irq);
+ IPADBG(":bam_irq = %d\n", ipa_res.bam_irq);
+
+ /* stash the IPA dev ptr */
+ ipa_dev = &pdev_p->dev;
+
+ /* get IPA clocks */
+ if (ipa_get_clks(ipa_dev) != 0)
+ return -ENODEV;
+
+ /* enable IPA clocks */
+ ipa_enable_clks();
+
+ /* Proceed to real initialization */
+ result = ipa_init(&ipa_res);
+ if (result)
+ IPAERR("ipa_init failed\n");
+
+ result = device_create_file(&pdev_p->dev,
+ &dev_attr_aggregation_type);
+ if (result)
+ IPAERR("failed to create device file\n");
+
+ result = device_create_file(&pdev_p->dev,
+ &dev_attr_aggregation_byte_limit);
+ if (result)
+ IPAERR("failed to create device file\n");
+
+ result = device_create_file(&pdev_p->dev,
+ &dev_attr_aggregation_time_limit);
+ if (result)
+ IPAERR("failed to create device file\n");
+
+ return result;
+}
+
+static struct platform_driver ipa_plat_drv = {
+ .probe = ipa_plat_drv_probe,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = ipa_plat_drv_match,
+ },
+};
+
+static int ipa_plat_drv_init(void)
+{
+ return platform_driver_register(&ipa_plat_drv);
+}
+
+struct ipa_context *ipa_get_ctx(void)
+{
+ return ipa_ctx;
+}
+
+static int __init ipa_module_init(void)
+{
+ int result = 0;
+
+ IPADBG("IPA module init\n");
+ ipa_debugfs_init();
+ /* Register as a platform device driver */
+ result = ipa_plat_drv_init();
+
+ return result;
+}
+
+late_initcall(ipa_module_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("IPA HW device driver");
+
diff --git a/drivers/platform/msm/ipa/ipa_bridge.c b/drivers/platform/msm/ipa/ipa_bridge.c
new file mode 100644
index 0000000..cf51ab6
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_bridge.c
@@ -0,0 +1,789 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/ratelimit.h>
+#include "ipa_i.h"
+
+enum ipa_bridge_id {
+ IPA_DL_FROM_A2,
+ IPA_DL_TO_IPA,
+ IPA_UL_FROM_IPA,
+ IPA_UL_TO_A2,
+ IPA_BRIDGE_ID_MAX
+};
+
+static int polling_min_sleep[IPA_DIR_MAX] = { 950, 950 };
+static int polling_max_sleep[IPA_DIR_MAX] = { 1050, 1050 };
+static int polling_inactivity[IPA_DIR_MAX] = { 20, 20 };
+
+struct ipa_pkt_info {
+ void *buffer;
+ dma_addr_t dma_address;
+ uint32_t len;
+ struct list_head list_node;
+};
+
+struct ipa_bridge_pipe_context {
+ struct list_head head_desc_list;
+ struct sps_pipe *pipe;
+ struct sps_connect connection;
+ struct sps_mem_buffer desc_mem_buf;
+ struct sps_register_event register_event;
+ spinlock_t spinlock;
+ u32 len;
+ u32 free_len;
+ struct list_head free_desc_list;
+};
+
+static struct ipa_bridge_pipe_context bridge[IPA_BRIDGE_ID_MAX];
+
+static struct workqueue_struct *ipa_ul_workqueue;
+static struct workqueue_struct *ipa_dl_workqueue;
+static void ipa_do_bridge_work(enum ipa_bridge_dir dir);
+
+static u32 alloc_cnt[IPA_DIR_MAX];
+
+static void ul_work_func(struct work_struct *work)
+{
+ ipa_do_bridge_work(IPA_UL);
+}
+
+static void dl_work_func(struct work_struct *work)
+{
+ ipa_do_bridge_work(IPA_DL);
+}
+
+static DECLARE_WORK(ul_work, ul_work_func);
+static DECLARE_WORK(dl_work, dl_work_func);
+
+static int ipa_switch_to_intr_mode(enum ipa_bridge_dir dir)
+{
+ int ret;
+ struct ipa_bridge_pipe_context *sys = &bridge[2 * dir];
+
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("sps_get_config() failed %d\n", ret);
+ goto fail;
+ }
+ sys->register_event.options = SPS_O_EOT;
+ ret = sps_register_event(sys->pipe, &sys->register_event);
+ if (ret) {
+ IPAERR("sps_register_event() failed %d\n", ret);
+ goto fail;
+ }
+ sys->connection.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_EOT;
+ ret = sps_set_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("sps_set_config() failed %d\n", ret);
+ goto fail;
+ }
+ ret = 0;
+fail:
+ return ret;
+}
+
+static int ipa_switch_to_poll_mode(enum ipa_bridge_dir dir)
+{
+ int ret;
+ struct ipa_bridge_pipe_context *sys = &bridge[2 * dir];
+
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("sps_get_config() failed %d\n", ret);
+ goto fail;
+ }
+ sys->connection.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+ ret = sps_set_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("sps_set_config() failed %d\n", ret);
+ goto fail;
+ }
+ ret = 0;
+fail:
+ return ret;
+}
+
+static int queue_rx_single(enum ipa_bridge_dir dir)
+{
+ struct ipa_bridge_pipe_context *sys_rx = &bridge[2 * dir];
+ struct ipa_pkt_info *info;
+ int ret;
+
+ info = kmalloc(sizeof(struct ipa_pkt_info), GFP_KERNEL);
+ if (!info) {
+ IPAERR("unable to alloc rx_pkt_info\n");
+ goto fail_pkt;
+ }
+
+ info->buffer = kmalloc(IPA_RX_SKB_SIZE, GFP_KERNEL | GFP_DMA);
+ if (!info->buffer) {
+ IPAERR("unable to alloc rx_pkt_buffer\n");
+ goto fail_buffer;
+ }
+
+ info->dma_address = dma_map_single(NULL, info->buffer, IPA_RX_SKB_SIZE,
+ DMA_BIDIRECTIONAL);
+ if (info->dma_address == 0 || info->dma_address == ~0) {
+ IPAERR("dma_map_single failure %p for %p\n",
+ (void *)info->dma_address, info->buffer);
+ goto fail_dma;
+ }
+
+ info->len = ~0;
+
+ list_add_tail(&info->list_node, &sys_rx->head_desc_list);
+ ret = sps_transfer_one(sys_rx->pipe, info->dma_address,
+ IPA_RX_SKB_SIZE, info,
+ SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
+ if (ret) {
+ list_del(&info->list_node);
+ dma_unmap_single(NULL, info->dma_address, IPA_RX_SKB_SIZE,
+ DMA_BIDIRECTIONAL);
+ IPAERR("sps_transfer_one failed %d\n", ret);
+ goto fail_dma;
+ }
+ sys_rx->len++;
+ return 0;
+
+fail_dma:
+ kfree(info->buffer);
+fail_buffer:
+ kfree(info);
+fail_pkt:
+ IPAERR("failed\n");
+ return -ENOMEM;
+}
+
+static void ipa_do_bridge_work(enum ipa_bridge_dir dir)
+{
+ struct ipa_bridge_pipe_context *sys_rx = &bridge[2 * dir];
+ struct ipa_bridge_pipe_context *sys_tx = &bridge[2 * dir + 1];
+ struct ipa_pkt_info *tx_pkt;
+ struct ipa_pkt_info *rx_pkt;
+ struct ipa_pkt_info *tmp_pkt;
+ struct sps_iovec iov;
+ int ret;
+ int inactive_cycles = 0;
+
+ while (1) {
+ ++inactive_cycles;
+ iov.addr = 0;
+ ret = sps_get_iovec(sys_tx->pipe, &iov);
+ if (ret || iov.addr == 0) {
+ /* no-op */
+ } else {
+ inactive_cycles = 0;
+
+ tx_pkt = list_first_entry(&sys_tx->head_desc_list,
+ struct ipa_pkt_info,
+ list_node);
+ list_move_tail(&tx_pkt->list_node,
+ &sys_tx->free_desc_list);
+ sys_tx->len--;
+ sys_tx->free_len++;
+ tx_pkt->len = ~0;
+ }
+
+ iov.addr = 0;
+ ret = sps_get_iovec(sys_rx->pipe, &iov);
+ if (ret || iov.addr == 0) {
+ /* no-op */
+ } else {
+ inactive_cycles = 0;
+
+ rx_pkt = list_first_entry(&sys_rx->head_desc_list,
+ struct ipa_pkt_info,
+ list_node);
+ list_del(&rx_pkt->list_node);
+ sys_rx->len--;
+ rx_pkt->len = iov.size;
+
+retry_alloc_tx:
+ if (list_empty(&sys_tx->free_desc_list)) {
+ tmp_pkt = kmalloc(sizeof(struct ipa_pkt_info),
+ GFP_KERNEL);
+ if (!tmp_pkt) {
+ pr_err_ratelimited("%s: unable to alloc tx_pkt_info\n",
+ __func__);
+ usleep_range(polling_min_sleep[dir],
+ polling_max_sleep[dir]);
+ goto retry_alloc_tx;
+ }
+
+ tmp_pkt->buffer = kmalloc(IPA_RX_SKB_SIZE,
+ GFP_KERNEL | GFP_DMA);
+ if (!tmp_pkt->buffer) {
+ pr_err_ratelimited("%s: unable to alloc tx_pkt_buffer\n",
+ __func__);
+ kfree(tmp_pkt);
+ usleep_range(polling_min_sleep[dir],
+ polling_max_sleep[dir]);
+ goto retry_alloc_tx;
+ }
+
+ tmp_pkt->dma_address = dma_map_single(NULL,
+ tmp_pkt->buffer,
+ IPA_RX_SKB_SIZE,
+ DMA_BIDIRECTIONAL);
+ if (tmp_pkt->dma_address == 0 ||
+ tmp_pkt->dma_address == ~0) {
+ pr_err_ratelimited("%s: dma_map_single failure %p for %p\n",
+ __func__,
+ (void *)tmp_pkt->dma_address,
+ tmp_pkt->buffer);
+ }
+
+ list_add_tail(&tmp_pkt->list_node,
+ &sys_tx->free_desc_list);
+ sys_tx->free_len++;
+ alloc_cnt[dir]++;
+
+ tmp_pkt->len = ~0;
+ }
+
+ tx_pkt = list_first_entry(&sys_tx->free_desc_list,
+ struct ipa_pkt_info,
+ list_node);
+ list_del(&tx_pkt->list_node);
+ sys_tx->free_len--;
+
+retry_add_rx:
+ list_add_tail(&tx_pkt->list_node,
+ &sys_rx->head_desc_list);
+ ret = sps_transfer_one(sys_rx->pipe,
+ tx_pkt->dma_address,
+ IPA_RX_SKB_SIZE,
+ tx_pkt,
+ SPS_IOVEC_FLAG_INT |
+ SPS_IOVEC_FLAG_EOT);
+ if (ret) {
+ list_del(&tx_pkt->list_node);
+ pr_err_ratelimited("%s: sps_transfer_one failed %d\n",
+ __func__, ret);
+ usleep_range(polling_min_sleep[dir],
+ polling_max_sleep[dir]);
+ goto retry_add_rx;
+ }
+ sys_rx->len++;
+
+retry_add_tx:
+ list_add_tail(&rx_pkt->list_node,
+ &sys_tx->head_desc_list);
+ ret = sps_transfer_one(sys_tx->pipe,
+ rx_pkt->dma_address,
+ iov.size,
+ rx_pkt,
+ SPS_IOVEC_FLAG_INT |
+ SPS_IOVEC_FLAG_EOT);
+ if (ret) {
+ pr_err_ratelimited("%s: fail to add to TX dir=%d\n",
+ __func__, dir);
+ list_del(&rx_pkt->list_node);
+ usleep_range(polling_min_sleep[dir],
+ polling_max_sleep[dir]);
+ goto retry_add_tx;
+ }
+ sys_tx->len++;
+ }
+
+ if (inactive_cycles >= polling_inactivity[dir]) {
+ ipa_switch_to_intr_mode(dir);
+ break;
+ }
+ }
+}
+
+static void ipa_rx_notify(struct sps_event_notify *notify)
+{
+ switch (notify->event_id) {
+ case SPS_EVENT_EOT:
+ ipa_switch_to_poll_mode(IPA_UL);
+ queue_work(ipa_ul_workqueue, &ul_work);
+ break;
+ default:
+ IPAERR("recieved unexpected event id %d\n", notify->event_id);
+ }
+}
+
+static int setup_bridge_to_ipa(enum ipa_bridge_dir dir)
+{
+ struct ipa_bridge_pipe_context *sys;
+ struct ipa_ep_cfg_mode mode;
+ dma_addr_t dma_addr;
+ int ipa_ep_idx;
+ int ret;
+ int i;
+
+ if (dir == IPA_DL) {
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode,
+ IPA_CLIENT_A2_TETHERED_PROD);
+ if (ipa_ep_idx == -1) {
+ IPAERR("Invalid client.\n");
+ ret = -EINVAL;
+ goto tx_alloc_endpoint_failed;
+ }
+
+ sys = &bridge[IPA_DL_TO_IPA];
+ sys->pipe = sps_alloc_endpoint();
+ if (sys->pipe == NULL) {
+ IPAERR("tx alloc endpoint failed\n");
+ ret = -ENOMEM;
+ goto tx_alloc_endpoint_failed;
+ }
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("tx get config failed %d\n", ret);
+ goto tx_get_config_failed;
+ }
+
+ sys->connection.source = SPS_DEV_HANDLE_MEM;
+ sys->connection.src_pipe_index = ipa_ctx->a5_pipe_index++;
+ sys->connection.destination = ipa_ctx->bam_handle;
+ sys->connection.dest_pipe_index = ipa_ep_idx;
+ sys->connection.mode = SPS_MODE_DEST;
+ sys->connection.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+ sys->desc_mem_buf.size = IPA_SYS_DESC_FIFO_SZ; /* 2k */
+ sys->desc_mem_buf.base = dma_alloc_coherent(NULL,
+ sys->desc_mem_buf.size,
+ &dma_addr,
+ 0);
+ if (sys->desc_mem_buf.base == NULL) {
+ IPAERR("tx memory alloc failed\n");
+ ret = -ENOMEM;
+ goto tx_get_config_failed;
+ }
+ sys->desc_mem_buf.phys_base = dma_addr;
+ memset(sys->desc_mem_buf.base, 0x0, sys->desc_mem_buf.size);
+ sys->connection.desc = sys->desc_mem_buf;
+ sys->connection.event_thresh = IPA_EVENT_THRESHOLD;
+
+ ret = sps_connect(sys->pipe, &sys->connection);
+ if (ret < 0) {
+ IPAERR("tx connect error %d\n", ret);
+ goto tx_connect_failed;
+ }
+
+ INIT_LIST_HEAD(&sys->head_desc_list);
+ INIT_LIST_HEAD(&sys->free_desc_list);
+ spin_lock_init(&sys->spinlock);
+
+ ipa_ctx->ep[ipa_ep_idx].valid = 1;
+
+ mode.mode = IPA_DMA;
+ mode.dst = IPA_CLIENT_USB_CONS;
+ ret = ipa_cfg_ep_mode(ipa_ep_idx, &mode);
+ if (ret < 0) {
+ IPAERR("DMA mode set error %d\n", ret);
+ goto tx_mode_set_failed;
+ }
+
+ return 0;
+
+tx_mode_set_failed:
+ sps_disconnect(sys->pipe);
+tx_connect_failed:
+ dma_free_coherent(NULL, sys->desc_mem_buf.size,
+ sys->desc_mem_buf.base,
+ sys->desc_mem_buf.phys_base);
+tx_get_config_failed:
+ sps_free_endpoint(sys->pipe);
+tx_alloc_endpoint_failed:
+ return ret;
+ } else {
+
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode,
+ IPA_CLIENT_A2_TETHERED_CONS);
+ if (ipa_ep_idx == -1) {
+ IPAERR("Invalid client.\n");
+ ret = -EINVAL;
+ goto rx_alloc_endpoint_failed;
+ }
+
+ sys = &bridge[IPA_UL_FROM_IPA];
+ sys->pipe = sps_alloc_endpoint();
+ if (sys->pipe == NULL) {
+ IPAERR("rx alloc endpoint failed\n");
+ ret = -ENOMEM;
+ goto rx_alloc_endpoint_failed;
+ }
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("rx get config failed %d\n", ret);
+ goto rx_get_config_failed;
+ }
+
+ sys->connection.source = ipa_ctx->bam_handle;
+ sys->connection.src_pipe_index = 7;
+ sys->connection.destination = SPS_DEV_HANDLE_MEM;
+ sys->connection.dest_pipe_index = ipa_ctx->a5_pipe_index++;
+ sys->connection.mode = SPS_MODE_SRC;
+ sys->connection.options = SPS_O_AUTO_ENABLE | SPS_O_EOT |
+ SPS_O_ACK_TRANSFERS;
+ sys->desc_mem_buf.size = IPA_SYS_DESC_FIFO_SZ; /* 2k */
+ sys->desc_mem_buf.base = dma_alloc_coherent(NULL,
+ sys->desc_mem_buf.size,
+ &dma_addr,
+ 0);
+ if (sys->desc_mem_buf.base == NULL) {
+ IPAERR("rx memory alloc failed\n");
+ ret = -ENOMEM;
+ goto rx_get_config_failed;
+ }
+ sys->desc_mem_buf.phys_base = dma_addr;
+ memset(sys->desc_mem_buf.base, 0x0, sys->desc_mem_buf.size);
+ sys->connection.desc = sys->desc_mem_buf;
+ sys->connection.event_thresh = IPA_EVENT_THRESHOLD;
+
+ ret = sps_connect(sys->pipe, &sys->connection);
+ if (ret < 0) {
+ IPAERR("rx connect error %d\n", ret);
+ goto rx_connect_failed;
+ }
+
+ sys->register_event.options = SPS_O_EOT;
+ sys->register_event.mode = SPS_TRIGGER_CALLBACK;
+ sys->register_event.xfer_done = NULL;
+ sys->register_event.callback = ipa_rx_notify;
+ sys->register_event.user = NULL;
+ ret = sps_register_event(sys->pipe, &sys->register_event);
+ if (ret < 0) {
+ IPAERR("tx register event error %d\n", ret);
+ goto rx_event_reg_failed;
+ }
+
+ INIT_LIST_HEAD(&sys->head_desc_list);
+ INIT_LIST_HEAD(&sys->free_desc_list);
+ spin_lock_init(&sys->spinlock);
+
+ for (i = 0; i < IPA_RX_POOL_CEIL; i++) {
+ ret = queue_rx_single(dir);
+ if (ret < 0)
+ IPAERR("queue fail %d %d\n", dir, i);
+ }
+
+ return 0;
+
+rx_event_reg_failed:
+ sps_disconnect(sys->pipe);
+rx_connect_failed:
+ dma_free_coherent(NULL,
+ sys->desc_mem_buf.size,
+ sys->desc_mem_buf.base,
+ sys->desc_mem_buf.phys_base);
+rx_get_config_failed:
+ sps_free_endpoint(sys->pipe);
+rx_alloc_endpoint_failed:
+ return ret;
+ }
+}
+
+static void bam_mux_rx_notify(struct sps_event_notify *notify)
+{
+ switch (notify->event_id) {
+ case SPS_EVENT_EOT:
+ ipa_switch_to_poll_mode(IPA_DL);
+ queue_work(ipa_dl_workqueue, &dl_work);
+ break;
+ default:
+ IPAERR("recieved unexpected event id %d\n", notify->event_id);
+ }
+}
+
+static int setup_bridge_to_a2(enum ipa_bridge_dir dir)
+{
+ struct ipa_bridge_pipe_context *sys;
+ struct a2_mux_pipe_connection pipe_conn = { 0, };
+ dma_addr_t dma_addr;
+ u32 a2_handle;
+ int ret;
+ int i;
+
+ if (dir == IPA_UL) {
+ ret = ipa_get_a2_mux_pipe_info(IPA_TO_A2, &pipe_conn);
+ if (ret) {
+ IPAERR("ipa_get_a2_mux_pipe_info failed IPA_TO_A2\n");
+ goto tx_alloc_endpoint_failed;
+ }
+
+ ret = sps_phy2h(pipe_conn.dst_phy_addr, &a2_handle);
+ if (ret) {
+ IPAERR("sps_phy2h failed (A2 BAM) %d\n", ret);
+ goto tx_alloc_endpoint_failed;
+ }
+
+ sys = &bridge[IPA_UL_TO_A2];
+ sys->pipe = sps_alloc_endpoint();
+ if (sys->pipe == NULL) {
+ IPAERR("tx alloc endpoint failed\n");
+ ret = -ENOMEM;
+ goto tx_alloc_endpoint_failed;
+ }
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("tx get config failed %d\n", ret);
+ goto tx_get_config_failed;
+ }
+
+ sys->connection.source = SPS_DEV_HANDLE_MEM;
+ sys->connection.src_pipe_index = ipa_ctx->a5_pipe_index++;
+ sys->connection.destination = a2_handle;
+ sys->connection.dest_pipe_index = pipe_conn.dst_pipe_index;
+ sys->connection.mode = SPS_MODE_DEST;
+ sys->connection.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+ sys->desc_mem_buf.size = IPA_SYS_DESC_FIFO_SZ; /* 2k */
+ sys->desc_mem_buf.base = dma_alloc_coherent(NULL,
+ sys->desc_mem_buf.size,
+ &dma_addr,
+ 0);
+ if (sys->desc_mem_buf.base == NULL) {
+ IPAERR("tx memory alloc failed\n");
+ ret = -ENOMEM;
+ goto tx_get_config_failed;
+ }
+ sys->desc_mem_buf.phys_base = dma_addr;
+ memset(sys->desc_mem_buf.base, 0x0, sys->desc_mem_buf.size);
+ sys->connection.desc = sys->desc_mem_buf;
+ sys->connection.event_thresh = IPA_EVENT_THRESHOLD;
+
+ ret = sps_connect(sys->pipe, &sys->connection);
+ if (ret < 0) {
+ IPAERR("tx connect error %d\n", ret);
+ goto tx_connect_failed;
+ }
+
+ INIT_LIST_HEAD(&sys->head_desc_list);
+ INIT_LIST_HEAD(&sys->free_desc_list);
+ spin_lock_init(&sys->spinlock);
+
+ return 0;
+
+tx_connect_failed:
+ dma_free_coherent(NULL,
+ sys->desc_mem_buf.size,
+ sys->desc_mem_buf.base,
+ sys->desc_mem_buf.phys_base);
+tx_get_config_failed:
+ sps_free_endpoint(sys->pipe);
+tx_alloc_endpoint_failed:
+ return ret;
+ } else { /* dir == IPA_UL */
+
+ ret = ipa_get_a2_mux_pipe_info(A2_TO_IPA, &pipe_conn);
+ if (ret) {
+ IPAERR("ipa_get_a2_mux_pipe_info failed A2_TO_IPA\n");
+ goto rx_alloc_endpoint_failed;
+ }
+
+ ret = sps_phy2h(pipe_conn.src_phy_addr, &a2_handle);
+ if (ret) {
+ IPAERR("sps_phy2h failed (A2 BAM) %d\n", ret);
+ goto rx_alloc_endpoint_failed;
+ }
+
+ sys = &bridge[IPA_DL_FROM_A2];
+ sys->pipe = sps_alloc_endpoint();
+ if (sys->pipe == NULL) {
+ IPAERR("rx alloc endpoint failed\n");
+ ret = -ENOMEM;
+ goto rx_alloc_endpoint_failed;
+ }
+ ret = sps_get_config(sys->pipe, &sys->connection);
+ if (ret) {
+ IPAERR("rx get config failed %d\n", ret);
+ goto rx_get_config_failed;
+ }
+
+ sys->connection.source = a2_handle;
+ sys->connection.src_pipe_index = pipe_conn.src_pipe_index;
+ sys->connection.destination = SPS_DEV_HANDLE_MEM;
+ sys->connection.dest_pipe_index = ipa_ctx->a5_pipe_index++;
+ sys->connection.mode = SPS_MODE_SRC;
+ sys->connection.options = SPS_O_AUTO_ENABLE | SPS_O_EOT |
+ SPS_O_ACK_TRANSFERS;
+ sys->desc_mem_buf.size = IPA_SYS_DESC_FIFO_SZ; /* 2k */
+ sys->desc_mem_buf.base = dma_alloc_coherent(NULL,
+ sys->desc_mem_buf.size,
+ &dma_addr,
+ 0);
+ if (sys->desc_mem_buf.base == NULL) {
+ IPAERR("rx memory alloc failed\n");
+ ret = -ENOMEM;
+ goto rx_get_config_failed;
+ }
+ sys->desc_mem_buf.phys_base = dma_addr;
+ memset(sys->desc_mem_buf.base, 0x0, sys->desc_mem_buf.size);
+ sys->connection.desc = sys->desc_mem_buf;
+ sys->connection.event_thresh = IPA_EVENT_THRESHOLD;
+
+ ret = sps_connect(sys->pipe, &sys->connection);
+ if (ret < 0) {
+ IPAERR("rx connect error %d\n", ret);
+ goto rx_connect_failed;
+ }
+
+ sys->register_event.options = SPS_O_EOT;
+ sys->register_event.mode = SPS_TRIGGER_CALLBACK;
+ sys->register_event.xfer_done = NULL;
+ sys->register_event.callback = bam_mux_rx_notify;
+ sys->register_event.user = NULL;
+ ret = sps_register_event(sys->pipe, &sys->register_event);
+ if (ret < 0) {
+ IPAERR("tx register event error %d\n", ret);
+ goto rx_event_reg_failed;
+ }
+
+ INIT_LIST_HEAD(&sys->head_desc_list);
+ INIT_LIST_HEAD(&sys->free_desc_list);
+ spin_lock_init(&sys->spinlock);
+
+
+ for (i = 0; i < IPA_RX_POOL_CEIL; i++) {
+ ret = queue_rx_single(dir);
+ if (ret < 0)
+ IPAERR("queue fail %d %d\n", dir, i);
+ }
+
+ return 0;
+
+rx_event_reg_failed:
+ sps_disconnect(sys->pipe);
+rx_connect_failed:
+ dma_free_coherent(NULL,
+ sys->desc_mem_buf.size,
+ sys->desc_mem_buf.base,
+ sys->desc_mem_buf.phys_base);
+rx_get_config_failed:
+ sps_free_endpoint(sys->pipe);
+rx_alloc_endpoint_failed:
+ return ret;
+ }
+}
+
+/**
+ * ipa_bridge_init() - initialize the tethered bridge, allocate UL and DL
+ * workqueues
+ *
+ * Return codes: 0: success, -ENOMEM: failure
+ */
+int ipa_bridge_init(void)
+{
+ int ret;
+
+ ipa_ul_workqueue = alloc_workqueue("ipa_ul",
+ WQ_MEM_RECLAIM | WQ_CPU_INTENSIVE, 1);
+ if (!ipa_ul_workqueue) {
+ IPAERR("ipa ul wq alloc failed\n");
+ ret = -ENOMEM;
+ goto fail_ul;
+ }
+
+ ipa_dl_workqueue = alloc_workqueue("ipa_dl",
+ WQ_MEM_RECLAIM | WQ_CPU_INTENSIVE, 1);
+ if (!ipa_dl_workqueue) {
+ IPAERR("ipa dl wq alloc failed\n");
+ ret = -ENOMEM;
+ goto fail_dl;
+ }
+
+ return 0;
+fail_dl:
+ destroy_workqueue(ipa_ul_workqueue);
+fail_ul:
+ return ret;
+}
+
+/**
+ * ipa_bridge_setup() - setup tethered SW bridge in specified direction
+ * @dir: downlink or uplink (from air interface perspective)
+ *
+ * Return codes:
+ * 0: success
+ * various negative error codes on errors
+ */
+int ipa_bridge_setup(enum ipa_bridge_dir dir)
+{
+ int ret;
+
+ if (atomic_inc_return(&ipa_ctx->ipa_active_clients) == 1)
+ ipa_enable_clks();
+
+ if (setup_bridge_to_a2(dir)) {
+ IPAERR("fail to setup SYS pipe to A2 %d\n", dir);
+ ret = -EINVAL;
+ goto bail_a2;
+ }
+
+ if (setup_bridge_to_ipa(dir)) {
+ IPAERR("fail to setup SYS pipe to IPA %d\n", dir);
+ ret = -EINVAL;
+ goto bail_ipa;
+ }
+
+ return 0;
+
+bail_ipa:
+ if (dir == IPA_UL)
+ sps_disconnect(bridge[IPA_UL_TO_A2].pipe);
+ else
+ sps_disconnect(bridge[IPA_DL_FROM_A2].pipe);
+bail_a2:
+ if (atomic_dec_return(&ipa_ctx->ipa_active_clients) == 0)
+ ipa_disable_clks();
+ return ret;
+}
+
+/**
+ * ipa_bridge_teardown() - teardown the tethered bridge in the specified dir
+ * @dir: downlink or uplink (from air interface perspective)
+ *
+ * Return codes:
+ * 0: always
+ */
+int ipa_bridge_teardown(enum ipa_bridge_dir dir)
+{
+ struct ipa_bridge_pipe_context *sys;
+
+ if (dir == IPA_UL) {
+ sys = &bridge[IPA_UL_TO_A2];
+ sps_disconnect(sys->pipe);
+ sys = &bridge[IPA_UL_FROM_IPA];
+ sps_disconnect(sys->pipe);
+ } else {
+ sys = &bridge[IPA_DL_FROM_A2];
+ sps_disconnect(sys->pipe);
+ sys = &bridge[IPA_DL_TO_IPA];
+ sps_disconnect(sys->pipe);
+ }
+
+ if (atomic_dec_return(&ipa_ctx->ipa_active_clients) == 0)
+ ipa_disable_clks();
+
+ return 0;
+}
+
+/**
+ * ipa_bridge_cleanup() - de-initialize the tethered bridge
+ *
+ * Return codes:
+ * None
+ */
+void ipa_bridge_cleanup(void)
+{
+ destroy_workqueue(ipa_dl_workqueue);
+ destroy_workqueue(ipa_ul_workqueue);
+}
diff --git a/drivers/platform/msm/ipa/ipa_client.c b/drivers/platform/msm/ipa/ipa_client.c
new file mode 100644
index 0000000..823b17d
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_client.c
@@ -0,0 +1,325 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ipa_i.h"
+
+static int ipa_connect_configure_sps(const struct ipa_connect_params *in,
+ struct ipa_ep_context *ep, int ipa_ep_idx)
+{
+ int result = -EFAULT;
+
+ /* Default Config */
+ ep->ep_hdl = sps_alloc_endpoint();
+
+ if (ep->ep_hdl == NULL) {
+ IPAERR("SPS EP alloc failed EP.\n");
+ return -EFAULT;
+ }
+
+ result = sps_get_config(ep->ep_hdl,
+ &ep->connect);
+ if (result) {
+ IPAERR("fail to get config.\n");
+ return -EFAULT;
+ }
+
+ /* Specific Config */
+ if (IPA_CLIENT_IS_CONS(in->client)) {
+ ep->connect.mode = SPS_MODE_SRC;
+ ep->connect.destination =
+ in->client_bam_hdl;
+ ep->connect.source = ipa_ctx->bam_handle;
+ ep->connect.dest_pipe_index =
+ in->client_ep_idx;
+ ep->connect.src_pipe_index = ipa_ep_idx;
+ } else {
+ ep->connect.mode = SPS_MODE_DEST;
+ ep->connect.source = in->client_bam_hdl;
+ ep->connect.destination = ipa_ctx->bam_handle;
+ ep->connect.src_pipe_index = in->client_ep_idx;
+ ep->connect.dest_pipe_index = ipa_ep_idx;
+ }
+
+ return 0;
+}
+
+static int ipa_connect_allocate_fifo(const struct ipa_connect_params *in,
+ struct sps_mem_buffer *mem_buff_ptr,
+ bool *fifo_in_pipe_mem_ptr,
+ u32 *fifo_pipe_mem_ofst_ptr,
+ u32 fifo_size, int ipa_ep_idx)
+{
+ dma_addr_t dma_addr;
+ u32 ofst;
+ int result = -EFAULT;
+
+ mem_buff_ptr->size = fifo_size;
+ if (in->pipe_mem_preferred) {
+ if (ipa_pipe_mem_alloc(&ofst, fifo_size)) {
+ IPAERR("FIFO pipe mem alloc fail ep %u\n",
+ ipa_ep_idx);
+ mem_buff_ptr->base =
+ dma_alloc_coherent(NULL,
+ mem_buff_ptr->size,
+ &dma_addr, GFP_KERNEL);
+ } else {
+ memset(mem_buff_ptr, 0, sizeof(struct sps_mem_buffer));
+ result = sps_setup_bam2bam_fifo(mem_buff_ptr, ofst,
+ fifo_size, 1);
+ WARN_ON(result);
+ *fifo_in_pipe_mem_ptr = 1;
+ dma_addr = mem_buff_ptr->phys_base;
+ *fifo_pipe_mem_ofst_ptr = ofst;
+ }
+ } else {
+ mem_buff_ptr->base =
+ dma_alloc_coherent(NULL, mem_buff_ptr->size,
+ &dma_addr, GFP_KERNEL);
+ }
+ mem_buff_ptr->phys_base = dma_addr;
+ if (mem_buff_ptr->base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+
+/**
+ * ipa_connect() - low-level IPA client connect
+ * @in: [in] input parameters from client
+ * @sps: [out] sps output from IPA needed by client for sps_connect
+ * @clnt_hdl: [out] opaque client handle assigned by IPA to client
+ *
+ * Should be called by the driver of the peripheral that wants to connect to
+ * IPA in BAM-BAM mode. these peripherals are A2, USB and HSIC. this api
+ * expects caller to take responsibility to add any needed headers, routing
+ * and filtering tables and rules as needed.
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_connect(const struct ipa_connect_params *in, struct ipa_sps_params *sps,
+ u32 *clnt_hdl)
+{
+ int ipa_ep_idx;
+ int ipa_ep_idx_dst;
+ int result = -EFAULT;
+ struct ipa_ep_context *ep;
+
+ if (atomic_inc_return(&ipa_ctx->ipa_active_clients) == 1)
+ ipa_enable_clks();
+
+ if (in == NULL || sps == NULL || clnt_hdl == NULL ||
+ in->client >= IPA_CLIENT_MAX ||
+ in->ipa_ep_cfg.mode.dst >= IPA_CLIENT_MAX ||
+ in->desc_fifo_sz == 0 || in->data_fifo_sz == 0) {
+ IPAERR("bad parm.\n");
+ result = -EINVAL;
+ goto fail;
+ }
+
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode, in->client);
+ if (ipa_ep_idx == -1) {
+ IPAERR("fail to alloc EP.\n");
+ goto fail;
+ }
+
+ ep = &ipa_ctx->ep[ipa_ep_idx];
+
+ if (ep->valid) {
+ IPAERR("EP already allocated.\n");
+ goto fail;
+ }
+
+ if (IPA_CLIENT_IS_PROD(in->client) &&
+ (in->ipa_ep_cfg.mode.mode == IPA_DMA)) {
+ ipa_ep_idx_dst = ipa_get_ep_mapping(ipa_ctx->mode,
+ in->ipa_ep_cfg.mode.dst);
+ if ((ipa_ep_idx_dst == -1) ||
+ (ipa_ctx->ep[ipa_ep_idx_dst].valid)) {
+ IPADBG("dst EP for IPA input pipe doesn't yet exist\n");
+ }
+ }
+
+ memset(&ipa_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa_ep_context));
+
+ ep->valid = 1;
+ ep->client = in->client;
+ ep->notify = in->notify;
+ ep->priv = in->priv;
+
+ if (ipa_cfg_ep(ipa_ep_idx, &in->ipa_ep_cfg)) {
+ IPAERR("fail to configure EP.\n");
+ goto ipa_cfg_ep_fail;
+ }
+
+ result = ipa_connect_configure_sps(in, ep, ipa_ep_idx);
+ if (result) {
+ IPAERR("fail to configure SPS.\n");
+ goto ipa_cfg_ep_fail;
+ }
+
+ if (in->desc.base == NULL) {
+ result = ipa_connect_allocate_fifo(in, &ep->connect.desc,
+ &ep->desc_fifo_in_pipe_mem,
+ &ep->desc_fifo_pipe_mem_ofst,
+ in->desc_fifo_sz, ipa_ep_idx);
+ if (result) {
+ IPAERR("fail to allocate DESC FIFO.\n");
+ goto desc_mem_alloc_fail;
+ }
+ } else {
+ IPADBG("client allocated DESC FIFO\n");
+ ep->connect.desc = in->desc;
+ ep->desc_fifo_client_allocated = 1;
+ }
+ IPADBG("Descriptor FIFO pa=0x%x, size=%d\n", ep->connect.desc.phys_base,
+ ep->connect.desc.size);
+
+ if (in->data.base == NULL) {
+ result = ipa_connect_allocate_fifo(in, &ep->connect.data,
+ &ep->data_fifo_in_pipe_mem,
+ &ep->data_fifo_pipe_mem_ofst,
+ in->data_fifo_sz, ipa_ep_idx);
+ if (result) {
+ IPAERR("fail to allocate DATA FIFO.\n");
+ goto data_mem_alloc_fail;
+ }
+ } else {
+ IPADBG("client allocated DATA FIFO\n");
+ ep->connect.data = in->data;
+ ep->data_fifo_client_allocated = 1;
+ }
+ IPADBG("Data FIFO pa=0x%x, size=%d\n", ep->connect.data.phys_base,
+ ep->connect.data.size);
+
+ ep->connect.event_thresh = IPA_EVENT_THRESHOLD;
+ ep->connect.options = SPS_O_AUTO_ENABLE; /* BAM-to-BAM */
+
+ result = sps_connect(ep->ep_hdl, &ep->connect);
+ if (result) {
+ IPAERR("sps_connect fails.\n");
+ goto sps_connect_fail;
+ }
+
+ sps->ipa_bam_hdl = ipa_ctx->bam_handle;
+ sps->ipa_ep_idx = ipa_ep_idx;
+ *clnt_hdl = ipa_ep_idx;
+ memcpy(&sps->desc, &ep->connect.desc, sizeof(struct sps_mem_buffer));
+ memcpy(&sps->data, &ep->connect.data, sizeof(struct sps_mem_buffer));
+
+ return 0;
+
+sps_connect_fail:
+ if (!ep->data_fifo_in_pipe_mem)
+ dma_free_coherent(NULL,
+ ep->connect.data.size,
+ ep->connect.data.base,
+ ep->connect.data.phys_base);
+ else
+ ipa_pipe_mem_free(ep->data_fifo_pipe_mem_ofst,
+ ep->connect.data.size);
+
+data_mem_alloc_fail:
+ if (!ep->desc_fifo_in_pipe_mem)
+ dma_free_coherent(NULL,
+ ep->connect.desc.size,
+ ep->connect.desc.base,
+ ep->connect.desc.phys_base);
+ else
+ ipa_pipe_mem_free(ep->desc_fifo_pipe_mem_ofst,
+ ep->connect.desc.size);
+
+desc_mem_alloc_fail:
+ sps_free_endpoint(ep->ep_hdl);
+ipa_cfg_ep_fail:
+ memset(&ipa_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa_ep_context));
+fail:
+ if (atomic_dec_return(&ipa_ctx->ipa_active_clients) == 0)
+ ipa_disable_clks();
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_connect);
+
+/**
+ * ipa_disconnect() - low-level IPA client disconnect
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ *
+ * Should be called by the driver of the peripheral that wants to disconnect
+ * from IPA in BAM-BAM mode. this api expects caller to take responsibility to
+ * free any needed headers, routing and filtering tables and rules as needed.
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_disconnect(u32 clnt_hdl)
+{
+ int result;
+ struct ipa_ep_context *ep;
+
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ ep = &ipa_ctx->ep[clnt_hdl];
+
+ result = sps_disconnect(ep->ep_hdl);
+ if (result) {
+ IPAERR("SPS disconnect failed.\n");
+ return -EPERM;
+ }
+
+ if (!ep->desc_fifo_client_allocated &&
+ ep->connect.desc.base) {
+ if (!ep->desc_fifo_in_pipe_mem)
+ dma_free_coherent(NULL,
+ ep->connect.desc.size,
+ ep->connect.desc.base,
+ ep->connect.desc.phys_base);
+ else
+ ipa_pipe_mem_free(ep->desc_fifo_pipe_mem_ofst,
+ ep->connect.desc.size);
+ }
+
+ if (!ep->data_fifo_client_allocated &&
+ ep->connect.data.base) {
+ if (!ep->data_fifo_in_pipe_mem)
+ dma_free_coherent(NULL,
+ ep->connect.data.size,
+ ep->connect.data.base,
+ ep->connect.data.phys_base);
+ else
+ ipa_pipe_mem_free(ep->data_fifo_pipe_mem_ofst,
+ ep->connect.data.size);
+ }
+
+ result = sps_free_endpoint(ep->ep_hdl);
+ if (result) {
+ IPAERR("SPS de-alloc EP failed.\n");
+ return -EPERM;
+ }
+
+ memset(&ipa_ctx->ep[clnt_hdl], 0, sizeof(struct ipa_ep_context));
+
+ if (atomic_dec_return(&ipa_ctx->ipa_active_clients) == 0)
+ ipa_disable_clks();
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_disconnect);
+
diff --git a/drivers/platform/msm/ipa/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_debugfs.c
new file mode 100644
index 0000000..43b0178d
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_debugfs.c
@@ -0,0 +1,507 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include "ipa_i.h"
+
+
+#define IPA_MAX_MSG_LEN 1024
+static struct dentry *dent;
+static struct dentry *dfile_gen_reg;
+static struct dentry *dfile_ep_reg;
+static struct dentry *dfile_hdr;
+static struct dentry *dfile_ip4_rt;
+static struct dentry *dfile_ip6_rt;
+static struct dentry *dfile_ip4_flt;
+static struct dentry *dfile_ip6_flt;
+static char dbg_buff[IPA_MAX_MSG_LEN];
+static s8 ep_reg_idx;
+
+static ssize_t ipa_read_gen_reg(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ int nbytes;
+
+ nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,
+ "IPA_VERSION=0x%x\n"
+ "IPA_COMP_HW_VERSION=0x%x\n"
+ "IPA_ROUTE=0x%x\n"
+ "IPA_FILTER=0x%x\n"
+ "IPA_SHARED_MEM_SIZE=0x%x\n"
+ "IPA_HEAD_OF_LINE_BLOCK_EN=0x%x\n",
+ ipa_read_reg(ipa_ctx->mmio, IPA_VERSION_OFST),
+ ipa_read_reg(ipa_ctx->mmio, IPA_COMP_HW_VERSION_OFST),
+ ipa_read_reg(ipa_ctx->mmio, IPA_ROUTE_OFST),
+ ipa_read_reg(ipa_ctx->mmio, IPA_FILTER_OFST),
+ ipa_read_reg(ipa_ctx->mmio, IPA_SHARED_MEM_SIZE_OFST),
+ ipa_read_reg(ipa_ctx->mmio,
+ IPA_HEAD_OF_LINE_BLOCK_EN_OFST));
+
+ return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, nbytes);
+}
+
+static ssize_t ipa_write_ep_reg(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ unsigned long missing;
+ s8 option = 0;
+
+ if (sizeof(dbg_buff) < count + 1)
+ return -EFAULT;
+
+ missing = copy_from_user(dbg_buff, buf, count);
+ if (missing)
+ return -EFAULT;
+
+ dbg_buff[count] = '\0';
+ if (kstrtos8(dbg_buff, 0, &option))
+ return -EFAULT;
+
+ if (option >= IPA_NUM_PIPES) {
+ IPAERR("bad pipe specified %u\n", option);
+ return count;
+ }
+
+ ep_reg_idx = option;
+
+ return count;
+}
+
+static ssize_t ipa_read_ep_reg(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ int nbytes;
+ int i;
+ int start_idx;
+ int end_idx;
+ int size = 0;
+ int ret;
+ loff_t pos;
+
+ /* negative ep_reg_idx means all registers */
+ if (ep_reg_idx < 0) {
+ start_idx = 0;
+ end_idx = IPA_NUM_PIPES;
+ } else {
+ start_idx = ep_reg_idx;
+ end_idx = start_idx + 1;
+ }
+ pos = *ppos;
+ for (i = start_idx; i < end_idx; i++) {
+
+ nbytes = scnprintf(dbg_buff, IPA_MAX_MSG_LEN,
+ "IPA_ENDP_INIT_NAT_%u=0x%x\n"
+ "IPA_ENDP_INIT_HDR_%u=0x%x\n"
+ "IPA_ENDP_INIT_MODE_%u=0x%x\n"
+ "IPA_ENDP_INIT_AGGR_%u=0x%x\n"
+ "IPA_ENDP_INIT_ROUTE_%u=0x%x\n",
+ i, ipa_read_reg(ipa_ctx->mmio,
+ IPA_ENDP_INIT_NAT_n_OFST(i)),
+ i, ipa_read_reg(ipa_ctx->mmio,
+ IPA_ENDP_INIT_HDR_n_OFST(i)),
+ i, ipa_read_reg(ipa_ctx->mmio,
+ IPA_ENDP_INIT_MODE_n_OFST(i)),
+ i, ipa_read_reg(ipa_ctx->mmio,
+ IPA_ENDP_INIT_AGGR_n_OFST(i)),
+ i, ipa_read_reg(ipa_ctx->mmio,
+ IPA_ENDP_INIT_ROUTE_n_OFST(i)));
+ *ppos = pos;
+ ret = simple_read_from_buffer(ubuf, count, ppos, dbg_buff,
+ nbytes);
+ if (ret < 0)
+ return ret;
+
+ size += ret;
+ ubuf += nbytes;
+ count -= nbytes;
+ }
+
+ *ppos = pos + size;
+ return size;
+}
+
+static ssize_t ipa_read_hdr(struct file *file, char __user *ubuf, size_t count,
+ loff_t *ppos)
+{
+ int nbytes = 0;
+ int cnt = 0;
+ int i = 0;
+ struct ipa_hdr_entry *entry;
+
+ mutex_lock(&ipa_ctx->lock);
+ list_for_each_entry(entry, &ipa_ctx->hdr_tbl.head_hdr_entry_list,
+ link) {
+ nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt,
+ "name:%s len=%d ref=%d partial=%d lcl=%d ofst=%u ",
+ entry->name,
+ entry->hdr_len, entry->ref_cnt,
+ entry->is_partial,
+ ipa_ctx->hdr_tbl_lcl,
+ entry->offset_entry->offset >> 2);
+ for (i = 0; i < entry->hdr_len; i++) {
+ scnprintf(dbg_buff + cnt + nbytes + i * 2,
+ IPA_MAX_MSG_LEN - cnt - nbytes - i * 2,
+ "%02x", entry->hdr[i]);
+ }
+ scnprintf(dbg_buff + cnt + nbytes + entry->hdr_len * 2,
+ IPA_MAX_MSG_LEN - cnt - nbytes - entry->hdr_len * 2,
+ "\n");
+ cnt += nbytes + entry->hdr_len * 2 + 1;
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt);
+}
+
+static int ipa_attrib_dump(char *buff, size_t sz,
+ struct ipa_rule_attrib *attrib, enum ipa_ip_type ip)
+{
+ int nbytes = 0;
+ int cnt = 0;
+ uint32_t addr[4];
+ uint32_t mask[4];
+ int i;
+
+ if (attrib->attrib_mask & IPA_FLT_TOS) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "tos:%d ",
+ attrib->u.v4.tos);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_PROTOCOL) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "protocol:%d ",
+ attrib->u.v4.protocol);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) {
+ if (ip == IPA_IP_v4) {
+ addr[0] = htonl(attrib->u.v4.src_addr);
+ mask[0] = htonl(attrib->u.v4.src_addr_mask);
+ nbytes = scnprintf(buff + cnt, sz - cnt,
+ "src_addr:%pI4 src_addr_mask:%pI4 ",
+ addr + 0, mask + 0);
+ cnt += nbytes;
+ } else if (ip == IPA_IP_v6) {
+ for (i = 0; i < 4; i++) {
+ addr[i] = htonl(attrib->u.v6.src_addr[i]);
+ mask[i] = htonl(attrib->u.v6.src_addr_mask[i]);
+ }
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt,
+ "src_addr:%pI6 src_addr_mask:%pI6 ",
+ addr + 0, mask + 0);
+ cnt += nbytes;
+ } else {
+ WARN_ON(1);
+ }
+ }
+ if (attrib->attrib_mask & IPA_FLT_DST_ADDR) {
+ if (ip == IPA_IP_v4) {
+ addr[0] = htonl(attrib->u.v4.dst_addr);
+ mask[0] = htonl(attrib->u.v4.dst_addr_mask);
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt,
+ "dst_addr:%pI4 dst_addr_mask:%pI4 ",
+ addr + 0, mask + 0);
+ cnt += nbytes;
+ } else if (ip == IPA_IP_v6) {
+ for (i = 0; i < 4; i++) {
+ addr[i] = htonl(attrib->u.v6.dst_addr[i]);
+ mask[i] = htonl(attrib->u.v6.dst_addr_mask[i]);
+ }
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt,
+ "dst_addr:%pI6 dst_addr_mask:%pI6 ",
+ addr + 0, mask + 0);
+ cnt += nbytes;
+ } else {
+ WARN_ON(1);
+ }
+ }
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) {
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt, "src_port_range:%u %u ",
+ attrib->src_port_lo,
+ attrib->src_port_hi);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) {
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt, "dst_port_range:%u %u ",
+ attrib->dst_port_lo,
+ attrib->dst_port_hi);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_TYPE) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "type:%d ",
+ attrib->type);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_CODE) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "code:%d ",
+ attrib->code);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_SPI) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "spi:%x ",
+ attrib->spi);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "src_port:%u ",
+ attrib->src_port);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "dst_port:%u ",
+ attrib->dst_port);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_TC) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "tc:%d ",
+ attrib->u.v6.tc);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_FLOW_LABEL) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "flow_label:%x ",
+ attrib->u.v6.flow_label);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_NEXT_HDR) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "next_hdr:%d ",
+ attrib->u.v6.next_hdr);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_META_DATA) {
+ nbytes =
+ scnprintf(buff + cnt, sz - cnt,
+ "metadata:%x metadata_mask:%x",
+ attrib->meta_data, attrib->meta_data_mask);
+ cnt += nbytes;
+ }
+ if (attrib->attrib_mask & IPA_FLT_FRAGMENT) {
+ nbytes = scnprintf(buff + cnt, sz - cnt, "frg ");
+ cnt += nbytes;
+ }
+ nbytes = scnprintf(buff + cnt, sz - cnt, "\n");
+ cnt += nbytes;
+
+ return cnt;
+}
+
+static int ipa_open_dbg(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t ipa_read_rt(struct file *file, char __user *ubuf, size_t count,
+ loff_t *ppos)
+{
+ int nbytes = 0;
+ int cnt = 0;
+ int i = 0;
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_entry *entry;
+ struct ipa_rt_tbl_set *set;
+ enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data;
+ u32 hdr_ofst;
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+
+ mutex_lock(&ipa_ctx->lock);
+ list_for_each_entry(tbl, &set->head_rt_tbl_list, link) {
+ i = 0;
+ list_for_each_entry(entry, &tbl->head_rt_rule_list, link) {
+ if (entry->hdr)
+ hdr_ofst = entry->hdr->offset_entry->offset;
+ else
+ hdr_ofst = 0;
+ nbytes = scnprintf(dbg_buff + cnt,
+ IPA_MAX_MSG_LEN - cnt,
+ "tbl_idx:%d tbl_name:%s tbl_ref:%u rule_idx:%d dst:%d ep:%d S:%u hdr_ofst[words]:%u attrib_mask:%08x ",
+ entry->tbl->idx, entry->tbl->name,
+ entry->tbl->ref_cnt, i, entry->rule.dst,
+ ipa_get_ep_mapping(ipa_ctx->mode,
+ entry->rule.dst),
+ !ipa_ctx->hdr_tbl_lcl,
+ hdr_ofst >> 2,
+ entry->rule.attrib.attrib_mask);
+ cnt += nbytes;
+ cnt += ipa_attrib_dump(dbg_buff + cnt,
+ IPA_MAX_MSG_LEN - cnt,
+ &entry->rule.attrib,
+ ip);
+ i++;
+ }
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt);
+}
+
+static ssize_t ipa_read_flt(struct file *file, char __user *ubuf, size_t count,
+ loff_t *ppos)
+{
+ int nbytes = 0;
+ int cnt = 0;
+ int i;
+ int j;
+ struct ipa_flt_tbl *tbl;
+ struct ipa_flt_entry *entry;
+ enum ipa_ip_type ip = (enum ipa_ip_type)file->private_data;
+ struct ipa_rt_tbl *rt_tbl;
+
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+ mutex_lock(&ipa_ctx->lock);
+ i = 0;
+ list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
+ rt_tbl = (struct ipa_rt_tbl *)entry->rule.rt_tbl_hdl;
+ nbytes = scnprintf(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt,
+ "ep_idx:global rule_idx:%d act:%d rt_tbl_idx:%d attrib_mask:%08x ",
+ i, entry->rule.action, rt_tbl->idx,
+ entry->rule.attrib.attrib_mask);
+ cnt += nbytes;
+ cnt += ipa_attrib_dump(dbg_buff + cnt, IPA_MAX_MSG_LEN - cnt,
+ &entry->rule.attrib, ip);
+ i++;
+ }
+
+ for (j = 0; j < IPA_NUM_PIPES; j++) {
+ tbl = &ipa_ctx->flt_tbl[j][ip];
+ i = 0;
+ list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
+ rt_tbl = (struct ipa_rt_tbl *)entry->rule.rt_tbl_hdl;
+ nbytes = scnprintf(dbg_buff + cnt,
+ IPA_MAX_MSG_LEN - cnt,
+ "ep_idx:%d rule_idx:%d act:%d rt_tbl_idx:%d attrib_mask:%08x ",
+ j, i, entry->rule.action, rt_tbl->idx,
+ entry->rule.attrib.attrib_mask);
+ cnt += nbytes;
+ cnt +=
+ ipa_attrib_dump(dbg_buff + cnt,
+ IPA_MAX_MSG_LEN - cnt,
+ &entry->rule.attrib,
+ ip);
+ i++;
+ }
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return simple_read_from_buffer(ubuf, count, ppos, dbg_buff, cnt);
+}
+
+const struct file_operations ipa_gen_reg_ops = {
+ .read = ipa_read_gen_reg,
+};
+
+const struct file_operations ipa_ep_reg_ops = {
+ .read = ipa_read_ep_reg,
+ .write = ipa_write_ep_reg,
+};
+
+const struct file_operations ipa_hdr_ops = {
+ .read = ipa_read_hdr,
+};
+
+const struct file_operations ipa_rt_ops = {
+ .read = ipa_read_rt,
+ .open = ipa_open_dbg,
+};
+
+const struct file_operations ipa_flt_ops = {
+ .read = ipa_read_flt,
+ .open = ipa_open_dbg,
+};
+
+void ipa_debugfs_init(void)
+{
+ const mode_t read_only_mode = S_IRUSR | S_IRGRP | S_IROTH;
+ const mode_t read_write_mode = S_IRUSR | S_IRGRP | S_IROTH |
+ S_IWUSR | S_IWGRP | S_IWOTH;
+
+ dent = debugfs_create_dir("ipa", 0);
+ if (IS_ERR(dent)) {
+ IPAERR("fail to create folder in debug_fs.\n");
+ return;
+ }
+
+ dfile_gen_reg = debugfs_create_file("gen_reg", read_only_mode, dent, 0,
+ &ipa_gen_reg_ops);
+ if (!dfile_gen_reg || IS_ERR(dfile_gen_reg)) {
+ IPAERR("fail to create file for debug_fs gen_reg\n");
+ goto fail;
+ }
+
+ dfile_ep_reg = debugfs_create_file("ep_reg", read_write_mode, dent, 0,
+ &ipa_ep_reg_ops);
+ if (!dfile_ep_reg || IS_ERR(dfile_ep_reg)) {
+ IPAERR("fail to create file for debug_fs ep_reg\n");
+ goto fail;
+ }
+
+ dfile_hdr = debugfs_create_file("hdr", read_only_mode, dent, 0,
+ &ipa_hdr_ops);
+ if (!dfile_hdr || IS_ERR(dfile_hdr)) {
+ IPAERR("fail to create file for debug_fs hdr\n");
+ goto fail;
+ }
+
+ dfile_ip4_rt = debugfs_create_file("ip4_rt", read_only_mode, dent,
+ (void *)IPA_IP_v4, &ipa_rt_ops);
+ if (!dfile_ip4_rt || IS_ERR(dfile_ip4_rt)) {
+ IPAERR("fail to create file for debug_fs ip4 rt\n");
+ goto fail;
+ }
+
+ dfile_ip6_rt = debugfs_create_file("ip6_rt", read_only_mode, dent,
+ (void *)IPA_IP_v6, &ipa_rt_ops);
+ if (!dfile_ip6_rt || IS_ERR(dfile_ip6_rt)) {
+ IPAERR("fail to create file for debug_fs ip6:w" " rt\n");
+ goto fail;
+ }
+
+ dfile_ip4_flt = debugfs_create_file("ip4_flt", read_only_mode, dent,
+ (void *)IPA_IP_v4, &ipa_flt_ops);
+ if (!dfile_ip4_flt || IS_ERR(dfile_ip4_flt)) {
+ IPAERR("fail to create file for debug_fs ip4 flt\n");
+ goto fail;
+ }
+
+ dfile_ip6_flt = debugfs_create_file("ip6_flt", read_only_mode, dent,
+ (void *)IPA_IP_v6, &ipa_flt_ops);
+ if (!dfile_ip6_flt || IS_ERR(dfile_ip6_flt)) {
+ IPAERR("fail to create file for debug_fs ip6 flt\n");
+ goto fail;
+ }
+
+ return;
+
+fail:
+ debugfs_remove_recursive(dent);
+}
+
+void ipa_debugfs_remove(void)
+{
+ if (IS_ERR(dent)) {
+ IPAERR("ipa_debugfs_remove: folder was not created.\n");
+ return;
+ }
+ debugfs_remove_recursive(dent);
+}
+
+#else /* !CONFIG_DEBUG_FS */
+void ipa_debugfs_init(void) {}
+void ipa_debugfs_remove(void) {}
+#endif
+
diff --git a/drivers/platform/msm/ipa/ipa_dp.c b/drivers/platform/msm/ipa/ipa_dp.c
new file mode 100644
index 0000000..c677a6e
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_dp.c
@@ -0,0 +1,1038 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include "ipa_i.h"
+
+#define list_next_entry(pos, member) \
+ list_entry(pos->member.next, typeof(*pos), member)
+/**
+ * ipa_write_done - this function will be (enevtually) called when a Tx
+ * operation is complete
+ * @work: work_struct used by the work queue
+ */
+void ipa_write_done(struct work_struct *work)
+{
+ struct ipa_tx_pkt_wrapper *tx_pkt;
+ struct ipa_tx_pkt_wrapper *next_pkt;
+ struct ipa_tx_pkt_wrapper *tx_pkt_expected;
+ unsigned long irq_flags;
+ struct ipa_mem_buffer mult = { 0 };
+ int i;
+ u16 cnt;
+
+ tx_pkt = container_of(work, struct ipa_tx_pkt_wrapper, work);
+ cnt = tx_pkt->cnt;
+ IPADBG("cnt=%d\n", cnt);
+
+ if (unlikely(cnt == 0))
+ WARN_ON(1);
+
+ if (cnt > 1 && cnt != 0xFFFF)
+ mult = tx_pkt->mult;
+
+ for (i = 0; i < cnt; i++) {
+ if (unlikely(tx_pkt == NULL))
+ WARN_ON(1);
+ spin_lock_irqsave(&tx_pkt->sys->spinlock, irq_flags);
+ tx_pkt_expected = list_first_entry(&tx_pkt->sys->head_desc_list,
+ struct ipa_tx_pkt_wrapper,
+ link);
+ if (unlikely(tx_pkt != tx_pkt_expected)) {
+ spin_unlock_irqrestore(&tx_pkt->sys->spinlock,
+ irq_flags);
+ WARN_ON(1);
+ }
+ next_pkt = list_next_entry(tx_pkt, link);
+ list_del(&tx_pkt->link);
+ tx_pkt->sys->len--;
+ spin_unlock_irqrestore(&tx_pkt->sys->spinlock, irq_flags);
+ dma_pool_free(ipa_ctx->one_kb_no_straddle_pool, tx_pkt->bounce,
+ tx_pkt->mem.phys_base);
+ if (tx_pkt->callback)
+ tx_pkt->callback(tx_pkt->user1, tx_pkt->user2);
+
+ kmem_cache_free(ipa_ctx->tx_pkt_wrapper_cache, tx_pkt);
+ tx_pkt = next_pkt;
+ }
+
+ if (mult.phys_base)
+ dma_free_coherent(NULL, mult.size, mult.base, mult.phys_base);
+}
+
+/**
+ * ipa_send_one() - Send a single descriptor
+ * @sys: system pipe context
+ * @desc: descriptor to send
+ *
+ * Return codes: 0: success, -EFAULT: failure
+ */
+int ipa_send_one(struct ipa_sys_context *sys, struct ipa_desc *desc)
+{
+ struct ipa_tx_pkt_wrapper *tx_pkt;
+ unsigned long irq_flags;
+ int result;
+ u16 sps_flags = SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_INT;
+ dma_addr_t dma_address;
+ u16 len;
+
+ tx_pkt = kmem_cache_zalloc(ipa_ctx->tx_pkt_wrapper_cache, GFP_KERNEL);
+ if (!tx_pkt) {
+ IPAERR("failed to alloc tx wrapper\n");
+ goto fail_mem_alloc;
+ }
+
+ WARN_ON(desc->len > 512);
+
+ /*
+ * Due to a HW limitation, we need to make sure that the packet does not
+ * cross a 1KB boundary
+ */
+ tx_pkt->bounce = dma_pool_alloc(ipa_ctx->one_kb_no_straddle_pool,
+ GFP_KERNEL, &dma_address);
+ if (!tx_pkt->bounce) {
+ dma_address = 0;
+ } else {
+ WARN_ON(!ipa_straddle_boundary
+ ((u32)dma_address, (u32)dma_address + desc->len - 1,
+ 1024));
+ memcpy(tx_pkt->bounce, desc->pyld, desc->len);
+ }
+
+ if (!dma_address) {
+ IPAERR("failed to DMA wrap\n");
+ goto fail_dma_map;
+ }
+
+ INIT_LIST_HEAD(&tx_pkt->link);
+ INIT_WORK(&tx_pkt->work, ipa_write_done);
+ tx_pkt->type = desc->type;
+ tx_pkt->cnt = 1; /* only 1 desc in this "set" */
+
+ tx_pkt->mem.phys_base = dma_address;
+ tx_pkt->mem.base = desc->pyld;
+ tx_pkt->mem.size = desc->len;
+ tx_pkt->sys = sys;
+ tx_pkt->callback = desc->callback;
+ tx_pkt->user1 = desc->user1;
+ tx_pkt->user2 = desc->user2;
+
+ /*
+ * Special treatment for immediate commands, where the structure of the
+ * descriptor is different
+ */
+ if (desc->type == IPA_IMM_CMD_DESC) {
+ sps_flags |= SPS_IOVEC_FLAG_IMME;
+ len = desc->opcode;
+ } else {
+ len = desc->len;
+ }
+
+ if (desc->type == IPA_IMM_CMD_DESC) {
+ IPADBG("sending cmd=%d pyld_len=%d sps_flags=%x\n",
+ desc->opcode, desc->len, sps_flags);
+ IPA_DUMP_BUFF(desc->pyld, dma_address, desc->len);
+ }
+
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_add_tail(&tx_pkt->link, &sys->head_desc_list);
+ sys->len++;
+ result = sps_transfer_one(sys->ep->ep_hdl, dma_address, len, tx_pkt,
+ sps_flags);
+ if (result) {
+ IPAERR("sps_transfer_one failed rc=%d\n", result);
+ goto fail_sps_send;
+ }
+
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ return 0;
+
+fail_sps_send:
+ list_del(&tx_pkt->link);
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+ dma_pool_free(ipa_ctx->one_kb_no_straddle_pool, tx_pkt->bounce,
+ dma_address);
+fail_dma_map:
+ kmem_cache_free(ipa_ctx->tx_pkt_wrapper_cache, tx_pkt);
+fail_mem_alloc:
+ return -EFAULT;
+}
+
+/**
+ * ipa_send() - Send multiple descriptors in one HW transaction
+ * @sys: system pipe context
+ * @num_desc: number of packets
+ * @desc: packets to send
+ *
+ * Return codes: 0: success, -EFAULT: failure
+ */
+int ipa_send(struct ipa_sys_context *sys, u16 num_desc, struct ipa_desc *desc)
+{
+ struct ipa_tx_pkt_wrapper *tx_pkt;
+ struct ipa_tx_pkt_wrapper *next_pkt;
+ struct sps_transfer transfer = { 0 };
+ struct sps_iovec *iovec;
+ unsigned long irq_flags;
+ dma_addr_t dma_addr;
+ int i;
+ int j;
+ int result;
+ int fail_dma_wrap;
+ uint size = num_desc * sizeof(struct sps_iovec);
+
+ for (i = 0; i < num_desc; i++) {
+ fail_dma_wrap = 0;
+ tx_pkt = kmem_cache_zalloc(ipa_ctx->tx_pkt_wrapper_cache,
+ GFP_KERNEL);
+ if (!tx_pkt) {
+ IPAERR("failed to alloc tx wrapper\n");
+ goto failure;
+ }
+ /*
+ * first desc of set is "special" as it holds the count and
+ * other info
+ */
+ if (i == 0) {
+ transfer.user = tx_pkt;
+ transfer.iovec =
+ dma_alloc_coherent(NULL, size, &dma_addr, 0);
+ transfer.iovec_phys = dma_addr;
+ transfer.iovec_count = num_desc;
+ if (!transfer.iovec) {
+ IPAERR("fail alloc DMA mem for sps xfr buff\n");
+ goto failure;
+ }
+
+ tx_pkt->mult.phys_base = dma_addr;
+ tx_pkt->mult.base = transfer.iovec;
+ tx_pkt->mult.size = size;
+ tx_pkt->cnt = num_desc;
+ }
+
+ iovec = &transfer.iovec[i];
+ iovec->flags = 0;
+
+ INIT_LIST_HEAD(&tx_pkt->link);
+ INIT_WORK(&tx_pkt->work, ipa_write_done);
+ tx_pkt->type = desc[i].type;
+
+ tx_pkt->mem.base = desc[i].pyld;
+ tx_pkt->mem.size = desc[i].len;
+
+ WARN_ON(tx_pkt->mem.size > 512);
+
+ /*
+ * Due to a HW limitation, we need to make sure that the
+ * packet does not cross a 1KB boundary
+ */
+ tx_pkt->bounce =
+ dma_pool_alloc(ipa_ctx->one_kb_no_straddle_pool, GFP_KERNEL,
+ &tx_pkt->mem.phys_base);
+ if (!tx_pkt->bounce) {
+ tx_pkt->mem.phys_base = 0;
+ } else {
+ WARN_ON(!ipa_straddle_boundary(
+ (u32)tx_pkt->mem.phys_base,
+ (u32)tx_pkt->mem.phys_base +
+ tx_pkt->mem.size - 1, 1024));
+ memcpy(tx_pkt->bounce, tx_pkt->mem.base,
+ tx_pkt->mem.size);
+ }
+
+ if (!tx_pkt->mem.phys_base) {
+ IPAERR("failed to alloc tx wrapper\n");
+ fail_dma_wrap = 1;
+ goto failure;
+ }
+
+ tx_pkt->sys = sys;
+ tx_pkt->callback = desc[i].callback;
+ tx_pkt->user1 = desc[i].user1;
+ tx_pkt->user2 = desc[i].user2;
+
+ iovec->addr = tx_pkt->mem.phys_base;
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_add_tail(&tx_pkt->link, &sys->head_desc_list);
+ sys->len++;
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ /*
+ * Special treatment for immediate commands, where the structure
+ * of the descriptor is different
+ */
+ if (desc[i].type == IPA_IMM_CMD_DESC) {
+ iovec->size = desc[i].opcode;
+ iovec->flags |= SPS_IOVEC_FLAG_IMME;
+ } else {
+ iovec->size = desc[i].len;
+ }
+
+ if (i == (num_desc - 1)) {
+ iovec->flags |= (SPS_IOVEC_FLAG_EOT |
+ SPS_IOVEC_FLAG_INT);
+ /* "mark" the last desc */
+ tx_pkt->cnt = 0xFFFF;
+ }
+ }
+
+ result = sps_transfer(sys->ep->ep_hdl, &transfer);
+ if (result) {
+ IPAERR("sps_transfer failed rc=%d\n", result);
+ goto failure;
+ }
+
+ return 0;
+
+failure:
+ tx_pkt = transfer.user;
+ for (j = 0; j < i; j++) {
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ next_pkt = list_next_entry(tx_pkt, link);
+ list_del(&tx_pkt->link);
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+ dma_pool_free(ipa_ctx->one_kb_no_straddle_pool, tx_pkt->bounce,
+ tx_pkt->mem.phys_base);
+ kmem_cache_free(ipa_ctx->tx_pkt_wrapper_cache, tx_pkt);
+ tx_pkt = next_pkt;
+ }
+ if (i < num_desc)
+ /* last desc failed */
+ if (fail_dma_wrap)
+ kmem_cache_free(ipa_ctx->tx_pkt_wrapper_cache, tx_pkt);
+ if (transfer.iovec_phys)
+ dma_free_coherent(NULL, size, transfer.iovec,
+ transfer.iovec_phys);
+
+ return -EFAULT;
+}
+
+/**
+ * ipa_cmd_ack - callback function which will be called by SPS driver after an
+ * immediate command is complete.
+ * @user1: pointer to the descriptor of the transfer
+ * @user2:
+ *
+ * Complete the immediate commands completion object, this will release the
+ * thread which waits on this completion object (ipa_send_cmd())
+ */
+static void ipa_cmd_ack(void *user1, void *user2)
+{
+ struct ipa_desc *desc = (struct ipa_desc *)user1;
+
+ if (!desc)
+ WARN_ON(1);
+ IPADBG("got ack for cmd=%d\n", desc->opcode);
+ complete(&desc->xfer_done);
+}
+
+/**
+ * ipa_send_cmd - send immediate commands
+ * @num_desc: number of descriptors within the descr struct
+ * @descr: descriptor structure
+ *
+ * Function will block till command gets ACK from IPA HW, caller needs
+ * to free any resources it allocated after function returns
+ */
+int ipa_send_cmd(u16 num_desc, struct ipa_desc *descr)
+{
+ struct ipa_desc *desc;
+
+ if (num_desc == 1) {
+ init_completion(&descr->xfer_done);
+
+ /* client should not set these */
+ if (descr->callback || descr->user1)
+ WARN_ON(1);
+
+ descr->callback = ipa_cmd_ack;
+ descr->user1 = descr;
+ if (ipa_send_one(&ipa_ctx->sys[IPA_A5_CMD], descr)) {
+ IPAERR("fail to send immediate command\n");
+ return -EFAULT;
+ }
+ wait_for_completion(&descr->xfer_done);
+ } else {
+ desc = &descr[num_desc - 1];
+ init_completion(&desc->xfer_done);
+
+ /* client should not set these */
+ if (desc->callback || desc->user1)
+ WARN_ON(1);
+
+ desc->callback = ipa_cmd_ack;
+ desc->user1 = desc;
+ if (ipa_send(&ipa_ctx->sys[IPA_A5_CMD], num_desc, descr)) {
+ IPAERR("fail to send multiple immediate command set\n");
+ return -EFAULT;
+ }
+ wait_for_completion(&desc->xfer_done);
+ }
+
+ return 0;
+}
+
+/**
+ * ipa_tx_notify() - Callback function which will be called by the SPS driver
+ * after a Tx operation is complete. Called in an interrupt context.
+ * @notify: SPS driver supplied notification struct
+ */
+static void ipa_tx_notify(struct sps_event_notify *notify)
+{
+ struct ipa_tx_pkt_wrapper *tx_pkt;
+
+ IPADBG("event %d notified\n", notify->event_id);
+
+ switch (notify->event_id) {
+ case SPS_EVENT_EOT:
+ tx_pkt = notify->data.transfer.user;
+ queue_work(ipa_ctx->tx_wq, &tx_pkt->work);
+ break;
+ default:
+ IPAERR("recieved unexpected event id %d\n", notify->event_id);
+ }
+}
+
+/**
+ * ipa_handle_rx_core() - The core functionality of packet reception. This
+ * function is read from multiple code paths.
+ *
+ * All the packets on the Rx data path are received on the IPA_A5_LAN_WAN_IN
+ * endpoint. The function runs as long as there are packets in the pipe.
+ * For each packet:
+ * - Disconnect the packet from the system pipe linked list
+ * - Unmap the packets skb, make it non DMAable
+ * - Free the packet from the cache
+ * - Prepare a proper skb
+ * - Call the endpoints notify function, passing the skb in the parameters
+ * - Replenish the rx cache
+ */
+void ipa_handle_rx_core(void)
+{
+ struct ipa_a5_mux_hdr *mux_hdr;
+ struct ipa_rx_pkt_wrapper *rx_pkt;
+ struct sk_buff *rx_skb;
+ struct sps_iovec iov;
+ unsigned long irq_flags;
+ u16 pull_len;
+ u16 padding;
+ int ret;
+ struct ipa_sys_context *sys = &ipa_ctx->sys[IPA_A5_LAN_WAN_IN];
+ struct ipa_ep_context *ep;
+
+ do {
+ ret = sps_get_iovec(sys->ep->ep_hdl, &iov);
+ if (ret) {
+ IPAERR("sps_get_iovec failed %d\n", ret);
+ break;
+ }
+
+ /* Break the loop when there are no more packets to receive */
+ if (iov.addr == 0)
+ break;
+
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ if (list_empty(&sys->head_desc_list))
+ WARN_ON(1);
+ rx_pkt = list_first_entry(&sys->head_desc_list,
+ struct ipa_rx_pkt_wrapper, link);
+ if (!rx_pkt)
+ WARN_ON(1);
+ rx_pkt->len = iov.size;
+ sys->len--;
+ list_del(&rx_pkt->link);
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ IPADBG("--curr_cnt=%d\n", sys->len);
+
+ rx_skb = rx_pkt->skb;
+ dma_unmap_single(NULL, rx_pkt->dma_address, IPA_RX_SKB_SIZE,
+ DMA_FROM_DEVICE);
+ kmem_cache_free(ipa_ctx->rx_pkt_wrapper_cache, rx_pkt);
+
+ /*
+ * make it look like a real skb, "data" was already set at
+ * alloc time
+ */
+ rx_skb->tail = rx_skb->data + rx_pkt->len;
+ rx_skb->len = rx_pkt->len;
+ rx_skb->truesize = rx_pkt->len + sizeof(struct sk_buff);
+
+ mux_hdr = (struct ipa_a5_mux_hdr *)rx_skb->data;
+
+ IPADBG("RX pkt len=%d IID=0x%x src=%d, flags=0x%x, meta=0x%x\n",
+ rx_skb->len, ntohs(mux_hdr->interface_id),
+ mux_hdr->src_pipe_index,
+ mux_hdr->flags, ntohl(mux_hdr->metadata));
+
+ IPA_DUMP_BUFF(rx_skb->data, 0, rx_skb->len);
+
+ if (mux_hdr->src_pipe_index >= IPA_NUM_PIPES ||
+ !ipa_ctx->ep[mux_hdr->src_pipe_index].valid ||
+ !ipa_ctx->ep[mux_hdr->src_pipe_index].notify) {
+ IPAERR("drop pipe=%d ep_valid=%d notify=%p\n",
+ mux_hdr->src_pipe_index,
+ ipa_ctx->ep[mux_hdr->src_pipe_index].valid,
+ ipa_ctx->ep[mux_hdr->src_pipe_index].notify);
+ dev_kfree_skb_any(rx_skb);
+ ipa_replenish_rx_cache();
+ continue;
+ }
+
+ ep = &ipa_ctx->ep[mux_hdr->src_pipe_index];
+ pull_len = sizeof(struct ipa_a5_mux_hdr);
+
+ /*
+ * IP packet starts on word boundary
+ * remove the MUX header and any padding and pass the frame to
+ * the client which registered a rx callback on the "src pipe"
+ */
+ padding = ep->cfg.hdr.hdr_len & 0x3;
+ if (padding)
+ pull_len += 4 - padding;
+
+ IPADBG("pulling %d bytes from skb\n", pull_len);
+ skb_pull(rx_skb, pull_len);
+ ep->notify(ep->priv, IPA_RECEIVE, (unsigned long)(rx_skb));
+ ipa_replenish_rx_cache();
+ } while (1);
+}
+
+/**
+ * ipa_rx_switch_to_intr_mode() - Operate the Rx data path in interrupt mode
+ */
+static void ipa_rx_switch_to_intr_mode(void)
+{
+ int ret;
+ struct ipa_sys_context *sys;
+
+ IPADBG("Enter");
+ if (!ipa_ctx->curr_polling_state) {
+ IPAERR("already in intr mode\n");
+ return;
+ }
+
+ sys = &ipa_ctx->sys[IPA_A5_LAN_WAN_IN];
+
+ ret = sps_get_config(sys->ep->ep_hdl, &sys->ep->connect);
+ if (ret) {
+ IPAERR("sps_get_config() failed %d\n", ret);
+ return;
+ }
+ sys->event.options = SPS_O_EOT;
+ ret = sps_register_event(sys->ep->ep_hdl, &sys->event);
+ if (ret) {
+ IPAERR("sps_register_event() failed %d\n", ret);
+ return;
+ }
+ sys->ep->connect.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_EOT;
+ ret = sps_set_config(sys->ep->ep_hdl, &sys->ep->connect);
+ if (ret) {
+ IPAERR("sps_set_config() failed %d\n", ret);
+ return;
+ }
+ ipa_handle_rx_core();
+ ipa_ctx->curr_polling_state = 0;
+}
+
+/**
+ * ipa_rx_switch_to_poll_mode() - Operate the Rx data path in polling mode
+ */
+static void ipa_rx_switch_to_poll_mode(void)
+{
+ int ret;
+ struct ipa_ep_context *ep;
+
+ IPADBG("Enter");
+ ep = ipa_ctx->sys[IPA_A5_LAN_WAN_IN].ep;
+
+ ret = sps_get_config(ep->ep_hdl, &ep->connect);
+ if (ret) {
+ IPAERR("sps_get_config() failed %d\n", ret);
+ return;
+ }
+ ep->connect.options =
+ SPS_O_AUTO_ENABLE | SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+ ret = sps_set_config(ep->ep_hdl, &ep->connect);
+ if (ret) {
+ IPAERR("sps_set_config() failed %d\n", ret);
+ return;
+ }
+ ipa_ctx->curr_polling_state = 1;
+}
+
+/**
+ * ipa_rx_notify() - Callback function which is called by the SPS driver when a
+ * a packet is received
+ * @notify: SPS driver supplied notification information
+ *
+ * Called in an interrupt context, therefore the majority of the work is
+ * deffered using a work queue.
+ *
+ * After receiving a packet, the driver goes to polling mode and keeps pulling
+ * packets until the rx buffer is empty, then it goes back to interrupt mode.
+ * This comes to prevent the CPU from handling too many interrupts when the
+ * throughput is high.
+ */
+static void ipa_rx_notify(struct sps_event_notify *notify)
+{
+ struct ipa_rx_pkt_wrapper *rx_pkt;
+
+ IPADBG("event %d notified\n", notify->event_id);
+
+ switch (notify->event_id) {
+ case SPS_EVENT_EOT:
+ if (!ipa_ctx->curr_polling_state) {
+ ipa_rx_switch_to_poll_mode();
+ rx_pkt = notify->data.transfer.user;
+ queue_work(ipa_ctx->rx_wq, &rx_pkt->work);
+ }
+ break;
+ default:
+ IPAERR("recieved unexpected event id %d\n", notify->event_id);
+ }
+}
+
+/**
+ * ipa_setup_sys_pipe() - Setup an IPA end-point in system-BAM mode and perform
+ * IPA EP configuration
+ * @sys_in: [in] input needed to setup BAM pipe and config EP
+ * @clnt_hdl: [out] client handle
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_setup_sys_pipe(struct ipa_sys_connect_params *sys_in, u32 *clnt_hdl)
+{
+ int ipa_ep_idx;
+ int sys_idx = -1;
+ int result = -EFAULT;
+ dma_addr_t dma_addr;
+
+ if (sys_in == NULL || clnt_hdl == NULL ||
+ sys_in->client >= IPA_CLIENT_MAX || sys_in->desc_fifo_sz == 0) {
+ IPAERR("bad parm.\n");
+ result = -EINVAL;
+ goto fail_bad_param;
+ }
+
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode, sys_in->client);
+ if (ipa_ep_idx == -1) {
+ IPAERR("Invalid client.\n");
+ goto fail_bad_param;
+ }
+
+ if (ipa_ctx->ep[ipa_ep_idx].valid == 1) {
+ IPAERR("EP already allocated.\n");
+ goto fail_bad_param;
+ }
+
+ memset(&ipa_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa_ep_context));
+
+ ipa_ctx->ep[ipa_ep_idx].valid = 1;
+ ipa_ctx->ep[ipa_ep_idx].client = sys_in->client;
+
+ if (ipa_cfg_ep(ipa_ep_idx, &sys_in->ipa_ep_cfg)) {
+ IPAERR("fail to configure EP.\n");
+ goto fail_sps_api;
+ }
+
+ /* Default Config */
+ ipa_ctx->ep[ipa_ep_idx].ep_hdl = sps_alloc_endpoint();
+
+ if (ipa_ctx->ep[ipa_ep_idx].ep_hdl == NULL) {
+ IPAERR("SPS EP allocation failed.\n");
+ goto fail_sps_api;
+ }
+
+ result = sps_get_config(ipa_ctx->ep[ipa_ep_idx].ep_hdl,
+ &ipa_ctx->ep[ipa_ep_idx].connect);
+ if (result) {
+ IPAERR("fail to get config.\n");
+ goto fail_mem_alloc;
+ }
+
+ /* Specific Config */
+ if (IPA_CLIENT_IS_CONS(sys_in->client)) {
+ ipa_ctx->ep[ipa_ep_idx].connect.mode = SPS_MODE_SRC;
+ ipa_ctx->ep[ipa_ep_idx].connect.destination =
+ SPS_DEV_HANDLE_MEM;
+ ipa_ctx->ep[ipa_ep_idx].connect.source = ipa_ctx->bam_handle;
+ ipa_ctx->ep[ipa_ep_idx].connect.dest_pipe_index =
+ ipa_ctx->a5_pipe_index++;
+ ipa_ctx->ep[ipa_ep_idx].connect.src_pipe_index = ipa_ep_idx;
+ ipa_ctx->ep[ipa_ep_idx].connect.options =
+ SPS_O_AUTO_ENABLE | SPS_O_EOT | SPS_O_ACK_TRANSFERS;
+ if (ipa_ctx->polling_mode)
+ ipa_ctx->ep[ipa_ep_idx].connect.options |= SPS_O_POLL;
+ } else {
+ ipa_ctx->ep[ipa_ep_idx].connect.mode = SPS_MODE_DEST;
+ ipa_ctx->ep[ipa_ep_idx].connect.source = SPS_DEV_HANDLE_MEM;
+ ipa_ctx->ep[ipa_ep_idx].connect.destination =
+ ipa_ctx->bam_handle;
+ ipa_ctx->ep[ipa_ep_idx].connect.src_pipe_index =
+ ipa_ctx->a5_pipe_index++;
+ ipa_ctx->ep[ipa_ep_idx].connect.dest_pipe_index = ipa_ep_idx;
+ ipa_ctx->ep[ipa_ep_idx].connect.options =
+ SPS_O_AUTO_ENABLE | SPS_O_EOT;
+ if (ipa_ctx->polling_mode)
+ ipa_ctx->ep[ipa_ep_idx].connect.options |=
+ SPS_O_ACK_TRANSFERS | SPS_O_POLL;
+ }
+
+ ipa_ctx->ep[ipa_ep_idx].connect.desc.size = sys_in->desc_fifo_sz;
+ ipa_ctx->ep[ipa_ep_idx].connect.desc.base =
+ dma_alloc_coherent(NULL, ipa_ctx->ep[ipa_ep_idx].connect.desc.size,
+ &dma_addr, 0);
+ ipa_ctx->ep[ipa_ep_idx].connect.desc.phys_base = dma_addr;
+ if (ipa_ctx->ep[ipa_ep_idx].connect.desc.base == NULL) {
+ IPAERR("fail to get DMA desc memory.\n");
+ goto fail_mem_alloc;
+ }
+
+ ipa_ctx->ep[ipa_ep_idx].connect.event_thresh = IPA_EVENT_THRESHOLD;
+
+ result = sps_connect(ipa_ctx->ep[ipa_ep_idx].ep_hdl,
+ &ipa_ctx->ep[ipa_ep_idx].connect);
+ if (result) {
+ IPAERR("sps_connect fails.\n");
+ goto fail_sps_connect;
+ }
+
+ switch (ipa_ep_idx) {
+ case 1:
+ /* fall through */
+ case 2:
+ /* fall through */
+ case 3:
+ sys_idx = ipa_ep_idx;
+ break;
+ case 15:
+ sys_idx = IPA_A5_WLAN_AMPDU_OUT;
+ break;
+ default:
+ IPAERR("Invalid EP index.\n");
+ result = -EFAULT;
+ goto fail_register_event;
+ }
+
+ if (!ipa_ctx->polling_mode) {
+ if (IPA_CLIENT_IS_CONS(sys_in->client)) {
+ ipa_ctx->sys[sys_idx].event.options = SPS_O_EOT;
+ ipa_ctx->sys[sys_idx].event.mode = SPS_TRIGGER_CALLBACK;
+ ipa_ctx->sys[sys_idx].event.xfer_done = NULL;
+ ipa_ctx->sys[sys_idx].event.callback = ipa_rx_notify;
+ ipa_ctx->sys[sys_idx].event.user =
+ &ipa_ctx->sys[sys_idx];
+ result =
+ sps_register_event(ipa_ctx->ep[ipa_ep_idx].ep_hdl,
+ &ipa_ctx->sys[sys_idx].event);
+ if (result < 0) {
+ IPAERR("rx register event error %d\n", result);
+ goto fail_register_event;
+ }
+ } else {
+ ipa_ctx->sys[sys_idx].event.options = SPS_O_EOT;
+ ipa_ctx->sys[sys_idx].event.mode = SPS_TRIGGER_CALLBACK;
+ ipa_ctx->sys[sys_idx].event.xfer_done = NULL;
+ ipa_ctx->sys[sys_idx].event.callback = ipa_tx_notify;
+ ipa_ctx->sys[sys_idx].event.user =
+ &ipa_ctx->sys[sys_idx];
+ result =
+ sps_register_event(ipa_ctx->ep[ipa_ep_idx].ep_hdl,
+ &ipa_ctx->sys[sys_idx].event);
+ if (result < 0) {
+ IPAERR("tx register event error %d\n", result);
+ goto fail_register_event;
+ }
+ }
+ }
+
+ return 0;
+
+fail_register_event:
+ sps_disconnect(ipa_ctx->ep[ipa_ep_idx].ep_hdl);
+fail_sps_connect:
+ dma_free_coherent(NULL, ipa_ctx->ep[ipa_ep_idx].connect.desc.size,
+ ipa_ctx->ep[ipa_ep_idx].connect.desc.base,
+ ipa_ctx->ep[ipa_ep_idx].connect.desc.phys_base);
+fail_mem_alloc:
+ sps_free_endpoint(ipa_ctx->ep[ipa_ep_idx].ep_hdl);
+fail_sps_api:
+ memset(&ipa_ctx->ep[ipa_ep_idx], 0, sizeof(struct ipa_ep_context));
+fail_bad_param:
+ return result;
+}
+EXPORT_SYMBOL(ipa_setup_sys_pipe);
+
+/**
+ * ipa_teardown_sys_pipe() - Teardown the system-BAM pipe and cleanup IPA EP
+ * @clnt_hdl: [in] the handle obtained from ipa_setup_sys_pipe
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_teardown_sys_pipe(u32 clnt_hdl)
+{
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ sps_disconnect(ipa_ctx->ep[clnt_hdl].ep_hdl);
+ dma_free_coherent(NULL, ipa_ctx->ep[clnt_hdl].connect.desc.size,
+ ipa_ctx->ep[clnt_hdl].connect.desc.base,
+ ipa_ctx->ep[clnt_hdl].connect.desc.phys_base);
+ sps_free_endpoint(ipa_ctx->ep[clnt_hdl].ep_hdl);
+ memset(&ipa_ctx->ep[clnt_hdl], 0, sizeof(struct ipa_ep_context));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_teardown_sys_pipe);
+
+/**
+ * ipa_tx_comp() - Callback function which will call the user supplied callback
+ * function to release the skb, or release it on its own if no callback function
+ * was supplied.
+ * @user1
+ * @user2
+ */
+static void ipa_tx_comp(void *user1, void *user2)
+{
+ struct sk_buff *skb = (struct sk_buff *)user1;
+ u32 ep_idx = (u32)user2;
+
+ IPADBG("skb=%p ep=%d\n", skb, ep_idx);
+
+ if (ipa_ctx->ep[ep_idx].notify)
+ ipa_ctx->ep[ep_idx].notify(ipa_ctx->ep[ep_idx].priv,
+ IPA_WRITE_DONE, (unsigned long)skb);
+ else
+ dev_kfree_skb_any(skb);
+}
+
+/**
+ * ipa_tx_dp() - Data-path tx handler
+ * @dst: [in] which IPA destination to route tx packets to
+ * @skb: [in] the packet to send
+ * @metadata: [in] TX packet meta-data
+ *
+ * Data-path tx handler, this is used for both SW data-path which by-passes most
+ * IPA HW blocks AND the regular HW data-path for WLAN AMPDU traffic only. If
+ * dst is a "valid" CONS type, then SW data-path is used. If dst is the
+ * WLAN_AMPDU PROD type, then HW data-path for WLAN AMPDU is used. Anything else
+ * is an error. For errors, client needs to free the skb as needed. For success,
+ * IPA driver will later invoke client calback if one was supplied. That
+ * callback should free the skb. If no callback supplied, IPA driver will free
+ * the skb internally
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb,
+ struct ipa_tx_meta *meta)
+{
+ struct ipa_desc desc[2];
+ int ipa_ep_idx;
+ struct ipa_ip_packet_init *cmd;
+
+ memset(&desc, 0, 2 * sizeof(struct ipa_desc));
+
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode, dst);
+ if (ipa_ep_idx == -1) {
+ IPAERR("dest EP does not exist.\n");
+ goto fail_gen;
+ }
+
+ if (ipa_ctx->ep[ipa_ep_idx].valid == 0) {
+ IPAERR("dest EP not valid.\n");
+ goto fail_gen;
+ }
+
+ if (IPA_CLIENT_IS_CONS(dst)) {
+ cmd = kzalloc(sizeof(struct ipa_ip_packet_init), GFP_KERNEL);
+ if (!cmd) {
+ IPAERR("failed to alloc immediate command object\n");
+ goto fail_mem_alloc;
+ }
+
+ cmd->destination_pipe_index = ipa_ep_idx;
+ if (meta && meta->mbim_stream_id_valid)
+ cmd->metadata = meta->mbim_stream_id;
+ desc[0].opcode = IPA_IP_PACKET_INIT;
+ desc[0].pyld = cmd;
+ desc[0].len = sizeof(struct ipa_ip_packet_init);
+ desc[0].type = IPA_IMM_CMD_DESC;
+ desc[1].pyld = skb->data;
+ desc[1].len = skb->len;
+ desc[1].type = IPA_DATA_DESC_SKB;
+ desc[1].callback = ipa_tx_comp;
+ desc[1].user1 = skb;
+ desc[1].user2 = (void *)ipa_ep_idx;
+
+ if (ipa_send(&ipa_ctx->sys[IPA_A5_LAN_WAN_OUT], 2, desc)) {
+ IPAERR("fail to send immediate command\n");
+ goto fail_send;
+ }
+ } else if (dst == IPA_CLIENT_A5_WLAN_AMPDU_PROD) {
+ desc[0].pyld = skb->data;
+ desc[0].len = skb->len;
+ desc[0].type = IPA_DATA_DESC_SKB;
+ desc[0].callback = ipa_tx_comp;
+ desc[0].user1 = skb;
+ desc[0].user2 = (void *)ipa_ep_idx;
+
+ if (ipa_send_one(&ipa_ctx->sys[IPA_A5_WLAN_AMPDU_OUT],
+ &desc[0])) {
+ IPAERR("fail to send skb\n");
+ goto fail_gen;
+ }
+ } else {
+ IPAERR("%d PROD is not supported.\n", dst);
+ goto fail_gen;
+ }
+
+ return 0;
+
+fail_send:
+ kfree(cmd);
+fail_mem_alloc:
+fail_gen:
+ return -EFAULT;
+}
+EXPORT_SYMBOL(ipa_tx_dp);
+
+/**
+ * ipa_handle_rx() - handle packet reception. This function is executed in the
+ * context of a work queue.
+ * @work: work struct needed by the work queue
+ *
+ * ipa_handle_rx_core() is run in polling mode. After all packets has been
+ * received, the driver switches back to interrupt mode.
+ */
+void ipa_handle_rx(struct work_struct *work)
+{
+ ipa_handle_rx_core();
+ ipa_rx_switch_to_intr_mode();
+}
+
+/**
+ * ipa_replenish_rx_cache() - Replenish the Rx packets cache.
+ *
+ * The function allocates buffers in the rx_pkt_wrapper_cache cache until there
+ * are IPA_RX_POOL_CEIL buffers in the cache.
+ * - Allocate a buffer in the cache
+ * - Initialized the packets link
+ * - Initialize the packets work struct
+ * - Allocate the packets socket buffer (skb)
+ * - Fill the packets skb with data
+ * - Make the packet DMAable
+ * - Add the packet to the system pipe linked list
+ * - Initiate a SPS transfer so that SPS driver will use this packet later.
+ */
+void ipa_replenish_rx_cache(void)
+{
+ void *ptr;
+ struct ipa_rx_pkt_wrapper *rx_pkt;
+ int ret;
+ int rx_len_cached;
+ unsigned long irq_flags;
+ struct ipa_sys_context *sys = &ipa_ctx->sys[IPA_A5_LAN_WAN_IN];
+
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ rx_len_cached = sys->len;
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ /* true RX data path is not currently exercised so drop the ceil */
+ while (rx_len_cached < (IPA_RX_POOL_CEIL >> 3)) {
+ rx_pkt = kmem_cache_zalloc(ipa_ctx->rx_pkt_wrapper_cache,
+ GFP_KERNEL);
+ if (!rx_pkt) {
+ IPAERR("failed to alloc rx wrapper\n");
+ return;
+ }
+
+ INIT_LIST_HEAD(&rx_pkt->link);
+ INIT_WORK(&rx_pkt->work, ipa_handle_rx);
+
+ rx_pkt->skb = __dev_alloc_skb(IPA_RX_SKB_SIZE, GFP_KERNEL);
+ if (rx_pkt->skb == NULL) {
+ IPAERR("failed to alloc skb\n");
+ goto fail_skb_alloc;
+ }
+ ptr = skb_put(rx_pkt->skb, IPA_RX_SKB_SIZE);
+ rx_pkt->dma_address = dma_map_single(NULL, ptr,
+ IPA_RX_SKB_SIZE,
+ DMA_FROM_DEVICE);
+ if (rx_pkt->dma_address == 0 || rx_pkt->dma_address == ~0) {
+ IPAERR("dma_map_single failure %p for %p\n",
+ (void *)rx_pkt->dma_address, ptr);
+ goto fail_dma_mapping;
+ }
+
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_add_tail(&rx_pkt->link, &sys->head_desc_list);
+ rx_len_cached = ++sys->len;
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+
+ ret = sps_transfer_one(sys->ep->ep_hdl, rx_pkt->dma_address,
+ IPA_RX_SKB_SIZE, rx_pkt,
+ SPS_IOVEC_FLAG_INT);
+
+ if (ret) {
+ IPAERR("sps_transfer_one failed %d\n", ret);
+ goto fail_sps_transfer;
+ }
+
+ IPADBG("++curr_cnt=%d\n", sys->len);
+ }
+
+ return;
+
+fail_sps_transfer:
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_del(&rx_pkt->link);
+ --sys->len;
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+ dma_unmap_single(NULL, rx_pkt->dma_address, IPA_RX_SKB_SIZE,
+ DMA_FROM_DEVICE);
+fail_dma_mapping:
+ dev_kfree_skb_any(rx_pkt->skb);
+fail_skb_alloc:
+ kmem_cache_free(ipa_ctx->rx_pkt_wrapper_cache, rx_pkt);
+
+ return;
+}
+
+/**
+ * ipa_cleanup_rx() - release RX queue resources
+ *
+ */
+void ipa_cleanup_rx(void)
+{
+ struct ipa_rx_pkt_wrapper *rx_pkt;
+ struct ipa_rx_pkt_wrapper *r;
+ unsigned long irq_flags;
+ struct ipa_sys_context *sys = &ipa_ctx->sys[IPA_A5_LAN_WAN_IN];
+
+ spin_lock_irqsave(&sys->spinlock, irq_flags);
+ list_for_each_entry_safe(rx_pkt, r,
+ &sys->head_desc_list, link) {
+ list_del(&rx_pkt->link);
+ dma_unmap_single(NULL, rx_pkt->dma_address, IPA_RX_SKB_SIZE,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb_any(rx_pkt->skb);
+ kmem_cache_free(ipa_ctx->rx_pkt_wrapper_cache, rx_pkt);
+ }
+ spin_unlock_irqrestore(&sys->spinlock, irq_flags);
+}
+
diff --git a/drivers/platform/msm/ipa/ipa_flt.c b/drivers/platform/msm/ipa/ipa_flt.c
new file mode 100644
index 0000000..81f3a80
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_flt.c
@@ -0,0 +1,811 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ipa_i.h"
+
+#define IPA_FLT_TABLE_WORD_SIZE (4)
+#define IPA_FLT_ENTRY_MEMORY_ALLIGNMENT (0x3)
+#define IPA_FLT_BIT_MASK (0x1)
+#define IPA_FLT_TABLE_INDEX_NOT_FOUND (-1)
+#define IPA_FLT_STATUS_OF_ADD_FAILED (-1)
+#define IPA_FLT_STATUS_OF_DEL_FAILED (-1)
+
+/**
+ * ipa_generate_flt_hw_rule() - generates the filtering hardware rule
+ * @ip: the ip address family type
+ * @entry: routing entry
+ * @buf: output buffer, buf == NULL means
+ * caller wants to know the size of the rule as seen
+ * by HW so they did not pass a valid buffer, we will use a
+ * scratch buffer instead.
+ * With this scheme we are going to
+ * generate the rule twice, once to know size using scratch
+ * buffer and second to write the rule to the actual caller
+ * supplied buffer which is of required size
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * caller needs to hold any needed locks to ensure integrity
+ *
+ */
+static int ipa_generate_flt_hw_rule(enum ipa_ip_type ip,
+ struct ipa_flt_entry *entry, u8 *buf)
+{
+ struct ipa_flt_rule_hw_hdr *hdr;
+ const struct ipa_flt_rule *rule =
+ (const struct ipa_flt_rule *)&entry->rule;
+ u16 en_rule = 0;
+ u8 tmp[IPA_RT_FLT_HW_RULE_BUF_SIZE];
+ u8 *start;
+
+ memset(tmp, 0, IPA_RT_FLT_HW_RULE_BUF_SIZE);
+ if (buf == NULL)
+ buf = tmp;
+
+ start = buf;
+ hdr = (struct ipa_flt_rule_hw_hdr *)buf;
+ hdr->u.hdr.action = entry->rule.action;
+ hdr->u.hdr.rt_tbl_idx = entry->rt_tbl->idx;
+ hdr->u.hdr.rsvd = 0;
+ buf += sizeof(struct ipa_flt_rule_hw_hdr);
+
+ if (ipa_generate_hw_rule(ip, &rule->attrib, &buf, &en_rule)) {
+ IPAERR("fail to generate hw rule\n");
+ return -EPERM;
+ }
+
+ IPADBG("en_rule %x\n", en_rule);
+
+ hdr->u.hdr.en_rule = en_rule;
+ ipa_write_32(hdr->u.word, (u8 *)hdr);
+
+ if (entry->hw_len == 0) {
+ entry->hw_len = buf - start;
+ } else if (entry->hw_len != (buf - start)) {
+ IPAERR("hw_len differs b/w passes passed=%x calc=%x\n",
+ entry->hw_len, (buf - start));
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/**
+ * ipa_get_flt_hw_tbl_size() - returns the size of HW filtering table
+ * @ip: the ip address family type
+ * @hdr_sz: header size
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * caller needs to hold any needed locks to ensure integrity
+ *
+ */
+static int ipa_get_flt_hw_tbl_size(enum ipa_ip_type ip, u32 *hdr_sz)
+{
+ struct ipa_flt_tbl *tbl;
+ struct ipa_flt_entry *entry;
+ u32 total_sz = 0;
+ u32 rule_set_sz;
+ int i;
+
+ *hdr_sz = 0;
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+ rule_set_sz = 0;
+ list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
+ if (ipa_generate_flt_hw_rule(ip, entry, NULL)) {
+ IPAERR("failed to find HW FLT rule size\n");
+ return -EPERM;
+ }
+ IPADBG("glob ip %d len %d\n", ip, entry->hw_len);
+ rule_set_sz += entry->hw_len;
+ }
+
+ if (rule_set_sz) {
+ tbl->sz = rule_set_sz + IPA_FLT_TABLE_WORD_SIZE;
+ /* this rule-set uses a word in header block */
+ *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
+ if (!tbl->in_sys) {
+ /* add the terminator */
+ total_sz += (rule_set_sz + IPA_FLT_TABLE_WORD_SIZE);
+ total_sz = (total_sz +
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) &
+ ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
+ }
+ }
+
+ for (i = 0; i < IPA_NUM_PIPES; i++) {
+ tbl = &ipa_ctx->flt_tbl[i][ip];
+ rule_set_sz = 0;
+ list_for_each_entry(entry, &tbl->head_flt_rule_list, link) {
+ if (ipa_generate_flt_hw_rule(ip, entry, NULL)) {
+ IPAERR("failed to find HW FLT rule size\n");
+ return -EPERM;
+ }
+ IPADBG("pipe %d len %d\n", i, entry->hw_len);
+ rule_set_sz += entry->hw_len;
+ }
+
+ if (rule_set_sz) {
+ tbl->sz = rule_set_sz + IPA_FLT_TABLE_WORD_SIZE;
+ /* this rule-set uses a word in header block */
+ *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
+ if (!tbl->in_sys) {
+ /* add the terminator */
+ total_sz += (rule_set_sz +
+ IPA_FLT_TABLE_WORD_SIZE);
+ total_sz = (total_sz +
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) &
+ ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
+ }
+ }
+ }
+
+ *hdr_sz += IPA_FLT_TABLE_WORD_SIZE;
+ total_sz += *hdr_sz;
+ IPADBG("FLT HW TBL SZ %d HDR SZ %d IP %d\n", total_sz, *hdr_sz, ip);
+
+ return total_sz;
+}
+
+/**
+ * ipa_generate_flt_hw_tbl() - generates the filtering hardware table
+ * @ip: [in] the ip address family type
+ * @mem: [out] buffer to put the filtering table
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_generate_flt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem)
+{
+ struct ipa_flt_tbl *tbl;
+ struct ipa_flt_entry *entry;
+ u32 hdr_top = 0;
+ int i;
+ u32 hdr_sz;
+ u32 offset;
+ u8 *hdr;
+ u8 *body;
+ u8 *base;
+ struct ipa_mem_buffer flt_tbl_mem;
+ u8 *ftbl_membody;
+
+ mem->size = ipa_get_flt_hw_tbl_size(ip, &hdr_sz);
+ mem->size = IPA_HW_TABLE_ALIGNMENT(mem->size);
+
+ if (mem->size == 0) {
+ IPAERR("flt tbl empty ip=%d\n", ip);
+ goto error;
+ }
+ mem->base = dma_alloc_coherent(NULL, mem->size, &mem->phys_base,
+ GFP_KERNEL);
+ if (!mem->base) {
+ IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
+ goto error;
+ }
+
+ memset(mem->base, 0, mem->size);
+
+ /* build the flt tbl in the DMA buffer to submit to IPA HW */
+ base = hdr = (u8 *)mem->base;
+ body = base + hdr_sz;
+
+ /* write a dummy header to move cursor */
+ hdr = ipa_write_32(hdr_top, hdr);
+
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+
+ if (!list_empty(&tbl->head_flt_rule_list)) {
+ hdr_top |= IPA_FLT_BIT_MASK;
+ if (!tbl->in_sys) {
+ offset = body - base;
+ if (offset & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) {
+ IPAERR("offset is not word multiple %d\n",
+ offset);
+ goto proc_err;
+ }
+
+ offset &= ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
+ /* rule is at an offset from base */
+ offset |= IPA_FLT_BIT_MASK;
+ hdr = ipa_write_32(offset, hdr);
+
+ /* generate the rule-set */
+ list_for_each_entry(entry, &tbl->head_flt_rule_list,
+ link) {
+ if (ipa_generate_flt_hw_rule(ip, entry, body)) {
+ IPAERR("failed to gen HW FLT rule\n");
+ goto proc_err;
+ }
+ body += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ body = ipa_write_32(0, body);
+ if ((u32)body & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT)
+ /* advance body to next word boundary */
+ body = body + (IPA_FLT_TABLE_WORD_SIZE -
+ ((u32)body &
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT));
+ } else {
+ WARN_ON(tbl->sz == 0);
+ /* allocate memory for the flt tbl */
+ flt_tbl_mem.size = tbl->sz;
+ flt_tbl_mem.base =
+ dma_alloc_coherent(NULL, flt_tbl_mem.size,
+ &flt_tbl_mem.phys_base, GFP_KERNEL);
+ if (!flt_tbl_mem.base) {
+ IPAERR("fail to alloc DMA buff of size %d\n",
+ flt_tbl_mem.size);
+ WARN_ON(1);
+ goto proc_err;
+ }
+
+ WARN_ON(flt_tbl_mem.phys_base &
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT);
+ ftbl_membody = flt_tbl_mem.base;
+ memset(flt_tbl_mem.base, 0, flt_tbl_mem.size);
+ hdr = ipa_write_32(flt_tbl_mem.phys_base, hdr);
+
+ /* generate the rule-set */
+ list_for_each_entry(entry, &tbl->head_flt_rule_list,
+ link) {
+ if (ipa_generate_flt_hw_rule(ip, entry,
+ ftbl_membody)) {
+ IPAERR("failed to gen HW FLT rule\n");
+ WARN_ON(1);
+ }
+ ftbl_membody += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ ftbl_membody = ipa_write_32(0, ftbl_membody);
+ if (tbl->curr_mem.phys_base) {
+ WARN_ON(tbl->prev_mem.phys_base);
+ tbl->prev_mem = tbl->curr_mem;
+ }
+ tbl->curr_mem = flt_tbl_mem;
+ }
+ }
+
+ for (i = 0; i < IPA_NUM_PIPES; i++) {
+ tbl = &ipa_ctx->flt_tbl[i][ip];
+ if (!list_empty(&tbl->head_flt_rule_list)) {
+ /* pipe "i" is at bit "i+1" */
+ hdr_top |= (1 << (i + 1));
+ if (!tbl->in_sys) {
+ offset = body - base;
+ if (offset & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT) {
+ IPAERR("ofst is not word multiple %d\n",
+ offset);
+ goto proc_err;
+ }
+ offset &= ~IPA_FLT_ENTRY_MEMORY_ALLIGNMENT;
+ /* rule is at an offset from base */
+ offset |= IPA_FLT_BIT_MASK;
+ hdr = ipa_write_32(offset, hdr);
+
+ /* generate the rule-set */
+ list_for_each_entry(entry,
+ &tbl->head_flt_rule_list,
+ link) {
+ if (ipa_generate_flt_hw_rule(ip, entry,
+ body)) {
+ IPAERR("fail gen FLT rule\n");
+ goto proc_err;
+ }
+ body += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ body = ipa_write_32(0, body);
+ if ((u32)body & IPA_FLT_ENTRY_MEMORY_ALLIGNMENT)
+ /* advance body to next word boundary */
+ body = body + (IPA_FLT_TABLE_WORD_SIZE -
+ ((u32)body &
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT));
+ } else {
+ WARN_ON(tbl->sz == 0);
+ /* allocate memory for the flt tbl */
+ flt_tbl_mem.size = tbl->sz;
+ flt_tbl_mem.base =
+ dma_alloc_coherent(NULL, flt_tbl_mem.size,
+ &flt_tbl_mem.phys_base,
+ GFP_KERNEL);
+ if (!flt_tbl_mem.base) {
+ IPAERR("fail alloc DMA buff size %d\n",
+ flt_tbl_mem.size);
+ WARN_ON(1);
+ goto proc_err;
+ }
+
+ WARN_ON(flt_tbl_mem.phys_base &
+ IPA_FLT_ENTRY_MEMORY_ALLIGNMENT);
+
+ ftbl_membody = flt_tbl_mem.base;
+ memset(flt_tbl_mem.base, 0, flt_tbl_mem.size);
+ hdr = ipa_write_32(flt_tbl_mem.phys_base, hdr);
+
+ /* generate the rule-set */
+ list_for_each_entry(entry,
+ &tbl->head_flt_rule_list,
+ link) {
+ if (ipa_generate_flt_hw_rule(ip, entry,
+ ftbl_membody)) {
+ IPAERR("fail gen FLT rule\n");
+ WARN_ON(1);
+ }
+ ftbl_membody += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ ftbl_membody =
+ ipa_write_32(0, ftbl_membody);
+ if (tbl->curr_mem.phys_base) {
+ WARN_ON(tbl->prev_mem.phys_base);
+ tbl->prev_mem = tbl->curr_mem;
+ }
+ tbl->curr_mem = flt_tbl_mem;
+ }
+ }
+ }
+
+ /* now write the hdr_top */
+ ipa_write_32(hdr_top, base);
+
+ return 0;
+proc_err:
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+error:
+
+ return -EPERM;
+}
+
+static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip)
+{
+ struct ipa_flt_tbl *tbl;
+ int i;
+
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+ if (tbl->prev_mem.phys_base) {
+ IPADBG("reaping glob flt tbl (prev) ip=%d\n", ip);
+ dma_free_coherent(NULL, tbl->prev_mem.size, tbl->prev_mem.base,
+ tbl->prev_mem.phys_base);
+ memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem));
+ }
+
+ if (list_empty(&tbl->head_flt_rule_list)) {
+ if (tbl->curr_mem.phys_base) {
+ IPADBG("reaping glob flt tbl (curr) ip=%d\n", ip);
+ dma_free_coherent(NULL, tbl->curr_mem.size,
+ tbl->curr_mem.base,
+ tbl->curr_mem.phys_base);
+ memset(&tbl->curr_mem, 0, sizeof(tbl->curr_mem));
+ }
+ }
+
+ for (i = 0; i < IPA_NUM_PIPES; i++) {
+ tbl = &ipa_ctx->flt_tbl[i][ip];
+ if (tbl->prev_mem.phys_base) {
+ IPADBG("reaping flt tbl (prev) pipe=%d ip=%d\n", i, ip);
+ dma_free_coherent(NULL, tbl->prev_mem.size,
+ tbl->prev_mem.base,
+ tbl->prev_mem.phys_base);
+ memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem));
+ }
+
+ if (list_empty(&tbl->head_flt_rule_list)) {
+ if (tbl->curr_mem.phys_base) {
+ IPADBG("reaping flt tbl (curr) pipe=%d ip=%d\n",
+ i, ip);
+ dma_free_coherent(NULL, tbl->curr_mem.size,
+ tbl->curr_mem.base,
+ tbl->curr_mem.phys_base);
+ memset(&tbl->curr_mem, 0,
+ sizeof(tbl->curr_mem));
+ }
+ }
+ }
+}
+
+static int __ipa_commit_flt(enum ipa_ip_type ip)
+{
+ struct ipa_desc desc = { 0 };
+ struct ipa_mem_buffer *mem;
+ void *cmd;
+ struct ipa_ip_v4_filter_init *v4;
+ struct ipa_ip_v6_filter_init *v6;
+ u16 avail;
+ u16 size;
+
+ mem = kmalloc(sizeof(struct ipa_mem_buffer), GFP_KERNEL);
+ if (!mem) {
+ IPAERR("failed to alloc memory object\n");
+ goto fail_alloc_mem;
+ }
+
+ if (ip == IPA_IP_v4) {
+ avail = IPA_RAM_V4_FLT_SIZE;
+ size = sizeof(struct ipa_ip_v4_filter_init);
+ } else {
+ avail = IPA_RAM_V6_FLT_SIZE;
+ size = sizeof(struct ipa_ip_v6_filter_init);
+ }
+ cmd = kmalloc(size, GFP_KERNEL);
+ if (!cmd) {
+ IPAERR("failed to alloc immediate command object\n");
+ goto fail_alloc_cmd;
+ }
+
+ if (ipa_generate_flt_hw_tbl(ip, mem)) {
+ IPAERR("fail to generate FLT HW TBL ip %d\n", ip);
+ goto fail_hw_tbl_gen;
+ }
+
+ if (mem->size > avail) {
+ IPAERR("tbl too big, needed %d avail %d\n", mem->size, avail);
+ goto fail_hw_tbl_gen;
+ }
+
+ if (ip == IPA_IP_v4) {
+ v4 = (struct ipa_ip_v4_filter_init *)cmd;
+ desc.opcode = IPA_IP_V4_FILTER_INIT;
+ v4->ipv4_rules_addr = mem->phys_base;
+ v4->size_ipv4_rules = mem->size;
+ v4->ipv4_addr = IPA_RAM_V4_FLT_OFST;
+ } else {
+ v6 = (struct ipa_ip_v6_filter_init *)cmd;
+ desc.opcode = IPA_IP_V6_FILTER_INIT;
+ v6->ipv6_rules_addr = mem->phys_base;
+ v6->size_ipv6_rules = mem->size;
+ v6->ipv6_addr = IPA_RAM_V6_FLT_OFST;
+ }
+
+ desc.pyld = cmd;
+ desc.len = size;
+ desc.type = IPA_IMM_CMD_DESC;
+ IPA_DUMP_BUFF(mem->base, mem->phys_base, mem->size);
+
+ if (ipa_send_cmd(1, &desc)) {
+ IPAERR("fail to send immediate command\n");
+ goto fail_send_cmd;
+ }
+
+ __ipa_reap_sys_flt_tbls(ip);
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+ kfree(cmd);
+ kfree(mem);
+
+ return 0;
+
+fail_send_cmd:
+ if (mem->phys_base)
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+fail_hw_tbl_gen:
+ kfree(cmd);
+fail_alloc_cmd:
+ kfree(mem);
+fail_alloc_mem:
+
+ return -EPERM;
+}
+
+static int __ipa_add_flt_rule(struct ipa_flt_tbl *tbl, enum ipa_ip_type ip,
+ const struct ipa_flt_rule *rule, u8 add_rear,
+ u32 *rule_hdl)
+{
+ struct ipa_flt_entry *entry;
+ struct ipa_tree_node *node;
+
+ if (!rule->rt_tbl_hdl) {
+ IPAERR("flt rule does not point to valid RT tbl\n");
+ goto error;
+ }
+
+ if (ipa_search(&ipa_ctx->rt_tbl_hdl_tree, rule->rt_tbl_hdl) == NULL) {
+ IPAERR("RT tbl not found\n");
+ goto error;
+ }
+
+ if (((struct ipa_rt_tbl *)rule->rt_tbl_hdl)->cookie != IPA_COOKIE) {
+ IPAERR("flt rule cookie is invalid\n");
+ goto error;
+ }
+
+ node = kmem_cache_zalloc(ipa_ctx->tree_node_cache, GFP_KERNEL);
+ if (!node) {
+ IPAERR("failed to alloc tree node object\n");
+ goto error;
+ }
+
+ entry = kmem_cache_zalloc(ipa_ctx->flt_rule_cache, GFP_KERNEL);
+ if (!entry) {
+ IPAERR("failed to alloc FLT rule object\n");
+ goto mem_alloc_fail;
+ }
+ INIT_LIST_HEAD(&entry->link);
+ entry->rule = *rule;
+ entry->cookie = IPA_COOKIE;
+ entry->rt_tbl = (struct ipa_rt_tbl *)rule->rt_tbl_hdl;
+ entry->tbl = tbl;
+ if (add_rear)
+ list_add_tail(&entry->link, &tbl->head_flt_rule_list);
+ else
+ list_add(&entry->link, &tbl->head_flt_rule_list);
+ tbl->rule_cnt++;
+ entry->rt_tbl->ref_cnt++;
+ *rule_hdl = (u32)entry;
+ IPADBG("add flt rule rule_cnt=%d\n", tbl->rule_cnt);
+
+ node->hdl = *rule_hdl;
+ if (ipa_insert(&ipa_ctx->flt_rule_hdl_tree, node)) {
+ IPAERR("failed to add to tree\n");
+ WARN_ON(1);
+ }
+
+ return 0;
+
+mem_alloc_fail:
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+error:
+
+ return -EPERM;
+}
+
+static int __ipa_del_flt_rule(u32 rule_hdl)
+{
+ struct ipa_flt_entry *entry = (struct ipa_flt_entry *)rule_hdl;
+ struct ipa_tree_node *node;
+
+ if (entry == NULL || (entry->cookie != IPA_COOKIE)) {
+ IPAERR("bad params\n");
+
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->flt_rule_hdl_tree, rule_hdl);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+
+ return -EPERM;
+ }
+ list_del(&entry->link);
+ entry->tbl->rule_cnt--;
+ entry->rt_tbl->ref_cnt--;
+ IPADBG("del flt rule rule_cnt=%d\n", entry->tbl->rule_cnt);
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+
+ return 0;
+}
+
+static int __ipa_add_global_flt_rule(enum ipa_ip_type ip,
+ const struct ipa_flt_rule *rule, u8 add_rear, u32 *rule_hdl)
+{
+ struct ipa_flt_tbl *tbl;
+
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+ IPADBG("add global flt rule ip=%d\n", ip);
+
+ return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl);
+}
+
+static int __ipa_add_ep_flt_rule(enum ipa_ip_type ip, enum ipa_client_type ep,
+ const struct ipa_flt_rule *rule, u8 add_rear,
+ u32 *rule_hdl)
+{
+ struct ipa_flt_tbl *tbl;
+ int ipa_ep_idx;
+
+ if (ip >= IPA_IP_MAX || rule == NULL || rule_hdl == NULL ||
+ ep >= IPA_CLIENT_MAX) {
+ IPAERR("bad parms\n");
+
+ return -EINVAL;
+ }
+ ipa_ep_idx = ipa_get_ep_mapping(ipa_ctx->mode, ep);
+ if (ipa_ep_idx == IPA_FLT_TABLE_INDEX_NOT_FOUND ||
+ ipa_ctx->ep[ipa_ep_idx].valid == 0) {
+ IPAERR("bad parms\n");
+
+ return -EINVAL;
+ }
+ tbl = &ipa_ctx->flt_tbl[ipa_ep_idx][ip];
+ IPADBG("add ep flt rule ip=%d ep=%d\n", ip, ep);
+
+ return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl);
+}
+
+/**
+ * ipa_add_flt_rule() - Add the specified filtering rules to SW and optionally
+ * commit to IPA HW
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_add_flt_rule(struct ipa_ioc_add_flt_rule *rules)
+{
+ int i;
+ int result;
+
+ if (rules == NULL || rules->num_rules == 0 ||
+ rules->ip >= IPA_IP_MAX) {
+ IPAERR("bad parm\n");
+
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < rules->num_rules; i++) {
+ if (rules->global)
+ result = __ipa_add_global_flt_rule(rules->ip,
+ &rules->rules[i].rule,
+ rules->rules[i].at_rear,
+ &rules->rules[i].flt_rule_hdl);
+ else
+ result = __ipa_add_ep_flt_rule(rules->ip, rules->ep,
+ &rules->rules[i].rule,
+ rules->rules[i].at_rear,
+ &rules->rules[i].flt_rule_hdl);
+ if (result) {
+ IPAERR("failed to add flt rule %d\n", i);
+ rules->rules[i].status = IPA_FLT_STATUS_OF_ADD_FAILED;
+ } else {
+ rules->rules[i].status = 0;
+ }
+ }
+
+ if (rules->commit)
+ if (__ipa_commit_flt(rules->ip)) {
+ result = -EPERM;
+ goto bail;
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_add_flt_rule);
+
+/**
+ * ipa_del_flt_rule() - Remove the specified filtering rules from SW and
+ * optionally commit to IPA HW
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_del_flt_rule(struct ipa_ioc_del_flt_rule *hdls)
+{
+ int i;
+ int result;
+
+ if (hdls == NULL || hdls->num_hdls == 0 || hdls->ip >= IPA_IP_MAX) {
+ IPAERR("bad parm\n");
+
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < hdls->num_hdls; i++) {
+ if (__ipa_del_flt_rule(hdls->hdl[i].hdl)) {
+ IPAERR("failed to del rt rule %i\n", i);
+ hdls->hdl[i].status = IPA_FLT_STATUS_OF_DEL_FAILED;
+ } else {
+ hdls->hdl[i].status = 0;
+ }
+ }
+
+ if (hdls->commit)
+ if (__ipa_commit_flt(hdls->ip)) {
+ mutex_unlock(&ipa_ctx->lock);
+ result = -EPERM;
+ goto bail;
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_del_flt_rule);
+
+/**
+ * ipa_commit_flt() - Commit the current SW filtering table of specified type to
+ * IPA HW
+ * @ip: [in] the family of routing tables
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_commit_flt(enum ipa_ip_type ip)
+{
+ int result;
+
+ mutex_lock(&ipa_ctx->lock);
+
+ if (__ipa_commit_flt(ip)) {
+ result = -EPERM;
+ goto bail;
+ }
+ result = 0;
+
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_commit_flt);
+
+/**
+ * ipa_reset_flt() - Reset the current SW filtering table of specified type
+ * (does not commit to HW)
+ * @ip: [in] the family of routing tables
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_reset_flt(enum ipa_ip_type ip)
+{
+ struct ipa_flt_tbl *tbl;
+ struct ipa_flt_entry *entry;
+ struct ipa_flt_entry *next;
+ struct ipa_tree_node *node;
+ int i;
+
+ tbl = &ipa_ctx->glob_flt_tbl[ip];
+ mutex_lock(&ipa_ctx->lock);
+ IPADBG("reset flt ip=%d\n", ip);
+ list_for_each_entry_safe(entry, next, &tbl->head_flt_rule_list, link) {
+ node = ipa_search(&ipa_ctx->flt_rule_hdl_tree, (u32)entry);
+ if (node == NULL)
+ WARN_ON(1);
+ list_del(&entry->link);
+ entry->tbl->rule_cnt--;
+ entry->rt_tbl->ref_cnt--;
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+ }
+
+ for (i = 0; i < IPA_NUM_PIPES; i++) {
+ tbl = &ipa_ctx->flt_tbl[i][ip];
+ list_for_each_entry_safe(entry, next, &tbl->head_flt_rule_list,
+ link) {
+ node = ipa_search(&ipa_ctx->flt_rule_hdl_tree,
+ (u32)entry);
+ if (node == NULL)
+ WARN_ON(1);
+ list_del(&entry->link);
+ entry->tbl->rule_cnt--;
+ entry->rt_tbl->ref_cnt--;
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->flt_rule_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->flt_rule_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+ }
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_reset_flt);
diff --git a/drivers/platform/msm/ipa/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_hdr.c
new file mode 100644
index 0000000..4b9a500
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_hdr.c
@@ -0,0 +1,614 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ipa_i.h"
+
+static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 32, 64 };
+
+/**
+ * ipa_generate_hdr_hw_tbl() - generates the headers table
+ * @mem: [out] buffer to put the header table
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem)
+{
+ struct ipa_hdr_entry *entry;
+
+ mem->size = ipa_ctx->hdr_tbl.end;
+
+ if (mem->size == 0) {
+ IPAERR("hdr tbl empty\n");
+ return -EPERM;
+ }
+ IPADBG("tbl_sz=%d\n", ipa_ctx->hdr_tbl.end);
+
+ mem->base = dma_alloc_coherent(NULL, mem->size, &mem->phys_base,
+ GFP_KERNEL);
+ if (!mem->base) {
+ IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
+ return -ENOMEM;
+ }
+
+ memset(mem->base, 0, mem->size);
+ list_for_each_entry(entry, &ipa_ctx->hdr_tbl.head_hdr_entry_list,
+ link) {
+ IPADBG("hdr of len %d ofst=%d\n", entry->hdr_len,
+ entry->offset_entry->offset);
+ memcpy(mem->base + entry->offset_entry->offset, entry->hdr,
+ entry->hdr_len);
+ }
+
+ return 0;
+}
+
+/*
+ * __ipa_commit_hdr() commits hdr to hardware
+ * This function needs to be called with a locked mutex.
+ */
+static int __ipa_commit_hdr(void)
+{
+ struct ipa_desc desc = { 0 };
+ struct ipa_mem_buffer *mem;
+ struct ipa_hdr_init_local *cmd;
+ u16 len;
+
+ mem = kmalloc(sizeof(struct ipa_mem_buffer), GFP_KERNEL);
+ if (!mem) {
+ IPAERR("failed to alloc memory object\n");
+ goto fail_alloc_mem;
+ }
+
+ /* the immediate command param size is same for both local and system */
+ len = sizeof(struct ipa_hdr_init_local);
+
+ /*
+ * we can use init_local ptr for init_system due to layout of the
+ * struct
+ */
+ cmd = kmalloc(len, GFP_KERNEL);
+ if (!cmd) {
+ IPAERR("failed to alloc immediate command object\n");
+ goto fail_alloc_cmd;
+ }
+
+ if (ipa_generate_hdr_hw_tbl(mem)) {
+ IPAERR("fail to generate HDR HW TBL\n");
+ goto fail_hw_tbl_gen;
+ }
+
+ if (ipa_ctx->hdr_tbl_lcl && mem->size > IPA_RAM_HDR_SIZE) {
+ IPAERR("tbl too big, needed %d avail %d\n", mem->size,
+ IPA_RAM_HDR_SIZE);
+ goto fail_hw_tbl_gen;
+ }
+
+ cmd->hdr_table_addr = mem->phys_base;
+ if (ipa_ctx->hdr_tbl_lcl) {
+ cmd->size_hdr_table = mem->size;
+ cmd->hdr_addr = IPA_RAM_HDR_OFST;
+ desc.opcode = IPA_HDR_INIT_LOCAL;
+ } else {
+ desc.opcode = IPA_HDR_INIT_SYSTEM;
+ }
+ desc.pyld = cmd;
+ desc.len = sizeof(struct ipa_hdr_init_local);
+ desc.type = IPA_IMM_CMD_DESC;
+ IPA_DUMP_BUFF(mem->base, mem->phys_base, mem->size);
+
+ if (ipa_send_cmd(1, &desc)) {
+ IPAERR("fail to send immediate command\n");
+ goto fail_send_cmd;
+ }
+
+ if (ipa_ctx->hdr_tbl_lcl) {
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+ } else {
+ if (ipa_ctx->hdr_mem.phys_base) {
+ dma_free_coherent(NULL, ipa_ctx->hdr_mem.size,
+ ipa_ctx->hdr_mem.base,
+ ipa_ctx->hdr_mem.phys_base);
+ }
+ ipa_ctx->hdr_mem = *mem;
+ }
+ kfree(cmd);
+ kfree(mem);
+
+ return 0;
+
+fail_send_cmd:
+ if (mem->phys_base)
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+fail_hw_tbl_gen:
+ kfree(cmd);
+fail_alloc_cmd:
+ kfree(mem);
+fail_alloc_mem:
+
+ return -EPERM;
+}
+
+static int __ipa_add_hdr(struct ipa_hdr_add *hdr)
+{
+ struct ipa_hdr_entry *entry;
+ struct ipa_hdr_offset_entry *offset;
+ struct ipa_tree_node *node;
+ u32 bin;
+ struct ipa_hdr_tbl *htbl = &ipa_ctx->hdr_tbl;
+
+ if (hdr->hdr_len == 0) {
+ IPAERR("bad parm\n");
+ goto error;
+ }
+
+ node = kmem_cache_zalloc(ipa_ctx->tree_node_cache, GFP_KERNEL);
+ if (!node) {
+ IPAERR("failed to alloc tree node object\n");
+ goto error;
+ }
+
+ entry = kmem_cache_zalloc(ipa_ctx->hdr_cache, GFP_KERNEL);
+ if (!entry) {
+ IPAERR("failed to alloc hdr object\n");
+ goto hdr_alloc_fail;
+ }
+
+ INIT_LIST_HEAD(&entry->link);
+
+ memcpy(entry->hdr, hdr->hdr, hdr->hdr_len);
+ entry->hdr_len = hdr->hdr_len;
+ strlcpy(entry->name, hdr->name, IPA_RESOURCE_NAME_MAX);
+ entry->is_partial = hdr->is_partial;
+ entry->cookie = IPA_COOKIE;
+
+ if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN0])
+ bin = IPA_HDR_BIN0;
+ else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN1])
+ bin = IPA_HDR_BIN1;
+ else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN2])
+ bin = IPA_HDR_BIN2;
+ else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN3])
+ bin = IPA_HDR_BIN3;
+ else {
+ IPAERR("unexpected hdr len %d\n", hdr->hdr_len);
+ goto bad_hdr_len;
+ }
+
+ if (list_empty(&htbl->head_free_offset_list[bin])) {
+ offset = kmem_cache_zalloc(ipa_ctx->hdr_offset_cache,
+ GFP_KERNEL);
+ if (!offset) {
+ IPAERR("failed to alloc hdr offset object\n");
+ goto ofst_alloc_fail;
+ }
+ INIT_LIST_HEAD(&offset->link);
+ /*
+ * for a first item grow, set the bin and offset which are set
+ * in stone
+ */
+ offset->offset = htbl->end;
+ offset->bin = bin;
+ htbl->end += ipa_hdr_bin_sz[bin];
+ list_add(&offset->link,
+ &htbl->head_offset_list[bin]);
+ } else {
+ /* get the first free slot */
+ offset =
+ list_first_entry(&htbl->head_free_offset_list[bin],
+ struct ipa_hdr_offset_entry, link);
+ list_move(&offset->link, &htbl->head_offset_list[bin]);
+ }
+
+ entry->offset_entry = offset;
+ list_add(&entry->link, &htbl->head_hdr_entry_list);
+ htbl->hdr_cnt++;
+ IPADBG("add hdr of sz=%d hdr_cnt=%d ofst=%d\n", hdr->hdr_len,
+ htbl->hdr_cnt, offset->offset);
+
+ hdr->hdr_hdl = (u32) entry;
+ node->hdl = hdr->hdr_hdl;
+ if (ipa_insert(&ipa_ctx->hdr_hdl_tree, node)) {
+ IPAERR("failed to add to tree\n");
+ WARN_ON(1);
+ }
+
+ return 0;
+
+ofst_alloc_fail:
+ kmem_cache_free(ipa_ctx->hdr_offset_cache, offset);
+bad_hdr_len:
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->hdr_cache, entry);
+hdr_alloc_fail:
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+error:
+ return -EPERM;
+}
+
+static int __ipa_del_hdr(u32 hdr_hdl)
+{
+ struct ipa_hdr_entry *entry = (struct ipa_hdr_entry *)hdr_hdl;
+ struct ipa_tree_node *node;
+ struct ipa_hdr_tbl *htbl = &ipa_ctx->hdr_tbl;
+
+ if (!entry || (entry->cookie != IPA_COOKIE) || (entry->ref_cnt != 0)) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->hdr_hdl_tree, hdr_hdl);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+ return -EPERM;
+ }
+
+ IPADBG("del hdr of sz=%d hdr_cnt=%d ofst=%d\n", entry->hdr_len,
+ htbl->hdr_cnt, entry->offset_entry->offset);
+
+ /* move the offset entry to appropriate free list */
+ list_move(&entry->offset_entry->link,
+ &htbl->head_free_offset_list[entry->offset_entry->bin]);
+ list_del(&entry->link);
+ htbl->hdr_cnt--;
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->hdr_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->hdr_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+
+ return 0;
+}
+
+/**
+ * ipa_add_hdr() - add the specified headers to SW and optionally commit them to
+ * IPA HW
+ * @hdrs: [inout] set of headers to add
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs)
+{
+ int i;
+ int result = -EFAULT;
+
+ if (hdrs == NULL || hdrs->num_hdrs == 0) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < hdrs->num_hdrs; i++) {
+ if (__ipa_add_hdr(&hdrs->hdr[i])) {
+ IPAERR("failed to add hdr %d\n", i);
+ hdrs->hdr[i].status = -1;
+ } else {
+ hdrs->hdr[i].status = 0;
+ }
+ }
+
+ if (hdrs->commit) {
+ if (__ipa_commit_hdr()) {
+ result = -EPERM;
+ goto bail;
+ }
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return result;
+}
+EXPORT_SYMBOL(ipa_add_hdr);
+
+/**
+ * ipa_del_hdr() - Remove the specified headers from SW and optionally commit them
+ * to IPA HW
+ * @hdls: [inout] set of headers to delete
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls)
+{
+ int i;
+ int result = -EFAULT;
+
+ if (hdls == NULL || hdls->num_hdls == 0) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < hdls->num_hdls; i++) {
+ if (__ipa_del_hdr(hdls->hdl[i].hdl)) {
+ IPAERR("failed to del hdr %i\n", i);
+ hdls->hdl[i].status = -1;
+ } else {
+ hdls->hdl[i].status = 0;
+ }
+ }
+
+ if (hdls->commit) {
+ if (__ipa_commit_hdr()) {
+ result = -EPERM;
+ goto bail;
+ }
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return result;
+}
+EXPORT_SYMBOL(ipa_del_hdr);
+
+/**
+ * ipa_dump_hdr() - prints all the headers in the header table in SW
+ *
+ * Note: Should not be called from atomic context
+ */
+void ipa_dump_hdr(void)
+{
+ struct ipa_hdr_entry *entry;
+
+ IPADBG("START\n");
+ mutex_lock(&ipa_ctx->lock);
+ list_for_each_entry(entry, &ipa_ctx->hdr_tbl.head_hdr_entry_list,
+ link) {
+ IPADBG("hdr_len=%4d off=%4d bin=%4d\n", entry->hdr_len,
+ entry->offset_entry->offset,
+ entry->offset_entry->bin);
+ }
+ mutex_unlock(&ipa_ctx->lock);
+ IPADBG("END\n");
+}
+
+/**
+ * ipa_commit_hdr() - commit to IPA HW the current header table in SW
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_commit_hdr(void)
+{
+ int result = -EFAULT;
+
+ /*
+ * issue a commit on the routing module since routing rules point to
+ * header table entries
+ */
+ if (ipa_commit_rt(IPA_IP_v4))
+ return -EPERM;
+ if (ipa_commit_rt(IPA_IP_v6))
+ return -EPERM;
+
+ mutex_lock(&ipa_ctx->lock);
+ if (__ipa_commit_hdr()) {
+ result = -EPERM;
+ goto bail;
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return result;
+}
+EXPORT_SYMBOL(ipa_commit_hdr);
+
+/**
+ * ipa_reset_hdr() - reset the current header table in SW (does not commit to
+ * HW)
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_reset_hdr(void)
+{
+ struct ipa_hdr_entry *entry;
+ struct ipa_hdr_entry *next;
+ struct ipa_hdr_offset_entry *off_entry;
+ struct ipa_hdr_offset_entry *off_next;
+ struct ipa_tree_node *node;
+ int i;
+
+ /*
+ * issue a reset on the routing module since routing rules point to
+ * header table entries
+ */
+ if (ipa_reset_rt(IPA_IP_v4))
+ IPAERR("fail to reset v4 rt\n");
+ if (ipa_reset_rt(IPA_IP_v6))
+ IPAERR("fail to reset v4 rt\n");
+
+ mutex_lock(&ipa_ctx->lock);
+ IPADBG("reset hdr\n");
+ list_for_each_entry_safe(entry, next,
+ &ipa_ctx->hdr_tbl.head_hdr_entry_list, link) {
+
+ /* do not remove the default exception header */
+ if (!strncmp(entry->name, IPA_DFLT_HDR_NAME,
+ IPA_RESOURCE_NAME_MAX))
+ continue;
+
+ node = ipa_search(&ipa_ctx->hdr_hdl_tree, (u32) entry);
+ if (node == NULL)
+ WARN_ON(1);
+ list_del(&entry->link);
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->hdr_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->hdr_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+
+ }
+ for (i = 0; i < IPA_HDR_BIN_MAX; i++) {
+ list_for_each_entry_safe(off_entry, off_next,
+ &ipa_ctx->hdr_tbl.head_offset_list[i],
+ link) {
+
+ /*
+ * do not remove the default exception header which is
+ * at offset 0
+ */
+ if (off_entry->offset == 0)
+ continue;
+
+ list_del(&off_entry->link);
+ kmem_cache_free(ipa_ctx->hdr_offset_cache, off_entry);
+ }
+ list_for_each_entry_safe(off_entry, off_next,
+ &ipa_ctx->hdr_tbl.head_free_offset_list[i],
+ link) {
+ list_del(&off_entry->link);
+ kmem_cache_free(ipa_ctx->hdr_offset_cache, off_entry);
+ }
+ }
+ /* there is one header of size 8 */
+ ipa_ctx->hdr_tbl.end = 8;
+ ipa_ctx->hdr_tbl.hdr_cnt = 1;
+ mutex_unlock(&ipa_ctx->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_reset_hdr);
+
+static struct ipa_hdr_entry *__ipa_find_hdr(const char *name)
+{
+ struct ipa_hdr_entry *entry;
+
+ list_for_each_entry(entry, &ipa_ctx->hdr_tbl.head_hdr_entry_list,
+ link) {
+ if (!strncmp(name, entry->name, IPA_RESOURCE_NAME_MAX))
+ return entry;
+ }
+
+ return NULL;
+}
+
+/**
+ * ipa_get_hdr() - Lookup the specified header resource
+ * @lookup: [inout] header to lookup and its handle
+ *
+ * lookup the specified header resource and return handle if it exists, if
+ * lookup succeeds the header entry ref cnt is increased
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ * Caller should call ipa_put_hdr later if this function succeeds
+ */
+int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup)
+{
+ struct ipa_hdr_entry *entry;
+ int result = -1;
+
+ if (lookup == NULL) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+ mutex_lock(&ipa_ctx->lock);
+ entry = __ipa_find_hdr(lookup->name);
+ if (entry) {
+ entry->ref_cnt++;
+ lookup->hdl = (uint32_t) entry;
+ result = 0;
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_get_hdr);
+
+/**
+ * ipa_put_hdr() - Release the specified header handle
+ * @hdr_hdl: [in] the header handle to release
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_put_hdr(u32 hdr_hdl)
+{
+ struct ipa_hdr_entry *entry = (struct ipa_hdr_entry *)hdr_hdl;
+ struct ipa_tree_node *node;
+ int result = -EFAULT;
+
+ if (entry == NULL || entry->cookie != IPA_COOKIE ||
+ entry->ref_cnt == 0) {
+ IPAERR("bad params\n");
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->hdr_hdl_tree, hdr_hdl);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+ return -EPERM;
+ }
+ mutex_lock(&ipa_ctx->lock);
+ entry->ref_cnt--;
+ if (entry->ref_cnt == 0) {
+ if (__ipa_del_hdr(hdr_hdl)) {
+ IPAERR("fail to del hdr\n");
+ result = -EFAULT;
+ goto bail;
+ }
+ /* commit for put */
+ if (__ipa_commit_hdr()) {
+ IPAERR("fail to commit hdr\n");
+ result = -EFAULT;
+ goto bail;
+ }
+ }
+ result = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return result;
+}
+EXPORT_SYMBOL(ipa_put_hdr);
+
+/**
+ * ipa_copy_hdr() - Lookup the specified header resource and return a copy of it
+ * @copy: [inout] header to lookup and its copy
+ *
+ * lookup the specified header resource and return a copy of it (along with its
+ * attributes) if it exists, this would be called for partial headers
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_copy_hdr(struct ipa_ioc_copy_hdr *copy)
+{
+ struct ipa_hdr_entry *entry;
+ int result = -EFAULT;
+
+ if (copy == NULL) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+ mutex_lock(&ipa_ctx->lock);
+ entry = __ipa_find_hdr(copy->name);
+ if (entry) {
+ memcpy(copy->hdr, entry->hdr, entry->hdr_len);
+ copy->hdr_len = entry->hdr_len;
+ copy->is_partial = entry->is_partial;
+ result = 0;
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_copy_hdr);
+
+
diff --git a/drivers/platform/msm/ipa/ipa_hw_defs.h b/drivers/platform/msm/ipa/ipa_hw_defs.h
new file mode 100644
index 0000000..3131a84
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_hw_defs.h
@@ -0,0 +1,258 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_HW_DEFS_H
+#define _IPA_HW_DEFS_H
+#include <linux/bitops.h>
+
+/* This header defines various HW related data types */
+
+/* immediate command op-codes */
+#define IPA_DECIPH_INIT (1)
+#define IPA_PPP_FRM_INIT (2)
+#define IPA_IP_V4_FILTER_INIT (3)
+#define IPA_IP_V6_FILTER_INIT (4)
+#define IPA_IP_V4_NAT_INIT (5)
+#define IPA_IP_V6_NAT_INIT (6)
+#define IPA_IP_V4_ROUTING_INIT (7)
+#define IPA_IP_V6_ROUTING_INIT (8)
+#define IPA_HDR_INIT_LOCAL (9)
+#define IPA_HDR_INIT_SYSTEM (10)
+#define IPA_DECIPH_SETUP (11)
+#define IPA_INSERT_NAT_RULE (12)
+#define IPA_DELETE_NAT_RULE (13)
+#define IPA_NAT_DMA (14)
+#define IPA_IP_PACKET_TAG (15)
+#define IPA_IP_PACKET_INIT (16)
+
+#define IPA_INTERFACE_ID_EXCEPTION (0)
+#define IPA_INTERFACE_ID_A2_WWAN (0x10)
+#define IPA_INTERFACE_ID_HSUSB_RMNET1 (0x21)
+#define IPA_INTERFACE_ID_HSUSB_RMNET2 (0x22)
+#define IPA_INTERFACE_ID_HSUSB_RMNET3 (0x23)
+#define IPA_INTERFACE_ID_HSIC_WLAN_WAN (0x31)
+#define IPA_INTERFACE_ID_HSIC_WLAN_LAN1 (0x32)
+#define IPA_INTERFACE_ID_HSIC_WLAN_LAN2 (0x33)
+#define IPA_INTERFACE_ID_HSIC_RMNET1 (0x41)
+#define IPA_INTERFACE_ID_HSIC_RMNET2 (0x42)
+#define IPA_INTERFACE_ID_HSIC_RMNET3 (0x43)
+#define IPA_INTERFACE_ID_HSIC_RMNET4 (0x44)
+#define IPA_INTERFACE_ID_HSIC_RMNET5 (0x45)
+
+/**
+ * struct ipa_flt_rule_hw_hdr - HW header of IPA filter rule
+ * @word: filtering rule properties
+ * @en_rule: enable rule
+ * @action: post routing action
+ * @rt_tbl_idx: index in routing table
+ * @rsvd: reserved
+ */
+struct ipa_flt_rule_hw_hdr {
+ union {
+ u32 word;
+ struct {
+ u32 en_rule:16;
+ u32 action:5;
+ u32 rt_tbl_idx:5;
+ u32 rsvd:6;
+ } hdr;
+ } u;
+};
+
+/**
+ * struct ipa_rt_rule_hw_hdr - HW header of IPA routing rule
+ * @word: filtering rule properties
+ * @en_rule: enable rule
+ * @pipe_dest_idx: destination pipe index
+ * @system: changed from local to system due to HW change
+ * @hdr_offset: header offset
+ */
+struct ipa_rt_rule_hw_hdr {
+ union {
+ u32 word;
+ struct {
+ u32 en_rule:16;
+ u32 pipe_dest_idx:5;
+ u32 system:1;
+ u32 hdr_offset:10;
+ } hdr;
+ } u;
+};
+
+/**
+ * struct ipa_ip_v4_filter_init - IPA_IP_V4_FILTER_INIT command payload
+ * @ipv4_rules_addr: address of ipv4 rules
+ * @size_ipv4_rules: size of the above
+ * @ipv4_addr: ipv4 address
+ * @rsvd: reserved
+ */
+struct ipa_ip_v4_filter_init {
+ u64 ipv4_rules_addr:32;
+ u64 size_ipv4_rules:12;
+ u64 ipv4_addr:16;
+ u64 rsvd:4;
+};
+
+/**
+ * struct ipa_ip_v6_filter_init - IPA_IP_V6_FILTER_INIT command payload
+ * @ipv6_rules_addr: address of ipv6 rules
+ * @size_ipv6_rules: size of the above
+ * @ipv6_addr: ipv6 address
+ */
+struct ipa_ip_v6_filter_init {
+ u64 ipv6_rules_addr:32;
+ u64 size_ipv6_rules:16;
+ u64 ipv6_addr:16;
+};
+
+/**
+ * struct ipa_ip_v4_routing_init - IPA_IP_V4_ROUTING_INIT command payload
+ * @ipv4_rules_addr: address of ipv4 rules
+ * @size_ipv4_rules: size of the above
+ * @ipv4_addr: ipv4 address
+ * @rsvd: reserved
+ */
+struct ipa_ip_v4_routing_init {
+ u64 ipv4_rules_addr:32;
+ u64 size_ipv4_rules:12;
+ u64 ipv4_addr:16;
+ u64 rsvd:4;
+};
+
+/**
+ * struct ipa_ip_v6_routing_init - IPA_IP_V6_ROUTING_INIT command payload
+ * @ipv6_rules_addr: address of ipv6 rules
+ * @size_ipv6_rules: size of the above
+ * @ipv6_addr: ipv6 address
+ */
+struct ipa_ip_v6_routing_init {
+ u64 ipv6_rules_addr:32;
+ u64 size_ipv6_rules:16;
+ u64 ipv6_addr:16;
+};
+
+/**
+ * struct ipa_hdr_init_local - IPA_HDR_INIT_LOCAL command payload
+ * @hdr_table_addr: address of header table
+ * @size_hdr_table: size of the above
+ * @hdr_addr: header address
+ * @rsvd: reserved
+ */
+struct ipa_hdr_init_local {
+ u64 hdr_table_addr:32;
+ u64 size_hdr_table:12;
+ u64 hdr_addr:16;
+ u64 rsvd:4;
+};
+
+/**
+ * struct ipa_hdr_init_system - IPA_HDR_INIT_SYSTEM command payload
+ * @hdr_table_addr: address of header table
+ * @rsvd: reserved
+ */
+struct ipa_hdr_init_system {
+ u64 hdr_table_addr:32;
+ u64 rsvd:32;
+};
+
+#define IPA_A5_MUX_HDR_EXCP_FLAG_IP BIT(0)
+#define IPA_A5_MUX_HDR_EXCP_FLAG_NAT BIT(1)
+#define IPA_A5_MUX_HDR_EXCP_FLAG_SW_FLT BIT(2)
+#define IPA_A5_MUX_HDR_EXCP_FLAG_TAG BIT(3)
+#define IPA_A5_MUX_HDR_EXCP_FLAG_REPLICATED BIT(4)
+#define IPA_A5_MUX_HDR_EXCP_FLAG_IHL BIT(5)
+
+/**
+ * struct ipa_a5_mux_hdr - A5 MUX header definition
+ * @interface_id: interface ID
+ * @src_pipe_index: source pipe index
+ * @flags: flags
+ * @metadata: metadata
+ *
+ * A5 MUX header is in BE, A5 runs in LE. This struct definition
+ * allows A5 SW to correctly parse the header
+ */
+struct ipa_a5_mux_hdr {
+ u16 interface_id;
+ u8 src_pipe_index;
+ u8 flags;
+ u32 metadata;
+};
+
+/**
+ * struct ipa_nat_dma - IPA_NAT_DMA command payload
+ * @table_index: NAT table index
+ * @rsvd1: reserved
+ * @base_addr: base address
+ * @rsvd2: reserved
+ * @offset: offset
+ * @data: metadata
+ * @rsvd3: reserved
+ */
+struct ipa_nat_dma {
+ u64 table_index:3;
+ u64 rsvd1:1;
+ u64 base_addr:2;
+ u64 rsvd2:2;
+ u64 offset:32;
+ u64 data:16;
+ u64 rsvd3:8;
+};
+
+/**
+ * struct ipa_nat_dma - IPA_IP_PACKET_INIT command payload
+ * @destination_pipe_index: destination pipe index
+ * @rsvd1: reserved
+ * @metadata: metadata
+ * @rsvd2: reserved
+ */
+struct ipa_ip_packet_init {
+ u64 destination_pipe_index:5;
+ u64 rsvd1:3;
+ u64 metadata:32;
+ u64 rsvd2:24;
+};
+
+/**
+ * struct ipa_nat_dma - IPA_IP_V4_NAT_INIT command payload
+ * @ipv4_rules_addr: ipv4 rules address
+ * @ipv4_expansion_rules_addr: ipv4 expansion rules address
+ * @index_table_addr: index tables address
+ * @index_table_expansion_addr: index expansion table address
+ * @table_index: index in table
+ * @ipv4_rules_addr_type: ipv4 address type
+ * @ipv4_expansion_rules_addr_type: ipv4 expansion address type
+ * @index_table_addr_type: index table address type
+ * @index_table_expansion_addr_type: index expansion table type
+ * @size_base_tables: size of base tables
+ * @size_expansion_tables: size of expansion tables
+ * @rsvd2: reserved
+ * @public_ip_addr: public IP address
+ */
+struct ipa_ip_v4_nat_init {
+ u64 ipv4_rules_addr:32;
+ u64 ipv4_expansion_rules_addr:32;
+ u64 index_table_addr:32;
+ u64 index_table_expansion_addr:32;
+ u64 table_index:3;
+ u64 rsvd1:1;
+ u64 ipv4_rules_addr_type:1;
+ u64 ipv4_expansion_rules_addr_type:1;
+ u64 index_table_addr_type:1;
+ u64 index_table_expansion_addr_type:1;
+ u64 size_base_tables:12;
+ u64 size_expansion_tables:10;
+ u64 rsvd2:2;
+ u64 public_ip_addr:32;
+};
+
+#endif /* _IPA_HW_DEFS_H */
diff --git a/drivers/platform/msm/ipa/ipa_i.h b/drivers/platform/msm/ipa/ipa_i.h
new file mode 100644
index 0000000..63ef5fb
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_i.h
@@ -0,0 +1,727 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_I_H_
+#define _IPA_I_H_
+
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/export.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <mach/ipa.h>
+#include <mach/sps.h>
+#include "ipa_hw_defs.h"
+#include "ipa_ram_mmap.h"
+#include "ipa_reg.h"
+
+#define DRV_NAME "ipa"
+#define IPA_COOKIE 0xfacefeed
+
+#define IPA_NUM_PIPES 0x14
+#define IPA_SYS_DESC_FIFO_SZ (0x800)
+
+#ifdef IPA_DEBUG
+#define IPADBG(fmt, args...) \
+ pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)
+#else
+#define IPADBG(fmt, args...)
+#endif
+
+#define IPAERR(fmt, args...) \
+ pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)
+
+#define IPA_TOS_EQ BIT(0)
+#define IPA_PROTOCOL_EQ BIT(1)
+#define IPA_OFFSET_MEQ32_0 BIT(2)
+#define IPA_OFFSET_MEQ32_1 BIT(3)
+#define IPA_IHL_OFFSET_RANGE16_0 BIT(4)
+#define IPA_IHL_OFFSET_RANGE16_1 BIT(5)
+#define IPA_IHL_OFFSET_EQ_16 BIT(6)
+#define IPA_IHL_OFFSET_EQ_32 BIT(7)
+#define IPA_IHL_OFFSET_MEQ32_0 BIT(8)
+#define IPA_OFFSET_MEQ128_0 BIT(9)
+#define IPA_OFFSET_MEQ128_1 BIT(10)
+#define IPA_TC_EQ BIT(11)
+#define IPA_FL_EQ BIT(12)
+#define IPA_IHL_OFFSET_MEQ32_1 BIT(13)
+#define IPA_METADATA_COMPARE BIT(14)
+#define IPA_IPV4_IS_FRAG BIT(15)
+
+#define IPA_HDR_BIN0 0
+#define IPA_HDR_BIN1 1
+#define IPA_HDR_BIN2 2
+#define IPA_HDR_BIN3 3
+#define IPA_HDR_BIN_MAX 4
+
+#define IPA_EVENT_THRESHOLD 0x10
+
+#define IPA_RX_POOL_CEIL 24
+#define IPA_RX_SKB_SIZE 2048
+
+#define IPA_DFLT_HDR_NAME "ipa_excp_hdr"
+
+#define IPA_CLIENT_IS_PROD(x) (x >= IPA_CLIENT_PROD && x < IPA_CLIENT_CONS)
+#define IPA_CLIENT_IS_CONS(x) (x >= IPA_CLIENT_CONS && x < IPA_CLIENT_MAX)
+#define IPA_SETFIELD(val, shift, mask) (((val) << (shift)) & (mask))
+
+#define IPA_HW_TABLE_ALIGNMENT(start_ofst) \
+ (((start_ofst) + 127) & ~127)
+#define IPA_RT_FLT_HW_RULE_BUF_SIZE (128)
+
+/**
+ * enum ipa_sys_pipe - 5 A5-IPA pipes
+ *
+ * 5 A5-IPA pipes (all system mode)
+ */
+enum ipa_sys_pipe {
+ IPA_A5_UNUSED,
+ IPA_A5_CMD,
+ IPA_A5_LAN_WAN_OUT,
+ IPA_A5_LAN_WAN_IN,
+ IPA_A5_WLAN_AMPDU_OUT,
+ IPA_A5_SYS_MAX
+};
+
+/**
+ * enum ipa_operating_mode - IPA operating mode
+ *
+ * IPA operating mode
+ */
+enum ipa_operating_mode {
+ IPA_MODE_USB_DONGLE,
+ IPA_MODE_MSM,
+ IPA_MODE_EXT_APPS,
+ IPA_MODE_MOBILE_AP_WAN,
+ IPA_MODE_MOBILE_AP_WLAN,
+ IPA_MODE_MOBILE_AP_ETH,
+ IPA_MODE_MAX
+};
+
+/**
+ * enum ipa_bridge_dir - direction of the bridge from air interface perspective
+ *
+ * IPA bridge direction
+ */
+enum ipa_bridge_dir {
+ IPA_DL,
+ IPA_UL,
+ IPA_DIR_MAX
+};
+
+/**
+ * struct ipa_mem_buffer - IPA memory buffer
+ * @base: base
+ * @phys_base: physical base address
+ * @size: size of memory buffer
+ */
+struct ipa_mem_buffer {
+ void *base;
+ dma_addr_t phys_base;
+ u32 size;
+};
+
+/**
+ * struct ipa_flt_entry - IPA filtering table entry
+ * @link: entry's link in global filtering enrties list
+ * @rule: filter rule
+ * @cookie: cookie used for validity check
+ * @tbl: filter table
+ * @rt_tbl: routing table
+ * @hw_len: entry's size
+ */
+struct ipa_flt_entry {
+ struct list_head link;
+ struct ipa_flt_rule rule;
+ u32 cookie;
+ struct ipa_flt_tbl *tbl;
+ struct ipa_rt_tbl *rt_tbl;
+ u32 hw_len;
+};
+
+/**
+ * struct ipa_rt_tbl - IPA routing table
+ * @link: table's link in global routing tables list
+ * @head_rt_rule_list: head of routing rules list
+ * @name: routing table name
+ * @idx: routing table index
+ * @rule_cnt: number of rules in routing table
+ * @ref_cnt: reference counter of raouting table
+ * @set: collection of routing tables
+ * @cookie: cookie used for validity check
+ * @in_sys: flag indicating if the table is located in system memory
+ * @sz: the size of the routing table
+ * @curr_mem: current routing tables block in sys memory
+ * @prev_mem: previous routing table block in sys memory
+ */
+struct ipa_rt_tbl {
+ struct list_head link;
+ struct list_head head_rt_rule_list;
+ char name[IPA_RESOURCE_NAME_MAX];
+ u32 idx;
+ u32 rule_cnt;
+ u32 ref_cnt;
+ struct ipa_rt_tbl_set *set;
+ u32 cookie;
+ bool in_sys;
+ u32 sz;
+ struct ipa_mem_buffer curr_mem;
+ struct ipa_mem_buffer prev_mem;
+};
+
+/**
+ * struct ipa_hdr_entry - IPA header table entry
+ * @link: entry's link in global header table entries list
+ * @hdr: the header
+ * @hdr_len: header length
+ * @name: name of header table entry
+ * @is_partial: flag indicating if header table entry is partial
+ * @offset_entry: entry's offset
+ * @cookie: cookie used for validity check
+ * @ref_cnt: reference counter of raouting table
+ */
+struct ipa_hdr_entry {
+ struct list_head link;
+ u8 hdr[IPA_HDR_MAX_SIZE];
+ u32 hdr_len;
+ char name[IPA_RESOURCE_NAME_MAX];
+ u8 is_partial;
+ struct ipa_hdr_offset_entry *offset_entry;
+ u32 cookie;
+ u32 ref_cnt;
+};
+
+/**
+ * struct ipa_hdr_offset_entry - IPA header offset entry
+ * @link: entry's link in global header offset entries list
+ * @offset: the offset
+ * @bin: bin
+ */
+struct ipa_hdr_offset_entry {
+ struct list_head link;
+ u32 offset;
+ u32 bin;
+};
+
+/**
+ * struct ipa_hdr_tbl - IPA header table
+ * @head_hdr_entry_list: header entries list
+ * @head_offset_list: header offset list
+ * @head_free_offset_list: header free offset list
+ * @hdr_cnt: number of headers
+ * @end: the last header index
+ */
+struct ipa_hdr_tbl {
+ struct list_head head_hdr_entry_list;
+ struct list_head head_offset_list[IPA_HDR_BIN_MAX];
+ struct list_head head_free_offset_list[IPA_HDR_BIN_MAX];
+ u32 hdr_cnt;
+ u32 end;
+};
+
+/**
+ * struct ipa_flt_tbl - IPA filter table
+ * @head_flt_rule_list: filter rules list
+ * @rule_cnt: number of filter rules
+ * @in_sys: flag indicating if filter table is located in system memory
+ * @sz: the size of the filter table
+ * @end: the last header index
+ * @curr_mem: current filter tables block in sys memory
+ * @prev_mem: previous filter table block in sys memory
+ */
+struct ipa_flt_tbl {
+ struct list_head head_flt_rule_list;
+ u32 rule_cnt;
+ bool in_sys;
+ u32 sz;
+ struct ipa_mem_buffer curr_mem;
+ struct ipa_mem_buffer prev_mem;
+};
+
+/**
+ * struct ipa_rt_entry - IPA routing table entry
+ * @link: entry's link in global routing table entries list
+ * @rule: routing rule
+ * @cookie: cookie used for validity check
+ * @tbl: routing table
+ * @hdr: header table
+ * @hw_len: the length of the table
+ */
+struct ipa_rt_entry {
+ struct list_head link;
+ struct ipa_rt_rule rule;
+ u32 cookie;
+ struct ipa_rt_tbl *tbl;
+ struct ipa_hdr_entry *hdr;
+ u32 hw_len;
+};
+
+/**
+ * struct ipa_rt_tbl_set - collection of routing tables
+ * @head_rt_tbl_list: collection of routing tables
+ * @tbl_cnt: number of routing tables
+ */
+struct ipa_rt_tbl_set {
+ struct list_head head_rt_tbl_list;
+ u32 tbl_cnt;
+};
+
+/**
+ * struct ipa_tree_node - handle database entry
+ * @node: RB node
+ * @hdl: handle
+ */
+struct ipa_tree_node {
+ struct rb_node node;
+ u32 hdl;
+};
+
+/**
+ * struct ipa_ep_context - IPA end point context
+ * @valid: flag indicating id EP context is valid
+ * @client: EP client type
+ * @ep_hdl: EP's client SPS handle
+ * @cfg: EP cionfiguration
+ * @dst_pipe_index: destination pipe index
+ * @rt_tbl_idx: routing table index
+ * @connect: SPS connect
+ * @priv: user provided information
+ * @notify: user provided CB for EP events notification
+ * @desc_fifo_in_pipe_mem: flag indicating if descriptors FIFO uses pipe memory
+ * @data_fifo_in_pipe_mem: flag indicating if data FIFO uses pipe memory
+ * @desc_fifo_pipe_mem_ofst: descriptors FIFO pipe memory offset
+ * @data_fifo_pipe_mem_ofst: data FIFO pipe memory offset
+ * @desc_fifo_client_allocated: if descriptors FIFO was allocated by a client
+ * @data_fifo_client_allocated: if data FIFO was allocated by a client
+ */
+struct ipa_ep_context {
+ int valid;
+ enum ipa_client_type client;
+ struct sps_pipe *ep_hdl;
+ struct ipa_ep_cfg cfg;
+ u32 dst_pipe_index;
+ u32 rt_tbl_idx;
+ struct sps_connect connect;
+ void *priv;
+ void (*notify)(void *priv, enum ipa_dp_evt_type evt,
+ unsigned long data);
+ bool desc_fifo_in_pipe_mem;
+ bool data_fifo_in_pipe_mem;
+ u32 desc_fifo_pipe_mem_ofst;
+ u32 data_fifo_pipe_mem_ofst;
+ bool desc_fifo_client_allocated;
+ bool data_fifo_client_allocated;
+};
+
+/**
+ * struct ipa_sys_context - IPA endpoint context for system to BAM pipes
+ * @head_desc_list: header descriptors list
+ * @len: the size of the above list
+ * @spinlock: protects the list and its size
+ * @event: used to request CALLBACK mode from SPS driver
+ * @ep: IPA EP context
+ * @wait_desc_list: used to hold completed Tx packets
+ *
+ * IPA context specific to the system-bam pipes a.k.a LAN IN/OUT and WAN
+ */
+struct ipa_sys_context {
+ struct list_head head_desc_list;
+ u32 len;
+ spinlock_t spinlock;
+ struct sps_register_event event;
+ struct ipa_ep_context *ep;
+ struct list_head wait_desc_list;
+};
+
+/**
+ * enum ipa_desc_type - IPA decriptors type
+ *
+ * IPA decriptors type, IPA supports DD and ICD but no CD
+ */
+enum ipa_desc_type {
+ IPA_DATA_DESC,
+ IPA_DATA_DESC_SKB,
+ IPA_IMM_CMD_DESC
+};
+
+/**
+ * struct ipa_tx_pkt_wrapper - IPA Tx packet wrapper
+ * @type: info for the skb or immediate command param
+ * @mem: memory buffer used by this Tx packet
+ * @work: work struct for current Tx packet
+ * @link: linked to the wrappers on that pipe
+ * @callback: IPA client provided callback
+ * @user1: cookie1 for above callback
+ * @user2: cookie2 for above callback
+ * @sys: corresponding IPA sys context
+ * @mult: valid only for first of a "multiple" transfer,
+ * holds info for the "sps_transfer" buffer
+ * @cnt: 1 for single transfers,
+ * >1 and <0xFFFF for first of a "multiple" tranfer,
+ * 0xFFFF for last desc, 0 for rest of "multiple' transfer
+ * @bounce: va of bounce buffer
+ */
+struct ipa_tx_pkt_wrapper {
+ enum ipa_desc_type type;
+ struct ipa_mem_buffer mem;
+ struct work_struct work;
+ struct list_head link;
+ void (*callback)(void *user1, void *user2);
+ void *user1;
+ void *user2;
+ struct ipa_sys_context *sys;
+ struct ipa_mem_buffer mult;
+ u16 cnt;
+ void *bounce;
+};
+
+/**
+ * struct ipa_desc - IPA descriptor
+ * @type: skb or immediate command or plain old data
+ * @pyld: points to skb
+ * or kmalloc'ed immediate command parameters/plain old data
+ * @len: length of the pyld
+ * @opcode: for immediate commands
+ * @callback: IPA client provided completion callback
+ * @user1: cookie1 for above callback
+ * @user2: cookie2 for above callback
+ * @xfer_done: completion object for sync completion
+ */
+struct ipa_desc {
+ enum ipa_desc_type type;
+ void *pyld;
+ u16 len;
+ u16 opcode;
+ void (*callback)(void *user1, void *user2);
+ void *user1;
+ void *user2;
+ struct completion xfer_done;
+};
+
+/**
+ * struct ipa_rx_pkt_wrapper - IPA Rx packet wrapper
+ * @skb: skb
+ * @dma_address: DMA address of this Rx packet
+ * @work: work struct for current Rx packet
+ * @link: linked to the Rx packets on that pipe
+ * @len: how many bytes are copied into skb's flat buffer
+ */
+struct ipa_rx_pkt_wrapper {
+ struct sk_buff *skb;
+ dma_addr_t dma_address;
+ struct work_struct work;
+ struct list_head link;
+ u16 len;
+};
+
+/**
+ * struct ipa_nat_mem - IPA NAT memory description
+ * @class: pointer to the struct class
+ * @dev: the dev_t of the device
+ * @cdev: cdev of the device
+ * @dev_num: device number
+ * @vaddr: virtual address
+ * @dma_handle: DMA handle
+ * @size: NAT memory size
+ * @is_mapped: flag indicating if NAT memory is mapped
+ * @is_sys_mem: flag indicating if NAT memory is sys memory
+ * @is_dev_init: flag indicating if NAT device is initialized
+ * @lock: NAT memory mutex
+ */
+struct ipa_nat_mem {
+ struct class *class;
+ struct device *dev;
+ struct cdev cdev;
+ dev_t dev_num;
+ void *vaddr;
+ dma_addr_t dma_handle;
+ size_t size;
+ bool is_mapped;
+ bool is_sys_mem;
+ bool is_dev_init;
+ struct mutex lock;
+};
+
+/**
+ * struct ipa_context - IPA context
+ * @class: pointer to the struct class
+ * @dev_num: device number
+ * @dev: the dev_t of the device
+ * @cdev: cdev of the device
+ * @bam_handle: IPA driver's BAM handle
+ * @ep: list of all end points
+ * @flt_tbl: list of all IPA filter tables
+ * @mode: IPA operating mode
+ * @mmio: iomem
+ * @ipa_wrapper_base: IPA wrapper base address
+ * @glob_flt_tbl: global filter table
+ * @hdr_tbl: IPA header table
+ * @rt_tbl_set: list of routing tables each of which is a list of rules
+ * @reap_rt_tbl_set: list of sys mem routing tables waiting to be reaped
+ * @flt_rule_cache: filter rule cache
+ * @rt_rule_cache: routing rule cache
+ * @hdr_cache: header cache
+ * @hdr_offset_cache: header offset cache
+ * @rt_tbl_cache: routing table cache
+ * @tx_pkt_wrapper_cache: Tx packets cache
+ * @rx_pkt_wrapper_cache: Rx packets cache
+ * @tree_node_cache: tree nodes cache
+ * @rt_idx_bitmap: routing table index bitmap
+ * @lock: this does NOT protect the linked lists within ipa_sys_context
+ * @sys: IPA sys context for system-bam pipes
+ * @rx_wq: Rx packets work queue
+ * @tx_wq: Tx packets work queue
+ * @smem_sz: shared memory size
+ * @hdr_hdl_tree: header handles tree
+ * @rt_rule_hdl_tree: routing rule handles tree
+ * @rt_tbl_hdl_tree: routing table handles tree
+ * @flt_rule_hdl_tree: filtering rule handles tree
+ * @nat_mem: NAT memory
+ * @excp_hdr_hdl: exception header handle
+ * @dflt_v4_rt_rule_hdl: default v4 routing rule handle
+ * @dflt_v6_rt_rule_hdl: default v6 routing rule handle
+ * @polling_mode: 1 - pure polling mode; 0 - interrupt+polling mode
+ * @aggregation_type: aggregation type used on USB client endpoint
+ * @aggregation_byte_limit: aggregation byte limit used on USB client endpoint
+ * @aggregation_time_limit: aggregation time limit used on USB client endpoint
+ * @curr_polling_state: current polling state
+ * @poll_work: polling work
+ * @hdr_tbl_lcl: where hdr tbl resides 1-local, 0-system
+ * @hdr_mem: header memory
+ * @ip4_rt_tbl_lcl: where ip4 rt tables reside 1-local; 0-system
+ * @ip6_rt_tbl_lcl: where ip6 rt tables reside 1-local; 0-system
+ * @ip4_flt_tbl_lcl: where ip4 flt tables reside 1-local; 0-system
+ * @ip6_flt_tbl_lcl: where ip6 flt tables reside 1-local; 0-system
+ * @empty_rt_tbl_mem: empty routing tables memory
+ * @pipe_mem_pool: pipe memory pool
+ * @one_kb_no_straddle_pool: one kb no straddle pool
+ *
+ * IPA context - holds all relevant info about IPA driver and its state
+ */
+struct ipa_context {
+ struct class *class;
+ dev_t dev_num;
+ struct device *dev;
+ struct cdev cdev;
+ u32 bam_handle;
+ struct ipa_ep_context ep[IPA_NUM_PIPES];
+ struct ipa_flt_tbl flt_tbl[IPA_NUM_PIPES][IPA_IP_MAX];
+ enum ipa_operating_mode mode;
+ void __iomem *mmio;
+ u32 ipa_wrapper_base;
+ struct ipa_flt_tbl glob_flt_tbl[IPA_IP_MAX];
+ struct ipa_hdr_tbl hdr_tbl;
+ struct ipa_rt_tbl_set rt_tbl_set[IPA_IP_MAX];
+ struct ipa_rt_tbl_set reap_rt_tbl_set[IPA_IP_MAX];
+ struct kmem_cache *flt_rule_cache;
+ struct kmem_cache *rt_rule_cache;
+ struct kmem_cache *hdr_cache;
+ struct kmem_cache *hdr_offset_cache;
+ struct kmem_cache *rt_tbl_cache;
+ struct kmem_cache *tx_pkt_wrapper_cache;
+ struct kmem_cache *rx_pkt_wrapper_cache;
+ struct kmem_cache *tree_node_cache;
+ unsigned long rt_idx_bitmap[IPA_IP_MAX];
+ struct mutex lock;
+ struct ipa_sys_context sys[IPA_A5_SYS_MAX];
+ struct workqueue_struct *rx_wq;
+ struct workqueue_struct *tx_wq;
+ u16 smem_sz;
+ struct rb_root hdr_hdl_tree;
+ struct rb_root rt_rule_hdl_tree;
+ struct rb_root rt_tbl_hdl_tree;
+ struct rb_root flt_rule_hdl_tree;
+ struct ipa_nat_mem nat_mem;
+ u32 excp_hdr_hdl;
+ u32 dflt_v4_rt_rule_hdl;
+ u32 dflt_v6_rt_rule_hdl;
+ bool polling_mode;
+ uint aggregation_type;
+ uint aggregation_byte_limit;
+ uint aggregation_time_limit;
+ uint curr_polling_state;
+ struct delayed_work poll_work;
+ bool hdr_tbl_lcl;
+ struct ipa_mem_buffer hdr_mem;
+ bool ip4_rt_tbl_lcl;
+ bool ip6_rt_tbl_lcl;
+ bool ip4_flt_tbl_lcl;
+ bool ip6_flt_tbl_lcl;
+ struct ipa_mem_buffer empty_rt_tbl_mem;
+ struct gen_pool *pipe_mem_pool;
+ struct dma_pool *one_kb_no_straddle_pool;
+ atomic_t ipa_active_clients;
+ u32 clnt_hdl_cmd;
+ u32 clnt_hdl_data_in;
+ u32 clnt_hdl_data_out;
+ u8 a5_pipe_index;
+};
+
+/**
+ * struct ipa_route - IPA route
+ * @route_dis: route disable
+ * @route_def_pipe: route default pipe
+ * @route_def_hdr_table: route default header table
+ * @route_def_hdr_ofst: route default header offset table
+ */
+struct ipa_route {
+ u32 route_dis;
+ u32 route_def_pipe;
+ u32 route_def_hdr_table;
+ u32 route_def_hdr_ofst;
+};
+
+/**
+ * enum ipa_pipe_mem_type - IPA pipe memory type
+ * @IPA_SPS_PIPE_MEM: Default, SPS dedicated pipe memory
+ * @IPA_PRIVATE_MEM: IPA's private memory
+ * @IPA_SYSTEM_MEM: System RAM, requires allocation
+ */
+enum ipa_pipe_mem_type {
+ IPA_SPS_PIPE_MEM = 0,
+ IPA_PRIVATE_MEM = 1,
+ IPA_SYSTEM_MEM = 2,
+};
+
+/**
+ * enum a2_mux_pipe_direction - IPA-A2 pipe direction
+ */
+enum a2_mux_pipe_direction {
+ A2_TO_IPA = 0,
+ IPA_TO_A2 = 1
+};
+
+/**
+ * struct a2_mux_pipe_connection - A2 MUX pipe connection
+ * @src_phy_addr: source physical address
+ * @src_pipe_index: source pipe index
+ * @dst_phy_addr: destination physical address
+ * @dst_pipe_index: destination pipe index
+ * @mem_type: pipe memory type
+ * @data_fifo_base_offset: data FIFO base offset
+ * @data_fifo_size: data FIFO size
+ * @desc_fifo_base_offset: descriptors FIFO base offset
+ * @desc_fifo_size: descriptors FIFO size
+ */
+struct a2_mux_pipe_connection {
+ int src_phy_addr;
+ int src_pipe_index;
+ int dst_phy_addr;
+ int dst_pipe_index;
+ enum ipa_pipe_mem_type mem_type;
+ int data_fifo_base_offset;
+ int data_fifo_size;
+ int desc_fifo_base_offset;
+ int desc_fifo_size;
+};
+
+extern struct ipa_context *ipa_ctx;
+
+int ipa_get_a2_mux_pipe_info(enum a2_mux_pipe_direction pipe_dir,
+ struct a2_mux_pipe_connection *pipe_connect);
+void rmnet_bridge_get_client_handles(u32 *producer_handle,
+ u32 *consumer_handle);
+int ipa_send_one(struct ipa_sys_context *sys, struct ipa_desc *desc);
+int ipa_send(struct ipa_sys_context *sys, u16 num_desc, struct ipa_desc *desc);
+int ipa_get_ep_mapping(enum ipa_operating_mode mode,
+ enum ipa_client_type client);
+int ipa_generate_hw_rule(enum ipa_ip_type ip,
+ const struct ipa_rule_attrib *attrib,
+ u8 **buf,
+ u16 *en_rule);
+u8 *ipa_write_32(u32 w, u8 *dest);
+u8 *ipa_write_16(u16 hw, u8 *dest);
+u8 *ipa_write_8(u8 b, u8 *dest);
+u8 *ipa_pad_to_32(u8 *dest);
+int ipa_init_hw(void);
+struct ipa_rt_tbl *__ipa_find_rt_tbl(enum ipa_ip_type ip, const char *name);
+void ipa_dump(void);
+int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem);
+int ipa_generate_rt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
+int ipa_generate_flt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
+void ipa_debugfs_init(void);
+void ipa_debugfs_remove(void);
+
+/*
+ * below functions read from/write to IPA local memory a.k.a. device memory.
+ * the order of the arguments is deliberately different from the ipa_write*
+ * functions which operate on system memory
+ */
+void ipa_write_dev_8(u8 val, u16 ofst_ipa_sram);
+void ipa_write_dev_16(u16 val, u16 ofst_ipa_sram);
+void ipa_write_dev_32(u32 val, u16 ofst_ipa_sram);
+unsigned int ipa_read_dev_8(u16 ofst_ipa_sram);
+unsigned int ipa_read_dev_16(u16 ofst_ipa_sram);
+unsigned int ipa_read_dev_32(u16 ofst_ipa_sram);
+void ipa_write_dev_8rep(u16 ofst_ipa_sram, const void *buf,
+ unsigned long count);
+void ipa_write_dev_16rep(u16 ofst_ipa_sram, const void *buf,
+ unsigned long count);
+void ipa_write_dev_32rep(u16 ofst_ipa_sram, const void *buf,
+ unsigned long count);
+void ipa_read_dev_8rep(u16 ofst_ipa_sram, void *buf, unsigned long count);
+void ipa_read_dev_16rep(u16 ofst_ipa_sram, void *buf, unsigned long count);
+void ipa_read_dev_32rep(u16 ofst_ipa_sram, void *buf, unsigned long count);
+void ipa_memset_dev(u16 ofst_ipa_sram, u8 value, unsigned int count);
+void ipa_memcpy_from_dev(void *dest, u16 ofst_ipa_sram, unsigned int count);
+void ipa_memcpy_to_dev(u16 ofst_ipa_sram, void *source, unsigned int count);
+
+int ipa_insert(struct rb_root *root, struct ipa_tree_node *data);
+struct ipa_tree_node *ipa_search(struct rb_root *root, u32 hdl);
+void ipa_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size);
+
+#ifdef IPA_DEBUG
+#define IPA_DUMP_BUFF(base, phy_base, size) \
+ ipa_dump_buff_internal(base, phy_base, size)
+#else
+#define IPA_DUMP_BUFF(base, phy_base, size)
+#endif
+
+int ipa_cfg_route(struct ipa_route *route);
+int ipa_send_cmd(u16 num_desc, struct ipa_desc *descr);
+void ipa_replenish_rx_cache(void);
+void ipa_cleanup_rx(void);
+int ipa_cfg_filter(u32 disable);
+void ipa_write_done(struct work_struct *work);
+void ipa_handle_rx(struct work_struct *work);
+void ipa_handle_rx_core(void);
+int ipa_pipe_mem_init(u32 start_ofst, u32 size);
+int ipa_pipe_mem_alloc(u32 *ofst, u32 size);
+int ipa_pipe_mem_free(u32 ofst, u32 size);
+int ipa_straddle_boundary(u32 start, u32 end, u32 boundary);
+struct ipa_context *ipa_get_ctx(void);
+void ipa_enable_clks(void);
+void ipa_disable_clks(void);
+
+static inline u32 ipa_read_reg(void *base, u32 offset)
+{
+ u32 val = ioread32(base + offset);
+ IPADBG("0x%x(va) read reg 0x%x r_val 0x%x.\n",
+ (u32)base, offset, val);
+ return val;
+}
+
+static inline void ipa_write_reg(void *base, u32 offset, u32 val)
+{
+ iowrite32(val, base + offset);
+ IPADBG("0x%x(va) write reg 0x%x w_val 0x%x.\n",
+ (u32)base, offset, val);
+}
+
+int ipa_bridge_init(void);
+void ipa_bridge_cleanup(void);
+int ipa_bridge_setup(enum ipa_bridge_dir dir);
+int ipa_bridge_teardown(enum ipa_bridge_dir dir);
+
+#endif /* _IPA_I_H_ */
diff --git a/drivers/platform/msm/ipa/ipa_nat.c b/drivers/platform/msm/ipa/ipa_nat.c
new file mode 100644
index 0000000..c13c53a
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_nat.c
@@ -0,0 +1,466 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include "ipa_i.h"
+
+#define IPA_NAT_PHYS_MEM_OFFSET 0
+#define IPA_NAT_PHYS_MEM_SIZE IPA_RAM_NAT_SIZE
+
+#define IPA_NAT_SYSTEM_MEMORY 0
+#define IPA_NAT_SHARED_MEMORY 1
+
+static int ipa_nat_vma_fault_remap(
+ struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+ IPADBG("\n");
+ vmf->page = NULL;
+
+ return VM_FAULT_SIGBUS;
+}
+
+/* VMA related file operations functions */
+static struct vm_operations_struct ipa_nat_remap_vm_ops = {
+ .fault = ipa_nat_vma_fault_remap,
+};
+
+static int ipa_nat_open(struct inode *inode, struct file *filp)
+{
+ struct ipa_nat_mem *nat_ctx;
+ IPADBG("\n");
+ nat_ctx = container_of(inode->i_cdev, struct ipa_nat_mem, cdev);
+ filp->private_data = nat_ctx;
+ IPADBG("return\n");
+ return 0;
+}
+
+static int ipa_nat_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ unsigned long vsize = vma->vm_end - vma->vm_start;
+ struct ipa_nat_mem *nat_ctx = (struct ipa_nat_mem *)filp->private_data;
+ unsigned long phys_addr;
+ int result;
+
+ mutex_lock(&nat_ctx->lock);
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ if (nat_ctx->is_sys_mem) {
+ IPADBG("Mapping system memory\n");
+ if (nat_ctx->is_mapped) {
+ IPAERR("mapping already exists, only 1 supported\n");
+ result = -EINVAL;
+ goto bail;
+ }
+ IPADBG("map sz=0x%x\n", nat_ctx->size);
+ result =
+ dma_mmap_coherent(
+ NULL, vma,
+ nat_ctx->vaddr, nat_ctx->dma_handle,
+ nat_ctx->size);
+
+ if (result) {
+ IPAERR("unable to map memory. Err:%d\n", result);
+ goto bail;
+ }
+ } else {
+ IPADBG("Mapping shared(local) memory\n");
+ IPADBG("map sz=0x%lx\n", vsize);
+ phys_addr = ipa_ctx->ipa_wrapper_base + IPA_REG_BASE_OFST +
+ IPA_SRAM_DIRECT_ACCESS_n_OFST(IPA_NAT_PHYS_MEM_OFFSET);
+
+ if (remap_pfn_range(
+ vma, vma->vm_start,
+ phys_addr >> PAGE_SHIFT, vsize, vma->vm_page_prot)) {
+ IPAERR("remap failed\n");
+ result = -EAGAIN;
+ goto bail;
+ }
+
+ }
+ nat_ctx->is_mapped = true;
+ vma->vm_ops = &ipa_nat_remap_vm_ops;
+ IPADBG("return\n");
+ result = 0;
+bail:
+ mutex_unlock(&nat_ctx->lock);
+ return result;
+}
+
+static const struct file_operations ipa_nat_fops = {
+ .owner = THIS_MODULE,
+ .open = ipa_nat_open,
+ .mmap = ipa_nat_mmap
+};
+
+/**
+ * allocate_nat_device() - Allocates memory for the NAT device
+ * @mem: [in/out] memory parameters
+ *
+ * Called by NAT client driver to allocate memory for the NAT entries. Based on
+ * the request size either shared or system memory will be used.
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int allocate_nat_device(struct ipa_ioc_nat_alloc_mem *mem)
+{
+ struct ipa_nat_mem *nat_ctx = &(ipa_ctx->nat_mem);
+ int gfp_flags = GFP_KERNEL | __GFP_ZERO;
+ int result;
+
+ IPADBG("passed memory size %d\n", mem->size);
+
+ mutex_lock(&nat_ctx->lock);
+ if (mem->size <= 0 || !strlen(mem->dev_name)
+ || nat_ctx->is_dev_init == true) {
+ IPADBG("Invalid Parameters or device is already init\n");
+ result = -EPERM;
+ goto bail;
+ }
+
+ if (mem->size > IPA_NAT_PHYS_MEM_SIZE) {
+ IPADBG("Allocating system memory\n");
+ nat_ctx->is_sys_mem = true;
+ nat_ctx->vaddr =
+ dma_alloc_coherent(NULL, mem->size, &nat_ctx->dma_handle,
+ gfp_flags);
+ if (nat_ctx->vaddr == NULL) {
+ IPAERR("memory alloc failed\n");
+ result = -ENOMEM;
+ goto bail;
+ }
+ nat_ctx->size = mem->size;
+ } else {
+ IPADBG("using shared(local) memory\n");
+ nat_ctx->is_sys_mem = false;
+ }
+
+ nat_ctx->class = class_create(THIS_MODULE, mem->dev_name);
+ if (IS_ERR(nat_ctx->class)) {
+ IPAERR("unable to create the class\n");
+ result = -ENODEV;
+ goto vaddr_alloc_fail;
+ }
+ result = alloc_chrdev_region(&nat_ctx->dev_num,
+ 0,
+ 1,
+ mem->dev_name);
+ if (result) {
+ IPAERR("alloc_chrdev_region err.\n");
+ result = -ENODEV;
+ goto alloc_chrdev_region_fail;
+ }
+
+ nat_ctx->dev =
+ device_create(nat_ctx->class, NULL, nat_ctx->dev_num, nat_ctx,
+ mem->dev_name);
+
+ if (IS_ERR(nat_ctx->dev)) {
+ IPAERR("device_create err:%ld\n", PTR_ERR(nat_ctx->dev));
+ result = -ENODEV;
+ goto device_create_fail;
+ }
+
+ cdev_init(&nat_ctx->cdev, &ipa_nat_fops);
+ nat_ctx->cdev.owner = THIS_MODULE;
+ nat_ctx->cdev.ops = &ipa_nat_fops;
+
+ result = cdev_add(&nat_ctx->cdev, nat_ctx->dev_num, 1);
+ if (result) {
+ IPAERR("cdev_add err=%d\n", -result);
+ goto cdev_add_fail;
+ }
+ nat_ctx->is_dev_init = true;
+ IPADBG("IPA NAT driver init successfully\n");
+ result = 0;
+ goto bail;
+
+cdev_add_fail:
+ device_destroy(nat_ctx->class, nat_ctx->dev_num);
+device_create_fail:
+ unregister_chrdev_region(nat_ctx->dev_num, 1);
+alloc_chrdev_region_fail:
+ class_destroy(nat_ctx->class);
+vaddr_alloc_fail:
+ if (nat_ctx->vaddr) {
+ IPADBG("Releasing system memory\n");
+ dma_free_coherent(
+ NULL, nat_ctx->size,
+ nat_ctx->vaddr, nat_ctx->dma_handle);
+ nat_ctx->vaddr = NULL;
+ nat_ctx->dma_handle = 0;
+ nat_ctx->size = 0;
+ }
+bail:
+ mutex_unlock(&nat_ctx->lock);
+
+ return result;
+}
+
+/* IOCTL function handlers */
+/**
+ * ipa_nat_init_cmd() - Post IP_V4_NAT_INIT command to IPA HW
+ * @init: [in] initialization command attributes
+ *
+ * Called by NAT client driver to post IP_V4_NAT_INIT command to IPA HW
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_nat_init_cmd(struct ipa_ioc_v4_nat_init *init)
+{
+ struct ipa_desc desc = { 0 };
+ struct ipa_ip_v4_nat_init *cmd;
+ u16 size = sizeof(struct ipa_ip_v4_nat_init);
+ int result;
+
+ IPADBG("\n");
+ if (init->tbl_index < 0 || init->table_entries <= 0) {
+ IPADBG("Table index or entries is zero\n");
+ result = -EPERM;
+ goto bail;
+ }
+ cmd = kmalloc(size, GFP_KERNEL);
+ if (!cmd) {
+ IPAERR("Failed to alloc immediate command object\n");
+ result = -ENOMEM;
+ goto bail;
+ }
+ if (ipa_ctx->nat_mem.vaddr) {
+ IPADBG("using system memory for nat table\n");
+ cmd->ipv4_rules_addr_type = IPA_NAT_SYSTEM_MEMORY;
+ cmd->ipv4_expansion_rules_addr_type = IPA_NAT_SYSTEM_MEMORY;
+ cmd->index_table_addr_type = IPA_NAT_SYSTEM_MEMORY;
+ cmd->index_table_expansion_addr_type = IPA_NAT_SYSTEM_MEMORY;
+
+ cmd->ipv4_rules_addr =
+ ipa_ctx->nat_mem.dma_handle + init->ipv4_rules_offset;
+ IPADBG("ipv4_rules_offset:0x%x\n", init->ipv4_rules_offset);
+
+ cmd->ipv4_expansion_rules_addr =
+ ipa_ctx->nat_mem.dma_handle + init->expn_rules_offset;
+ IPADBG("expn_rules_offset:0x%x\n", init->expn_rules_offset);
+
+ cmd->index_table_addr =
+ ipa_ctx->nat_mem.dma_handle + init->index_offset;
+ IPADBG("index_offset:0x%x\n", init->index_offset);
+
+ cmd->index_table_expansion_addr =
+ ipa_ctx->nat_mem.dma_handle + init->index_expn_offset;
+ IPADBG("index_expn_offset:0x%x\n", init->index_expn_offset);
+ } else {
+ IPADBG("using shared(local) memory for nat table\n");
+ cmd->ipv4_rules_addr_type = IPA_NAT_SHARED_MEMORY;
+ cmd->ipv4_expansion_rules_addr_type = IPA_NAT_SHARED_MEMORY;
+ cmd->index_table_addr_type = IPA_NAT_SHARED_MEMORY;
+ cmd->index_table_expansion_addr_type = IPA_NAT_SHARED_MEMORY;
+
+ cmd->ipv4_rules_addr =
+ init->ipv4_rules_offset + IPA_RAM_NAT_OFST;
+
+ cmd->ipv4_expansion_rules_addr =
+ init->expn_rules_offset + IPA_RAM_NAT_OFST;
+
+ cmd->index_table_addr = init->index_offset + IPA_RAM_NAT_OFST;
+
+ cmd->index_table_expansion_addr =
+ init->index_expn_offset + IPA_RAM_NAT_OFST;
+ }
+ cmd->table_index = init->tbl_index;
+ IPADBG("Table index:0x%x\n", cmd->table_index);
+ cmd->size_base_tables = init->table_entries;
+ IPADBG("Base Table size:0x%x\n", cmd->size_base_tables);
+ cmd->size_expansion_tables = init->expn_table_entries;
+ IPADBG("Expansion Table size:0x%x\n", cmd->size_expansion_tables);
+ cmd->public_ip_addr = init->ip_addr;
+ IPADBG("Public ip address:0x%x\n", cmd->public_ip_addr);
+ desc.opcode = IPA_IP_V4_NAT_INIT;
+ desc.type = IPA_IMM_CMD_DESC;
+ desc.callback = NULL;
+ desc.user1 = NULL;
+ desc.user2 = NULL;
+ desc.pyld = (void *)cmd;
+ desc.len = size;
+ IPADBG("posting v4 init command\n");
+ if (ipa_send_cmd(1, &desc)) {
+ IPAERR("Fail to send immediate command\n");
+ result = -EPERM;
+ goto free_cmd;
+ }
+
+ IPADBG("return\n");
+ result = 0;
+free_cmd:
+ kfree(cmd);
+bail:
+ return result;
+}
+
+/**
+ * ipa_nat_dma_cmd() - Post NAT_DMA command to IPA HW
+ * @dma: [in] initialization command attributes
+ *
+ * Called by NAT client driver to post NAT_DMA command to IPA HW
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_nat_dma_cmd(struct ipa_ioc_nat_dma_cmd *dma)
+{
+ struct ipa_nat_dma *cmd = NULL;
+ struct ipa_desc *desc = NULL;
+ u16 size = 0, cnt = 0;
+ int ret = 0;
+
+ IPADBG("\n");
+ if (dma->entries <= 0) {
+ IPADBG("Invalid number of commands\n");
+ ret = -EPERM;
+ goto bail;
+ }
+ size = sizeof(struct ipa_desc) * dma->entries;
+ desc = kmalloc(size, GFP_KERNEL);
+ if (desc == NULL) {
+ IPAERR("Failed to alloc memory\n");
+ ret = -ENOMEM;
+ goto bail;
+ }
+ size = sizeof(struct ipa_nat_dma) * dma->entries;
+ cmd = kmalloc(size, GFP_KERNEL);
+ if (cmd == NULL) {
+ IPAERR("Failed to alloc memory\n");
+ ret = -ENOMEM;
+ goto bail;
+ }
+ for (cnt = 0; cnt < dma->entries; cnt++) {
+ cmd[cnt].table_index = dma->dma[cnt].table_index;
+ cmd[cnt].base_addr = dma->dma[cnt].base_addr;
+ cmd[cnt].offset = dma->dma[cnt].offset;
+ cmd[cnt].data = dma->dma[cnt].data;
+ desc[cnt].type = IPA_IMM_CMD_DESC;
+ desc[cnt].opcode = IPA_NAT_DMA;
+ desc[cnt].callback = NULL;
+ desc[cnt].user1 = NULL;
+
+ desc[cnt].user2 = NULL;
+
+ desc[cnt].len = sizeof(struct ipa_nat_dma);
+ desc[cnt].pyld = (void *)&cmd[cnt];
+ }
+ IPADBG("posting dma command with entries %d\n", dma->entries);
+ ret = ipa_send_cmd(dma->entries, desc);
+ if (ret == -EPERM)
+ IPAERR("Fail to send immediate command\n");
+
+bail:
+ kfree(cmd);
+ kfree(desc);
+
+ return ret;
+}
+
+/**
+ * ipa_nat_free_mem_and_device() - free the NAT memory and remove the device
+ * @nat_ctx: [in] the IPA NAT memory to free
+ *
+ * Called by NAT client driver to free the NAT memory and remove the device
+ */
+void ipa_nat_free_mem_and_device(struct ipa_nat_mem *nat_ctx)
+{
+ IPADBG("\n");
+ mutex_lock(&nat_ctx->lock);
+
+ if (nat_ctx->is_sys_mem) {
+ IPADBG("freeing the dma memory\n");
+ dma_free_coherent(
+ NULL, nat_ctx->size,
+ nat_ctx->vaddr, nat_ctx->dma_handle);
+ nat_ctx->size = 0;
+ nat_ctx->vaddr = NULL;
+ }
+ nat_ctx->is_mapped = false;
+ nat_ctx->is_sys_mem = false;
+ cdev_del(&nat_ctx->cdev);
+ device_destroy(nat_ctx->class, nat_ctx->dev_num);
+ unregister_chrdev_region(nat_ctx->dev_num, 1);
+ class_destroy(nat_ctx->class);
+ nat_ctx->is_dev_init = false;
+
+ mutex_unlock(&nat_ctx->lock);
+ IPADBG("return\n");
+ return;
+}
+
+/**
+ * ipa_nat_del_cmd() - Delete a NAT table
+ * @del: [in] delete table table table parameters
+ *
+ * Called by NAT client driver to delete the nat table
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_nat_del_cmd(struct ipa_ioc_v4_nat_del *del)
+{
+ struct ipa_desc desc = { 0 };
+ struct ipa_ip_v4_nat_init *cmd;
+ u16 size = sizeof(struct ipa_ip_v4_nat_init);
+ u8 mem_type = IPA_NAT_SHARED_MEMORY;
+ u32 base_addr = IPA_NAT_PHYS_MEM_OFFSET;
+ int result;
+
+ IPADBG("\n");
+ if (del->table_index < 0 || del->public_ip_addr == 0) {
+ IPADBG("Bad Parameter\n");
+ result = -EPERM;
+ goto bail;
+ }
+ cmd = kmalloc(size, GFP_KERNEL);
+ if (cmd == NULL) {
+ IPAERR("Failed to alloc immediate command object\n");
+ result = -ENOMEM;
+ goto bail;
+ }
+ cmd->table_index = del->table_index;
+ cmd->ipv4_rules_addr = base_addr;
+ cmd->ipv4_rules_addr_type = mem_type;
+ cmd->ipv4_expansion_rules_addr = base_addr;
+ cmd->ipv4_expansion_rules_addr_type = mem_type;
+ cmd->index_table_addr = base_addr;
+ cmd->index_table_addr_type = mem_type;
+ cmd->index_table_expansion_addr = base_addr;
+ cmd->index_table_expansion_addr_type = mem_type;
+ cmd->size_base_tables = 0;
+ cmd->size_expansion_tables = 0;
+ cmd->public_ip_addr = del->public_ip_addr;
+
+ desc.opcode = IPA_IP_V4_NAT_INIT;
+ desc.type = IPA_IMM_CMD_DESC;
+ desc.callback = NULL;
+ desc.user1 = NULL;
+ desc.user2 = NULL;
+ desc.pyld = (void *)cmd;
+ desc.len = size;
+ if (ipa_send_cmd(1, &desc)) {
+ IPAERR("Fail to send immediate command\n");
+ result = -EPERM;
+ goto free_mem;
+ }
+
+ ipa_nat_free_mem_and_device(&ipa_ctx->nat_mem);
+ IPADBG("return\n");
+ result = 0;
+free_mem:
+ kfree(cmd);
+bail:
+ return result;
+}
diff --git a/drivers/platform/msm/ipa/ipa_ram_mmap.h b/drivers/platform/msm/ipa/ipa_ram_mmap.h
new file mode 100644
index 0000000..000718b
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_ram_mmap.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_RAM_MMAP_H_
+#define _IPA_RAM_MMAP_H_
+
+/*
+ * This header defines the memory map of the IPA RAM (not all 8K is available
+ * for SW use) the first 2K are set aside for NAT
+ */
+
+#define IPA_RAM_NAT_OFST 0
+#define IPA_RAM_NAT_SIZE 2048
+#define IPA_RAM_HDR_OFST 2048
+#define IPA_RAM_HDR_SIZE 256
+#define IPA_RAM_V4_FLT_OFST (IPA_RAM_HDR_OFST + IPA_RAM_HDR_SIZE)
+#define IPA_RAM_V4_FLT_SIZE 1024
+#define IPA_RAM_V4_RT_OFST (IPA_RAM_V4_FLT_OFST + IPA_RAM_V4_FLT_SIZE)
+#define IPA_RAM_V4_RT_SIZE 1024
+#define IPA_RAM_V6_FLT_OFST (IPA_RAM_V4_RT_OFST + IPA_RAM_V4_RT_SIZE)
+#define IPA_RAM_V6_FLT_SIZE 1024
+#define IPA_RAM_V6_RT_OFST (IPA_RAM_V6_FLT_OFST + IPA_RAM_V6_FLT_SIZE)
+#define IPA_RAM_V6_RT_SIZE 1024
+#define IPA_RAM_END_OFST (IPA_RAM_V6_RT_OFST + IPA_RAM_V6_RT_SIZE)
+
+#endif /* _IPA_RAM_MMAP_H_ */
diff --git a/drivers/platform/msm/ipa/ipa_reg.h b/drivers/platform/msm/ipa/ipa_reg.h
new file mode 100644
index 0000000..61913b6
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_reg.h
@@ -0,0 +1,223 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __IPA_REG_H__
+#define __IPA_REG_H__
+
+/*
+ * IPA's BAM specific registers
+ */
+
+#define IPA_BAM_REG_BASE_OFST 0x00004000
+
+#define IPA_BAM_CNFG_BITS_OFST 0x7c
+#define IPA_BAM_REMAP_SIZE (0x1000)
+
+/*
+ * IPA's core specific regtisters
+ */
+
+#define IPA_REG_BASE_OFST 0x00020000
+
+#define IPA_COMP_HW_VERSION_OFST 0x00000030
+#define IPA_COMP_HW_VERSION_RMSK 0xffffffff
+#define IPA_COMP_HW_VERSION_MAJOR_BMSK 0xff000000
+#define IPA_COMP_HW_VERSION_MAJOR_SHFT 0x18
+#define IPA_COMP_HW_VERSION_MINOR_BMSK 0xff0000
+#define IPA_COMP_HW_VERSION_MINOR_SHFT 0x10
+#define IPA_COMP_HW_VERSION_STEP_BMSK 0xffff
+#define IPA_COMP_HW_VERSION_STEP_SHFT 0x0
+
+#define IPA_VERSION_OFST 0x00000034
+#define IPA_VERSION_RMSK 0xffffffff
+#define IPA_VERSION_IPA_R_REV_BMSK 0xff000000
+#define IPA_VERSION_IPA_R_REV_SHFT 0x18
+#define IPA_VERSION_IPA_Q_REV_BMSK 0xff0000
+#define IPA_VERSION_IPA_Q_REV_SHFT 0x10
+#define IPA_VERSION_IPA_P_REV_BMSK 0xff00
+#define IPA_VERSION_IPA_P_REV_SHFT 0x8
+#define IPA_VERSION_IPA_ECO_REV_BMSK 0xff
+#define IPA_VERSION_IPA_ECO_REV_SHFT 0x0
+
+#define IPA_COMP_CFG_OFST 0x00000038
+#define IPA_COMP_CFG_RMSK 0x1
+#define IPA_COMP_CFG_ENABLE_BMSK 0x1
+#define IPA_COMP_CFG_ENABLE_SHFT 0x0
+
+#define IPA_COMP_SW_RESET_OFST 0x0000003c
+#define IPA_COMP_SW_RESET_RMSK 0x1
+#define IPA_COMP_SW_RESET_SW_RESET_BMSK 0x1
+#define IPA_COMP_SW_RESET_SW_RESET_SHFT 0x0
+
+#define IPA_CLKON_CFG_OFST 0x00000040
+#define IPA_CLKON_CFG_RMSK 0xf
+#define IPA_CLKON_CFG_CGC_OPEN_MISC_BMSK 0x8
+#define IPA_CLKON_CFG_CGC_OPEN_MISC_SHFT 0x3
+#define IPA_CLKON_CFG_CGC_OPEN_TX_BMSK 0x4
+#define IPA_CLKON_CFG_CGC_OPEN_TX_SHFT 0x2
+#define IPA_CLKON_CFG_CGC_OPEN_PROC_BMSK 0x2
+#define IPA_CLKON_CFG_CGC_OPEN_PROC_SHFT 0x1
+#define IPA_CLKON_CFG_CGC_OPEN_RX_BMSK 0x1
+#define IPA_CLKON_CFG_CGC_OPEN_RX_SHFT 0x0
+
+#define IPA_HEAD_OF_LINE_BLOCK_EN_OFST 0x00000044
+#define IPA_HEAD_OF_LINE_BLOCK_EN_RMSK 0x1
+#define IPA_HEAD_OF_LINE_BLOCK_EN_EN_BMSK 0x1
+#define IPA_HEAD_OF_LINE_BLOCK_EN_EN_SHFT 0x0
+
+#define IPA_HEAD_OF_LINE_BLOCK_TIMER_OFST 0x00000048
+#define IPA_HEAD_OF_LINE_BLOCK_TIMER_RMSK 0x1ff
+#define IPA_HEAD_OF_LINE_BLOCK_TIMER_TIMER_BMSK 0x1ff
+#define IPA_HEAD_OF_LINE_BLOCK_TIMER_TIMER_SHFT 0x0
+
+#define IPA_ROUTE_OFST 0x0000004c
+#define IPA_ROUTE_RMSK 0x1ffff
+#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x1ff80
+#define IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x7
+#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x40
+#define IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x6
+#define IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0x3e
+#define IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1
+#define IPA_ROUTE_ROUTE_DIS_BMSK 0x1
+#define IPA_ROUTE_ROUTE_DIS_SHFT 0x0
+
+#define IPA_FILTER_OFST 0x00000050
+#define IPA_FILTER_RMSK 0x1
+#define IPA_FILTER_FILTER_EN_BMSK 0x1
+#define IPA_FILTER_FILTER_EN_SHFT 0x0
+
+#define IPA_MASTER_PRIORITY_OFST 0x00000054
+#define IPA_MASTER_PRIORITY_RMSK 0xffffffff
+#define IPA_MASTER_PRIORITY_MASTER_7_WR_BMSK 0xc0000000
+#define IPA_MASTER_PRIORITY_MASTER_7_WR_SHFT 0x1e
+#define IPA_MASTER_PRIORITY_MASTER_7_RD_BMSK 0x30000000
+#define IPA_MASTER_PRIORITY_MASTER_7_RD_SHFT 0x1c
+#define IPA_MASTER_PRIORITY_MASTER_6_WR_BMSK 0xc000000
+#define IPA_MASTER_PRIORITY_MASTER_6_WR_SHFT 0x1a
+#define IPA_MASTER_PRIORITY_MASTER_6_RD_BMSK 0x3000000
+#define IPA_MASTER_PRIORITY_MASTER_6_RD_SHFT 0x18
+#define IPA_MASTER_PRIORITY_MASTER_5_WR_BMSK 0xc00000
+#define IPA_MASTER_PRIORITY_MASTER_5_WR_SHFT 0x16
+#define IPA_MASTER_PRIORITY_MASTER_5_RD_BMSK 0x300000
+#define IPA_MASTER_PRIORITY_MASTER_5_RD_SHFT 0x14
+#define IPA_MASTER_PRIORITY_MASTER_4_WR_BMSK 0xc0000
+#define IPA_MASTER_PRIORITY_MASTER_4_WR_SHFT 0x12
+#define IPA_MASTER_PRIORITY_MASTER_4_RD_BMSK 0x30000
+#define IPA_MASTER_PRIORITY_MASTER_4_RD_SHFT 0x10
+#define IPA_MASTER_PRIORITY_MASTER_3_WR_BMSK 0xc000
+#define IPA_MASTER_PRIORITY_MASTER_3_WR_SHFT 0xe
+#define IPA_MASTER_PRIORITY_MASTER_3_RD_BMSK 0x3000
+#define IPA_MASTER_PRIORITY_MASTER_3_RD_SHFT 0xc
+#define IPA_MASTER_PRIORITY_MASTER_2_WR_BMSK 0xc00
+#define IPA_MASTER_PRIORITY_MASTER_2_WR_SHFT 0xa
+#define IPA_MASTER_PRIORITY_MASTER_2_RD_BMSK 0x300
+#define IPA_MASTER_PRIORITY_MASTER_2_RD_SHFT 0x8
+#define IPA_MASTER_PRIORITY_MASTER_1_WR_BMSK 0xc0
+#define IPA_MASTER_PRIORITY_MASTER_1_WR_SHFT 0x6
+#define IPA_MASTER_PRIORITY_MASTER_1_RD_BMSK 0x30
+#define IPA_MASTER_PRIORITY_MASTER_1_RD_SHFT 0x4
+#define IPA_MASTER_PRIORITY_MASTER_0_WR_BMSK 0xc
+#define IPA_MASTER_PRIORITY_MASTER_0_WR_SHFT 0x2
+#define IPA_MASTER_PRIORITY_MASTER_0_RD_BMSK 0x3
+#define IPA_MASTER_PRIORITY_MASTER_0_RD_SHFT 0x0
+
+#define IPA_SHARED_MEM_SIZE_OFST 0x00000058
+#define IPA_SHARED_MEM_SIZE_RMSK 0x1fff
+#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_BMSK 0x1fff
+#define IPA_SHARED_MEM_SIZE_SHARED_MEM_SIZE_SHFT 0x0
+
+#define IPA_NAT_TIMER_OFST 0x0000005c
+#define IPA_NAT_TIMER_RMSK 0xffffff
+#define IPA_NAT_TIMER_NAT_TIMER_BMSK 0xffffff
+#define IPA_NAT_TIMER_NAT_TIMER_SHFT 0x0
+
+#define IPA_NAT_TIMER_RESET_OFST 0x00000060
+#define IPA_NAT_TIMER_RESET_RMSK 0x1
+#define IPA_NAT_TIMER_RESET_NAT_TIMER_RESET_BMSK 0x1
+#define IPA_NAT_TIMER_RESET_NAT_TIMER_RESET_SHFT 0x0
+
+#define IPA_ENDP_INIT_NAT_n_OFST(n) (0x00000080 + 0x4 * (n))
+#define IPA_ENDP_INIT_NAT_n_RMSK 0x3
+#define IPA_ENDP_INIT_NAT_n_MAXn 19
+#define IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3
+#define IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0
+
+#define IPA_ENDP_INIT_HDR_n_OFST(n) (0x000000e0 + 0x4 * (n))
+#define IPA_ENDP_INIT_HDR_n_RMSK 0x7ffffff
+#define IPA_ENDP_INIT_HDR_n_MAXn 19
+#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000
+#define IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13
+#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000
+#define IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40
+#define IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6
+#define IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f
+#define IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0
+
+#define IPA_ENDP_INIT_MODE_n_OFST(n) (0x00000140 + 0x4 * (n))
+#define IPA_ENDP_INIT_MODE_n_RMSK 0x7f
+#define IPA_ENDP_INIT_MODE_n_MAXn 19
+#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0x7c
+#define IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x2
+#define IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x3
+#define IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0
+
+#define IPA_ENDP_INIT_AGGR_n_OFST(n) (0x000001a0 + 0x4 * (n))
+#define IPA_ENDP_INIT_AGGR_n_RMSK 0x7fff
+#define IPA_ENDP_INIT_AGGR_n_MAXn 19
+#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x7c00
+#define IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xa
+#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x3e0
+#define IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5
+#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c
+#define IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2
+#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3
+#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0
+
+#define IPA_ENDP_INIT_ROUTE_n_OFST(n) (0x00000200 + 0x4 * (n))
+#define IPA_ENDP_INIT_ROUTE_n_RMSK 0x1f
+#define IPA_ENDP_INIT_ROUTE_n_MAXn 19
+#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f
+#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_SHFT 0x0
+
+#define IPA_AGGREGATION_SPARE_REG_1_OFST 0x00002090
+#define IPA_AGGREGATION_SPARE_REG_1_RMSK 0xffffffff
+#define IPA_AGGREGATION_SPARE_REG_1_GENERAL_CONFIG_BMSK 0xffffffff
+#define IPA_AGGREGATION_SPARE_REG_1_GENERAL_CONFIG_SHFT 0x0
+
+#define IPA_AGGREGATION_SPARE_REG_2_OFST 0x00002094
+#define IPA_AGGREGATION_SPARE_REG_2_RMSK 0xffffffff
+#define IPA_AGGREGATION_SPARE_REG_2_GENERAL_CONFIG_BMSK 0xffffffff
+#define IPA_AGGREGATION_SPARE_REG_2_GENERAL_CONFIG_SHFT 0x0
+
+#define IPA_AGGREGATION_MODE_MSK 0x1
+#define IPA_AGGREGATION_MODE_SHFT 31
+#define IPA_AGGREGATION_MODE_BMSK 0x7fffffff
+#define IPA_AGGREGATION_QCNCM_SIG0_SHFT 16
+#define IPA_AGGREGATION_QCNCM_SIG1_SHFT 8
+#define IPA_AGGREGATION_QCNCM_SIG_BMSK 0xff000000
+#define IPA_AGGREGATION_SINGLE_NDP_MSK 0x1
+#define IPA_AGGREGATION_SINGLE_NDP_BMSK 0xfffffffe
+
+#define IPA_SRAM_DIRECT_ACCESS_n_OFST(n) (0x00004000 + 0x4 * (n))
+#define IPA_SRAM_DIRECT_ACCESS_n_RMSK 0xffffffff
+#define IPA_SRAM_DIRECT_ACCESS_n_MAXn 2047
+#define IPA_SRAM_DIRECT_ACCESS_n_DATA_WORD_BMSK 0xffffffff
+#define IPA_SRAM_DIRECT_ACCESS_n_DATA_WORD_SHFT 0x0
+
+#endif /* __IPA_REG_H__ */
diff --git a/drivers/platform/msm/ipa/ipa_rt.c b/drivers/platform/msm/ipa/ipa_rt.c
new file mode 100644
index 0000000..c69e1fb
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_rt.c
@@ -0,0 +1,964 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include "ipa_i.h"
+
+#define IPA_RT_TABLE_INDEX_NOT_FOUND (-1)
+#define IPA_RT_TABLE_WORD_SIZE (4)
+#define IPA_RT_INDEX_BITMAP_SIZE (32)
+#define IPA_RT_TABLE_MEMORY_ALLIGNMENT (127)
+#define IPA_RT_ENTRY_MEMORY_ALLIGNMENT (3)
+#define IPA_RT_BIT_MASK (0x1)
+#define IPA_RT_STATUS_OF_ADD_FAILED (-1)
+#define IPA_RT_STATUS_OF_DEL_FAILED (-1)
+
+/**
+ * ipa_generate_rt_hw_rule() - generates the routing hardware rule
+ * @ip: the ip address family type
+ * @entry: routing entry
+ * @buf: output buffer, buf == NULL means
+ * caller wants to know the size of the rule as seen
+ * by HW so they did not pass a valid buffer, we will use a
+ * scratch buffer instead.
+ * With this scheme we are going to
+ * generate the rule twice, once to know size using scratch
+ * buffer and second to write the rule to the actual caller
+ * supplied buffer which is of required size
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * caller needs to hold any needed locks to ensure integrity
+ *
+ */
+static int ipa_generate_rt_hw_rule(enum ipa_ip_type ip,
+ struct ipa_rt_entry *entry, u8 *buf)
+{
+ struct ipa_rt_rule_hw_hdr *rule_hdr;
+ const struct ipa_rt_rule *rule =
+ (const struct ipa_rt_rule *)&entry->rule;
+ u16 en_rule = 0;
+ u8 tmp[IPA_RT_FLT_HW_RULE_BUF_SIZE];
+ u8 *start;
+ int pipe_idx;
+
+ memset(tmp, 0, IPA_RT_FLT_HW_RULE_BUF_SIZE);
+ if (buf == NULL)
+ buf = tmp;
+
+ start = buf;
+ rule_hdr = (struct ipa_rt_rule_hw_hdr *)buf;
+ pipe_idx = ipa_get_ep_mapping(ipa_ctx->mode,
+ entry->rule.dst);
+ if (pipe_idx == -1) {
+ IPAERR("Wrong destination pipe specified in RT rule\n");
+ WARN_ON(1);
+ return -EPERM;
+ }
+ rule_hdr->u.hdr.pipe_dest_idx = pipe_idx;
+ rule_hdr->u.hdr.system = !ipa_ctx->hdr_tbl_lcl;
+ if (entry->hdr)
+ rule_hdr->u.hdr.hdr_offset =
+ entry->hdr->offset_entry->offset >> 2;
+ else
+ rule_hdr->u.hdr.hdr_offset = 0;
+
+ buf += sizeof(struct ipa_rt_rule_hw_hdr);
+ if (ipa_generate_hw_rule(ip, &rule->attrib, &buf, &en_rule)) {
+ IPAERR("fail to generate hw rule\n");
+ return -EPERM;
+ }
+
+ IPADBG("en_rule 0x%x\n", en_rule);
+
+ rule_hdr->u.hdr.en_rule = en_rule;
+ ipa_write_32(rule_hdr->u.word, (u8 *)rule_hdr);
+
+ if (entry->hw_len == 0) {
+ entry->hw_len = buf - start;
+ } else if (entry->hw_len != (buf - start)) {
+ IPAERR(
+ "hw_len differs b/w passes passed=0x%x calc=0x%x\n",
+ entry->hw_len,
+ (buf - start));
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/**
+ * ipa_get_rt_hw_tbl_size() - returns the size of HW routing table
+ * @ip: the ip address family type
+ * @hdr_sz: header size
+ * @max_rt_idx: maximal index
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * caller needs to hold any needed locks to ensure integrity
+ *
+ * the MSB set in rt_idx_bitmap indicates the size of hdr of routing tbl
+ */
+static int ipa_get_rt_hw_tbl_size(enum ipa_ip_type ip, u32 *hdr_sz,
+ int *max_rt_idx)
+{
+ struct ipa_rt_tbl_set *set;
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_entry *entry;
+ u32 total_sz = 0;
+ u32 tbl_sz;
+ u32 bitmap = ipa_ctx->rt_idx_bitmap[ip];
+ int highest_bit_set = IPA_RT_TABLE_INDEX_NOT_FOUND;
+ int i;
+
+ *hdr_sz = 0;
+ set = &ipa_ctx->rt_tbl_set[ip];
+
+ for (i = 0; i < IPA_RT_INDEX_BITMAP_SIZE; i++) {
+ if (bitmap & IPA_RT_BIT_MASK)
+ highest_bit_set = i;
+ bitmap >>= 1;
+ }
+
+ *max_rt_idx = highest_bit_set;
+ if (highest_bit_set == IPA_RT_TABLE_INDEX_NOT_FOUND) {
+ IPAERR("no rt tbls present\n");
+ total_sz = IPA_RT_TABLE_WORD_SIZE;
+ *hdr_sz = IPA_RT_TABLE_WORD_SIZE;
+ return total_sz;
+ }
+
+ *hdr_sz = (highest_bit_set + 1) * IPA_RT_TABLE_WORD_SIZE;
+ total_sz += *hdr_sz;
+ list_for_each_entry(tbl, &set->head_rt_tbl_list, link) {
+ tbl_sz = 0;
+ list_for_each_entry(entry, &tbl->head_rt_rule_list, link) {
+ if (ipa_generate_rt_hw_rule(ip, entry, NULL)) {
+ IPAERR("failed to find HW RT rule size\n");
+ return -EPERM;
+ }
+ tbl_sz += entry->hw_len;
+ }
+
+ if (tbl_sz)
+ tbl->sz = tbl_sz + IPA_RT_TABLE_WORD_SIZE;
+
+ if (tbl->in_sys)
+ continue;
+
+ if (tbl_sz) {
+ /* add the terminator */
+ total_sz += (tbl_sz + IPA_RT_TABLE_WORD_SIZE);
+ /* every rule-set should start at word boundary */
+ total_sz = (total_sz + IPA_RT_ENTRY_MEMORY_ALLIGNMENT) &
+ ~IPA_RT_ENTRY_MEMORY_ALLIGNMENT;
+ }
+ }
+
+ IPADBG("RT HW TBL SZ %d HDR SZ %d IP %d\n", total_sz, *hdr_sz, ip);
+
+ return total_sz;
+}
+
+/**
+ * ipa_generate_rt_hw_tbl() - generates the routing hardware table
+ * @ip: [in] the ip address family type
+ * @mem: [out] buffer to put the filtering table
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_generate_rt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem)
+{
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_entry *entry;
+ struct ipa_rt_tbl_set *set;
+ u32 hdr_sz;
+ u32 offset;
+ u8 *hdr;
+ u8 *body;
+ u8 *base;
+ struct ipa_mem_buffer rt_tbl_mem;
+ u8 *rt_tbl_mem_body;
+ int max_rt_idx;
+ int i;
+
+ mem->size = ipa_get_rt_hw_tbl_size(ip, &hdr_sz, &max_rt_idx);
+ mem->size = (mem->size + IPA_RT_TABLE_MEMORY_ALLIGNMENT) &
+ ~IPA_RT_TABLE_MEMORY_ALLIGNMENT;
+
+ if (mem->size == 0) {
+ IPAERR("rt tbl empty ip=%d\n", ip);
+ goto error;
+ }
+ mem->base = dma_alloc_coherent(NULL, mem->size, &mem->phys_base,
+ GFP_KERNEL);
+ if (!mem->base) {
+ IPAERR("fail to alloc DMA buff of size %d\n", mem->size);
+ goto error;
+ }
+
+ memset(mem->base, 0, mem->size);
+
+ /* build the rt tbl in the DMA buffer to submit to IPA HW */
+ base = hdr = (u8 *)mem->base;
+ body = base + hdr_sz;
+
+ /* setup all indices to point to the empty sys rt tbl */
+ for (i = 0; i <= max_rt_idx; i++)
+ ipa_write_32(ipa_ctx->empty_rt_tbl_mem.phys_base,
+ hdr + (i * IPA_RT_TABLE_WORD_SIZE));
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+ list_for_each_entry(tbl, &set->head_rt_tbl_list, link) {
+ offset = body - base;
+ if (offset & IPA_RT_ENTRY_MEMORY_ALLIGNMENT) {
+ IPAERR("offset is not word multiple %d\n", offset);
+ goto proc_err;
+ }
+
+ if (!tbl->in_sys) {
+ /* convert offset to words from bytes */
+ offset &= ~IPA_RT_ENTRY_MEMORY_ALLIGNMENT;
+ /* rule is at an offset from base */
+ offset |= IPA_RT_BIT_MASK;
+
+ /* update the hdr at the right index */
+ ipa_write_32(offset, hdr +
+ (tbl->idx * IPA_RT_TABLE_WORD_SIZE));
+
+ /* generate the rule-set */
+ list_for_each_entry(entry, &tbl->head_rt_rule_list,
+ link) {
+ if (ipa_generate_rt_hw_rule(ip, entry, body)) {
+ IPAERR("failed to gen HW RT rule\n");
+ goto proc_err;
+ }
+ body += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ body = ipa_write_32(0, body);
+ if ((u32)body & IPA_RT_ENTRY_MEMORY_ALLIGNMENT)
+ /* advance body to next word boundary */
+ body = body + (IPA_RT_TABLE_WORD_SIZE -
+ ((u32)body &
+ IPA_RT_ENTRY_MEMORY_ALLIGNMENT));
+ } else {
+ WARN_ON(tbl->sz == 0);
+ /* allocate memory for the RT tbl */
+ rt_tbl_mem.size = tbl->sz;
+ rt_tbl_mem.base =
+ dma_alloc_coherent(NULL, rt_tbl_mem.size,
+ &rt_tbl_mem.phys_base, GFP_KERNEL);
+ if (!rt_tbl_mem.base) {
+ IPAERR("fail to alloc DMA buff of size %d\n",
+ rt_tbl_mem.size);
+ WARN_ON(1);
+ goto proc_err;
+ }
+
+ WARN_ON(rt_tbl_mem.phys_base &
+ IPA_RT_ENTRY_MEMORY_ALLIGNMENT);
+ rt_tbl_mem_body = rt_tbl_mem.base;
+ memset(rt_tbl_mem.base, 0, rt_tbl_mem.size);
+ /* update the hdr at the right index */
+ ipa_write_32(rt_tbl_mem.phys_base,
+ hdr + (tbl->idx *
+ IPA_RT_TABLE_WORD_SIZE));
+ /* generate the rule-set */
+ list_for_each_entry(entry, &tbl->head_rt_rule_list,
+ link) {
+ if (ipa_generate_rt_hw_rule(ip, entry,
+ rt_tbl_mem_body)) {
+ IPAERR("failed to gen HW RT rule\n");
+ WARN_ON(1);
+ goto rt_table_mem_alloc_failed;
+ }
+ rt_tbl_mem_body += entry->hw_len;
+ }
+
+ /* write the rule-set terminator */
+ rt_tbl_mem_body = ipa_write_32(0, rt_tbl_mem_body);
+
+ if (tbl->curr_mem.phys_base) {
+ WARN_ON(tbl->prev_mem.phys_base);
+ tbl->prev_mem = tbl->curr_mem;
+ }
+ tbl->curr_mem = rt_tbl_mem;
+ }
+ }
+
+ return 0;
+
+rt_table_mem_alloc_failed:
+ dma_free_coherent(NULL, rt_tbl_mem.size,
+ rt_tbl_mem.base, rt_tbl_mem.phys_base);
+proc_err:
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+error:
+ return -EPERM;
+}
+
+static void __ipa_reap_sys_rt_tbls(enum ipa_ip_type ip)
+{
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_tbl *next;
+ struct ipa_rt_tbl_set *set;
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+ list_for_each_entry(tbl, &set->head_rt_tbl_list, link) {
+ if (tbl->prev_mem.phys_base) {
+ IPADBG("reaping rt tbl name=%s ip=%d\n", tbl->name, ip);
+ dma_free_coherent(NULL, tbl->prev_mem.size,
+ tbl->prev_mem.base,
+ tbl->prev_mem.phys_base);
+ memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem));
+ }
+ }
+
+ set = &ipa_ctx->reap_rt_tbl_set[ip];
+ list_for_each_entry_safe(tbl, next, &set->head_rt_tbl_list, link) {
+ list_del(&tbl->link);
+ WARN_ON(tbl->prev_mem.phys_base != 0);
+ if (tbl->curr_mem.phys_base) {
+ IPADBG("reaping sys rt tbl name=%s ip=%d\n", tbl->name,
+ ip);
+ dma_free_coherent(NULL, tbl->curr_mem.size,
+ tbl->curr_mem.base,
+ tbl->curr_mem.phys_base);
+ kmem_cache_free(ipa_ctx->rt_tbl_cache, tbl);
+ }
+ }
+}
+
+static int __ipa_commit_rt(enum ipa_ip_type ip)
+{
+ struct ipa_desc desc = { 0 };
+ struct ipa_mem_buffer *mem;
+ void *cmd;
+ struct ipa_ip_v4_routing_init *v4;
+ struct ipa_ip_v6_routing_init *v6;
+ u16 avail;
+ u16 size;
+
+ mem = kmalloc(sizeof(struct ipa_mem_buffer), GFP_KERNEL);
+ if (!mem) {
+ IPAERR("failed to alloc memory object\n");
+ goto fail_alloc_mem;
+ }
+
+ if (ip == IPA_IP_v4) {
+ avail = IPA_RAM_V4_RT_SIZE;
+ size = sizeof(struct ipa_ip_v4_routing_init);
+ } else {
+ avail = IPA_RAM_V6_RT_SIZE;
+ size = sizeof(struct ipa_ip_v6_routing_init);
+ }
+ cmd = kmalloc(size, GFP_KERNEL);
+ if (!cmd) {
+ IPAERR("failed to alloc immediate command object\n");
+ goto fail_alloc_cmd;
+ }
+
+ if (ipa_generate_rt_hw_tbl(ip, mem)) {
+ IPAERR("fail to generate RT HW TBL ip %d\n", ip);
+ goto fail_hw_tbl_gen;
+ }
+
+ if (mem->size > avail) {
+ IPAERR("tbl too big, needed %d avail %d\n", mem->size, avail);
+ goto fail_hw_tbl_gen;
+ }
+
+ if (ip == IPA_IP_v4) {
+ v4 = (struct ipa_ip_v4_routing_init *)cmd;
+ desc.opcode = IPA_IP_V4_ROUTING_INIT;
+ v4->ipv4_rules_addr = mem->phys_base;
+ v4->size_ipv4_rules = mem->size;
+ v4->ipv4_addr = IPA_RAM_V4_RT_OFST;
+ } else {
+ v6 = (struct ipa_ip_v6_routing_init *)cmd;
+ desc.opcode = IPA_IP_V6_ROUTING_INIT;
+ v6->ipv6_rules_addr = mem->phys_base;
+ v6->size_ipv6_rules = mem->size;
+ v6->ipv6_addr = IPA_RAM_V6_RT_OFST;
+ }
+
+ desc.pyld = cmd;
+ desc.len = size;
+ desc.type = IPA_IMM_CMD_DESC;
+ IPA_DUMP_BUFF(mem->base, mem->phys_base, mem->size);
+
+ if (ipa_send_cmd(1, &desc)) {
+ IPAERR("fail to send immediate command\n");
+ goto fail_send_cmd;
+ }
+
+ __ipa_reap_sys_rt_tbls(ip);
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+ kfree(cmd);
+ kfree(mem);
+
+ return 0;
+
+fail_send_cmd:
+ if (mem->phys_base)
+ dma_free_coherent(NULL, mem->size, mem->base, mem->phys_base);
+fail_hw_tbl_gen:
+ kfree(cmd);
+fail_alloc_cmd:
+ kfree(mem);
+fail_alloc_mem:
+ return -EPERM;
+}
+
+/**
+ * __ipa_find_rt_tbl() - find the routing table
+ * which name is given as parameter
+ * @ip: [in] the ip address family type of the wanted routing table
+ * @name: [in] the name of the wanted routing table
+ *
+ * Returns: the routing table which name is given as parameter, or NULL if it
+ * doesn't exist
+ */
+struct ipa_rt_tbl *__ipa_find_rt_tbl(enum ipa_ip_type ip, const char *name)
+{
+ struct ipa_rt_tbl *entry;
+ struct ipa_rt_tbl_set *set;
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+ list_for_each_entry(entry, &set->head_rt_tbl_list, link) {
+ if (!strncmp(name, entry->name, IPA_RESOURCE_NAME_MAX))
+ return entry;
+ }
+
+ return NULL;
+}
+
+static struct ipa_rt_tbl *__ipa_add_rt_tbl(enum ipa_ip_type ip,
+ const char *name)
+{
+ struct ipa_rt_tbl *entry;
+ struct ipa_rt_tbl_set *set;
+ struct ipa_tree_node *node;
+ int i;
+
+ node = kmem_cache_zalloc(ipa_ctx->tree_node_cache, GFP_KERNEL);
+ if (!node) {
+ IPAERR("failed to alloc tree node object\n");
+ goto node_alloc_fail;
+ }
+
+ if (ip >= IPA_IP_MAX || name == NULL) {
+ IPAERR("bad parm\n");
+ goto error;
+ }
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+ /* check if this table exists */
+ entry = __ipa_find_rt_tbl(ip, name);
+ if (!entry) {
+ entry = kmem_cache_zalloc(ipa_ctx->rt_tbl_cache, GFP_KERNEL);
+ if (!entry) {
+ IPAERR("failed to alloc RT tbl object\n");
+ goto error;
+ }
+ /* find a routing tbl index */
+ for (i = 0; i < IPA_RT_INDEX_BITMAP_SIZE; i++) {
+ if (!test_bit(i, &ipa_ctx->rt_idx_bitmap[ip])) {
+ entry->idx = i;
+ set_bit(i, &ipa_ctx->rt_idx_bitmap[ip]);
+ break;
+ }
+ }
+ if (i == IPA_RT_INDEX_BITMAP_SIZE) {
+ IPAERR("not free RT tbl indices left\n");
+ goto fail_rt_idx_alloc;
+ }
+
+ INIT_LIST_HEAD(&entry->head_rt_rule_list);
+ INIT_LIST_HEAD(&entry->link);
+ strlcpy(entry->name, name, IPA_RESOURCE_NAME_MAX);
+ entry->set = set;
+ entry->cookie = IPA_COOKIE;
+ entry->in_sys = (ip == IPA_IP_v4) ?
+ !ipa_ctx->ip4_rt_tbl_lcl : !ipa_ctx->ip6_rt_tbl_lcl;
+ set->tbl_cnt++;
+ list_add(&entry->link, &set->head_rt_tbl_list);
+
+ IPADBG("add rt tbl idx=%d tbl_cnt=%d ip=%d\n", entry->idx,
+ set->tbl_cnt, ip);
+
+ node->hdl = (u32)entry;
+ if (ipa_insert(&ipa_ctx->rt_tbl_hdl_tree, node)) {
+ IPAERR("failed to add to tree\n");
+ WARN_ON(1);
+ }
+ }
+
+ return entry;
+
+fail_rt_idx_alloc:
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->rt_tbl_cache, entry);
+error:
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+node_alloc_fail:
+ return NULL;
+}
+
+static int __ipa_del_rt_tbl(struct ipa_rt_tbl *entry)
+{
+ struct ipa_tree_node *node;
+ enum ipa_ip_type ip = IPA_IP_MAX;
+
+ if (entry == NULL || (entry->cookie != IPA_COOKIE)) {
+ IPAERR("bad parms\n");
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->rt_tbl_hdl_tree, (u32)entry);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+ return -EPERM;
+ }
+
+ if (entry->set == &ipa_ctx->rt_tbl_set[IPA_IP_v4])
+ ip = IPA_IP_v4;
+ else if (entry->set == &ipa_ctx->rt_tbl_set[IPA_IP_v6])
+ ip = IPA_IP_v6;
+ else
+ WARN_ON(1);
+
+ if (!entry->in_sys) {
+ list_del(&entry->link);
+ clear_bit(entry->idx, &ipa_ctx->rt_idx_bitmap[ip]);
+ entry->set->tbl_cnt--;
+ IPADBG("del rt tbl_idx=%d tbl_cnt=%d\n", entry->idx,
+ entry->set->tbl_cnt);
+ kmem_cache_free(ipa_ctx->rt_tbl_cache, entry);
+ } else {
+ list_move(&entry->link,
+ &ipa_ctx->reap_rt_tbl_set[ip].head_rt_tbl_list);
+ clear_bit(entry->idx, &ipa_ctx->rt_idx_bitmap[ip]);
+ entry->set->tbl_cnt--;
+ IPADBG("del sys rt tbl_idx=%d tbl_cnt=%d\n", entry->idx,
+ entry->set->tbl_cnt);
+ }
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->rt_tbl_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+
+ return 0;
+}
+
+static int __ipa_add_rt_rule(enum ipa_ip_type ip, const char *name,
+ const struct ipa_rt_rule *rule, u8 at_rear, u32 *rule_hdl)
+{
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_entry *entry;
+ struct ipa_tree_node *node;
+
+ if (rule->hdr_hdl &&
+ ((ipa_search(&ipa_ctx->hdr_hdl_tree, rule->hdr_hdl) == NULL) ||
+ ((struct ipa_hdr_entry *)rule->hdr_hdl)->cookie != IPA_COOKIE)) {
+ IPAERR("rt rule does not point to valid hdr\n");
+ goto error;
+ }
+
+ node = kmem_cache_zalloc(ipa_ctx->tree_node_cache, GFP_KERNEL);
+ if (!node) {
+ IPAERR("failed to alloc tree node object\n");
+ goto error;
+ }
+
+ tbl = __ipa_add_rt_tbl(ip, name);
+ if (tbl == NULL || (tbl->cookie != IPA_COOKIE)) {
+ IPAERR("bad params\n");
+ goto fail_rt_tbl_sanity;
+ }
+ /*
+ * do not allow any rules to be added at end of the "default" routing
+ * tables
+ */
+ if (!strncmp(tbl->name, IPA_DFLT_RT_TBL_NAME, IPA_RESOURCE_NAME_MAX) &&
+ (tbl->rule_cnt > 0) && (at_rear != 0)) {
+ IPAERR("cannot add rule at end of tbl rule_cnt=%d at_rear=%d\n",
+ tbl->rule_cnt, at_rear);
+ goto fail_rt_tbl_sanity;
+ }
+
+ entry = kmem_cache_zalloc(ipa_ctx->rt_rule_cache, GFP_KERNEL);
+ if (!entry) {
+ IPAERR("failed to alloc RT rule object\n");
+ goto fail_rt_tbl_sanity;
+ }
+ INIT_LIST_HEAD(&entry->link);
+ entry->cookie = IPA_COOKIE;
+ entry->rule = *rule;
+ entry->tbl = tbl;
+ entry->hdr = (struct ipa_hdr_entry *)rule->hdr_hdl;
+ if (at_rear)
+ list_add_tail(&entry->link, &tbl->head_rt_rule_list);
+ else
+ list_add(&entry->link, &tbl->head_rt_rule_list);
+ tbl->rule_cnt++;
+ if (entry->hdr)
+ entry->hdr->ref_cnt++;
+ IPADBG("add rt rule tbl_idx=%d rule_cnt=%d\n", tbl->idx, tbl->rule_cnt);
+ *rule_hdl = (u32)entry;
+
+ node->hdl = *rule_hdl;
+ if (ipa_insert(&ipa_ctx->rt_rule_hdl_tree, node)) {
+ IPAERR("failed to add to tree\n");
+ WARN_ON(1);
+ goto ipa_insert_failed;
+ }
+
+ return 0;
+
+ipa_insert_failed:
+ list_del(&entry->link);
+ kmem_cache_free(ipa_ctx->rt_rule_cache, entry);
+fail_rt_tbl_sanity:
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+error:
+ return -EPERM;
+}
+
+/**
+ * ipa_add_rt_rule() - Add the specified routing rules to SW and optionally
+ * commit to IPA HW
+ * @rules: [inout] set of routing rules to add
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_add_rt_rule(struct ipa_ioc_add_rt_rule *rules)
+{
+ int i;
+ int ret;
+
+ if (rules == NULL || rules->num_rules == 0 || rules->ip >= IPA_IP_MAX) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < rules->num_rules; i++) {
+ if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name,
+ &rules->rules[i].rule,
+ rules->rules[i].at_rear,
+ &rules->rules[i].rt_rule_hdl)) {
+ IPAERR("failed to add rt rule %d\n", i);
+ rules->rules[i].status = IPA_RT_STATUS_OF_ADD_FAILED;
+ } else {
+ rules->rules[i].status = 0;
+ }
+ }
+
+ if (rules->commit)
+ if (__ipa_commit_rt(rules->ip)) {
+ ret = -EPERM;
+ goto bail;
+ }
+
+ ret = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_add_rt_rule);
+
+static int __ipa_del_rt_rule(u32 rule_hdl)
+{
+ struct ipa_rt_entry *entry = (struct ipa_rt_entry *)rule_hdl;
+ struct ipa_tree_node *node;
+
+ if (entry == NULL || (entry->cookie != IPA_COOKIE)) {
+ IPAERR("bad params\n");
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->rt_rule_hdl_tree, rule_hdl);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+ return -EPERM;
+ }
+
+ if (entry->hdr)
+ entry->hdr->ref_cnt--;
+ list_del(&entry->link);
+ entry->tbl->rule_cnt--;
+ IPADBG("del rt rule tbl_idx=%d rule_cnt=%d\n", entry->tbl->idx,
+ entry->tbl->rule_cnt);
+ if (entry->tbl->rule_cnt == 0 && entry->tbl->ref_cnt == 0) {
+ if (__ipa_del_rt_tbl(entry->tbl))
+ IPAERR("fail to del RT tbl\n");
+ }
+ entry->cookie = 0;
+ kmem_cache_free(ipa_ctx->rt_rule_cache, entry);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->rt_rule_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+
+ return 0;
+}
+
+/**
+ * ipa_del_rt_rule() - Remove the specified routing rules to SW and optionally
+ * commit to IPA HW
+ * @hdls: [inout] set of routing rules to delete
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_del_rt_rule(struct ipa_ioc_del_rt_rule *hdls)
+{
+ int i;
+ int ret;
+
+ if (hdls == NULL || hdls->num_hdls == 0 || hdls->ip >= IPA_IP_MAX) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&ipa_ctx->lock);
+ for (i = 0; i < hdls->num_hdls; i++) {
+ if (__ipa_del_rt_rule(hdls->hdl[i].hdl)) {
+ IPAERR("failed to del rt rule %i\n", i);
+ hdls->hdl[i].status = IPA_RT_STATUS_OF_DEL_FAILED;
+ } else {
+ hdls->hdl[i].status = 0;
+ }
+ }
+
+ if (hdls->commit)
+ if (__ipa_commit_rt(hdls->ip)) {
+ ret = -EPERM;
+ goto bail;
+ }
+
+ ret = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_del_rt_rule);
+
+/**
+ * ipa_commit_rt_rule() - Commit the current SW routing table of specified type
+ * to IPA HW
+ * @ip: The family of routing tables
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_commit_rt(enum ipa_ip_type ip)
+{
+ int ret;
+ /*
+ * issue a commit on the filtering module of same IP type since
+ * filtering rules point to routing tables
+ */
+ if (ipa_commit_flt(ip))
+ return -EPERM;
+
+ mutex_lock(&ipa_ctx->lock);
+ if (__ipa_commit_rt(ip)) {
+ ret = -EPERM;
+ goto bail;
+ }
+
+ ret = 0;
+bail:
+ mutex_unlock(&ipa_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_commit_rt);
+
+/**
+ * ipa_reset_rt() - reset the current SW routing table of specified type
+ * (does not commit to HW)
+ * @ip: The family of routing tables
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_reset_rt(enum ipa_ip_type ip)
+{
+ struct ipa_rt_tbl *tbl;
+ struct ipa_rt_tbl *tbl_next;
+ struct ipa_rt_tbl_set *set;
+ struct ipa_rt_entry *rule;
+ struct ipa_rt_entry *rule_next;
+ struct ipa_tree_node *node;
+ struct ipa_rt_tbl_set *rset;
+
+ /*
+ * issue a reset on the filtering module of same IP type since
+ * filtering rules point to routing tables
+ */
+ if (ipa_reset_flt(ip))
+ IPAERR("fail to reset flt ip=%d\n", ip);
+
+ set = &ipa_ctx->rt_tbl_set[ip];
+ rset = &ipa_ctx->reap_rt_tbl_set[ip];
+ mutex_lock(&ipa_ctx->lock);
+ IPADBG("reset rt ip=%d\n", ip);
+ list_for_each_entry_safe(tbl, tbl_next, &set->head_rt_tbl_list, link) {
+ list_for_each_entry_safe(rule, rule_next,
+ &tbl->head_rt_rule_list, link) {
+ node = ipa_search(&ipa_ctx->rt_rule_hdl_tree,
+ (u32)rule);
+ if (node == NULL)
+ WARN_ON(1);
+
+ /*
+ * for the "default" routing tbl, remove all but the
+ * last rule
+ */
+ if (tbl->idx == 0 && tbl->rule_cnt == 1)
+ continue;
+
+ list_del(&rule->link);
+ tbl->rule_cnt--;
+ if (rule->hdr)
+ rule->hdr->ref_cnt--;
+ rule->cookie = 0;
+ kmem_cache_free(ipa_ctx->rt_rule_cache, rule);
+
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->rt_rule_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+ }
+
+ node = ipa_search(&ipa_ctx->rt_tbl_hdl_tree, (u32)tbl);
+ if (node == NULL)
+ WARN_ON(1);
+
+ /* do not remove the "default" routing tbl which has index 0 */
+ if (tbl->idx != 0) {
+ if (!tbl->in_sys) {
+ list_del(&tbl->link);
+ set->tbl_cnt--;
+ clear_bit(tbl->idx,
+ &ipa_ctx->rt_idx_bitmap[ip]);
+ IPADBG("rst rt tbl_idx=%d tbl_cnt=%d\n",
+ tbl->idx, set->tbl_cnt);
+ kmem_cache_free(ipa_ctx->rt_tbl_cache, tbl);
+ } else {
+ list_move(&tbl->link, &rset->head_rt_tbl_list);
+ clear_bit(tbl->idx,
+ &ipa_ctx->rt_idx_bitmap[ip]);
+ set->tbl_cnt--;
+ IPADBG("rst sys rt tbl_idx=%d tbl_cnt=%d\n",
+ tbl->idx, set->tbl_cnt);
+ }
+ /* remove the handle from the database */
+ rb_erase(&node->node, &ipa_ctx->rt_tbl_hdl_tree);
+ kmem_cache_free(ipa_ctx->tree_node_cache, node);
+ }
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_reset_rt);
+
+/**
+ * ipa_get_rt_tbl() - lookup the specified routing table and return handle if it
+ * exists, if lookup succeeds the routing table ref cnt is increased
+ * @lookup: [inout] routing table to lookup and its handle
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ * Caller should call ipa_put_rt_tbl later if this function succeeds
+ */
+int ipa_get_rt_tbl(struct ipa_ioc_get_rt_tbl *lookup)
+{
+ struct ipa_rt_tbl *entry;
+ int result = -EFAULT;
+
+ if (lookup == NULL || lookup->ip >= IPA_IP_MAX) {
+ IPAERR("bad parm\n");
+ return -EINVAL;
+ }
+ mutex_lock(&ipa_ctx->lock);
+ entry = __ipa_add_rt_tbl(lookup->ip, lookup->name);
+ if (entry && entry->cookie == IPA_COOKIE) {
+ entry->ref_cnt++;
+ lookup->hdl = (uint32_t)entry;
+
+ /* commit for get */
+ if (__ipa_commit_rt(lookup->ip))
+ IPAERR("fail to commit RT tbl\n");
+
+ result = 0;
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return result;
+}
+EXPORT_SYMBOL(ipa_get_rt_tbl);
+
+/**
+ * ipa_put_rt_tbl() - Release the specified routing table handle
+ * @rt_tbl_hdl: [in] the routing table handle to release
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_put_rt_tbl(u32 rt_tbl_hdl)
+{
+ struct ipa_rt_tbl *entry = (struct ipa_rt_tbl *)rt_tbl_hdl;
+ struct ipa_tree_node *node;
+ enum ipa_ip_type ip = IPA_IP_MAX;
+
+ if (entry == NULL || (entry->cookie != IPA_COOKIE) ||
+ entry->ref_cnt == 0) {
+ IPAERR("bad parms\n");
+ return -EINVAL;
+ }
+ node = ipa_search(&ipa_ctx->rt_tbl_hdl_tree, rt_tbl_hdl);
+ if (node == NULL) {
+ IPAERR("lookup failed\n");
+ return -EPERM;
+ }
+
+ if (entry->set == &ipa_ctx->rt_tbl_set[IPA_IP_v4])
+ ip = IPA_IP_v4;
+ else if (entry->set == &ipa_ctx->rt_tbl_set[IPA_IP_v6])
+ ip = IPA_IP_v6;
+ else
+ WARN_ON(1);
+
+ mutex_lock(&ipa_ctx->lock);
+ entry->ref_cnt--;
+ if (entry->ref_cnt == 0 && entry->rule_cnt == 0) {
+ if (__ipa_del_rt_tbl(entry))
+ IPAERR("fail to del RT tbl\n");
+ /* commit for put */
+ if (__ipa_commit_rt(ip))
+ IPAERR("fail to commit RT tbl\n");
+ }
+ mutex_unlock(&ipa_ctx->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_put_rt_tbl);
diff --git a/drivers/platform/msm/ipa/ipa_utils.c b/drivers/platform/msm/ipa/ipa_utils.c
new file mode 100644
index 0000000..d5d5566
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_utils.c
@@ -0,0 +1,1353 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <net/ip.h>
+#include <linux/genalloc.h> /* gen_pool_alloc() */
+#include <linux/io.h>
+#include "ipa_i.h"
+
+static const int ipa_ofst_meq32[] = { IPA_OFFSET_MEQ32_0,
+ IPA_OFFSET_MEQ32_1, -1 };
+static const int ipa_ofst_meq128[] = { IPA_OFFSET_MEQ128_0,
+ IPA_OFFSET_MEQ128_1, -1 };
+static const int ipa_ihl_ofst_rng16[] = { IPA_IHL_OFFSET_RANGE16_0,
+ IPA_IHL_OFFSET_RANGE16_1, -1 };
+static const int ipa_ihl_ofst_meq32[] = { IPA_IHL_OFFSET_MEQ32_0,
+ IPA_IHL_OFFSET_MEQ32_1, -1 };
+
+static const int ep_mapping[IPA_MODE_MAX][IPA_CLIENT_MAX] = {
+ { -1, -1, -1, -1, -1, 11, -1, 8, 6, 2, 1, 5, -1, -1, -1, -1, -1, 10, 9, 7, 3, 4 },
+ { -1, -1, -1, -1, -1, 11, -1, 8, 6, 2, 1, 5, -1, -1, -1, -1, -1, 10, 9, 7, 3, 4 },
+ { 11, 13, 15, 17, 19, -1, -1, 8, 6, 2, 1, 5, 10, 12, 14, 16, 18, -1, 9, 7, 3, 4 },
+ { 19, -1, -1, -1, -1, 11, 15, 8, 6, 2, 1, 5, 14, 16, 17, 18, -1, 10, 9, 7, 3, 4 },
+ { 19, -1, -1, -1, -1, 11, 15, 8, 6, 2, 1, 5, 14, 16, 17, 18, -1, 10, 9, 7, 3, 4 },
+ { 19, -1, -1, -1, -1, 11, 15, 8, 6, 2, 1, 5, 14, 16, 17, 18, -1, 10, 9, 7, 3, 4 },
+};
+
+/**
+ * ipa_cfg_route() - configure IPA route
+ * @route: IPA route
+ *
+ * Return codes:
+ * 0: success
+ */
+int ipa_cfg_route(struct ipa_route *route)
+{
+ ipa_write_reg(ipa_ctx->mmio, IPA_ROUTE_OFST,
+ IPA_SETFIELD(route->route_dis,
+ IPA_ROUTE_ROUTE_DIS_SHFT,
+ IPA_ROUTE_ROUTE_DIS_BMSK) |
+ IPA_SETFIELD(route->route_def_pipe,
+ IPA_ROUTE_ROUTE_DEF_PIPE_SHFT,
+ IPA_ROUTE_ROUTE_DEF_PIPE_BMSK) |
+ IPA_SETFIELD(route->route_def_hdr_table,
+ IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT,
+ IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK) |
+ IPA_SETFIELD(route->route_def_hdr_ofst,
+ IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT,
+ IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK));
+
+ return 0;
+}
+/**
+ * ipa_cfg_filter() - configure filter
+ * @disable: disable value
+ *
+ * Return codes:
+ * 0: success
+ */
+int ipa_cfg_filter(u32 disable)
+{
+ ipa_write_reg(ipa_ctx->mmio, IPA_FILTER_OFST,
+ IPA_SETFIELD(!disable,
+ IPA_FILTER_FILTER_EN_SHFT,
+ IPA_FILTER_FILTER_EN_BMSK));
+ return 0;
+}
+
+/**
+ * ipa_init_hw() - initialize HW
+ *
+ * Return codes:
+ * 0: success
+ */
+int ipa_init_hw(void)
+{
+ u32 ipa_version = 0;
+
+ /* do soft reset of IPA */
+ ipa_write_reg(ipa_ctx->mmio, IPA_COMP_SW_RESET_OFST, 1);
+ ipa_write_reg(ipa_ctx->mmio, IPA_COMP_SW_RESET_OFST, 0);
+
+ /* enable IPA */
+ ipa_write_reg(ipa_ctx->mmio, IPA_COMP_CFG_OFST, 1);
+
+ /* Read IPA version and make sure we have access to the registers */
+ ipa_version = ipa_read_reg(ipa_ctx->mmio, IPA_VERSION_OFST);
+ if (ipa_version == 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/**
+ * ipa_get_ep_mapping() - provide endpoint mapping
+ * @mode: IPA operating mode
+ * @client: client type
+ *
+ * Return value: endpoint mapping
+ */
+int ipa_get_ep_mapping(enum ipa_operating_mode mode,
+ enum ipa_client_type client)
+{
+ return ep_mapping[mode][client];
+}
+
+/**
+ * ipa_write_32() - convert 32 bit value to byte array
+ * @w: 32 bit integer
+ * @dest: byte array
+ *
+ * Return value: converted value
+ */
+u8 *ipa_write_32(u32 w, u8 *dest)
+{
+ *dest++ = (u8)((w) & 0xFF);
+ *dest++ = (u8)((w >> 8) & 0xFF);
+ *dest++ = (u8)((w >> 16) & 0xFF);
+ *dest++ = (u8)((w >> 24) & 0xFF);
+
+ return dest;
+}
+
+/**
+ * ipa_write_16() - convert 16 bit value to byte array
+ * @hw: 16 bit integer
+ * @dest: byte array
+ *
+ * Return value: converted value
+ */
+u8 *ipa_write_16(u16 hw, u8 *dest)
+{
+ *dest++ = (u8)((hw) & 0xFF);
+ *dest++ = (u8)((hw >> 8) & 0xFF);
+
+ return dest;
+}
+
+/**
+ * ipa_write_8() - convert 8 bit value to byte array
+ * @hw: 8 bit integer
+ * @dest: byte array
+ *
+ * Return value: converted value
+ */
+u8 *ipa_write_8(u8 b, u8 *dest)
+{
+ *dest++ = (b) & 0xFF;
+
+ return dest;
+}
+
+/**
+ * ipa_pad_to_32() - pad byte array to 32 bit value
+ * @dest: byte array
+ *
+ * Return value: padded value
+ */
+u8 *ipa_pad_to_32(u8 *dest)
+{
+ int i = (u32)dest & 0x3;
+ int j;
+
+ if (i)
+ for (j = 0; j < (4 - i); j++)
+ *dest++ = 0;
+
+ return dest;
+}
+
+/**
+ * ipa_generate_hw_rule() - generate HW rule
+ * @ip: IP address type
+ * @attrib: IPA rule attribute
+ * @buf: output buffer
+ * @en_rule: rule
+ *
+ * Return codes:
+ * 0: success
+ * -EPERM: wrong input
+ */
+int ipa_generate_hw_rule(enum ipa_ip_type ip,
+ const struct ipa_rule_attrib *attrib, u8 **buf, u16 *en_rule)
+{
+ u8 ofst_meq32 = 0;
+ u8 ihl_ofst_rng16 = 0;
+ u8 ihl_ofst_meq32 = 0;
+ u8 ofst_meq128 = 0;
+
+ if (ip == IPA_IP_v4) {
+
+ /* error check */
+ if (attrib->attrib_mask & IPA_FLT_NEXT_HDR ||
+ attrib->attrib_mask & IPA_FLT_TC || attrib->attrib_mask &
+ IPA_FLT_FLOW_LABEL) {
+ IPAERR("v6 attrib's specified for v4 rule\n");
+ return -EPERM;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_TOS) {
+ *en_rule |= IPA_TOS_EQ;
+ *buf = ipa_write_8(attrib->u.v4.tos, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_PROTOCOL) {
+ *en_rule |= IPA_PROTOCOL_EQ;
+ *buf = ipa_write_8(attrib->u.v4.protocol, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) {
+ if (ipa_ofst_meq32[ofst_meq32] == -1) {
+ IPAERR("ran out of meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ofst_meq32[ofst_meq32];
+ /* 12 => offset of src ip in v4 header */
+ *buf = ipa_write_8(12, *buf);
+ *buf = ipa_write_32(attrib->u.v4.src_addr_mask, *buf);
+ *buf = ipa_write_32(attrib->u.v4.src_addr, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_ADDR) {
+ if (ipa_ofst_meq32[ofst_meq32] == -1) {
+ IPAERR("ran out of meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ofst_meq32[ofst_meq32];
+ /* 16 => offset of dst ip in v4 header */
+ *buf = ipa_write_8(16, *buf);
+ *buf = ipa_write_32(attrib->u.v4.dst_addr_mask, *buf);
+ *buf = ipa_write_32(attrib->u.v4.dst_addr, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ if (attrib->src_port_hi < attrib->src_port_lo) {
+ IPAERR("bad src port range param\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 0 => offset of src port after v4 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_16(attrib->src_port_hi, *buf);
+ *buf = ipa_write_16(attrib->src_port_lo, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ if (attrib->dst_port_hi < attrib->dst_port_lo) {
+ IPAERR("bad dst port range param\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 2 => offset of dst port after v4 header */
+ *buf = ipa_write_8(2, *buf);
+ *buf = ipa_write_16(attrib->dst_port_hi, *buf);
+ *buf = ipa_write_16(attrib->dst_port_lo, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_TYPE) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 0 => offset of type after v4 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_32(0xFF, *buf);
+ *buf = ipa_write_32(attrib->type, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_CODE) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 1 => offset of code after v4 header */
+ *buf = ipa_write_8(1, *buf);
+ *buf = ipa_write_32(0xFF, *buf);
+ *buf = ipa_write_32(attrib->code, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SPI) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 0 => offset of SPI after v4 header FIXME */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_32(0xFFFFFFFF, *buf);
+ *buf = ipa_write_32(attrib->spi, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 0 => offset of src port after v4 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_16(attrib->src_port, *buf);
+ *buf = ipa_write_16(attrib->src_port, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 2 => offset of dst port after v4 header */
+ *buf = ipa_write_8(2, *buf);
+ *buf = ipa_write_16(attrib->dst_port, *buf);
+ *buf = ipa_write_16(attrib->dst_port, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_META_DATA) {
+ *en_rule |= IPA_METADATA_COMPARE;
+ *buf = ipa_write_8(0, *buf); /* offset, reserved */
+ *buf = ipa_write_32(attrib->meta_data_mask, *buf);
+ *buf = ipa_write_32(attrib->meta_data, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_FRAGMENT) {
+ *en_rule |= IPA_IPV4_IS_FRAG;
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ } else if (ip == IPA_IP_v6) {
+
+ /* v6 code below assumes no extension headers TODO: fix this */
+
+ /* error check */
+ if (attrib->attrib_mask & IPA_FLT_TOS ||
+ attrib->attrib_mask & IPA_FLT_PROTOCOL ||
+ attrib->attrib_mask & IPA_FLT_FRAGMENT) {
+ IPAERR("v4 attrib's specified for v6 rule\n");
+ return -EPERM;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_NEXT_HDR) {
+ *en_rule |= IPA_PROTOCOL_EQ;
+ *buf = ipa_write_8(attrib->u.v6.next_hdr, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_TYPE) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 0 => offset of type after v6 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_32(0xFF, *buf);
+ *buf = ipa_write_32(attrib->type, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_CODE) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 1 => offset of code after v6 header */
+ *buf = ipa_write_8(1, *buf);
+ *buf = ipa_write_32(0xFF, *buf);
+ *buf = ipa_write_32(attrib->code, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SPI) {
+ if (ipa_ihl_ofst_meq32[ihl_ofst_meq32] == -1) {
+ IPAERR("ran out of ihl_meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_meq32[ihl_ofst_meq32];
+ /* 0 => offset of SPI after v6 header FIXME */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_32(0xFFFFFFFF, *buf);
+ *buf = ipa_write_32(attrib->spi, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_meq32++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 0 => offset of src port after v6 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_16(attrib->src_port, *buf);
+ *buf = ipa_write_16(attrib->src_port, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 2 => offset of dst port after v6 header */
+ *buf = ipa_write_8(2, *buf);
+ *buf = ipa_write_16(attrib->dst_port, *buf);
+ *buf = ipa_write_16(attrib->dst_port, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_PORT_RANGE) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ if (attrib->src_port_hi < attrib->src_port_lo) {
+ IPAERR("bad src port range param\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 0 => offset of src port after v6 header */
+ *buf = ipa_write_8(0, *buf);
+ *buf = ipa_write_16(attrib->src_port_hi, *buf);
+ *buf = ipa_write_16(attrib->src_port_lo, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_PORT_RANGE) {
+ if (ipa_ihl_ofst_rng16[ihl_ofst_rng16] == -1) {
+ IPAERR("ran out of ihl_rng16 eq\n");
+ return -EPERM;
+ }
+ if (attrib->dst_port_hi < attrib->dst_port_lo) {
+ IPAERR("bad dst port range param\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ihl_ofst_rng16[ihl_ofst_rng16];
+ /* 2 => offset of dst port after v6 header */
+ *buf = ipa_write_8(2, *buf);
+ *buf = ipa_write_16(attrib->dst_port_hi, *buf);
+ *buf = ipa_write_16(attrib->dst_port_lo, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ihl_ofst_rng16++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_SRC_ADDR) {
+ if (ipa_ofst_meq128[ofst_meq128] == -1) {
+ IPAERR("ran out of meq128 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ofst_meq128[ofst_meq128];
+ /* 8 => offset of src ip in v6 header */
+ *buf = ipa_write_8(8, *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr_mask[0],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr_mask[1],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr_mask[2],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr_mask[3],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr[0], *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr[1], *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr[2], *buf);
+ *buf = ipa_write_32(attrib->u.v6.src_addr[3], *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ofst_meq128++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_DST_ADDR) {
+ if (ipa_ofst_meq128[ofst_meq128] == -1) {
+ IPAERR("ran out of meq128 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ofst_meq128[ofst_meq128];
+ /* 24 => offset of dst ip in v6 header */
+ *buf = ipa_write_8(24, *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr_mask[0],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr_mask[1],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr_mask[2],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr_mask[3],
+ *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr[0], *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr[1], *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr[2], *buf);
+ *buf = ipa_write_32(attrib->u.v6.dst_addr[3], *buf);
+ *buf = ipa_pad_to_32(*buf);
+ ofst_meq128++;
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_TC) {
+ *en_rule |= IPA_FLT_TC;
+ *buf = ipa_write_8(attrib->u.v6.tc, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_FLOW_LABEL) {
+ *en_rule |= IPA_FLT_FLOW_LABEL;
+ /* FIXME FL is only 20 bits */
+ *buf = ipa_write_32(attrib->u.v6.flow_label, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ if (attrib->attrib_mask & IPA_FLT_META_DATA) {
+ *en_rule |= IPA_METADATA_COMPARE;
+ *buf = ipa_write_8(0, *buf); /* offset, reserved */
+ *buf = ipa_write_32(attrib->meta_data_mask, *buf);
+ *buf = ipa_write_32(attrib->meta_data, *buf);
+ *buf = ipa_pad_to_32(*buf);
+ }
+
+ } else {
+ IPAERR("unsupported ip %d\n", ip);
+ return -EPERM;
+ }
+
+ /*
+ * default "rule" means no attributes set -> map to
+ * OFFSET_MEQ32_0 with mask of 0 and val of 0 and offset 0
+ */
+ if (attrib->attrib_mask == 0) {
+ if (ipa_ofst_meq32[ofst_meq32] == -1) {
+ IPAERR("ran out of meq32 eq\n");
+ return -EPERM;
+ }
+ *en_rule |= ipa_ofst_meq32[ofst_meq32];
+ *buf = ipa_write_8(0, *buf); /* offset */
+ *buf = ipa_write_32(0, *buf); /* mask */
+ *buf = ipa_write_32(0, *buf); /* val */
+ *buf = ipa_pad_to_32(*buf);
+ ofst_meq32++;
+ }
+
+ return 0;
+}
+
+/**
+ * ipa_cfg_ep - IPA end-point configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * This includes nat, header, mode, aggregation and route settings and is a one
+ * shot API to configure the IPA end-point fully
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep(u32 clnt_hdl, const struct ipa_ep_cfg *ipa_ep_cfg)
+{
+ int result = -EINVAL;
+
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ result = ipa_cfg_ep_hdr(clnt_hdl, &ipa_ep_cfg->hdr);
+ if (result)
+ return result;
+
+ result = ipa_cfg_ep_aggr(clnt_hdl, &ipa_ep_cfg->aggr);
+ if (result)
+ return result;
+
+ if (IPA_CLIENT_IS_PROD(ipa_ctx->ep[clnt_hdl].client)) {
+ result = ipa_cfg_ep_nat(clnt_hdl, &ipa_ep_cfg->nat);
+ if (result)
+ return result;
+
+ result = ipa_cfg_ep_mode(clnt_hdl, &ipa_ep_cfg->mode);
+ if (result)
+ return result;
+
+ result = ipa_cfg_ep_route(clnt_hdl, &ipa_ep_cfg->route);
+ if (result)
+ return result;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep);
+
+/**
+ * ipa_cfg_ep_nat() - IPA end-point NAT configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ipa_ep_cfg)
+{
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ if (IPA_CLIENT_IS_CONS(ipa_ctx->ep[clnt_hdl].client)) {
+ IPAERR("NAT does not apply to IPA out EP %d\n", clnt_hdl);
+ return -EINVAL;
+ }
+ /* copy over EP cfg */
+ ipa_ctx->ep[clnt_hdl].cfg.nat = *ipa_ep_cfg;
+ /* clnt_hdl is used as pipe_index */
+ ipa_write_reg(ipa_ctx->mmio, IPA_ENDP_INIT_NAT_n_OFST(clnt_hdl),
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.nat.nat_en,
+ IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT,
+ IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep_nat);
+
+/**
+ * ipa_cfg_ep_hdr() - IPA end-point header configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ipa_ep_cfg)
+{
+ u32 val;
+ struct ipa_ep_context *ep;
+
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ ep = &ipa_ctx->ep[clnt_hdl];
+
+ /* copy over EP cfg */
+ ep->cfg.hdr = *ipa_ep_cfg;
+
+ val = IPA_SETFIELD(ep->cfg.hdr.hdr_len,
+ IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_ofst_metadata_valid,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_ofst_metadata,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_additional_const_len,
+ IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_ofst_pkt_size_valid,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_ofst_pkt_size,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK) |
+ IPA_SETFIELD(ep->cfg.hdr.hdr_a5_mux,
+ IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT,
+ IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK);
+
+ ipa_write_reg(ipa_ctx->mmio, IPA_ENDP_INIT_HDR_n_OFST(clnt_hdl), val);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep_hdr);
+
+/**
+ * ipa_cfg_ep_mode() - IPA end-point mode configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ipa_ep_cfg)
+{
+ u32 val;
+
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ if (IPA_CLIENT_IS_CONS(ipa_ctx->ep[clnt_hdl].client)) {
+ IPAERR("MODE does not apply to IPA out EP %d\n", clnt_hdl);
+ return -EINVAL;
+ }
+
+ /* copy over EP cfg */
+ ipa_ctx->ep[clnt_hdl].cfg.mode = *ipa_ep_cfg;
+ ipa_ctx->ep[clnt_hdl].dst_pipe_index = ipa_get_ep_mapping(ipa_ctx->mode,
+ ipa_ep_cfg->dst);
+
+ val = IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.mode.mode,
+ IPA_ENDP_INIT_MODE_n_MODE_SHFT,
+ IPA_ENDP_INIT_MODE_n_MODE_BMSK) |
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].dst_pipe_index,
+ IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT,
+ IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK);
+
+ ipa_write_reg(ipa_ctx->mmio, IPA_ENDP_INIT_MODE_n_OFST(clnt_hdl), val);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep_mode);
+
+/**
+ * ipa_cfg_ep_aggr() - IPA end-point aggregation configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ipa_ep_cfg)
+{
+ u32 val;
+
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+ /* copy over EP cfg */
+ ipa_ctx->ep[clnt_hdl].cfg.aggr = *ipa_ep_cfg;
+
+ val = IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.aggr.aggr_en,
+ IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT,
+ IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK) |
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.aggr.aggr,
+ IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT,
+ IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK) |
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.aggr.aggr_byte_limit,
+ IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT,
+ IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK) |
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].cfg.aggr.aggr_time_limit,
+ IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT,
+ IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK);
+
+ ipa_write_reg(ipa_ctx->mmio, IPA_ENDP_INIT_AGGR_n_OFST(clnt_hdl), val);
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep_aggr);
+
+/**
+ * ipa_cfg_ep_route() - IPA end-point routing configuration
+ * @clnt_hdl: [in] opaque client handle assigned by IPA to client
+ * @ipa_ep_cfg: [in] IPA end-point configuration params
+ *
+ * Returns: 0 on success, negative on failure
+ *
+ * Note: Should not be called from atomic context
+ */
+int ipa_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ipa_ep_cfg)
+{
+ if (clnt_hdl >= IPA_NUM_PIPES || ipa_ctx->ep[clnt_hdl].valid == 0 ||
+ ipa_ep_cfg == NULL) {
+ IPAERR("bad parm.\n");
+ return -EINVAL;
+ }
+
+ if (IPA_CLIENT_IS_CONS(ipa_ctx->ep[clnt_hdl].client)) {
+ IPAERR("ROUTE does not apply to IPA out EP %d\n", clnt_hdl);
+ return -EINVAL;
+ }
+
+ /*
+ * if DMA mode was configured previously for this EP, return with
+ * success
+ */
+ if (ipa_ctx->ep[clnt_hdl].cfg.mode.mode == IPA_DMA) {
+ IPADBG("DMA mode for EP %d\n", clnt_hdl);
+ return 0;
+ }
+
+ if (ipa_ep_cfg->rt_tbl_hdl)
+ IPAERR("client specified non-zero RT TBL hdl - ignore it\n");
+
+ /* always use the "default" routing tables whose indices are 0 */
+ ipa_ctx->ep[clnt_hdl].rt_tbl_idx = 0;
+
+ ipa_write_reg(ipa_ctx->mmio, IPA_ENDP_INIT_ROUTE_n_OFST(clnt_hdl),
+ IPA_SETFIELD(ipa_ctx->ep[clnt_hdl].rt_tbl_idx,
+ IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_SHFT,
+ IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK));
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_cfg_ep_route);
+
+/**
+ * ipa_dump_buff_internal() - dumps buffer for debug purposes
+ * @base: buffer base address
+ * @phy_base: buffer physical base address
+ * @size: size of the buffer
+ */
+void ipa_dump_buff_internal(void *base, dma_addr_t phy_base, u32 size)
+{
+ int i;
+ u32 *cur = (u32 *)base;
+ u8 *byt;
+ IPADBG("START phys=%x\n", phy_base);
+ for (i = 0; i < size / 4; i++) {
+ byt = (u8 *)(cur + i);
+ IPADBG("%2d %08x %02x %02x %02x %02x\n", i, *(cur + i),
+ byt[0], byt[1], byt[2], byt[3]);
+ }
+ IPADBG("END\n");
+}
+
+/**
+ * ipa_dump() - dumps part of driver data structures for debug purposes
+ */
+void ipa_dump(void)
+{
+ struct ipa_mem_buffer hdr_mem = { 0 };
+ struct ipa_mem_buffer rt_mem = { 0 };
+ struct ipa_mem_buffer flt_mem = { 0 };
+
+ mutex_lock(&ipa_ctx->lock);
+
+ if (ipa_generate_hdr_hw_tbl(&hdr_mem))
+ IPAERR("fail\n");
+ if (ipa_generate_rt_hw_tbl(IPA_IP_v4, &rt_mem))
+ IPAERR("fail\n");
+ if (ipa_generate_flt_hw_tbl(IPA_IP_v4, &flt_mem))
+ IPAERR("fail\n");
+ IPAERR("PHY hdr=%x rt=%x flt=%x\n", hdr_mem.phys_base, rt_mem.phys_base,
+ flt_mem.phys_base);
+ IPAERR("VIRT hdr=%x rt=%x flt=%x\n", (u32)hdr_mem.base,
+ (u32)rt_mem.base, (u32)flt_mem.base);
+ IPAERR("SIZE hdr=%d rt=%d flt=%d\n", hdr_mem.size, rt_mem.size,
+ flt_mem.size);
+ IPA_DUMP_BUFF(hdr_mem.base, hdr_mem.phys_base, hdr_mem.size);
+ IPA_DUMP_BUFF(rt_mem.base, rt_mem.phys_base, rt_mem.size);
+ IPA_DUMP_BUFF(flt_mem.base, flt_mem.phys_base, flt_mem.size);
+ if (hdr_mem.phys_base)
+ dma_free_coherent(NULL, hdr_mem.size, hdr_mem.base,
+ hdr_mem.phys_base);
+ if (rt_mem.phys_base)
+ dma_free_coherent(NULL, rt_mem.size, rt_mem.base,
+ rt_mem.phys_base);
+ if (flt_mem.phys_base)
+ dma_free_coherent(NULL, flt_mem.size, flt_mem.base,
+ flt_mem.phys_base);
+ mutex_unlock(&ipa_ctx->lock);
+}
+
+/*
+ * TODO: add swap if needed, for now assume LE is ok for device memory
+ * even though IPA registers are assumed to be BE
+ */
+/**
+ * ipa_write_dev_8() - writes 8 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ */
+void ipa_write_dev_8(u8 val, u16 ofst_ipa_sram)
+{
+ iowrite8(val, (u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_write_dev_16() - writes 16 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ *
+ */
+void ipa_write_dev_16(u16 val, u16 ofst_ipa_sram)
+{
+ iowrite16(val, (u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_write_dev_32() - writes 32 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ */
+void ipa_write_dev_32(u32 val, u16 ofst_ipa_sram)
+{
+ iowrite32(val, (u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_read_dev_8() - reads 8 bit value
+ * @ofst_ipa_sram: address to read from
+ *
+ * Return value: value read
+ */
+unsigned int ipa_read_dev_8(u16 ofst_ipa_sram)
+{
+ return ioread8((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_read_dev_16() - reads 16 bit value
+ * @ofst_ipa_sram: address to read from
+ *
+ * Return value: value read
+ */
+unsigned int ipa_read_dev_16(u16 ofst_ipa_sram)
+{
+ return ioread16((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_read_dev_32() - reads 32 bit value
+ * @ofst_ipa_sram: address to read from
+ *
+ * Return value: value read
+ */
+unsigned int ipa_read_dev_32(u16 ofst_ipa_sram)
+{
+ return ioread32((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram);
+}
+
+/**
+ * ipa_write_dev_8rep() - writes 8 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ * @count: num of bytes to write
+ */
+void ipa_write_dev_8rep(u16 ofst_ipa_sram, const void *buf, unsigned long count)
+{
+ iowrite8_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram), buf,
+ count);
+}
+
+/**
+ * ipa_write_dev_16rep() - writes 16 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ * @count: num of bytes to write
+ */
+void ipa_write_dev_16rep(u16 ofst_ipa_sram, const void *buf,
+ unsigned long count)
+{
+ iowrite16_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram),
+ buf, count);
+}
+
+/**
+ * ipa_write_dev_32rep() - writes 32 bit value
+ * @val: value
+ * @ofst_ipa_sram: address to write to
+ * @count: num of bytes to write
+ */
+void ipa_write_dev_32rep(u16 ofst_ipa_sram, const void *buf,
+ unsigned long count)
+{
+ iowrite32_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram),
+ buf, count);
+}
+
+/**
+ * ipa_read_dev_8rep() - reads 8 bit value
+ * @ofst_ipa_sram: address to read from
+ * @buf: buffer to read to
+ * @count: number of bytes to read
+ */
+void ipa_read_dev_8rep(u16 ofst_ipa_sram, void *buf, unsigned long count)
+{
+ ioread8_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram), buf,
+ count);
+}
+
+/**
+ * ipa_read_dev_16rep() - reads 16 bit value
+ * @ofst_ipa_sram: address to read from
+ * @buf: buffer to read to
+ * @count: number of bytes to read
+ */
+void ipa_read_dev_16rep(u16 ofst_ipa_sram, void *buf, unsigned long count)
+{
+ ioread16_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram), buf,
+ count);
+}
+
+/**
+ * ipa_read_dev_32rep() - reads 32 bit value
+ * @ofst_ipa_sram: address to read from
+ * @buf: buffer to read to
+ * @count: number of bytes to read
+ */
+void ipa_read_dev_32rep(u16 ofst_ipa_sram, void *buf, unsigned long count)
+{
+ ioread32_rep((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram), buf,
+ count);
+}
+
+/**
+ * ipa_memset_dev() - memset IO
+ * @ofst_ipa_sram: address to set
+ * @value: value
+ * @count: number of bytes to set
+ */
+void ipa_memset_dev(u16 ofst_ipa_sram, u8 value, unsigned int count)
+{
+ memset_io((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram), value,
+ count);
+}
+
+/**
+ * ipa_memcpy_from_dev() - copy memory from device
+ * @dest: buffer to copy to
+ * @ofst_ipa_sram: address
+ * @count: number of bytes to copy
+ */
+void ipa_memcpy_from_dev(void *dest, u16 ofst_ipa_sram, unsigned int count)
+{
+ memcpy_fromio(dest, (void *)((u32)ipa_ctx->mmio + 0x4000 +
+ ofst_ipa_sram), count);
+}
+
+/**
+ * ipa_memcpy_to_dev() - copy memory to device
+ * @ofst_ipa_sram: address
+ * @source: buffer to copy from
+ * @count: number of bytes to copy
+ */
+void ipa_memcpy_to_dev(u16 ofst_ipa_sram, void *source, unsigned int count)
+{
+ memcpy_toio((void *)((u32)ipa_ctx->mmio + 0x4000 + ofst_ipa_sram),
+ source, count);
+}
+
+/**
+ * ipa_defrag() - handle de-frag for bridging type of cases
+ * @skb: skb
+ *
+ * Return value:
+ * 0: success
+ */
+int ipa_defrag(struct sk_buff *skb)
+{
+ /*
+ * Reassemble IP fragments. TODO: need to setup network_header to
+ * point to start of IP header
+ */
+ if (ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET)) {
+ if (ip_defrag(skb, IP_DEFRAG_CONNTRACK_IN))
+ return -EINPROGRESS;
+ }
+
+ /* skb is not fully assembled, send it back out */
+ return 0;
+}
+
+/**
+ * ipa_search() - search for handle in RB tree
+ * @root: tree root
+ * @hdl: handle
+ *
+ * Return value: tree node corresponding to the handle
+ */
+struct ipa_tree_node *ipa_search(struct rb_root *root, u32 hdl)
+{
+ struct rb_node *node = root->rb_node;
+
+ while (node) {
+ struct ipa_tree_node *data = container_of(node,
+ struct ipa_tree_node, node);
+
+ if (hdl < data->hdl)
+ node = node->rb_left;
+ else if (hdl > data->hdl)
+ node = node->rb_right;
+ else
+ return data;
+ }
+ return NULL;
+}
+
+/**
+ * ipa_insert() - insert new node to RB tree
+ * @root: tree root
+ * @data: new data to insert
+ *
+ * Return value:
+ * 0: success
+ * -EPERM: tree already contains the node with provided handle
+ */
+int ipa_insert(struct rb_root *root, struct ipa_tree_node *data)
+{
+ struct rb_node **new = &(root->rb_node), *parent = NULL;
+
+ /* Figure out where to put new node */
+ while (*new) {
+ struct ipa_tree_node *this = container_of(*new,
+ struct ipa_tree_node, node);
+
+ parent = *new;
+ if (data->hdl < this->hdl)
+ new = &((*new)->rb_left);
+ else if (data->hdl > this->hdl)
+ new = &((*new)->rb_right);
+ else
+ return -EPERM;
+ }
+
+ /* Add new node and rebalance tree. */
+ rb_link_node(&data->node, parent, new);
+ rb_insert_color(&data->node, root);
+
+ return 0;
+}
+
+/**
+ * ipa_pipe_mem_init() - initialize the pipe memory
+ * @start_ofst: start offset
+ * @size: size
+ *
+ * Return value:
+ * 0: success
+ * -ENOMEM: no memory
+ */
+int ipa_pipe_mem_init(u32 start_ofst, u32 size)
+{
+ int res;
+ u32 aligned_start_ofst;
+ u32 aligned_size;
+ struct gen_pool *pool;
+
+ if (!size) {
+ IPAERR("no IPA pipe mem alloted\n");
+ goto fail;
+ }
+
+ aligned_start_ofst = IPA_HW_TABLE_ALIGNMENT(start_ofst);
+ aligned_size = size - (aligned_start_ofst - start_ofst);
+
+ IPADBG("start_ofst=%u aligned_start_ofst=%u size=%u aligned_size=%u\n",
+ start_ofst, aligned_start_ofst, size, aligned_size);
+
+ /* allocation order of 8 i.e. 128 bytes, global pool */
+ pool = gen_pool_create(8, -1);
+ if (!pool) {
+ IPAERR("Failed to create a new memory pool.\n");
+ goto fail;
+ }
+
+ res = gen_pool_add(pool, aligned_start_ofst, aligned_size, -1);
+ if (res) {
+ IPAERR("Failed to add memory to IPA pipe pool\n");
+ goto err_pool_add;
+ }
+
+ ipa_ctx->pipe_mem_pool = pool;
+ return 0;
+
+err_pool_add:
+ gen_pool_destroy(pool);
+fail:
+ return -ENOMEM;
+}
+
+/**
+ * ipa_pipe_mem_alloc() - allocate pipe memory
+ * @ofst: offset
+ * @size: size
+ *
+ * Return value:
+ * 0: success
+ */
+int ipa_pipe_mem_alloc(u32 *ofst, u32 size)
+{
+ u32 vaddr;
+ int res = -1;
+
+ if (!ipa_ctx->pipe_mem_pool || !size) {
+ IPAERR("failed size=%u pipe_mem_pool=%p\n", size,
+ ipa_ctx->pipe_mem_pool);
+ return res;
+ }
+
+ vaddr = gen_pool_alloc(ipa_ctx->pipe_mem_pool, size);
+
+ if (vaddr) {
+ *ofst = vaddr;
+ res = 0;
+ IPADBG("size=%u ofst=%u\n", size, vaddr);
+ } else {
+ IPAERR("size=%u failed\n", size);
+ }
+
+ return res;
+}
+
+/**
+ * ipa_pipe_mem_free() - free pipe memory
+ * @ofst: offset
+ * @size: size
+ *
+ * Return value:
+ * 0: success
+ */
+int ipa_pipe_mem_free(u32 ofst, u32 size)
+{
+ IPADBG("size=%u ofst=%u\n", size, ofst);
+ if (ipa_ctx->pipe_mem_pool && size)
+ gen_pool_free(ipa_ctx->pipe_mem_pool, ofst, size);
+ return 0;
+}
+
+/**
+ * ipa_set_aggr_mode() - Set the aggregation mode which is a global setting
+ * @mode: [in] the desired aggregation mode for e.g. straight MBIM, QCNCM,
+ * etc
+ *
+ * Returns: 0 on success
+ */
+int ipa_set_aggr_mode(enum ipa_aggr_mode mode)
+{
+ u32 reg_val;
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_2_OFST);
+ ipa_write_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_2_OFST,
+ ((mode & IPA_AGGREGATION_MODE_MSK) <<
+ IPA_AGGREGATION_MODE_SHFT) |
+ (reg_val & IPA_AGGREGATION_MODE_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_set_aggr_mode);
+
+/**
+ * ipa_set_qcncm_ndp_sig() - Set the NDP signature used for QCNCM aggregation
+ * mode
+ * @sig: [in] the first 3 bytes of QCNCM NDP signature (expected to be
+ * "QND")
+ *
+ * Set the NDP signature used for QCNCM aggregation mode. The fourth byte
+ * (expected to be 'P') needs to be set using the header addition mechanism
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_set_qcncm_ndp_sig(char sig[3])
+{
+ u32 reg_val;
+
+ if (sig == NULL) {
+ IPAERR("bad argument for ipa_set_qcncm_ndp_sig/n");
+ return -EINVAL;
+ }
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_2_OFST);
+ ipa_write_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_2_OFST, sig[0] <<
+ IPA_AGGREGATION_QCNCM_SIG0_SHFT |
+ (sig[1] << IPA_AGGREGATION_QCNCM_SIG1_SHFT) |
+ sig[2] | (reg_val & IPA_AGGREGATION_QCNCM_SIG_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_set_qcncm_ndp_sig);
+
+/**
+ * ipa_set_single_ndp_per_mbim() - Enable/disable single NDP per MBIM frame
+ * configuration
+ * @enable: [in] true for single NDP/MBIM; false otherwise
+ *
+ * Returns: 0 on success
+ */
+int ipa_set_single_ndp_per_mbim(bool enable)
+{
+ u32 reg_val;
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST);
+ ipa_write_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST, (enable &
+ IPA_AGGREGATION_SINGLE_NDP_MSK) |
+ (reg_val & IPA_AGGREGATION_SINGLE_NDP_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_set_single_ndp_per_mbim);
+
+/**
+ * ipa_straddle_boundary() - Checks whether a memory buffer straddles a boundary
+ * @start: start address of the memory buffer
+ * @end: end address of the memory buffer
+ * @boundary: boundary
+ *
+ * Return value:
+ * 1: if the interval [start, end] straddles boundary
+ * 0: otherwise
+ */
+int ipa_straddle_boundary(u32 start, u32 end, u32 boundary)
+{
+ u32 next_start;
+ u32 prev_end;
+
+ IPADBG("start=%u end=%u boundary=%u\n", start, end, boundary);
+
+ next_start = (start + (boundary - 1)) & ~(boundary - 1);
+ prev_end = ((end + (boundary - 1)) & ~(boundary - 1)) - boundary;
+
+ while (next_start < prev_end)
+ next_start += boundary;
+
+ if (next_start == prev_end)
+ return 1;
+ else
+ return 0;
+}
+
diff --git a/drivers/platform/msm/ipa/rmnet_bridge.c b/drivers/platform/msm/ipa/rmnet_bridge.c
new file mode 100644
index 0000000..3c7f5ca
--- /dev/null
+++ b/drivers/platform/msm/ipa/rmnet_bridge.c
@@ -0,0 +1,122 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <mach/bam_dmux.h>
+#include <mach/ipa.h>
+#include <mach/sps.h>
+#include "a2_service.h"
+#include "ipa_i.h"
+
+static struct rmnet_bridge_cb_type {
+ u32 producer_handle;
+ u32 consumer_handle;
+ bool is_connected;
+} rmnet_bridge_cb;
+
+/**
+* rmnet_bridge_init() - Initialize RmNet bridge module
+*
+* Return codes:
+* 0: success
+*/
+int rmnet_bridge_init(void)
+{
+ memset(&rmnet_bridge_cb, 0, sizeof(struct rmnet_bridge_cb_type));
+
+ return 0;
+}
+EXPORT_SYMBOL(rmnet_bridge_init);
+
+/**
+* rmnet_bridge_disconnect() - Disconnect RmNet bridge module
+*
+* Return codes:
+* 0: success
+* -EINVAL: invalid parameters
+*/
+int rmnet_bridge_disconnect(void)
+{
+ int ret = 0;
+ if (false == rmnet_bridge_cb.is_connected) {
+ pr_err("%s: trying to disconnect already disconnected RmNet bridge\n",
+ __func__);
+ goto bail;
+ }
+
+ rmnet_bridge_cb.is_connected = false;
+
+ ret = ipa_bridge_teardown(IPA_DL);
+ ret = ipa_bridge_teardown(IPA_UL);
+bail:
+ return ret;
+}
+EXPORT_SYMBOL(rmnet_bridge_disconnect);
+
+/**
+* rmnet_bridge_connect() - Connect RmNet bridge module
+* @producer_hdl: IPA producer handle
+* @consumer_hdl: IPA consumer handle
+* @wwan_logical_channel_id: WWAN logical channel ID
+*
+* Return codes:
+* 0: success
+* -EINVAL: invalid parameters
+*/
+int rmnet_bridge_connect(u32 producer_hdl,
+ u32 consumer_hdl,
+ int wwan_logical_channel_id)
+{
+ int ret = 0;
+
+ if (true == rmnet_bridge_cb.is_connected) {
+ ret = 0;
+ pr_err("%s: trying to connect already connected RmNet bridge\n",
+ __func__);
+ goto bail;
+ }
+
+ rmnet_bridge_cb.consumer_handle = consumer_hdl;
+ rmnet_bridge_cb.producer_handle = producer_hdl;
+ rmnet_bridge_cb.is_connected = true;
+
+ ret = ipa_bridge_setup(IPA_DL);
+ if (ret) {
+ pr_err("%s: IPA DL bridge setup failure\n", __func__);
+ goto bail_dl;
+ }
+ ret = ipa_bridge_setup(IPA_UL);
+ if (ret) {
+ pr_err("%s: IPA UL bridge setup failure\n", __func__);
+ goto bail_ul;
+ }
+ return 0;
+bail_ul:
+ ipa_bridge_teardown(IPA_DL);
+bail_dl:
+ rmnet_bridge_cb.is_connected = false;
+bail:
+ return ret;
+}
+EXPORT_SYMBOL(rmnet_bridge_connect);
+
+void rmnet_bridge_get_client_handles(u32 *producer_handle,
+ u32 *consumer_handle)
+{
+ if (producer_handle == NULL || consumer_handle == NULL)
+ return;
+
+ *producer_handle = rmnet_bridge_cb.producer_handle;
+ *consumer_handle = rmnet_bridge_cb.consumer_handle;
+}
diff --git a/drivers/platform/msm/sps/sps.c b/drivers/platform/msm/sps/sps.c
index 25febff..e9c3371 100644
--- a/drivers/platform/msm/sps/sps.c
+++ b/drivers/platform/msm/sps/sps.c
@@ -2122,14 +2122,6 @@
SPS_DBG("sps:bamdma_restricted_pipes=0x%x.",
sps->bamdma_restricted_pipes);
- if (of_property_read_u32((&pdev->dev)->of_node,
- "qcom,device-type",
- &d_type)) {
- d_type = 1;
- SPS_DBG("sps:default device type.\n");
- } else
- SPS_DBG("sps:device type is %d.", d_type);
-
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (resource) {
sps->bamdma_bam_phys_base = resource->start;
@@ -2174,6 +2166,14 @@
}
#endif
+ if (of_property_read_u32((&pdev->dev)->of_node,
+ "qcom,device-type",
+ &d_type)) {
+ d_type = 1;
+ SPS_DBG("sps:default device type.\n");
+ } else
+ SPS_DBG("sps:device type is %d.", d_type);
+
return 0;
}
diff --git a/drivers/platform/msm/sps/sps_dma.c b/drivers/platform/msm/sps/sps_dma.c
index f8b4f51d..335de9a 100644
--- a/drivers/platform/msm/sps/sps_dma.c
+++ b/drivers/platform/msm/sps/sps_dma.c
@@ -274,7 +274,6 @@
{
struct bamdma_device *dev;
struct sps_bam_props *props;
- u32 chan;
int result = SPS_ERROR;
mutex_lock(&bam_dma_lock);
@@ -343,14 +342,6 @@
dev->num_pipes = dev->bam->props.num_pipes;
- /* Disable all channels */
- if (dev->local)
- for (chan = 0; chan < (dev->num_pipes / 2); chan++) {
- dma_write_reg_field(dev->virt_addr,
- DMA_CHNL_CONFIG(chan),
- DMA_CHNL_ENABLE, 0);
- }
-
result = 0;
exit_err:
if (result) {
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 7b7e05e..bc2e2ae 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -333,6 +333,16 @@
To compile this driver as a module, choose M here: the module will
be called smb137b.
+config SMB137C_CHARGER
+ tristate "Summit SMB137C Battery Charger"
+ depends on I2C
+ depends on OF
+ help
+ The SMB137C charger chip from Summit is a switching mode based
+ charging solution. This driver supports enabling and disabling
+ charging, setting the input current limit, and enabling USB OTG mode
+ in order to supply 5 V on the VBUS line.
+
config SMB349_CHARGER
tristate "smb349 charger"
depends on I2C
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 3e74f35..990bd03 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -55,6 +55,7 @@
obj-$(CONFIG_BATTERY_BQ27541) += bq27541_fuelgauger.o
obj-$(CONFIG_BATTERY_BQ28400) += bq28400_battery.o
obj-$(CONFIG_SMB137B_CHARGER) += smb137b.o
+obj-$(CONFIG_SMB137C_CHARGER) += smb137c-charger.o
obj-$(CONFIG_PM8XXX_CCADC) += pm8xxx-ccadc.o
obj-$(CONFIG_PM8921_BMS) += pm8921-bms.o
obj-$(CONFIG_QPNP_BMS) += qpnp-bms.o
diff --git a/drivers/power/bq28400_battery.c b/drivers/power/bq28400_battery.c
index 39d52cb..77e74fa 100644
--- a/drivers/power/bq28400_battery.c
+++ b/drivers/power/bq28400_battery.c
@@ -486,6 +486,8 @@
u16 battery_status;
battery_status = bq28400_read_reg(client, SBS_BATTERY_STATUS);
+ rsoc = bq28400_read_rsoc(client);
+ current_ma = bq28400_read_current(client);
if (battery_status & BAT_STATUS_EMPTY)
pr_debug("Battery report Empty.\n");
@@ -493,29 +495,31 @@
/* Battery may report FULL before rsoc is 100%
* for protection and cell-balancing.
* The FULL report may remain when rsoc drops from 100%.
+ * If battery is full but DC-Jack is removed then report discahrging.
*/
if (battery_status & BAT_STATUS_FULL) {
pr_debug("Battery report Full.\n");
bq28400_enable_charging(bq28400_dev, false);
+ if (current_ma < 0)
+ return POWER_SUPPLY_STATUS_DISCHARGING;
return POWER_SUPPLY_STATUS_FULL;
}
- rsoc = bq28400_read_rsoc(client);
- current_ma = bq28400_read_current(client);
-
if (rsoc == 100) {
bq28400_enable_charging(bq28400_dev, false);
pr_debug("Full.\n");
return POWER_SUPPLY_STATUS_FULL;
}
+ /* Enable charging when battery is not full */
+ bq28400_enable_charging(bq28400_dev, true);
+
/*
* Positive current indicates charging
* Negative current indicates discharging.
* Charging is stopped at termination-current.
*/
if (current_ma < 0) {
- bq28400_enable_charging(bq28400_dev, true);
pr_debug("Discharging.\n");
status = POWER_SUPPLY_STATUS_DISCHARGING;
} else if (current_ma > BQ_TERMINATION_CURRENT_MA) {
@@ -755,6 +759,12 @@
static void bq28400_external_power_changed(struct power_supply *psy)
{
pr_debug("Notify power_supply_changed.\n");
+
+ /* The battery gauge monitors the current and voltage every 1 second.
+ * Therefore a delay from the time that the charger start/stop charging
+ * until the battery gauge detects it.
+ */
+ msleep(1000);
/* Update LEDs and notify uevents */
power_supply_changed(&bq28400_dev->batt_psy);
}
@@ -818,6 +828,11 @@
return -EIO;
}
+ if (bq28400_read_reg(client, SBS_BATTERY_STATUS) < 0) {
+ pr_err("Device doesn't exist.\n");
+ return -ENODEV;
+ }
+
bq28400_dev = kzalloc(sizeof(*bq28400_dev), GFP_KERNEL);
if (!bq28400_dev) {
pr_err(" alloc fail.\n");
@@ -876,7 +891,8 @@
}
static const struct of_device_id bq28400_match[] = {
- { .compatible = "ti,bq28400-battery", },
+ { .compatible = "ti,bq28400-battery" },
+ { .compatible = "ti,bq30z55-battery" },
{ },
};
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index 23903df..703aca9 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -87,7 +87,7 @@
struct pm8921_bms_chip {
struct device *dev;
struct dentry *dent;
- unsigned int r_sense;
+ int r_sense_uohm;
unsigned int v_cutoff;
unsigned int fcc;
struct single_row_lut *fcc_temp_lut;
@@ -500,15 +500,15 @@
#define SLEEP_CLK_HZ 32764
#define SECONDS_PER_HOUR 3600
/**
- * ccmicrovolt_to_nvh -
+ * ccmicrovolt_to_uvh -
* @cc_uv: coulumb counter converted to uV
*
- * RETURNS: coulumb counter based charge in nVh
- * (nano Volt Hour)
+ * RETURNS: coulumb counter based charge in uVh
+ * (micro Volt Hour)
*/
-static s64 ccmicrovolt_to_nvh(s64 cc_uv)
+static s64 ccmicrovolt_to_uvh(s64 cc_uv)
{
- return div_s64(cc_uv * CC_READING_TICKS * 1000,
+ return div_s64(cc_uv * CC_READING_TICKS,
SLEEP_CLK_HZ * SECONDS_PER_HOUR);
}
@@ -618,7 +618,7 @@
convert_vbatt_raw_to_uv(the_chip, usb_chg, vbat_raw, vbat_uv);
convert_vsense_to_uv(the_chip, vsense_raw, &vsense_uv);
- *ibat_ua = vsense_uv * 1000 / (int)the_chip->r_sense;
+ *ibat_ua = div_s64((s64)vsense_uv * 1000000LL, the_chip->r_sense_uohm);
pr_debug("vsense_raw = 0x%x vbat_raw = 0x%x"
" ibat_ua = %d vbat_uv = %d\n",
@@ -840,7 +840,7 @@
*/
static void calculate_cc_uah(struct pm8921_bms_chip *chip, int cc, int *val)
{
- int64_t cc_voltage_uv, cc_nvh, cc_uah;
+ int64_t cc_voltage_uv, cc_uvh, cc_uah;
cc_voltage_uv = cc;
cc_voltage_uv -= chip->cc_reading_at_100;
@@ -850,12 +850,28 @@
cc_voltage_uv = cc_to_microvolt(chip, cc_voltage_uv);
cc_voltage_uv = pm8xxx_cc_adjust_for_gain(cc_voltage_uv);
pr_debug("cc_voltage_uv = %lld microvolts\n", cc_voltage_uv);
- cc_nvh = ccmicrovolt_to_nvh(cc_voltage_uv);
- pr_debug("cc_nvh = %lld nano_volt_hour\n", cc_nvh);
- cc_uah = div_s64(cc_nvh, chip->r_sense);
+ cc_uvh = ccmicrovolt_to_uvh(cc_voltage_uv);
+ pr_debug("cc_uvh = %lld micro_volt_hour\n", cc_uvh);
+ cc_uah = div_s64(cc_uvh * 1000000LL, chip->r_sense_uohm);
*val = cc_uah;
}
+int pm8921_bms_cc_uah(int *cc_uah)
+{
+ int cc;
+
+ *cc_uah = 0;
+
+ if (!the_chip)
+ return -EINVAL;
+
+ read_cc(the_chip, &cc);
+ calculate_cc_uah(the_chip, cc, cc_uah);
+
+ return 0;
+}
+EXPORT_SYMBOL(pm8921_bms_cc_uah);
+
static int calculate_termination_uuc(struct pm8921_bms_chip *chip,
int batt_temp, int chargecycles,
int fcc_uah, int i_ma,
@@ -1398,7 +1414,7 @@
(s64)fcc_uah - uuc_uah);
soc_est = bound_soc(soc_est);
- if (ibat_ua < 0) {
+ if (ibat_ua < 0 && pm8921_is_batfet_closed()) {
soc = charging_adjustments(chip, soc, vbat_uv, ibat_ua,
batt_temp, chargecycles,
fcc_uah, cc_uah, uuc_uah);
@@ -1895,7 +1911,8 @@
}
/* last_soc < soc ... scale and catch up */
- if (last_soc != -EINVAL && last_soc < soc && soc != 100)
+ if (last_soc != -EINVAL && last_soc < soc && soc != 100
+ && chip->catch_up_time_us != 0)
soc = scale_soc_while_chg(chip, delta_time_us, soc, last_soc);
last_soc = soc;
@@ -2054,25 +2071,25 @@
int pm8921_bms_get_battery_current(int *result_ua)
{
- int vsense;
+ int vsense_uv;
if (!the_chip) {
pr_err("called before initialization\n");
return -EINVAL;
}
- if (the_chip->r_sense == 0) {
+ if (the_chip->r_sense_uohm == 0) {
pr_err("r_sense is zero\n");
return -EINVAL;
}
mutex_lock(&the_chip->bms_output_lock);
pm_bms_lock_output_data(the_chip);
- read_vsense_avg(the_chip, &vsense);
+ read_vsense_avg(the_chip, &vsense_uv);
pm_bms_unlock_output_data(the_chip);
mutex_unlock(&the_chip->bms_output_lock);
- pr_debug("vsense=%duV\n", vsense);
+ pr_debug("vsense=%duV\n", vsense_uv);
/* cast for signed division */
- *result_ua = vsense * 1000 / (int)the_chip->r_sense;
+ *result_ua = div_s64(vsense_uv * 1000000LL, the_chip->r_sense_uohm);
pr_debug("ibat=%duA\n", *result_ua);
return 0;
}
@@ -2880,7 +2897,7 @@
mutex_init(&chip->bms_output_lock);
mutex_init(&chip->last_ocv_uv_mutex);
chip->dev = &pdev->dev;
- chip->r_sense = pdata->r_sense;
+ chip->r_sense_uohm = pdata->r_sense_uohm;
chip->v_cutoff = pdata->v_cutoff;
chip->max_voltage_uv = pdata->max_voltage_uv;
chip->chg_term_ua = pdata->chg_term_ua;
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 8c561b9b..8dbdfa3 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -87,6 +87,7 @@
#define EOC_CHECK_PERIOD_MS 10000
/* check for USB unplug every 200 msecs */
#define UNPLUG_CHECK_WAIT_PERIOD_MS 200
+#define USB_TRIM_ENTRIES 16
enum chg_fsm_state {
FSM_STATE_OFF_0 = 0,
@@ -209,7 +210,6 @@
* @dc_present: present status of dc
* @usb_charger_current: usb current to charge the battery with used when
* the usb path is enabled or charging is resumed
- * @safety_time: max time for which charging will happen
* @update_time: how frequently the userland needs to be updated
* @max_voltage_mv: the max volts the batt should be charged up to
* @min_voltage_mv: the min battery voltage before turning the FETon
@@ -230,12 +230,12 @@
unsigned int usb_charger_current;
unsigned int max_bat_chg_current;
unsigned int pmic_chg_irq[PM_CHG_MAX_INTS];
- unsigned int safety_time;
unsigned int ttrkl_time;
unsigned int update_time;
unsigned int max_voltage_mv;
unsigned int min_voltage_mv;
unsigned int uvd_voltage_mv;
+ unsigned int safe_current_ma;
unsigned int alarm_low_mv;
unsigned int alarm_high_mv;
int cool_temp_dc;
@@ -259,6 +259,7 @@
struct power_supply batt_psy;
struct dentry *dent;
struct bms_notify bms_notify;
+ int *usb_trim_table;
bool keep_btm_on_suspend;
bool ext_charging;
bool ext_charge_done;
@@ -290,6 +291,7 @@
u8 active_path;
int recent_reported_soc;
int battery_less_hardware;
+ int ibatmax_max_adj_ma;
};
/* user space parameter to limit usb current */
@@ -634,10 +636,26 @@
}
#define PM8921_CHG_IBATMAX_MIN 325
-#define PM8921_CHG_IBATMAX_MAX 2000
+#define PM8921_CHG_IBATMAX_MAX 3025
#define PM8921_CHG_I_MIN_MA 225
#define PM8921_CHG_I_STEP_MA 50
#define PM8921_CHG_I_MASK 0x3F
+static int pm_chg_ibatmax_get(struct pm8921_chg_chip *chip, int *ibat_ma)
+{
+ u8 temp;
+ int rc;
+
+ rc = pm8xxx_readb(chip->dev->parent, CHG_IBAT_MAX, &temp);
+ if (rc) {
+ pr_err("rc = %d while reading ibat max\n", rc);
+ *ibat_ma = 0;
+ return rc;
+ }
+ *ibat_ma = (int)(temp & PM8921_CHG_I_MASK) * PM8921_CHG_I_STEP_MA
+ + PM8921_CHG_I_MIN_MA;
+ return 0;
+}
+
static int pm_chg_ibatmax_set(struct pm8921_chg_chip *chip, int chg_current)
{
u8 temp;
@@ -709,6 +727,46 @@
u8 value;
};
+/* USB Trim tables */
+static int usb_trim_8038_table[USB_TRIM_ENTRIES] = {
+ 0x0,
+ 0x0,
+ -0x9,
+ 0x0,
+ -0xD,
+ 0x0,
+ -0x10,
+ -0x11,
+ 0x0,
+ 0x0,
+ -0x25,
+ 0x0,
+ -0x28,
+ 0x0,
+ -0x32,
+ 0x0
+};
+
+static int usb_trim_8917_table[USB_TRIM_ENTRIES] = {
+ 0x0,
+ 0x0,
+ 0xA,
+ 0xC,
+ 0x10,
+ 0x10,
+ 0x13,
+ 0x14,
+ 0x13,
+ 0x16,
+ 0x1A,
+ 0x1D,
+ 0x1D,
+ 0x21,
+ 0x24,
+ 0x26
+};
+
+/* Maximum USB setting table */
static struct usb_ma_limit_entry usb_ma_table[] = {
{100, 0x0},
{200, 0x1},
@@ -728,18 +786,92 @@
{1600, 0xF},
};
+#define REG_SBI_CONFIG 0x04F
+#define PAGE3_ENABLE_MASK 0x6
+#define USB_OVP_TRIM_MASK 0x3F
+#define USB_OVP_TRIM_MIN 0x00
+#define REG_USB_OVP_TRIM_ORIG_LSB 0x10A
+#define REG_USB_OVP_TRIM_ORIG_MSB 0x09C
+static int pm_chg_usb_trim(struct pm8921_chg_chip *chip, int index)
+{
+ u8 temp, sbi_config, msb, lsb;
+ s8 trim;
+ int rc = 0;
+ static u8 usb_trim_reg_orig = 0xFF;
+
+ /* No trim data for PM8921 */
+ if (!chip->usb_trim_table)
+ return 0;
+
+ if (usb_trim_reg_orig == 0xFF) {
+ rc = pm8xxx_readb(chip->dev->parent,
+ REG_USB_OVP_TRIM_ORIG_MSB, &msb);
+ if (rc) {
+ pr_err("error = %d reading sbi config reg\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent,
+ REG_USB_OVP_TRIM_ORIG_LSB, &lsb);
+ if (rc) {
+ pr_err("error = %d reading sbi config reg\n", rc);
+ return rc;
+ }
+
+ msb = msb >> 5;
+ lsb = lsb >> 5;
+ usb_trim_reg_orig = msb << 3 | lsb;
+ }
+
+ /* use the original trim value */
+ trim = usb_trim_reg_orig;
+
+ trim += chip->usb_trim_table[index];
+ if (trim < 0)
+ trim = 0;
+
+ pr_err("trim_orig %d write 0x%x index=%d value 0x%x to USB_OVP_TRIM\n",
+ usb_trim_reg_orig, trim, index, chip->usb_trim_table[index]);
+
+ rc = pm8xxx_readb(chip->dev->parent, REG_SBI_CONFIG, &sbi_config);
+ if (rc) {
+ pr_err("error = %d reading sbi config reg\n", rc);
+ return rc;
+ }
+
+ temp = sbi_config | PAGE3_ENABLE_MASK;
+ rc = pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, temp);
+ if (rc) {
+ pr_err("error = %d writing sbi config reg\n", rc);
+ return rc;
+ }
+
+ rc = pm_chg_masked_write(chip, USB_OVP_TRIM, USB_OVP_TRIM_MASK, trim);
+ if (rc) {
+ pr_err("error = %d writing USB_OVP_TRIM\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, sbi_config);
+ if (rc) {
+ pr_err("error = %d writing sbi config reg\n", rc);
+ return rc;
+ }
+ return rc;
+}
+
#define PM8921_CHG_IUSB_MASK 0x1C
#define PM8921_CHG_IUSB_SHIFT 2
#define PM8921_CHG_IUSB_MAX 7
#define PM8921_CHG_IUSB_MIN 0
#define PM8917_IUSB_FINE_RES BIT(0)
-static int pm_chg_iusbmax_set(struct pm8921_chg_chip *chip, int reg_val)
+static int pm_chg_iusbmax_set(struct pm8921_chg_chip *chip, int index)
{
- u8 temp, fineres;
+ u8 temp, fineres, reg_val;
int rc;
- fineres = PM8917_IUSB_FINE_RES & usb_ma_table[reg_val].value;
- reg_val = usb_ma_table[reg_val].value >> 1;
+ reg_val = usb_ma_table[index].value >> 1;
+ fineres = PM8917_IUSB_FINE_RES & usb_ma_table[index].value;
if (reg_val < PM8921_CHG_IUSB_MIN || reg_val > PM8921_CHG_IUSB_MAX) {
pr_err("bad mA=%d asked to set\n", reg_val);
@@ -764,17 +896,25 @@
if (fineres) {
rc = pm_chg_masked_write(chip, IUSB_FINE_RES,
PM8917_IUSB_FINE_RES, fineres);
- if (rc)
+ if (rc) {
pr_err("Failed to write ISUB_FINE_RES rc=%d\n",
rc);
+ return rc;
+ }
}
} else {
rc = pm_chg_masked_write(chip, PBL_ACCESS2,
PM8921_CHG_IUSB_MASK, temp);
- if (rc)
+ if (rc) {
pr_err("Failed to write PBL_ACCESS2 rc=%d\n", rc);
+ return rc;
+ }
}
+ rc = pm_chg_usb_trim(chip, index);
+ if (rc)
+ pr_err("unable to set usb trim rc = %d\n", rc);
+
return rc;
}
@@ -1354,6 +1494,7 @@
POWER_SUPPLY_PROP_CURRENT_NOW,
POWER_SUPPLY_PROP_TEMP,
POWER_SUPPLY_PROP_ENERGY_FULL,
+ POWER_SUPPLY_PROP_CHARGE_NOW,
};
static int get_prop_battery_uvolts(struct pm8921_chg_chip *chip)
@@ -1489,6 +1630,20 @@
return rc;
}
+static int get_prop_batt_charge_now(struct pm8921_chg_chip *chip)
+{
+ int rc;
+ int cc_uah;
+
+ rc = pm8921_bms_cc_uah(&cc_uah);
+
+ if (rc == 0)
+ return cc_uah;
+
+ pr_err("unable to get batt fcc rc = %d\n", rc);
+ return rc;
+}
+
static int get_prop_batt_health(struct pm8921_chg_chip *chip)
{
int temp;
@@ -1627,6 +1782,9 @@
case POWER_SUPPLY_PROP_ENERGY_FULL:
val->intval = get_prop_batt_fcc(chip) * 1000;
break;
+ case POWER_SUPPLY_PROP_CHARGE_NOW:
+ val->intval = get_prop_batt_charge_now(chip);
+ break;
default:
return -EINVAL;
}
@@ -1699,9 +1857,8 @@
if (i < 0)
i = 0;
rc = pm_chg_iusbmax_set(the_chip, i);
- if (rc) {
+ if (rc)
pr_err("unable to set iusb to %d rc = %d\n", i, rc);
- }
}
}
@@ -2673,8 +2830,8 @@
goto check_again_later;
}
}
-
- if (active_path & USB_ACTIVE_BIT) {
+ /* AICL only for usb wall charger */
+ if ((active_path & USB_ACTIVE_BIT) && usb_target_ma > 0) {
reg_loop = pm_chg_get_regulation_loop(chip);
pr_debug("reg_loop=0x%x usb_ma = %d\n", reg_loop, usb_ma);
if ((reg_loop & VIN_ACTIVE_BIT) &&
@@ -2719,7 +2876,9 @@
unplug_ovp_fet_open(chip);
}
+ /* AICL only for usb wall charger */
if (!(reg_loop & VIN_ACTIVE_BIT) && (active_path & USB_ACTIVE_BIT)
+ && usb_target_ma > 0
&& !charging_disabled) {
/* only increase iusb_max if vin loop not active */
if (usb_ma < usb_target_ma) {
@@ -2749,6 +2908,30 @@
return IRQ_HANDLED;
}
+struct ibatmax_max_adj_entry {
+ int ibat_max_ma;
+ int max_adj_ma;
+};
+
+static struct ibatmax_max_adj_entry ibatmax_adj_table[] = {
+ {975, 300},
+ {1475, 150},
+ {1975, 200},
+ {2475, 250},
+};
+
+static int find_ibat_max_adj_ma(int ibat_target_ma)
+{
+ int i = 0;
+
+ for (i = ARRAY_SIZE(ibatmax_adj_table) - 1; i >= 0; i--) {
+ if (ibat_target_ma <= ibatmax_adj_table[i].ibat_max_ma)
+ break;
+ }
+
+ return ibatmax_adj_table[i].max_adj_ma;
+}
+
static irqreturn_t fastchg_irq_handler(int irq, void *data)
{
struct pm8921_chg_chip *chip = data;
@@ -3533,6 +3716,12 @@
chip->dc_present,
get_prop_batt_present(chip),
fsm_state);
+
+ /* Determine which USB trim column to use */
+ if (pm8xxx_get_version(chip->dev->parent) == PM8XXX_VERSION_8917)
+ chip->usb_trim_table = usb_trim_8917_table;
+ else if (pm8xxx_get_version(chip->dev->parent) == PM8XXX_VERSION_8038)
+ chip->usb_trim_table = usb_trim_8038_table;
}
struct pm_chg_irq_init_data {
@@ -3739,11 +3928,15 @@
#define CHG_BAT_TEMP_DIS_BIT BIT(2)
#define SAFE_CURRENT_MA 1500
#define PM_SUB_REV 0x001
+#define MIN_CHARGE_CURRENT_MA 350
+#define DEFAULT_SAFETY_MINUTES 500
static int __devinit pm8921_chg_hw_init(struct pm8921_chg_chip *chip)
{
int rc;
int vdd_safe;
u8 subrev;
+ int fcc_uah;
+ int safety_time = DEFAULT_SAFETY_MINUTES;
/* forcing 19p2mhz before accessing any charger registers */
pm8921_chg_force_19p2mhz_clk(chip);
@@ -3784,7 +3977,11 @@
chip->max_voltage_mv, rc);
return rc;
}
- rc = pm_chg_ibatsafe_set(chip, SAFE_CURRENT_MA);
+
+ if (chip->safe_current_ma == 0)
+ chip->safe_current_ma = SAFE_CURRENT_MA;
+
+ rc = pm_chg_ibatsafe_set(chip, chip->safe_current_ma);
if (rc) {
pr_err("Failed to set max voltage to %d rc=%d\n",
SAFE_CURRENT_MA, rc);
@@ -3812,20 +4009,26 @@
return rc;
}
- if (chip->safety_time != 0) {
- rc = pm_chg_tchg_max_set(chip, chip->safety_time);
- if (rc) {
- pr_err("Failed to set max time to %d minutes rc=%d\n",
- chip->safety_time, rc);
- return rc;
- }
+ fcc_uah = pm8921_bms_get_fcc();
+ if (fcc_uah > 0) {
+ safety_time = div_s64((s64)fcc_uah * 60,
+ 1000 * MIN_CHARGE_CURRENT_MA);
+ /* add 20 minutes of buffer time */
+ safety_time += 20;
+ }
+
+ rc = pm_chg_tchg_max_set(chip, safety_time);
+ if (rc) {
+ pr_err("Failed to set max time to %d minutes rc=%d\n",
+ safety_time, rc);
+ return rc;
}
if (chip->ttrkl_time != 0) {
rc = pm_chg_ttrkl_max_set(chip, chip->ttrkl_time);
if (rc) {
pr_err("Failed to set trkl time to %d minutes rc=%d\n",
- chip->safety_time, rc);
+ chip->ttrkl_time, rc);
return rc;
}
}
@@ -4045,6 +4248,81 @@
}
DEFINE_SIMPLE_ATTRIBUTE(reg_fops, get_reg, set_reg, "0x%02llx\n");
+static int reg_loop;
+#define MAX_REG_LOOP_CHAR 10
+static int get_reg_loop_param(char *buf, struct kernel_param *kp)
+{
+ u8 temp;
+
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+ temp = pm_chg_get_regulation_loop(the_chip);
+ return snprintf(buf, MAX_REG_LOOP_CHAR, "%d", temp);
+}
+module_param_call(reg_loop, NULL, get_reg_loop_param,
+ ®_loop, 0644);
+
+static int max_chg_ma;
+#define MAX_MA_CHAR 10
+static int get_max_chg_ma_param(char *buf, struct kernel_param *kp)
+{
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+ return snprintf(buf, MAX_MA_CHAR, "%d", the_chip->max_bat_chg_current);
+}
+module_param_call(max_chg_ma, NULL, get_max_chg_ma_param,
+ &max_chg_ma, 0644);
+static int ibatmax_ma;
+static int set_ibat_max(const char *val, struct kernel_param *kp)
+{
+ int rc;
+
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+
+ rc = param_set_int(val, kp);
+ if (rc) {
+ pr_err("error setting value %d\n", rc);
+ return rc;
+ }
+
+ if (abs(ibatmax_ma - the_chip->max_bat_chg_current)
+ <= the_chip->ibatmax_max_adj_ma) {
+ rc = pm_chg_ibatmax_set(the_chip, ibatmax_ma);
+ if (rc) {
+ pr_err("Failed to set ibatmax rc = %d\n", rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+static int get_ibat_max(char *buf, struct kernel_param *kp)
+{
+ int ibat_ma;
+ int rc;
+
+ if (!the_chip) {
+ pr_err("called before init\n");
+ return -EINVAL;
+ }
+
+ rc = pm_chg_ibatmax_get(the_chip, &ibat_ma);
+ if (rc) {
+ pr_err("ibatmax_get error = %d\n", rc);
+ return rc;
+ }
+
+ return snprintf(buf, MAX_MA_CHAR, "%d", ibat_ma);
+}
+module_param_call(ibatmax_ma, set_ibat_max, get_ibat_max,
+ &ibatmax_ma, 0644);
enum {
BAT_WARM_ZONE,
BAT_COOL_ZONE,
@@ -4231,13 +4509,13 @@
}
chip->dev = &pdev->dev;
- chip->safety_time = pdata->safety_time;
chip->ttrkl_time = pdata->ttrkl_time;
chip->update_time = pdata->update_time;
chip->max_voltage_mv = pdata->max_voltage;
chip->alarm_low_mv = pdata->alarm_low_mv;
chip->alarm_high_mv = pdata->alarm_high_mv;
chip->min_voltage_mv = pdata->min_voltage;
+ chip->safe_current_ma = pdata->safe_current_ma;
chip->uvd_voltage_mv = pdata->uvd_thresh_voltage;
chip->resume_voltage_delta = pdata->resume_voltage_delta;
chip->resume_charge_percent = pdata->resume_charge_percent;
@@ -4283,6 +4561,9 @@
if (chip->battery_less_hardware)
charging_disabled = 1;
+ chip->ibatmax_max_adj_ma = find_ibat_max_adj_ma(
+ chip->max_bat_chg_current);
+
rc = pm8921_chg_hw_init(chip);
if (rc) {
pr_err("couldn't init hardware rc=%d\n", rc);
@@ -4339,6 +4620,11 @@
vin_collapse_check_worker);
INIT_DELAYED_WORK(&chip->unplug_check_work, unplug_check_worker);
+ INIT_WORK(&chip->bms_notify.work, bms_notify);
+ INIT_WORK(&chip->battery_id_valid_work, battery_id_valid);
+
+ INIT_DELAYED_WORK(&chip->update_heartbeat_work, update_heartbeat);
+
rc = request_irqs(chip, pdev);
if (rc) {
pr_err("couldn't register interrupts rc=%d\n", rc);
@@ -4375,19 +4661,13 @@
}
create_debugfs_entries(chip);
- INIT_WORK(&chip->bms_notify.work, bms_notify);
- INIT_WORK(&chip->battery_id_valid_work, battery_id_valid);
-
/* determine what state the charger is in */
determine_initial_state(chip);
- if (chip->update_time) {
- INIT_DELAYED_WORK(&chip->update_heartbeat_work,
- update_heartbeat);
+ if (chip->update_time)
schedule_delayed_work(&chip->update_heartbeat_work,
round_jiffies_relative(msecs_to_jiffies
(chip->update_time)));
- }
return 0;
free_irq:
diff --git a/drivers/power/pm8xxx-ccadc.c b/drivers/power/pm8xxx-ccadc.c
index 1b9426a..a586f3d8 100644
--- a/drivers/power/pm8xxx-ccadc.c
+++ b/drivers/power/pm8xxx-ccadc.c
@@ -72,7 +72,7 @@
unsigned int revision;
unsigned int calib_delay_ms;
int eoc_irq;
- int r_sense;
+ int r_sense_uohm;
struct delayed_work calib_ccadc_work;
};
@@ -562,7 +562,8 @@
return rc;
}
- *bat_current_ua = voltage_uv * 1000/the_chip->r_sense;
+ *bat_current_ua = div_s64((s64)voltage_uv * 1000000LL,
+ the_chip->r_sense_uohm);
/*
* ccadc reads +ve current when the battery is charging
* We need to return -ve if the battery is charging
@@ -675,7 +676,7 @@
chip->dev = &pdev->dev;
chip->revision = pm8xxx_get_revision(chip->dev->parent);
chip->eoc_irq = res->start;
- chip->r_sense = pdata->r_sense;
+ chip->r_sense_uohm = pdata->r_sense_uohm;
chip->calib_delay_ms = pdata->calib_delay_ms;
calib_ccadc_read_offset_and_gain(chip,
diff --git a/drivers/power/qpnp-bms.c b/drivers/power/qpnp-bms.c
index 7b4d97e..1955ff4 100644
--- a/drivers/power/qpnp-bms.c
+++ b/drivers/power/qpnp-bms.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,7 +10,7 @@
* GNU General Public License for more details.
*/
-#define pr_fmt(fmt) "%s: " fmt, __func__
+#define pr_fmt(fmt) "BMS: %s: " fmt, __func__
#include <linux/module.h>
#include <linux/types.h>
@@ -21,26 +21,17 @@
#include <linux/of_device.h>
#include <linux/power_supply.h>
#include <linux/spmi.h>
-
-/* Interrupt offsets */
-#define INT_RT_STS(base) (base + 0x10)
-#define INT_SET_TYPE(base) (base + 0x11)
-#define INT_POLARITY_HIGH(base) (base + 0x12)
-#define INT_POLARITY_LOW(base) (base + 0x13)
-#define INT_LATCHED_CLR(base) (base + 0x14)
-#define INT_EN_SET(base) (base + 0x15)
-#define INT_EN_CLR(base) (base + 0x16)
-#define INT_LATCHED_STS(base) (base + 0x18)
-#define INT_PENDING_STS(base) (base + 0x19)
-#define INT_MID_SEL(base) (base + 0x1A)
-#define INT_PRIORITY(base) (base + 0x1B)
+#include <linux/rtc.h>
+#include <linux/delay.h>
+#include <linux/qpnp/qpnp-adc.h>
+#include <linux/mfd/pm8xxx/batterydata-lib.h>
/* BMS Register Offsets */
#define BMS1_REVISION1 0x0
#define BMS1_REVISION2 0x1
#define BMS1_STATUS1 0x8
#define BMS1_MODE_CTL 0X40
-/* Columb counter clear registers */
+/* Coulomb counter clear registers */
#define BMS1_CC_DATA_CTL 0x42
#define BMS1_CC_CLEAR_CTRL 0x43
/* OCV limit registers */
@@ -49,6 +40,8 @@
#define BMS1_OCV_USE_HIGH_LIMIT_THR0 0x4A
#define BMS1_OCV_USE_HIGH_LIMIT_THR1 0x4B
#define BMS1_OCV_USE_LIMIT_CTL 0x4C
+/* Delay control */
+#define BMS1_S1_DELAY_CTL 0x5A
/* CC interrupt threshold */
#define BMS1_CC_THR0 0x7A
#define BMS1_CC_THR1 0x7B
@@ -60,7 +53,7 @@
#define BMS1_OCV_FOR_R_DATA1 0x81
#define BMS1_VSENSE_FOR_R_DATA0 0x82
#define BMS1_VSENSE_FOR_R_DATA1 0x83
-/* Columb counter data */
+/* Coulomb counter data */
#define BMS1_CC_DATA0 0x8A
#define BMS1_CC_DATA1 0x8B
#define BMS1_CC_DATA2 0x8C
@@ -71,19 +64,45 @@
#define BMS1_OCV_FOR_SOC_DATA1 0x91
#define BMS1_VSENSE_PON_DATA0 0x94
#define BMS1_VSENSE_PON_DATA1 0x95
+#define BMS1_VSENSE_AVG_DATA0 0x98
+#define BMS1_VSENSE_AVG_DATA1 0x99
#define BMS1_VBAT_AVG_DATA0 0x9E
#define BMS1_VBAT_AVG_DATA1 0x9F
/* Extra bms registers */
#define BMS1_BMS_DATA_REG_0 0xB0
-#define BMS1_BMS_DATA_REG_1 0xB1
-#define BMS1_BMS_DATA_REG_2 0xB2
+#define IAVG_STORAGE_REG 0xB1
+#define SOC_STORAGE_REG 0xB2
#define BMS1_BMS_DATA_REG_3 0xB3
+/* Configuration for saving of shutdown soc/iavg */
+#define IGNORE_SOC_TEMP_DECIDEG 50
+#define IAVG_STEP_SIZE_MA 50
+#define IAVG_START 600
+#define SOC_ZERO 0xFF
+
+#define IAVG_SAMPLES 16
+
#define QPNP_BMS_DEV_NAME "qcom,qpnp-bms"
+struct soc_params {
+ int fcc_uah;
+ int cc_uah;
+ int rbatt;
+ int iavg_ua;
+ int uuc_uah;
+ int ocv_charge_uah;
+};
+
+struct raw_soc_params {
+ uint16_t last_good_ocv_raw;
+ int64_t cc;
+ int last_good_ocv_uv;
+};
+
struct qpnp_bms_chip {
struct device *dev;
struct power_supply bms_psy;
+ struct power_supply *batt_psy;
struct spmi_device *spmi;
u16 base;
@@ -93,13 +112,71 @@
bool online;
/* platform data */
unsigned int r_sense_mohm;
- unsigned int v_cutoff;
- unsigned int max_voltage;
+ unsigned int v_cutoff_uv;
+ unsigned int max_voltage_uv;
unsigned int r_conn_mohm;
int shutdown_soc_valid_limit;
int adjust_soc_low_threshold;
int adjust_soc_high_threshold;
- int chg_term;
+ int chg_term_ua;
+ enum battery_type batt_type;
+ unsigned int fcc;
+ struct single_row_lut *fcc_temp_lut;
+ struct single_row_lut *fcc_sf_lut;
+ struct pc_temp_ocv_lut *pc_temp_ocv_lut;
+ struct sf_lut *pc_sf_lut;
+ struct sf_lut *rbatt_sf_lut;
+ int default_rbatt_mohm;
+
+ struct delayed_work calculate_soc_delayed_work;
+
+ struct mutex bms_output_lock;
+ struct mutex last_ocv_uv_mutex;
+ struct mutex soc_invalidation_mutex;
+
+ unsigned int start_percent;
+ unsigned int end_percent;
+ bool ignore_shutdown_soc;
+ int shutdown_soc_invalid;
+ int shutdown_soc;
+ int shutdown_iavg_ma;
+
+ int low_soc_calc_threshold;
+ int low_soc_calculate_soc_ms;
+ int calculate_soc_ms;
+
+ uint16_t ocv_reading_at_100;
+ int64_t cc_reading_at_100;
+ uint16_t prev_last_good_ocv_raw;
+ int last_ocv_uv;
+ int last_cc_uah;
+ unsigned long tm_sec;
+ bool first_time_calc_soc;
+ bool first_time_calc_uuc;
+ int pon_ocv_uv;
+
+ int iavg_samples_ma[IAVG_SAMPLES];
+ int iavg_index;
+ int iavg_num_samples;
+ struct timespec t_soc_queried;
+ int last_soc;
+ int last_soc_est;
+
+ int charge_time_us;
+ int catch_up_time_us;
+ struct single_row_lut *adjusted_fcc_temp_lut;
+
+ unsigned int vadc_v0625;
+ unsigned int vadc_v1250;
+
+ int prev_iavg_ua;
+ int prev_uuc_iavg_ma;
+ int prev_pc_unusable;
+ int ibat_at_cv_ua;
+ int soc_at_cv;
+ int prev_chg_soc;
+ int calculated_soc;
+ int last_vbat_read_uv;
};
static struct of_device_id qpnp_bms_match_table[] = {
@@ -119,6 +196,38 @@
POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
};
+static bool use_voltage_soc;
+
+/* module params */
+static int bms_param_set_bool(const char *val, const struct kernel_param *kp)
+{
+ int rc;
+ struct power_supply *bms_psy;
+
+ rc = param_set_bool(val, kp);
+ if (rc) {
+ pr_err("failed to set %s, rc = %d\n", kp->name, rc);
+ return rc;
+ }
+
+ bms_psy = power_supply_get_by_name("bms");
+
+ if (bms_psy)
+ power_supply_changed(bms_psy);
+ else
+ pr_debug("%s changed but bms has not been initialized yet\n",
+ kp->name);
+
+ return 0;
+}
+
+static struct kernel_param_ops bms_param_ops = {
+ .set = bms_param_set_bool,
+ .get = param_get_bool,
+};
+
+module_param_cb(use_voltage_soc, &bms_param_ops, &use_voltage_soc, 0644);
+
static int qpnp_read_wrapper(struct qpnp_bms_chip *chip, u8 *val,
u16 base, int count)
{
@@ -126,31 +235,1420 @@
struct spmi_device *spmi = chip->spmi;
rc = spmi_ext_register_readl(spmi->ctrl, spmi->sid, base, val, count);
- if (rc)
+ if (rc) {
pr_err("SPMI read failed rc=%d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int qpnp_write_wrapper(struct qpnp_bms_chip *chip, u8 *val,
+ u16 base, int count)
+{
+ int rc;
+ struct spmi_device *spmi = chip->spmi;
+
+ rc = spmi_ext_register_writel(spmi->ctrl, spmi->sid, base, val, count);
+ if (rc) {
+ pr_err("SPMI write failed rc=%d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int qpnp_masked_write(struct qpnp_bms_chip *chip, u16 addr,
+ u8 mask, u8 val)
+{
+ int rc;
+ u8 reg;
+
+ rc = qpnp_read_wrapper(chip, ®, chip->base + addr, 1);
+ if (rc) {
+ pr_err("read failed addr = %03X, rc = %d\n",
+ chip->base + addr, rc);
+ return rc;
+ }
+ reg &= ~mask;
+ reg |= val & mask;
+ rc = qpnp_write_wrapper(chip, ®, chip->base + addr, 1);
+ if (rc) {
+ pr_err("write failed addr = %03X, val = %02x, mask = %02x, reg = %02x, rc = %d\n",
+ chip->base + addr, val, mask, reg, rc);
+ return rc;
+ }
+ return 0;
+}
+
+#define HOLD_OREG_DATA BIT(0)
+static int lock_output_data(struct qpnp_bms_chip *chip)
+{
+ int rc;
+
+ rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL,
+ HOLD_OREG_DATA, HOLD_OREG_DATA);
+ if (rc) {
+ pr_err("couldnt lock bms output rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int unlock_output_data(struct qpnp_bms_chip *chip)
+{
+ int rc;
+
+ rc = qpnp_masked_write(chip, BMS1_CC_DATA_CTL, HOLD_OREG_DATA, 0);
+ if (rc) {
+ pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+#define V_PER_BIT_MUL_FACTOR 97656
+#define V_PER_BIT_DIV_FACTOR 1000
+#define VADC_INTRINSIC_OFFSET 0x6000
+
+static int vadc_reading_to_uv(unsigned int reading)
+{
+ if (reading <= VADC_INTRINSIC_OFFSET)
+ return 0;
+
+ return (reading - VADC_INTRINSIC_OFFSET)
+ * V_PER_BIT_MUL_FACTOR / V_PER_BIT_DIV_FACTOR;
+}
+
+#define VADC_CALIB_UV 625000
+#define VBATT_MUL_FACTOR 3
+
+static int adjust_vbatt_reading(struct qpnp_bms_chip *chip,
+ unsigned int reading_uv)
+{
+ s64 numerator, denominator;
+
+ if (reading_uv == 0)
+ return 0;
+
+ /* don't adjust if not calibrated */
+ if (chip->vadc_v0625 == 0 || chip->vadc_v1250 == 0) {
+ pr_debug("No cal yet return %d\n",
+ VBATT_MUL_FACTOR * reading_uv);
+ return VBATT_MUL_FACTOR * reading_uv;
+ }
+
+ numerator = ((s64)reading_uv - chip->vadc_v0625) * VADC_CALIB_UV;
+ denominator = (s64)chip->vadc_v1250 - chip->vadc_v0625;
+ if (denominator == 0)
+ return reading_uv * VBATT_MUL_FACTOR;
+ return (VADC_CALIB_UV + div_s64(numerator, denominator))
+ * VBATT_MUL_FACTOR;
+}
+
+static inline int convert_vbatt_raw_to_uv(struct qpnp_bms_chip *chip,
+ uint16_t reading)
+{
+ int uv;
+
+ uv = vadc_reading_to_uv(reading);
+ pr_debug("%u raw converted into %d uv\n", reading, uv);
+ uv = adjust_vbatt_reading(chip, uv);
+ pr_debug("adjusted into %d uv\n", uv);
+ return uv;
+}
+
+#define CC_READING_RESOLUTION_N 542535
+#define CC_READING_RESOLUTION_D 100000
+static int cc_reading_to_uv(int16_t reading)
+{
+ return div_s64(reading * CC_READING_RESOLUTION_N,
+ CC_READING_RESOLUTION_D);
+}
+
+#define QPNP_ADC_GAIN_NV 17857LL
+static s64 cc_adjust_for_gain(s64 uv, uint16_t gain)
+{
+ s64 result_uv;
+
+ pr_debug("adjusting_uv = %lld\n", uv);
+ pr_debug("adjusting by factor: %lld/%hu = %lld%%\n",
+ QPNP_ADC_GAIN_NV, gain,
+ div_s64(QPNP_ADC_GAIN_NV * 100LL, (s64)gain));
+
+ result_uv = div_s64(uv * QPNP_ADC_GAIN_NV, (s64)gain);
+ pr_debug("result_uv = %lld\n", result_uv);
+ return result_uv;
+}
+
+static int convert_vsense_to_uv(struct qpnp_bms_chip *chip,
+ int16_t reading)
+{
+ struct qpnp_iadc_calib calibration;
+
+ qpnp_iadc_get_gain_and_offset(&calibration);
+ return cc_adjust_for_gain(cc_reading_to_uv(reading),
+ calibration.gain_raw);
+}
+
+static int read_vsense_avg(struct qpnp_bms_chip *chip, int *result_uv)
+{
+ int rc;
+ int16_t reading;
+
+ rc = qpnp_read_wrapper(chip, (u8 *)&reading,
+ chip->base + BMS1_VSENSE_AVG_DATA0, 2);
+
+ if (rc) {
+ pr_err("fail to read VSENSE_AVG rc = %d\n", rc);
+ return rc;
+ }
+
+ *result_uv = convert_vsense_to_uv(chip, reading);
+ return 0;
+}
+
+static int get_battery_current(struct qpnp_bms_chip *chip, int *result_ua)
+{
+ int vsense_uv = 0;
+
+ if (chip->r_sense_mohm == 0) {
+ pr_err("r_sense is zero\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&chip->bms_output_lock);
+ lock_output_data(chip);
+ read_vsense_avg(chip, &vsense_uv);
+ unlock_output_data(chip);
+ mutex_unlock(&chip->bms_output_lock);
+
+ pr_debug("vsense_uv=%duV\n", vsense_uv);
+ /* cast for signed division */
+ *result_ua = vsense_uv * 1000 / (int)chip->r_sense_mohm;
+ pr_debug("ibat=%duA\n", *result_ua);
+ return 0;
+}
+
+static int get_battery_voltage(int *result_uv)
+{
+ int rc;
+ struct qpnp_vadc_result adc_result;
+
+ rc = qpnp_vadc_read(VBAT_SNS, &adc_result);
+ if (rc) {
+ pr_err("error reading adc channel = %d, rc = %d\n",
+ VBAT_SNS, rc);
+ return rc;
+ }
+ pr_debug("mvolts phy = %lld meas = 0x%llx\n", adc_result.physical,
+ adc_result.measurement);
+ *result_uv = (int)adc_result.physical;
+ return 0;
+}
+
+#define CC_36_BIT_MASK 0xFFFFFFFFFLL
+
+static int read_cc_raw(struct qpnp_bms_chip *chip, int64_t *reading)
+{
+ int64_t raw_reading;
+ int rc;
+
+ rc = qpnp_read_wrapper(chip, (u8 *)&raw_reading,
+ chip->base + BMS1_CC_DATA0, 5);
+ if (rc) {
+ pr_err("Error reading cc: rc = %d\n", rc);
+ return -ENXIO;
+ }
+
+ raw_reading = raw_reading & CC_36_BIT_MASK;
+ /* convert 36 bit signed value into 64 signed value */
+ *reading = (raw_reading >> 35) == 0LL ?
+ raw_reading : ((-1LL ^ CC_36_BIT_MASK) | raw_reading);
+ pr_debug("before conversion: %llx, after conversion: %llx\n",
+ raw_reading, *reading);
return 0;
}
+static int calib_vadc(struct qpnp_bms_chip *chip)
+{
+ int rc;
+ struct qpnp_vadc_result result;
+
+ rc = qpnp_vadc_read(REF_625MV, &result);
+ if (rc) {
+ pr_debug("vadc read failed with rc = %d\n", rc);
+ return rc;
+ }
+ chip->vadc_v0625 = result.physical;
+
+ rc = qpnp_vadc_read(REF_125V, &result);
+ if (rc) {
+ pr_debug("vadc read failed with rc = %d\n", rc);
+ return rc;
+ }
+ chip->vadc_v1250 = result.physical;
+ pr_debug("vadc calib: 0625 = %d, 1250 = %d\n",
+ chip->vadc_v0625, chip->vadc_v1250);
+ return 0;
+}
+
+static void convert_and_store_ocv(struct qpnp_bms_chip *chip,
+ struct raw_soc_params *raw)
+{
+ int rc;
+
+ pr_debug("prev_last_good_ocv_raw = %d, last_good_ocv_raw = %d\n",
+ chip->prev_last_good_ocv_raw,
+ raw->last_good_ocv_raw);
+ rc = calib_vadc(chip);
+ if (rc)
+ pr_err("Vadc reference voltage read failed, rc = %d\n", rc);
+ chip->prev_last_good_ocv_raw = raw->last_good_ocv_raw;
+ raw->last_good_ocv_uv = convert_vbatt_raw_to_uv(chip,
+ raw->last_good_ocv_raw);
+ chip->last_ocv_uv = raw->last_good_ocv_uv;
+ pr_debug("last_good_ocv_uv = %d\n", raw->last_good_ocv_uv);
+}
+
+static int read_soc_params_raw(struct qpnp_bms_chip *chip,
+ struct raw_soc_params *raw)
+{
+ int rc;
+
+ mutex_lock(&chip->bms_output_lock);
+ lock_output_data(chip);
+
+ rc = qpnp_read_wrapper(chip, (u8 *)&raw->last_good_ocv_raw,
+ chip->base + BMS1_OCV_FOR_SOC_DATA0, 2);
+ if (rc) {
+ pr_err("Error reading ocv: rc = %d\n", rc);
+ return -ENXIO;
+ }
+
+ rc = read_cc_raw(chip, &raw->cc);
+ if (rc) {
+ pr_err("Failed to read raw cc data, rc = %d\n", rc);
+ return rc;
+ }
+
+ unlock_output_data(chip);
+ mutex_unlock(&chip->bms_output_lock);
+
+ if (chip->prev_last_good_ocv_raw == 0) {
+ convert_and_store_ocv(chip, raw);
+ pr_debug("PON_OCV_UV = %d\n", chip->last_ocv_uv);
+ } else if (chip->prev_last_good_ocv_raw != raw->last_good_ocv_raw) {
+ convert_and_store_ocv(chip, raw);
+ /* forget the old cc value upon ocv */
+ chip->last_cc_uah = 0;
+ } else {
+ raw->last_good_ocv_uv = chip->last_ocv_uv;
+ }
+
+ /* fake a high OCV if done charging */
+ if (chip->ocv_reading_at_100 != raw->last_good_ocv_raw) {
+ chip->ocv_reading_at_100 = 0;
+ chip->cc_reading_at_100 = 0;
+ } else {
+ /*
+ * force 100% ocv by selecting the highest voltage the
+ * battery could ever reach
+ */
+ raw->last_good_ocv_uv = chip->max_voltage_uv;
+ chip->last_ocv_uv = chip->max_voltage_uv;
+ }
+ pr_debug("last_good_ocv_raw= 0x%x, last_good_ocv_uv= %duV\n",
+ raw->last_good_ocv_raw, raw->last_good_ocv_uv);
+ pr_debug("cc_raw= 0x%llx\n", raw->cc);
+ return 0;
+}
+
+static int calculate_pc(struct qpnp_bms_chip *chip, int ocv_uv,
+ int batt_temp)
+{
+ int pc;
+
+ pc = interpolate_pc(chip->pc_temp_ocv_lut,
+ batt_temp / 10, ocv_uv / 1000);
+ pr_debug("pc = %u %% for ocv = %d uv batt_temp = %d\n",
+ pc, ocv_uv, batt_temp);
+ /* Multiply the initial FCC value by the scale factor. */
+ return pc;
+}
+
+static int calculate_fcc(struct qpnp_bms_chip *chip, int batt_temp)
+{
+ int fcc_uah;
+
+ if (chip->adjusted_fcc_temp_lut == NULL) {
+ /* interpolate_fcc returns a mv value. */
+ fcc_uah = interpolate_fcc(chip->fcc_temp_lut,
+ batt_temp) * 1000;
+ pr_debug("fcc = %d uAh\n", fcc_uah);
+ return fcc_uah;
+ } else {
+ return 1000 * interpolate_fcc(chip->adjusted_fcc_temp_lut,
+ batt_temp);
+ }
+}
+
+/* calculate remaining charge at the time of ocv */
+static int calculate_ocv_charge(struct qpnp_bms_chip *chip,
+ struct raw_soc_params *raw,
+ int fcc_uah,
+ int batt_temp)
+{
+ int ocv_uv, pc;
+
+ ocv_uv = raw->last_good_ocv_uv;
+ pc = calculate_pc(chip, ocv_uv, batt_temp);
+ pr_debug("ocv_uv = %d pc = %d\n", ocv_uv, pc);
+ return (fcc_uah * pc) / 100;
+}
+
+#define CC_RESOLUTION_N 542535
+#define CC_RESOLUTION_D 100000
+
+static s64 cc_to_uv(s64 cc)
+{
+ return div_s64(cc * CC_RESOLUTION_N, CC_RESOLUTION_D);
+}
+
+#define CC_READING_TICKS 56
+#define SLEEP_CLK_HZ 32764
+#define SECONDS_PER_HOUR 3600
+
+static s64 cc_uv_to_nvh(s64 cc_uv)
+{
+ return div_s64(cc_uv * CC_READING_TICKS * 1000,
+ SLEEP_CLK_HZ * SECONDS_PER_HOUR);
+}
+
+/**
+ * calculate_cc-
+ * @chip: the bms chip pointer
+ * @cc: the cc reading from bms h/w
+ * @val: return value
+ * @coulomb_counter: adjusted coulomb counter for 100%
+ *
+ * RETURNS: in val pointer coulomb counter based charger in uAh
+ * (micro Amp hour)
+ */
+static int calculate_cc(struct qpnp_bms_chip *chip, int64_t cc)
+{
+ int64_t cc_voltage_uv, cc_nvh, cc_uah;
+ struct qpnp_iadc_calib calibration;
+
+ qpnp_iadc_get_gain_and_offset(&calibration);
+ cc_voltage_uv = cc;
+ cc_voltage_uv -= chip->cc_reading_at_100;
+ pr_debug("cc = %lld. after subtracting 0x%llx cc = %lld\n",
+ cc, chip->cc_reading_at_100,
+ cc_voltage_uv);
+ cc_voltage_uv = cc_to_uv(cc_voltage_uv);
+ cc_voltage_uv = cc_adjust_for_gain(cc_voltage_uv, calibration.gain_raw);
+ pr_debug("cc_voltage_uv = %lld uv\n", cc_voltage_uv);
+ cc_nvh = cc_uv_to_nvh(cc_voltage_uv);
+ pr_debug("cc_nvh = %lld nano_volt_hour\n", cc_nvh);
+ cc_uah = div_s64(cc_nvh, chip->r_sense_mohm);
+ /* cc_raw had 4 bits of extra precision.
+ By now it should be within 32 bit range */
+ return (int)cc_uah;
+}
+
+static int get_rbatt(struct qpnp_bms_chip *chip,
+ int soc_rbatt_mohm, int batt_temp)
+{
+ int rbatt_mohm, scalefactor;
+
+ rbatt_mohm = chip->default_rbatt_mohm;
+ pr_debug("rbatt before scaling = %d\n", rbatt_mohm);
+ if (chip->rbatt_sf_lut == NULL) {
+ pr_debug("RBATT = %d\n", rbatt_mohm);
+ return rbatt_mohm;
+ }
+ /* Convert the batt_temp to DegC from deciDegC */
+ batt_temp = batt_temp / 10;
+ scalefactor = interpolate_scalingfactor(chip->rbatt_sf_lut,
+ batt_temp, soc_rbatt_mohm);
+ pr_debug("rbatt sf = %d for batt_temp = %d, soc_rbatt = %d\n",
+ scalefactor, batt_temp, soc_rbatt_mohm);
+ rbatt_mohm = (rbatt_mohm * scalefactor) / 100;
+
+ rbatt_mohm += chip->r_conn_mohm;
+ pr_debug("adding r_conn_mohm = %d rbatt = %d\n",
+ chip->r_conn_mohm, rbatt_mohm);
+
+ pr_debug("RBATT = %d\n", rbatt_mohm);
+ return rbatt_mohm;
+}
+
+static void calculate_iavg(struct qpnp_bms_chip *chip, int cc_uah,
+ int *iavg_ua)
+{
+ int delta_cc_uah, delta_time_s, rc;
+ struct rtc_time tm;
+ struct rtc_device *rtc;
+ unsigned long now_tm_sec = 0;
+
+ rc = 0;
+ /* if anything fails report the previous iavg_ua */
+ *iavg_ua = chip->prev_iavg_ua;
+
+ rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE);
+ if (rtc == NULL) {
+ pr_err("%s: unable to open rtc device (%s)\n",
+ __FILE__, CONFIG_RTC_HCTOSYS_DEVICE);
+ goto out;
+ }
+
+ rc = rtc_read_time(rtc, &tm);
+ if (rc) {
+ pr_err("Error reading rtc device (%s) : %d\n",
+ CONFIG_RTC_HCTOSYS_DEVICE, rc);
+ goto out;
+ }
+
+ rc = rtc_valid_tm(&tm);
+ if (rc) {
+ pr_err("Invalid RTC time (%s): %d\n",
+ CONFIG_RTC_HCTOSYS_DEVICE, rc);
+ goto out;
+ }
+ rtc_tm_to_time(&tm, &now_tm_sec);
+
+ if (chip->tm_sec == 0) {
+ get_battery_current(chip, iavg_ua);
+ goto out;
+ }
+
+ delta_time_s = (now_tm_sec - chip->tm_sec);
+
+ /* use the previous iavg if called within 15 seconds */
+ if (delta_time_s < 15) {
+ *iavg_ua = chip->prev_iavg_ua;
+ goto out;
+ }
+
+ delta_cc_uah = cc_uah - chip->last_cc_uah;
+
+ *iavg_ua = div_s64((s64)delta_cc_uah * 3600, delta_time_s);
+
+ pr_debug("tm_sec = %ld, now_tm_sec = %ld delta_s = %d delta_cc = %d iavg_ua = %d\n",
+ chip->tm_sec, now_tm_sec,
+ delta_time_s, delta_cc_uah, (int)*iavg_ua);
+
+out:
+ /* remember the iavg */
+ chip->prev_iavg_ua = *iavg_ua;
+
+ /* remember cc_uah */
+ chip->last_cc_uah = cc_uah;
+
+ /* remember this time */
+ chip->tm_sec = now_tm_sec;
+}
+
+static int calculate_termination_uuc(struct qpnp_bms_chip *chip,
+ struct soc_params *params,
+ int batt_temp, int uuc_iavg_ma,
+ int *ret_pc_unusable)
+{
+ int unusable_uv, pc_unusable, uuc_uah;
+ int i = 0;
+ int ocv_mv;
+ int batt_temp_degc = batt_temp / 10;
+ int rbatt_mohm;
+ int delta_uv;
+ int prev_delta_uv = 0;
+ int prev_rbatt_mohm = 0;
+ int uuc_rbatt_mohm;
+
+ for (i = 0; i <= 100; i++) {
+ ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut,
+ batt_temp_degc, i);
+ rbatt_mohm = get_rbatt(chip, i, batt_temp);
+ unusable_uv = (rbatt_mohm * uuc_iavg_ma)
+ + (chip->v_cutoff_uv);
+ delta_uv = ocv_mv * 1000 - unusable_uv;
+
+ pr_debug("soc = %d ocv = %d rbat = %d u_uv = %d delta_v = %d\n",
+ i, ocv_mv, rbatt_mohm, unusable_uv, delta_uv);
+
+ if (delta_uv > 0)
+ break;
+
+ prev_delta_uv = delta_uv;
+ prev_rbatt_mohm = rbatt_mohm;
+ }
+
+ uuc_rbatt_mohm = linear_interpolate(rbatt_mohm, delta_uv,
+ prev_rbatt_mohm, prev_delta_uv,
+ 0);
+
+ unusable_uv = (uuc_rbatt_mohm * uuc_iavg_ma) + (chip->v_cutoff_uv);
+
+ pc_unusable = calculate_pc(chip, unusable_uv, batt_temp);
+ uuc_uah = (params->fcc_uah * pc_unusable) / 100;
+ pr_debug("For uuc_iavg_ma = %d, unusable_rbatt = %d unusable_uv = %d unusable_pc = %d uuc = %d\n",
+ uuc_iavg_ma,
+ uuc_rbatt_mohm, unusable_uv,
+ pc_unusable, uuc_uah);
+ *ret_pc_unusable = pc_unusable;
+ return uuc_uah;
+}
+
+static int adjust_uuc(struct qpnp_bms_chip *chip,
+ struct soc_params *params,
+ int new_pc_unusable,
+ int new_uuc_uah,
+ int batt_temp)
+{
+ int new_unusable_mv, new_iavg_ma;
+ int batt_temp_degc = batt_temp / 10;
+
+ if (chip->prev_pc_unusable == -EINVAL
+ || abs(chip->prev_pc_unusable - new_pc_unusable) <= 1) {
+ chip->prev_pc_unusable = new_pc_unusable;
+ return new_uuc_uah;
+ }
+
+ /* the uuc is trying to change more than 1% restrict it */
+ if (new_pc_unusable > chip->prev_pc_unusable)
+ chip->prev_pc_unusable++;
+ else
+ chip->prev_pc_unusable--;
+
+ new_uuc_uah = (params->fcc_uah * chip->prev_pc_unusable) / 100;
+
+ /* also find update the iavg_ma accordingly */
+ new_unusable_mv = interpolate_ocv(chip->pc_temp_ocv_lut,
+ batt_temp_degc, chip->prev_pc_unusable);
+ if (new_unusable_mv < chip->v_cutoff_uv/1000)
+ new_unusable_mv = chip->v_cutoff_uv/1000;
+
+ new_iavg_ma = (new_unusable_mv * 1000 - chip->v_cutoff_uv)
+ / params->rbatt;
+ if (new_iavg_ma == 0)
+ new_iavg_ma = 1;
+ chip->prev_uuc_iavg_ma = new_iavg_ma;
+ pr_debug("Restricting UUC to %d (%d%%) unusable_mv = %d iavg_ma = %d\n",
+ new_uuc_uah, chip->prev_pc_unusable,
+ new_unusable_mv, new_iavg_ma);
+
+ return new_uuc_uah;
+}
+
+#define CHARGING_IAVG_MA 250
+#define MIN_SECONDS_FOR_VALID_SAMPLE 20
+static int calculate_unusable_charge_uah(struct qpnp_bms_chip *chip,
+ struct soc_params *params,
+ int batt_temp)
+{
+ int uuc_uah_iavg;
+ int i;
+ int uuc_iavg_ma = params->iavg_ua / 1000;
+ int pc_unusable;
+
+ /*
+ * if called first time, fill all the samples with
+ * the shutdown_iavg_ma
+ */
+ if (chip->first_time_calc_uuc && chip->shutdown_iavg_ma != 0) {
+ pr_debug("Using shutdown_iavg_ma = %d in all samples\n",
+ chip->shutdown_iavg_ma);
+ for (i = 0; i < IAVG_SAMPLES; i++)
+ chip->iavg_samples_ma[i] = chip->shutdown_iavg_ma;
+
+ chip->iavg_index = 0;
+ chip->iavg_num_samples = IAVG_SAMPLES;
+ }
+
+ /*
+ * if charging use a nominal avg current to keep
+ * a reasonable UUC while charging
+ */
+ if (uuc_iavg_ma < 0)
+ uuc_iavg_ma = CHARGING_IAVG_MA;
+ chip->iavg_samples_ma[chip->iavg_index] = uuc_iavg_ma;
+ chip->iavg_index = (chip->iavg_index + 1) % IAVG_SAMPLES;
+ chip->iavg_num_samples++;
+ if (chip->iavg_num_samples >= IAVG_SAMPLES)
+ chip->iavg_num_samples = IAVG_SAMPLES;
+
+ /* now that this sample is added calcualte the average */
+ uuc_iavg_ma = 0;
+ if (chip->iavg_num_samples != 0) {
+ for (i = 0; i < chip->iavg_num_samples; i++) {
+ pr_debug("iavg_samples_ma[%d] = %d\n", i,
+ chip->iavg_samples_ma[i]);
+ uuc_iavg_ma += chip->iavg_samples_ma[i];
+ }
+
+ uuc_iavg_ma = DIV_ROUND_CLOSEST(uuc_iavg_ma,
+ chip->iavg_num_samples);
+ }
+
+ uuc_uah_iavg = calculate_termination_uuc(chip, params, uuc_iavg_ma,
+ batt_temp, &pc_unusable);
+ pr_debug("uuc_iavg_ma = %d uuc with iavg = %d\n",
+ uuc_iavg_ma, uuc_uah_iavg);
+
+ chip->prev_uuc_iavg_ma = uuc_iavg_ma;
+ /* restrict the uuc such that it can increase only by one percent */
+ uuc_uah_iavg = adjust_uuc(chip, params, pc_unusable,
+ uuc_uah_iavg, batt_temp);
+
+ chip->first_time_calc_uuc = 0;
+ return uuc_uah_iavg;
+}
+
+static void find_ocv_for_soc(struct qpnp_bms_chip *chip,
+ struct soc_params *params,
+ int batt_temp,
+ int shutdown_soc,
+ int *ret_ocv_uv)
+{
+ s64 ocv_charge_uah;
+ int pc, new_pc;
+ int batt_temp_degc = batt_temp / 10;
+ int ocv_uv;
+
+ ocv_charge_uah = (s64)shutdown_soc
+ * (params->fcc_uah - params->uuc_uah);
+ ocv_charge_uah = div_s64(ocv_charge_uah, 100)
+ + params->cc_uah + params->uuc_uah;
+ pc = DIV_ROUND_CLOSEST((int)ocv_charge_uah * 100, params->fcc_uah);
+ pc = clamp(pc, 0, 100);
+
+ ocv_uv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc);
+
+ pr_debug("s_soc = %d, fcc = %d uuc = %d rc = %d, pc = %d, ocv mv = %d\n",
+ shutdown_soc, params->fcc_uah,
+ params->uuc_uah, (int)ocv_charge_uah,
+ pc, ocv_uv);
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv_uv);
+ pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv_uv);
+
+ while (abs(new_pc - pc) > 1) {
+ int delta_mv = 5;
+
+ if (new_pc > pc)
+ delta_mv = -1 * delta_mv;
+
+ ocv_uv = ocv_uv + delta_mv;
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut,
+ batt_temp_degc, ocv_uv);
+ pr_debug("test revlookup pc = %d for ocv = %d\n",
+ new_pc, ocv_uv);
+ }
+
+ *ret_ocv_uv = ocv_uv * 1000;
+ params->ocv_charge_uah = (int)ocv_charge_uah;
+}
+
+static void calculate_soc_params(struct qpnp_bms_chip *chip,
+ struct raw_soc_params *raw,
+ struct soc_params *params,
+ int batt_temp)
+{
+ int soc_rbatt;
+
+ params->fcc_uah = calculate_fcc(chip, batt_temp);
+ pr_debug("FCC = %uuAh batt_temp = %d\n", params->fcc_uah, batt_temp);
+
+ /* calculate remainging charge */
+ params->ocv_charge_uah = calculate_ocv_charge(
+ chip, raw,
+ params->fcc_uah,
+ batt_temp);
+ pr_debug("ocv_charge_uah = %uuAh\n", params->ocv_charge_uah);
+
+ /* calculate cc micro_volt_hour */
+ params->cc_uah = calculate_cc(chip, raw->cc);
+ pr_debug("cc_uah = %duAh raw->cc = %llx cc = %lld after subtracting %llx\n",
+ params->cc_uah, raw->cc,
+ (int64_t)raw->cc - chip->cc_reading_at_100,
+ chip->cc_reading_at_100);
+
+ soc_rbatt = ((params->ocv_charge_uah - params->cc_uah) * 100)
+ / params->fcc_uah;
+ if (soc_rbatt < 0)
+ soc_rbatt = 0;
+ params->rbatt = get_rbatt(chip, soc_rbatt, batt_temp);
+
+ calculate_iavg(chip, params->cc_uah, ¶ms->iavg_ua);
+
+ params->uuc_uah = calculate_unusable_charge_uah(chip, params,
+ batt_temp);
+ pr_debug("UUC = %uuAh\n", params->uuc_uah);
+}
+
+static bool is_shutdown_soc_within_limits(struct qpnp_bms_chip *chip, int soc)
+{
+ if (chip->shutdown_soc_invalid) {
+ pr_debug("NOT forcing shutdown soc = %d\n", chip->shutdown_soc);
+ return 0;
+ }
+
+ if (abs(chip->shutdown_soc - soc) > chip->shutdown_soc_valid_limit) {
+ pr_debug("rejecting shutdown soc = %d, soc = %d limit = %d\n",
+ chip->shutdown_soc, soc,
+ chip->shutdown_soc_valid_limit);
+ chip->shutdown_soc_invalid = 1;
+ return 0;
+ }
+
+ return 1;
+}
+
+#define BMS_OVERRIDE_MODE_EN_BIT BIT(7)
+#define EN_VBAT_BIT BIT(0)
+#define OVERRIDE_MODE_DELAY_MS 20
+static int override_mode_batt_v_and_i(
+ struct qpnp_bms_chip *chip, int *ibat_ua, int *vbat_uv)
+{
+ int16_t vsense_raw, vbat_raw;
+ int vsense_uv, rc;
+ u8 delay;
+
+ mutex_lock(&chip->bms_output_lock);
+
+ delay = 0x00;
+ rc = qpnp_write_wrapper(chip, &delay,
+ chip->base + BMS1_S1_DELAY_CTL, 1);
+ if (rc)
+ pr_err("unable to write into BMS1_S1_DELAY, rc: %d\n", rc);
+
+ rc = qpnp_masked_write(chip, BMS1_MODE_CTL,
+ BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT,
+ BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT);
+ if (rc)
+ pr_err("unable to write into BMS1_MODE_CTL, rc: %d\n", rc);
+
+ msleep(OVERRIDE_MODE_DELAY_MS);
+
+ lock_output_data(chip);
+ qpnp_read_wrapper(chip, (u8 *)&vsense_raw,
+ chip->base + BMS1_VSENSE_AVG_DATA0, 2);
+ qpnp_read_wrapper(chip, (u8 *)&vbat_raw,
+ chip->base + BMS1_VBAT_AVG_DATA0, 2);
+ unlock_output_data(chip);
+
+ rc = qpnp_masked_write(chip, BMS1_MODE_CTL,
+ BMS_OVERRIDE_MODE_EN_BIT | EN_VBAT_BIT, 0);
+
+ delay = 0x0B;
+ rc = qpnp_write_wrapper(chip, &delay,
+ chip->base + BMS1_S1_DELAY_CTL, 1);
+ if (rc)
+ pr_err("unable to write into BMS1_S1_DELAY, rc: %d\n", rc);
+
+ mutex_unlock(&chip->bms_output_lock);
+
+ *vbat_uv = convert_vbatt_raw_to_uv(chip, vbat_raw);
+ vsense_uv = convert_vsense_to_uv(chip, vsense_raw);
+ *ibat_ua = vsense_uv * 1000 / (int)chip->r_sense_mohm;
+
+ pr_debug("vsense_raw = 0x%x vbat_raw = 0x%x ibat_ua = %d vbat_uv = %d\n",
+ (uint16_t)vsense_raw, (uint16_t)vbat_raw,
+ *ibat_ua, *vbat_uv);
+ return 0;
+}
+
+static int get_simultaneous_batt_v_and_i(
+ struct qpnp_bms_chip *chip,
+ int *ibat_ua, int *vbat_uv)
+{
+ int rc;
+ union power_supply_propval ret = {0,};
+
+ if (chip->batt_psy == NULL)
+ chip->batt_psy = power_supply_get_by_name("battery");
+ if (chip->batt_psy) {
+ /* if battery has been registered, use the status property */
+ chip->batt_psy->get_property(chip->batt_psy,
+ POWER_SUPPLY_PROP_STATUS, &ret);
+ } else {
+ /* default to using separate vbat/ibat if unregistered */
+ ret.intval = POWER_SUPPLY_STATUS_FULL;
+ }
+
+ if (ret.intval == POWER_SUPPLY_STATUS_FULL) {
+ pr_debug("batfet is open using separate vbat and ibat meas\n");
+ rc = get_battery_voltage(vbat_uv);
+ if (rc < 0) {
+ pr_err("adc vbat failed err = %d\n", rc);
+ return rc;
+ }
+ rc = get_battery_current(chip, ibat_ua);
+ if (rc < 0) {
+ pr_err("bms ibat failed err = %d\n", rc);
+ return rc;
+ }
+ } else {
+ return override_mode_batt_v_and_i(chip, ibat_ua, vbat_uv);
+ }
+
+ return 0;
+}
+
+static int bound_soc(int soc)
+{
+ soc = max(0, soc);
+ soc = min(100, soc);
+ return soc;
+}
+
+static int charging_adjustments(struct qpnp_bms_chip *chip,
+ struct soc_params *params, int soc,
+ int vbat_uv, int ibat_ua, int batt_temp)
+{
+ int chg_soc;
+
+ if (chip->soc_at_cv == -EINVAL) {
+ /* In constant current charging return the calc soc */
+ if (vbat_uv <= chip->max_voltage_uv)
+ pr_debug("CC CHG SOC %d\n", soc);
+
+ /* Note the CC to CV point */
+ if (vbat_uv >= chip->max_voltage_uv) {
+ chip->soc_at_cv = soc;
+ chip->prev_chg_soc = soc;
+ chip->ibat_at_cv_ua = ibat_ua;
+ pr_debug("CC_TO_CV ibat_ua = %d CHG SOC %d\n",
+ ibat_ua, soc);
+ }
+ return soc;
+ }
+
+ /*
+ * battery is in CV phase - begin liner inerpolation of soc based on
+ * battery charge current
+ */
+
+ /*
+ * if voltage lessened (possibly because of a system load)
+ * keep reporting the prev chg soc
+ */
+ if (vbat_uv <= chip->max_voltage_uv) {
+ pr_debug("vbat %d < max = %d CC CHG SOC %d\n",
+ vbat_uv, chip->max_voltage_uv, chip->prev_chg_soc);
+ return chip->prev_chg_soc;
+ }
+
+ chg_soc = linear_interpolate(chip->soc_at_cv, chip->ibat_at_cv_ua,
+ 100, -100000,
+ ibat_ua);
+
+ /* always report a higher soc */
+ if (chg_soc > chip->prev_chg_soc) {
+ int new_ocv_uv;
+
+ chip->prev_chg_soc = chg_soc;
+
+ find_ocv_for_soc(chip, params, batt_temp, chg_soc, &new_ocv_uv);
+ chip->last_ocv_uv = new_ocv_uv;
+ pr_debug("CC CHG ADJ OCV = %d CHG SOC %d\n",
+ new_ocv_uv,
+ chip->prev_chg_soc);
+ }
+
+ pr_debug("Reporting CHG SOC %d\n", chip->prev_chg_soc);
+ return chip->prev_chg_soc;
+}
+
+static int adjust_soc(struct qpnp_bms_chip *chip, struct soc_params *params,
+ int soc, int batt_temp)
+{
+ int ibat_ua = 0, vbat_uv = 0;
+ int ocv_est_uv = 0, soc_est = 0, pc_est = 0, pc = 0;
+ int delta_ocv_uv = 0;
+ int n = 0;
+ int rc_new_uah = 0;
+ int pc_new = 0;
+ int soc_new = 0;
+ int slope = 0;
+ int rc = 0;
+ int delta_ocv_uv_limit = 0;
+
+ rc = get_simultaneous_batt_v_and_i(chip, &ibat_ua, &vbat_uv);
+ if (rc < 0) {
+ pr_err("simultaneous vbat ibat failed err = %d\n", rc);
+ goto out;
+ }
+
+ delta_ocv_uv_limit = DIV_ROUND_CLOSEST(ibat_ua, 1000);
+
+ ocv_est_uv = vbat_uv + (ibat_ua * params->rbatt)/1000;
+ pc_est = calculate_pc(chip, ocv_est_uv, batt_temp);
+ soc_est = div_s64((s64)params->fcc_uah * pc_est - params->uuc_uah*100,
+ (s64)params->fcc_uah - params->uuc_uah);
+ soc_est = bound_soc(soc_est);
+
+ if (ibat_ua < 0) {
+ soc = charging_adjustments(chip, params, soc, vbat_uv, ibat_ua,
+ batt_temp);
+ goto out;
+ }
+
+ /*
+ * do not adjust
+ * if soc is same as what bms calculated
+ * if soc_est is between 45 and 25, this is the flat portion of the
+ * curve where soc_est is not so accurate. We generally don't want to
+ * adjust when soc_est is inaccurate except for the cases when soc is
+ * way far off (higher than 50 or lesser than 20).
+ * Also don't adjust soc if it is above 90 becuase it might be pulled
+ * low and cause a bad user experience
+ */
+ if (soc_est == soc
+ || (is_between(45, chip->adjust_soc_low_threshold, soc_est)
+ && is_between(50, chip->adjust_soc_low_threshold - 5, soc))
+ || soc >= 90)
+ goto out;
+
+ if (chip->last_soc_est == -EINVAL)
+ chip->last_soc_est = soc;
+
+ n = min(200, max(1 , soc + soc_est + chip->last_soc_est));
+ chip->last_soc_est = soc_est;
+
+ pc = calculate_pc(chip, chip->last_ocv_uv, batt_temp);
+ if (pc > 0) {
+ pc_new = calculate_pc(chip,
+ chip->last_ocv_uv - (++slope * 1000),
+ batt_temp);
+ while (pc_new == pc) {
+ /* start taking 10mV steps */
+ slope = slope + 10;
+ pc_new = calculate_pc(chip,
+ chip->last_ocv_uv - (slope * 1000),
+ batt_temp);
+ }
+ } else {
+ /*
+ * pc is already at the lowest point,
+ * assume 1 millivolt translates to 1% pc
+ */
+ pc = 1;
+ pc_new = 0;
+ slope = 1;
+ }
+
+ delta_ocv_uv = div_s64((soc - soc_est) * (s64)slope * 1000,
+ n * (pc - pc_new));
+
+ if (abs(delta_ocv_uv) > delta_ocv_uv_limit) {
+ pr_debug("limiting delta ocv %d limit = %d\n", delta_ocv_uv,
+ delta_ocv_uv_limit);
+
+ if (delta_ocv_uv > 0)
+ delta_ocv_uv = delta_ocv_uv_limit;
+ else
+ delta_ocv_uv = -1 * delta_ocv_uv_limit;
+ pr_debug("new delta ocv = %d\n", delta_ocv_uv);
+ }
+
+ chip->last_ocv_uv -= delta_ocv_uv;
+
+ if (chip->last_ocv_uv >= chip->max_voltage_uv)
+ chip->last_ocv_uv = chip->max_voltage_uv;
+
+ /* calculate the soc based on this new ocv */
+ pc_new = calculate_pc(chip, chip->last_ocv_uv, batt_temp);
+ rc_new_uah = (params->fcc_uah * pc_new) / 100;
+ soc_new = (rc_new_uah - params->cc_uah - params->uuc_uah)*100
+ / (params->fcc_uah - params->uuc_uah);
+ soc_new = bound_soc(soc_new);
+
+ /*
+ * if soc_new is ZERO force it higher so that phone doesnt report soc=0
+ * soc = 0 should happen only when soc_est == 0
+ */
+ if (soc_new == 0 && soc_est != 0)
+ soc_new = 1;
+
+ soc = soc_new;
+
+out:
+ pr_debug("ibat_ua = %d, vbat_uv = %d, ocv_est_uv = %d, pc_est = %d, soc_est = %d, n = %d, delta_ocv_uv = %d, last_ocv_uv = %d, pc_new = %d, soc_new = %d, rbatt = %d, slope = %d\n",
+ ibat_ua, vbat_uv, ocv_est_uv, pc_est,
+ soc_est, n, delta_ocv_uv, chip->last_ocv_uv,
+ pc_new, soc_new, params->rbatt, slope);
+
+ return soc;
+}
+
+static int calculate_state_of_charge(struct qpnp_bms_chip *chip,
+ struct raw_soc_params *raw,
+ int batt_temp)
+{
+ int soc, new_ocv_uv;
+ int shutdown_soc, new_calculated_soc, remaining_usable_charge_uah;
+ struct soc_params params;
+
+ calculate_soc_params(chip, raw, ¶ms, batt_temp);
+ /* calculate remaining usable charge */
+ remaining_usable_charge_uah = params.ocv_charge_uah
+ - params.cc_uah
+ - params.uuc_uah;
+
+ pr_debug("RUC = %duAh\n", remaining_usable_charge_uah);
+ if (params.fcc_uah - params.uuc_uah <= 0) {
+ pr_warn("FCC = %duAh, UUC = %duAh forcing soc = 0\n",
+ params.fcc_uah,
+ params.uuc_uah);
+ soc = 0;
+ } else {
+ soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100),
+ (params.fcc_uah
+ - params.uuc_uah));
+ }
+
+ if (chip->first_time_calc_soc && soc < 0) {
+ /*
+ * first time calcualtion and the pon ocv is too low resulting
+ * in a bad soc. Adjust ocv to get 0 soc
+ */
+ pr_debug("soc is %d, adjusting pon ocv to make it 0\n", soc);
+ find_ocv_for_soc(chip, ¶ms, batt_temp, 0, &new_ocv_uv);
+ chip->last_ocv_uv = new_ocv_uv;
+
+ remaining_usable_charge_uah = params.ocv_charge_uah
+ - params.cc_uah
+ - params.uuc_uah;
+
+ soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100),
+ (params.fcc_uah
+ - params.uuc_uah));
+ pr_debug("DONE for O soc is %d, pon ocv adjusted to %duV\n",
+ soc, chip->last_ocv_uv);
+ }
+
+ if (soc > 100)
+ soc = 100;
+
+ if (soc < 0) {
+ pr_err("bad rem_usb_chg = %d rem_chg %d, cc_uah %d, unusb_chg %d\n",
+ remaining_usable_charge_uah,
+ params.ocv_charge_uah,
+ params.cc_uah, params.uuc_uah);
+
+ pr_err("for bad rem_usb_chg last_ocv_uv = %d batt_temp = %d fcc = %d soc =%d\n",
+ chip->last_ocv_uv, batt_temp,
+ params.fcc_uah, soc);
+ soc = 0;
+ }
+
+ mutex_lock(&chip->soc_invalidation_mutex);
+ shutdown_soc = chip->shutdown_soc;
+
+ if (chip->first_time_calc_soc && soc != shutdown_soc
+ && is_shutdown_soc_within_limits(chip, soc)) {
+ /*
+ * soc for the first time - use shutdown soc
+ * to adjust pon ocv since it is a small percent away from
+ * the real soc
+ */
+ pr_debug("soc = %d before forcing shutdown_soc = %d\n",
+ soc, shutdown_soc);
+ find_ocv_for_soc(chip, ¶ms, batt_temp,
+ shutdown_soc, &new_ocv_uv);
+ chip->pon_ocv_uv = chip->last_ocv_uv;
+ chip->last_ocv_uv = new_ocv_uv;
+
+ remaining_usable_charge_uah = params.ocv_charge_uah
+ - params.cc_uah
+ - params.uuc_uah;
+
+ soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100),
+ (params.fcc_uah
+ - params.uuc_uah));
+
+ pr_debug("DONE for shutdown_soc = %d soc is %d, adjusted ocv to %duV\n",
+ shutdown_soc, soc, chip->last_ocv_uv);
+ }
+ mutex_unlock(&chip->soc_invalidation_mutex);
+
+ pr_debug("SOC before adjustment = %d\n", soc);
+ new_calculated_soc = adjust_soc(chip, ¶ms, soc, batt_temp);
+
+ if (new_calculated_soc != chip->calculated_soc
+ && chip->bms_psy.name != NULL) {
+ power_supply_changed(&chip->bms_psy);
+ pr_debug("power supply changed\n");
+ }
+
+ chip->calculated_soc = new_calculated_soc;
+ pr_debug("Set calculated SOC = %d\n", chip->calculated_soc);
+ chip->first_time_calc_soc = 0;
+ return chip->calculated_soc;
+}
+
+static void read_vbat(struct qpnp_bms_chip *chip)
+{
+ int rc;
+ struct qpnp_vadc_result result;
+
+ rc = qpnp_vadc_read(VBAT_SNS, &result);
+ if (rc) {
+ pr_err("error reading vadc VBAT_SNS = %d, rc = %d\n",
+ VBAT_SNS, rc);
+ return;
+ }
+ chip->last_vbat_read_uv = (int)result.physical;
+}
+
+static void calculate_soc_work(struct work_struct *work)
+{
+ struct qpnp_bms_chip *chip = container_of(work,
+ struct qpnp_bms_chip,
+ calculate_soc_delayed_work.work);
+ int batt_temp, rc, soc;
+ struct qpnp_vadc_result result;
+ struct raw_soc_params raw;
+
+ read_vbat(chip);
+
+ rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
+ if (rc) {
+ pr_err("error reading vadc LR_MUX1_BATT_THERM = %d, rc = %d\n",
+ LR_MUX1_BATT_THERM, rc);
+ return;
+ }
+ pr_debug("batt_temp phy = %lld meas = 0x%llx\n", result.physical,
+ result.measurement);
+ batt_temp = (int)result.physical;
+
+ mutex_lock(&chip->last_ocv_uv_mutex);
+ read_soc_params_raw(chip, &raw);
+ soc = calculate_state_of_charge(chip, &raw, batt_temp);
+ mutex_unlock(&chip->last_ocv_uv_mutex);
+
+ if (soc < chip->low_soc_calc_threshold)
+ schedule_delayed_work(&chip->calculate_soc_delayed_work,
+ round_jiffies_relative(msecs_to_jiffies
+ (chip->low_soc_calculate_soc_ms)));
+ else
+ schedule_delayed_work(&chip->calculate_soc_delayed_work,
+ round_jiffies_relative(msecs_to_jiffies
+ (chip->calculate_soc_ms)));
+}
+
+static void backup_soc_and_iavg(struct qpnp_bms_chip *chip, int batt_temp,
+ int soc)
+{
+ u8 temp;
+ int rc;
+ int iavg_ma = chip->prev_uuc_iavg_ma;
+
+ if (iavg_ma > IAVG_START)
+ temp = (iavg_ma - IAVG_START) / IAVG_STEP_SIZE_MA;
+ else
+ temp = 0;
+
+ rc = qpnp_write_wrapper(chip, &temp,
+ chip->base + IAVG_STORAGE_REG, 1);
+
+ if (soc == 0)
+ temp = SOC_ZERO;
+ else
+ temp = soc;
+
+ /* don't store soc if temperature is below 5degC */
+ if (batt_temp > IGNORE_SOC_TEMP_DECIDEG)
+ rc = qpnp_write_wrapper(chip, &temp,
+ chip->base + SOC_STORAGE_REG, 1);
+}
+
+#define SOC_CATCHUP_SEC_MAX 600
+#define SOC_CATCHUP_SEC_PER_PERCENT 60
+#define MAX_CATCHUP_SOC (SOC_CATCHUP_SEC_MAX/SOC_CATCHUP_SEC_PER_PERCENT)
+static int scale_soc_while_chg(struct qpnp_bms_chip *chip,
+ int delta_time_us, int new_soc, int prev_soc)
+{
+ int chg_time_sec;
+ int catch_up_sec;
+ int scaled_soc;
+ int numerator;
+
+ /*
+ * The device must be charging for reporting a higher soc, if
+ * not ignore this soc and continue reporting the prev_soc.
+ * Also don't report a high value immediately slowly scale the
+ * value from prev_soc to the new soc based on a charge time
+ * weighted average
+ */
+
+ /* if not charging, return last soc */
+ if (chip->start_percent == -EINVAL)
+ return prev_soc;
+
+ chg_time_sec = DIV_ROUND_UP(chip->charge_time_us, USEC_PER_SEC);
+ catch_up_sec = DIV_ROUND_UP(chip->catch_up_time_us, USEC_PER_SEC);
+ pr_debug("cts= %d catch_up_sec = %d\n", chg_time_sec, catch_up_sec);
+
+ /*
+ * if charging for more than catch_up time, simply return
+ * new soc
+ */
+ if (chg_time_sec > catch_up_sec)
+ return new_soc;
+
+ numerator = (catch_up_sec - chg_time_sec) * prev_soc
+ + chg_time_sec * new_soc;
+ scaled_soc = numerator / catch_up_sec;
+
+ pr_debug("cts = %d new_soc = %d prev_soc = %d scaled_soc = %d\n",
+ chg_time_sec, new_soc, prev_soc, scaled_soc);
+
+ return scaled_soc;
+}
+
+/*
+ * bms_fake_battery is set in setups where a battery emulator is used instead
+ * of a real battery. This makes the bms driver report a different/fake value
+ * regardless of the calculated state of charge.
+ */
+static int bms_fake_battery = -EINVAL;
+module_param(bms_fake_battery, int, 0644);
+
+static int report_state_of_charge(struct qpnp_bms_chip *chip)
+{
+ int soc;
+ int delta_time_us;
+ struct timespec now;
+ struct qpnp_vadc_result result;
+ int batt_temp;
+ int rc;
+
+ if (bms_fake_battery != -EINVAL) {
+ pr_debug("Returning Fake SOC = %d%%\n", bms_fake_battery);
+ return bms_fake_battery;
+ }
+
+ soc = chip->calculated_soc;
+
+ rc = qpnp_vadc_read(LR_MUX1_BATT_THERM, &result);
+
+ if (rc) {
+ pr_err("error reading adc channel = %d, rc = %d\n",
+ LR_MUX1_BATT_THERM, rc);
+ return rc;
+ }
+ pr_debug("batt_temp phy = %lld meas = 0x%llx\n", result.physical,
+ result.measurement);
+ batt_temp = (int)result.physical;
+
+ do_posix_clock_monotonic_gettime(&now);
+ if (chip->t_soc_queried.tv_sec != 0) {
+ delta_time_us
+ = (now.tv_sec - chip->t_soc_queried.tv_sec) * USEC_PER_SEC
+ + (now.tv_nsec - chip->t_soc_queried.tv_nsec) / 1000;
+ } else {
+ /* calculation for the first time */
+ delta_time_us = 0;
+ }
+
+ /*
+ * account for charge time - limit it to SOC_CATCHUP_SEC to
+ * avoid overflows when charging continues for extended periods
+ */
+ if (chip->start_percent != -EINVAL) {
+ if (chip->charge_time_us == 0) {
+ /*
+ * calculating soc for the first time
+ * after start of chg. Initialize catchup time
+ */
+ if (abs(soc - chip->last_soc) < MAX_CATCHUP_SOC)
+ chip->catch_up_time_us =
+ (soc - chip->last_soc)
+ * SOC_CATCHUP_SEC_PER_PERCENT
+ * USEC_PER_SEC;
+ else
+ chip->catch_up_time_us =
+ SOC_CATCHUP_SEC_MAX * USEC_PER_SEC;
+
+ if (chip->catch_up_time_us < 0)
+ chip->catch_up_time_us = 0;
+ }
+
+ /* add charge time */
+ if (chip->charge_time_us < SOC_CATCHUP_SEC_MAX * USEC_PER_SEC)
+ chip->charge_time_us += delta_time_us;
+
+ /* end catchup if calculated soc and last soc are same */
+ if (chip->last_soc == soc)
+ chip->catch_up_time_us = 0;
+ }
+
+ /* last_soc < soc ... scale and catch up */
+ if (chip->last_soc != -EINVAL && chip->last_soc < soc && soc != 100)
+ soc = scale_soc_while_chg(chip, delta_time_us,
+ soc, chip->last_soc);
+
+ pr_debug("last_soc = %d, calculated_soc = %d, soc = %d\n",
+ chip->last_soc, chip->calculated_soc, soc);
+ chip->last_soc = soc;
+ backup_soc_and_iavg(chip, batt_temp, chip->last_soc);
+ pr_debug("Reported SOC = %d\n", chip->last_soc);
+ chip->t_soc_queried = now;
+
+ return chip->last_soc;
+}
+
+static int calculate_soc_from_voltage(struct qpnp_bms_chip *chip)
+{
+ int voltage_range_uv, voltage_remaining_uv, voltage_based_soc;
+
+ if (chip->last_vbat_read_uv < 0)
+ read_vbat(chip);
+
+ voltage_range_uv = chip->max_voltage_uv - chip->v_cutoff_uv;
+ voltage_remaining_uv = chip->last_vbat_read_uv - chip->v_cutoff_uv;
+ voltage_based_soc = voltage_remaining_uv * 100 / voltage_range_uv;
+
+ return clamp(voltage_based_soc, 0, 100);
+}
+
/* Returns capacity as a SoC percentage between 0 and 100 */
static int get_prop_bms_capacity(struct qpnp_bms_chip *chip)
{
- /* return 50 until a real algorithm is implemented */
- return 50;
+ if (use_voltage_soc)
+ return calculate_soc_from_voltage(chip);
+ else
+ return report_state_of_charge(chip);
}
/* Returns instantaneous current in uA */
static int get_prop_bms_current_now(struct qpnp_bms_chip *chip)
{
/* temporarily return 0 until a real algorithm is put in */
- return 0;
+ int rc, result_ua;
+
+ rc = get_battery_current(chip, &result_ua);
+ if (rc) {
+ pr_err("failed to get current: %d\n", rc);
+ return rc;
+ }
+ return result_ua;
}
/* Returns full charge design in uAh */
static int get_prop_bms_charge_full_design(struct qpnp_bms_chip *chip)
{
- /* temporarily return 0 until a real algorithm is put in */
- return 0;
+ return chip->fcc;
+}
+
+static bool get_prop_bms_online(struct qpnp_bms_chip *chip)
+{
+ return chip->online;
+}
+
+static int get_prop_bms_status(struct qpnp_bms_chip *chip)
+{
+ return chip->charger_status;
}
static void set_prop_bms_online(struct qpnp_bms_chip *chip, bool online)
@@ -184,6 +1682,12 @@
case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
val->intval = get_prop_bms_charge_full_design(chip);
break;
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = get_prop_bms_status(chip);
+ break;
+ case POWER_SUPPLY_PROP_ONLINE:
+ val->intval = get_prop_bms_online(chip);
+ break;
default:
return -EINVAL;
}
@@ -210,24 +1714,206 @@
return 0;
}
-#define SPMI_PROPERTY_READ(chip_prop, qpnp_spmi_property, retval, errlabel)\
+static void read_shutdown_soc_and_iavg(struct qpnp_bms_chip *chip)
+{
+ int rc;
+ u8 temp;
+
+ if (chip->ignore_shutdown_soc) {
+ chip->shutdown_soc_invalid = 1;
+ chip->shutdown_soc = 0;
+ chip->shutdown_iavg_ma = 0;
+ } else {
+ rc = qpnp_read_wrapper(chip, &temp,
+ chip->base + IAVG_STORAGE_REG, 1);
+ if (rc) {
+ pr_err("failed to read addr = %d %d assuming %d\n",
+ chip->base + IAVG_STORAGE_REG, rc,
+ IAVG_START);
+ chip->shutdown_iavg_ma = IAVG_START;
+ } else {
+ if (temp == 0) {
+ chip->shutdown_iavg_ma = IAVG_START;
+ } else {
+ chip->shutdown_iavg_ma = IAVG_START
+ + IAVG_STEP_SIZE_MA * (temp + 1);
+ }
+ }
+
+ rc = qpnp_read_wrapper(chip, &temp,
+ chip->base + SOC_STORAGE_REG, 1);
+ if (rc) {
+ pr_err("failed to read addr = %d %d\n",
+ chip->base + SOC_STORAGE_REG, rc);
+ } else {
+ chip->shutdown_soc = temp;
+
+ if (chip->shutdown_soc == 0) {
+ pr_debug("No shutdown soc available\n");
+ chip->shutdown_soc_invalid = 1;
+ chip->shutdown_iavg_ma = 0;
+ } else if (chip->shutdown_soc == SOC_ZERO) {
+ chip->shutdown_soc = 0;
+ }
+ }
+ }
+
+ pr_debug("shutdown_soc = %d shutdown_iavg = %d shutdown_soc_invalid = %d\n",
+ chip->shutdown_soc,
+ chip->shutdown_iavg_ma,
+ chip->shutdown_soc_invalid);
+}
+
+#define PALLADIUM_ID_MIN 0x7F40
+#define PALLADIUM_ID_MAX 0x7F5A
+#define DESAY_5200_ID_MIN 0x7F7F
+#define DESAY_5200_ID_MAX 0x802F
+static int32_t read_battery_id(struct qpnp_bms_chip *chip)
+{
+ int rc;
+ struct qpnp_vadc_result result;
+
+ rc = qpnp_vadc_read(LR_MUX2_BAT_ID, &result);
+ if (rc) {
+ pr_err("error reading batt id channel = %d, rc = %d\n",
+ LR_MUX2_BAT_ID, rc);
+ return rc;
+ }
+ pr_debug("batt_id phy = %lld meas = 0x%llx\n", result.physical,
+ result.measurement);
+ pr_debug("raw_code = 0x%x\n", result.adc_code);
+ return result.adc_code;
+}
+
+static int set_battery_data(struct qpnp_bms_chip *chip)
+{
+ int64_t battery_id;
+
+ if (chip->batt_type == BATT_DESAY)
+ goto desay;
+ else if (chip->batt_type == BATT_PALLADIUM)
+ goto palladium;
+
+ battery_id = read_battery_id(chip);
+ if (battery_id < 0) {
+ pr_err("cannot read battery id err = %lld\n", battery_id);
+ return battery_id;
+ }
+
+ if (is_between(PALLADIUM_ID_MIN, PALLADIUM_ID_MAX, battery_id)) {
+ goto palladium;
+ } else if (is_between(DESAY_5200_ID_MIN, DESAY_5200_ID_MAX,
+ battery_id)) {
+ goto desay;
+ } else {
+ pr_warn("invalid battid, palladium 1500 assumed batt_id %llx\n",
+ battery_id);
+ goto palladium;
+ }
+
+palladium:
+ chip->fcc = palladium_1500_data.fcc;
+ chip->fcc_temp_lut = palladium_1500_data.fcc_temp_lut;
+ chip->fcc_sf_lut = palladium_1500_data.fcc_sf_lut;
+ chip->pc_temp_ocv_lut = palladium_1500_data.pc_temp_ocv_lut;
+ chip->pc_sf_lut = palladium_1500_data.pc_sf_lut;
+ chip->rbatt_sf_lut = palladium_1500_data.rbatt_sf_lut;
+ chip->default_rbatt_mohm
+ = palladium_1500_data.default_rbatt_mohm;
+ goto check_lut;
+desay:
+ chip->fcc = desay_5200_data.fcc;
+ chip->fcc_temp_lut = desay_5200_data.fcc_temp_lut;
+ chip->pc_temp_ocv_lut = desay_5200_data.pc_temp_ocv_lut;
+ chip->pc_sf_lut = desay_5200_data.pc_sf_lut;
+ chip->rbatt_sf_lut = desay_5200_data.rbatt_sf_lut;
+ chip->default_rbatt_mohm = desay_5200_data.default_rbatt_mohm;
+ goto check_lut;
+check_lut:
+ if (chip->pc_temp_ocv_lut == NULL) {
+ pr_err("temp ocv lut table is NULL\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+#define SPMI_PROP_READ(chip_prop, qpnp_spmi_property, retval) \
do { \
- retval = of_property_read_u32(spmi->dev.of_node, \
+ retval = of_property_read_u32(chip->spmi->dev.of_node, \
"qcom,bms-" qpnp_spmi_property, \
&chip->chip_prop); \
if (retval) { \
pr_err("Error reading " #qpnp_spmi_property \
" property %d\n", rc); \
- goto errlabel; \
+ return -EINVAL; \
} \
} while (0)
+static inline int bms_read_properties(struct qpnp_bms_chip *chip)
+{
+ int rc;
+
+ SPMI_PROP_READ(r_sense_mohm, "r-sense-mohm", rc);
+ SPMI_PROP_READ(v_cutoff_uv, "v-cutoff-uv", rc);
+ SPMI_PROP_READ(max_voltage_uv, "max-voltage-uv", rc);
+ SPMI_PROP_READ(r_conn_mohm, "r-conn-mohm", rc);
+ SPMI_PROP_READ(chg_term_ua, "chg-term-ua", rc);
+ SPMI_PROP_READ(shutdown_soc_valid_limit,
+ "shutdown-soc-valid-limit", rc);
+ SPMI_PROP_READ(adjust_soc_high_threshold,
+ "adjust-soc-high-threshold", rc);
+ SPMI_PROP_READ(adjust_soc_low_threshold,
+ "adjust-soc-low-threshold", rc);
+ SPMI_PROP_READ(batt_type, "batt-type", rc);
+ SPMI_PROP_READ(low_soc_calc_threshold,
+ "low-soc-calculate-soc-threshold", rc);
+ SPMI_PROP_READ(low_soc_calculate_soc_ms,
+ "low-soc-calculate-soc-ms", rc);
+ SPMI_PROP_READ(calculate_soc_ms, "calculate-soc-ms", rc);
+ chip->ignore_shutdown_soc = of_property_read_bool(
+ chip->spmi->dev.of_node,
+ "qcom,bms-ignore-shutdown-soc");
+ use_voltage_soc = of_property_read_bool(chip->spmi->dev.of_node,
+ "qcom,bms-use-voltage-soc");
+
+ if (chip->adjust_soc_low_threshold >= 45)
+ chip->adjust_soc_low_threshold = 45;
+
+ pr_debug("dts data: r_sense_mohm:%d, v_cutoff_uv:%d, max_v:%d\n",
+ chip->r_sense_mohm, chip->v_cutoff_uv,
+ chip->max_voltage_uv);
+ pr_debug("r_conn:%d, shutdown_soc: %d, adjust_soc_low:%d\n",
+ chip->r_conn_mohm, chip->shutdown_soc_valid_limit,
+ chip->adjust_soc_low_threshold);
+ pr_debug("adjust_soc_high:%d, chg_term_ua:%d, batt_type:%d\n",
+ chip->adjust_soc_high_threshold, chip->chg_term_ua,
+ chip->batt_type);
+ pr_debug("ignore_shutdown_soc:%d, use_voltage_soc:%d\n",
+ chip->ignore_shutdown_soc, use_voltage_soc);
+
+ return 0;
+}
+
+static inline void bms_initialize_constants(struct qpnp_bms_chip *chip)
+{
+ chip->start_percent = -EINVAL;
+ chip->end_percent = -EINVAL;
+ chip->prev_pc_unusable = -EINVAL;
+ chip->soc_at_cv = -EINVAL;
+ chip->calculated_soc = -EINVAL;
+ chip->last_soc = -EINVAL;
+ chip->last_vbat_read_uv = -EINVAL;
+ chip->last_soc_est = -EINVAL;
+ chip->first_time_calc_soc = 1;
+ chip->first_time_calc_uuc = 1;
+}
+
static int __devinit
qpnp_bms_probe(struct spmi_device *spmi)
{
struct qpnp_bms_chip *chip;
struct resource *bms_resource;
- int rc;
+ int rc, vbatt;
chip = kzalloc(sizeof *chip, GFP_KERNEL);
@@ -239,6 +1925,10 @@
chip->dev = &(spmi->dev);
chip->spmi = spmi;
+ mutex_init(&chip->bms_output_lock);
+ mutex_init(&chip->last_ocv_uv_mutex);
+ mutex_init(&chip->soc_invalidation_mutex);
+
bms_resource = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
if (!bms_resource) {
dev_err(&spmi->dev, "Unable to get BMS base address\n");
@@ -260,29 +1950,30 @@
goto error_read;
}
- SPMI_PROPERTY_READ(r_sense_mohm, "r-sense-mohm", rc, error_read);
- SPMI_PROPERTY_READ(v_cutoff, "v-cutoff-uv", rc, error_read);
- SPMI_PROPERTY_READ(max_voltage, "max-voltage-uv", rc, error_read);
- SPMI_PROPERTY_READ(r_conn_mohm, "r-conn-mohm", rc, error_read);
- SPMI_PROPERTY_READ(shutdown_soc_valid_limit,
- "shutdown-soc-valid-limit", rc, error_read);
- SPMI_PROPERTY_READ(adjust_soc_low_threshold,
- "adjust-soc-low-threshold", rc, error_read);
- SPMI_PROPERTY_READ(adjust_soc_high_threshold,
- "adjust-soc-high-threshold", rc, error_read);
- SPMI_PROPERTY_READ(chg_term, "chg-term-ua", rc, error_read);
+ rc = set_battery_data(chip);
+ if (rc) {
+ pr_err("Bad battery data %d\n", rc);
+ goto error_read;
+ }
- pr_debug("dts data: r_sense_mohm:%d, v_cutoff:%d, max_v:%d, r_conn:%d, shutdown_soc: %d, adjust_soc_low:%d, adjust_soc_high:%d, chg_term:%d\n",
- chip->r_sense_mohm, chip->v_cutoff,
- chip->max_voltage, chip->r_conn_mohm,
- chip->shutdown_soc_valid_limit,
- chip->adjust_soc_low_threshold,
- chip->adjust_soc_high_threshold,
- chip->chg_term);
+ rc = bms_read_properties(chip);
+ if (rc) {
+ pr_err("Unable to read all bms properties, rc = %d\n", rc);
+ goto error_read;
+ }
+
+ bms_initialize_constants(chip);
+
+ INIT_DELAYED_WORK(&chip->calculate_soc_delayed_work,
+ calculate_soc_work);
+
+ read_shutdown_soc_and_iavg(chip);
dev_set_drvdata(&spmi->dev, chip);
device_init_wakeup(&spmi->dev, 1);
+ calculate_soc_work(&(chip->calculate_soc_delayed_work.work));
+
/* setup & register the battery power supply */
chip->bms_psy.name = "bms";
chip->bms_psy.type = POWER_SUPPLY_TYPE_BMS;
@@ -302,6 +1993,12 @@
goto unregister_dc;
}
+ vbatt = 0;
+ get_battery_voltage(&vbatt);
+
+ pr_info("OK battery_capacity_at_boot=%d vbatt = %d\n",
+ get_prop_bms_capacity(chip),
+ vbatt);
pr_info("probe success\n");
return 0;
diff --git a/drivers/power/qpnp-charger.c b/drivers/power/qpnp-charger.c
index bc012ca..b5559db 100644
--- a/drivers/power/qpnp-charger.c
+++ b/drivers/power/qpnp-charger.c
@@ -702,7 +702,7 @@
}
static int
-qpnp_chg_charge_dis(struct qpnp_chg_chip *chip, int disable)
+qpnp_chg_force_run_on_batt(struct qpnp_chg_chip *chip, int disable)
{
/* This bit forces the charger to run off of the battery rather
* than a connected charger */
@@ -784,11 +784,9 @@
switch (psp) {
case POWER_SUPPLY_PROP_CHARGING_ENABLED:
- if (val->intval)
- qpnp_chg_charge_en(chip, val->intval);
- else
- qpnp_chg_charge_dis(chip, val->intval);
chip->charging_disabled = !(val->intval);
+ qpnp_chg_charge_en(chip, !chip->charging_disabled);
+ qpnp_chg_force_run_on_batt(chip, chip->charging_disabled);
break;
default:
return -EINVAL;
@@ -1275,7 +1273,7 @@
qpnp_chg_is_usb_chg_plugged_in(chip));
qpnp_chg_charge_en(chip, !chip->charging_disabled);
- qpnp_chg_charge_dis(chip, chip->charging_disabled);
+ qpnp_chg_force_run_on_batt(chip, chip->charging_disabled);
pr_info("Probe success !\n");
return 0;
diff --git a/drivers/power/smb137c-charger.c b/drivers/power/smb137c-charger.c
new file mode 100644
index 0000000..9cdf5b5
--- /dev/null
+++ b/drivers/power/smb137c-charger.c
@@ -0,0 +1,1369 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/power_supply.h>
+#include <linux/slab.h>
+
+struct smb137c_chip {
+ struct i2c_client *client;
+ struct power_supply psy;
+ struct power_supply *usb_psy;
+ struct mutex lock;
+ int charge_current_limit_ua;
+ int input_current_limit_ua;
+ int term_current_ua;
+ bool charging_enabled;
+ bool otg_mode_enabled;
+ bool charging_allowed;
+};
+
+struct input_current_config {
+ int current_limit_ua;
+ u8 cmd_b_reg;
+ u8 var_func_reg;
+ u8 input_cur_reg;
+};
+
+struct term_current_config {
+ int term_current_ua;
+ u8 charge_cur_reg;
+};
+
+#define INPUT_CURRENT(_current_limit_ua, _cmd_b_reg, _var_func_reg, \
+ _input_cur_reg) \
+ { \
+ .current_limit_ua = _current_limit_ua, \
+ .cmd_b_reg = _cmd_b_reg, \
+ .var_func_reg = _var_func_reg, \
+ .input_cur_reg = _input_cur_reg, \
+ }
+
+#define CHARGE_CURRENT_REG 0x00
+#define CHARGE_CURRENT_FAST_CHG_MASK 0xE0
+#define CHARGE_CURRENT_FAST_CHG_SHIFT 5
+#define CHARGE_CURRENT_PRE_CHG_MASK 0x18
+#define CHARGE_CURRENT_PRE_CHG_SHIFT 3
+#define CHARGE_CURRENT_TERM_CUR_MASK 0x06
+
+#define INPUT_CURRENT_REG 0x01
+#define INPUT_CURRENT_LIMIT_MASK 0xE0
+
+#define FLOAT_VOLTAGE_REG 0x02
+#define FLOAT_VOLTAGE_MASK 0x7F
+#define FLOAT_VOLTAGE_SHIFT 0
+
+#define CTRL_A_REG 0x03
+#define CTRL_A_AUTO_RECHARGE_MASK 0x80
+#define CTRL_A_AUTO_RECHARGE_ENABLED 0x00
+#define CTRL_A_AUTO_RECHARGE_DISABLED 0x80
+#define CTRL_A_TERM_CUR_MASK 0x40
+#define CTRL_A_TERM_CUR_ENABLED 0x00
+#define CTRL_A_TERM_CUR_DISABLED 0x40
+#define CTRL_A_THRESH_VOLTAGE_MASK 0x38
+#define CTRL_A_THRESH_VOLTAGE_SHIFT 3
+#define CTRL_A_VOUTL_MASK 0x02
+#define CTRL_A_VOUTL_4250MV 0x00
+#define CTRL_A_VOUTL_4460MV 0x02
+#define CTRL_A_THERM_MONITOR_MASK 0x01
+#define CTRL_A_THERM_MONITOR_ENABLED 0x01
+#define CTRL_A_THERM_MONITOR_DISABLED 0x00
+
+#define PIN_CTRL_REG 0x05
+#define PIN_CTRL_DEAD_BATT_CHG_MASK 0x80
+#define PIN_CTRL_DEAD_BATT_CHG_ENABLED 0x80
+#define PIN_CTRL_DEAD_BATT_CHG_DISABLED 0x00
+#define PIN_CTRL_OTG_LBR_MASK 0x20
+#define PIN_CTRL_OTG 0x00
+#define PIN_CTRL_LBR 0x20
+#define PIN_CTRL_USB_CUR_LIMIT_MASK 0x10
+#define PIN_CTRL_USB_CUR_LIMIT_REG 0x00
+#define PIN_CTRL_USB_CUR_LIMIT_PIN 0x10
+#define PIN_CTRL_CHG_EN_MASK 0x0C
+#define PIN_CTRL_CHG_EN_REG_LOW 0x00
+#define PIN_CTRL_CHG_EN_REG_HIGH 0x04
+#define PIN_CTRL_CHG_EN_PIN_LOW 0x08
+#define PIN_CTRL_CHG_EN_PIN_HIGH 0x0C
+#define PIN_CTRL_OTG_CTRL_MASK 0x02
+#define PIN_CTRL_OTG_CTRL_REG 0x00
+#define PIN_CTRL_OTG_CTRL_PIN 0x02
+
+#define OTG_CTRL_REG 0x06
+#define OTG_CTRL_BMD_MASK 0x80
+#define OTG_CTRL_BMD_ENABLED 0x80
+#define OTG_CTRL_BMD_DISABLED 0x00
+#define OTG_CTRL_AUTO_RECHARGE_MASK 0x40
+#define OTG_CTRL_AUTO_RECHARGE_75MV 0x00
+#define OTG_CTRL_AUTO_RECHARGE_120MV 0x40
+
+#define TEMP_MON_REG 0x08
+#define TEMP_MON_THERM_CURRENT_MASK 0xC0
+#define TEMP_MON_THERM_CURRENT_SHIFT 6
+#define TEMP_MON_TEMP_LOW_MASK 0x38
+#define TEMP_MON_TEMP_LOW_SHIFT 3
+#define TEMP_MON_TEMP_HIGH_MASK 0x07
+#define TEMP_MON_TEMP_HIGH_SHIFT 0
+
+#define SAFETY_TIMER_REG 0x09
+#define SAFETY_TIMER_RELOAD_MASK 0x40
+#define SAFETY_TIMER_RELOAD_ENABLED 0x40
+#define SAFETY_TIMER_RELOAD_DISABLED 0x00
+#define SAFETY_TIMER_CHG_TIMEOUT_MASK 0x0C
+#define SAFETY_TIMER_CHG_TIMEOUT_SHIFT 2
+#define SAFETY_TIMER_PRE_CHG_TIME_MASK 0x03
+#define SAFETY_TIMER_PRE_CHG_TIME_SHIFT 0
+
+#define VAR_FUNC_REG 0x0C
+#define VAR_FUNC_USB_MODE_MASK 0x80
+#define VAR_FUNC_BMD_MASK 0x0C
+#define VAR_FUNC_BMD_DISABLED 0x00
+#define VAR_FUNC_BMD_ALGO_PERIODIC 0x04
+#define VAR_FUNC_BMD_ALGO 0x08
+#define VAR_FUNC_BMD_THERM 0x0C
+
+#define CMD_A_REG 0x30
+#define CMD_A_VOLATILE_WRITE_MASK 0x80
+#define CMD_A_VOLATILE_WRITE_ALLOW 0x80
+#define CMD_A_VOLATILE_WRITE_DISALLOW 0x00
+#define CMD_A_FAST_CHG_MASK 0x40
+#define CMD_A_FAST_CHG_ALLOW 0x40
+#define CMD_A_FAST_CHG_DISALLOW 0x00
+#define CMD_A_OTG_MASK 0x10
+#define CMD_A_OTG_ENABLED 0x10
+#define CMD_A_OTG_DISABLED 0x00
+#define CMD_A_CHARGING_MASK 0x02
+#define CMD_A_CHARGING_ENABLED 0x00
+#define CMD_A_CHARGING_DISABLED 0x02
+
+#define CMD_B_REG 0x31
+#define CMD_B_USB_MODE_MASK 0x03
+
+#define DEV_ID_REG 0x33
+#define DEV_ID_PART_MASK 0x80
+#define DEV_ID_PART_SMB137C 0x00
+#define DEV_ID_GUI_REV_MASK 0x70
+#define DEV_ID_GUI_REV_SHIFT 4
+#define DEV_ID_SILICON_REV_MASK 0x0F
+#define DEV_ID_SILICON_REV_SHIFT 0
+
+#define IRQ_STAT_A_REG 0x35
+#define IRQ_STAT_A_BATT_HOT 0x40
+#define IRQ_STAT_A_BATT_COLD 0x10
+
+#define IRQ_STAT_B_REG 0x36
+#define IRQ_STAT_B_BATT_OVERVOLT 0x40
+#define IRQ_STAT_B_BATT_MISSING 0x10
+#define IRQ_STAT_B_BATT_UNDERVOLT 0x04
+
+#define STAT_C_REG 0x3D
+#define STAT_C_CHG_ERROR 0x40
+#define STAT_C_VBATT_LEVEL_BELOW_2P1V 0x10
+#define STAT_C_CHG_STAT_MASK 0x06
+#define STAT_C_CHG_STAT_SHIFT 1
+#define STAT_C_CHG_ENABLED 0x01
+
+/* Charge status register values */
+enum smb137c_charge_status {
+ CHARGE_STAT_NO_CHG = 0,
+ CHARGE_STAT_PRE_CHG = 1,
+ CHARGE_STAT_FAST_CHG = 2,
+ CHARGE_STAT_TAPER_CHG = 3,
+};
+
+#define PRE_CHARGE_CURRENT_MIN_UA 50000
+#define PRE_CHARGE_CURRENT_MAX_UA 200000
+#define PRE_CHARGE_CURRENT_STEP_UA 50000
+
+#define FLOAT_VOLTAGE_MIN_UV 3460000
+#define FLOAT_VOLTAGE_MAX_UV 4730000
+#define FLOAT_VOLTAGE_STEP_UV 10000
+
+#define PRE_CHG_THRESH_VOLTAGE_MIN_UV 2400000
+#define PRE_CHG_THRESH_VOLTAGE_MAX_UV 3100000
+#define PRE_CHG_THRESH_VOLTAGE_STEP_UV 100000
+
+#define USB_MIN_CURRENT_UA 100000
+
+static int smb137c_read_reg(struct smb137c_chip *chip, u8 reg, u8 *val)
+{
+ int rc;
+
+ rc = i2c_smbus_read_byte_data(chip->client, reg);
+ if (rc < 0) {
+ pr_err("i2c_smbus_read_byte_data failed. reg=0x%02X, rc=%d\n",
+ reg, rc);
+ } else {
+ *val = rc;
+ rc = 0;
+ pr_debug("read(0x%02X)=0x%02X\n", reg, *val);
+ }
+
+ return rc;
+}
+
+static int smb137c_write_reg(struct smb137c_chip *chip, u8 reg, u8 val)
+{
+ int rc;
+
+ rc = i2c_smbus_write_byte_data(chip->client, reg, val);
+ if (rc < 0)
+ pr_err("i2c_smbus_write_byte_data failed. reg=0x%02X, rc=%d\n",
+ reg, rc);
+ else
+ pr_debug("write(0x%02X)=0x%02X\n", reg, val);
+
+ return rc;
+}
+
+static int smb137c_masked_write_reg(struct smb137c_chip *chip, u8 reg, u8 mask,
+ u8 val)
+{
+ u8 reg_val;
+ int rc;
+
+ pr_debug("masked write(0x%02X), mask=0x%02X, value=0x%02X\n", reg, mask,
+ val);
+
+ rc = smb137c_read_reg(chip, reg, ®_val);
+ if (rc < 0)
+ return rc;
+
+ val = (reg_val & ~mask) | (val & mask);
+
+ if (val != reg_val)
+ rc = smb137c_write_reg(chip, reg, val);
+
+ return rc;
+}
+
+static int smb137c_enable_charging(struct smb137c_chip *chip)
+{
+ int rc = 0;
+
+ chip->charging_allowed = true;
+
+ if (chip->input_current_limit_ua > 0
+ && chip->charge_current_limit_ua > 0) {
+ if (!chip->charging_enabled)
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG,
+ CMD_A_CHARGING_MASK, CMD_A_CHARGING_ENABLED);
+ chip->charging_enabled = true;
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s\n", __func__);
+ }
+
+ return rc;
+}
+
+static int smb137c_disable_charging(struct smb137c_chip *chip)
+{
+ int rc = 0;
+
+ chip->charging_allowed = false;
+
+ if (chip->charging_enabled) {
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG,
+ CMD_A_CHARGING_MASK, CMD_A_CHARGING_DISABLED);
+ }
+
+ chip->charging_enabled = false;
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s\n", __func__);
+
+ return rc;
+}
+
+static int smb137c_enable_otg_mode(struct smb137c_chip *chip)
+{
+ int rc = 0;
+
+ if (!chip->otg_mode_enabled) {
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG, CMD_A_OTG_MASK,
+ CMD_A_OTG_ENABLED);
+ chip->otg_mode_enabled = true;
+ }
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s\n", __func__);
+
+ return rc;
+}
+
+static int smb137c_disable_otg_mode(struct smb137c_chip *chip)
+{
+ int rc = 0;
+
+ if (chip->otg_mode_enabled) {
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG, CMD_A_OTG_MASK,
+ CMD_A_OTG_DISABLED);
+ chip->otg_mode_enabled = false;
+ }
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s\n", __func__);
+
+ return rc;
+}
+
+static struct input_current_config supported_input_current[] = {
+ INPUT_CURRENT(100000, 0x00, 0x00, 0x00),
+ INPUT_CURRENT(150000, 0x00, 0x80, 0x00),
+ INPUT_CURRENT(500000, 0x02, 0x00, 0x00),
+ INPUT_CURRENT(700000, 0x01, 0x00, 0x00),
+ INPUT_CURRENT(800000, 0x01, 0x00, 0x20),
+ INPUT_CURRENT(900000, 0x01, 0x00, 0x40),
+ INPUT_CURRENT(1000000, 0x01, 0x00, 0x60),
+ INPUT_CURRENT(1100000, 0x01, 0x00, 0x80),
+ INPUT_CURRENT(1200000, 0x01, 0x00, 0xA0),
+ INPUT_CURRENT(1300000, 0x01, 0x00, 0xC0),
+ INPUT_CURRENT(1500000, 0x01, 0x00, 0xE0),
+};
+
+static int smb137c_set_usb_input_current_limit(struct smb137c_chip *chip,
+ int current_limit_ua)
+{
+ struct input_current_config *config = NULL;
+ int rc = 0;
+ int i;
+
+ for (i = ARRAY_SIZE(supported_input_current) - 1; i >= 0; i--) {
+ if (current_limit_ua
+ >= supported_input_current[i].current_limit_ua) {
+ config = &supported_input_current[i];
+ break;
+ }
+ }
+
+ if (config) {
+ if (chip->input_current_limit_ua != config->current_limit_ua) {
+ rc = smb137c_masked_write_reg(chip, INPUT_CURRENT_REG,
+ INPUT_CURRENT_LIMIT_MASK, config->input_cur_reg);
+ if (rc)
+ return rc;
+
+ rc = smb137c_masked_write_reg(chip, VAR_FUNC_REG,
+ VAR_FUNC_USB_MODE_MASK, config->var_func_reg);
+ if (rc)
+ return rc;
+
+ rc = smb137c_masked_write_reg(chip, CMD_B_REG,
+ CMD_B_USB_MODE_MASK, config->cmd_b_reg);
+ if (rc)
+ return rc;
+
+ chip->input_current_limit_ua = config->current_limit_ua;
+ }
+
+ if (chip->charging_allowed)
+ rc = smb137c_enable_charging(chip);
+ } else {
+ /* Current limit is below all set points so disable charging. */
+ chip->input_current_limit_ua = 0;
+
+ rc = smb137c_disable_charging(chip);
+ }
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ chip->input_current_limit_ua);
+
+ return rc;
+}
+
+static int fast_charge_current_ua[] = {
+ 500000,
+ 650000,
+ 750000,
+ 850000,
+ 950000,
+ 1100000,
+ 1300000,
+ 1500000,
+};
+
+static int smb137c_set_charge_current_limit(struct smb137c_chip *chip,
+ int current_limit_ua)
+{
+ int fast_charge_limit_ua = 0;
+ int rc = 0;
+ u8 val = 0;
+ int i;
+
+ for (i = ARRAY_SIZE(fast_charge_current_ua) - 1; i >= 0; i--) {
+ if (current_limit_ua >= fast_charge_current_ua[i]) {
+ val = i << CHARGE_CURRENT_FAST_CHG_SHIFT;
+ fast_charge_limit_ua = fast_charge_current_ua[i];
+ break;
+ }
+ }
+
+ if (fast_charge_limit_ua
+ && chip->charge_current_limit_ua != fast_charge_limit_ua)
+ rc = smb137c_masked_write_reg(chip, CHARGE_CURRENT_REG,
+ CHARGE_CURRENT_FAST_CHG_MASK, val);
+ else if (fast_charge_limit_ua == 0)
+ rc = smb137c_disable_charging(chip);
+
+ chip->charge_current_limit_ua = fast_charge_limit_ua;
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ fast_charge_limit_ua);
+
+ return rc;
+}
+
+static int smb137c_get_charge_current_limit(struct smb137c_chip *chip)
+{
+ int fast_charge_limit_ua = 0;
+ u8 val = 0;
+ int rc, i;
+
+ rc = smb137c_read_reg(chip, CHARGE_CURRENT_REG, &val);
+ if (rc)
+ return rc;
+
+ i = (val & CHARGE_CURRENT_FAST_CHG_MASK)
+ >> CHARGE_CURRENT_FAST_CHG_SHIFT;
+
+ if (i >= 0 && i < ARRAY_SIZE(fast_charge_current_ua))
+ fast_charge_limit_ua = fast_charge_current_ua[i];
+
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ fast_charge_limit_ua);
+
+ return fast_charge_limit_ua;
+}
+
+static struct term_current_config term_current_ua[] = {
+ { 35000, 0x06},
+ { 50000, 0x00},
+ {100000, 0x02},
+ {150000, 0x04},
+};
+
+static int smb137c_set_term_current(struct smb137c_chip *chip,
+ int current_limit_ua)
+{
+ int term_current_limit_ua = 0;
+ int rc = 0;
+ u8 val = 0;
+ int i;
+
+ for (i = ARRAY_SIZE(term_current_ua) - 1; i >= 0; i--) {
+ if (current_limit_ua >= term_current_ua[i].term_current_ua) {
+ val = term_current_ua[i].charge_cur_reg;
+ term_current_limit_ua
+ = term_current_ua[i].term_current_ua;
+ break;
+ }
+ }
+
+ if (term_current_limit_ua) {
+ rc = smb137c_masked_write_reg(chip, CHARGE_CURRENT_REG,
+ CHARGE_CURRENT_TERM_CUR_MASK, val);
+ if (rc)
+ return rc;
+ rc = smb137c_masked_write_reg(chip, CTRL_A_REG,
+ CTRL_A_TERM_CUR_MASK, CTRL_A_TERM_CUR_ENABLED);
+ } else {
+ rc = smb137c_masked_write_reg(chip, CTRL_A_REG,
+ CTRL_A_TERM_CUR_MASK, CTRL_A_TERM_CUR_DISABLED);
+ }
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ term_current_limit_ua);
+
+ return rc;
+}
+
+static int smb137c_set_pre_charge_current_limit(struct smb137c_chip *chip,
+ int current_limit_ua)
+{
+ int setpoint, rc;
+ u8 val;
+
+ if (current_limit_ua < PRE_CHARGE_CURRENT_MIN_UA ||
+ current_limit_ua > PRE_CHARGE_CURRENT_MAX_UA) {
+ dev_err(&chip->client->dev, "%s: current limit out of bounds: %d\n",
+ __func__, current_limit_ua);
+ return -EINVAL;
+ }
+
+ setpoint = (current_limit_ua - PRE_CHARGE_CURRENT_MIN_UA)
+ / PRE_CHARGE_CURRENT_STEP_UA;
+ val = setpoint << CHARGE_CURRENT_PRE_CHG_SHIFT;
+
+ rc = smb137c_masked_write_reg(chip, CHARGE_CURRENT_REG,
+ CHARGE_CURRENT_PRE_CHG_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ setpoint * PRE_CHARGE_CURRENT_STEP_UA
+ + PRE_CHARGE_CURRENT_MIN_UA);
+
+ return rc;
+}
+
+static int smb137c_set_float_voltage(struct smb137c_chip *chip, int voltage_uv)
+{
+ int setpoint, rc;
+ u8 val;
+
+ if (voltage_uv < FLOAT_VOLTAGE_MIN_UV ||
+ voltage_uv > FLOAT_VOLTAGE_MAX_UV) {
+ dev_err(&chip->client->dev, "%s: voltage out of bounds: %d\n",
+ __func__, voltage_uv);
+ return -EINVAL;
+ }
+
+ setpoint = (voltage_uv - FLOAT_VOLTAGE_MIN_UV) / FLOAT_VOLTAGE_STEP_UV;
+ val = setpoint << FLOAT_VOLTAGE_SHIFT;
+
+ rc = smb137c_masked_write_reg(chip, FLOAT_VOLTAGE_REG,
+ FLOAT_VOLTAGE_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: voltage=%d uV\n", __func__,
+ setpoint * FLOAT_VOLTAGE_STEP_UV + FLOAT_VOLTAGE_MIN_UV);
+
+ return rc;
+}
+
+static int smb137c_set_pre_charge_threshold_voltage(struct smb137c_chip *chip,
+ int voltage_uv)
+{
+ int setpoint, rc;
+ u8 val;
+
+ if (voltage_uv < PRE_CHG_THRESH_VOLTAGE_MIN_UV ||
+ voltage_uv > PRE_CHG_THRESH_VOLTAGE_MAX_UV) {
+ dev_err(&chip->client->dev, "%s: voltage out of bounds: %d\n",
+ __func__, voltage_uv);
+ return -EINVAL;
+ }
+
+ setpoint = (voltage_uv - PRE_CHG_THRESH_VOLTAGE_MIN_UV)
+ / PRE_CHG_THRESH_VOLTAGE_STEP_UV;
+ val = setpoint << CTRL_A_THRESH_VOLTAGE_SHIFT;
+
+ rc = smb137c_masked_write_reg(chip, CTRL_A_REG,
+ CTRL_A_THRESH_VOLTAGE_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: voltage=%d uV\n", __func__,
+ setpoint * PRE_CHG_THRESH_VOLTAGE_STEP_UV
+ + PRE_CHG_THRESH_VOLTAGE_MIN_UV);
+
+ return rc;
+}
+
+static int smb137c_set_recharge_threshold_voltage(struct smb137c_chip *chip,
+ int voltage_uv)
+{
+ int rc;
+ u8 val;
+
+ if (voltage_uv == 75000) {
+ val = OTG_CTRL_AUTO_RECHARGE_75MV;
+ } else if (voltage_uv == 120000) {
+ val = OTG_CTRL_AUTO_RECHARGE_120MV;
+ } else {
+ dev_err(&chip->client->dev, "%s: voltage out of bounds: %d\n",
+ __func__, voltage_uv);
+ return -EINVAL;
+ }
+
+ rc = smb137c_masked_write_reg(chip, OTG_CTRL_REG,
+ OTG_CTRL_AUTO_RECHARGE_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: voltage=%d uV\n", __func__,
+ voltage_uv);
+
+ return rc;
+}
+
+static int smb137c_set_system_voltage(struct smb137c_chip *chip, int voltage_uv)
+{
+ int rc;
+ u8 val;
+
+ if (voltage_uv == 4250000) {
+ val = CTRL_A_VOUTL_4250MV;
+ } else if (voltage_uv == 4460000) {
+ val = CTRL_A_VOUTL_4460MV;
+ } else {
+ dev_err(&chip->client->dev, "%s: voltage out of bounds: %d\n",
+ __func__, voltage_uv);
+ return -EINVAL;
+ }
+
+ rc = smb137c_masked_write_reg(chip, CTRL_A_REG, CTRL_A_VOUTL_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: voltage=%d uV\n", __func__,
+ voltage_uv);
+
+ return rc;
+}
+
+static int charging_timeout[] = {
+ 382,
+ 764,
+ 1527,
+};
+
+static int smb137c_set_charging_timeout(struct smb137c_chip *chip, int timeout)
+{
+ int timeout_chosen = 0;
+ u8 val = 3 << SAFETY_TIMER_CHG_TIMEOUT_SHIFT;
+ int rc, i;
+
+ for (i = ARRAY_SIZE(charging_timeout) - 1; i >= 0; i--) {
+ if (timeout >= charging_timeout[i]) {
+ val = i << SAFETY_TIMER_CHG_TIMEOUT_SHIFT;
+ timeout_chosen = charging_timeout[i];
+ break;
+ }
+ }
+
+ rc = smb137c_masked_write_reg(chip, SAFETY_TIMER_REG,
+ SAFETY_TIMER_CHG_TIMEOUT_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: timeout=%d min\n", __func__,
+ timeout_chosen);
+
+ return rc;
+}
+
+static int pre_charge_timeout[] = {
+ 48,
+ 95,
+ 191,
+};
+
+static int smb137c_set_pre_charge_timeout(struct smb137c_chip *chip,
+ int timeout)
+{
+ int timeout_chosen = 0;
+ u8 val = 3 << SAFETY_TIMER_PRE_CHG_TIME_SHIFT;
+ int rc, i;
+
+ for (i = ARRAY_SIZE(pre_charge_timeout) - 1; i >= 0; i--) {
+ if (timeout >= pre_charge_timeout[i]) {
+ val = i << SAFETY_TIMER_PRE_CHG_TIME_SHIFT;
+ timeout_chosen = pre_charge_timeout[i];
+ break;
+ }
+ }
+
+ rc = smb137c_masked_write_reg(chip, SAFETY_TIMER_REG,
+ SAFETY_TIMER_PRE_CHG_TIME_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: timeout=%d min\n", __func__,
+ timeout_chosen);
+
+ return rc;
+}
+
+static int thermistor_current[] = {
+ 100,
+ 40,
+ 20,
+ 10,
+};
+
+static int smb137c_set_thermistor_current(struct smb137c_chip *chip,
+ int current_ua)
+{
+ bool found = false;
+ u8 val = 0;
+ int rc, i;
+
+ for (i = 0; i < ARRAY_SIZE(thermistor_current); i++) {
+ if (current_ua == thermistor_current[i]) {
+ found = true;
+ val = i << TEMP_MON_THERM_CURRENT_SHIFT;
+ }
+ }
+
+ if (!found) {
+ dev_err(&chip->client->dev, "%s: current out of bounds: %d\n",
+ __func__, current_ua);
+ return -EINVAL;
+ }
+
+ rc = smb137c_masked_write_reg(chip, TEMP_MON_REG,
+ TEMP_MON_THERM_CURRENT_MASK, val);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: current=%d uA\n", __func__,
+ current_ua);
+
+ return 0;
+}
+
+static int smb137c_set_temperature_low_limit(struct smb137c_chip *chip,
+ int value)
+{
+ int rc;
+
+ if (value < 0 || value > 7) {
+ dev_err(&chip->client->dev, "%s: temperature value out of bounds: %d\n",
+ __func__, value);
+ return -EINVAL;
+ }
+
+ rc = smb137c_masked_write_reg(chip, TEMP_MON_REG,
+ TEMP_MON_TEMP_LOW_MASK, value << TEMP_MON_TEMP_LOW_SHIFT);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: temperature value=%d\n",
+ __func__, value);
+
+ return rc;
+}
+
+static int smb137c_set_temperature_high_limit(struct smb137c_chip *chip,
+ int value)
+{
+ int rc;
+
+ if (value < 0 || value > 7) {
+ dev_err(&chip->client->dev, "%s: temperature value out of bounds: %d\n",
+ __func__, value);
+ return -EINVAL;
+ }
+
+ rc = smb137c_masked_write_reg(chip, TEMP_MON_REG,
+ TEMP_MON_TEMP_HIGH_MASK, value << TEMP_MON_TEMP_HIGH_SHIFT);
+
+ if (!rc)
+ dev_dbg(&chip->client->dev, "%s: temperature value=%d\n",
+ __func__, value);
+
+ return rc;
+}
+
+static int charge_status_type_map[] = {
+ [CHARGE_STAT_NO_CHG] = POWER_SUPPLY_CHARGE_TYPE_NONE,
+ [CHARGE_STAT_PRE_CHG] = POWER_SUPPLY_CHARGE_TYPE_TRICKLE,
+ [CHARGE_STAT_FAST_CHG] = POWER_SUPPLY_CHARGE_TYPE_FAST,
+ [CHARGE_STAT_TAPER_CHG] = POWER_SUPPLY_CHARGE_TYPE_FAST,
+};
+
+static const char * const charge_status_name[] = {
+ [CHARGE_STAT_NO_CHG] = "none",
+ [CHARGE_STAT_PRE_CHG] = "pre-charge",
+ [CHARGE_STAT_FAST_CHG] = "fast-charge",
+ [CHARGE_STAT_TAPER_CHG] = "taper-charge",
+};
+
+static int smb137c_get_property_status(struct smb137c_chip *chip)
+{
+ int status = POWER_SUPPLY_STATUS_DISCHARGING;
+ enum smb137c_charge_status charging_status;
+ bool charging_enabled;
+ bool charging_error;
+ int rc;
+ u8 val;
+
+ rc = smb137c_read_reg(chip, STAT_C_REG, &val);
+ if (rc)
+ return POWER_SUPPLY_STATUS_UNKNOWN;
+
+ charging_enabled = val & STAT_C_CHG_ENABLED;
+ charging_error = val & STAT_C_CHG_ERROR;
+ charging_status = (val & STAT_C_CHG_STAT_MASK) >> STAT_C_CHG_STAT_SHIFT;
+
+ if (charging_enabled && !charging_error
+ && charging_status != CHARGE_STAT_NO_CHG)
+ status = POWER_SUPPLY_STATUS_CHARGING;
+
+ dev_dbg(&chip->client->dev, "%s: status=%s\n", __func__,
+ (status == POWER_SUPPLY_STATUS_CHARGING ? "charging"
+ : "discharging"));
+
+ return status;
+}
+
+static int smb137c_get_property_battery_present(struct smb137c_chip *chip)
+{
+ int rc;
+ u8 val;
+
+ rc = smb137c_read_reg(chip, IRQ_STAT_B_REG, &val);
+ if (rc || (val & IRQ_STAT_B_BATT_MISSING))
+ return 0;
+
+ /* Treat battery voltage less than 2.1 V as battery not present. */
+ rc = smb137c_read_reg(chip, STAT_C_REG, &val);
+ if (rc || (val & STAT_C_VBATT_LEVEL_BELOW_2P1V))
+ return 0;
+
+ return 1;
+}
+
+static int smb137c_get_property_battery_health(struct smb137c_chip *chip)
+{
+ int rc;
+ u8 val;
+
+ /* The health of a disconnected battery is unknown. */
+ if (!smb137c_get_property_battery_present(chip))
+ return POWER_SUPPLY_HEALTH_UNKNOWN;
+
+ rc = smb137c_read_reg(chip, IRQ_STAT_B_REG, &val);
+ if (rc)
+ return POWER_SUPPLY_HEALTH_UNKNOWN;
+
+ if (val & IRQ_STAT_B_BATT_OVERVOLT)
+ return POWER_SUPPLY_HEALTH_OVERVOLTAGE;
+ else if (val & IRQ_STAT_B_BATT_UNDERVOLT)
+ return POWER_SUPPLY_HEALTH_DEAD;
+
+ rc = smb137c_read_reg(chip, IRQ_STAT_A_REG, &val);
+ if (rc)
+ return POWER_SUPPLY_HEALTH_UNKNOWN;
+
+ if (val & IRQ_STAT_A_BATT_HOT)
+ return POWER_SUPPLY_HEALTH_OVERHEAT;
+ else if (val & IRQ_STAT_A_BATT_COLD)
+ return POWER_SUPPLY_HEALTH_COLD;
+
+ return POWER_SUPPLY_HEALTH_GOOD;
+}
+
+static int smb137c_get_property_charge_type(struct smb137c_chip *chip)
+{
+ enum smb137c_charge_status status;
+ int charge_type = POWER_SUPPLY_CHARGE_TYPE_NONE;
+ bool charging_enabled;
+ bool charging_error;
+ int rc;
+ u8 val;
+
+ rc = smb137c_read_reg(chip, STAT_C_REG, &val);
+ if (rc)
+ return POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
+
+ charging_enabled = val & STAT_C_CHG_ENABLED;
+ charging_error = val & STAT_C_CHG_ERROR;
+ status = (val & STAT_C_CHG_STAT_MASK) >> STAT_C_CHG_STAT_SHIFT;
+
+ if (!charging_enabled) {
+ dev_dbg(&chip->client->dev, "%s: not charging\n", __func__);
+ } else if (charging_error) {
+ dev_warn(&chip->client->dev, "%s: charger error detected\n",
+ __func__);
+ } else {
+ charge_type = charge_status_type_map[status];
+ }
+
+ dev_dbg(&chip->client->dev, "%s: charging status=%s\n", __func__,
+ charge_status_name[status]);
+
+ return charge_type;
+}
+
+static enum power_supply_property smb137c_power_properties[] = {
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_HEALTH,
+ POWER_SUPPLY_PROP_PRESENT,
+ POWER_SUPPLY_PROP_CHARGING_ENABLED,
+ POWER_SUPPLY_PROP_CHARGE_TYPE,
+ POWER_SUPPLY_PROP_CURRENT_MAX,
+ POWER_SUPPLY_PROP_TECHNOLOGY,
+ POWER_SUPPLY_PROP_MODEL_NAME,
+ POWER_SUPPLY_PROP_MANUFACTURER,
+};
+
+static int smb137c_property_is_writeable(struct power_supply *psy,
+ enum power_supply_property psp)
+{
+ switch (psp) {
+ case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+ case POWER_SUPPLY_PROP_CURRENT_MAX:
+ return 1;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int smb137c_power_set_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ const union power_supply_propval *val)
+{
+ struct smb137c_chip *chip = container_of(psy, struct smb137c_chip, psy);
+
+ mutex_lock(&chip->lock);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+ if (val->intval)
+ smb137c_enable_charging(chip);
+ else
+ smb137c_disable_charging(chip);
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_MAX:
+ smb137c_set_charge_current_limit(chip, val->intval);
+ break;
+ default:
+ mutex_unlock(&chip->lock);
+ return -EINVAL;
+ }
+
+ mutex_unlock(&chip->lock);
+
+ power_supply_changed(&chip->psy);
+ return 0;
+}
+
+static int smb137c_power_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct smb137c_chip *chip = container_of(psy, struct smb137c_chip, psy);
+
+ mutex_lock(&chip->lock);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = smb137c_get_property_status(chip);
+ break;
+ case POWER_SUPPLY_PROP_HEALTH:
+ val->intval = smb137c_get_property_battery_health(chip);
+ break;
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = smb137c_get_property_battery_present(chip);
+ break;
+ case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+ val->intval = chip->charging_enabled;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_TYPE:
+ val->intval = smb137c_get_property_charge_type(chip);
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_MAX:
+ val->intval = chip->charge_current_limit_ua;
+ break;
+ case POWER_SUPPLY_PROP_TECHNOLOGY:
+ val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+ break;
+ case POWER_SUPPLY_PROP_MODEL_NAME:
+ val->strval = "SMB137C";
+ break;
+ case POWER_SUPPLY_PROP_MANUFACTURER:
+ val->strval = "Summit Microelectronics";
+ break;
+ default:
+ mutex_unlock(&chip->lock);
+ return -EINVAL;
+ }
+
+ mutex_unlock(&chip->lock);
+
+ return 0;
+}
+
+static void smb137c_external_power_changed(struct power_supply *psy)
+{
+ struct smb137c_chip *chip = container_of(psy, struct smb137c_chip, psy);
+ union power_supply_propval prop = {0,};
+ int scope = POWER_SUPPLY_SCOPE_DEVICE;
+ int current_limit = USB_MIN_CURRENT_UA;
+ int online = 0;
+ int rc;
+
+ mutex_lock(&chip->lock);
+ dev_dbg(&chip->client->dev, "%s: start\n", __func__);
+
+ rc = chip->usb_psy->get_property(chip->usb_psy,
+ POWER_SUPPLY_PROP_ONLINE, &prop);
+ if (rc)
+ dev_err(&chip->client->dev, "%s: could not read USB online property, rc=%d\n",
+ __func__, rc);
+ else
+ online = prop.intval;
+
+ rc = chip->usb_psy->get_property(chip->usb_psy, POWER_SUPPLY_PROP_SCOPE,
+ &prop);
+ if (rc)
+ dev_err(&chip->client->dev, "%s: could not read USB scope property, rc=%d\n",
+ __func__, rc);
+ else
+ scope = prop.intval;
+
+ rc = chip->usb_psy->get_property(chip->usb_psy,
+ POWER_SUPPLY_PROP_CURRENT_MAX, &prop);
+ if (rc)
+ dev_err(&chip->client->dev, "%s: could not read USB current_max property, rc=%d\n",
+ __func__, rc);
+ else
+ current_limit = prop.intval;
+
+ if (scope == POWER_SUPPLY_SCOPE_SYSTEM) {
+ /* USB host mode */
+ smb137c_disable_charging(chip);
+ smb137c_enable_otg_mode(chip);
+ } else if (online) {
+ /* USB online in device mode */
+ smb137c_set_usb_input_current_limit(chip, current_limit);
+ smb137c_enable_charging(chip);
+ smb137c_disable_otg_mode(chip);
+ } else {
+ /* USB offline */
+ smb137c_disable_charging(chip);
+ smb137c_disable_otg_mode(chip);
+ smb137c_set_usb_input_current_limit(chip, USB_MIN_CURRENT_UA);
+ }
+
+ dev_dbg(&chip->client->dev, "%s: end\n", __func__);
+ mutex_unlock(&chip->lock);
+
+ power_supply_changed(&chip->psy);
+}
+
+static int __devinit smb137c_set_register_defaults(struct smb137c_chip *chip)
+{
+ int rc;
+ u8 val, mask;
+
+ /* Allow volatile register writes. */
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG,
+ CMD_A_VOLATILE_WRITE_MASK, CMD_A_VOLATILE_WRITE_ALLOW);
+ if (rc)
+ return rc;
+
+ /* Do not reset register values on USB reinsertion. */
+ rc = smb137c_masked_write_reg(chip, SAFETY_TIMER_REG,
+ SAFETY_TIMER_RELOAD_MASK, SAFETY_TIMER_RELOAD_DISABLED);
+ if (rc)
+ return rc;
+
+ /* Set various default control parameters. */
+ val = PIN_CTRL_DEAD_BATT_CHG_ENABLED | PIN_CTRL_OTG
+ | PIN_CTRL_USB_CUR_LIMIT_REG | PIN_CTRL_CHG_EN_REG_LOW
+ | PIN_CTRL_OTG_CTRL_REG;
+ mask = PIN_CTRL_DEAD_BATT_CHG_MASK | PIN_CTRL_OTG_LBR_MASK
+ | PIN_CTRL_USB_CUR_LIMIT_MASK | PIN_CTRL_CHG_EN_MASK
+ | PIN_CTRL_OTG_CTRL_MASK;
+ rc = smb137c_masked_write_reg(chip, PIN_CTRL_REG, mask, val);
+ if (rc)
+ return rc;
+
+ /* Disable charging, disable OTG mode, and allow fast-charge current. */
+ val = CMD_A_CHARGING_DISABLED | CMD_A_OTG_DISABLED
+ | CMD_A_FAST_CHG_ALLOW;
+ mask = CMD_A_CHARGING_MASK | CMD_A_OTG_MASK | CMD_A_FAST_CHG_MASK;
+ rc = smb137c_masked_write_reg(chip, CMD_A_REG, mask, val);
+ if (rc)
+ return rc;
+
+ /* Enable auto recharging and full-time THERM monitor. */
+ val = CTRL_A_AUTO_RECHARGE_ENABLED | CTRL_A_THERM_MONITOR_ENABLED;
+ mask = CTRL_A_AUTO_RECHARGE_MASK | CTRL_A_THERM_MONITOR_MASK;
+ rc = smb137c_masked_write_reg(chip, CTRL_A_REG, mask, val);
+
+ return rc;
+}
+
+static int __devinit smb137c_apply_dt_configs(struct smb137c_chip *chip)
+{
+ struct device *dev = &chip->client->dev;
+ struct device_node *node = chip->client->dev.of_node;
+ int ret, current_ma, voltage_mv, timeout, value;
+ int rc = 0;
+
+ /*
+ * All device tree parameters are optional so it is ok if read calls
+ * fail.
+ */
+ ret = of_property_read_u32(node, "summit,chg-current-ma", ¤t_ma);
+ if (ret == 0) {
+ rc = smb137c_set_charge_current_limit(chip, current_ma * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set charge current, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ } else {
+ chip->charge_current_limit_ua
+ = smb137c_get_charge_current_limit(chip);
+ rc = chip->charge_current_limit_ua;
+ if (rc < 0) {
+ dev_err(dev, "%s: Failed to get charge current, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,term-current-ma", ¤t_ma);
+ if (ret == 0) {
+ rc = smb137c_set_term_current(chip, current_ma * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set termination current, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,pre-chg-current-ma",
+ ¤t_ma);
+ if (ret == 0) {
+ rc = smb137c_set_pre_charge_current_limit(chip,
+ current_ma * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set pre-charge current limit, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,float-voltage-mv",
+ &voltage_mv);
+ if (ret == 0) {
+ rc = smb137c_set_float_voltage(chip, voltage_mv * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set float voltage, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,thresh-voltage-mv",
+ &voltage_mv);
+ if (ret == 0) {
+ rc = smb137c_set_pre_charge_threshold_voltage(chip,
+ voltage_mv * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set fast-charge threshold voltage, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,recharge-thresh-mv",
+ &voltage_mv);
+ if (ret == 0) {
+ rc = smb137c_set_recharge_threshold_voltage(chip,
+ voltage_mv * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set recharge threshold voltage, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,system-voltage-mv",
+ &voltage_mv);
+ if (ret == 0) {
+ rc = smb137c_set_system_voltage(chip, voltage_mv * 1000);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set system voltage, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,charging-timeout", &timeout);
+ if (ret == 0) {
+ rc = smb137c_set_charging_timeout(chip, timeout);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set charging timeout, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,pre-charge-timeout", &timeout);
+ if (ret == 0) {
+ rc = smb137c_set_pre_charge_timeout(chip, timeout);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set pre-charge timeout, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,therm-current-ua", &value);
+ if (ret == 0) {
+ rc = smb137c_set_thermistor_current(chip, value);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set thermistor current, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,temperature-min", &value);
+ if (ret == 0) {
+ rc = smb137c_set_temperature_low_limit(chip, value);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set low temperature limit, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ ret = of_property_read_u32(node, "summit,temperature-max", &value);
+ if (ret == 0) {
+ rc = smb137c_set_temperature_high_limit(chip, value);
+ if (rc) {
+ dev_err(dev, "%s: Failed to set high temperature limit, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
+static int __devinit smb137c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct smb137c_chip *chip;
+ struct device *dev = &client->dev;
+ struct device_node *node = client->dev.of_node;
+ int rc = 0;
+ int gui_rev, silicon_rev;
+ u8 dev_id;
+
+ if (!node) {
+ dev_err(dev, "%s: device tree information missing\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(dev, "%s: SMBUS_BYTE_DATA unsupported\n", __func__);
+ return -EIO;
+ }
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip) {
+ dev_err(dev, "%s: devm_kzalloc failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ mutex_init(&chip->lock);
+ chip->client = client;
+ i2c_set_clientdata(client, chip);
+
+ chip->usb_psy = power_supply_get_by_name("usb");
+ if (!chip->usb_psy) {
+ dev_dbg(dev, "%s: USB supply not found; deferring charger probe\n",
+ __func__);
+ return -EPROBE_DEFER;
+ }
+
+ rc = smb137c_read_reg(chip, DEV_ID_REG, &dev_id);
+ if (rc)
+ return rc;
+
+ if ((dev_id & DEV_ID_PART_MASK) != DEV_ID_PART_SMB137C) {
+ dev_err(dev, "%s: invalid device ID=0x%02X\n", __func__,
+ dev_id);
+ return -ENODEV;
+ }
+
+ gui_rev = (dev_id & DEV_ID_GUI_REV_MASK) >> DEV_ID_GUI_REV_SHIFT;
+ silicon_rev = (dev_id & DEV_ID_SILICON_REV_MASK)
+ >> DEV_ID_SILICON_REV_SHIFT;
+
+ rc = smb137c_set_register_defaults(chip);
+ if (rc)
+ return rc;
+
+ rc = smb137c_apply_dt_configs(chip);
+ if (rc)
+ return rc;
+
+ chip->psy.name = "battery";
+ chip->psy.type = POWER_SUPPLY_TYPE_BATTERY;
+ chip->psy.properties = smb137c_power_properties;
+ chip->psy.num_properties = ARRAY_SIZE(smb137c_power_properties);
+ chip->psy.get_property = smb137c_power_get_property;
+ chip->psy.set_property = smb137c_power_set_property;
+ chip->psy.property_is_writeable = smb137c_property_is_writeable;
+ chip->psy.external_power_changed = smb137c_external_power_changed;
+
+ rc = power_supply_register(dev, &chip->psy);
+ if (rc < 0) {
+ dev_err(dev, "%s: power_supply_register failed, rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ smb137c_external_power_changed(&chip->psy);
+
+ dev_info(dev, "%s: SMB137C charger probed successfully, gui_rev=%d, silicon_rev=%d\n",
+ __func__, gui_rev, silicon_rev);
+
+ return rc;
+}
+
+static int __devexit smb137c_remove(struct i2c_client *client)
+{
+ return 0;
+}
+
+static const struct i2c_device_id smb137c_id[] = {
+ { .name = "smb137c", },
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, smb137c_id);
+
+static const struct of_device_id smb137c_match[] = {
+ { .compatible = "summit,smb137c", },
+ { },
+};
+
+static struct i2c_driver smb137c_driver = {
+ .driver = {
+ .name = "smb137c",
+ .owner = THIS_MODULE,
+ .of_match_table = smb137c_match,
+ },
+ .probe = smb137c_probe,
+ .remove = __devexit_p(smb137c_remove),
+ .id_table = smb137c_id,
+};
+
+static int __init smb137c_init(void)
+{
+ return i2c_add_driver(&smb137c_driver);
+}
+module_init(smb137c_init);
+
+static void __exit smb137c_exit(void)
+{
+ return i2c_del_driver(&smb137c_driver);
+}
+module_exit(smb137c_exit);
+
+MODULE_DESCRIPTION("SMB137C Charger");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("i2c:smb137c");
diff --git a/drivers/power/smb350_charger.c b/drivers/power/smb350_charger.c
index 93e208c..dc0c4bd 100644
--- a/drivers/power/smb350_charger.c
+++ b/drivers/power/smb350_charger.c
@@ -55,6 +55,8 @@
#define CMD_B_REG 0x31 /* Volatile Read-Write */
#define CMD_C_REG 0x33 /* Volatile Read-Write */
+#define HW_VERSION_REG 0x34 /* Volatile Read-Only */
+
#define IRQ_STATUS_A_REG 0x35 /* Volatile Read-Only */
#define IRQ_STATUS_B_REG 0x36 /* Volatile Read-Only */
#define IRQ_STATUS_C_REG 0x37 /* Volatile Read-Only */
@@ -149,6 +151,7 @@
SMB350_DEBUG_REG(CMD_A),
SMB350_DEBUG_REG(CMD_B),
SMB350_DEBUG_REG(CMD_C),
+ SMB350_DEBUG_REG(HW_VERSION),
SMB350_DEBUG_REG(IRQ_STATUS_A),
SMB350_DEBUG_REG(IRQ_STATUS_B),
SMB350_DEBUG_REG(IRQ_STATUS_C),
@@ -212,21 +215,6 @@
return ret;
}
-#define SMB350_FLOAT_VOLT_BASE_MV 6920
-#define SMB350_FLOAT_VOLT_STEP_MV 40
-#define SMB350_FLOAT_VOLT_MAX_MV (6920 + 0x2F * 40)
-
-/* Fast-to-Taper charging volatge */
-static int smb350_get_float_voltage(struct i2c_client *client)
-{
- u16 val = smb350_read_reg(client, STATUS_A_REG);
-
- val = SMB350_FLOAT_VOLT_BASE_MV +
- ((val & 0x2F) * SMB350_FLOAT_VOLT_STEP_MV);
-
- return val;
-}
-
static bool smb350_is_dc_present(struct i2c_client *client)
{
u16 irq_status_f = smb350_read_reg(client, IRQ_STATUS_F_REG);
@@ -398,7 +386,6 @@
POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_ONLINE,
POWER_SUPPLY_PROP_CHARGE_TYPE,
- POWER_SUPPLY_PROP_VOLTAGE_NOW,
/* fixed */
POWER_SUPPLY_PROP_MANUFACTURER,
POWER_SUPPLY_PROP_MODEL_NAME,
@@ -429,10 +416,6 @@
case POWER_SUPPLY_PROP_CHARGE_TYPE:
val->intval = smb350_get_prop_charge_type(dev);
break;
- case POWER_SUPPLY_PROP_VOLTAGE_NOW:
- val->intval = smb350_get_float_voltage(client);
- val->intval *= 1000; /* mV to uV */
- break;
case POWER_SUPPLY_PROP_MODEL_NAME:
val->strval = SMB350_NAME;
break;
@@ -665,6 +648,7 @@
const struct smb350_platform_data *pdata;
struct device_node *dev_node = client->dev.of_node;
struct smb350_device *dev;
+ u8 version;
/* STAT pin change on start/stop charging */
u32 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
@@ -753,13 +737,25 @@
i2c_set_clientdata(client, dev);
- pr_debug("set charge-enable + not suspend.\n");
- gpio_set_value_cansleep(dev->chg_en_n_gpio, 1); /* Disable */
+ /* Disable battery charging by default on power up.
+ * Battery charging is enabled by BMS or Battery-Gauge
+ * by using the set_property callback.
+ */
+ smb350_enable_charging(dev, false);
msleep(100);
gpio_set_value_cansleep(dev->chg_susp_n_gpio, 1); /* Normal */
msleep(100); /* Allow the device to exist shutdown */
- smb350_read_reg(client, I2C_SLAVE_ADDR_REG);
+ /* I2C transaction allowed only after device exit suspend */
+ ret = smb350_read_reg(client, I2C_SLAVE_ADDR_REG);
+ if ((ret>>1) != client->addr) {
+ pr_err("No device.\n");
+ ret = -ENODEV;
+ goto err_no_dev;
+ }
+
+ version = smb350_read_reg(client, HW_VERSION_REG);
+ version &= 0x0F; /* bits 0..3 */
ret = smb350_set_volatile_params(dev);
if (ret)
@@ -784,7 +780,7 @@
goto err_irq;
}
- smb350_enable_charging(dev, true);
+ pr_info("HW Version = 0x%X.\n", version);
return 0;
@@ -792,6 +788,7 @@
err_debugfs:
if (dev->dent)
debugfs_remove_recursive(dev->dent);
+err_no_dev:
err_set_params:
gpio_free(dev->chg_en_n_gpio);
err_en_gpio:
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 57cde45..0ebb944 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1897,6 +1897,8 @@
if (rdev->desc->ops->list_voltage)
selector = rdev->desc->ops->list_voltage(rdev,
selector);
+ else if (rdev->desc->ops->get_voltage)
+ selector = rdev->desc->ops->get_voltage(rdev);
else
selector = -1;
} else if (rdev->desc->ops->set_voltage_sel) {
diff --git a/drivers/regulator/qpnp-regulator.c b/drivers/regulator/qpnp-regulator.c
index 0549593..a330f1b 100644
--- a/drivers/regulator/qpnp-regulator.c
+++ b/drivers/regulator/qpnp-regulator.c
@@ -550,11 +550,12 @@
}
static int qpnp_regulator_select_voltage(struct qpnp_regulator *vreg,
- int min_uV, int max_uV, int *range_sel, int *voltage_sel)
+ int min_uV, int max_uV, int *range_sel, int *voltage_sel,
+ unsigned *selector)
{
struct qpnp_voltage_range *range;
int uV = min_uV;
- int lim_min_uV, lim_max_uV, i;
+ int lim_min_uV, lim_max_uV, i, range_id;
/* Check if request voltage is outside of physically settable range. */
lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
@@ -575,7 +576,8 @@
for (i = vreg->set_points->count - 1; i > 0; i--)
if (uV > vreg->set_points->range[i - 1].max_uV)
break;
- range = &vreg->set_points->range[i];
+ range_id = i;
+ range = &vreg->set_points->range[range_id];
*range_sel = range->range_sel;
/*
@@ -594,6 +596,11 @@
return -EINVAL;
}
+ *selector = 0;
+ for (i = 0; i < range_id; i++)
+ *selector += vreg->set_points->range[i].n_voltages;
+ *selector += (uV - range->set_point_min_uV) / range->step_uV;
+
return 0;
}
@@ -605,7 +612,7 @@
u8 buf[2];
rc = qpnp_regulator_select_voltage(vreg, min_uV, max_uV, &range_sel,
- &voltage_sel);
+ &voltage_sel, selector);
if (rc) {
vreg_err(vreg, "could not set voltage, rc=%d\n", rc);
return rc;
@@ -669,7 +676,7 @@
int rc, range_sel, voltage_sel;
rc = qpnp_regulator_select_voltage(vreg, min_uV, max_uV, &range_sel,
- &voltage_sel);
+ &voltage_sel, selector);
if (rc) {
vreg_err(vreg, "could not set voltage, rc=%d\n", rc);
return rc;
diff --git a/drivers/slimbus/slim-msm-ctrl.c b/drivers/slimbus/slim-msm-ctrl.c
index 58a1d66..9c69f47 100644
--- a/drivers/slimbus/slim-msm-ctrl.c
+++ b/drivers/slimbus/slim-msm-ctrl.c
@@ -111,15 +111,16 @@
static int msm_sat_enqueue(struct msm_slim_sat *sat, u32 *buf, u8 len)
{
struct msm_slim_ctrl *dev = sat->dev;
- spin_lock(&sat->lock);
+ unsigned long flags;
+ spin_lock_irqsave(&sat->lock, flags);
if ((sat->stail + 1) % SAT_CONCUR_MSG == sat->shead) {
- spin_unlock(&sat->lock);
+ spin_unlock_irqrestore(&sat->lock, flags);
dev_err(dev->dev, "SAT QUEUE full!");
return -EXFULL;
}
memcpy(sat->sat_msgs[sat->stail], (u8 *)buf, len);
sat->stail = (sat->stail + 1) % SAT_CONCUR_MSG;
- spin_unlock(&sat->lock);
+ spin_unlock_irqrestore(&sat->lock, flags);
return 0;
}
@@ -618,6 +619,7 @@
u16 chh[40];
struct slim_ch prop;
u32 exp;
+ u16 *grph = NULL;
u8 coeff, cc;
u8 prrate = buf[6];
if (len <= 8)
@@ -638,6 +640,9 @@
return ret;
if (mc == SLIM_USR_MC_DEF_ACT_CHAN)
sat->satch[j].req_def++;
+ /* First channel in group from satellite */
+ if (i == 8)
+ grph = &sat->satch[j].chanh;
continue;
}
if (sat->nsatch >= MSM_MAX_SATCH)
@@ -649,6 +654,8 @@
sat->satch[j].chanh = chh[i - 8];
if (mc == SLIM_USR_MC_DEF_ACT_CHAN)
sat->satch[j].req_def++;
+ if (i == 8)
+ grph = &sat->satch[j].chanh;
sat->nsatch++;
}
prop.dataf = (enum slim_ch_dataf)((buf[3] & 0xE0) >> 5);
@@ -669,10 +676,12 @@
true, &chh[0]);
else
ret = slim_define_ch(&sat->satcl, &prop,
- &chh[0], 1, false, NULL);
+ chh, 1, true, &chh[0]);
dev_dbg(dev->dev, "define sat grp returned:%d", ret);
if (ret)
return ret;
+ else if (grph)
+ *grph = chh[0];
/* part of group so activating 1 will take care of rest */
if (mc == SLIM_USR_MC_DEF_ACT_CHAN)
@@ -805,6 +814,8 @@
slim_control_ch(&sat->satcl,
sat->satch[i].chanh,
SLIM_CH_REMOVE, true);
+ slim_dealloc_ch(&sat->satcl,
+ sat->satch[i].chanh);
sat->satch[i].reconf = false;
}
}
diff --git a/drivers/slimbus/slim-msm-ngd.c b/drivers/slimbus/slim-msm-ngd.c
index 1f2a95e..02e1952 100644
--- a/drivers/slimbus/slim-msm-ngd.c
+++ b/drivers/slimbus/slim-msm-ngd.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -144,6 +144,30 @@
return IRQ_HANDLED;
}
+static int ngd_clk_pause_wakeup(struct slim_controller *ctrl)
+{
+ struct msm_slim_ctrl *dev = slim_get_ctrldata(ctrl);
+ return msm_slim_qmi_power_request(dev, true);
+}
+
+static int ngd_qmi_available(struct notifier_block *n, unsigned long code,
+ void *_cmd)
+{
+ struct msm_slim_qmi *qmi = container_of(n, struct msm_slim_qmi, nb);
+ pr_info("Slimbus QMI NGD CB received event:%ld", code);
+ switch (code) {
+ case QMI_SERVER_ARRIVE:
+ complete(&qmi->qmi_comp);
+ break;
+ case QMI_SERVER_EXIT:
+ /* SSR implementation */
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
static int ngd_get_tid(struct slim_controller *ctrl, struct slim_msg_txn *txn,
u8 *tid, struct completion *done)
{
@@ -184,16 +208,21 @@
u32 *pbuf;
u8 *puc;
int ret = 0;
- int msgv = -1;
u8 la = txn->la;
u8 wbuf[SLIM_RX_MSGQ_BUF_LEN];
+ if (txn->mc == (SLIM_MSG_CLK_PAUSE_SEQ_FLG |
+ SLIM_MSG_MC_RECONFIGURE_NOW))
+ return msm_slim_qmi_power_request(dev, false);
+ else if (txn->mc & SLIM_MSG_CLK_PAUSE_SEQ_FLG)
+ return 0;
+
if (txn->mt == SLIM_MSG_MT_CORE &&
(txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW)) {
return 0;
}
- msgv = msm_slim_get_ctrl(dev);
+ msm_slim_get_ctrl(dev);
mutex_lock(&dev->tx_lock);
if (txn->mc != SLIM_USR_MC_REPORT_SATELLITE &&
(dev->state == MSM_CTRL_ASLEEP ||
@@ -206,8 +235,7 @@
if (timeout) {
mutex_lock(&dev->tx_lock);
} else {
- if (msgv >= 0)
- msm_slim_put_ctrl(dev);
+ msm_slim_put_ctrl(dev);
return -EBUSY;
}
}
@@ -293,8 +321,7 @@
*/
dev->pipes[wbuf[1]].connected = false;
mutex_unlock(&dev->tx_lock);
- if (msgv >= 0)
- msm_slim_put_ctrl(dev);
+ msm_slim_put_ctrl(dev);
return 0;
}
if (dev->err) {
@@ -336,8 +363,7 @@
txn->mc == SLIM_USR_MC_DISCONNECT_PORT)) {
int timeout;
mutex_unlock(&dev->tx_lock);
- if (msgv >= 0)
- msm_slim_put_ctrl(dev);
+ msm_slim_put_ctrl(dev);
timeout = wait_for_completion_timeout(txn->comp, HZ);
if (!timeout) {
pr_err("connect/disc :0x%x, tid:%d timed out", txn->mc,
@@ -353,8 +379,7 @@
}
ngd_xfer_err:
mutex_unlock(&dev->tx_lock);
- if (msgv >= 0)
- msm_slim_put_ctrl(dev);
+ msm_slim_put_ctrl(dev);
return ret ? ret : dev->err;
}
@@ -405,8 +430,9 @@
return -ENXIO;
}
if (txn.len == 0) {
+ /* Per protocol, only last 5 bits for client no. */
wbuf[txn.len++] = (u8) (slc->prop.dataf << 5) |
- sb->laddr;
+ (sb->laddr & 0x1f);
wbuf[txn.len] = slc->seglen;
if (slc->coeff == SLIM_COEFF_3)
wbuf[txn.len] |= 1 << 5;
@@ -420,6 +446,7 @@
}
}
wbuf[txn.len++] = slc->chan;
+ pr_debug("slim define chan:%d, tid:0x%x", slc->chan, txn.tid);
}
if (txn.len) {
txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
@@ -448,8 +475,9 @@
return -ENXIO;
}
if (txn.len == 0) {
+ /* Per protocol, only last 5 bits for client no. */
wbuf[txn.len++] = (u8) (SLIM_CH_REMOVE << 6) |
- sb->laddr;
+ (sb->laddr & 0x1f);
ret = ngd_get_tid(ctrl, &txn, &wbuf[txn.len++], &done);
if (ret) {
pr_err("no tid for channel define?");
@@ -457,6 +485,7 @@
}
}
wbuf[txn.len++] = slc->chan;
+ pr_debug("slim remove chan:%d, tid:0x%x", slc->chan, txn.tid);
}
if (txn.len) {
txn.mc = SLIM_USR_MC_CHAN_CTRL;
@@ -544,6 +573,7 @@
wbuf[3] = SAT_MSG_PROT;
txn.wbuf = wbuf;
txn.len = 4;
+ pr_info("SLIM SAT: Received master capability");
dev->use_rx_msgqs = 1;
msm_slim_sps_init(dev, dev->bam_mem,
NGD_BASE(dev->ctrl.nr, dev->ver) + NGD_STATUS, true);
@@ -557,6 +587,12 @@
ret = ngd_xfer_msg(&dev->ctrl, &txn);
if (!ret) {
dev->state = MSM_CTRL_AWAKE;
+
+ pm_runtime_use_autosuspend(dev->dev);
+ pm_runtime_set_autosuspend_delay(dev->dev,
+ MSM_SLIM_AUTOSUSPEND);
+ pm_runtime_set_active(dev->dev);
+ pm_runtime_enable(dev->dev);
complete(&dev->reconf);
}
}
@@ -595,6 +631,41 @@
complete(txn->comp);
}
}
+
+static int ngd_slim_enable(struct msm_slim_ctrl *dev, bool enable)
+{
+ u32 ngd_int = (NGD_INT_RECFG_DONE | NGD_INT_TX_NACKED_2 |
+ NGD_INT_MSG_BUF_CONTE | NGD_INT_MSG_TX_INVAL |
+ NGD_INT_IE_VE_CHG | NGD_INT_DEV_ERR |
+ NGD_INT_TX_MSG_SENT | NGD_INT_RX_MSG_RCVD);
+ if (enable) {
+ int ret = msm_slim_qmi_init(dev, false);
+ if (ret)
+ return ret;
+ ret = msm_slim_qmi_power_request(dev, true);
+ if (ret)
+ return ret;
+ writel_relaxed(ngd_int, dev->base + NGD_INT_EN +
+ NGD_BASE(dev->ctrl.nr, dev->ver));
+ /*
+ * Enable NGD. Configure NGD in register acc. mode until master
+ * announcement is received
+ */
+ writel_relaxed(1, dev->base + NGD_BASE(dev->ctrl.nr, dev->ver));
+ /* make sure NGD enabling goes through */
+ mb();
+ } else {
+ writel_relaxed(0, dev->base + NGD_BASE(dev->ctrl.nr, dev->ver));
+ writel_relaxed(0, dev->base + NGD_INT_EN +
+ NGD_BASE(dev->ctrl.nr, dev->ver));
+ /* make sure NGD disabling goes through */
+ mb();
+ msm_slim_qmi_exit(dev);
+ }
+
+ return 0;
+}
+
static int ngd_slim_rx_msgq_thread(void *data)
{
struct msm_slim_ctrl *dev = (struct msm_slim_ctrl *)data;
@@ -605,6 +676,14 @@
u32 buffer[10];
u8 msg_len = 0;
+ wait_for_completion_interruptible(&dev->qmi.qmi_comp);
+ ret = ngd_slim_enable(dev, true);
+ /* Exit the thread if component can't be enabled */
+ if (ret) {
+ pr_err("Enabling NGD failed:%d", ret);
+ return 0;
+ }
+
while (!kthread_should_stop()) {
set_current_state(TASK_INTERRUPTIBLE);
ret = wait_for_completion_interruptible(notify);
@@ -648,7 +727,6 @@
struct resource *slim_mem;
struct resource *irq, *bam_irq;
enum apr_subsys_state q6_state;
- u32 ngd_int;
q6_state = apr_get_q6_state();
if (q6_state == APR_SUBSYS_DOWN) {
@@ -725,7 +803,7 @@
dev->ctrl.get_laddr = ngd_get_laddr;
dev->ctrl.allocbw = ngd_allocbw;
dev->ctrl.xfer_msg = ngd_xfer_msg;
- dev->ctrl.wakeup = NULL;
+ dev->ctrl.wakeup = ngd_clk_pause_wakeup;
dev->ctrl.config_port = msm_config_port;
dev->ctrl.port_xfer = msm_slim_port_xfer;
dev->ctrl.port_xfer_status = msm_slim_port_xfer_status;
@@ -743,10 +821,6 @@
dev->ver = readl_relaxed(dev->base);
/* Version info in 16 MSbits */
dev->ver >>= 16;
- ngd_int = (NGD_INT_RECFG_DONE | NGD_INT_TX_NACKED_2 |
- NGD_INT_MSG_BUF_CONTE | NGD_INT_MSG_TX_INVAL |
- NGD_INT_IE_VE_CHG | NGD_INT_DEV_ERR |
- NGD_INT_TX_MSG_SENT | NGD_INT_RX_MSG_RCVD);
init_completion(&dev->rx_msgq_notify);
/* Register with framework */
@@ -768,6 +842,15 @@
goto err_request_irq_failed;
}
+ init_completion(&dev->qmi.qmi_comp);
+ dev->qmi.nb.notifier_call = ngd_qmi_available;
+ ret = qmi_svc_event_notifier_register(SLIMBUS_QMI_SVC_ID,
+ SLIMBUS_QMI_INS_ID, &dev->qmi.nb);
+ if (ret) {
+ pr_err("Slimbus QMI service registration failed:%d", ret);
+ goto qmi_register_failed;
+ }
+
/* Fire up the Rx message queue thread */
dev->rx_msgq_thread = kthread_run(ngd_slim_rx_msgq_thread, dev,
NGD_SLIM_NAME "_ngd_msgq_thread");
@@ -777,30 +860,19 @@
goto err_thread_create_failed;
}
- writel_relaxed(ngd_int, dev->base + NGD_INT_EN +
- NGD_BASE(dev->ctrl.nr, dev->ver));
- /*
- * Enable NGD. Configure NGD in register access mode until master
- * announcement is received
- */
- writel_relaxed(1, dev->base + NGD_BASE(dev->ctrl.nr, dev->ver));
- /* make sure NGD enabling goes through */
- mb();
-
if (pdev->dev.of_node)
of_register_slim_devices(&dev->ctrl);
/* Add devices registered with board-info now that controller is up */
slim_ctrl_add_boarddevs(&dev->ctrl);
- pm_runtime_use_autosuspend(&pdev->dev);
- pm_runtime_set_autosuspend_delay(&pdev->dev, MSM_SLIM_AUTOSUSPEND);
- pm_runtime_set_active(&pdev->dev);
-
dev_dbg(dev->dev, "NGD SB controller is up!\n");
return 0;
err_thread_create_failed:
+ qmi_svc_event_notifier_unregister(SLIMBUS_QMI_SVC_ID,
+ SLIMBUS_QMI_INS_ID, &dev->qmi.nb);
+qmi_register_failed:
free_irq(dev->irq, dev);
err_request_irq_failed:
slim_del_controller(&dev->ctrl);
@@ -816,6 +888,9 @@
static int __devexit ngd_slim_remove(struct platform_device *pdev)
{
struct msm_slim_ctrl *dev = platform_get_drvdata(pdev);
+ ngd_slim_enable(dev, false);
+ qmi_svc_event_notifier_unregister(SLIMBUS_QMI_SVC_ID,
+ SLIMBUS_QMI_INS_ID, &dev->qmi.nb);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
free_irq(dev->irq, dev);
diff --git a/drivers/slimbus/slim-msm.c b/drivers/slimbus/slim-msm.c
index 7cd34d3..c62ac27 100644
--- a/drivers/slimbus/slim-msm.c
+++ b/drivers/slimbus/slim-msm.c
@@ -582,3 +582,351 @@
sps_deregister_bam_device(dev->bam.hdl);
}
}
+
+/* Slimbus QMI Messaging */
+#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
+#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
+#define SLIMBUS_QMI_POWER_REQ_V01 0x0021
+#define SLIMBUS_QMI_POWER_RESP_V01 0x0021
+
+enum slimbus_mode_enum_type_v01 {
+ /* To force a 32 bit signed enum. Do not change or use*/
+ SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
+ SLIMBUS_MODE_SATELLITE_V01 = 1,
+ SLIMBUS_MODE_MASTER_V01 = 2,
+ SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
+};
+
+enum slimbus_pm_enum_type_v01 {
+ /* To force a 32 bit signed enum. Do not change or use*/
+ SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
+ SLIMBUS_PM_INACTIVE_V01 = 1,
+ SLIMBUS_PM_ACTIVE_V01 = 2,
+ SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
+};
+
+struct slimbus_select_inst_req_msg_v01 {
+ /* Mandatory */
+ /* Hardware Instance Selection */
+ uint32_t instance;
+
+ /* Optional */
+ /* Optional Mode Request Operation */
+ /* Must be set to true if mode is being passed */
+ uint8_t mode_valid;
+ enum slimbus_mode_enum_type_v01 mode;
+};
+
+struct slimbus_select_inst_resp_msg_v01 {
+ /* Mandatory */
+ /* Result Code */
+ struct qmi_response_type_v01 resp;
+};
+
+struct slimbus_power_req_msg_v01 {
+ /* Mandatory */
+ /* Power Request Operation */
+ enum slimbus_pm_enum_type_v01 pm_req;
+};
+
+struct slimbus_power_resp_msg_v01 {
+ /* Mandatory */
+ /* Result Code */
+ struct qmi_response_type_v01 resp;
+};
+
+static struct elem_info slimbus_select_inst_req_msg_v01_ei[] = {
+ {
+ .data_type = QMI_UNSIGNED_4_BYTE,
+ .elem_len = 1,
+ .elem_size = sizeof(uint32_t),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
+ instance),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size = sizeof(uint8_t),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x10,
+ .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
+ mode_valid),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_UNSIGNED_4_BYTE,
+ .elem_len = 1,
+ .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x10,
+ .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
+ mode),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_EOTI,
+ .elem_len = 0,
+ .elem_size = 0,
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x00,
+ .offset = 0,
+ .ei_array = NULL,
+ },
+};
+
+static struct elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof(struct qmi_response_type_v01),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
+ resp),
+ .ei_array = get_qmi_response_type_v01_ei(),
+ },
+ {
+ .data_type = QMI_EOTI,
+ .elem_len = 0,
+ .elem_size = 0,
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x00,
+ .offset = 0,
+ .ei_array = NULL,
+ },
+};
+
+static struct elem_info slimbus_power_req_msg_v01_ei[] = {
+ {
+ .data_type = QMI_UNSIGNED_4_BYTE,
+ .elem_len = 1,
+ .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct slimbus_power_req_msg_v01, pm_req),
+ .ei_array = NULL,
+ },
+ {
+ .data_type = QMI_EOTI,
+ .elem_len = 0,
+ .elem_size = 0,
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x00,
+ .offset = 0,
+ .ei_array = NULL,
+ },
+};
+
+static struct elem_info slimbus_power_resp_msg_v01_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof(struct qmi_response_type_v01),
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
+ .ei_array = get_qmi_response_type_v01_ei(),
+ },
+ {
+ .data_type = QMI_EOTI,
+ .elem_len = 0,
+ .elem_size = 0,
+ .is_array = NO_ARRAY,
+ .tlv_type = 0x00,
+ .offset = 0,
+ .ei_array = NULL,
+ },
+};
+
+static void msm_slim_qmi_recv_msg(struct kthread_work *work)
+{
+ int rc;
+ struct msm_slim_qmi *qmi =
+ container_of(work, struct msm_slim_qmi, kwork);
+
+ rc = qmi_recv_msg(qmi->handle);
+ if (rc < 0)
+ pr_err("%s: Error receiving QMI message\n", __func__);
+}
+
+static void msm_slim_qmi_notify(struct qmi_handle *handle,
+ enum qmi_event_type event, void *notify_priv)
+{
+ struct msm_slim_ctrl *dev = notify_priv;
+ struct msm_slim_qmi *qmi = &dev->qmi;
+
+ switch (event) {
+ case QMI_RECV_MSG:
+ queue_kthread_work(&qmi->kworker, &qmi->kwork);
+ break;
+ default:
+ break;
+ }
+}
+
+static const char *get_qmi_error(struct qmi_response_type_v01 *r)
+{
+ if (r->result == QMI_RESULT_SUCCESS_V01 || r->error == QMI_ERR_NONE_V01)
+ return "No Error";
+ else if (r->error == QMI_ERR_NO_MEMORY_V01)
+ return "Out of Memory";
+ else if (r->error == QMI_ERR_INTERNAL_V01)
+ return "Unexpected error occurred";
+ else if (r->error == QMI_ERR_INCOMPATIBLE_STATE_V01)
+ return "Slimbus s/w already configured to a different mode";
+ else if (r->error == QMI_ERR_INVALID_ID_V01)
+ return "Slimbus hardware instance is not valid";
+ else
+ return "Unknown error";
+}
+
+static int msm_slim_qmi_send_select_inst_req(struct msm_slim_ctrl *dev,
+ struct slimbus_select_inst_req_msg_v01 *req)
+{
+ struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
+ struct msg_desc req_desc, resp_desc;
+ int rc;
+
+ req_desc.msg_id = SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01;
+ req_desc.max_msg_len = sizeof(*req);
+ req_desc.ei_array = slimbus_select_inst_req_msg_v01_ei;
+
+ resp_desc.msg_id = SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01;
+ resp_desc.max_msg_len = sizeof(resp);
+ resp_desc.ei_array = slimbus_select_inst_resp_msg_v01_ei;
+
+ rc = qmi_send_req_wait(dev->qmi.handle, &req_desc, req, sizeof(*req),
+ &resp_desc, &resp, sizeof(resp), 5000);
+ if (rc < 0) {
+ pr_err("%s: QMI send req failed %d\n", __func__, rc);
+ return rc;
+ }
+
+ /* Check the response */
+ if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
+ pr_err("%s: QMI request failed 0x%x (%s)\n", __func__,
+ resp.resp.result, get_qmi_error(&resp.resp));
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+static int msm_slim_qmi_send_power_request(struct msm_slim_ctrl *dev,
+ struct slimbus_power_req_msg_v01 *req)
+{
+ struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
+ struct msg_desc req_desc, resp_desc;
+ int rc;
+
+ req_desc.msg_id = SLIMBUS_QMI_POWER_REQ_V01;
+ req_desc.max_msg_len = sizeof(*req);
+ req_desc.ei_array = slimbus_power_req_msg_v01_ei;
+
+ resp_desc.msg_id = SLIMBUS_QMI_POWER_RESP_V01;
+ resp_desc.max_msg_len = sizeof(resp);
+ resp_desc.ei_array = slimbus_power_resp_msg_v01_ei;
+
+ rc = qmi_send_req_wait(dev->qmi.handle, &req_desc, req, sizeof(*req),
+ &resp_desc, &resp, sizeof(resp), 5000);
+ if (rc < 0) {
+ pr_err("%s: QMI send req failed %d\n", __func__, rc);
+ return rc;
+ }
+
+ /* Check the response */
+ if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
+ pr_err("%s: QMI request failed 0x%x (%s)\n", __func__,
+ resp.resp.result, get_qmi_error(&resp.resp));
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+int msm_slim_qmi_init(struct msm_slim_ctrl *dev, bool apps_is_master)
+{
+ int rc = 0;
+ struct qmi_handle *handle;
+ struct slimbus_select_inst_req_msg_v01 req;
+
+ init_kthread_worker(&dev->qmi.kworker);
+
+ dev->qmi.task = kthread_run(kthread_worker_fn,
+ &dev->qmi.kworker, "msm_slim_qmi_clnt%d", dev->ctrl.nr);
+
+ if (IS_ERR(dev->qmi.task)) {
+ pr_err("%s: Failed to create QMI client kthread\n", __func__);
+ return -ENOMEM;
+ }
+
+ init_kthread_work(&dev->qmi.kwork, msm_slim_qmi_recv_msg);
+
+ handle = qmi_handle_create(msm_slim_qmi_notify, dev);
+ if (!handle) {
+ rc = -ENOMEM;
+ pr_err("%s: QMI client handle alloc failed\n", __func__);
+ goto qmi_handle_create_failed;
+ }
+
+ rc = qmi_connect_to_service(handle, SLIMBUS_QMI_SVC_ID,
+ SLIMBUS_QMI_INS_ID);
+ if (rc < 0) {
+ pr_err("%s: QMI server not found\n", __func__);
+ goto qmi_connect_to_service_failed;
+ }
+
+ /* Instance is 0 based */
+ req.instance = dev->ctrl.nr - 1;
+ req.mode_valid = 1;
+
+ /* Mode indicates the role of the ADSP */
+ if (apps_is_master)
+ req.mode = SLIMBUS_MODE_SATELLITE_V01;
+ else
+ req.mode = SLIMBUS_MODE_MASTER_V01;
+
+ dev->qmi.handle = handle;
+
+ rc = msm_slim_qmi_send_select_inst_req(dev, &req);
+ if (rc) {
+ pr_err("%s: failed to select h/w instance\n", __func__);
+ goto qmi_select_instance_failed;
+ }
+
+ return 0;
+
+qmi_select_instance_failed:
+ dev->qmi.handle = NULL;
+qmi_connect_to_service_failed:
+ qmi_handle_destroy(handle);
+qmi_handle_create_failed:
+ flush_kthread_worker(&dev->qmi.kworker);
+ kthread_stop(dev->qmi.task);
+ dev->qmi.task = NULL;
+ return rc;
+}
+
+void msm_slim_qmi_exit(struct msm_slim_ctrl *dev)
+{
+ qmi_handle_destroy(dev->qmi.handle);
+ flush_kthread_worker(&dev->qmi.kworker);
+ kthread_stop(dev->qmi.task);
+ dev->qmi.task = NULL;
+ dev->qmi.handle = NULL;
+}
+
+int msm_slim_qmi_power_request(struct msm_slim_ctrl *dev, bool active)
+{
+ struct slimbus_power_req_msg_v01 req;
+
+ if (active)
+ req.pm_req = SLIMBUS_PM_ACTIVE_V01;
+ else
+ req.pm_req = SLIMBUS_PM_INACTIVE_V01;
+
+ return msm_slim_qmi_send_power_request(dev, &req);
+}
diff --git a/drivers/slimbus/slim-msm.h b/drivers/slimbus/slim-msm.h
index 7d50620..3daf7ee 100644
--- a/drivers/slimbus/slim-msm.h
+++ b/drivers/slimbus/slim-msm.h
@@ -12,6 +12,10 @@
#ifndef _SLIM_MSM_H
#define _SLIM_MSM_H
+
+#include <linux/kthread.h>
+#include <mach/msm_qmi_interface.h>
+
/* Per spec.max 40 bytes per received message */
#define SLIM_RX_MSGQ_BUF_LEN 40
@@ -64,6 +68,10 @@
#define MSM_MAX_NSATS 2
#define MSM_MAX_SATCH 32
+/* Slimbus QMI service */
+#define SLIMBUS_QMI_SVC_ID 0x0301
+#define SLIMBUS_QMI_INS_ID 1
+
#define PGD_THIS_EE(r, v) ((v) ? PGD_THIS_EE_V2(r) : PGD_THIS_EE_V1(r))
#define PGD_PORT(r, p, v) ((v) ? PGD_PORT_V2(r, p) : PGD_PORT_V1(r, p))
#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
@@ -161,6 +169,15 @@
bool connected;
};
+struct msm_slim_qmi {
+ struct qmi_handle *handle;
+ struct task_struct *task;
+ struct kthread_work kwork;
+ struct kthread_worker kworker;
+ struct completion qmi_comp;
+ struct notifier_block nb;
+};
+
struct msm_slim_ctrl {
struct slim_controller ctrl;
struct slim_framer framer;
@@ -197,6 +214,7 @@
enum msm_ctrl_state state;
int nsats;
u32 ver;
+ struct msm_slim_qmi qmi;
};
struct msm_sat_chan {
@@ -249,4 +267,8 @@
int msm_slim_sps_init(struct msm_slim_ctrl *dev, struct resource *bam_mem,
u32 pipe_reg, bool remote);
void msm_slim_sps_exit(struct msm_slim_ctrl *dev);
+
+void msm_slim_qmi_exit(struct msm_slim_ctrl *dev);
+int msm_slim_qmi_init(struct msm_slim_ctrl *dev, bool apps_is_master);
+int msm_slim_qmi_power_request(struct msm_slim_ctrl *dev, bool active);
#endif
diff --git a/drivers/slimbus/slimbus.c b/drivers/slimbus/slimbus.c
index 1e79dce..d5d6e0c 100644
--- a/drivers/slimbus/slimbus.c
+++ b/drivers/slimbus/slimbus.c
@@ -26,6 +26,7 @@
#define SLIM_HDL_TO_PORT(hdl) ((u32)(hdl) & 0xFF)
#define SLIM_HDL_TO_CHIDX(hdl) ((u16)(hdl) & 0xFF)
+#define SLIM_GRP_TO_NCHAN(hdl) ((u16)(hdl >> 8) & 0xFF)
#define SLIM_SLAVE_PORT(p, la) (((la)<<16) | (p))
#define SLIM_MGR_PORT(p) ((0xFF << 16) | (p))
@@ -767,6 +768,7 @@
list_for_each_entry(sbdev, &ctrl->devs, dev_list) {
if (memcmp(sbdev->e_addr, e_addr, 6) == 0) {
struct slim_driver *sbdrv;
+ sbdev->laddr = *laddr;
if (sbdev->dev.driver) {
sbdrv = to_slim_driver(sbdev->dev.driver);
if (sbdrv->device_up)
@@ -1845,7 +1847,7 @@
}
if (grp)
- *grph = chanh[0];
+ *grph = ((nchan << 8) | SLIM_HDL_TO_CHIDX(chanh[0]));
for (i = 0; i < nchan; i++) {
u8 chan = SLIM_HDL_TO_CHIDX(chanh[i]);
struct slim_ich *slc = &ctrl->chans[chan];
@@ -2868,6 +2870,7 @@
int ret = 0;
/* Get rid of the group flag in MSB if any */
u8 chan = SLIM_HDL_TO_CHIDX(chanh);
+ u8 nchan = 0;
struct slim_ich *slc = &ctrl->chans[chan];
if (!(slc->nextgrp & SLIM_START_GRP))
return -EINVAL;
@@ -2928,9 +2931,10 @@
}
}
- if (!(slc->nextgrp & SLIM_END_GRP))
+ nchan++;
+ if (nchan < SLIM_GRP_TO_NCHAN(chanh))
chan = SLIM_HDL_TO_CHIDX(slc->nextgrp);
- } while (!(slc->nextgrp & SLIM_END_GRP));
+ } while (nchan < SLIM_GRP_TO_NCHAN(chanh));
mutex_unlock(&ctrl->m_ctrl);
if (!ret && commit == true)
ret = slim_reconfigure_now(sb);
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index becd823..2161fac 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -4,3 +4,7 @@
obj-$(CONFIG_SPMI) += spmi.o spmi-resources.o
obj-$(CONFIG_SPMI_MSM_PMIC_ARB) += spmi-pmic-arb.o
obj-$(CONFIG_MSM_QPNP_INT) += qpnp-int.o
+
+ifdef CONFIG_DEBUG_FS
+obj-$(CONFIG_SPMI) += spmi-dbgfs.o
+endif
diff --git a/drivers/spmi/spmi-dbgfs.c b/drivers/spmi/spmi-dbgfs.c
new file mode 100644
index 0000000..a23f945
--- /dev/null
+++ b/drivers/spmi/spmi-dbgfs.c
@@ -0,0 +1,725 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * SPMI Debug-fs support.
+ *
+ * Hierarchy schema:
+ * /sys/kernel/debug/spmi
+ * /help -- static help text
+ * /spmi-0
+ * /spmi-0/address -- Starting register address for reads or writes
+ * /spmi-0/count -- number of registers to read (only on read)
+ * /spmi-0/data -- Triggers the SPMI formatted read.
+ * /spmi-0/data_raw -- Triggers the SPMI raw read or write
+ * /spmi-#
+ */
+
+#define DEBUG
+#define pr_fmt(fmt) "%s:%d: " fmt, __func__, __LINE__
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/debugfs.h>
+#include <linux/spmi.h>
+#include <linux/ctype.h>
+
+#define ADDR_LEN 6 /* 5 byte address + 1 space character */
+#define CHARS_PER_ITEM 3 /* Format is 'XX ' */
+#define ITEMS_PER_LINE 16 /* 16 data items per line */
+#define MAX_LINE_LENGTH (ADDR_LEN + (ITEMS_PER_LINE * CHARS_PER_ITEM) + 1)
+#define MAX_REG_PER_TRANSACTION (8)
+
+static const char *DFS_ROOT_NAME = "spmi";
+static const mode_t DFS_MODE = S_IRUSR | S_IWUSR;
+
+/* Log buffer */
+struct spmi_log_buffer {
+ u32 rpos; /* Current 'read' position in buffer */
+ u32 wpos; /* Current 'write' position in buffer */
+ u32 len; /* Length of the buffer */
+ char data[0]; /* Log buffer */
+};
+
+/* SPMI controller specific data */
+struct spmi_ctrl_data {
+ u32 cnt;
+ u32 addr;
+ struct list_head node;
+ struct spmi_controller *ctrl;
+};
+
+/* SPMI transaction parameters */
+struct spmi_trans {
+ u32 cnt; /* Number of bytes to read */
+ u32 addr; /* 20-bit address: SID + PID + Register offset */
+ u32 offset; /* Offset of last read data */
+ bool raw_data; /* Set to true for raw data dump */
+ struct spmi_controller *ctrl;
+ struct spmi_log_buffer *log; /* log buffer */
+};
+
+struct spmi_dbgfs {
+ struct dentry *root;
+ struct mutex lock;
+ struct list_head ctrl; /* List of spmi_ctrl_data nodes */
+ struct debugfs_blob_wrapper help_msg;
+};
+
+static struct spmi_dbgfs dbgfs_data = {
+ .lock = __MUTEX_INITIALIZER(dbgfs_data.lock),
+ .ctrl = LIST_HEAD_INIT(dbgfs_data.ctrl),
+ .help_msg = {
+ .data =
+"SPMI Debug-FS support\n"
+"\n"
+"Hierarchy schema:\n"
+"/sys/kernel/debug/spmi\n"
+" /help -- Static help text\n"
+" /spmi-0 -- Directory for SPMI bus 0\n"
+" /spmi-0/address -- Starting register address for reads or writes\n"
+" /spmi-0/count -- Number of registers to read (only used for reads)\n"
+" /spmi-0/data -- Initiates the SPMI read (formatted output)\n"
+" /spmi-0/data_raw -- Initiates the SPMI raw read or write\n"
+" /spmi-n -- Directory for SPMI bus n\n"
+"\n"
+"To perform SPMI read or write transactions, you need to first write the\n"
+"address of the slave device register to the 'address' file. For read\n"
+"transactions, the number of bytes to be read needs to be written to the\n"
+"'count' file.\n"
+"\n"
+"The 'address' file specifies the 20-bit address of a slave device register.\n"
+"The upper 4 bits 'address[19..16]' specify the slave identifier (SID) for\n"
+"the slave device. The lower 16 bits specify the slave register address.\n"
+"\n"
+"Reading from the 'data' file will initiate a SPMI read transaction starting\n"
+"from slave register 'address' for 'count' number of bytes.\n"
+"\n"
+"Writing to the 'data' file will initiate a SPMI write transaction starting\n"
+"from slave register 'address'. The number of registers written to will\n"
+"match the number of bytes written to the 'data' file.\n"
+"\n"
+"Example: Read 4 bytes starting at register address 0x1234 for SID 2\n"
+"\n"
+"echo 0x21234 > address\n"
+"echo 4 > count\n"
+"cat data\n"
+"\n"
+"Example: Write 3 bytes starting at register address 0x1008 for SID 1\n"
+"\n"
+"echo 0x11008 > address\n"
+"echo 0x01 0x02 0x03 > data\n"
+"\n"
+"Note that the count file is not used for writes. Since 3 bytes are\n"
+"written to the 'data' file, then 3 bytes will be written across the\n"
+"SPMI bus.\n\n",
+ },
+};
+
+static int spmi_dfs_open(struct spmi_ctrl_data *ctrl_data, struct file *file)
+{
+ struct spmi_log_buffer *log;
+ struct spmi_trans *trans;
+
+ size_t logbufsize = SZ_4K;
+
+ if (!ctrl_data) {
+ pr_err("No SPMI controller data\n");
+ return -EINVAL;
+ }
+
+ /* Per file "transaction" data */
+ trans = kzalloc(sizeof(*trans), GFP_KERNEL);
+
+ if (!trans) {
+ pr_err("Unable to allocate memory for transaction data\n");
+ return -ENOMEM;
+ }
+
+ /* Allocate log buffer */
+ log = kzalloc(logbufsize, GFP_KERNEL);
+
+ if (!log) {
+ kfree(trans);
+ pr_err("Unable to allocate memory for log buffer\n");
+ return -ENOMEM;
+ }
+
+ log->rpos = 0;
+ log->wpos = 0;
+ log->len = logbufsize - sizeof(*log);
+
+ trans->log = log;
+ trans->cnt = ctrl_data->cnt;
+ trans->addr = ctrl_data->addr;
+ trans->ctrl = ctrl_data->ctrl;
+ trans->offset = trans->addr;
+
+ file->private_data = trans;
+ return 0;
+}
+
+static int spmi_dfs_data_open(struct inode *inode, struct file *file)
+{
+ struct spmi_ctrl_data *ctrl_data = inode->i_private;
+ return spmi_dfs_open(ctrl_data, file);
+}
+
+static int spmi_dfs_raw_data_open(struct inode *inode, struct file *file)
+{
+ int rc;
+ struct spmi_trans *trans;
+ struct spmi_ctrl_data *ctrl_data = inode->i_private;
+
+ rc = spmi_dfs_open(ctrl_data, file);
+ trans = file->private_data;
+ trans->raw_data = true;
+ return rc;
+}
+
+static int spmi_dfs_close(struct inode *inode, struct file *file)
+{
+ struct spmi_trans *trans = file->private_data;
+
+ if (trans && trans->log) {
+ file->private_data = NULL;
+ kfree(trans->log);
+ kfree(trans);
+ }
+
+ return 0;
+}
+
+/**
+ * spmi_read_data: reads data across the SPMI bus
+ * @ctrl: The SPMI controller
+ * @buf: buffer to store the data read.
+ * @offset: SPMI address offset to start reading from.
+ * @cnt: The number of bytes to read.
+ *
+ * Returns 0 on success, otherwise returns error code from SPMI driver.
+ */
+static int
+spmi_read_data(struct spmi_controller *ctrl, uint8_t *buf, int offset, int cnt)
+{
+ int ret = 0;
+ int len;
+ uint8_t sid;
+ uint16_t addr;
+
+ while (cnt > 0) {
+ sid = (offset >> 16) & 0xF;
+ addr = offset & 0xFFFF;
+ len = min(cnt, MAX_REG_PER_TRANSACTION);
+
+ ret = spmi_ext_register_readl(ctrl, sid, addr, buf, len);
+ if (ret < 0) {
+ pr_err("SPMI read failed, err = %d\n", ret);
+ goto done;
+ }
+
+ cnt -= len;
+ buf += len;
+ offset += len;
+ }
+
+done:
+ return ret;
+}
+
+/**
+ * spmi_write_data: writes data across the SPMI bus
+ * @ctrl: The SPMI controller
+ * @buf: data to be written.
+ * @offset: SPMI address offset to start writing to.
+ * @cnt: The number of bytes to write.
+ *
+ * Returns 0 on success, otherwise returns error code from SPMI driver.
+ */
+static int
+spmi_write_data(struct spmi_controller *ctrl, uint8_t *buf, int offset, int cnt)
+{
+ int ret = 0;
+ int len;
+ uint8_t sid;
+ uint16_t addr;
+
+ while (cnt > 0) {
+ sid = (offset >> 16) & 0xF;
+ addr = offset & 0xFFFF;
+ len = min(cnt, MAX_REG_PER_TRANSACTION);
+
+ ret = spmi_ext_register_writel(ctrl, sid, addr, buf, len);
+ if (ret < 0) {
+ pr_err("SPMI write failed, err = %d\n", ret);
+ goto done;
+ }
+
+ cnt -= len;
+ buf += len;
+ offset += len;
+ }
+
+done:
+ return ret;
+}
+
+/**
+ * print_to_log: format a string and place into the log buffer
+ * @log: The log buffer to place the result into.
+ * @fmt: The format string to use.
+ * @...: The arguments for the format string.
+ *
+ * The return value is the number of characters written to @log buffer
+ * not including the trailing '\0'.
+ */
+static int print_to_log(struct spmi_log_buffer *log, const char *fmt, ...)
+{
+ va_list args;
+ int cnt;
+ char *buf = &log->data[log->wpos];
+ size_t size = log->len - log->wpos;
+
+ va_start(args, fmt);
+ cnt = vscnprintf(buf, size, fmt, args);
+ va_end(args);
+
+ log->wpos += cnt;
+ return cnt;
+}
+
+/**
+ * write_next_line_to_log: Writes a single "line" of data into the log buffer
+ * @trans: Pointer to SPMI transaction data.
+ * @offset: SPMI address offset to start reading from.
+ * @pcnt: Pointer to 'cnt' variable. Indicates the number of bytes to read.
+ *
+ * The 'offset' is a 20-bits SPMI address which includes a 4-bit slave id (SID),
+ * an 8-bit peripheral id (PID), and an 8-bit peripheral register address.
+ *
+ * On a successful read, the pcnt is decremented by the number of data
+ * bytes read across the SPMI bus. When the cnt reaches 0, all requested
+ * bytes have been read.
+ */
+static int
+write_next_line_to_log(struct spmi_trans *trans, int offset, size_t *pcnt)
+{
+ int i, j;
+ u8 data[ITEMS_PER_LINE];
+ struct spmi_log_buffer *log = trans->log;
+
+ int cnt = 0;
+ int padding = offset % ITEMS_PER_LINE;
+ int items_to_read = min(ARRAY_SIZE(data) - padding, *pcnt);
+ int items_to_log = min(ITEMS_PER_LINE, padding + items_to_read);
+
+ /* Buffer needs enough space for an entire line */
+ if ((log->len - log->wpos) < MAX_LINE_LENGTH)
+ goto done;
+
+ /* Read the desired number of "items" */
+ if (spmi_read_data(trans->ctrl, data, offset, items_to_read))
+ goto done;
+
+ *pcnt -= items_to_read;
+
+ /* Each line starts with the aligned offset (20-bit address) */
+ cnt = print_to_log(log, "%5.5X ", offset & 0xffff0);
+ if (cnt == 0)
+ goto done;
+
+ /* If the offset is unaligned, add padding to right justify items */
+ for (i = 0; i < padding; ++i) {
+ cnt = print_to_log(log, "-- ");
+ if (cnt == 0)
+ goto done;
+ }
+
+ /* Log the data items */
+ for (j = 0; i < items_to_log; ++i, ++j) {
+ cnt = print_to_log(log, "%2.2X ", data[j]);
+ if (cnt == 0)
+ goto done;
+ }
+
+ /* If the last character was a space, then replace it with a newline */
+ if (log->wpos > 0 && log->data[log->wpos - 1] == ' ')
+ log->data[log->wpos - 1] = '\n';
+
+done:
+ return cnt;
+}
+
+/**
+ * write_raw_data_to_log: Writes a single "line" of data into the log buffer
+ * @trans: Pointer to SPMI transaction data.
+ * @offset: SPMI address offset to start reading from.
+ * @pcnt: Pointer to 'cnt' variable. Indicates the number of bytes to read.
+ *
+ * The 'offset' is a 20-bits SPMI address which includes a 4-bit slave id (SID),
+ * an 8-bit peripheral id (PID), and an 8-bit peripheral register address.
+ *
+ * On a successful read, the pcnt is decremented by the number of data
+ * bytes read across the SPMI bus. When the cnt reaches 0, all requested
+ * bytes have been read.
+ */
+static int
+write_raw_data_to_log(struct spmi_trans *trans, int offset, size_t *pcnt)
+{
+ u8 data[16];
+ struct spmi_log_buffer *log = trans->log;
+
+ int i;
+ int cnt = 0;
+ int items_to_read = min(ARRAY_SIZE(data), *pcnt);
+
+ /* Buffer needs enough space for an entire line */
+ if ((log->len - log->wpos) < 80)
+ goto done;
+
+ /* Read the desired number of "items" */
+ if (spmi_read_data(trans->ctrl, data, offset, items_to_read))
+ goto done;
+
+ *pcnt -= items_to_read;
+
+ /* Log the data items */
+ for (i = 0; i < items_to_read; ++i) {
+ cnt = print_to_log(log, "0x%2.2X ", data[i]);
+ if (cnt == 0)
+ goto done;
+ }
+
+ /* If the last character was a space, then replace it with a newline */
+ if (log->wpos > 0 && log->data[log->wpos - 1] == ' ')
+ log->data[log->wpos - 1] = '\n';
+
+done:
+ return cnt;
+}
+
+/**
+ * get_log_data - reads data across the SPMI bus and saves to the log buffer
+ * @trans: Pointer to SPMI transaction data.
+ *
+ * Returns the number of "items" read or SPMI error code for read failures.
+ */
+static int get_log_data(struct spmi_trans *trans)
+{
+ int cnt;
+ int last_cnt;
+ int items_read;
+ int total_items_read = 0;
+ u32 offset = trans->offset;
+ size_t item_cnt = trans->cnt;
+ struct spmi_log_buffer *log = trans->log;
+ int (*write_to_log)(struct spmi_trans *, int, size_t *);
+
+ if (item_cnt == 0)
+ return 0;
+
+ if (trans->raw_data)
+ write_to_log = write_raw_data_to_log;
+ else
+ write_to_log = write_next_line_to_log;
+
+ /* Reset the log buffer 'pointers' */
+ log->wpos = log->rpos = 0;
+
+ /* Keep reading data until the log is full */
+ do {
+ last_cnt = item_cnt;
+ cnt = write_to_log(trans, offset, &item_cnt);
+ items_read = last_cnt - item_cnt;
+ offset += items_read;
+ total_items_read += items_read;
+ } while (cnt && item_cnt > 0);
+
+ /* Adjust the transaction offset and count */
+ trans->cnt = item_cnt;
+ trans->offset += total_items_read;
+
+ return total_items_read;
+}
+
+/**
+ * spmi_dfs_reg_write: write user's byte array (coded as string) over SPMI.
+ * @file: file pointer
+ * @buf: user data to be written.
+ * @count: maximum space available in @buf
+ * @ppos: starting position
+ * @return number of user byte written, or negative error value
+ */
+static ssize_t spmi_dfs_reg_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int bytes_read;
+ int data;
+ int pos = 0;
+ int cnt = 0;
+ u8 *values;
+ size_t ret = 0;
+
+ struct spmi_trans *trans = file->private_data;
+ u32 offset = trans->offset;
+
+ /* Make a copy of the user data */
+ char *kbuf = kmalloc(count + 1, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ ret = copy_from_user(kbuf, buf, count);
+ if (ret == count) {
+ pr_err("failed to copy data from user\n");
+ ret = -EFAULT;
+ goto free_buf;
+ }
+
+ count -= ret;
+ *ppos += count;
+ kbuf[count] = '\0';
+
+ /* Override the text buffer with the raw data */
+ values = kbuf;
+
+ /* Parse the data in the buffer. It should be a string of numbers */
+ while (sscanf(kbuf + pos, "%i%n", &data, &bytes_read) == 1) {
+ pos += bytes_read;
+ values[cnt++] = data & 0xff;
+ }
+
+ if (!cnt)
+ goto free_buf;
+
+ /* Perform the SPMI write(s) */
+ ret = spmi_write_data(trans->ctrl, values, offset, cnt);
+
+ if (ret) {
+ pr_err("SPMI write failed, err = %zu\n", ret);
+ } else {
+ ret = count;
+ trans->offset += cnt;
+ }
+
+free_buf:
+ kfree(kbuf);
+ return ret;
+}
+
+/**
+ * spmi_dfs_reg_read: reads value(s) over SPMI and fill user's buffer a
+ * byte array (coded as string)
+ * @file: file pointer
+ * @buf: where to put the result
+ * @count: maximum space available in @buf
+ * @ppos: starting position
+ * @return number of user bytes read, or negative error value
+ */
+static ssize_t spmi_dfs_reg_read(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct spmi_trans *trans = file->private_data;
+ struct spmi_log_buffer *log = trans->log;
+ size_t ret;
+ size_t len;
+
+ /* Is the the log buffer empty */
+ if (log->rpos >= log->wpos) {
+ if (get_log_data(trans) <= 0)
+ return 0;
+ }
+
+ len = min(count, log->wpos - log->rpos);
+
+ ret = copy_to_user(buf, &log->data[log->rpos], len);
+ if (ret == len) {
+ pr_err("error copy SPMI register values to user\n");
+ return -EFAULT;
+ }
+
+ /* 'ret' is the number of bytes not copied */
+ len -= ret;
+
+ *ppos += len;
+ log->rpos += len;
+ return len;
+}
+
+static const struct file_operations spmi_dfs_reg_fops = {
+ .open = spmi_dfs_data_open,
+ .release = spmi_dfs_close,
+ .read = spmi_dfs_reg_read,
+ .write = spmi_dfs_reg_write,
+};
+
+static const struct file_operations spmi_dfs_raw_data_fops = {
+ .open = spmi_dfs_raw_data_open,
+ .release = spmi_dfs_close,
+ .read = spmi_dfs_reg_read,
+ .write = spmi_dfs_reg_write,
+};
+
+/**
+ * spmi_dfs_create_fs: create debugfs file system.
+ * @return pointer to root directory or NULL if failed to create fs
+ */
+static struct dentry *spmi_dfs_create_fs(void)
+{
+ struct dentry *root, *file;
+
+ pr_debug("Creating SPMI debugfs file-system at\n");
+ root = debugfs_create_dir(DFS_ROOT_NAME, NULL);
+ if (IS_ERR(root)) {
+ pr_err("Error creating top level directory err:%ld",
+ (long)root);
+ if ((int)root == -ENODEV)
+ pr_err("debugfs is not enabled in the kernel");
+ return NULL;
+ }
+
+ dbgfs_data.help_msg.size = strlen(dbgfs_data.help_msg.data);
+
+ file = debugfs_create_blob("help", S_IRUGO, root, &dbgfs_data.help_msg);
+ if (!file) {
+ pr_err("error creating help entry\n");
+ goto err_remove_fs;
+ }
+ return root;
+
+err_remove_fs:
+ debugfs_remove_recursive(root);
+ return NULL;
+}
+
+/**
+ * spmi_dfs_get_root: return a pointer to SPMI debugfs root directory.
+ * @brief return a pointer to the existing directory, or if no root
+ * directory exists then create one. Directory is created with file that
+ * configures SPMI transaction, namely: sid, address, and count.
+ * @returns valid pointer on success or NULL
+ */
+struct dentry *spmi_dfs_get_root(void)
+{
+ if (dbgfs_data.root)
+ return dbgfs_data.root;
+
+ if (mutex_lock_interruptible(&dbgfs_data.lock) < 0)
+ return NULL;
+ /* critical section */
+ if (!dbgfs_data.root) { /* double checking idiom */
+ dbgfs_data.root = spmi_dfs_create_fs();
+ }
+ mutex_unlock(&dbgfs_data.lock);
+ return dbgfs_data.root;
+}
+
+/*
+ * spmi_dfs_add_controller: adds new spmi controller entry
+ * @return zero on success
+ */
+int spmi_dfs_add_controller(struct spmi_controller *ctrl)
+{
+ struct dentry *dir;
+ struct dentry *root;
+ struct dentry *file;
+ struct spmi_ctrl_data *ctrl_data;
+
+ pr_debug("Adding controller %s\n", ctrl->dev.kobj.name);
+ root = spmi_dfs_get_root();
+ if (!root)
+ return -ENOENT;
+
+ /* Allocate transaction data for the controller */
+ ctrl_data = kzalloc(sizeof(*ctrl_data), GFP_KERNEL);
+ if (!ctrl_data)
+ return -ENOMEM;
+
+ dir = debugfs_create_dir(ctrl->dev.kobj.name, root);
+ if (!dir) {
+ pr_err("Error creating entry for spmi controller %s\n",
+ ctrl->dev.kobj.name);
+ goto err_create_dir_failed;
+ }
+
+ ctrl_data->cnt = 1;
+ ctrl_data->ctrl = ctrl;
+
+ file = debugfs_create_u32("count", DFS_MODE, dir, &ctrl_data->cnt);
+ if (!file) {
+ pr_err("error creating 'count' entry\n");
+ goto err_remove_fs;
+ }
+
+ file = debugfs_create_x32("address", DFS_MODE, dir, &ctrl_data->addr);
+ if (!file) {
+ pr_err("error creating 'address' entry\n");
+ goto err_remove_fs;
+ }
+
+ file = debugfs_create_file("data", DFS_MODE, dir, ctrl_data,
+ &spmi_dfs_reg_fops);
+ if (!file) {
+ pr_err("error creating 'data' entry\n");
+ goto err_remove_fs;
+ }
+
+ file = debugfs_create_file("data_raw", DFS_MODE, dir, ctrl_data,
+ &spmi_dfs_raw_data_fops);
+ if (!file) {
+ pr_err("error creating 'data' entry\n");
+ goto err_remove_fs;
+ }
+
+ list_add(&ctrl_data->node, &dbgfs_data.ctrl);
+ return 0;
+
+err_remove_fs:
+ debugfs_remove_recursive(dir);
+err_create_dir_failed:
+ kfree(ctrl_data);
+ return -ENOMEM;
+}
+
+static void __exit spmi_dfs_delete_all_ctrl(struct list_head *head)
+{
+ struct list_head *pos, *tmp;
+
+ list_for_each_safe(pos, tmp, head) {
+ struct spmi_ctrl_data *ctrl_data;
+
+ ctrl_data = list_entry(pos, struct spmi_ctrl_data, node);
+ list_del(pos);
+ kfree(ctrl_data);
+ }
+}
+
+static void __exit spmi_dfs_destroy(void)
+{
+ pr_debug("de-initializing spmi debugfs ...");
+ if (mutex_lock_interruptible(&dbgfs_data.lock) < 0)
+ return;
+ if (dbgfs_data.root) {
+ debugfs_remove_recursive(dbgfs_data.root);
+ dbgfs_data.root = NULL;
+ spmi_dfs_delete_all_ctrl(&dbgfs_data.ctrl);
+ }
+ mutex_unlock(&dbgfs_data.lock);
+}
+
+module_exit(spmi_dfs_destroy);
+
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:spmi_debug_fs");
diff --git a/drivers/spmi/spmi-dbgfs.h b/drivers/spmi/spmi-dbgfs.h
new file mode 100644
index 0000000..0baa4db
--- /dev/null
+++ b/drivers/spmi/spmi-dbgfs.h
@@ -0,0 +1,21 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SPMI_DBGFS_H
+#define _SPMI_DBGFS_H
+
+#ifdef CONFIG_DEBUG_FS
+int spmi_dfs_add_controller(struct spmi_controller *ctrl);
+#else
+int spmi_dfs_add_controller(struct spmi_controller *ctrl) { return 0; }
+#endif
+
+#endif /* _SPMI_DBGFS_H */
diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
index 914df95..ad58240 100644
--- a/drivers/spmi/spmi.c
+++ b/drivers/spmi/spmi.c
@@ -22,6 +22,8 @@
#include <linux/module.h>
#include <linux/pm_runtime.h>
+#include "spmi-dbgfs.h"
+
struct spmii_boardinfo {
struct list_head list;
struct spmi_boardinfo board_info;
@@ -755,6 +757,7 @@
list_add_tail(&ctrl->list, &spmi_ctrl_list);
mutex_unlock(&board_lock);
+ spmi_dfs_add_controller(ctrl);
return 0;
exit:
diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig
index 9a99238..43d17c2 100644
--- a/drivers/staging/android/Kconfig
+++ b/drivers/staging/android/Kconfig
@@ -67,6 +67,15 @@
---help---
Register processes to be killed when memory is low
+config ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES
+ bool "Android Low Memory Killer: detect oom_adj values"
+ depends on ANDROID_LOW_MEMORY_KILLER
+ default y
+ ---help---
+ Detect oom_adj values written to
+ /sys/module/lowmemorykiller/parameters/adj and convert them
+ to oom_score_adj values.
+
source "drivers/staging/android/switch/Kconfig"
config ANDROID_INTF_ALARM_DEV
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index e73caf1..c67b75b 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -62,6 +62,81 @@
printk(x); \
} while (0)
+static int nr_free_zone_mtype_pages(struct zone *zone, int mtype)
+{
+ int order;
+ int sum = 0;
+
+ for (order = 0; order < MAX_ORDER; ++order) {
+ unsigned long freecount = 0;
+ struct free_area *area;
+ struct list_head *curr;
+
+ area = &(zone->free_area[order]);
+
+ list_for_each(curr, &area->free_list[mtype])
+ freecount++;
+
+ sum += freecount << order;
+ }
+ return sum;
+}
+
+static int nr_free_zone_pages(struct zone *zone, gfp_t gfp_mask)
+{
+ int sum = 0;
+ int mtype = allocflags_to_migratetype(gfp_mask);
+ int i = 0;
+ int *mtype_fallbacks = get_migratetype_fallbacks(mtype);
+
+ sum = nr_free_zone_mtype_pages(zone, mtype);
+
+ /*
+ * Also count the fallback pages
+ */
+ for (i = 0;; i++) {
+ int fallbacktype = mtype_fallbacks[i];
+ sum += nr_free_zone_mtype_pages(zone, fallbacktype);
+
+ if (fallbacktype == MIGRATE_RESERVE)
+ break;
+ }
+
+ return sum;
+}
+
+static int nr_free_pages(gfp_t gfp_mask)
+{
+ struct zoneref *z;
+ struct zone *zone;
+ int sum = 0;
+
+ struct zonelist *zonelist = node_zonelist(numa_node_id(), gfp_mask);
+
+ for_each_zone_zonelist(zone, z, zonelist, gfp_zone(gfp_mask)) {
+ sum += nr_free_zone_pages(zone, gfp_mask);
+ }
+
+ return sum;
+}
+
+
+static int test_task_flag(struct task_struct *p, int flag)
+{
+ struct task_struct *t = p;
+
+ do {
+ task_lock(t);
+ if (test_tsk_thread_flag(t, flag)) {
+ task_unlock(t);
+ return 1;
+ }
+ task_unlock(t);
+ } while_each_thread(p, t);
+
+ return 0;
+}
+
static int lowmem_shrink(struct shrinker *s, struct shrink_control *sc)
{
struct task_struct *tsk;
@@ -77,6 +152,15 @@
int other_file = global_page_state(NR_FILE_PAGES) -
global_page_state(NR_SHMEM);
+ if (sc->nr_to_scan > 0 && other_free > other_file) {
+ /*
+ * If the number of free pages is going to affect the decision
+ * of which process is selected then ensure only free pages
+ * which can satisfy the request are considered.
+ */
+ other_free = nr_free_pages(sc->gfp_mask);
+ }
+
if (lowmem_adj_size < array_size)
array_size = lowmem_adj_size;
if (lowmem_minfree_size < array_size)
@@ -111,16 +195,17 @@
if (tsk->flags & PF_KTHREAD)
continue;
+ if (time_before_eq(jiffies, lowmem_deathpending_timeout)) {
+ if (test_task_flag(tsk, TIF_MEMDIE)) {
+ rcu_read_unlock();
+ return 0;
+ }
+ }
+
p = find_lock_task_mm(tsk);
if (!p)
continue;
- if (test_tsk_thread_flag(p, TIF_MEMDIE) &&
- time_before_eq(jiffies, lowmem_deathpending_timeout)) {
- task_unlock(p);
- rcu_read_unlock();
- return 0;
- }
oom_score_adj = p->signal->oom_score_adj;
if (oom_score_adj < min_score_adj) {
task_unlock(p);
@@ -174,9 +259,94 @@
unregister_shrinker(&lowmem_shrinker);
}
+#ifdef CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES
+static int lowmem_oom_adj_to_oom_score_adj(int oom_adj)
+{
+ if (oom_adj == OOM_ADJUST_MAX)
+ return OOM_SCORE_ADJ_MAX;
+ else
+ return (oom_adj * OOM_SCORE_ADJ_MAX) / -OOM_DISABLE;
+}
+
+static void lowmem_autodetect_oom_adj_values(void)
+{
+ int i;
+ int oom_adj;
+ int oom_score_adj;
+ int array_size = ARRAY_SIZE(lowmem_adj);
+
+ if (lowmem_adj_size < array_size)
+ array_size = lowmem_adj_size;
+
+ if (array_size <= 0)
+ return;
+
+ oom_adj = lowmem_adj[array_size - 1];
+ if (oom_adj > OOM_ADJUST_MAX)
+ return;
+
+ oom_score_adj = lowmem_oom_adj_to_oom_score_adj(oom_adj);
+ if (oom_score_adj <= OOM_ADJUST_MAX)
+ return;
+
+ lowmem_print(1, "lowmem_shrink: convert oom_adj to oom_score_adj:\n");
+ for (i = 0; i < array_size; i++) {
+ oom_adj = lowmem_adj[i];
+ oom_score_adj = lowmem_oom_adj_to_oom_score_adj(oom_adj);
+ lowmem_adj[i] = oom_score_adj;
+ lowmem_print(1, "oom_adj %d => oom_score_adj %d\n",
+ oom_adj, oom_score_adj);
+ }
+}
+
+static int lowmem_adj_array_set(const char *val, const struct kernel_param *kp)
+{
+ int ret;
+
+ ret = param_array_ops.set(val, kp);
+
+ /* HACK: Autodetect oom_adj values in lowmem_adj array */
+ lowmem_autodetect_oom_adj_values();
+
+ return ret;
+}
+
+static int lowmem_adj_array_get(char *buffer, const struct kernel_param *kp)
+{
+ return param_array_ops.get(buffer, kp);
+}
+
+static void lowmem_adj_array_free(void *arg)
+{
+ param_array_ops.free(arg);
+}
+
+static struct kernel_param_ops lowmem_adj_array_ops = {
+ .set = lowmem_adj_array_set,
+ .get = lowmem_adj_array_get,
+ .free = lowmem_adj_array_free,
+};
+
+static const struct kparam_array __param_arr_adj = {
+ .max = ARRAY_SIZE(lowmem_adj),
+ .num = &lowmem_adj_size,
+ .ops = ¶m_ops_int,
+ .elemsize = sizeof(lowmem_adj[0]),
+ .elem = lowmem_adj,
+};
+#endif
+
module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR);
+#ifdef CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES
+__module_param_call(MODULE_PARAM_PREFIX, adj,
+ &lowmem_adj_array_ops,
+ .arr = &__param_arr_adj,
+ S_IRUGO | S_IWUSR, -1);
+__MODULE_PARM_TYPE(adj, "array of int");
+#else
module_param_array_named(adj, lowmem_adj, int, &lowmem_adj_size,
S_IRUGO | S_IWUSR);
+#endif
module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size,
S_IRUGO | S_IWUSR);
module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR);
diff --git a/drivers/thermal/msm8974-tsens.c b/drivers/thermal/msm8974-tsens.c
index 8e13fbf..4cb93b8 100644
--- a/drivers/thermal/msm8974-tsens.c
+++ b/drivers/thermal/msm8974-tsens.c
@@ -558,6 +558,7 @@
int tsens9_point2 = 0, tsens10_point2 = 0;
int tsens_base2_data = 0, tsens_calibration_mode = 0, temp = 0;
uint32_t calib_data[6], calib_redun_sel, calib_data_backup[4];
+ uint32_t calib_tsens_point1_data[11], calib_tsens_point2_data[11];
if (tmdev->calibration_less_mode)
goto calibration_less_mode;
@@ -619,45 +620,46 @@
tsens10_point1 = (calib_data_backup[2] &
TSENS10_POINT1_MASK_BACKUP) >>
TSENS10_POINT1_BACKUP_SHIFT;
- } else if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
- pr_debug("backup two point calibrationless mode\n");
- tsens_base2_data = (calib_data_backup[2] &
+ } else
+ goto calibration_less_mode;
+
+ if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
+ pr_debug("backup two point calibrationless mode\n");
+ tsens_base2_data = (calib_data_backup[2] &
TSENS_BASE2_BACKUP_MASK) >>
TSENS_POINT2_BASE_BACKUP_SHIFT;
- tsens0_point2 = (calib_data_backup[2] &
+ tsens0_point2 = (calib_data_backup[2] &
TSENS0_POINT2_BACKUP_MASK) >>
TSENS0_POINT2_BACKUP_SHIFT;
- tsens1_point2 = (calib_data_backup[3] &
+ tsens1_point2 = (calib_data_backup[3] &
TSENS1_POINT2_BACKUP_MASK);
- tsens2_point2 = (calib_data_backup[3] &
+ tsens2_point2 = (calib_data_backup[3] &
TSENS2_POINT2_BACKUP_MASK) >>
TSENS2_POINT2_BACKUP_SHIFT;
- tsens3_point2 = (calib_data_backup[3] &
+ tsens3_point2 = (calib_data_backup[3] &
TSENS3_POINT2_BACKUP_MASK) >>
TSENS3_POINT2_BACKUP_SHIFT;
- tsens4_point2 = (calib_data_backup[3] &
+ tsens4_point2 = (calib_data_backup[3] &
TSENS4_POINT2_BACKUP_MASK) >>
TSENS4_POINT2_BACKUP_SHIFT;
- tsens5_point2 = (calib_data[4] & TSENS5_POINT2_BACKUP_MASK) >>
- TSENS5_POINT2_BACKUP_SHIFT;
- tsens6_point2 = (calib_data[5] & TSENS6_POINT2_BACKUP_MASK);
- tsens7_point2 = (calib_data[5] & TSENS7_POINT2_BACKUP_MASK) >>
- TSENS7_POINT2_BACKUP_SHIFT;
- tsens8_point2 = (calib_data[5] & TSENS8_POINT2_BACKUP_MASK) >>
- TSENS8_POINT2_BACKUP_SHIFT;
- tsens9_point2 = (calib_data[5] & TSENS9_POINT2_BACKUP_MASK) >>
- TSENS9_POINT2_BACKUP_SHIFT;
- tsens10_point2 = (calib_data[5] & TSENS10_POINT2_BACKUP_MASK)
- >> TSENS10_POINT2_BACKUP_SHIFT;
- } else {
- pr_debug("TSENS:backup is calibrationless mode\n");
- for (i = 0; i < tmdev->tsens_num_sensor; i++) {
- tmdev->sensor[i].calib_data_point2 = 780;
- tmdev->sensor[i].calib_data_point1 = 492;
+ tsens5_point2 = (calib_data[4] &
+ TSENS5_POINT2_BACKUP_MASK) >>
+ TSENS5_POINT2_BACKUP_SHIFT;
+ tsens6_point2 = (calib_data[5] &
+ TSENS6_POINT2_BACKUP_MASK);
+ tsens7_point2 = (calib_data[5] &
+ TSENS7_POINT2_BACKUP_MASK) >>
+ TSENS7_POINT2_BACKUP_SHIFT;
+ tsens8_point2 = (calib_data[5] &
+ TSENS8_POINT2_BACKUP_MASK) >>
+ TSENS8_POINT2_BACKUP_SHIFT;
+ tsens9_point2 = (calib_data[5] &
+ TSENS9_POINT2_BACKUP_MASK) >>
+ TSENS9_POINT2_BACKUP_SHIFT;
+ tsens10_point2 = (calib_data[5] &
+ TSENS10_POINT2_BACKUP_MASK)
+ >> TSENS10_POINT2_BACKUP_SHIFT;
}
- tsens_calibration_mode = 0;
- goto compute_intercept_slope;
- }
} else {
tsens_calibration_mode = (calib_data[1] & TSENS_CAL_SEL_0_1)
>> TSENS_CAL_SEL_SHIFT;
@@ -690,7 +692,10 @@
tsens9_point1 = (calib_data[2] & TSENS9_POINT1_MASK);
tsens10_point1 = (calib_data[2] & TSENS10_POINT1_MASK)
>> TSENS10_POINT1_SHIFT;
- } else if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
+ } else
+ goto calibration_less_mode;
+
+ if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
pr_debug("TSENS is two point calibrationless mode\n");
tsens_base2_data = (calib_data[2] & TSENS_BASE2_MASK) >>
TSENS_POINT2_BASE_SHIFT;
@@ -714,120 +719,145 @@
TSENS9_POINT2_SHIFT;
tsens10_point2 = (calib_data[4] & TSENS10_POINT2_MASK)
>> TSENS10_POINT2_SHIFT;
- } else {
+ }
+
+ if (tsens_calibration_mode == 0) {
calibration_less_mode:
pr_debug("TSENS is calibrationless mode\n");
for (i = 0; i < tmdev->tsens_num_sensor; i++)
- tmdev->sensor[i].calib_data_point2 = 780;
- tmdev->sensor[0].calib_data_point1 = 502;
- tmdev->sensor[1].calib_data_point1 = 509;
- tmdev->sensor[2].calib_data_point1 = 503;
- tmdev->sensor[3].calib_data_point1 = 509;
- tmdev->sensor[4].calib_data_point1 = 505;
- tmdev->sensor[5].calib_data_point1 = 509;
- tmdev->sensor[6].calib_data_point1 = 507;
- tmdev->sensor[7].calib_data_point1 = 510;
- tmdev->sensor[8].calib_data_point1 = 508;
- tmdev->sensor[9].calib_data_point1 = 509;
- tmdev->sensor[10].calib_data_point1 = 508;
+ calib_tsens_point2_data[i] = 780;
+ calib_tsens_point1_data[0] = 502;
+ calib_tsens_point1_data[1] = 509;
+ calib_tsens_point1_data[2] = 503;
+ calib_tsens_point1_data[3] = 509;
+ calib_tsens_point1_data[4] = 505;
+ calib_tsens_point1_data[5] = 509;
+ calib_tsens_point1_data[6] = 507;
+ calib_tsens_point1_data[7] = 510;
+ calib_tsens_point1_data[8] = 508;
+ calib_tsens_point1_data[9] = 509;
+ calib_tsens_point1_data[10] = 508;
goto compute_intercept_slope;
}
}
if (tsens_calibration_mode == TSENS_ONE_POINT_CALIB) {
pr_debug("old one point calibration calculation\n");
- tmdev->sensor[0].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens0_point1;
- tmdev->sensor[1].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens1_point1;
- tmdev->sensor[2].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens2_point1;
- tmdev->sensor[3].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens3_point1;
- tmdev->sensor[4].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens4_point1;
- tmdev->sensor[5].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens5_point1;
- tmdev->sensor[6].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens6_point1;
- tmdev->sensor[7].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens7_point1;
- tmdev->sensor[8].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens8_point1;
- tmdev->sensor[9].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens9_point1;
- tmdev->sensor[10].calib_data_point1 =
- (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) + tsens10_point1;
+ calib_tsens_point1_data[0] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens0_point1;
+ calib_tsens_point1_data[1] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens1_point1;
+ calib_tsens_point1_data[2] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens2_point1;
+ calib_tsens_point1_data[3] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens3_point1;
+ calib_tsens_point1_data[4] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens4_point1;
+ calib_tsens_point1_data[5] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens5_point1;
+ calib_tsens_point1_data[6] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens6_point1;
+ calib_tsens_point1_data[7] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens7_point1;
+ calib_tsens_point1_data[8] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens8_point1;
+ calib_tsens_point1_data[9] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens9_point1;
+ calib_tsens_point1_data[10] =
+ (((tsens_base1_data) << 2) | TSENS_BIT_APPEND)
+ + tsens10_point1;
}
if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) ||
(tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) {
pr_debug("one and two point calibration calculation\n");
-
- tmdev->sensor[0].calib_data_point1 =
- ((((tsens_base1_data) + tsens0_point1) << 2) |
+ calib_tsens_point1_data[0] =
+ ((((tsens_base1_data) + tsens0_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[1].calib_data_point1 =
- ((((tsens_base1_data) + tsens1_point1) << 2) |
+ calib_tsens_point1_data[1] =
+ ((((tsens_base1_data) + tsens1_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[2].calib_data_point1 =
- ((((tsens_base1_data) + tsens2_point1) << 2) |
+ calib_tsens_point1_data[2] =
+ ((((tsens_base1_data) + tsens2_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[3].calib_data_point1 =
- ((((tsens_base1_data) + tsens3_point1) << 2) |
+ calib_tsens_point1_data[3] =
+ ((((tsens_base1_data) + tsens3_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[4].calib_data_point1 =
- ((((tsens_base1_data) + tsens4_point1) << 2) |
+ calib_tsens_point1_data[4] =
+ ((((tsens_base1_data) + tsens4_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[5].calib_data_point1 =
- ((((tsens_base1_data) + tsens5_point1) << 2) |
+ calib_tsens_point1_data[5] =
+ ((((tsens_base1_data) + tsens5_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[6].calib_data_point1 =
- ((((tsens_base1_data) + tsens6_point1) << 2) |
+ calib_tsens_point1_data[6] =
+ ((((tsens_base1_data) + tsens6_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[7].calib_data_point1 =
- ((((tsens_base1_data) + tsens7_point1) << 2) |
+ calib_tsens_point1_data[7] =
+ ((((tsens_base1_data) + tsens7_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[8].calib_data_point1 =
- ((((tsens_base1_data) + tsens8_point1) << 2) |
+ calib_tsens_point1_data[8] =
+ ((((tsens_base1_data) + tsens8_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[9].calib_data_point1 =
- ((((tsens_base1_data) + tsens9_point1) << 2) |
+ calib_tsens_point1_data[9] =
+ ((((tsens_base1_data) + tsens9_point1) << 2) |
TSENS_BIT_APPEND);
- tmdev->sensor[10].calib_data_point1 =
- ((((tsens_base1_data) + tsens10_point1) << 2) |
+ calib_tsens_point1_data[10] =
+ ((((tsens_base1_data) + tsens10_point1) << 2) |
TSENS_BIT_APPEND);
}
if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
pr_debug("two point calibration calculation\n");
- tmdev->sensor[0].calib_data_point2 =
- (((tsens_base2_data + tsens0_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[1].calib_data_point2 =
- (((tsens_base2_data + tsens1_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[2].calib_data_point2 =
- (((tsens_base2_data + tsens2_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[3].calib_data_point2 =
- (((tsens_base2_data + tsens3_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[4].calib_data_point2 =
- (((tsens_base2_data + tsens4_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[5].calib_data_point2 =
- (((tsens_base2_data + tsens5_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[6].calib_data_point2 =
- (((tsens_base2_data + tsens6_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[7].calib_data_point2 =
- (((tsens_base2_data + tsens7_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[8].calib_data_point2 =
- (((tsens_base2_data + tsens8_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[9].calib_data_point2 =
- (((tsens_base2_data + tsens9_point2) << 2) | TSENS_BIT_APPEND);
- tmdev->sensor[10].calib_data_point2 =
- (((tsens_base2_data + tsens10_point2) << 2) | TSENS_BIT_APPEND);
+ calib_tsens_point2_data[0] =
+ (((tsens_base2_data + tsens0_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[1] =
+ (((tsens_base2_data + tsens1_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[2] =
+ (((tsens_base2_data + tsens2_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[3] =
+ (((tsens_base2_data + tsens3_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[4] =
+ (((tsens_base2_data + tsens4_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[5] =
+ (((tsens_base2_data + tsens5_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[6] =
+ (((tsens_base2_data + tsens6_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[7] =
+ (((tsens_base2_data + tsens7_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[8] =
+ (((tsens_base2_data + tsens8_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[9] =
+ (((tsens_base2_data + tsens9_point2) << 2) |
+ TSENS_BIT_APPEND);
+ calib_tsens_point2_data[10] =
+ (((tsens_base2_data + tsens10_point2) << 2) |
+ TSENS_BIT_APPEND);
}
compute_intercept_slope:
for (i = 0; i < tmdev->tsens_num_sensor; i++) {
int32_t num = 0, den = 0;
+ tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i];
+ tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i];
if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) {
num = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT2;
den = tmdev->sensor[i].calib_data_point2 -
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index 4a9c9a3..84cd3e7 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -168,6 +168,7 @@
struct work_struct clock_off_w; /* work for actual clock off */
struct workqueue_struct *hsuart_wq; /* hsuart workqueue */
struct mutex clk_mutex; /* mutex to guard against clock off/clock on */
+ bool tty_flush_receive;
};
#define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */
@@ -1250,6 +1251,13 @@
}
+static void msm_hs_flush_buffer(struct uart_port *uport)
+{
+ struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
+
+ msm_uport->tty_flush_receive = true;
+}
+
/*
* Standard API, Break Signal
*
@@ -1465,7 +1473,14 @@
*/
mb();
/* Complete DMA TX transactions and submit new transactions */
- tx_buf->tail = (tx_buf->tail + tx->tx_count) & ~UART_XMIT_SIZE;
+
+ /* Do not update tx_buf.tail if uart_flush_buffer already
+ called in serial core */
+ if (!msm_uport->tty_flush_receive)
+ tx_buf->tail = (tx_buf->tail +
+ tx->tx_count) & ~UART_XMIT_SIZE;
+ else
+ msm_uport->tty_flush_receive = false;
tx->dma_in_flight = 0;
@@ -2209,6 +2224,7 @@
.config_port = msm_hs_config_port,
.release_port = msm_hs_release_port,
.request_port = msm_hs_request_port,
+ .flush_buffer = msm_hs_flush_buffer,
};
module_init(msm_serial_hs_init);
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index f065eaa..cc9ffaa 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -149,12 +149,9 @@
static int get_line(struct platform_device *pdev)
{
- const struct msm_serial_hslite_platform_data *pdata =
- pdev->dev.platform_data;
- if (pdata)
- return pdata->line;
+ struct msm_hsl_port *msm_hsl_port = platform_get_drvdata(pdev);
- return pdev->id;
+ return msm_hsl_port->uart.line;
}
static int clk_en(struct uart_port *port, int enable)
@@ -1357,18 +1354,35 @@
struct resource *uart_resource;
struct resource *gsbi_resource;
struct uart_port *port;
+ const struct msm_serial_hslite_platform_data *pdata;
const struct of_device_id *match;
+ u32 line;
int ret;
if (pdev->id == -1)
pdev->id = atomic_inc_return(&msm_serial_hsl_next_id) - 1;
- if (unlikely(get_line(pdev) < 0 || get_line(pdev) >= UART_NR))
+ /* Use line (ttyHSLx) number from pdata or device tree if specified */
+ pdata = pdev->dev.platform_data;
+ if (pdata)
+ line = pdata->line;
+ else
+ line = pdev->id;
+
+ /* Use line number from device tree alias if present */
+ if (pdev->dev.of_node) {
+ ret = of_alias_get_id(pdev->dev.of_node, "serial");
+ if (ret >= 0)
+ line = ret;
+ }
+
+ if (unlikely(line < 0 || line >= UART_NR))
return -ENXIO;
- printk(KERN_INFO "msm_serial_hsl: detected port #%d\n", pdev->id);
+ printk(KERN_INFO "msm_serial_hsl: detected port #%d (ttyHSL%d)\n",
+ pdev->id, line);
- port = get_port_from_line(get_line(pdev));
+ port = get_port_from_line(line);
port->dev = &pdev->dev;
msm_hsl_port = UART_TO_MSM(port);
diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
index a292416..494ec49 100644
--- a/drivers/usb/core/driver.c
+++ b/drivers/usb/core/driver.c
@@ -1405,7 +1405,6 @@
* (This can't be done in usb_resume_interface()
* above because it doesn't own the right set of locks.)
*/
- pm_runtime_get_sync(dev->parent);
status = usb_resume_both(udev, msg);
if (status == 0) {
pm_runtime_disable(dev);
@@ -1413,7 +1412,6 @@
pm_runtime_enable(dev);
unbind_no_reset_resume_drivers_interfaces(udev);
}
- pm_runtime_put_sync(dev->parent);
/* Avoid PM error messages for devices disconnected while suspended
* as we'll display regular disconnect messages just a bit later.
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 0531f83..4073fc8 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -1262,6 +1262,17 @@
dwc3_msm_write_readback(mdwc->base, HS_PHY_CTRL_REG,
0xC00000, 0x800000);
+ /* Sequence to put SSPHY in low power state:
+ * 1. Clear REF_SS_PHY_EN in SS_PHY_CTRL_REG
+ * 2. Clear REF_USE_PAD in SS_PHY_CTRL_REG
+ * 3. Set TEST_POWERED_DOWN in SS_PHY_CTRL_REG to enable PHY retention
+ * 4. Disable SSPHY ref clk
+ */
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 8), 0x0);
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 28), 0x0);
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 26),
+ (1 << 26));
+
usleep_range(1000, 1200);
clk_disable_unprepare(mdwc->ref_clk);
@@ -1290,6 +1301,8 @@
if (mdwc->otg_xceiv && mdwc->ext_xceiv.otg_capability)
dwc3_hsusb_ldo_enable(0);
+ dwc3_ssusb_ldo_enable(0);
+ dwc3_ssusb_config_vddcx(0);
dwc3_hsusb_config_vddcx(0);
wake_unlock(&mdwc->wlock);
atomic_set(&mdwc->in_lpm, 1);
@@ -1328,6 +1341,8 @@
if (mdwc->otg_xceiv && mdwc->ext_xceiv.otg_capability)
dwc3_hsusb_ldo_enable(1);
+ dwc3_ssusb_ldo_enable(1);
+ dwc3_ssusb_config_vddcx(1);
dwc3_hsusb_config_vddcx(1);
clk_prepare_enable(mdwc->ref_clk);
usleep_range(1000, 1200);
@@ -1342,14 +1357,26 @@
dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0),
dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)) | 0xF0000000);
- /* 20usec delay required before de-asserting PHY RESET */
- udelay(20);
+ /* 10usec delay required before de-asserting PHY RESET */
+ udelay(10);
dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0),
dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0)) & 0x7FFFFFFF);
/* Bring PHY out of suspend */
dwc3_msm_write_readback(mdwc->base, HS_PHY_CTRL_REG, 0xC00000, 0x0);
+ /* Assert SS PHY RESET */
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 7),
+ (1 << 7));
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 28),
+ (1 << 28));
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 8),
+ (1 << 8));
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 26), 0x0);
+ /* 10usec delay required before de-asserting SS PHY RESET */
+ udelay(10);
+ dwc3_msm_write_readback(mdwc->base, SS_PHY_CTRL_REG, (1 << 7), 0x0);
+
atomic_set(&mdwc->in_lpm, 0);
/* match disable_irq call from isr */
@@ -1741,7 +1768,9 @@
}
msm->ext_xceiv.otg_capability = of_property_read_bool(node,
- "qcom,dwc-usb3-msm-otg-capability");
+ "qcom,otg-capability");
+ msm->charger.charging_disabled = of_property_read_bool(node,
+ "qcom,charging-disabled");
if (!msm->ext_xceiv.otg_capability) {
/* DWC3 has separate IRQ line for OTG events (ID/BSV etc.) */
diff --git a/drivers/usb/dwc3/dwc3_otg.c b/drivers/usb/dwc3/dwc3_otg.c
index 1aa8519..7b672c4 100644
--- a/drivers/usb/dwc3/dwc3_otg.c
+++ b/drivers/usb/dwc3/dwc3_otg.c
@@ -100,11 +100,23 @@
static int dwc3_otg_start_host(struct usb_otg *otg, int on)
{
struct dwc3_otg *dotg = container_of(otg, struct dwc3_otg, otg);
+ struct dwc3 *dwc = dotg->dwc;
int ret = 0;
- if (!dotg->dwc->xhci)
+ if (!dwc->xhci)
return -EINVAL;
+ if (!dotg->vbus_otg) {
+ dotg->vbus_otg = devm_regulator_get(dwc->dev->parent,
+ "vbus_dwc3");
+ if (IS_ERR(dotg->vbus_otg)) {
+ dev_err(dwc->dev, "Failed to get vbus regulator\n");
+ ret = PTR_ERR(dotg->vbus_otg);
+ dotg->vbus_otg = 0;
+ return ret;
+ }
+ }
+
if (on) {
dev_dbg(otg->phy->dev, "%s: turn on host\n", __func__);
@@ -119,7 +131,7 @@
* anymore.
*/
dwc3_otg_set_host_regs(dotg);
- ret = platform_device_add(dotg->dwc->xhci);
+ ret = platform_device_add(dwc->xhci);
if (ret) {
dev_err(otg->phy->dev,
"%s: failed to add XHCI pdev ret=%d\n",
@@ -131,7 +143,7 @@
ret = regulator_enable(dotg->vbus_otg);
if (ret) {
dev_err(otg->phy->dev, "unable to enable vbus_otg\n");
- platform_device_del(dotg->dwc->xhci);
+ platform_device_del(dwc->xhci);
return ret;
}
@@ -140,7 +152,7 @@
} else {
dev_dbg(otg->phy->dev, "%s: turn off host\n", __func__);
- platform_device_del(dotg->dwc->xhci);
+ platform_device_del(dwc->xhci);
ret = regulator_disable(dotg->vbus_otg);
if (ret) {
@@ -150,7 +162,7 @@
dwc3_otg_notify_host_mode(otg, on);
/* re-init core and OTG register as XHCI reset clears it */
- dwc3_post_host_reset_core_init(dotg->dwc);
+ dwc3_post_host_reset_core_init(dwc);
dwc3_otg_reset(dotg);
}
@@ -381,11 +393,14 @@
struct dwc3_otg *dotg = container_of(phy->otg, struct dwc3_otg, otg);
- if (!dotg->psy) {
- dev_err(phy->dev, "no usb power supply registered\n");
+ if (!dotg->psy || !dotg->charger) {
+ dev_err(phy->dev, "no usb power supply/charger registered\n");
return 0;
}
+ if (dotg->charger->charging_disabled)
+ return 0;
+
if (dotg->charger->chg_type == DWC3_SDP_CHARGER)
power_supply_type = POWER_SUPPLY_TYPE_USB;
else if (dotg->charger->chg_type == DWC3_CDP_CHARGER)
@@ -769,13 +784,6 @@
return -ENOMEM;
}
- dotg->vbus_otg = devm_regulator_get(dwc->dev->parent, "vbus_dwc3");
- if (IS_ERR(dotg->vbus_otg)) {
- dev_err(dwc->dev, "Unable to get vbus_dwc3 regulator\n");
- ret = PTR_ERR(dotg->vbus_otg);
- goto err1;
- }
-
/* DWC3 has separate IRQ line for OTG events (ID/BSV etc.) */
dotg->irq = platform_get_irq_byname(to_platform_device(dwc->dev),
"otg_irq");
diff --git a/drivers/usb/dwc3/dwc3_otg.h b/drivers/usb/dwc3/dwc3_otg.h
index 4384888..c93ce5f 100644
--- a/drivers/usb/dwc3/dwc3_otg.h
+++ b/drivers/usb/dwc3/dwc3_otg.h
@@ -70,6 +70,7 @@
struct dwc3_charger {
enum dwc3_chg_type chg_type;
unsigned max_power;
+ bool charging_disabled;
/* start/stop charger detection, provided by external charger module */
void (*start_detection)(struct dwc3_charger *charger, bool start);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 9c1ebf8..3679191 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1527,6 +1527,13 @@
} else {
ret = dwc3_gadget_run_stop(dwc, 0);
}
+ } else if (dwc->gadget_driver && !dwc->softconnect &&
+ !dwc->vbus_active) {
+ if (dwc->gadget_driver->disconnect) {
+ spin_unlock_irqrestore(&dwc->lock, flags);
+ dwc->gadget_driver->disconnect(&dwc->gadget);
+ return 0;
+ }
}
spin_unlock_irqrestore(&dwc->lock, flags);
@@ -2551,7 +2558,7 @@
dev_set_name(&dwc->gadget.dev, "gadget");
dwc->gadget.ops = &dwc3_gadget_ops;
- dwc->gadget.max_speed = USB_SPEED_HIGH;
+ dwc->gadget.max_speed = USB_SPEED_SUPER;
dwc->gadget.speed = USB_SPEED_UNKNOWN;
dwc->gadget.dev.parent = dwc->dev;
dwc->gadget.sg_supported = true;
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index 52c19cf..b773d1a 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -24,6 +24,7 @@
#include <linux/utsname.h>
#include <linux/platform_device.h>
#include <linux/pm_qos.h>
+#include <linux/of.h>
#include <linux/usb/ch9.h>
#include <linux/usb/composite.h>
@@ -107,9 +108,6 @@
char *dev_name;
struct device_attribute **attributes;
- /* for android_conf.enabled_functions */
- struct list_head enabled_list;
-
struct android_dev *android_dev;
/* Optional: initialization during gadget bind */
@@ -134,6 +132,14 @@
const struct usb_ctrlrequest *);
};
+struct android_usb_function_holder {
+
+ struct android_usb_function *f;
+
+ /* for android_conf.enabled_functions */
+ struct list_head enabled_list;
+};
+
struct android_dev {
const char *name;
struct android_usb_function **functions;
@@ -1713,15 +1719,15 @@
android_bind_enabled_functions(struct android_dev *dev,
struct usb_configuration *c)
{
- struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
struct android_configuration *conf =
container_of(c, struct android_configuration, usb_config);
int ret;
- list_for_each_entry(f, &conf->enabled_functions, enabled_list) {
- ret = f->bind_config(f, c);
+ list_for_each_entry(f_holder, &conf->enabled_functions, enabled_list) {
+ ret = f_holder->f->bind_config(f_holder->f, c);
if (ret) {
- pr_err("%s: %s failed", __func__, f->name);
+ pr_err("%s: %s failed", __func__, f_holder->f->name);
return ret;
}
}
@@ -1732,13 +1738,13 @@
android_unbind_enabled_functions(struct android_dev *dev,
struct usb_configuration *c)
{
- struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
struct android_configuration *conf =
container_of(c, struct android_configuration, usb_config);
- list_for_each_entry(f, &conf->enabled_functions, enabled_list) {
- if (f->unbind_config)
- f->unbind_config(f, c);
+ list_for_each_entry(f_holder, &conf->enabled_functions, enabled_list) {
+ if (f_holder->f->unbind_config)
+ f_holder->f->unbind_config(f_holder->f, c);
}
}
@@ -1748,16 +1754,24 @@
{
struct android_usb_function **functions = dev->functions;
struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
while ((f = *functions++)) {
if (!strcmp(name, f->name)) {
- if (f->android_dev)
- pr_err("%s already enabled in other " \
- "configuration or device\n",
+ if (f->android_dev && f->android_dev != dev)
+ pr_err("%s is enabled in other device\n",
f->name);
else {
- list_add_tail(&f->enabled_list,
- &conf->enabled_functions);
+ f_holder = kzalloc(sizeof(*f_holder),
+ GFP_KERNEL);
+ if (!f_holder) {
+ pr_err("Failed to alloc f_holder\n");
+ return -ENOMEM;
+ }
+
f->android_dev = dev;
+ f_holder->f = f;
+ list_add_tail(&f_holder->enabled_list,
+ &conf->enabled_functions);
return 0;
}
}
@@ -1817,7 +1831,7 @@
{
struct android_dev *dev = dev_get_drvdata(pdev);
struct android_configuration *conf;
- struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
char *buff = buf;
mutex_lock(&dev->mutex);
@@ -1825,8 +1839,10 @@
list_for_each_entry(conf, &dev->configs, list_item) {
if (buff != buf)
*(buff-1) = ':';
- list_for_each_entry(f, &conf->enabled_functions, enabled_list)
- buff += snprintf(buff, PAGE_SIZE, "%s,", f->name);
+ list_for_each_entry(f_holder, &conf->enabled_functions,
+ enabled_list)
+ buff += snprintf(buff, PAGE_SIZE, "%s,",
+ f_holder->f->name);
}
mutex_unlock(&dev->mutex);
@@ -1841,10 +1857,10 @@
const char *buff, size_t size)
{
struct android_dev *dev = dev_get_drvdata(pdev);
- struct android_usb_function *f;
struct list_head *curr_conf = &dev->configs;
struct android_configuration *conf;
char *conf_str;
+ struct android_usb_function_holder *f_holder;
char *name;
char buf[256], *b;
int err;
@@ -1858,8 +1874,15 @@
/* Clear previous enabled list */
list_for_each_entry(conf, &dev->configs, list_item) {
- list_for_each_entry(f, &conf->enabled_functions, enabled_list)
- f->android_dev = NULL;
+ while (conf->enabled_functions.next !=
+ &conf->enabled_functions) {
+ f_holder = list_entry(conf->enabled_functions.next,
+ typeof(*f_holder),
+ enabled_list);
+ f_holder->f->android_dev = NULL;
+ list_del(&f_holder->enabled_list);
+ kfree(f_holder);
+ }
INIT_LIST_HEAD(&conf->enabled_functions);
}
@@ -1916,7 +1939,7 @@
{
struct android_dev *dev = dev_get_drvdata(pdev);
struct usb_composite_dev *cdev = dev->cdev;
- struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
struct android_configuration *conf;
int enabled = 0;
@@ -1938,20 +1961,20 @@
cdev->desc.bDeviceSubClass = device_desc.bDeviceSubClass;
cdev->desc.bDeviceProtocol = device_desc.bDeviceProtocol;
list_for_each_entry(conf, &dev->configs, list_item)
- list_for_each_entry(f, &conf->enabled_functions,
+ list_for_each_entry(f_holder, &conf->enabled_functions,
enabled_list) {
- if (f->enable)
- f->enable(f);
+ if (f_holder->f->enable)
+ f_holder->f->enable(f_holder->f);
}
android_enable(dev);
dev->enabled = true;
} else if (!enabled && dev->enabled) {
android_disable(dev);
list_for_each_entry(conf, &dev->configs, list_item)
- list_for_each_entry(f, &conf->enabled_functions,
+ list_for_each_entry(f_holder, &conf->enabled_functions,
enabled_list) {
- if (f->disable)
- f->disable(f);
+ if (f_holder->f->disable)
+ f_holder->f->disable(f_holder->f);
}
dev->enabled = false;
} else {
@@ -2199,6 +2222,7 @@
struct android_dev *dev = cdev_to_android_dev(cdev);
struct usb_request *req = cdev->req;
struct android_usb_function *f;
+ struct android_usb_function_holder *f_holder;
struct android_configuration *conf;
int value = -EOPNOTSUPP;
unsigned long flags;
@@ -2209,14 +2233,16 @@
gadget->ep0->driver_data = cdev;
list_for_each_entry(conf, &dev->configs, list_item)
- list_for_each_entry(f,
- &conf->enabled_functions,
- enabled_list)
- if (f->ctrlrequest) {
- value = f->ctrlrequest(f, cdev, c);
- if (value >= 0)
- break;
- }
+ list_for_each_entry(f_holder,
+ &conf->enabled_functions,
+ enabled_list) {
+ f = f_holder->f;
+ if (f->ctrlrequest) {
+ value = f->ctrlrequest(f, cdev, c);
+ if (value >= 0)
+ break;
+ }
+ }
/* Special case the accessory function.
* It needs to handle control requests before it is enabled.
@@ -2384,11 +2410,26 @@
static int __devinit android_probe(struct platform_device *pdev)
{
- struct android_usb_platform_data *pdata = pdev->dev.platform_data;
+ struct android_usb_platform_data *pdata;
struct android_dev *android_dev;
struct resource *res;
int ret = 0;
+ if (pdev->dev.of_node) {
+ dev_dbg(&pdev->dev, "device tree enabled\n");
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ pr_err("unable to allocate platform data\n");
+ return -ENOMEM;
+ }
+
+ of_property_read_u32(pdev->dev.of_node,
+ "qcom,android-usb-swfi-latency",
+ &pdata->swfi_latency);
+ } else {
+ pdata = pdev->dev.platform_data;
+ }
+
if (!android_class) {
android_class = class_create(THIS_MODULE, "android_usb");
if (IS_ERR(android_class))
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 576ea1e..4bc0da2 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -371,7 +371,8 @@
c->bConfigurationValue = config->bConfigurationValue;
c->iConfiguration = config->iConfiguration;
c->bmAttributes = USB_CONFIG_ATT_ONE | config->bmAttributes;
- c->bMaxPower = config->bMaxPower ? : (CONFIG_USB_GADGET_VBUS_DRAW / 2);
+ c->bMaxPower = config->bMaxPower ? :
+ (CONFIG_USB_GADGET_VBUS_DRAW / config->cdev->vbus_draw_units);
/* There may be e.g. OTG descriptors */
if (config->descriptors) {
@@ -688,7 +689,8 @@
}
/* when we return, be sure our power usage is valid */
- power = c->bMaxPower ? (2 * c->bMaxPower) : CONFIG_USB_GADGET_VBUS_DRAW;
+ power = c->bMaxPower ? (cdev->vbus_draw_units * c->bMaxPower) :
+ CONFIG_USB_GADGET_VBUS_DRAW;
done:
usb_gadget_vbus_draw(gadget, power);
@@ -1113,12 +1115,16 @@
count_configs(cdev, USB_DT_DEVICE);
cdev->desc.bMaxPacketSize0 =
cdev->gadget->ep0->maxpacket;
+ cdev->vbus_draw_units = 2;
if (gadget_is_superspeed(gadget)) {
if (gadget->speed >= USB_SPEED_SUPER) {
cdev->desc.bcdUSB = cpu_to_le16(0x0300);
cdev->desc.bMaxPacketSize0 = 9;
+ cdev->vbus_draw_units = 8;
+ DBG(cdev, "Config SS device in SS\n");
} else {
cdev->desc.bcdUSB = cpu_to_le16(0x0210);
+ DBG(cdev, "Config SS device in HS\n");
}
}
@@ -1576,7 +1582,8 @@
maxpower = cdev->config->bMaxPower;
usb_gadget_vbus_draw(gadget, maxpower ?
- (2 * maxpower) : CONFIG_USB_GADGET_VBUS_DRAW);
+ (cdev->vbus_draw_units * maxpower) :
+ CONFIG_USB_GADGET_VBUS_DRAW);
}
cdev->suspended = 0;
diff --git a/drivers/usb/gadget/f_accessory.c b/drivers/usb/gadget/f_accessory.c
index 42a6c43..5659c79 100644
--- a/drivers/usb/gadget/f_accessory.c
+++ b/drivers/usb/gadget/f_accessory.c
@@ -132,6 +132,41 @@
.bInterfaceProtocol = 0,
};
+static struct usb_endpoint_descriptor acc_superspeed_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor acc_superspeed_in_comp_desc = {
+ .bLength = sizeof acc_superspeed_in_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_endpoint_descriptor acc_superspeed_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor acc_superspeed_out_comp_desc = {
+ .bLength = sizeof acc_superspeed_out_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+
static struct usb_endpoint_descriptor acc_highspeed_in_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
@@ -176,6 +211,15 @@
NULL,
};
+static struct usb_descriptor_header *ss_acc_descs[] = {
+ (struct usb_descriptor_header *) &acc_interface_desc,
+ (struct usb_descriptor_header *) &acc_superspeed_in_desc,
+ (struct usb_descriptor_header *) &acc_superspeed_in_comp_desc,
+ (struct usb_descriptor_header *) &acc_superspeed_out_desc,
+ (struct usb_descriptor_header *) &acc_superspeed_out_comp_desc,
+ NULL,
+};
+
static struct usb_string acc_string_defs[] = {
[INTERFACE_STRING_INDEX].s = "Android Accessory Interface",
{ }, /* end of list */
@@ -907,6 +951,14 @@
acc_fullspeed_out_desc.bEndpointAddress;
}
+ /* support super speed hardware */
+ if (gadget_is_superspeed(c->cdev->gadget)) {
+ acc_superspeed_in_desc.bEndpointAddress =
+ acc_fullspeed_in_desc.bEndpointAddress;
+ acc_superspeed_out_desc.bEndpointAddress =
+ acc_fullspeed_out_desc.bEndpointAddress;
+ }
+
DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n",
gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full",
f->name, dev->ep_in->name, dev->ep_out->name);
@@ -1135,6 +1187,8 @@
dev->function.strings = acc_strings,
dev->function.descriptors = fs_acc_descs;
dev->function.hs_descriptors = hs_acc_descs;
+ if (gadget_is_superspeed(c->cdev->gadget))
+ dev->function.ss_descriptors = ss_acc_descs;
dev->function.bind = acc_function_bind;
dev->function.unbind = acc_function_unbind;
dev->function.set_alt = acc_function_set_alt;
diff --git a/drivers/usb/gadget/f_adb.c b/drivers/usb/gadget/f_adb.c
index 14e5b60..68c99a3 100644
--- a/drivers/usb/gadget/f_adb.c
+++ b/drivers/usb/gadget/f_adb.c
@@ -69,6 +69,40 @@
.bInterfaceProtocol = 1,
};
+static struct usb_endpoint_descriptor adb_superspeed_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor adb_superspeed_in_comp_desc = {
+ .bLength = sizeof adb_superspeed_in_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_endpoint_descriptor adb_superspeed_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor adb_superspeed_out_comp_desc = {
+ .bLength = sizeof adb_superspeed_out_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
static struct usb_endpoint_descriptor adb_highspeed_in_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
@@ -113,6 +147,15 @@
NULL,
};
+static struct usb_descriptor_header *ss_adb_descs[] = {
+ (struct usb_descriptor_header *) &adb_interface_desc,
+ (struct usb_descriptor_header *) &adb_superspeed_in_desc,
+ (struct usb_descriptor_header *) &adb_superspeed_in_comp_desc,
+ (struct usb_descriptor_header *) &adb_superspeed_out_desc,
+ (struct usb_descriptor_header *) &adb_superspeed_out_comp_desc,
+ NULL,
+};
+
static void adb_ready_callback(void);
static void adb_closed_callback(void);
@@ -503,6 +546,13 @@
adb_highspeed_out_desc.bEndpointAddress =
adb_fullspeed_out_desc.bEndpointAddress;
}
+ /* support super speed hardware */
+ if (gadget_is_superspeed(c->cdev->gadget)) {
+ adb_superspeed_in_desc.bEndpointAddress =
+ adb_fullspeed_in_desc.bEndpointAddress;
+ adb_superspeed_out_desc.bEndpointAddress =
+ adb_fullspeed_out_desc.bEndpointAddress;
+ }
DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n",
gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full",
@@ -605,6 +655,8 @@
dev->function.name = "adb";
dev->function.descriptors = fs_adb_descs;
dev->function.hs_descriptors = hs_adb_descs;
+ if (gadget_is_superspeed(c->cdev->gadget))
+ dev->function.ss_descriptors = ss_adb_descs;
dev->function.bind = adb_function_bind;
dev->function.unbind = adb_function_unbind;
dev->function.set_alt = adb_function_set_alt;
diff --git a/drivers/usb/gadget/f_diag.c b/drivers/usb/gadget/f_diag.c
index 87597d5..8f68234 100644
--- a/drivers/usb/gadget/f_diag.c
+++ b/drivers/usb/gadget/f_diag.c
@@ -73,6 +73,40 @@
.bInterval = 0,
};
+static struct usb_endpoint_descriptor ss_bulk_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor ss_bulk_in_comp_desc = {
+ .bLength = sizeof ss_bulk_in_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_endpoint_descriptor ss_bulk_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor ss_bulk_out_comp_desc = {
+ .bLength = sizeof ss_bulk_out_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
static struct usb_descriptor_header *fs_diag_desc[] = {
(struct usb_descriptor_header *) &intf_desc,
(struct usb_descriptor_header *) &fs_bulk_in_desc,
@@ -86,6 +120,15 @@
NULL,
};
+static struct usb_descriptor_header *ss_diag_desc[] = {
+ (struct usb_descriptor_header *) &intf_desc,
+ (struct usb_descriptor_header *) &ss_bulk_in_desc,
+ (struct usb_descriptor_header *) &ss_bulk_in_comp_desc,
+ (struct usb_descriptor_header *) &ss_bulk_out_desc,
+ (struct usb_descriptor_header *) &ss_bulk_out_comp_desc,
+ NULL,
+};
+
/**
* struct diag_context - USB diag function driver private structure
* @function: function structure for USB interface
@@ -551,6 +594,8 @@
{
struct diag_context *ctxt = func_to_diag(f);
+ if (gadget_is_superspeed(c->cdev->gadget))
+ usb_free_descriptors(f->ss_descriptors);
if (gadget_is_dualspeed(c->cdev->gadget))
usb_free_descriptors(f->hs_descriptors);
@@ -580,6 +625,7 @@
ctxt->out = ep;
ep->driver_data = ctxt;
+ status = -ENOMEM;
/* copy descriptors, and track endpoint copies */
f->descriptors = usb_copy_descriptors(fs_diag_desc);
if (!f->descriptors)
@@ -593,9 +639,29 @@
/* copy descriptors, and track endpoint copies */
f->hs_descriptors = usb_copy_descriptors(hs_diag_desc);
+ if (!f->hs_descriptors)
+ goto fail;
+ }
+
+ if (gadget_is_superspeed(c->cdev->gadget)) {
+ ss_bulk_in_desc.bEndpointAddress =
+ fs_bulk_in_desc.bEndpointAddress;
+ ss_bulk_out_desc.bEndpointAddress =
+ fs_bulk_out_desc.bEndpointAddress;
+
+ /* copy descriptors, and track endpoint copies */
+ f->ss_descriptors = usb_copy_descriptors(ss_diag_desc);
+ if (!f->ss_descriptors)
+ goto fail;
}
return 0;
fail:
+ if (f->ss_descriptors)
+ usb_free_descriptors(f->ss_descriptors);
+ if (f->hs_descriptors)
+ usb_free_descriptors(f->hs_descriptors);
+ if (f->descriptors)
+ usb_free_descriptors(f->descriptors);
if (ctxt->out)
ctxt->out->driver_data = NULL;
if (ctxt->in)
diff --git a/drivers/usb/gadget/f_mbim.c b/drivers/usb/gadget/f_mbim.c
index 729910d..85240ef 100644
--- a/drivers/usb/gadget/f_mbim.c
+++ b/drivers/usb/gadget/f_mbim.c
@@ -546,19 +546,19 @@
spin_lock_irqsave(&dev->lock, flags);
if (!atomic_read(&dev->online)) {
- pr_info("dev:%p is not online\n", dev);
+ pr_err("dev:%p is not online\n", dev);
spin_unlock_irqrestore(&dev->lock, flags);
return;
}
if (!req) {
- pr_info("dev:%p req is NULL\n", dev);
+ pr_err("dev:%p req is NULL\n", dev);
spin_unlock_irqrestore(&dev->lock, flags);
return;
}
if (!req->buf) {
- pr_info("dev:%p req->buf is NULL\n", dev);
+ pr_err("dev:%p req->buf is NULL\n", dev);
spin_unlock_irqrestore(&dev->lock, flags);
return;
}
@@ -601,10 +601,10 @@
return -ENODEV;
}
- pr_info("dev:%p port_num#%d\n", dev, dev->port_num);
+ pr_debug("dev:%p port_num#%d\n", dev, dev->port_num);
if (!atomic_read(&dev->online)) {
- pr_info("dev:%p is not connected\n", dev);
+ pr_err("dev:%p is not connected\n", dev);
mbim_free_ctrl_pkt(cpkt);
return 0;
}
@@ -739,7 +739,7 @@
__le32 *data;
int status;
- pr_info("notify_state: %d", mbim->not_port.notify_state);
+ pr_debug("notify_state: %d", mbim->not_port.notify_state);
if (!req)
return;
@@ -827,7 +827,7 @@
* notification is sent, then it will reset to send the SPEED
* notificaion again (and again, and again), but it's not a problem
*/
- pr_info("dev:%p\n", mbim);
+ pr_debug("dev:%p\n", mbim);
mbim->not_port.notify_state = NCM_NOTIFY_SPEED;
mbim_do_notify(mbim);
@@ -868,7 +868,7 @@
mbim_do_notify(mbim);
spin_unlock(&mbim->lock);
- pr_info("dev:%p Exit\n", mbim);
+ pr_debug("dev:%p Exit\n", mbim);
}
static void mbim_ep0out_complete(struct usb_ep *ep, struct usb_request *req)
@@ -879,7 +879,7 @@
struct f_mbim *mbim = func_to_mbim(f);
struct mbim_ntb_input_size *ntb = NULL;
- pr_info("dev:%p\n", mbim);
+ pr_debug("dev:%p\n", mbim);
req->context = NULL;
if (req->status || req->actual != req->length) {
@@ -909,7 +909,7 @@
goto invalid;
}
- pr_info("Set NTB INPUT SIZE %d\n", in_size);
+ pr_debug("Set NTB INPUT SIZE %d\n", in_size);
mbim->ntb_input_size = in_size;
return;
@@ -939,29 +939,30 @@
return;
}
- pr_info("dev:%p port#%d\n", dev, dev->port_num);
+ pr_debug("dev:%p port#%d\n", dev, dev->port_num);
+
+ cpkt = mbim_alloc_ctrl_pkt(len, GFP_ATOMIC);
+ if (!cpkt) {
+ pr_err("Unable to allocate ctrl pkt\n");
+ return;
+ }
+
+ pr_debug("Add to cpkt_req_q packet with len = %d\n", len);
+ memcpy(cpkt->buf, req->buf, len);
spin_lock(&dev->lock);
if (!dev->is_open) {
pr_err("mbim file handler %p is not open", dev);
spin_unlock(&dev->lock);
+ mbim_free_ctrl_pkt(cpkt);
return;
}
- cpkt = mbim_alloc_ctrl_pkt(len, GFP_ATOMIC);
- if (!cpkt) {
- pr_err("Unable to allocate ctrl pkt\n");
- spin_unlock(&dev->lock);
- return;
- }
-
- pr_info("Add to cpkt_req_q packet with len = %d\n", len);
- memcpy(cpkt->buf, req->buf, len);
list_add_tail(&cpkt->list, &dev->cpkt_req_q);
spin_unlock(&dev->lock);
/* wakeup read thread */
- pr_info("Wake up read queue");
+ pr_debug("Wake up read queue");
wake_up(&dev->read_wq);
return;
@@ -993,7 +994,7 @@
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_RESET_FUNCTION:
- pr_info("USB_CDC_RESET_FUNCTION");
+ pr_debug("USB_CDC_RESET_FUNCTION");
value = 0;
req->complete = fmbim_reset_cmd_complete;
req->context = mbim;
@@ -1002,10 +1003,10 @@
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_SEND_ENCAPSULATED_COMMAND:
- pr_info("USB_CDC_SEND_ENCAPSULATED_COMMAND");
+ pr_debug("USB_CDC_SEND_ENCAPSULATED_COMMAND");
if (w_length > req->length) {
- pr_err("w_length > req->length: %d > %d",
+ pr_debug("w_length > req->length: %d > %d",
w_length, req->length);
}
value = w_length;
@@ -1016,14 +1017,14 @@
case ((USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_GET_ENCAPSULATED_RESPONSE:
- pr_info("USB_CDC_GET_ENCAPSULATED_RESPONSE");
+ pr_debug("USB_CDC_GET_ENCAPSULATED_RESPONSE");
if (w_value) {
pr_err("w_length > 0: %d", w_length);
break;
}
- pr_info("req%02x.%02x v%04x i%04x l%d\n",
+ pr_debug("req%02x.%02x v%04x i%04x l%d\n",
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
@@ -1043,7 +1044,7 @@
memcpy(req->buf, cpkt->buf, value);
mbim_free_ctrl_pkt(cpkt);
- pr_info("copied encapsulated_response %d bytes",
+ pr_debug("copied encapsulated_response %d bytes",
value);
break;
@@ -1051,7 +1052,7 @@
case ((USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_GET_NTB_PARAMETERS:
- pr_info("USB_CDC_GET_NTB_PARAMETERS");
+ pr_debug("USB_CDC_GET_NTB_PARAMETERS");
if (w_length == 0 || w_value != 0 || w_index != mbim->ctrl_id)
break;
@@ -1064,21 +1065,21 @@
case ((USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_GET_NTB_INPUT_SIZE:
- pr_info("USB_CDC_GET_NTB_INPUT_SIZE");
+ pr_debug("USB_CDC_GET_NTB_INPUT_SIZE");
if (w_length < 4 || w_value != 0 || w_index != mbim->ctrl_id)
break;
put_unaligned_le32(mbim->ntb_input_size, req->buf);
value = 4;
- pr_info("Reply to host INPUT SIZE %d\n",
+ pr_debug("Reply to host INPUT SIZE %d\n",
mbim->ntb_input_size);
break;
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_SET_NTB_INPUT_SIZE:
- pr_info("USB_CDC_SET_NTB_INPUT_SIZE");
+ pr_debug("USB_CDC_SET_NTB_INPUT_SIZE");
if (w_length != 4 && w_length != 8) {
pr_err("wrong NTB length %d", w_length);
@@ -1100,7 +1101,7 @@
{
uint16_t format;
- pr_info("USB_CDC_GET_NTB_FORMAT");
+ pr_debug("USB_CDC_GET_NTB_FORMAT");
if (w_length < 2 || w_value != 0 || w_index != mbim->ctrl_id)
break;
@@ -1108,25 +1109,25 @@
format = (mbim->parser_opts == &ndp16_opts) ? 0x0000 : 0x0001;
put_unaligned_le16(format, req->buf);
value = 2;
- pr_info("NTB FORMAT: sending %d\n", format);
+ pr_debug("NTB FORMAT: sending %d\n", format);
break;
}
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_SET_NTB_FORMAT:
{
- pr_info("USB_CDC_SET_NTB_FORMAT");
+ pr_debug("USB_CDC_SET_NTB_FORMAT");
if (w_length != 0 || w_index != mbim->ctrl_id)
break;
switch (w_value) {
case 0x0000:
mbim->parser_opts = &ndp16_opts;
- pr_info("NCM16 selected\n");
+ pr_debug("NCM16 selected\n");
break;
case 0x0001:
mbim->parser_opts = &ndp32_opts;
- pr_info("NCM32 selected\n");
+ pr_debug("NCM32 selected\n");
break;
default:
break;
@@ -1147,7 +1148,7 @@
/* respond with data transfer or status phase? */
if (value >= 0) {
- pr_info("control request: %02x.%02x v%04x i%04x l%d\n",
+ pr_debug("control request: %02x.%02x v%04x i%04x l%d\n",
ctrl->bRequestType, ctrl->bRequest,
w_value, w_index, w_length);
req->zero = (value < w_length);
@@ -1820,7 +1821,7 @@
struct f_mbim *mbim = fp->private_data;
int ret = 0;
- pr_info("Received command %d", cmd);
+ pr_debug("Received command %d", cmd);
if (mbim_lock(&mbim->ioctl_excl))
return -EBUSY;
diff --git a/drivers/usb/gadget/f_mtp.c b/drivers/usb/gadget/f_mtp.c
index ccbc330..82ffbba 100644
--- a/drivers/usb/gadget/f_mtp.c
+++ b/drivers/usb/gadget/f_mtp.c
@@ -129,6 +129,40 @@
.bInterfaceProtocol = 1,
};
+static struct usb_endpoint_descriptor mtp_superspeed_in_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor mtp_superspeed_in_comp_desc = {
+ .bLength = sizeof mtp_superspeed_in_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_endpoint_descriptor mtp_superspeed_out_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor mtp_superspeed_out_comp_desc = {
+ .bLength = sizeof mtp_superspeed_out_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
static struct usb_endpoint_descriptor mtp_highspeed_in_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
@@ -168,6 +202,16 @@
.bInterval = 6,
};
+static struct usb_ss_ep_comp_descriptor mtp_superspeed_intr_comp_desc = {
+ .bLength = sizeof mtp_superspeed_intr_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 3 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+ .wBytesPerInterval = cpu_to_le16(INTR_BUFFER_SIZE),
+};
+
static struct usb_descriptor_header *fs_mtp_descs[] = {
(struct usb_descriptor_header *) &mtp_interface_desc,
(struct usb_descriptor_header *) &mtp_fullspeed_in_desc,
@@ -184,6 +228,17 @@
NULL,
};
+static struct usb_descriptor_header *ss_mtp_descs[] = {
+ (struct usb_descriptor_header *) &mtp_interface_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_in_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_in_comp_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_out_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_out_comp_desc,
+ (struct usb_descriptor_header *) &mtp_intr_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_intr_comp_desc,
+ NULL,
+};
+
static struct usb_descriptor_header *fs_ptp_descs[] = {
(struct usb_descriptor_header *) &ptp_interface_desc,
(struct usb_descriptor_header *) &mtp_fullspeed_in_desc,
@@ -200,6 +255,17 @@
NULL,
};
+static struct usb_descriptor_header *ss_ptp_descs[] = {
+ (struct usb_descriptor_header *) &ptp_interface_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_in_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_in_comp_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_out_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_out_comp_desc,
+ (struct usb_descriptor_header *) &mtp_intr_desc,
+ (struct usb_descriptor_header *) &mtp_superspeed_intr_comp_desc,
+ NULL,
+};
+
static struct usb_string mtp_string_defs[] = {
/* Naming interface "MTP" so libmtp will recognize us */
[INTERFACE_STRING_INDEX].s = "MTP",
@@ -1126,6 +1192,14 @@
mtp_fullspeed_out_desc.bEndpointAddress;
}
+ /* support super speed hardware */
+ if (gadget_is_superspeed(c->cdev->gadget)) {
+ mtp_superspeed_in_desc.bEndpointAddress =
+ mtp_fullspeed_in_desc.bEndpointAddress;
+ mtp_superspeed_out_desc.bEndpointAddress =
+ mtp_fullspeed_out_desc.bEndpointAddress;
+ }
+
DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n",
gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full",
f->name, dev->ep_in->name, dev->ep_out->name);
@@ -1239,9 +1313,13 @@
if (ptp_config) {
dev->function.descriptors = fs_ptp_descs;
dev->function.hs_descriptors = hs_ptp_descs;
+ if (gadget_is_superspeed(c->cdev->gadget))
+ dev->function.ss_descriptors = ss_ptp_descs;
} else {
dev->function.descriptors = fs_mtp_descs;
dev->function.hs_descriptors = hs_mtp_descs;
+ if (gadget_is_superspeed(c->cdev->gadget))
+ dev->function.ss_descriptors = ss_mtp_descs;
}
dev->function.bind = mtp_function_bind;
dev->function.unbind = mtp_function_unbind;
diff --git a/drivers/usb/gadget/f_rmnet.c b/drivers/usb/gadget/f_rmnet.c
index aa9daf3..4357e0d 100644
--- a/drivers/usb/gadget/f_rmnet.c
+++ b/drivers/usb/gadget/f_rmnet.c
@@ -147,6 +147,71 @@
NULL,
};
+/* Super speed support */
+static struct usb_endpoint_descriptor rmnet_ss_notify_desc = {
+ .bLength = sizeof rmnet_ss_notify_desc,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize = __constant_cpu_to_le16(RMNET_MAX_NOTIFY_SIZE),
+ .bInterval = RMNET_NOTIFY_INTERVAL + 4,
+};
+
+static struct usb_ss_ep_comp_descriptor rmnet_ss_notify_comp_desc = {
+ .bLength = sizeof rmnet_ss_notify_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 3 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+ .wBytesPerInterval = cpu_to_le16(RMNET_MAX_NOTIFY_SIZE),
+};
+
+static struct usb_endpoint_descriptor rmnet_ss_in_desc = {
+ .bLength = sizeof rmnet_ss_in_desc,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor rmnet_ss_in_comp_desc = {
+ .bLength = sizeof rmnet_ss_in_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_endpoint_descriptor rmnet_ss_out_desc = {
+ .bLength = sizeof rmnet_ss_out_desc,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = __constant_cpu_to_le16(1024),
+};
+
+static struct usb_ss_ep_comp_descriptor rmnet_ss_out_comp_desc = {
+ .bLength = sizeof rmnet_ss_out_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+};
+
+static struct usb_descriptor_header *rmnet_ss_function[] = {
+ (struct usb_descriptor_header *) &rmnet_interface_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_notify_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_notify_comp_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_in_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_in_comp_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_out_desc,
+ (struct usb_descriptor_header *) &rmnet_ss_out_comp_desc,
+ NULL,
+};
+
/* String descriptors */
static struct usb_string rmnet_string_defs[] = {
@@ -460,6 +525,8 @@
pr_debug("%s: portno:%d\n", __func__, dev->port_num);
+ if (gadget_is_superspeed(c->cdev->gadget))
+ usb_free_descriptors(f->ss_descriptors);
if (gadget_is_dualspeed(c->cdev->gadget))
usb_free_descriptors(f->hs_descriptors);
usb_free_descriptors(f->descriptors);
@@ -964,6 +1031,7 @@
dev->notify_req->complete = frmnet_notify_complete;
dev->notify_req->context = dev;
+ ret = -ENOMEM;
f->descriptors = usb_copy_descriptors(rmnet_fs_function);
if (!f->descriptors)
@@ -984,6 +1052,21 @@
goto fail;
}
+ if (gadget_is_superspeed(cdev->gadget)) {
+ rmnet_ss_in_desc.bEndpointAddress =
+ rmnet_fs_in_desc.bEndpointAddress;
+ rmnet_ss_out_desc.bEndpointAddress =
+ rmnet_fs_out_desc.bEndpointAddress;
+ rmnet_ss_notify_desc.bEndpointAddress =
+ rmnet_fs_notify_desc.bEndpointAddress;
+
+ /* copy descriptors, and track endpoint copies */
+ f->ss_descriptors = usb_copy_descriptors(rmnet_ss_function);
+
+ if (!f->ss_descriptors)
+ goto fail;
+ }
+
pr_info("%s: RmNet(%d) %s Speed, IN:%s OUT:%s\n",
__func__, dev->port_num,
gadget_is_dualspeed(cdev->gadget) ? "dual" : "full",
@@ -992,8 +1075,14 @@
return 0;
fail:
+ if (f->ss_descriptors)
+ usb_free_descriptors(f->ss_descriptors);
+ if (f->hs_descriptors)
+ usb_free_descriptors(f->hs_descriptors);
if (f->descriptors)
usb_free_descriptors(f->descriptors);
+ if (dev->notify_req)
+ frmnet_free_req(dev->notify, dev->notify_req);
ep_notify_alloc_fail:
dev->notify->driver_data = NULL;
dev->notify = NULL;
diff --git a/drivers/usb/gadget/f_rmnet_smd.c b/drivers/usb/gadget/f_rmnet_smd.c
index 5e2c6ed..e8c1f2a 100644
--- a/drivers/usb/gadget/f_rmnet_smd.c
+++ b/drivers/usb/gadget/f_rmnet_smd.c
@@ -874,9 +874,6 @@
struct rmnet_smd_dev *dev = container_of(f, struct rmnet_smd_dev,
function);
- if (!atomic_read(&dev->online))
- return;
-
atomic_set(&dev->online, 0);
usb_ep_fifo_flush(dev->epnotify);
diff --git a/drivers/usb/gadget/f_serial.c b/drivers/usb/gadget/f_serial.c
index 649fe14..43347b3 100644
--- a/drivers/usb/gadget/f_serial.c
+++ b/drivers/usb/gadget/f_serial.c
@@ -244,8 +244,37 @@
.bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
};
+#ifdef CONFIG_MODEM_SUPPORT
+static struct usb_endpoint_descriptor gser_ss_notify_desc = {
+ .bLength = sizeof gser_ss_notify_desc,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize = __constant_cpu_to_le16(GS_NOTIFY_MAXPACKET),
+ .bInterval = GS_LOG2_NOTIFY_INTERVAL+4,
+};
+
+static struct usb_ss_ep_comp_descriptor gser_ss_notify_comp_desc = {
+ .bLength = sizeof gser_ss_notify_comp_desc,
+ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP,
+
+ /* the following 2 values can be tweaked if necessary */
+ /* .bMaxBurst = 0, */
+ /* .bmAttributes = 0, */
+ .wBytesPerInterval = cpu_to_le16(GS_NOTIFY_MAXPACKET),
+};
+#endif
+
static struct usb_descriptor_header *gser_ss_function[] = {
(struct usb_descriptor_header *) &gser_interface_desc,
+#ifdef CONFIG_MODEM_SUPPORT
+ (struct usb_descriptor_header *) &gser_header_desc,
+ (struct usb_descriptor_header *) &gser_call_mgmt_descriptor,
+ (struct usb_descriptor_header *) &gser_descriptor,
+ (struct usb_descriptor_header *) &gser_union_desc,
+ (struct usb_descriptor_header *) &gser_ss_notify_desc,
+ (struct usb_descriptor_header *) &gser_ss_notify_comp_desc,
+#endif
(struct usb_descriptor_header *) &gser_ss_in_desc,
(struct usb_descriptor_header *) &gser_ss_bulk_comp_desc,
(struct usb_descriptor_header *) &gser_ss_out_desc,
@@ -304,7 +333,6 @@
ret = ghsic_ctrl_setup(no_hsic_sports, USB_GADGET_SERIAL);
if (ret < 0)
return ret;
- return 0;
}
if (no_hsuart_sports) {
port_idx = ghsuart_data_setup(no_hsuart_sports,
@@ -319,8 +347,6 @@
port_idx++;
}
}
-
- return 0;
}
return ret;
}
@@ -824,6 +850,10 @@
gser_fs_in_desc.bEndpointAddress;
gser_ss_out_desc.bEndpointAddress =
gser_fs_out_desc.bEndpointAddress;
+#ifdef CONFIG_MODEM_SUPPORT
+ gser_ss_notify_desc.bEndpointAddress =
+ gser_fs_notify_desc.bEndpointAddress;
+#endif
/* copy descriptors, and track endpoint copies */
f->ss_descriptors = usb_copy_descriptors(gser_ss_function);
@@ -839,6 +869,10 @@
return 0;
fail:
+ if (f->ss_descriptors)
+ usb_free_descriptors(f->ss_descriptors);
+ if (f->hs_descriptors)
+ usb_free_descriptors(f->hs_descriptors);
if (f->descriptors)
usb_free_descriptors(f->descriptors);
#ifdef CONFIG_MODEM_SUPPORT
diff --git a/drivers/usb/gadget/u_smd.c b/drivers/usb/gadget/u_smd.c
index ce285a3..effe418 100644
--- a/drivers/usb/gadget/u_smd.c
+++ b/drivers/usb/gadget/u_smd.c
@@ -72,6 +72,7 @@
struct smd_port_info *pi;
struct delayed_work connect_work;
+ struct work_struct disconnect_work;
/* At present, smd does not notify
* control bit change info from modem
@@ -589,6 +590,20 @@
}
}
+static void gsmd_disconnect_work(struct work_struct *w)
+{
+ struct gsmd_port *port;
+ struct smd_port_info *pi;
+
+ port = container_of(w, struct gsmd_port, disconnect_work);
+ pi = port->pi;
+
+ pr_debug("%s: port:%p port#%d\n", __func__, port, port->port_num);
+
+ smd_close(port->pi->ch);
+ port->pi->ch = NULL;
+}
+
static void gsmd_notify_modem(void *gptr, u8 portno, int ctrl_bits)
{
struct gsmd_port *port;
@@ -731,10 +746,8 @@
~port->cbits_to_modem);
}
- if (port->pi->ch) {
- smd_close(port->pi->ch);
- port->pi->ch = NULL;
- }
+ if (port->pi->ch)
+ queue_work(gsmd_wq, &port->disconnect_work);
}
#define SMD_CH_MAX_LEN 20
@@ -819,6 +832,7 @@
INIT_WORK(&port->pull, gsmd_tx_pull);
INIT_DELAYED_WORK(&port->connect_work, gsmd_connect_work);
+ INIT_WORK(&port->disconnect_work, gsmd_disconnect_work);
smd_ports[portno].port = port;
pdrv = &smd_ports[portno].pdrv;
diff --git a/drivers/usb/host/ehci-mem.c b/drivers/usb/host/ehci-mem.c
index 12f70c3..c61591a 100644
--- a/drivers/usb/host/ehci-mem.c
+++ b/drivers/usb/host/ehci-mem.c
@@ -178,12 +178,15 @@
static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
{
int i;
+ size_t align;
+
+ align = ((ehci->pool_64_bit_align) ? 64 : 32);
/* QTDs for control/bulk/intr transfers */
ehci->qtd_pool = dma_pool_create ("ehci_qtd",
ehci_to_hcd(ehci)->self.controller,
sizeof (struct ehci_qtd),
- 32 /* byte alignment (for hw parts) */,
+ align /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
if (!ehci->qtd_pool) {
goto fail;
@@ -193,7 +196,7 @@
ehci->qh_pool = dma_pool_create ("ehci_qh",
ehci_to_hcd(ehci)->self.controller,
sizeof(struct ehci_qh_hw),
- 32 /* byte alignment (for hw parts) */,
+ align /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
if (!ehci->qh_pool) {
goto fail;
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index cd02489..2d69a98 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -81,7 +81,6 @@
struct wake_lock wlock;
int peripheral_status_irq;
int wakeup_irq;
- int wakeup_gpio;
bool wakeup_irq_enabled;
atomic_t pm_usage_cnt;
uint32_t bus_perf_client;
@@ -325,7 +324,7 @@
#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
#define USB_PHY_VDD_DIG_VOL_NONE 0 /*uV */
-#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
+#define USB_PHY_VDD_DIG_VOL_MIN 945000 /* uV */
#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
#define HSIC_DBG1_REG 0x38
@@ -525,22 +524,11 @@
if (rc < 0) {
dev_err(mehci->dev, "gpio request failed for HSIC DATA\n");
goto free_strobe;
- }
-
- if (mehci->wakeup_gpio) {
- rc = gpio_request(mehci->wakeup_gpio, "HSIC_WAKEUP_GPIO");
- if (rc < 0) {
- dev_err(mehci->dev, "gpio request failed for HSIC WAKEUP\n");
- goto free_data;
- }
}
return 0;
free_gpio:
- if (mehci->wakeup_gpio)
- gpio_free(mehci->wakeup_gpio);
-free_data:
gpio_free(pdata->data);
free_strobe:
gpio_free(pdata->strobe);
@@ -653,6 +641,7 @@
int cnt = 0, ret;
u32 val;
int none_vol, max_vol;
+ struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
if (atomic_read(&mehci->in_lpm)) {
dev_dbg(mehci->dev, "%s called in lpm\n", __func__);
@@ -731,6 +720,10 @@
enable_irq_wake(mehci->wakeup_irq);
enable_irq(mehci->wakeup_irq);
+ if (pdata && pdata->standalone_latency)
+ pm_qos_update_request(&mehci->pm_qos_req_dma,
+ PM_QOS_DEFAULT_VALUE);
+
wake_unlock(&mehci->wlock);
dev_info(mehci->dev, "HSIC-USB in low power mode\n");
@@ -745,12 +738,17 @@
unsigned temp;
int min_vol, max_vol;
unsigned long flags;
+ struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
if (!atomic_read(&mehci->in_lpm)) {
dev_dbg(mehci->dev, "%s called in !in_lpm\n", __func__);
return 0;
}
+ if (pdata && pdata->standalone_latency)
+ pm_qos_update_request(&mehci->pm_qos_req_dma,
+ pdata->standalone_latency + 1);
+
spin_lock_irqsave(&mehci->wakeup_lock, flags);
if (mehci->wakeup_irq_enabled) {
disable_irq_wake(mehci->wakeup_irq);
@@ -1043,9 +1041,9 @@
pm_qos_update_request(&mehci->pm_qos_req_dma,
pdata->swfi_latency + 1);
wait_for_completion(&mehci->gpt0_completion);
- if (pdata && pdata->swfi_latency)
+ if (pdata && pdata->standalone_latency)
pm_qos_update_request(&mehci->pm_qos_req_dma,
- PM_QOS_DEFAULT_VALUE);
+ pdata->standalone_latency + 1);
spin_lock_irq(&ehci->lock);
} else {
dbg_log_event(NULL, "FPR: Tightloop", 0);
@@ -1596,10 +1594,9 @@
if (res)
mehci->peripheral_status_irq = res->start;
- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "wakeup");
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "wakeup");
if (res) {
- mehci->wakeup_gpio = res->start;
- mehci->wakeup_irq = MSM_GPIO_TO_INT(res->start);
+ mehci->wakeup_irq = res->start;
dev_dbg(mehci->dev, "wakeup_irq: %d\n", mehci->wakeup_irq);
}
@@ -1693,9 +1690,9 @@
__mehci = mehci;
- if (pdata && pdata->swfi_latency)
+ if (pdata && pdata->standalone_latency)
pm_qos_add_request(&mehci->pm_qos_req_dma,
- PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+ PM_QOS_CPU_DMA_LATENCY, pdata->standalone_latency + 1);
/*
* This pdev->dev is assigned parent of root-hub by USB core,
@@ -1734,7 +1731,7 @@
struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
- if (pdata && pdata->swfi_latency)
+ if (pdata && pdata->standalone_latency)
pm_qos_remove_request(&mehci->pm_qos_req_dma);
if (mehci->peripheral_status_irq)
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index d238b4e2..07a232a 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -30,6 +30,7 @@
hcd->has_tt = pdata->has_tt;
ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug;
+ ehci->pool_64_bit_align = pdata->pool_64_bit_align;
ehci->big_endian_desc = pdata->big_endian_desc;
ehci->big_endian_mmio = pdata->big_endian_mmio;
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index f8b884a..cd17421 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -166,6 +166,7 @@
unsigned has_hostpc:1;
unsigned has_lpm:1; /* support link power management */
unsigned has_ppcd:1; /* support per-port change bits */
+ unsigned pool_64_bit_align:1; /* for 64 bit alignment */
u8 sbrn; /* packed release number */
/* irq statistics */
diff --git a/drivers/usb/misc/mdm_ctrl_bridge.c b/drivers/usb/misc/mdm_ctrl_bridge.c
index 2f7e2c3..abc7b86 100644
--- a/drivers/usb/misc/mdm_ctrl_bridge.c
+++ b/drivers/usb/misc/mdm_ctrl_bridge.c
@@ -320,7 +320,6 @@
dev_dbg(&dev->intf->dev, "%s:\n", __func__);
ctrl_bridge_set_cbits(dev->brdg->ch_id, 0);
- usb_unlink_anchored_urbs(&dev->tx_submitted);
dev->brdg = NULL;
}
@@ -718,6 +717,8 @@
platform_device_unregister(dev->pdev);
+ usb_unlink_anchored_urbs(&dev->tx_submitted);
+
kfree(dev->in_ctlreq);
kfree(dev->readbuf);
kfree(dev->intbuf);
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 92cbe6f..c6fe765 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -82,6 +82,11 @@
MODULE_PARM_DESC(override_phy_init,
"Override HSUSB PHY Init Settings");
+unsigned int lpm_disconnect_thresh = 1000;
+module_param(lpm_disconnect_thresh , uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(lpm_disconnect_thresh,
+ "Delay before entering LPM on USB disconnect");
+
static DECLARE_COMPLETION(pmic_vbus_init);
static struct msm_otg *the_msm_otg;
static bool debug_aca_enabled;
@@ -1132,11 +1137,20 @@
if (legacy_power_supply) {
/* legacy support */
- if (host_mode)
+ if (host_mode) {
power_supply_set_scope(psy, POWER_SUPPLY_SCOPE_SYSTEM);
- else
+ } else {
power_supply_set_scope(psy, POWER_SUPPLY_SCOPE_DEVICE);
- return;
+ /*
+ * VBUS comparator is disabled by PMIC charging driver
+ * when SYSTEM scope is selected. For ID_GND->ID_A
+ * transition, give 50 msec delay so that PMIC charger
+ * driver detect the VBUS and ready for accepting
+ * charging current value from USB.
+ */
+ if (test_bit(ID_A, &motg->inputs))
+ msleep(50);
+ }
} else {
motg->host_mode = host_mode;
power_supply_changed(psy);
@@ -1568,6 +1582,26 @@
return 0;
}
+static bool msm_otg_read_pmic_id_state(struct msm_otg *motg)
+{
+ unsigned long flags;
+ int id;
+
+ if (!motg->pdata->pmic_id_irq)
+ return -ENODEV;
+
+ local_irq_save(flags);
+ id = irq_read_line(motg->pdata->pmic_id_irq);
+ local_irq_restore(flags);
+
+ /*
+ * If we can not read ID line state for some reason, treat
+ * it as float. This would prevent MHL discovery and kicking
+ * host mode unnecessarily.
+ */
+ return !!id;
+}
+
static int msm_otg_mhl_register_callback(struct msm_otg *motg,
void (*callback)(int on))
{
@@ -1650,14 +1684,11 @@
static bool msm_chg_mhl_detect(struct msm_otg *motg)
{
bool ret, id;
- unsigned long flags;
if (!motg->mhl_enabled)
return false;
- local_irq_save(flags);
- id = irq_read_line(motg->pdata->pmic_id_irq);
- local_irq_restore(flags);
+ id = msm_otg_read_pmic_id_state(motg);
if (id)
return false;
@@ -2285,13 +2316,10 @@
clear_bit(B_SESS_VLD, &motg->inputs);
} else if (pdata->otg_control == OTG_PMIC_CONTROL) {
if (pdata->pmic_id_irq) {
- unsigned long flags;
- local_irq_save(flags);
- if (irq_read_line(pdata->pmic_id_irq))
+ if (msm_otg_read_pmic_id_state(motg))
set_bit(ID, &motg->inputs);
else
clear_bit(ID, &motg->inputs);
- local_irq_restore(flags);
}
/*
* VBUS initial state is reported after PMIC
@@ -2439,8 +2467,25 @@
motg->chg_type = USB_INVALID_CHARGER;
msm_otg_notify_charger(motg, 0);
msm_otg_reset(otg->phy);
+ /*
+ * There is a small window where ID interrupt
+ * is not monitored during ID detection circuit
+ * switch from ACA to PMIC. Check ID state
+ * before entering into low power mode.
+ */
+ if (!msm_otg_read_pmic_id_state(motg)) {
+ pr_debug("process missed ID intr\n");
+ clear_bit(ID, &motg->inputs);
+ work = 1;
+ break;
+ }
pm_runtime_put_noidle(otg->phy->dev);
- pm_runtime_suspend(otg->phy->dev);
+ /*
+ * Only if autosuspend was enabled in probe, it will be
+ * used here. Otherwise, no delay will be used.
+ */
+ pm_runtime_mark_last_busy(otg->phy->dev);
+ pm_runtime_autosuspend(otg->phy->dev);
}
break;
case OTG_STATE_B_SRP_INIT:
@@ -3068,10 +3113,9 @@
{
static bool init;
struct msm_otg *motg = the_msm_otg;
- struct usb_otg *otg = motg->phy.otg;
- /* In A Host Mode, ignore received BSV interrupts */
- if (otg->phy->state >= OTG_STATE_A_IDLE)
+ /* Ignore received BSV interrupts, if ID pin is GND */
+ if (!test_bit(ID, &motg->inputs))
return;
if (online) {
@@ -3106,10 +3150,8 @@
struct msm_otg *motg = container_of(w, struct msm_otg,
pmic_id_status_work.work);
int work = 0;
- unsigned long flags;
- local_irq_save(flags);
- if (irq_read_line(motg->pdata->pmic_id_irq)) {
+ if (msm_otg_read_pmic_id_state(motg)) {
if (!test_and_set_bit(ID, &motg->inputs)) {
pr_debug("PMIC: ID set\n");
work = 1;
@@ -3128,7 +3170,6 @@
else
queue_work(system_nrt_wq, &motg->sm_work);
}
- local_irq_restore(flags);
}
@@ -3990,6 +4031,12 @@
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
+ if (motg->pdata->delay_lpm_on_disconnect) {
+ pm_runtime_set_autosuspend_delay(&pdev->dev,
+ lpm_disconnect_thresh);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ }
+
if (motg->pdata->bus_scale_table) {
motg->bus_perf_client =
msm_bus_scale_register_client(motg->pdata->bus_scale_table);
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index 9f30041..7a92645 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -3022,8 +3022,6 @@
hdmi_msm_state->hdcp_activating = TRUE;
mutex_unlock(&hdmi_msm_state_mutex);
- fill_black_screen();
-
mutex_lock(&hdcp_auth_state_mutex);
/*
* Initialize this to zero here to make
@@ -3065,8 +3063,6 @@
if (ret)
goto error;
- unfill_black_screen();
-
mutex_lock(&hdmi_msm_state_mutex);
hdmi_msm_state->hdcp_activating = FALSE;
mutex_unlock(&hdmi_msm_state_mutex);
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 25da094..fc512c1 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1333,7 +1333,7 @@
}
#endif
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp_dma_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
@@ -1452,6 +1452,11 @@
vsync_period);
if (diff_to_next > vsync_period)
return;
+ pr_debug("%s cur_time %d, pre_vsync %d, to_next %d\n",
+ __func__,
+ (int)ktime_to_ms(cur_time),
+ (int)ktime_to_ms(pre_vsync),
+ diff_to_next);
wakeup_time = ktime_add_ns(cur_time, diff_to_next * NSEC_PER_MSEC);
activate_event_timer(mfd->cpu_pm_hdl, wakeup_time);
}
@@ -2239,15 +2244,6 @@
}
#endif
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
-
static int mdp_on(struct platform_device *pdev)
{
int ret = 0;
@@ -2282,21 +2278,7 @@
if (mdp_rev == MDP_REV_303 && mfd->panel.type == MIPI_CMD_PANEL) {
vsync_cntrl.dev = mfd->fbi->dev;
-
- if (!vsync_cntrl.sysfs_created) {
- ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vsync_cntrl.sysfs_created = 1;
- }
- atomic_set(&vsync_cntrl.suspend, 0);
+ atomic_set(&vsync_cntrl.suspend, 1);
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
@@ -2528,8 +2510,6 @@
#if defined(CONFIG_FB_MSM_MIPI_DSI) && defined(CONFIG_FB_MSM_MDP40)
struct mipi_panel_info *mipi;
#endif
- static int contSplash_update_done;
- char *cp;
unsigned int mdp_r = 0;
if ((pdev->id == 0) && (pdev->num_resources > 0)) {
@@ -2612,57 +2592,7 @@
/* link to the latest pdev */
mfd->pdev = msm_fb_dev;
mfd->mdp_rev = mdp_rev;
-
- if (mdp_pdata) {
- if (mdp_pdata->cont_splash_enabled) {
- mfd->cont_splash_done = 0;
-
- if (!contSplash_update_done) {
- uint32 bpp = 3;
- /*read panel wxh and calculate splash screen
- size*/
- mdp_pdata->splash_screen_size =
- inpdw(MDP_BASE + 0x90004);
- mdp_pdata->splash_screen_size =
- (((mdp_pdata->splash_screen_size >> 16) &
- 0x00000FFF) * (
- mdp_pdata->splash_screen_size &
- 0x00000FFF)) * bpp;
-
- mdp_pdata->splash_screen_addr =
- inpdw(MDP_BASE + 0x90008);
-
- mfd->copy_splash_buf = dma_alloc_coherent(NULL,
- mdp_pdata->splash_screen_size,
- (dma_addr_t *) &(mfd->copy_splash_phys),
- GFP_KERNEL);
-
- if (!mfd->copy_splash_buf) {
- pr_err("DMA ALLOC FAILED for SPLASH\n");
- return -ENOMEM;
- }
- cp = (char *)ioremap(
- mdp_pdata->splash_screen_addr,
- mdp_pdata->splash_screen_size);
- if (!cp) {
- pr_err("IOREMAP FAILED for SPLASH\n");
- return -ENOMEM;
- }
- memcpy(mfd->copy_splash_buf, cp,
- mdp_pdata->splash_screen_size);
-
- MDP_OUTP(MDP_BASE + 0x90008,
- mfd->copy_splash_phys);
-
- if (mfd->panel.type == MIPI_VIDEO_PANEL ||
- mfd->panel.type == LCDC_PANEL)
- mdp_pipe_ctrl(MDP_CMD_BLOCK,
- MDP_BLOCK_POWER_ON, FALSE);
- contSplash_update_done = 1;
- }
- } else
- mfd->cont_splash_done = 1;
- }
+ mfd->vsync_init = NULL;
mfd->ov0_wb_buf = MDP_ALLOC(sizeof(struct mdp_buf_type));
mfd->ov1_wb_buf = MDP_ALLOC(sizeof(struct mdp_buf_type));
@@ -2694,6 +2624,53 @@
rc = -ENOMEM;
goto mdp_probe_err;
}
+
+ if (mdp_pdata) {
+ if (mdp_pdata->cont_splash_enabled &&
+ mfd->panel_info.pdest == DISPLAY_1) {
+ char *cp;
+ uint32 bpp = 3;
+ /*read panel wxh and calculate splash screen
+ size*/
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
+
+ mdp_pdata->splash_screen_size =
+ inpdw(MDP_BASE + 0x90004);
+ mdp_pdata->splash_screen_size =
+ (((mdp_pdata->splash_screen_size >> 16) &
+ 0x00000FFF) * (
+ mdp_pdata->splash_screen_size &
+ 0x00000FFF)) * bpp;
+
+ mdp_pdata->splash_screen_addr =
+ inpdw(MDP_BASE + 0x90008);
+
+ mfd->copy_splash_buf = dma_alloc_coherent(NULL,
+ mdp_pdata->splash_screen_size,
+ (dma_addr_t *) &(mfd->copy_splash_phys),
+ GFP_KERNEL);
+
+ if (!mfd->copy_splash_buf) {
+ pr_err("DMA ALLOC FAILED for SPLASH\n");
+ return -ENOMEM;
+ }
+ cp = (char *)ioremap(
+ mdp_pdata->splash_screen_addr,
+ mdp_pdata->splash_screen_size);
+ if (!cp) {
+ pr_err("IOREMAP FAILED for SPLASH\n");
+ return -ENOMEM;
+ }
+ memcpy(mfd->copy_splash_buf, cp,
+ mdp_pdata->splash_screen_size);
+
+ MDP_OUTP(MDP_BASE + 0x90008,
+ mfd->copy_splash_phys);
+ }
+
+ mfd->cont_splash_done = (1 - mdp_pdata->cont_splash_enabled);
+ }
+
/* data chain */
pdata = msm_fb_dev->dev.platform_data;
pdata->on = mdp_on;
@@ -2781,7 +2758,8 @@
case MIPI_VIDEO_PANEL:
#ifndef CONFIG_FB_MSM_MDP303
mipi = &mfd->panel_info.mipi;
- mdp4_dsi_vsync_init(0);
+ mfd->vsync_init = mdp4_dsi_vsync_init;
+ mfd->vsync_show = mdp4_dsi_video_show_event;
mfd->hw_refresh = TRUE;
mfd->dma_fnc = mdp4_dsi_video_overlay;
mfd->lut_update = mdp_lut_update_lcdc;
@@ -2805,6 +2783,7 @@
mfd->start_histogram = mdp_histogram_start;
mfd->stop_histogram = mdp_histogram_stop;
mfd->vsync_ctrl = mdp_dma_video_vsync_ctrl;
+ mfd->vsync_show = mdp_dma_video_show_event;
if (mfd->panel_info.pdest == DISPLAY_1)
mfd->dma = &dma2_data;
else {
@@ -2825,7 +2804,8 @@
#ifndef CONFIG_FB_MSM_MDP303
mfd->dma_fnc = mdp4_dsi_cmd_overlay;
mipi = &mfd->panel_info.mipi;
- mdp4_dsi_rdptr_init(0);
+ mfd->vsync_init = mdp4_dsi_rdptr_init;
+ mfd->vsync_show = mdp4_dsi_cmd_show_event;
if (mfd->panel_info.pdest == DISPLAY_1) {
if_no = PRIMARY_INTF_SEL;
mfd->dma = &dma2_data;
@@ -2844,6 +2824,7 @@
mfd->start_histogram = mdp_histogram_start;
mfd->stop_histogram = mdp_histogram_stop;
mfd->vsync_ctrl = mdp_dma_vsync_ctrl;
+ mfd->vsync_show = mdp_dma_show_event;
if (mfd->panel_info.pdest == DISPLAY_1)
mfd->dma = &dma2_data;
else {
@@ -2861,7 +2842,8 @@
#ifdef CONFIG_FB_MSM_DTV
case DTV_PANEL:
- mdp4_dtv_vsync_init(0);
+ mfd->vsync_init = mdp4_dtv_vsync_init;
+ mfd->vsync_show = mdp4_dtv_show_event;
pdata->on = mdp4_dtv_on;
pdata->off = mdp4_dtv_off;
mfd->hw_refresh = TRUE;
@@ -2900,7 +2882,8 @@
#endif
#ifdef CONFIG_FB_MSM_MDP40
- mdp4_lcdc_vsync_init(0);
+ mfd->vsync_init = mdp4_lcdc_vsync_init;
+ mfd->vsync_show = mdp4_lcdc_show_event;
if (mfd->panel.type == HDMI_PANEL) {
mfd->dma = &dma_e_data;
mdp4_display_intf_sel(EXTERNAL_INTF_SEL, LCDC_RGB_INTF);
@@ -2911,6 +2894,7 @@
#else
mfd->dma = &dma2_data;
mfd->vsync_ctrl = mdp_dma_lcdc_vsync_ctrl;
+ mfd->vsync_show = mdp_dma_lcdc_show_event;
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_intr_mask &= ~MDP_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
@@ -2993,7 +2977,7 @@
}
/* req bus bandwidth immediately */
- if (!(mfd->cont_splash_done))
+ if (!(mfd->cont_splash_done) && (mfd->panel_info.pdest == DISPLAY_1))
mdp_bus_scale_update_request(5);
#endif
@@ -3011,6 +2995,29 @@
pdev_list[pdev_list_cnt++] = pdev;
mdp4_extn_disp = 0;
+
+ if (mfd->vsync_init != NULL) {
+ mfd->vsync_init(0);
+
+ if (!mfd->vsync_sysfs_created) {
+ mfd->dev_attr.attr.name = "vsync_event";
+ mfd->dev_attr.attr.mode = S_IRUGO;
+ mfd->dev_attr.show = mfd->vsync_show;
+ sysfs_attr_init(&mfd->dev_attr.attr);
+
+ rc = sysfs_create_file(&mfd->fbi->dev->kobj,
+ &mfd->dev_attr.attr);
+ if (rc) {
+ pr_err("%s: sysfs creation failed, ret=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ kobject_uevent(&mfd->fbi->dev->kobj, KOBJ_ADD);
+ pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
+ mfd->vsync_sysfs_created = 1;
+ }
+ }
return 0;
mdp_probe_err:
@@ -3120,7 +3127,7 @@
{
mdp_suspend_sub();
#ifdef CONFIG_FB_MSM_DTV
- mdp4_dtv_set_black_screen();
+ mdp4_dtv_set_black_screen(FALSE);
#endif
mdp_footswitch_ctrl(FALSE);
}
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index b4a7f79..0bc2532 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -862,6 +862,12 @@
void mdp_dma_vsync_ctrl(int enable);
void mdp_dma_video_vsync_ctrl(int enable);
void mdp_dma_lcdc_vsync_ctrl(int enable);
+ssize_t mdp_dma_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t mdp_dma_video_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t mdp_dma_lcdc_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
#ifdef MDP_HW_VSYNC
void vsync_clk_prepare_enable(void);
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 3ea196a..2f4fac1 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -531,7 +531,7 @@
}
#endif /* CONFIG_FB_MSM_DTV */
-void mdp4_dtv_set_black_screen(void);
+void mdp4_dtv_set_black_screen(bool commit);
int mdp4_overlay_dtv_set(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe);
@@ -557,6 +557,14 @@
void mdp4_dsi_vsync_init(int cndx);
void mdp4_lcdc_vsync_init(int cndx);
void mdp4_dtv_vsync_init(int cndx);
+ssize_t mdp4_dsi_cmd_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t mdp4_dsi_video_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t mdp4_lcdc_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
+ssize_t mdp4_dtv_show_event(struct device *dev,
+ struct device_attribute *attr, char *buf);
void mdp4_overlay_dsi_state_set(int state);
int mdp4_overlay_dsi_state_get(void);
void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index 1bd697e..11952f3 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -192,12 +192,19 @@
return;
if (pipe->flags & MDP_MEMORY_ID_TYPE_FB) {
- if (pipe->put0_need)
+ pipe->flags &= ~MDP_MEMORY_ID_TYPE_FB;
+ if (pipe->put0_need) {
fput_light(pipe->srcp0_file, pipe->put0_need);
- if (pipe->put1_need)
+ pipe->put0_need = 0;
+ }
+ if (pipe->put1_need) {
fput_light(pipe->srcp1_file, pipe->put1_need);
- if (pipe->put2_need)
+ pipe->put1_need = 0;
+ }
+ if (pipe->put2_need) {
fput_light(pipe->srcp2_file, pipe->put2_need);
+ pipe->put2_need = 0;
+ }
pr_debug("%s: ndx=%d flags=%x put=%d\n", __func__,
pipe->pipe_ndx, pipe->flags, pipe->put0_need);
@@ -409,53 +416,34 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
-#ifdef CONFIG_FB_MSM_HDMI_3D
-void unfill_black_screen(void) { return; }
-#else
-void unfill_black_screen(void)
+void fill_black_screen(bool on, uint8 pipe_num, uint8 mixer_num)
{
- uint32 temp_src_format;
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
- /*
- * VG2 Constant Color
- */
- temp_src_format = inpdw(MDP_BASE + 0x30050);
- MDP_OUTP(MDP_BASE + 0x30050, temp_src_format&(~BIT(22)));
- /*
- * MDP_OVERLAY_REG_FLUSH
- */
- MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
- return;
-}
-#endif
+ uint32 reg_base = 0x010000;
+ uint32 const_color_reg = reg_base * (pipe_num + 2) + 0x1008;
+ uint32 src_fmt_reg = reg_base * (pipe_num + 2) + 0x50;
+ uint32 color = 0x00000000;
+ uint32 temp_src_format = 0x00000000;
+ uint8 bit = pipe_num + 2;
-#ifdef CONFIG_FB_MSM_HDMI_3D
-void fill_black_screen(void) { return; }
-#else
-void fill_black_screen(void)
-{
- /*Black color*/
- uint32 color = 0x00000000;
- uint32 temp_src_format;
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
- /*
- * VG2 Constant Color
- */
- MDP_OUTP(MDP_BASE + 0x31008, color);
- /*
- * MDP_VG2_SRC_FORMAT
- */
- temp_src_format = inpdw(MDP_BASE + 0x30050);
- MDP_OUTP(MDP_BASE + 0x30050, temp_src_format | BIT(22));
- /*
- * MDP_OVERLAY_REG_FLUSH
- */
- MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
+
+ /* Fill constant color */
+ MDP_OUTP(MDP_BASE + const_color_reg, color);
+
+ /* Update source format for pipe */
+ temp_src_format = inpdw(MDP_BASE + src_fmt_reg);
+
+ if (on)
+ MDP_OUTP(MDP_BASE + src_fmt_reg, temp_src_format | BIT(22));
+ else
+ MDP_OUTP(MDP_BASE + src_fmt_reg, temp_src_format | (~BIT(22)));
+
+ /* MDP_OVERLAY_REG_FLUSH for pipe*/
+ MDP_OUTP(MDP_BASE + 0x18000, BIT(bit) | BIT(mixer_num));
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+
return;
}
-#endif
void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
{
@@ -730,8 +718,14 @@
op_mode &= ~(MDP4_OP_FLIP_LR + MDP4_OP_SCALEX_EN);
op_mode &= ~(MDP4_OP_FLIP_UD + MDP4_OP_SCALEY_EN);
outpdw(rgb_base + 0x0058, op_mode);/* MDP_RGB_OP_MODE */
- } else
+ } else {
+ if (pipe->op_mode & MDP4_OP_FLIP_LR && mdp_rev >= MDP_REV_42) {
+ /* Enable x-scaling bit to enable LR flip */
+ /* for MDP > 4.2 targets */
+ pipe->op_mode |= 0x01;
+ }
outpdw(rgb_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
+ }
outpdw(rgb_base + 0x005c, pipe->phasex_step);
outpdw(rgb_base + 0x0060, pipe->phasey_step);
@@ -1777,6 +1771,7 @@
struct mdp4_overlay_pipe *bspipe;
int ptype, pnum, pndx, mixer;
int format, alpha_enable, alpha;
+ struct mdp4_iommu_pipe_info iom;
if (pipe->pipe_type != OVERLAY_TYPE_BF)
return;
@@ -1791,6 +1786,7 @@
return;
}
+ iom = bspipe->iommu;
ptype = bspipe->pipe_type;
pnum = bspipe->pipe_num;
pndx = bspipe->pipe_ndx;
@@ -1804,6 +1800,7 @@
bspipe->src_format = format;
bspipe->alpha_enable = alpha_enable;
bspipe->alpha = alpha;
+ bspipe->iommu = iom;
bspipe->pipe_used++; /* mark base layer pipe used */
@@ -3116,6 +3113,9 @@
__func__);
}
+ if (hdmi_prim_display)
+ fill_black_screen(FALSE, pipe->pipe_num, pipe->mixer_num);
+
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mutex_unlock(&mfd->dma->ov_mutex);
@@ -3188,8 +3188,12 @@
if (pipe->mixer_num == MDP4_MIXER0) {
} else { /* mixer1, DTV, ATV */
- if (ctrl->panel_mode & MDP4_PANEL_DTV)
+ if (ctrl->panel_mode & MDP4_PANEL_DTV) {
+ if (hdmi_prim_display)
+ fill_black_screen(TRUE, pipe->pipe_num,
+ pipe->mixer_num);
mdp4_overlay_dtv_unset(mfd, pipe);
+ }
}
mdp4_stat.overlay_unset[pipe->mixer_num]++;
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index 10410a7..9cb2b34 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -70,6 +70,7 @@
struct vsync_update vlist[2];
int vsync_enabled;
int clk_enabled;
+ int new_update;
int clk_control;
ktime_t vsync_time;
struct work_struct clk_work;
@@ -272,6 +273,8 @@
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
@@ -421,6 +424,7 @@
mipi_dsi_clk_cfg(1);
mdp_clk_ctrl(1);
vctrl->clk_enabled = 1;
+ vctrl->new_update = 1;
clk_set_on = 1;
}
if (clk_set_on) {
@@ -517,6 +521,12 @@
spin_lock(&vctrl->spin_lock);
vctrl->vsync_time = ktime_get();
+ if (vctrl->new_update) {
+ vctrl->new_update = 0;
+ spin_unlock(&vctrl->spin_lock);
+ return;
+ }
+
complete_all(&vctrl->vsync_comp);
vctrl->wait_vsync_cnt = 0;
@@ -652,7 +662,7 @@
mutex_unlock(&vctrl->update_lock);
}
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp4_dsi_cmd_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
int cndx;
@@ -673,9 +683,12 @@
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
- if (ret)
- return ret;
+ ret = wait_for_completion_interruptible_timeout(&vctrl->vsync_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+ if (ret <= 0) {
+ vctrl->wait_vsync_cnt = 0;
+ return -EBUSY;
+ }
spin_lock_irqsave(&vctrl->spin_lock, flags);
vsync_tick = ktime_to_ns(vctrl->vsync_time);
@@ -708,6 +721,7 @@
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->vsync_comp);
spin_lock_init(&vctrl->spin_lock);
+ atomic_set(&vctrl->suspend, 1);
INIT_WORK(&vctrl->clk_work, clk_ctrl_work);
}
@@ -976,14 +990,6 @@
mdp4_dsi_cmd_do_blt(mfd, req->enable);
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
int mdp4_dsi_cmd_on(struct platform_device *pdev)
{
int ret = 0;
@@ -1008,22 +1014,7 @@
atomic_set(&vctrl->suspend, 0);
- if (!vctrl->sysfs_created) {
- ret = sysfs_create_group(&vctrl->dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs group creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vctrl->sysfs_created = 1;
- }
-
pr_debug("%s-:\n", __func__);
-
return ret;
}
@@ -1037,6 +1028,7 @@
struct vsync_update *vp;
int undx;
int need_wait, cnt;
+ unsigned long flags;
pr_debug("%s+: pid=%d\n", __func__, current->pid);
@@ -1071,11 +1063,16 @@
}
}
- /* message for system suspnded */
- if (cnt > 10)
- pr_err("%s:Error, mdp clocks NOT off\n", __func__);
- else
- pr_debug("%s: mdp clocks off at cnt=%d\n", __func__, cnt);
+ if (cnt > 10) {
+ spin_lock_irqsave(&vctrl->spin_lock, flags);
+ vctrl->clk_control = 0;
+ vctrl->clk_enabled = 0;
+ vctrl->expire_tick = 0;
+ spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ mipi_dsi_clk_cfg(0);
+ mdp_clk_ctrl(0);
+ pr_err("%s: Error, SET_CLK_OFF by force\n", __func__);
+ }
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index 5551c9d..239d9f5 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -56,6 +56,7 @@
int wait_vsync_cnt;
int blt_change;
int blt_free;
+ int blt_ctrl;
int sysfs_created;
struct mutex update_lock;
struct completion ov_comp;
@@ -167,6 +168,8 @@
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
@@ -373,7 +376,7 @@
wait_for_completion(&vctrl->ov_comp);
}
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp4_dsi_video_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
int cndx;
@@ -394,9 +397,12 @@
INIT_COMPLETION(vctrl->vsync_comp);
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
- if (ret)
- return ret;
+ ret = wait_for_completion_interruptible_timeout(&vctrl->vsync_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+ if (ret <= 0) {
+ vctrl->wait_vsync_cnt = 0;
+ return -EBUSY;
+ }
spin_lock_irqsave(&vctrl->spin_lock, flags);
vsync_tick = ktime_to_ns(vctrl->vsync_time);
@@ -416,7 +422,7 @@
return;
}
- pr_info("%s: ndx=%d\n", __func__, cndx);
+ pr_debug("%s: ndx=%d\n", __func__, cndx);
vctrl = &vsync_ctrl_db[cndx];
if (vctrl->inited)
@@ -428,7 +434,7 @@
init_completion(&vctrl->vsync_comp);
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->ov_comp);
- atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
}
@@ -446,16 +452,6 @@
vctrl->base_pipe = pipe;
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
int mdp4_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
@@ -498,9 +494,11 @@
int ret = 0;
int cndx = 0;
struct vsycn_ctrl *vctrl;
+ struct msm_panel_info *pinfo;
vctrl = &vsync_ctrl_db[cndx];
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
+ pinfo = &mfd->panel_info;
if (!mfd)
return -ENODEV;
@@ -510,6 +508,7 @@
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
+ vctrl->blt_ctrl = pinfo->lcd.blt_ctrl;
/* mdp clock on */
mdp_clk_ctrl(1);
@@ -669,20 +668,6 @@
mdp_histogram_ctrl_all(TRUE);
- if (!vctrl->sysfs_created) {
- ret = sysfs_create_group(&vctrl->dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs group creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vctrl->sysfs_created = 1;
- }
-
return ret;
}
@@ -1011,6 +996,7 @@
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
+ long long vtime;
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
@@ -1047,8 +1033,32 @@
spin_unlock_irqrestore(&vctrl->spin_lock, flag);
return;
}
-
spin_unlock_irqrestore(&vctrl->spin_lock, flag);
+
+ if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) {
+ int tg_enabled;
+
+ vctrl->blt_change = 0;
+ tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
+ if (tg_enabled) {
+ mdp4_dsi_video_wait4vsync(0, &vtime);
+ MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
+ mdp4_dsi_video_wait4dmap_done(0);
+ }
+ mdp4_overlayproc_cfg(pipe);
+ mdp4_overlay_dmap_xy(pipe);
+ if (tg_enabled) {
+ /*
+ * need wait for more than 1 ms to
+ * make sure dsi lanes' fifo is empty and
+ * lanes in stop state befroe reset
+ * controller
+ */
+ usleep(2000);
+ mipi_dsi_sw_reset();
+ MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
+ }
+ }
}
void mdp4_dsi_video_overlay_blt(struct msm_fb_data_type *mfd,
@@ -1102,7 +1112,6 @@
mdp4_dsi_video_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
mdp4_overlay_mdp_perf_upd(mfd, 1);
cnt = mdp4_dsi_video_pipe_commit(cndx, 0);
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index e71f49f..398fafa 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -72,6 +72,7 @@
struct completion dmae_comp;
struct completion vsync_comp;
spinlock_t spin_lock;
+ struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *base_pipe;
struct vsync_update vlist[2];
int vsync_irq_enabled;
@@ -180,6 +181,8 @@
mixer = pipe->mixer_num;
mdp4_overlay_iommu_unmap_freelist(mixer);
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
@@ -310,7 +313,7 @@
wait_for_completion(&vctrl->dmae_comp);
}
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp4_dtv_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
int cndx;
@@ -337,9 +340,12 @@
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
- if (ret)
- return ret;
+ ret = wait_for_completion_interruptible_timeout(&vctrl->vsync_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+ if (ret <= 0) {
+ vctrl->wait_vsync_cnt = 0;
+ return -EBUSY;
+ }
spin_lock_irqsave(&vctrl->spin_lock, flags);
vg1fd = vctrl->vg1fd;
@@ -382,7 +388,7 @@
init_completion(&vctrl->vsync_comp);
init_completion(&vctrl->ov_comp);
init_completion(&vctrl->dmae_comp);
- atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
}
@@ -439,6 +445,9 @@
int hsync_end_x;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
+ struct vsycn_ctrl *vctrl;
+
+ vctrl = &vsync_ctrl_db[0];
if (!mfd)
return -ENODEV;
@@ -449,6 +458,8 @@
fbi = mfd->fbi;
var = &fbi->var;
+ vctrl->mfd = mfd;
+
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (hdmi_prim_display) {
if (is_mdp4_hw_reset()) {
@@ -561,15 +572,6 @@
return 0;
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
-
int mdp4_dtv_on(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
@@ -609,21 +611,6 @@
pr_warn("%s: panel_next_on failed", __func__);
atomic_set(&vctrl->suspend, 0);
-
- if (!vctrl->sysfs_created) {
- ret = sysfs_create_group(&vctrl->dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs group creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vctrl->sysfs_created = 1;
- }
-
if (mfd->avtimer_phy && (vctrl->avtimer == NULL)) {
vctrl->avtimer = (uint32 *)ioremap(mfd->avtimer_phy, 8);
if (vctrl->avtimer == NULL)
@@ -1004,7 +991,7 @@
spin_unlock(&vctrl->spin_lock);
}
-void mdp4_dtv_set_black_screen(void)
+void mdp4_dtv_set_black_screen(bool commit)
{
char *rgb_base;
/*Black color*/
@@ -1015,26 +1002,34 @@
vctrl = &vsync_ctrl_db[cndx];
if (vctrl->base_pipe == NULL || !hdmi_prim_display) {
- pr_err("dtv_pipe is not configured yet\n");
+ pr_debug("dtv_pipe is not configured yet\n");
return;
}
- rgb_base = MDP_BASE + MDP4_RGB_BASE;
- rgb_base += (MDP4_RGB_OFF * vctrl->base_pipe->pipe_num);
+ rgb_base = MDP_BASE;
+ rgb_base += (MDP4_RGB_OFF * (vctrl->base_pipe->pipe_num + 2));
- /*
- * RGB Constant Color
- */
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
+
+ /* RGB Constant Color */
MDP_OUTP(rgb_base + 0x1008, color);
- /*
- * MDP_RGB_SRC_FORMAT
- */
+
+ /* MDP_RGB_SRC_FORMAT */
temp_src_format = inpdw(rgb_base + 0x0050);
MDP_OUTP(rgb_base + 0x0050, temp_src_format | BIT(22));
- mdp4_overlay_reg_flush(vctrl->base_pipe, 1);
- mdp4_mixer_stage_up(vctrl->base_pipe, 0);
- mdp4_mixer_stage_commit(vctrl->base_pipe->mixer_num);
- mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+ if (commit) {
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+
+ mdp4_overlay_reg_flush(vctrl->base_pipe, 1);
+
+ mdp4_mixer_stage_up(vctrl->base_pipe, 0);
+ mdp4_mixer_stage_commit(vctrl->base_pipe->mixer_num);
+ } else {
+ /* MDP_OVERLAY_REG_FLUSH for pipe*/
+ MDP_OUTP(MDP_BASE + 0x18000,
+ BIT(vctrl->base_pipe->pipe_num + 2) | BIT(MDP4_MIXER1));
+ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+ }
}
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
@@ -1145,7 +1140,6 @@
pipe->srcp0_addr = (uint32)mfd->ibuf.buf;
mdp4_dtv_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
if (hdmi_prim_display)
wait = 1;
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index df5c262..a7058ce 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -172,6 +172,8 @@
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
@@ -359,7 +361,7 @@
wait_for_completion(&vctrl->ov_comp);
}
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp4_lcdc_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
int cndx;
@@ -380,9 +382,12 @@
INIT_COMPLETION(vctrl->vsync_comp);
vctrl->wait_vsync_cnt++;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
- ret = wait_for_completion_interruptible(&vctrl->vsync_comp);
- if (ret)
- return ret;
+ ret = wait_for_completion_interruptible_timeout(&vctrl->vsync_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+ if (ret <= 0) {
+ vctrl->wait_vsync_cnt = 0;
+ return -EBUSY;
+ }
spin_lock_irqsave(&vctrl->spin_lock, flags);
vsync_tick = ktime_to_ns(vctrl->vsync_time);
@@ -414,7 +419,7 @@
init_completion(&vctrl->vsync_comp);
init_completion(&vctrl->dmap_comp);
init_completion(&vctrl->ov_comp);
- atomic_set(&vctrl->suspend, 0);
+ atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 1);
spin_lock_init(&vctrl->spin_lock);
}
@@ -432,15 +437,6 @@
vctrl->base_pipe = pipe;
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
-
int mdp4_lcdc_on(struct platform_device *pdev)
{
int lcdc_width;
@@ -655,20 +651,6 @@
mdp_histogram_ctrl_all(TRUE);
- if (!vctrl->sysfs_created) {
- ret = sysfs_create_group(&vctrl->dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs group creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vctrl->dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vctrl->sysfs_created = 1;
- }
-
return ret;
}
@@ -989,7 +971,6 @@
mdp4_lcdc_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
mdp4_overlay_mdp_perf_upd(mfd, 1);
diff --git a/drivers/video/msm/mdp4_overlay_writeback.c b/drivers/video/msm/mdp4_overlay_writeback.c
index 18c6635..6c2b1f6 100644
--- a/drivers/video/msm/mdp4_overlay_writeback.c
+++ b/drivers/video/msm/mdp4_overlay_writeback.c
@@ -171,6 +171,8 @@
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
int ret = 0;
+ int undx;
+ struct vsync_update *vp;
pr_debug("%s+:\n", __func__);
@@ -189,6 +191,16 @@
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
+ undx = vctrl->update_ndx;
+ vp = &vctrl->vlist[undx];
+ if (vp->update_cnt) {
+ /*
+ * pipe's iommu will be freed at next overlay play
+ * and iommu_drop statistic will be increased by one
+ */
+ vp->update_cnt = 0; /* empty queue */
+ }
+
ret = panel_next_off(pdev);
mdp_clk_ctrl(1);
@@ -253,6 +265,12 @@
mdp4_mixer_stage_up(pipe, 0);
mdp4_overlayproc_cfg(pipe);
+
+ if (hdmi_prim_display)
+ outpdw(MDP_BASE + 0x100F4, 0x01);
+ else
+ outpdw(MDP_BASE + 0x100F4, 0x02);
+
/* MDP cmd block disable */
mdp_clk_ctrl(0);
diff --git a/drivers/video/msm/mdp_dma_dsi_video.c b/drivers/video/msm/mdp_dma_dsi_video.c
index e2fb8ba..cfbff9a 100644
--- a/drivers/video/msm/mdp_dma_dsi_video.c
+++ b/drivers/video/msm/mdp_dma_dsi_video.c
@@ -34,7 +34,7 @@
static int first_pixel_start_x;
static int first_pixel_start_y;
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp_dma_video_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
@@ -52,15 +52,6 @@
return ret;
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
-
int mdp_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
@@ -254,20 +245,6 @@
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
- if (!vsync_cntrl.sysfs_created) {
- ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vsync_cntrl.sysfs_created = 1;
- }
-
return ret;
}
diff --git a/drivers/video/msm/mdp_dma_lcdc.c b/drivers/video/msm/mdp_dma_lcdc.c
index fbfe35f..c51a99a 100644
--- a/drivers/video/msm/mdp_dma_lcdc.c
+++ b/drivers/video/msm/mdp_dma_lcdc.c
@@ -51,7 +51,7 @@
int first_pixel_start_x;
int first_pixel_start_y;
-static ssize_t vsync_show_event(struct device *dev,
+ssize_t mdp_dma_lcdc_show_event(struct device *dev,
struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
@@ -69,15 +69,6 @@
return ret;
}
-static DEVICE_ATTR(vsync_event, S_IRUGO, vsync_show_event, NULL);
-static struct attribute *vsync_fs_attrs[] = {
- &dev_attr_vsync_event.attr,
- NULL,
-};
-static struct attribute_group vsync_fs_attr_group = {
- .attrs = vsync_fs_attrs,
-};
-
int mdp_lcdc_on(struct platform_device *pdev)
{
int lcdc_width;
@@ -320,20 +311,6 @@
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
- if (!vsync_cntrl.sysfs_created) {
- ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
- &vsync_fs_attr_group);
- if (ret) {
- pr_err("%s: sysfs creation failed, ret=%d\n",
- __func__, ret);
- return ret;
- }
-
- kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
- pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
- vsync_cntrl.sysfs_created = 1;
- }
-
return ret;
}
diff --git a/drivers/video/msm/mdss/Kconfig b/drivers/video/msm/mdss/Kconfig
index 424455f..56eb90c 100644
--- a/drivers/video/msm/mdss/Kconfig
+++ b/drivers/video/msm/mdss/Kconfig
@@ -11,3 +11,12 @@
---help---
The MDSS HDMI Panel provides support for transmitting TMDS signals of
MDSS frame buffer data to connected hdmi compliant TVs, monitors etc.
+
+config FB_MSM_MDSS_HDMI_MHL_8334
+ depends on FB_MSM_MDSS_HDMI_PANEL
+ bool 'MHL SII8334 support '
+ default n
+ ---help---
+ Support the HDMI to MHL conversion.
+ MHL (Mobile High-Definition Link) technology
+ uses USB connector to output HDMI content
diff --git a/drivers/video/msm/mdss/Makefile b/drivers/video/msm/mdss/Makefile
index b4bd31e..88a7c45 100644
--- a/drivers/video/msm/mdss/Makefile
+++ b/drivers/video/msm/mdss/Makefile
@@ -18,5 +18,6 @@
obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_tx.o
obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_util.o
obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_edid.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_MHL_8334) += mhl_sii8334.o
obj-$(CONFIG_FB_MSM_MDSS_WRITEBACK) += mdss_wb.o
diff --git a/drivers/video/msm/mdss/mdss_dsi.c b/drivers/video/msm/mdss/mdss_dsi.c
index 8f4f4d5..980ed46 100644
--- a/drivers/video/msm/mdss/mdss_dsi.c
+++ b/drivers/video/msm/mdss/mdss_dsi.c
@@ -327,6 +327,26 @@
return ret;
}
+static int mdss_dsi_event_handler(struct mdss_panel_data *pdata,
+ int event, void *arg)
+{
+ int rc = 0;
+
+ pr_debug("%s: event=%d\n", __func__, event);
+ switch (event) {
+ case MDSS_EVENT_UNBLANK:
+ rc = mdss_dsi_on(pdata);
+ break;
+ case MDSS_EVENT_BLANK:
+ rc = mdss_dsi_ctrl_unprepare(pdata);
+ break;
+ case MDSS_EVENT_TIMEGEN_OFF:
+ rc = mdss_dsi_off(pdata);
+ break;
+ }
+ return rc;
+}
+
static int mdss_dsi_resource_initialized;
static int __devinit mdss_dsi_probe(struct platform_device *pdev)
@@ -476,9 +496,7 @@
if (!ctrl_pdata)
return -ENOMEM;
- (ctrl_pdata->panel_data).on = mdss_dsi_on;
- (ctrl_pdata->panel_data).off = mdss_dsi_off;
- (ctrl_pdata->panel_data).intf_unprepare = mdss_dsi_ctrl_unprepare;
+ ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler;
memcpy(&((ctrl_pdata->panel_data).panel_info),
&(panel_data->panel_info),
sizeof(struct mdss_panel_info));
diff --git a/drivers/video/msm/mdss/mdss_edp.c b/drivers/video/msm/mdss/mdss_edp.c
index b35be75..1cf3101 100644
--- a/drivers/video/msm/mdss/mdss_edp.c
+++ b/drivers/video/msm/mdss/mdss_edp.c
@@ -153,7 +153,7 @@
if (ret) {
pr_err("%s: Request reset gpio_panel_en failed, ret=%d\n",
__func__, ret);
- goto gpio_free;
+ return ret;
}
ret = gpio_direction_output(edp_drv->gpio_panel_en, 1);
@@ -163,8 +163,6 @@
goto gpio_free;
}
- gpio_set_value(edp_drv->gpio_panel_en, 1);
-
return 0;
gpio_free:
@@ -212,13 +210,11 @@
if (ret) {
pr_err("%s: Request reset gpio_panel_pwm failed, ret=%d\n",
__func__, ret);
- goto edp_free_gpio_pwm;
+ goto edp_free_pwm;
}
return 0;
-edp_free_gpio_pwm:
- gpio_free(edp_drv->gpio_panel_pwm);
edp_free_pwm:
pwm_free(edp_drv->bl_pwm);
return -ENODEV;
@@ -323,6 +319,7 @@
mdss_edp_config_sw_div(edp_drv->edp_base);
mdss_edp_config_static_mdiv(edp_drv->edp_base);
mdss_edp_enable(edp_drv->edp_base, 1);
+ gpio_set_value(edp_drv->gpio_panel_en, 1);
return 0;
}
@@ -340,6 +337,7 @@
return -EINVAL;
}
+ gpio_set_value(edp_drv->gpio_panel_en, 0);
pwm_disable(edp_drv->bl_pwm);
mdss_edp_enable(edp_drv->edp_base, 0);
mdss_edp_unconfig_clk(edp_drv->edp_base, edp_drv->mmss_cc_base);
@@ -355,6 +353,23 @@
return ret;
}
+static int mdss_edp_event_handler(struct mdss_panel_data *pdata,
+ int event, void *arg)
+{
+ int rc = 0;
+
+ pr_debug("%s: event=%d\n", __func__, event);
+ switch (event) {
+ case MDSS_EVENT_UNBLANK:
+ rc = mdss_edp_on(pdata);
+ break;
+ case MDSS_EVENT_TIMEGEN_OFF:
+ rc = mdss_edp_off(pdata);
+ break;
+ }
+ return rc;
+}
+
/*
* Converts from EDID struct to mdss_panel_info
*/
@@ -415,8 +430,7 @@
edp_drv->panel_data.panel_info.bl_min = 1;
edp_drv->panel_data.panel_info.bl_max = 255;
- edp_drv->panel_data.on = mdss_edp_on;
- edp_drv->panel_data.off = mdss_edp_off;
+ edp_drv->panel_data.event_handler = mdss_edp_event_handler;
edp_drv->panel_data.set_backlight = mdss_edp_set_backlight;
ret = mdss_register_panel(&edp_drv->panel_data);
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index b711fd9..d0361e5 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -325,6 +325,24 @@
return 0;
}
+static inline int mdss_fb_send_panel_event(struct msm_fb_data_type *mfd, int e)
+{
+ struct mdss_panel_data *pdata;
+
+ pdata = dev_get_platdata(&mfd->pdev->dev);
+ if (!pdata) {
+ pr_err("no panel connected\n");
+ return -ENODEV;
+ }
+
+ pr_debug("sending event=%d for fb%d\n", e, mfd->index);
+
+ if (pdata->event_handler)
+ return pdata->event_handler(pdata, e, NULL);
+
+ return 0;
+}
+
static int mdss_fb_suspend_sub(struct msm_fb_data_type *mfd)
{
int ret = 0;
@@ -334,6 +352,12 @@
pr_debug("mdss_fb suspend index=%d\n", mfd->index);
+ ret = mdss_fb_send_panel_event(mfd, MDSS_EVENT_SUSPEND);
+ if (ret) {
+ pr_warn("unable to suspend fb%d (%d)\n", mfd->index, ret);
+ return ret;
+ }
+
mfd->suspend.op_enable = mfd->op_enable;
mfd->suspend.panel_power_on = mfd->panel_power_on;
@@ -359,6 +383,12 @@
pr_debug("mdss_fb resume index=%d\n", mfd->index);
+ ret = mdss_fb_send_panel_event(mfd, MDSS_EVENT_RESUME);
+ if (ret) {
+ pr_warn("unable to resume fb%d (%d)\n", mfd->index, ret);
+ return ret;
+ }
+
/* resume state var recover */
mfd->op_enable = mfd->suspend.op_enable;
diff --git a/drivers/video/msm/mdss/mdss_fb.h b/drivers/video/msm/mdss/mdss_fb.h
index 78f2b9a..b760388 100644
--- a/drivers/video/msm/mdss/mdss_fb.h
+++ b/drivers/video/msm/mdss/mdss_fb.h
@@ -93,6 +93,7 @@
u32 bl_scale;
u32 bl_min_lvl;
struct mutex lock;
+ struct mutex ov_lock;
struct platform_device *pdev;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.c b/drivers/video/msm/mdss/mdss_hdmi_tx.c
index c2d5f28..5d953c5 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.c
@@ -15,9 +15,11 @@
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mutex.h>
+#include <linux/iopoll.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>
#include <linux/types.h>
+#include <mach/msm_hdmi_audio.h>
#define REG_DUMP 0
@@ -36,12 +38,27 @@
#define SW_RESET BIT(2)
#define SW_RESET_PLL BIT(0)
+#define HPD_DISCONNECT_POLARITY 0
+#define HPD_CONNECT_POLARITY 1
+
#define IFRAME_CHECKSUM_32(d) \
((d & 0xff) + ((d >> 8) & 0xff) + \
((d >> 16) & 0xff) + ((d >> 24) & 0xff))
+/* parameters for clock regeneration */
+struct hdmi_tx_audio_acr {
+ u32 n;
+ u32 cts;
+};
+
+struct hdmi_tx_audio_acr_arry {
+ u32 pclk;
+ struct hdmi_tx_audio_acr lut[HDMI_SAMPLE_RATE_MAX];
+};
+
static int hdmi_tx_sysfs_enable_hpd(struct hdmi_tx_ctrl *hdmi_ctrl, int on);
static irqreturn_t hdmi_tx_isr(int irq, void *data);
+static void hdmi_tx_hpd_off(struct hdmi_tx_ctrl *hdmi_ctrl);
struct mdss_hw hdmi_tx_hw = {
.hw_ndx = MDSS_HW_HDMI,
@@ -90,6 +107,27 @@
0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/
};
+/* Audio constants lookup table for hdmi_tx_audio_acr_setup */
+/* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
+static const struct hdmi_tx_audio_acr_arry hdmi_tx_audio_acr_lut[] = {
+ /* 25.200MHz */
+ {25200, {{4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
+ {12288, 25200}, {25088, 28000}, {24576, 25200} } },
+ /* 27.000MHz */
+ {27000, {{4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
+ {12288, 27000}, {25088, 30000}, {24576, 27000} } },
+ /* 27.027MHz */
+ {27030, {{4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
+ {12288, 27027}, {25088, 30030}, {24576, 27027} } },
+ /* 74.250MHz */
+ {74250, {{4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
+ {12288, 74250}, {25088, 82500}, {24576, 74250} } },
+ /* 148.500MHz */
+ {148500, {{4096, 148500}, {6272, 165000}, {6144, 148500},
+ {12544, 165000}, {12288, 148500}, {25088, 165000},
+ {24576, 148500} } },
+};
+
const char *hdmi_tx_pm_name(enum hdmi_tx_power_module_type module)
{
switch (module) {
@@ -335,8 +373,8 @@
static inline u32 hdmi_tx_is_dvi_mode(struct hdmi_tx_ctrl *hdmi_ctrl)
{
- struct dss_io_data *io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
- return !(DSS_REG_R_ND(io, HDMI_CTRL) & BIT(1));
+ return hdmi_edid_get_sink_mode(
+ hdmi_ctrl->feature_data[HDMI_TX_FEAT_EDID]) ? 0 : 1;
} /* hdmi_tx_is_dvi_mode */
static int hdmi_tx_init_panel_info(uint32_t resolution,
@@ -424,86 +462,8 @@
return status;
} /* hdmi_tx_read_sink_info */
-static void hdmi_tx_hpd_state_work(struct work_struct *work)
-{
- u32 hpd_state = false;
- struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
- struct dss_io_data *io = NULL;
-
- hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, hpd_state_work);
- if (!hdmi_ctrl || !hdmi_ctrl->hpd_initialized) {
- DEV_DBG("%s: invalid input\n", __func__);
- return;
- }
-
- io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
- if (!io->base) {
- DEV_ERR("%s: Core io is not initialized\n", __func__);
- return;
- }
-
- DEV_DBG("%s: Got HPD interrupt\n", __func__);
-
- hpd_state = (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
- mutex_lock(&hdmi_ctrl->mutex);
- if ((hdmi_ctrl->hpd_prev_state != hdmi_ctrl->hpd_state) ||
- (hdmi_ctrl->hpd_state != hpd_state)) {
-
- hdmi_ctrl->hpd_state = hpd_state;
- hdmi_ctrl->hpd_prev_state = hdmi_ctrl->hpd_state;
- hdmi_ctrl->hpd_stable = 0;
-
- DEV_DBG("%s: state not stable yet, wait again (%d|%d|%d)\n",
- __func__, hdmi_ctrl->hpd_prev_state,
- hdmi_ctrl->hpd_state, hpd_state);
-
- mutex_unlock(&hdmi_ctrl->mutex);
-
- mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
-
- return;
- }
-
- if (hdmi_ctrl->hpd_stable) {
- mutex_unlock(&hdmi_ctrl->mutex);
- DEV_DBG("%s: no more timer, depending on IRQ now\n",
- __func__);
- return;
- }
-
- hdmi_ctrl->hpd_stable = 1;
-
- /*
- *todo: Revisit cable chg detected condition when HPD support is ready
- */
- hdmi_ctrl->hpd_cable_chg_detected = false;
- mutex_unlock(&hdmi_ctrl->mutex);
-
- if (hpd_state) {
- /* todo: what if EDID read fails? */
- hdmi_tx_read_sink_info(hdmi_ctrl);
- DEV_INFO("HDMI HPD: sense CONNECTED: send ONLINE\n");
- kobject_uevent(hdmi_ctrl->kobj, KOBJ_ONLINE);
- switch_set_state(&hdmi_ctrl->sdev, 1);
- DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
- hdmi_ctrl->sdev.state);
- } else {
- DEV_INFO("HDMI HPD: sense DISCONNECTED: send OFFLINE\n");
- kobject_uevent(hdmi_ctrl->kobj, KOBJ_OFFLINE);
- switch_set_state(&hdmi_ctrl->sdev, 0);
- DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
- hdmi_ctrl->sdev.state);
- }
-
- /* Set IRQ for HPD */
- DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hpd_state ? 0 : 2));
-} /* hdmi_tx_hpd_state_work */
-
static void hdmi_tx_hpd_int_work(struct work_struct *work)
{
- u32 hpd_int_status;
- u32 hpd_int_ctrl;
- u32 cable_detected;
struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
struct dss_io_data *io = NULL;
@@ -519,23 +479,24 @@
return;
}
- /* Process HPD Interrupt */
- hpd_int_status = DSS_REG_R(io, HDMI_HPD_INT_STATUS);
- hpd_int_ctrl = DSS_REG_R(io, HDMI_HPD_INT_CTRL);
+ DEV_DBG("%s: Got HPD interrupt\n", __func__);
- DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(2));
-
- cable_detected = hpd_int_status & BIT(1);
- mutex_lock(&hdmi_ctrl->mutex);
- hdmi_ctrl->hpd_cable_chg_detected = true;
- hdmi_ctrl->hpd_prev_state = cable_detected ? 0 : 1;
- hdmi_ctrl->hpd_stable = 0;
- mutex_unlock(&hdmi_ctrl->mutex);
-
- mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
-
- DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>\n", __func__, hpd_int_ctrl,
- hpd_int_status);
+ hdmi_ctrl->hpd_state =
+ (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
+ if (hdmi_ctrl->hpd_state) {
+ hdmi_tx_read_sink_info(hdmi_ctrl);
+ DEV_INFO("HDMI HPD: sense CONNECTED: send ONLINE\n");
+ kobject_uevent(hdmi_ctrl->kobj, KOBJ_ONLINE);
+ switch_set_state(&hdmi_ctrl->sdev, 1);
+ DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
+ hdmi_ctrl->sdev.state);
+ } else {
+ DEV_INFO("HDMI HPD: sense DISCONNECTED: send OFFLINE\n");
+ kobject_uevent(hdmi_ctrl->kobj, KOBJ_OFFLINE);
+ switch_set_state(&hdmi_ctrl->sdev, 0);
+ DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
+ hdmi_ctrl->sdev.state);
+ }
} /* hdmi_tx_hpd_int_work */
static int hdmi_tx_check_capability(struct dss_io_data *io)
@@ -976,17 +937,6 @@
DSS_REG_W(io, HDMI_GEN_PKT_CTRL, packet_control);
} /* hdmi_tx_set_spd_infoframe */
-/* todo: revisit when new HPD debouncing logic is avialble */
-static void hdmi_tx_hpd_state_timer(unsigned long data)
-{
- struct hdmi_tx_ctrl *hdmi_ctrl = (struct hdmi_tx_ctrl *)data;
-
- if (hdmi_ctrl)
- queue_work(hdmi_ctrl->workq, &hdmi_ctrl->hpd_state_work);
- else
- DEV_ERR("%s: invalid input\n", __func__);
-} /* hdmi_tx_hpd_state_timer */
-
static void hdmi_tx_set_mode(struct hdmi_tx_ctrl *hdmi_ctrl, u32 power_on)
{
u32 reg_val = 0;
@@ -1133,6 +1083,8 @@
} else {
msm_dss_enable_clk(power_data->clk_config,
power_data->num_clk, 0);
+ msm_dss_clk_set_rate(power_data->clk_config,
+ power_data->num_clk);
msm_dss_enable_gpio(power_data->gpio_config,
power_data->num_gpio, 0);
msm_dss_enable_vreg(power_data->vreg_config,
@@ -1275,6 +1227,346 @@
DSS_REG_W_ND(io, HDMI_PHY_PD_CTRL0, 0x7F);
} /* hdmi_tx_powerdown_phy */
+static int hdmi_tx_audio_acr_setup(struct hdmi_tx_ctrl *hdmi_ctrl,
+ bool enabled, int num_of_channels)
+{
+ /* Read first before writing */
+ u32 acr_pck_ctrl_reg;
+ struct dss_io_data *io = NULL;
+
+ if (!hdmi_ctrl) {
+ DEV_ERR("%s: Invalid input\n", __func__);
+ return -EINVAL;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io not inititalized\n", __func__);
+ return -EINVAL;
+ }
+
+ acr_pck_ctrl_reg = DSS_REG_R(io, HDMI_ACR_PKT_CTRL);
+
+ if (enabled) {
+ const struct hdmi_disp_mode_timing_type *timing =
+ hdmi_get_supported_mode(hdmi_ctrl->video_resolution);
+ const struct hdmi_tx_audio_acr_arry *audio_acr =
+ &hdmi_tx_audio_acr_lut[0];
+ const int lut_size = sizeof(hdmi_tx_audio_acr_lut)
+ / sizeof(*hdmi_tx_audio_acr_lut);
+ u32 i, n, cts, layout, multiplier, aud_pck_ctrl_2_reg;
+
+ if (timing == NULL) {
+ DEV_WARN("%s: video format %d not supported\n",
+ __func__, hdmi_ctrl->video_resolution);
+ return -EPERM;
+ }
+
+ for (i = 0; i < lut_size;
+ audio_acr = &hdmi_tx_audio_acr_lut[++i]) {
+ if (audio_acr->pclk == timing->pixel_freq)
+ break;
+ }
+ if (i >= lut_size) {
+ DEV_WARN("%s: pixel clk %d not supported\n", __func__,
+ timing->pixel_freq);
+ return -EPERM;
+ }
+
+ n = audio_acr->lut[hdmi_ctrl->audio_sample_rate].n;
+ cts = audio_acr->lut[hdmi_ctrl->audio_sample_rate].cts;
+ layout = (MSM_HDMI_AUDIO_CHANNEL_2 == num_of_channels) ? 0 : 1;
+
+ if (
+ (HDMI_SAMPLE_RATE_192KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_176_4KHZ == hdmi_ctrl->audio_sample_rate)) {
+ multiplier = 4;
+ n >>= 2; /* divide N by 4 and use multiplier */
+ } else if (
+ (HDMI_SAMPLE_RATE_96KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_88_2KHZ == hdmi_ctrl->audio_sample_rate)) {
+ multiplier = 2;
+ n >>= 1; /* divide N by 2 and use multiplier */
+ } else {
+ multiplier = 1;
+ }
+ DEV_DBG("%s: n=%u, cts=%u, layout=%u\n", __func__, n, cts,
+ layout);
+
+ /* AUDIO_PRIORITY | SOURCE */
+ acr_pck_ctrl_reg |= 0x80000100;
+ /* N_MULTIPLE(multiplier) */
+ acr_pck_ctrl_reg |= (multiplier & 7) << 16;
+
+ if ((HDMI_SAMPLE_RATE_48KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_96KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_192KHZ == hdmi_ctrl->audio_sample_rate)) {
+ /* SELECT(3) */
+ acr_pck_ctrl_reg |= 3 << 4;
+ /* CTS_48 */
+ cts <<= 12;
+
+ /* CTS: need to determine how many fractional bits */
+ DSS_REG_W(io, HDMI_ACR_48_0, cts);
+ /* N */
+ DSS_REG_W(io, HDMI_ACR_48_1, n);
+ } else if (
+ (HDMI_SAMPLE_RATE_44_1KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_88_2KHZ == hdmi_ctrl->audio_sample_rate) ||
+ (HDMI_SAMPLE_RATE_176_4KHZ == hdmi_ctrl->audio_sample_rate)) {
+ /* SELECT(2) */
+ acr_pck_ctrl_reg |= 2 << 4;
+ /* CTS_44 */
+ cts <<= 12;
+
+ /* CTS: need to determine how many fractional bits */
+ DSS_REG_W(io, HDMI_ACR_44_0, cts);
+ /* N */
+ DSS_REG_W(io, HDMI_ACR_44_1, n);
+ } else { /* default to 32k */
+ /* SELECT(1) */
+ acr_pck_ctrl_reg |= 1 << 4;
+ /* CTS_32 */
+ cts <<= 12;
+
+ /* CTS: need to determine how many fractional bits */
+ DSS_REG_W(io, HDMI_ACR_32_0, cts);
+ /* N */
+ DSS_REG_W(io, HDMI_ACR_32_1, n);
+ }
+ /* Payload layout depends on number of audio channels */
+ /* LAYOUT_SEL(layout) */
+ aud_pck_ctrl_2_reg = 1 | (layout << 1);
+ /* override | layout */
+ DSS_REG_W(io, HDMI_AUDIO_PKT_CTRL2, aud_pck_ctrl_2_reg);
+
+ /* SEND | CONT */
+ acr_pck_ctrl_reg |= 0x00000003;
+ } else {
+ /* ~(SEND | CONT) */
+ acr_pck_ctrl_reg &= ~0x00000003;
+ }
+ DSS_REG_W(io, HDMI_ACR_PKT_CTRL, acr_pck_ctrl_reg);
+
+ return 0;
+} /* hdmi_tx_audio_acr_setup */
+
+static int hdmi_tx_audio_info_setup(void *priv_d, bool enabled,
+ u32 num_of_channels, u32 channel_allocation, u32 level_shift,
+ bool down_mix)
+{
+ struct hdmi_tx_ctrl *hdmi_ctrl = (struct hdmi_tx_ctrl *)priv_d;
+ struct dss_io_data *io = NULL;
+
+ u32 channel_count = 1; /* Def to 2 channels -> Table 17 in CEA-D */
+ u32 check_sum, audio_info_0_reg, audio_info_1_reg;
+ u32 audio_info_ctrl_reg;
+ u32 aud_pck_ctrl_2_reg;
+ u32 layout;
+
+ if (!hdmi_ctrl) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ return -EINVAL;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io not inititalized\n", __func__);
+ return -EINVAL;
+ }
+
+ layout = (MSM_HDMI_AUDIO_CHANNEL_2 == num_of_channels) ? 0 : 1;
+ aud_pck_ctrl_2_reg = 1 | (layout << 1);
+ DSS_REG_W(io, HDMI_AUDIO_PKT_CTRL2, aud_pck_ctrl_2_reg);
+
+ /*
+ * Please see table 20 Audio InfoFrame in HDMI spec
+ * FL = front left
+ * FC = front Center
+ * FR = front right
+ * FLC = front left center
+ * FRC = front right center
+ * RL = rear left
+ * RC = rear center
+ * RR = rear right
+ * RLC = rear left center
+ * RRC = rear right center
+ * LFE = low frequency effect
+ */
+
+ /* Read first then write because it is bundled with other controls */
+ audio_info_ctrl_reg = DSS_REG_R(io, HDMI_INFOFRAME_CTRL0);
+
+ if (enabled) {
+ switch (num_of_channels) {
+ case MSM_HDMI_AUDIO_CHANNEL_2:
+ channel_allocation = 0; /* Default to FR, FL */
+ break;
+ case MSM_HDMI_AUDIO_CHANNEL_4:
+ channel_count = 3;
+ /* FC, LFE, FR, FL */
+ channel_allocation = 0x3;
+ break;
+ case MSM_HDMI_AUDIO_CHANNEL_6:
+ channel_count = 5;
+ /* RR, RL, FC, LFE, FR, FL */
+ channel_allocation = 0xB;
+ break;
+ case MSM_HDMI_AUDIO_CHANNEL_8:
+ channel_count = 7;
+ /* FRC, FLC, RR, RL, FC, LFE, FR, FL */
+ channel_allocation = 0x1f;
+ break;
+ default:
+ DEV_ERR("%s: Unsupported num_of_channels = %u\n",
+ __func__, num_of_channels);
+ return -EINVAL;
+ }
+
+ /* Program the Channel-Speaker allocation */
+ audio_info_1_reg = 0;
+ /* CA(channel_allocation) */
+ audio_info_1_reg |= channel_allocation & 0xff;
+ /* Program the Level shifter */
+ audio_info_1_reg |= (level_shift << 11) & 0x00007800;
+ /* Program the Down-mix Inhibit Flag */
+ audio_info_1_reg |= (down_mix << 15) & 0x00008000;
+
+ DSS_REG_W(io, HDMI_AUDIO_INFO1, audio_info_1_reg);
+
+ /*
+ * Calculate CheckSum: Sum of all the bytes in the
+ * Audio Info Packet (See table 8.4 in HDMI spec)
+ */
+ check_sum = 0;
+ /* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_TYPE[0x84] */
+ check_sum += 0x84;
+ /* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_VERSION[0x01] */
+ check_sum += 1;
+ /* HDMI_AUDIO_INFO_FRAME_PACKET_LENGTH[0x0A] */
+ check_sum += 0x0A;
+ check_sum += channel_count;
+ check_sum += channel_allocation;
+ /* See Table 8.5 in HDMI spec */
+ check_sum += (level_shift & 0xF) << 3 | (down_mix & 0x1) << 7;
+ check_sum &= 0xFF;
+ check_sum = (u8) (256 - check_sum);
+
+ audio_info_0_reg = 0;
+ /* CHECKSUM(check_sum) */
+ audio_info_0_reg |= check_sum & 0xff;
+ /* CC(channel_count) */
+ audio_info_0_reg |= (channel_count << 8) & 0x00000700;
+
+ DSS_REG_W(io, HDMI_AUDIO_INFO0, audio_info_0_reg);
+
+ /*
+ * Set these flags
+ * AUDIO_INFO_UPDATE |
+ * AUDIO_INFO_SOURCE |
+ * AUDIO_INFO_CONT |
+ * AUDIO_INFO_SEND
+ */
+ audio_info_ctrl_reg |= 0x000000F0;
+ } else {
+ /*Clear these flags
+ * ~(AUDIO_INFO_UPDATE |
+ * AUDIO_INFO_SOURCE |
+ * AUDIO_INFO_CONT |
+ * AUDIO_INFO_SEND)
+ */
+ audio_info_ctrl_reg &= ~0x000000F0;
+ }
+ DSS_REG_W(io, HDMI_INFOFRAME_CTRL0, audio_info_ctrl_reg);
+
+ dss_reg_dump(io->base, io->len,
+ enabled ? "HDMI-AUDIO-ON: " : "HDMI-AUDIO-OFF: ", REG_DUMP);
+
+ return 0;
+} /* hdmi_tx_audio_info_setup */
+
+static int hdmi_tx_audio_setup(struct hdmi_tx_ctrl *hdmi_ctrl)
+{
+ int rc = 0;
+ const int channels = MSM_HDMI_AUDIO_CHANNEL_2;
+ struct dss_io_data *io = NULL;
+
+ if (!hdmi_ctrl) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ return -EINVAL;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io not inititalized\n", __func__);
+ return -EINVAL;
+ }
+
+ rc = hdmi_tx_audio_acr_setup(hdmi_ctrl, true, channels);
+ if (rc) {
+ DEV_ERR("%s: hdmi_tx_audio_acr_setup failed. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ rc = hdmi_tx_audio_info_setup(hdmi_ctrl, true, channels, 0, 0, false);
+ if (rc) {
+ DEV_ERR("%s: hdmi_tx_audio_info_setup failed. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ DEV_INFO("HDMI Audio: Enabled\n");
+
+ return 0;
+} /* hdmi_tx_audio_setup */
+
+static void hdmi_tx_audio_off(struct hdmi_tx_ctrl *hdmi_ctrl)
+{
+ u32 i, status, max_reads, timeout_us, timeout_sec = 15;
+ struct dss_io_data *io = NULL;
+
+ if (!hdmi_ctrl) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ return;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io not inititalized\n", __func__);
+ return;
+ }
+
+ /* Check if audio engine is turned off by QDSP or not */
+ /* send off notification after every 1 sec for 15 seconds */
+ for (i = 0; i < timeout_sec; i++) {
+ max_reads = 500;
+ timeout_us = 1000 * 2;
+
+ if (readl_poll_timeout_noirq((io->base + HDMI_AUDIO_CFG),
+ status, ((status & BIT(0)) == 0),
+ max_reads, timeout_us)) {
+
+ DEV_ERR("%s: audio still on after %d sec. try again\n",
+ __func__, i+1);
+
+ switch_set_state(&hdmi_ctrl->audio_sdev, 0);
+ continue;
+ }
+ break;
+ }
+ if (i == timeout_sec)
+ DEV_ERR("%s: Error: cannot turn off audio engine\n", __func__);
+
+ if (hdmi_tx_audio_info_setup(hdmi_ctrl, false, 0, 0, 0, false))
+ DEV_ERR("%s: hdmi_tx_audio_info_setup failed.\n", __func__);
+
+ if (hdmi_tx_audio_acr_setup(hdmi_ctrl, false, 0))
+ DEV_ERR("%s: hdmi_tx_audio_acr_setup failed.\n", __func__);
+
+ DEV_INFO("HDMI Audio: Disabled\n");
+} /* hdmi_tx_audio_off */
+
static int hdmi_tx_start(struct hdmi_tx_ctrl *hdmi_ctrl)
{
int rc = 0;
@@ -1290,8 +1582,6 @@
return -EINVAL;
}
- /* todo: Audio */
-
hdmi_tx_set_mode(hdmi_ctrl, false);
hdmi_tx_init_phy(hdmi_ctrl);
DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
@@ -1299,14 +1589,25 @@
hdmi_tx_set_mode(hdmi_ctrl, true);
hdmi_tx_video_setup(hdmi_ctrl, hdmi_ctrl->video_resolution);
- /* todo: Audio */
+
+ if (!hdmi_tx_is_dvi_mode(hdmi_ctrl)) {
+ rc = hdmi_tx_audio_setup(hdmi_ctrl);
+ if (rc) {
+ DEV_ERR("%s: hdmi_msm_audio_setup failed. rc=%d\n",
+ __func__, rc);
+ hdmi_tx_set_mode(hdmi_ctrl, false);
+ return rc;
+ }
+
+ switch_set_state(&hdmi_ctrl->audio_sdev, 1);
+ DEV_INFO("%s: hdmi_audio state switch to %d\n", __func__,
+ hdmi_ctrl->audio_sdev.state);
+ }
+
hdmi_tx_set_avi_infoframe(hdmi_ctrl);
/* todo: CONFIG_FB_MSM_HDMI_3D */
hdmi_tx_set_spd_infoframe(hdmi_ctrl);
- /* Set IRQ for HPD */
- DSS_REG_W(io, HDMI_HPD_INT_CTRL, 4 | (hdmi_ctrl->hpd_state ? 0 : 2));
-
/* todo: HDCP/CEC */
DEV_INFO("%s: HDMI Core: Initialized\n", __func__);
@@ -1314,21 +1615,107 @@
return rc;
} /* hdmi_tx_start */
+static void hdmi_tx_hpd_polarity_setup(struct hdmi_tx_ctrl *hdmi_ctrl,
+ bool polarity)
+{
+ struct dss_io_data *io = NULL;
+ u32 cable_sense;
+
+ if (!hdmi_ctrl) {
+ DEV_ERR("%s: invalid input\n", __func__);
+ return;
+ }
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: core io is not initialized\n", __func__);
+ return;
+ }
+
+ if (polarity)
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(2) | BIT(1));
+ else
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(2));
+
+ cable_sense = (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(1)) >> 1;
+ DEV_DBG("%s: listen = %s, sense = %s\n", __func__,
+ polarity ? "connect" : "disconnect",
+ cable_sense ? "connect" : "disconnect");
+
+ if (cable_sense == polarity) {
+ u32 reg_val = DSS_REG_R(io, HDMI_HPD_CTRL);
+
+ /* Toggle HPD circuit to trigger HPD sense */
+ DSS_REG_W(io, HDMI_HPD_CTRL, reg_val & ~BIT(28));
+ DSS_REG_W(io, HDMI_HPD_CTRL, reg_val | BIT(28));
+ }
+} /* hdmi_tx_hpd_polarity_setup */
+
+static void hdmi_tx_power_off_work(struct work_struct *work)
+{
+ struct hdmi_tx_ctrl *hdmi_ctrl = NULL;
+ struct dss_io_data *io = NULL;
+
+ hdmi_ctrl = container_of(work, struct hdmi_tx_ctrl, power_off_work);
+ if (!hdmi_ctrl) {
+ DEV_DBG("%s: invalid input\n", __func__);
+ return;
+ }
+
+ io = &hdmi_ctrl->pdata.io[HDMI_TX_CORE_IO];
+ if (!io->base) {
+ DEV_ERR("%s: Core io is not initialized\n", __func__);
+ return;
+ }
+
+ if (!hdmi_tx_is_dvi_mode(hdmi_ctrl)) {
+ switch_set_state(&hdmi_ctrl->audio_sdev, 0);
+ DEV_INFO("%s: hdmi_audio state switch to %d\n", __func__,
+ hdmi_ctrl->audio_sdev.state);
+
+ hdmi_tx_audio_off(hdmi_ctrl);
+ }
+
+ hdmi_tx_powerdown_phy(hdmi_ctrl);
+
+ /*
+ * this is needed to avoid pll lock failure due to
+ * clk framework's rate caching.
+ */
+ hdmi_ctrl->pdata.power_data[HDMI_TX_CORE_PM].clk_config[0].rate = 0;
+
+ hdmi_tx_core_off(hdmi_ctrl);
+
+ mutex_lock(&hdmi_ctrl->mutex);
+ hdmi_ctrl->panel_power_on = false;
+ mutex_unlock(&hdmi_ctrl->mutex);
+
+ if (hdmi_ctrl->hpd_off_pending) {
+ hdmi_tx_hpd_off(hdmi_ctrl);
+ hdmi_ctrl->hpd_off_pending = false;
+ } else {
+ hdmi_tx_hpd_polarity_setup(hdmi_ctrl, HPD_CONNECT_POLARITY);
+ }
+
+ DEV_INFO("%s: HDMI Core: OFF\n", __func__);
+} /* hdmi_tx_power_off_work */
+
static int hdmi_tx_power_off(struct mdss_panel_data *panel_data)
{
struct hdmi_tx_ctrl *hdmi_ctrl =
hdmi_tx_get_drvdata_from_panel_data(panel_data);
- if (!hdmi_ctrl) {
+ if (!hdmi_ctrl || !hdmi_ctrl->panel_power_on) {
DEV_ERR("%s: invalid input\n", __func__);
return -EINVAL;
}
- DEV_INFO("%s: power: OFF (audio off, Reset Core)\n", __func__);
- /* todo: Audio */
- hdmi_tx_powerdown_phy(hdmi_ctrl);
- hdmi_ctrl->panel_power_on = false;
- hdmi_tx_core_off(hdmi_ctrl);
+ /*
+ * Queue work item to handle power down sequence.
+ * This is needed since we need to wait for the audio engine
+ * to shutdown first before we shutdown the HDMI core.
+ */
+ DEV_DBG("%s: Queuing work to power off HDMI core\n", __func__);
+ queue_work(hdmi_ctrl->workq, &hdmi_ctrl->power_off_work);
return 0;
} /* hdmi_tx_power_off */
@@ -1350,6 +1737,15 @@
return -EINVAL;
}
+ if (!hdmi_ctrl->hpd_initialized) {
+ DEV_ERR("%s: HDMI on is not possible w/o cable detection.\n",
+ __func__);
+ return -EPERM;
+ }
+
+ /* If a power down is already underway, wait for it to finish */
+ flush_work_sync(&hdmi_ctrl->power_off_work);
+
DEV_INFO("power: ON (%dx%d %ld)\n", hdmi_ctrl->xres, hdmi_ctrl->yres,
hdmi_ctrl->pixel_clk);
@@ -1390,6 +1786,8 @@
hdmi_tx_is_controller_on(hdmi_ctrl) ? "ON" : "OFF" ,
hdmi_tx_is_dvi_mode(hdmi_ctrl) ? "ON" : "OFF");
+ hdmi_tx_hpd_polarity_setup(hdmi_ctrl, HPD_DISCONNECT_POLARITY);
+
return 0;
} /* hdmi_tx_power_on */
@@ -1407,8 +1805,6 @@
return;
}
- DEV_DBG("%s: (timer, 5V, IRQ off)\n", __func__);
- del_timer_sync(&hdmi_ctrl->hpd_state_timer);
mdss_disable_irq(&hdmi_tx_hw);
hdmi_tx_set_mode(hdmi_ctrl, false);
@@ -1456,28 +1852,18 @@
DSS_REG_W(io, HDMI_USEC_REFTIMER, 0x0001001B);
- /* set timeout to 4.1ms (max) for hardware debounce */
- reg_val = DSS_REG_R(io, HDMI_HPD_CTRL) | 0x1FFF;
-
- /* Toggle HPD circuit to trigger HPD sense */
- DSS_REG_W(io, HDMI_HPD_CTRL,
- ~(1 << 28) & reg_val);
- DSS_REG_W(io, HDMI_HPD_CTRL, (1 << 28) | reg_val);
+ mdss_enable_irq(&hdmi_tx_hw);
hdmi_ctrl->hpd_initialized = true;
- /* Check HPD State */
- mdss_enable_irq(&hdmi_tx_hw);
- }
+ /* set timeout to 4.1ms (max) for hardware debounce */
+ reg_val = DSS_REG_R(io, HDMI_HPD_CTRL) | 0x1FFF;
- /* Set HPD state machine: ensure at least 2 readouts */
- mutex_lock(&hdmi_ctrl->mutex);
- hdmi_ctrl->hpd_stable = 0;
- hdmi_ctrl->hpd_prev_state = true;
- hdmi_ctrl->hpd_state = false;
- hdmi_ctrl->hpd_cable_chg_detected = true;
- mutex_unlock(&hdmi_ctrl->mutex);
- mod_timer(&hdmi_ctrl->hpd_state_timer, jiffies + HZ/2);
+ /* Turn on HPD HW circuit */
+ DSS_REG_W(io, HDMI_HPD_CTRL, reg_val | BIT(28));
+
+ hdmi_tx_hpd_polarity_setup(hdmi_ctrl, HPD_CONNECT_POLARITY);
+ }
return rc;
} /* hdmi_tx_hpd_on */
@@ -1495,10 +1881,20 @@
if (on) {
rc = hdmi_tx_hpd_on(hdmi_ctrl);
} else {
- hdmi_tx_hpd_off(hdmi_ctrl);
- switch_set_state(&hdmi_ctrl->sdev, 0);
- DEV_INFO("%s: Hdmi state switch to %d\n", __func__,
- hdmi_ctrl->sdev.state);
+ /* If power down is already underway, wait for it to finish */
+ flush_work_sync(&hdmi_ctrl->power_off_work);
+
+ if (!hdmi_ctrl->panel_power_on) {
+ hdmi_tx_hpd_off(hdmi_ctrl);
+ } else {
+ hdmi_ctrl->hpd_off_pending = true;
+
+ switch_set_state(&hdmi_ctrl->sdev, 0);
+ DEV_DBG("%s: Hdmi state switch to %d\n", __func__,
+ hdmi_ctrl->sdev.state);
+ DEV_DBG("HDMI HPD: sent fake OFFLINE event\n");
+ kobject_uevent(hdmi_ctrl->kobj, KOBJ_OFFLINE);
+ }
}
return rc;
@@ -1523,10 +1919,10 @@
if (DSS_REG_R(io, HDMI_HPD_INT_STATUS) & BIT(0)) {
/*
- * Turn off HPD irq and clear all interrupts,
- * worker will turn IRQ back on
+ * Ack the current hpd interrupt and stop listening to
+ * new hpd interrupt.
*/
- DSS_REG_W(io, HDMI_HPD_INT_CTRL, ~BIT(2) | BIT(0));
+ DSS_REG_W(io, HDMI_HPD_INT_CTRL, BIT(0));
queue_work(hdmi_ctrl->workq, &hdmi_ctrl->hpd_int_work);
}
@@ -1546,8 +1942,8 @@
if (hdmi_ctrl->feature_data[HDMI_TX_FEAT_EDID])
hdmi_edid_deinit(hdmi_ctrl->feature_data[HDMI_TX_FEAT_EDID]);
+ switch_dev_unregister(&hdmi_ctrl->audio_sdev);
switch_dev_unregister(&hdmi_ctrl->sdev);
- del_timer_sync(&hdmi_ctrl->hpd_state_timer);
if (hdmi_ctrl->workq)
destroy_workqueue(hdmi_ctrl->workq);
mutex_destroy(&hdmi_ctrl->mutex);
@@ -1581,29 +1977,41 @@
hdmi_ctrl->workq = create_workqueue("hdmi_tx_workq");
if (!hdmi_ctrl->workq) {
DEV_ERR("%s: hdmi_tx_workq creation failed.\n", __func__);
+ rc = -EPERM;
goto fail_create_workq;
}
hdmi_ctrl->ddc_ctrl.io = &pdata->io[HDMI_TX_CORE_IO];
init_completion(&hdmi_ctrl->ddc_ctrl.ddc_sw_done);
- INIT_WORK(&hdmi_ctrl->hpd_state_work, hdmi_tx_hpd_state_work);
+ hdmi_ctrl->hpd_state = false;
+ hdmi_ctrl->hpd_initialized = false;
+ hdmi_ctrl->hpd_off_pending = false;
INIT_WORK(&hdmi_ctrl->hpd_int_work, hdmi_tx_hpd_int_work);
- init_timer(&hdmi_ctrl->hpd_state_timer);
- hdmi_ctrl->hpd_state_timer.function = hdmi_tx_hpd_state_timer;
- hdmi_ctrl->hpd_state_timer.data = (u32)hdmi_ctrl;
- hdmi_ctrl->hpd_state_timer.expires = 0xffffffffL;
+
+ INIT_WORK(&hdmi_ctrl->power_off_work, hdmi_tx_power_off_work);
+
+ hdmi_ctrl->audio_sample_rate = HDMI_SAMPLE_RATE_48KHZ;
hdmi_ctrl->sdev.name = "hdmi";
if (switch_dev_register(&hdmi_ctrl->sdev) < 0) {
DEV_ERR("%s: Hdmi switch registration failed\n", __func__);
- goto fail_switch_dev;
+ rc = -ENODEV;
+ goto fail_create_workq;
+ }
+
+ hdmi_ctrl->audio_sdev.name = "hdmi_audio";
+ if (switch_dev_register(&hdmi_ctrl->audio_sdev) < 0) {
+ DEV_ERR("%s: hdmi_audio switch registration failed\n",
+ __func__);
+ rc = -ENODEV;
+ goto fail_audio_switch_dev;
}
return 0;
-fail_switch_dev:
- del_timer_sync(&hdmi_ctrl->hpd_state_timer);
+fail_audio_switch_dev:
+ switch_dev_unregister(&hdmi_ctrl->sdev);
fail_create_workq:
if (hdmi_ctrl->workq)
destroy_workqueue(hdmi_ctrl->workq);
@@ -1612,6 +2020,21 @@
return rc;
} /* hdmi_tx_dev_init */
+static int hdmi_tx_event_handler(struct mdss_panel_data *panel_data,
+ int event, void *arg)
+{
+ int rc = 0;
+ switch (event) {
+ case MDSS_EVENT_UNBLANK:
+ rc = hdmi_tx_power_on(panel_data);
+ break;
+ case MDSS_EVENT_TIMEGEN_OFF:
+ rc = hdmi_tx_power_off(panel_data);
+ break;
+ }
+ return rc;
+}
+
static int hdmi_tx_register_panel(struct hdmi_tx_ctrl *hdmi_ctrl)
{
int rc = 0;
@@ -1621,8 +2044,7 @@
return -EINVAL;
}
- hdmi_ctrl->panel_data.on = hdmi_tx_power_on;
- hdmi_ctrl->panel_data.off = hdmi_tx_power_off;
+ hdmi_ctrl->panel_data.event_handler = hdmi_tx_event_handler;
hdmi_ctrl->video_resolution = DEFAULT_VIDEO_RESOLUTION;
rc = hdmi_tx_init_panel_info(hdmi_ctrl->video_resolution,
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.h b/drivers/video/msm/mdss/mdss_hdmi_tx.h
index 94e0fda..ce19355 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.h
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.h
@@ -41,23 +41,24 @@
struct hdmi_tx_platform_data pdata;
struct mdss_panel_data panel_data;
+ int audio_sample_rate;
+
struct mutex mutex;
struct kobject *kobj;
struct switch_dev sdev;
+ struct switch_dev audio_sdev;
struct workqueue_struct *workq;
uint32_t video_resolution;
u32 panel_power_on;
u32 hpd_initialized;
- int hpd_stable;
- u32 hpd_prev_state;
- u32 hpd_cable_chg_detected;
u32 hpd_state;
+ u32 hpd_off_pending;
u32 hpd_feature_on;
- struct work_struct hpd_state_work;
struct work_struct hpd_int_work;
- struct timer_list hpd_state_timer;
+
+ struct work_struct power_off_work;
unsigned long pixel_clk;
u32 xres;
diff --git a/drivers/video/msm/mdss/mdss_io_util.c b/drivers/video/msm/mdss/mdss_io_util.c
index 5778525..d7c19b4 100644
--- a/drivers/video/msm/mdss/mdss_io_util.c
+++ b/drivers/video/msm/mdss/mdss_io_util.c
@@ -15,6 +15,7 @@
#include <linux/io.h>
#include "mdss_io_util.h"
+#define MAX_I2C_CMDS 16
void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug)
{
u32 in_val;
@@ -136,7 +137,7 @@
curr_vreg = &in_vreg[i];
curr_vreg->vreg = regulator_get(dev,
curr_vreg->vreg_name);
- rc = IS_ERR(curr_vreg->vreg);
+ rc = PTR_RET(curr_vreg->vreg);
if (rc) {
DEV_ERR("%pS->%s: %s get failed. rc=%d\n",
__builtin_return_address(0), __func__,
@@ -215,7 +216,7 @@
int i = 0, rc = 0;
if (enable) {
for (i = 0; i < num_vreg; i++) {
- rc = IS_ERR(in_vreg[i].vreg);
+ rc = PTR_RET(in_vreg[i].vreg);
if (rc) {
DEV_ERR("%pS->%s: %s regulator error. rc=%d\n",
__builtin_return_address(0), __func__,
@@ -286,7 +287,7 @@
for (i = 0; i < num_clk; i++) {
clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name);
- rc = IS_ERR(clk_arry[i].clk);
+ rc = PTR_RET(clk_arry[i].clk);
if (rc) {
DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n",
__builtin_return_address(0), __func__,
@@ -382,3 +383,59 @@
return rc;
} /* msm_dss_enable_clk */
+
+
+int mdss_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
+ uint8_t reg_offset, uint8_t *read_buf)
+{
+ struct i2c_msg msgs[2];
+ int ret = -1;
+
+ pr_debug("%s: reading from slave_addr=[%x] and offset=[%x]\n",
+ __func__, slave_addr, reg_offset);
+
+ msgs[0].addr = slave_addr >> 1;
+ msgs[0].flags = 0;
+ msgs[0].buf = ®_offset;
+ msgs[0].len = 1;
+
+ msgs[1].addr = slave_addr >> 1;
+ msgs[1].flags = I2C_M_RD;
+ msgs[1].buf = read_buf;
+ msgs[1].len = 1;
+
+ ret = i2c_transfer(client->adapter, msgs, 2);
+ if (ret < 1) {
+ pr_err("%s: I2C READ FAILED=[%d]\n", __func__, ret);
+ return -EACCES;
+ }
+ pr_debug("%s: i2c buf is [%x]\n", __func__, *read_buf);
+ return 0;
+}
+
+int mdss_i2c_byte_write(struct i2c_client *client, uint8_t slave_addr,
+ uint8_t reg_offset, uint8_t *value)
+{
+ struct i2c_msg msgs[1];
+ uint8_t data[2];
+ int status = -EACCES;
+
+ pr_debug("%s: writing from slave_addr=[%x] and offset=[%x]\n",
+ __func__, slave_addr, reg_offset);
+
+ data[0] = reg_offset;
+ data[1] = *value;
+
+ msgs[0].addr = slave_addr >> 1;
+ msgs[0].flags = 0;
+ msgs[0].len = 2;
+ msgs[0].buf = data;
+
+ status = i2c_transfer(client->adapter, msgs, 1);
+ if (status < 1) {
+ pr_err("I2C WRITE FAILED=[%d]\n", status);
+ return -EACCES;
+ }
+ pr_debug("%s: I2C write status=%x\n", __func__, status);
+ return status;
+}
diff --git a/drivers/video/msm/mdss/mdss_io_util.h b/drivers/video/msm/mdss/mdss_io_util.h
index 51e9e54..9d78d70 100644
--- a/drivers/video/msm/mdss/mdss_io_util.h
+++ b/drivers/video/msm/mdss/mdss_io_util.h
@@ -16,6 +16,8 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
#ifdef DEBUG
#define DEV_DBG(fmt, args...) pr_err(fmt, ##args)
@@ -97,4 +99,9 @@
int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
+int mdss_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
+ uint8_t reg_offset, uint8_t *read_buf);
+int mdss_i2c_byte_write(struct i2c_client *client, uint8_t slave_addr,
+ uint8_t reg_offset, uint8_t *value);
+
#endif /* __MDSS_IO_UTIL_H__ */
diff --git a/drivers/video/msm/mdss/mdss_mdp.c b/drivers/video/msm/mdss/mdss_mdp.c
index c2d107a..11b0831 100644
--- a/drivers/video/msm/mdss/mdss_mdp.c
+++ b/drivers/video/msm/mdss/mdss_mdp.c
@@ -226,7 +226,7 @@
mdss_res->irq_mask &= ~ndx_bit;
if (mdss_res->irq_mask == 0) {
mdss_res->irq_ena = false;
- disable_irq(mdss_res->irq);
+ disable_irq_nosync(mdss_res->irq);
}
}
spin_unlock_irqrestore(&mdss_lock, irq_flags);
@@ -292,7 +292,7 @@
msm_bus_scale_unregister_client(mdata->bus_hdl);
}
-int mdss_mdp_bus_scale_set_quota(u32 ab_quota, u32 ib_quota)
+int mdss_mdp_bus_scale_set_quota(u64 ab_quota, u64 ib_quota)
{
static int current_bus_idx;
int bus_idx;
@@ -310,6 +310,10 @@
bus_idx = (current_bus_idx % (num_cases - 1)) + 1;
+ /* aligning to avoid performing updates for small changes */
+ ab_quota = ALIGN(ab_quota, SZ_64M);
+ ib_quota = ALIGN(ib_quota, SZ_64M);
+
vect = mdp_bus_scale_table.usecase[current_bus_idx].vectors;
if ((ab_quota == vect->ab) && (ib_quota == vect->ib)) {
pr_debug("skip bus scaling, no change in vectors\n");
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index 33028cb..2e92591 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -229,6 +229,7 @@
u8 mixer_stage;
u8 is_fg;
u8 alpha;
+ u8 overfetch_disable;
u32 transp;
struct msm_fb_data_type *mfd;
@@ -276,20 +277,20 @@
int mdss_mdp_set_intr_callback(u32 intr_type, u32 intf_num,
void (*fnc_ptr)(void *), void *arg);
-int mdss_mdp_bus_scale_set_quota(u32 ab_quota, u32 ib_quota);
+int mdss_mdp_bus_scale_set_quota(u64 ab_quota, u64 ib_quota);
void mdss_mdp_set_clk_rate(unsigned long min_clk_rate);
unsigned long mdss_mdp_get_clk_rate(u32 clk_idx);
int mdss_mdp_vsync_clk_enable(int enable);
void mdss_mdp_clk_ctrl(int enable, int isr);
int mdss_mdp_overlay_init(struct msm_fb_data_type *mfd);
-int mdss_mdp_overlay_release_all(struct msm_fb_data_type *mfd);
int mdss_mdp_overlay_vsync_ctrl(struct msm_fb_data_type *mfd, int en);
int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl);
int mdss_mdp_writeback_start(struct mdss_mdp_ctl *ctl);
int mdss_mdp_ctl_on(struct msm_fb_data_type *mfd);
int mdss_mdp_ctl_off(struct msm_fb_data_type *mfd);
+int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg);
struct mdss_mdp_mixer *mdss_mdp_wb_mixer_alloc(int rotator);
int mdss_mdp_wb_mixer_destroy(struct mdss_mdp_mixer *mixer);
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index 73b8c60..00f5874 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -20,8 +20,10 @@
#include "mdss_fb.h"
#include "mdss_mdp.h"
+/* truncate at 1k */
+#define MDSS_MDP_BUS_FACTOR_SHIFT 10
/* 1.5 bus fudge factor */
-#define MDSS_MDP_BUS_FUDGE_FACTOR(val) ALIGN((((val) * 3) / 2), SZ_16M)
+#define MDSS_MDP_BUS_FUDGE_FACTOR(val) (((val) / 2) * 3)
/* 1.25 clock fudge factor */
#define MDSS_MDP_CLK_FUDGE_FACTOR(val) (((val) * 5) / 4)
@@ -44,7 +46,7 @@
struct mdss_mdp_ctl *ctl;
int cnum;
unsigned long clk_rate = 0;
- u32 bus_ab_quota = 0, bus_ib_quota = 0;
+ u64 bus_ab_quota = 0, bus_ib_quota = 0;
if (!flags) {
pr_err("nothing to update\n");
@@ -63,7 +65,14 @@
}
}
if (flags & MDSS_MDP_PERF_UPDATE_BUS) {
+ bus_ab_quota = bus_ab_quota << MDSS_MDP_BUS_FACTOR_SHIFT;
bus_ib_quota = MDSS_MDP_BUS_FUDGE_FACTOR(bus_ib_quota);
+ bus_ib_quota <<= MDSS_MDP_BUS_FACTOR_SHIFT;
+
+ if ((bus_ib_quota == 0) && (clk_rate > 0)) {
+ /* allocate min bw for panel cmds if mdp is active */
+ bus_ib_quota = SZ_16M;
+ }
mdss_mdp_bus_scale_set_quota(bus_ab_quota, bus_ib_quota);
}
if (flags & MDSS_MDP_PERF_UPDATE_CLK) {
@@ -116,6 +125,7 @@
if (is_writeback) {
/* perf for bus writeback */
*bus_ab_quota = fps * mixer->width * mixer->height * 3;
+ *bus_ab_quota >>= MDSS_MDP_BUS_FACTOR_SHIFT;
*bus_ib_quota = *bus_ab_quota;
}
}
@@ -148,13 +158,13 @@
if (mixer->rotator_mode)
rate /= 4; /* block mode fetch at 4 pix/clk */
- *bus_ab_quota += quota;
- *bus_ib_quota += ib_quota;
- if (rate > *clk_rate)
- *clk_rate = rate;
-
pr_debug("mixer=%d pnum=%d clk_rate=%u bus ab=%u ib=%u\n",
mixer->num, pipe->num, rate, quota, ib_quota);
+
+ *bus_ab_quota += quota >> MDSS_MDP_BUS_FACTOR_SHIFT;
+ *bus_ib_quota += ib_quota >> MDSS_MDP_BUS_FACTOR_SHIFT;
+ if (rate > *clk_rate)
+ *clk_rate = rate;
}
pr_debug("final mixer=%d clk_rate=%u bus ab=%u ib=%u\n", mixer->num,
@@ -469,15 +479,25 @@
if (ctl->intf_num == MDSS_MDP_NO_INTF) {
ctl->dst_format = mfd->panel_info.out_format;
} else {
+ struct mdp_dither_cfg_data dither = {
+ .block = mfd->index + MDP_LOGICAL_BLOCK_DISP_0,
+ .flags = MDP_PP_OPS_DISABLE,
+ };
+
switch (mfd->panel_info.bpp) {
case 18:
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB666;
+ dither.flags = MDP_PP_OPS_ENABLE | MDP_PP_OPS_WRITE;
+ dither.g_y_depth = 2;
+ dither.r_cr_depth = 2;
+ dither.b_cb_depth = 2;
break;
case 24:
default:
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB888;
break;
}
+ mdss_mdp_dither_config(&dither, NULL);
}
if (ctl->mixer_right) {
@@ -516,9 +536,28 @@
return 0;
}
-int mdss_mdp_ctl_on(struct msm_fb_data_type *mfd)
+int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg)
{
struct mdss_panel_data *pdata;
+ if (!ctl || !ctl->mfd)
+ return -ENODEV;
+
+ pdata = dev_get_platdata(&ctl->mfd->pdev->dev);
+ if (!pdata) {
+ pr_err("no panel connected\n");
+ return -ENODEV;
+ }
+
+ pr_debug("sending ctl=%d event=%d\n", ctl->num, event);
+
+ if (pdata->event_handler)
+ return pdata->event_handler(pdata, event, arg);
+
+ return 0;
+}
+
+int mdss_mdp_ctl_on(struct msm_fb_data_type *mfd)
+{
struct mdss_mdp_ctl *ctl;
struct mdss_mdp_mixer *mixer;
u32 outsize, temp, off;
@@ -530,12 +569,6 @@
if (mfd->key != MFD_KEY)
return -EINVAL;
- pdata = dev_get_platdata(&mfd->pdev->dev);
- if (!pdata) {
- pr_err("no panel connected\n");
- return -ENODEV;
- }
-
if (mdss_mdp_ctl_init(mfd)) {
pr_err("unable to initialize ctl\n");
return -ENODEV;
@@ -553,6 +586,12 @@
ctl->power_on = true;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_RESET, NULL);
+ if (ret) {
+ pr_err("panel power on failed ctl=%d\n", ctl->num);
+ goto start_fail;
+ }
+
if (ctl->start_fnc)
ret = ctl->start_fnc(ctl);
else
@@ -592,23 +631,17 @@
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_PACK_3D, 0);
}
- /* request bus bandwidth for panel commands */
- ctl->clk_rate = MDP_CLK_DEFAULT_RATE;
- ctl->bus_ib_quota = SZ_1M;
- mdss_mdp_ctl_perf_commit(MDSS_MDP_PERF_UPDATE_ALL);
-
- ret = pdata->on(pdata);
-
start_fail:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mutex_unlock(&ctl->lock);
+ if (ret)
+ mdss_mdp_ctl_destroy(mfd);
return ret;
}
int mdss_mdp_ctl_off(struct msm_fb_data_type *mfd)
{
- struct mdss_panel_data *pdata;
struct mdss_mdp_ctl *ctl;
int ret = 0;
@@ -623,12 +656,6 @@
return -ENODEV;
}
- pdata = dev_get_platdata(&mfd->pdev->dev);
- if (!pdata) {
- pr_err("no panel connected\n");
- return -ENODEV;
- }
-
ctl = mfd->ctl;
if (!ctl->power_on) {
@@ -638,43 +665,33 @@
pr_debug("ctl_num=%d\n", mfd->ctl->num);
- mdss_mdp_overlay_release_all(mfd);
-
- /* request bus bandwidth for panel commands */
- ctl->bus_ib_quota = SZ_1M;
- mdss_mdp_ctl_perf_commit(MDSS_MDP_PERF_UPDATE_ALL);
-
mutex_lock(&ctl->lock);
- ctl->power_on = false;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- if (pdata->intf_unprepare)
- ret = pdata->intf_unprepare(pdata);
-
- if (ret)
- pr_err("%s: intf_unprepare failed\n", __func__);
-
if (ctl->stop_fnc)
ret = ctl->stop_fnc(ctl);
else
pr_warn("no stop func for ctl=%d\n", ctl->num);
- if (ret)
+ if (ret) {
pr_warn("error powering off intf ctl=%d\n", ctl->num);
-
- ret = pdata->off(pdata);
+ } else {
+ ctl->power_on = false;
+ ctl->play_cnt = 0;
+ ctl->clk_rate = 0;
+ mdss_mdp_ctl_perf_commit(MDSS_MDP_PERF_UPDATE_ALL);
+ }
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
- ctl->play_cnt = 0;
-
- mdss_mdp_ctl_perf_commit(MDSS_MDP_PERF_UPDATE_ALL);
-
mutex_unlock(&ctl->lock);
- if (!mfd->ref_cnt)
+ if (!ret && !mfd->ref_cnt) {
+ ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_CLOSE, NULL);
+ WARN(ret, "unable to close intf %d\n", ctl->intf_num);
mdss_mdp_ctl_destroy(mfd);
+ }
return ret;
}
@@ -682,7 +699,7 @@
static int mdss_mdp_mixer_setup(struct mdss_mdp_ctl *ctl,
struct mdss_mdp_mixer *mixer)
{
- struct mdss_mdp_pipe *pipe, *bgpipe = NULL;
+ struct mdss_mdp_pipe *pipe;
u32 off, blend_op, blend_stage;
u32 mixercfg = 0, blend_color_out = 0, bgalpha = 0;
int stage;
@@ -692,26 +709,24 @@
pr_debug("setup mixer=%d\n", mixer->num);
- for (stage = MDSS_MDP_STAGE_BASE; stage < MDSS_MDP_MAX_STAGE; stage++) {
+ pipe = mixer->stage_pipe[MDSS_MDP_STAGE_BASE];
+ if (pipe == NULL) {
+ mixercfg = MDSS_MDP_LM_BORDER_COLOR;
+ } else {
+ mixercfg = 1 << (3 * pipe->num);
+ if (pipe->src_fmt->alpha_enable)
+ bgalpha = 1;
+ }
+
+ for (stage = MDSS_MDP_STAGE_0; stage < MDSS_MDP_MAX_STAGE; stage++) {
pipe = mixer->stage_pipe[stage];
- if (pipe == NULL) {
- if (stage == MDSS_MDP_STAGE_BASE)
- mixercfg |= MDSS_MDP_LM_BORDER_COLOR;
+ if (pipe == NULL)
continue;
- }
if (stage != pipe->mixer_stage) {
mixer->stage_pipe[stage] = NULL;
continue;
}
- mixercfg |= stage << (3 * pipe->num);
-
- if (stage == MDSS_MDP_STAGE_BASE) {
- bgpipe = pipe;
- if (pipe->src_fmt->alpha_enable)
- bgalpha = 1;
- continue;
- }
blend_stage = stage - MDSS_MDP_STAGE_0;
off = MDSS_MDP_REG_LM_OFFSET(mixer->num) +
@@ -719,10 +734,8 @@
if (pipe->is_fg) {
bgalpha = 0;
- if (bgpipe) {
- mixercfg &= ~(0x7 << (3 * bgpipe->num));
- mixercfg |= MDSS_MDP_LM_BORDER_COLOR;
- }
+ mixercfg = MDSS_MDP_LM_BORDER_COLOR;
+
blend_op = (MDSS_MDP_BLEND_FG_ALPHA_FG_CONST |
MDSS_MDP_BLEND_BG_ALPHA_BG_CONST);
/* keep fg alpha */
@@ -753,6 +766,8 @@
stage);
}
+ mixercfg |= stage << (3 * pipe->num);
+
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_OP_MODE, blend_op);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_LM_BLEND_FG_ALPHA,
pipe->alpha);
@@ -903,13 +918,16 @@
return -ENODEV;
}
- if (!ctl->power_on)
- return 0;
-
pr_debug("commit ctl=%d play_cnt=%d\n", ctl->num, ctl->play_cnt);
- if (mutex_lock_interruptible(&ctl->lock))
- return -EINTR;
+ ret = mutex_lock_interruptible(&ctl->lock);
+ if (ret)
+ return ret;
+
+ if (!ctl->power_on) {
+ mutex_unlock(&ctl->lock);
+ return 0;
+ }
mixer1_changed = (ctl->mixer_left && ctl->mixer_left->params_changed);
mixer2_changed = (ctl->mixer_right && ctl->mixer_right->params_changed);
@@ -969,7 +987,7 @@
mutex_lock(&mdss_mdp_ctl_lock);
for (i = 0; i < MDSS_MDP_MAX_CTL; i++) {
ctl = &mdss_mdp_ctl_list[i];
- if ((ctl->power_on) &&
+ if ((ctl->power_on) && (ctl->mfd) &&
(ctl->mfd->index == fb_num)) {
if (ctl->mixer_left) {
mixer_id[mixer_cnt] = ctl->mixer_left->num;
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index 4d3fbf0..9508846 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -201,7 +201,7 @@
static int mdss_mdp_video_stop(struct mdss_mdp_ctl *ctl)
{
struct mdss_mdp_video_ctx *ctx;
- int off;
+ int rc, off;
pr_debug("stop ctl=%d\n", ctl->num);
@@ -211,16 +211,27 @@
return -ENODEV;
}
- if (ctx->vsync_handler)
- mdss_mdp_video_set_vsync_handler(ctl, NULL);
-
if (ctx->timegen_en) {
+ rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_BLANK, NULL);
+ if (rc == -EBUSY) {
+ pr_debug("intf #%d busy don't turn off\n",
+ ctl->intf_num);
+ return rc;
+ }
+ WARN(rc, "intf %d blank error (%d)\n", ctl->intf_num, rc);
+
off = MDSS_MDP_REG_INTF_OFFSET(ctl->intf_num);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_INTF_TIMING_ENGINE_EN, 0);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
ctx->timegen_en = false;
+
+ rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_TIMEGEN_OFF, NULL);
+ WARN(rc, "intf %d timegen off error (%d)\n", ctl->intf_num, rc);
}
+ if (ctx->vsync_handler)
+ mdss_mdp_video_set_vsync_handler(ctl, NULL);
+
mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_INTF_VSYNC, ctl->intf_num,
NULL, NULL);
mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num,
@@ -288,6 +299,7 @@
static int mdss_mdp_video_display(struct mdss_mdp_ctl *ctl, void *arg)
{
struct mdss_mdp_video_ctx *ctx;
+ int rc;
pr_debug("kickoff ctl=%d\n", ctl->num);
@@ -306,15 +318,23 @@
if (!ctx->timegen_en) {
int off = MDSS_MDP_REG_INTF_OFFSET(ctl->intf_num);
+ rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_UNBLANK, NULL);
+ WARN(rc, "intf %d unblank error (%d)\n", ctl->intf_num, rc);
+
pr_debug("enabling timing gen for intf=%d\n", ctl->intf_num);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
MDSS_MDP_REG_WRITE(off + MDSS_MDP_REG_INTF_TIMING_ENGINE_EN, 1);
- ctx->timegen_en = true;
wmb();
}
wait_for_completion(&ctx->vsync_comp);
+
+ if (!ctx->timegen_en) {
+ ctx->timegen_en = true;
+ rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_TIMEGEN_ON, NULL);
+ WARN(rc, "intf %d timegen on error (%d)\n", ctl->intf_num, rc);
+ }
if (!ctx->vsync_handler)
mdss_mdp_irq_disable(MDSS_MDP_IRQ_INTF_VSYNC, ctl->intf_num);
mutex_unlock(&ctx->vsync_lock);
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index d52df66..ca8b2f9 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,8 @@
#define CHECK_BOUNDS(offset, size, max_size) \
(((size) > (max_size)) || ((offset) > ((max_size) - (size))))
+static atomic_t ov_active_panels = ATOMIC_INIT(0);
+
static int mdss_mdp_overlay_get(struct msm_fb_data_type *mfd,
struct mdp_overlay *req)
{
@@ -206,6 +208,11 @@
rot->src_rect.w = req->src_rect.w;
rot->src_rect.h = req->src_rect.h;
+ if (req->flags & MDP_DEINTERLACE) {
+ rot->rotations |= MDP_DEINTERLACE;
+ rot->src_rect.h /= 2;
+ }
+
rot->params_changed++;
req->id = rot->session_id;
@@ -313,6 +320,7 @@
pipe->is_fg = req->is_fg;
pipe->alpha = req->alpha;
pipe->transp = req->transp_mask;
+ pipe->overfetch_disable = fmt->is_yuv;
pipe->req_data = *req;
@@ -325,6 +333,15 @@
__func__);
}
+ if (pipe->flags & MDP_DEINTERLACE) {
+ if (pipe->flags & MDP_SOURCE_ROTATED_90) {
+ pipe->src.w /= 2;
+ pipe->img_width /= 2;
+ } else {
+ pipe->src.h /= 2;
+ }
+ }
+
pipe->params_changed++;
req->id = pipe->ndx;
@@ -341,6 +358,15 @@
{
int ret;
+ ret = mutex_lock_interruptible(&mfd->ov_lock);
+ if (ret)
+ return ret;
+
+ if (!mfd->panel_power_on) {
+ mutex_unlock(&mfd->ov_lock);
+ return -EPERM;
+ }
+
if (req->flags & MDSS_MDP_ROT_ONLY) {
ret = mdss_mdp_overlay_rotator_setup(mfd, req);
} else {
@@ -354,6 +380,8 @@
req->z_order -= MDSS_MDP_STAGE_0;
}
+ mutex_unlock(&mfd->ov_lock);
+
return ret;
}
@@ -393,35 +421,18 @@
return 0;
}
-static int mdss_mdp_overlay_kickoff(struct mdss_mdp_ctl *ctl)
+static int mdss_mdp_overlay_cleanup(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_pipe *pipe, *tmp;
- struct msm_fb_data_type *mfd = ctl->mfd;
- int i, ret;
+ LIST_HEAD(destroy_pipes);
+ int i;
- if (mfd->kickoff_fnc)
- ret = mfd->kickoff_fnc(ctl);
- else
- ret = mdss_mdp_display_commit(ctl, NULL);
- if (IS_ERR_VALUE(ret))
- return ret;
-
- complete(&mfd->update.comp);
- mutex_lock(&mfd->no_update.lock);
- if (mfd->no_update.timer.function)
- del_timer(&(mfd->no_update.timer));
-
- mfd->no_update.timer.expires = jiffies + (2 * HZ);
- add_timer(&mfd->no_update.timer);
- mutex_unlock(&mfd->no_update.lock);
-
+ mutex_lock(&mfd->ov_lock);
mutex_lock(&mfd->lock);
list_for_each_entry_safe(pipe, tmp, &mfd->pipes_cleanup, cleanup_list) {
- list_del(&pipe->cleanup_list);
+ list_move(&pipe->cleanup_list, &destroy_pipes);
for (i = 0; i < ARRAY_SIZE(pipe->buffers); i++)
mdss_mdp_overlay_free_buf(&pipe->buffers[i]);
-
- mdss_mdp_pipe_destroy(pipe);
}
if (!list_empty(&mfd->pipes_used)) {
@@ -440,33 +451,44 @@
}
}
mutex_unlock(&mfd->lock);
+ list_for_each_entry_safe(pipe, tmp, &destroy_pipes, cleanup_list)
+ mdss_mdp_pipe_destroy(pipe);
+ mutex_unlock(&mfd->ov_lock);
+
+ return 0;
+}
+
+static int mdss_mdp_overlay_kickoff(struct mdss_mdp_ctl *ctl)
+{
+ struct msm_fb_data_type *mfd = ctl->mfd;
+ int ret;
+
+ if (mfd->kickoff_fnc)
+ ret = mfd->kickoff_fnc(ctl);
+ else
+ ret = mdss_mdp_display_commit(ctl, NULL);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ complete(&mfd->update.comp);
+ mutex_lock(&mfd->no_update.lock);
+ if (mfd->no_update.timer.function)
+ del_timer(&(mfd->no_update.timer));
+
+ mfd->no_update.timer.expires = jiffies + (2 * HZ);
+ add_timer(&mfd->no_update.timer);
+ mutex_unlock(&mfd->no_update.lock);
+
+ ret = mdss_mdp_overlay_cleanup(mfd);
return ret;
}
-static int mdss_mdp_overlay_unset(struct msm_fb_data_type *mfd, int ndx)
+static int mdss_mdp_overlay_release(struct msm_fb_data_type *mfd, int ndx)
{
struct mdss_mdp_pipe *pipe;
- int i, ret = 0;
u32 pipe_ndx, unset_ndx = 0;
-
- if (!mfd || !mfd->ctl)
- return -ENODEV;
-
- pr_debug("unset ndx=%x\n", ndx);
-
- if (ndx & MDSS_MDP_ROT_SESSION_MASK) {
- struct mdss_mdp_rotator_session *rot;
- rot = mdss_mdp_rotator_session_get(ndx);
- if (rot) {
- mdss_mdp_rotator_finish(rot);
- } else {
- pr_warn("unknown session id=%x\n", ndx);
- ret = -ENODEV;
- }
-
- return ret;
- }
+ int i;
for (i = 0; unset_ndx != ndx && i < MDSS_MDP_MAX_SSPP; i++) {
pipe_ndx = BIT(i);
@@ -484,37 +506,59 @@
mdss_mdp_mixer_pipe_unstage(pipe);
}
}
+ return 0;
+}
+
+static int mdss_mdp_overlay_unset(struct msm_fb_data_type *mfd, int ndx)
+{
+ int ret = 0;
+
+ if (!mfd || !mfd->ctl)
+ return -ENODEV;
+
+ ret = mutex_lock_interruptible(&mfd->ov_lock);
+ if (ret)
+ return ret;
+
+ if (!mfd->panel_power_on) {
+ mutex_unlock(&mfd->ov_lock);
+ return -EPERM;
+ }
+
+ pr_debug("unset ndx=%x\n", ndx);
+
+ if (ndx & MDSS_MDP_ROT_SESSION_MASK)
+ ret = mdss_mdp_rotator_release(ndx);
+ else
+ ret = mdss_mdp_overlay_release(mfd, ndx);
+
+ mutex_unlock(&mfd->ov_lock);
return ret;
}
-int mdss_mdp_overlay_release_all(struct msm_fb_data_type *mfd)
+static int mdss_mdp_overlay_release_all(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_pipe *pipe;
u32 unset_ndx = 0;
int cnt = 0;
+ mutex_lock(&mfd->ov_lock);
mutex_lock(&mfd->lock);
- if (!list_empty(&mfd->pipes_used)) {
- list_for_each_entry(pipe, &mfd->pipes_used, used_list) {
- if (pipe->ndx & MDSS_MDP_ROT_SESSION_MASK) {
- struct mdss_mdp_rotator_session *rot;
- rot = mdss_mdp_rotator_session_get(pipe->ndx);
- if (rot)
- mdss_mdp_rotator_finish(rot);
- } else {
- unset_ndx |= pipe->ndx;
- cnt++;
- }
- }
+ list_for_each_entry(pipe, &mfd->pipes_used, used_list) {
+ unset_ndx |= pipe->ndx;
+ cnt++;
}
mutex_unlock(&mfd->lock);
if (unset_ndx) {
pr_debug("%d pipes need cleanup (%x)\n", cnt, unset_ndx);
- mdss_mdp_overlay_unset(mfd, unset_ndx);
- mdss_mdp_overlay_kickoff(mfd->ctl);
+ mdss_mdp_overlay_release(mfd, unset_ndx);
}
+ mutex_unlock(&mfd->ov_lock);
+
+ if (cnt)
+ mdss_mdp_overlay_kickoff(mfd->ctl);
return 0;
}
@@ -541,6 +585,12 @@
struct mdss_mdp_data src_data, dst_data;
int ret;
+ rot = mdss_mdp_rotator_session_get(req->id);
+ if (!rot) {
+ pr_err("invalid session id=%x\n", req->id);
+ return -ENOENT;
+ }
+
ret = mdss_mdp_overlay_get_buf(mfd, &src_data, &req->data, 1);
if (ret) {
pr_err("src_data pmem error\n");
@@ -553,13 +603,6 @@
goto rotate_done;
}
- rot = mdss_mdp_rotator_session_get(req->id);
- if (!rot) {
- pr_err("invalid session id=%x\n", req->id);
- ret = -ENODEV;
- goto rotate_done;
- }
-
ret = mdss_mdp_rotator_queue(rot, &src_data, &dst_data);
if (ret) {
pr_err("rotator queue error session id=%x\n", req->id);
@@ -604,9 +647,6 @@
ctl = pipe->mixer->ctl;
mdss_mdp_pipe_unlock(pipe);
- if ((ret == 0) && (mfd->panel_info.type == WRITEBACK_PANEL))
- ret = mdss_mdp_overlay_kickoff(ctl);
-
return ret;
}
@@ -617,11 +657,29 @@
pr_debug("play req id=%x\n", req->id);
- if (req->id & MDSS_MDP_ROT_SESSION_MASK)
+ ret = mutex_lock_interruptible(&mfd->ov_lock);
+ if (ret)
+ return ret;
+
+ if (!mfd->panel_power_on) {
+ mutex_unlock(&mfd->ov_lock);
+ return -EPERM;
+ }
+
+ if (req->id & MDSS_MDP_ROT_SESSION_MASK) {
ret = mdss_mdp_overlay_rotate(mfd, req);
- else
+ } else {
ret = mdss_mdp_overlay_queue(mfd, req);
+ if ((ret == 0) && (mfd->panel_info.type == WRITEBACK_PANEL)) {
+ mutex_unlock(&mfd->ov_lock);
+ ret = mdss_mdp_overlay_kickoff(mfd->ctl);
+ return ret;
+ }
+ }
+
+ mutex_unlock(&mfd->ov_lock);
+
return ret;
}
@@ -695,10 +753,7 @@
u32 offset;
int bpp, ret;
- if (!mfd)
- return;
-
- if (!mfd->ctl || !mfd->panel_power_on)
+ if (!mfd || !mfd->ctl)
return;
fbi = mfd->fbi;
@@ -708,6 +763,14 @@
return;
}
+ if (mutex_lock_interruptible(&mfd->ov_lock))
+ return;
+
+ if (!mfd->panel_power_on) {
+ mutex_unlock(&mfd->ov_lock);
+ return;
+ }
+
memset(&data, 0, sizeof(data));
bpp = fbi->var.bits_per_pixel / 8;
@@ -758,6 +821,7 @@
return;
}
}
+ mutex_unlock(&mfd->ov_lock);
if (fbi->var.activate & FB_ACTIVATE_VBL)
mdss_mdp_overlay_kickoff(mfd->ctl);
@@ -960,7 +1024,7 @@
}
if (ret) {
- pr_err("OVERLAY_GET failed (%d)\n", ret);
+ pr_debug("OVERLAY_GET failed (%d)\n", ret);
ret = -EFAULT;
}
break;
@@ -974,7 +1038,7 @@
ret = copy_to_user(argp, &req, sizeof(req));
}
if (ret) {
- pr_err("OVERLAY_SET failed (%d)\n", ret);
+ pr_debug("OVERLAY_SET failed (%d)\n", ret);
ret = -EFAULT;
}
break;
@@ -1006,7 +1070,7 @@
}
if (ret) {
- pr_err("OVERLAY_PLAY failed (%d)\n", ret);
+ pr_debug("OVERLAY_PLAY failed (%d)\n", ret);
ret = -EFAULT;
}
} else {
@@ -1052,10 +1116,36 @@
return ret;
}
+static int mdss_mdp_overlay_on(struct msm_fb_data_type *mfd)
+{
+ int rc;
+
+ rc = mdss_mdp_ctl_on(mfd);
+ if (rc == 0)
+ atomic_inc(&ov_active_panels);
+
+ return rc;
+}
+
+static int mdss_mdp_overlay_off(struct msm_fb_data_type *mfd)
+{
+ int rc;
+
+ mdss_mdp_overlay_release_all(mfd);
+
+ rc = mdss_mdp_ctl_off(mfd);
+ if (rc == 0) {
+ if (atomic_dec_return(&ov_active_panels) == 0)
+ mdss_mdp_rotator_release_all();
+ }
+
+ return rc;
+}
+
int mdss_mdp_overlay_init(struct msm_fb_data_type *mfd)
{
- mfd->on_fnc = mdss_mdp_ctl_on;
- mfd->off_fnc = mdss_mdp_ctl_off;
+ mfd->on_fnc = mdss_mdp_overlay_on;
+ mfd->off_fnc = mdss_mdp_overlay_off;
mfd->hw_refresh = true;
mfd->do_histogram = NULL;
mfd->overlay_play_enable = true;
@@ -1068,6 +1158,7 @@
INIT_LIST_HEAD(&mfd->pipes_used);
INIT_LIST_HEAD(&mfd->pipes_cleanup);
+ mutex_init(&mfd->ov_lock);
return 0;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_pipe.c b/drivers/video/msm/mdss/mdss_mdp_pipe.c
index c90ce8c..042b5e9 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pipe.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pipe.c
@@ -22,6 +22,7 @@
#define SMP_MB_CNT (mdss_res->smp_mb_cnt)
static DEFINE_MUTEX(mdss_mdp_sspp_lock);
+static DEFINE_MUTEX(mdss_mdp_smp_lock);
static DECLARE_BITMAP(mdss_mdp_smp_mmb_pool, MDSS_MDP_SMP_MMB_BLOCKS);
static struct mdss_mdp_pipe mdss_mdp_pipe_list[MDSS_MDP_MAX_SSPP];
@@ -69,9 +70,11 @@
static void mdss_mdp_smp_free(struct mdss_mdp_pipe *pipe)
{
+ mutex_lock(&mdss_mdp_smp_lock);
mdss_mdp_smp_mmb_free(&pipe->smp[0]);
mdss_mdp_smp_mmb_free(&pipe->smp[1]);
mdss_mdp_smp_mmb_free(&pipe->smp[2]);
+ mutex_unlock(&mdss_mdp_smp_lock);
}
static int mdss_mdp_smp_reserve(struct mdss_mdp_pipe *pipe)
@@ -83,7 +86,7 @@
(pipe->type == MDSS_MDP_PIPE_TYPE_RGB))
return -EINVAL;
- mutex_lock(&mdss_mdp_sspp_lock);
+ mutex_lock(&mdss_mdp_smp_lock);
for (i = 0; i < pipe->src_planes.num_planes; i++) {
num_blks = DIV_ROUND_UP(2 * pipe->src_planes.ystride[i],
mdss_res->smp_mb_size);
@@ -98,10 +101,11 @@
if (reserved < num_blks) {
pr_err("insufficient MMB blocks\n");
- mdss_mdp_smp_free(pipe);
+ for (; i >= 0; i--)
+ mdss_mdp_smp_mmb_free(&pipe->smp[i]);
return -ENOMEM;
}
- mutex_unlock(&mdss_mdp_sspp_lock);
+ mutex_unlock(&mdss_mdp_smp_lock);
return 0;
}
@@ -141,10 +145,10 @@
return -EINVAL;
}
- mutex_lock(&mdss_mdp_sspp_lock);
+ mutex_lock(&mdss_mdp_smp_lock);
for (i = 0; i < pipe->src_planes.num_planes; i++)
mdss_mdp_smp_mmb_set(client_id + i, &pipe->smp[i]);
- mutex_unlock(&mdss_mdp_sspp_lock);
+ mutex_unlock(&mdss_mdp_smp_lock);
return 0;
}
@@ -264,9 +268,7 @@
atomic_read(&pipe->ref_cnt));
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- mutex_lock(&mdss_mdp_sspp_lock);
mdss_mdp_pipe_free(pipe);
- mutex_unlock(&mdss_mdp_sspp_lock);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
return 0;
@@ -464,6 +466,7 @@
static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe)
{
u32 img_size, src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;
+ u32 width, height;
pr_debug("pnum=%d wh=%dx%d src={%d,%d,%d,%d} dst={%d,%d,%d,%d}\n",
pipe->num, pipe->img_width, pipe->img_height,
@@ -473,10 +476,21 @@
if (mdss_mdp_scale_setup(pipe))
return -EINVAL;
- mdss_mdp_get_plane_sizes(pipe->src_fmt->format, pipe->img_width,
- pipe->img_height, &pipe->src_planes);
+ width = pipe->img_width;
+ height = pipe->img_height;
+ mdss_mdp_get_plane_sizes(pipe->src_fmt->format, width, height,
+ &pipe->src_planes);
- img_size = (pipe->img_height << 16) | pipe->img_width;
+ if ((pipe->flags & MDP_DEINTERLACE) &&
+ !(pipe->flags & MDP_SOURCE_ROTATED_90)) {
+ int i;
+ for (i = 0; i < pipe->src_planes.num_planes; i++)
+ pipe->src_planes.ystride[i] *= 2;
+ width *= 2;
+ height /= 2;
+ }
+
+ img_size = (height << 16) | width;
src_size = (pipe->src.h << 16) | pipe->src.w;
src_xy = (pipe->src.y << 16) | pipe->src.x;
dst_size = (pipe->dst.h << 16) | pipe->dst.w;
@@ -486,6 +500,11 @@
ystride1 = (pipe->src_planes.ystride[2]) |
(pipe->src_planes.ystride[3] << 16);
+ if (pipe->overfetch_disable) {
+ img_size = src_size;
+ src_xy = 0;
+ }
+
mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_IMG_SIZE, img_size);
mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_SIZE, src_size);
mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_XY, src_xy);
@@ -591,6 +610,28 @@
return 0;
}
+static void mdss_mdp_addr_add_offset(struct mdss_mdp_pipe *pipe,
+ struct mdss_mdp_data *data)
+{
+ data->p[0].addr += pipe->src.x +
+ (pipe->src.y * pipe->src_planes.ystride[0]);
+ if (data->num_planes > 1) {
+ u8 hmap[] = { 1, 2, 1, 2 };
+ u8 vmap[] = { 1, 1, 2, 2 };
+ u16 xoff = pipe->src.x / hmap[pipe->src_fmt->chroma_sample];
+ u16 yoff = pipe->src.y / vmap[pipe->src_fmt->chroma_sample];
+
+ if (data->num_planes == 2) /* pseudo planar */
+ xoff *= 2;
+ data->p[1].addr += xoff + (yoff * pipe->src_planes.ystride[1]);
+
+ if (data->num_planes > 2) { /* planar */
+ data->p[2].addr += xoff +
+ (yoff * pipe->src_planes.ystride[2]);
+ }
+ }
+}
+
static int mdss_mdp_src_addr_setup(struct mdss_mdp_pipe *pipe,
struct mdss_mdp_data *data)
{
@@ -606,6 +647,9 @@
if (ret)
return ret;
+ if (pipe->overfetch_disable)
+ mdss_mdp_addr_add_offset(pipe, data);
+
/* planar format expects YCbCr, swap chroma planes if YCrCb */
if (!is_rot && (pipe->src_fmt->fetch_planes == MDSS_MDP_PLANE_PLANAR) &&
(pipe->src_fmt->element[0] == C2_R_Cr))
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.c b/drivers/video/msm/mdss/mdss_mdp_rotator.c
index dc1cb0d..647fddc 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.c
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -187,12 +187,17 @@
{
struct mdss_mdp_pipe *rot_pipe;
struct mdss_mdp_ctl *ctl;
- int ret;
+ int ret, need_wait = false;
- if (!rot)
+ ret = mutex_lock_interruptible(&rotator_lock);
+ if (ret)
+ return ret;
+
+ if (!rot || !rot->ref_cnt) {
+ mutex_unlock(&rotator_lock);
return -ENODEV;
+ }
- mutex_lock(&rotator_lock);
ret = mdss_mdp_rotator_pipe_dequeue(rot);
if (ret) {
pr_err("unable to acquire rotator\n");
@@ -225,16 +230,18 @@
ret = mdss_mdp_rotator_kickoff(ctl, rot, dst_data);
+ if (ret == 0 && !rot->no_wait)
+ need_wait = true;
done:
mutex_unlock(&rotator_lock);
- if (!rot->no_wait)
+ if (need_wait)
mdss_mdp_rotator_busy_wait(rot);
return ret;
}
-int mdss_mdp_rotator_finish(struct mdss_mdp_rotator_session *rot)
+static int mdss_mdp_rotator_finish(struct mdss_mdp_rotator_session *rot)
{
struct mdss_mdp_pipe *rot_pipe;
@@ -243,7 +250,6 @@
pr_debug("finish rot id=%x\n", rot->session_id);
- mutex_lock(&rotator_lock);
rot_pipe = rot->pipe;
if (rot_pipe) {
mdss_mdp_rotator_busy_wait(rot);
@@ -255,7 +261,43 @@
mdss_mdp_pipe_destroy(rot_pipe);
mdss_mdp_wb_mixer_destroy(mixer);
}
+
+ return 0;
+}
+
+int mdss_mdp_rotator_release(u32 ndx)
+{
+ struct mdss_mdp_rotator_session *rot;
+ mutex_lock(&rotator_lock);
+ rot = mdss_mdp_rotator_session_get(ndx);
+ if (rot) {
+ mdss_mdp_rotator_finish(rot);
+ } else {
+ pr_warn("unknown session id=%x\n", ndx);
+ return -ENOENT;
+ }
mutex_unlock(&rotator_lock);
return 0;
}
+
+int mdss_mdp_rotator_release_all(void)
+{
+ struct mdss_mdp_rotator_session *rot;
+ int i, cnt;
+
+ mutex_lock(&rotator_lock);
+ for (i = 0, cnt = 0; i < MAX_ROTATOR_SESSIONS; i++) {
+ rot = &rotator_session[i];
+ if (rot->ref_cnt) {
+ mdss_mdp_rotator_finish(rot);
+ cnt++;
+ }
+ }
+ mutex_unlock(&rotator_lock);
+
+ if (cnt)
+ pr_debug("cleaned up %d rotator sessions\n", cnt);
+
+ return 0;
+}
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.h b/drivers/video/msm/mdss/mdss_mdp_rotator.h
index eb5b47a..cc4e339 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.h
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -48,7 +48,8 @@
int mdss_mdp_rotator_queue(struct mdss_mdp_rotator_session *rot,
struct mdss_mdp_data *src_data,
struct mdss_mdp_data *dst_data);
-int mdss_mdp_rotator_finish(struct mdss_mdp_rotator_session *rot);
-int mdss_mdp_rotator_ctl_busy_wait(struct mdss_mdp_ctl *ctl);
+
+int mdss_mdp_rotator_release(u32 ndx);
+int mdss_mdp_rotator_release_all(void);
#endif /* MDSS_MDP_ROTATOR_H */
diff --git a/drivers/video/msm/mdss/mdss_mdp_util.c b/drivers/video/msm/mdss/mdss_mdp_util.c
index 95c92fc..ee9582a 100644
--- a/drivers/video/msm/mdss/mdss_mdp_util.c
+++ b/drivers/video/msm/mdss/mdss_mdp_util.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -21,6 +21,7 @@
#include <linux/msm_kgsl.h>
#include <linux/spinlock.h>
#include <linux/types.h>
+#include <media/msm_media_info.h>
#include <mach/iommu_domains.h>
@@ -210,6 +211,13 @@
ps->num_planes = 1;
ps->plane_size[0] = w * h * bpp;
ps->ystride[0] = w * bpp;
+ } else if (format == MDP_Y_CBCR_H2V2_VENUS) {
+ int cf = COLOR_FMT_NV12;
+ ps->num_planes = 2;
+ ps->ystride[0] = VENUS_Y_STRIDE(cf, w);
+ ps->ystride[1] = VENUS_UV_STRIDE(cf, w);
+ ps->plane_size[0] = VENUS_Y_SCANLINES(cf, h) * ps->ystride[0];
+ ps->plane_size[1] = VENUS_UV_SCANLINES(cf, h) * ps->ystride[1];
} else {
u8 hmap[] = { 1, 2, 1, 2 };
u8 vmap[] = { 1, 1, 2, 2 };
@@ -223,10 +231,6 @@
stride_align = 16;
height_align = 1;
break;
- case MDP_Y_CBCR_H2V2_VENUS:
- stride_align = 32;
- height_align = 32;
- break;
default:
stride_align = 1;
height_align = 1;
diff --git a/drivers/video/msm/mdss/mdss_panel.h b/drivers/video/msm/mdss/mdss_panel.h
index 5cdfe34..28d7051 100644
--- a/drivers/video/msm/mdss/mdss_panel.h
+++ b/drivers/video/msm/mdss/mdss_panel.h
@@ -55,6 +55,17 @@
MAX_PHYS_TARGET_NUM,
};
+enum mdss_intf_events {
+ MDSS_EVENT_RESET,
+ MDSS_EVENT_UNBLANK,
+ MDSS_EVENT_TIMEGEN_ON,
+ MDSS_EVENT_BLANK,
+ MDSS_EVENT_TIMEGEN_OFF,
+ MDSS_EVENT_CLOSE,
+ MDSS_EVENT_SUSPEND,
+ MDSS_EVENT_RESUME,
+};
+
/* panel info type */
struct lcd_panel_info {
u32 vsync_enable;
@@ -178,14 +189,11 @@
struct mdss_panel_data {
struct mdss_panel_info panel_info;
- void (*set_backlight) (struct mdss_panel_data *pdata,
- u32 bl_level);
- int (*intf_unprepare) (struct mdss_panel_data *pdata);
+ void (*set_backlight) (struct mdss_panel_data *pdata, u32 bl_level);
unsigned char *mmss_cc_base;
/* function entry chain */
- int (*on) (struct mdss_panel_data *pdata);
- int (*off) (struct mdss_panel_data *pdata);
+ int (*event_handler) (struct mdss_panel_data *pdata, int e, void *arg);
};
int mdss_register_panel(struct mdss_panel_data *pdata);
diff --git a/drivers/video/msm/mdss/mdss_wb.c b/drivers/video/msm/mdss/mdss_wb.c
index d4c924f..c3dc06b 100644
--- a/drivers/video/msm/mdss/mdss_wb.c
+++ b/drivers/video/msm/mdss/mdss_wb.c
@@ -25,15 +25,10 @@
#include "mdss_panel.h"
-static int mdss_wb_on(struct mdss_panel_data *pdata)
+static int mdss_wb_event_handler(struct mdss_panel_data *pdata,
+ int event, void *arg)
{
- pr_debug("%s\n", __func__);
- return 0;
-}
-
-static int mdss_wb_off(struct mdss_panel_data *pdata)
-{
- pr_debug("%s\n", __func__);
+ pr_debug("%s: event=%d\n", __func__, event);
return 0;
}
@@ -75,8 +70,7 @@
pdata->panel_info.pdest = DISPLAY_3;
pdata->panel_info.out_format = MDP_Y_CBCR_H2V2_VENUS;
- pdata->on = mdss_wb_on;
- pdata->off = mdss_wb_off;
+ pdata->event_handler = mdss_wb_event_handler;
pdev->dev.platform_data = pdata;
rc = mdss_register_panel(pdata);
diff --git a/drivers/video/msm/mdss/mhl_sii8334.c b/drivers/video/msm/mdss/mhl_sii8334.c
new file mode 100644
index 0000000..6a63964
--- /dev/null
+++ b/drivers/video/msm/mdss/mhl_sii8334.c
@@ -0,0 +1,1184 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/types.h>
+#include <linux/mhl_8334.h>
+
+#include "mdss_fb.h"
+#include "mdss_hdmi_tx.h"
+#include "mdss_hdmi_edid.h"
+#include "mdss.h"
+#include "mdss_panel.h"
+#include "mdss_io_util.h"
+
+#define MHL_DRIVER_NAME "sii8334"
+#define COMPATIBLE_NAME "qcom,mhl-sii8334"
+
+#define pr_debug_intr(...) pr_debug("\n")
+
+enum mhl_gpio_type {
+ MHL_TX_RESET_GPIO,
+ MHL_TX_INTR_GPIO,
+ MHL_TX_PMIC_PWR_GPIO,
+ MHL_TX_MAX_GPIO,
+};
+
+enum mhl_vreg_type {
+ MHL_TX_3V_VREG,
+ MHL_TX_MAX_VREG,
+};
+
+struct mhl_tx_platform_data {
+ /* Data filled from device tree nodes */
+ struct dss_gpio *gpios[MHL_TX_MAX_GPIO];
+ struct dss_vreg *vregs[MHL_TX_MAX_VREG];
+ int irq;
+};
+
+struct mhl_tx_ctrl {
+ struct platform_device *pdev;
+ struct mhl_tx_platform_data *pdata;
+ struct i2c_client *i2c_handle;
+ uint8_t cur_state;
+ uint8_t chip_rev_id;
+ int mhl_mode;
+};
+
+
+uint8_t slave_addrs[MAX_PAGES] = {
+ DEV_PAGE_TPI_0 ,
+ DEV_PAGE_TX_L0_0 ,
+ DEV_PAGE_TX_L1_0 ,
+ DEV_PAGE_TX_2_0 ,
+ DEV_PAGE_TX_3_0 ,
+ DEV_PAGE_CBUS ,
+ DEV_PAGE_DDC_EDID ,
+ DEV_PAGE_DDC_SEGM ,
+};
+
+static irqreturn_t mhl_tx_isr(int irq, void *dev_id);
+static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl,
+ enum mhl_st_type to_mode);
+static void mhl_drive_hpd(struct mhl_tx_ctrl *mhl_ctrl,
+ uint8_t to_state);
+
+static int mhl_i2c_reg_read(struct i2c_client *client,
+ uint8_t slave_addr_index, uint8_t reg_offset)
+{
+ int rc = -1;
+ uint8_t buffer = 0;
+
+ rc = mdss_i2c_byte_read(client, slave_addrs[slave_addr_index],
+ reg_offset, &buffer);
+ if (rc) {
+ pr_err("%s: slave=%x, off=%x\n",
+ __func__, slave_addrs[slave_addr_index], reg_offset);
+ return rc;
+ }
+ return buffer;
+}
+
+
+static int mhl_i2c_reg_write(struct i2c_client *client,
+ uint8_t slave_addr_index, uint8_t reg_offset,
+ uint8_t value)
+{
+ return mdss_i2c_byte_write(client, slave_addrs[slave_addr_index],
+ reg_offset, &value);
+}
+
+static void mhl_i2c_reg_modify(struct i2c_client *client,
+ uint8_t slave_addr_index, uint8_t reg_offset,
+ uint8_t mask, uint8_t val)
+{
+ uint8_t temp;
+
+ temp = mhl_i2c_reg_read(client, slave_addr_index, reg_offset);
+ temp &= (~mask);
+ temp |= (mask & val);
+ mhl_i2c_reg_write(client, slave_addr_index, reg_offset, temp);
+}
+
+
+static int mhl_tx_get_dt_data(struct device *dev,
+ struct mhl_tx_platform_data *pdata)
+{
+ int i, rc = 0;
+ struct device_node *of_node = NULL;
+ struct dss_gpio *temp_gpio = NULL;
+ i = 0;
+
+ if (!dev || !pdata) {
+ pr_err("%s: invalid input\n", __func__);
+ return -EINVAL;
+ }
+
+ of_node = dev->of_node;
+ if (!of_node) {
+ pr_err("%s: invalid of_node\n", __func__);
+ goto error;
+ }
+
+ pr_debug("%s: id=%d\n", __func__, dev->id);
+
+ /* GPIOs */
+ temp_gpio = NULL;
+ temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL);
+ pr_debug("%s: gpios allocd\n", __func__);
+ if (!(temp_gpio)) {
+ pr_err("%s: can't alloc %d gpio mem\n", __func__, i);
+ goto error;
+ }
+ /* RESET */
+ temp_gpio->gpio = of_get_named_gpio(of_node, "mhl-rst-gpio", 0);
+ snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-rst-gpio");
+ pr_debug("%s: rst gpio=[%d]\n", __func__,
+ temp_gpio->gpio);
+ pdata->gpios[MHL_TX_RESET_GPIO] = temp_gpio;
+
+ /* PWR */
+ temp_gpio = NULL;
+ temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL);
+ pr_debug("%s: gpios allocd\n", __func__);
+ if (!(temp_gpio)) {
+ pr_err("%s: can't alloc %d gpio mem\n", __func__, i);
+ goto error;
+ }
+ temp_gpio->gpio = of_get_named_gpio(of_node, "mhl-pwr-gpio", 0);
+ snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-pwr-gpio");
+ pr_debug("%s: pmic gpio=[%d]\n", __func__,
+ temp_gpio->gpio);
+ pdata->gpios[MHL_TX_PMIC_PWR_GPIO] = temp_gpio;
+
+ /* INTR */
+ temp_gpio = NULL;
+ temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL);
+ pr_debug("%s: gpios allocd\n", __func__);
+ if (!(temp_gpio)) {
+ pr_err("%s: can't alloc %d gpio mem\n", __func__, i);
+ goto error;
+ }
+ temp_gpio->gpio = of_get_named_gpio(of_node, "mhl-intr-gpio", 0);
+ snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-intr-gpio");
+ pr_debug("%s: intr gpio=[%d]\n", __func__,
+ temp_gpio->gpio);
+ pdata->gpios[MHL_TX_INTR_GPIO] = temp_gpio;
+
+ return 0;
+error:
+ pr_err("%s: ret due to err\n", __func__);
+ for (i = 0; i < MHL_TX_MAX_GPIO; i++)
+ if (pdata->gpios[i])
+ devm_kfree(dev, pdata->gpios[i]);
+ return rc;
+} /* mhl_tx_get_dt_data */
+
+static int mhl_sii_reset_pin(struct mhl_tx_ctrl *mhl_ctrl, int on)
+{
+ gpio_set_value(mhl_ctrl->pdata->gpios[MHL_TX_RESET_GPIO]->gpio,
+ on);
+ return 0;
+}
+
+static void cbus_reset(struct i2c_client *client)
+{
+ uint8_t i;
+
+ /*
+ * REG_SRST
+ */
+ MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, BIT3);
+ msleep(20);
+ MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, 0x00);
+ /*
+ * REG_INTR1 and REG_INTR4
+ */
+ MHL_SII_REG_NAME_WR(REG_INTR1_MASK, BIT6);
+ MHL_SII_REG_NAME_WR(REG_INTR4_MASK,
+ BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
+
+ MHL_SII_REG_NAME_WR(REG_INTR5_MASK, 0x00);
+
+ /* Unmask CBUS1 Intrs */
+ MHL_SII_CBUS_WR(0x0009,
+ BIT2 | BIT3 | BIT4 | BIT5 | BIT6);
+
+ /* Unmask CBUS2 Intrs */
+ MHL_SII_CBUS_WR(0x001F, BIT2 | BIT3);
+
+ for (i = 0; i < 4; i++) {
+ /*
+ * Enable WRITE_STAT interrupt for writes to
+ * all 4 MSC Status registers.
+ */
+ MHL_SII_CBUS_WR((0xE0 + i), 0xFF);
+
+ /*
+ * Enable SET_INT interrupt for writes to
+ * all 4 MSC Interrupt registers.
+ */
+ MHL_SII_CBUS_WR((0xF0 + i), 0xFF);
+ }
+ return;
+}
+
+static void init_cbus_regs(struct i2c_client *client)
+{
+ uint8_t regval;
+
+ /* Increase DDC translation layer timer*/
+ MHL_SII_CBUS_WR(0x0007, 0xF2);
+ /* Drive High Time */
+ MHL_SII_CBUS_WR(0x0036, 0x03);
+ /* Use programmed timing */
+ MHL_SII_CBUS_WR(0x0039, 0x30);
+ /* CBUS Drive Strength */
+ MHL_SII_CBUS_WR(0x0040, 0x03);
+ /*
+ * Write initial default settings
+ * to devcap regs: default settings
+ */
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_DEV_STATE, DEVCAP_VAL_DEV_STATE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_MHL_VERSION, DEVCAP_VAL_MHL_VERSION);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_DEV_CAT, DEVCAP_VAL_DEV_CAT);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_ADOPTER_ID_H, DEVCAP_VAL_ADOPTER_ID_H);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_ADOPTER_ID_L, DEVCAP_VAL_ADOPTER_ID_L);
+ MHL_SII_CBUS_WR(0x0080 | DEVCAP_OFFSET_VID_LINK_MODE,
+ DEVCAP_VAL_VID_LINK_MODE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_AUD_LINK_MODE,
+ DEVCAP_VAL_AUD_LINK_MODE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_VIDEO_TYPE, DEVCAP_VAL_VIDEO_TYPE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_LOG_DEV_MAP, DEVCAP_VAL_LOG_DEV_MAP);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_BANDWIDTH, DEVCAP_VAL_BANDWIDTH);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_FEATURE_FLAG, DEVCAP_VAL_FEATURE_FLAG);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_DEVICE_ID_H, DEVCAP_VAL_DEVICE_ID_H);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_DEVICE_ID_L, DEVCAP_VAL_DEVICE_ID_L);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_SCRATCHPAD_SIZE,
+ DEVCAP_VAL_SCRATCHPAD_SIZE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_INT_STAT_SIZE,
+ DEVCAP_VAL_INT_STAT_SIZE);
+ MHL_SII_CBUS_WR(0x0080 |
+ DEVCAP_OFFSET_RESERVED, DEVCAP_VAL_RESERVED);
+
+ /* Make bits 2,3 (initiator timeout) to 1,1
+ * for register CBUS_LINK_CONTROL_2
+ * REG_CBUS_LINK_CONTROL_2
+ */
+ regval = MHL_SII_CBUS_RD(0x0031);
+ regval = (regval | 0x0C);
+ /* REG_CBUS_LINK_CONTROL_2 */
+ MHL_SII_CBUS_WR(0x0031, regval);
+ /* REG_MSC_TIMEOUT_LIMIT */
+ MHL_SII_CBUS_WR(0x0022, 0x0F);
+ /* REG_CBUS_LINK_CONTROL_1 */
+ MHL_SII_CBUS_WR(0x0030, 0x01);
+ /* disallow vendor specific commands */
+ MHL_SII_CBUS_MOD(0x002E, BIT4, BIT4);
+}
+
+/*
+ * Configure the initial reg settings
+ */
+static void mhl_init_reg_settings(struct i2c_client *client, bool mhl_disc_en)
+{
+ /*
+ * ============================================
+ * POWER UP
+ * ============================================
+ */
+
+ /* Power up 1.2V core */
+ MHL_SII_PAGE1_WR(0x003D, 0x3F);
+ /*
+ * Wait for the source power to be enabled
+ * before enabling pll clocks.
+ */
+ msleep(50);
+ /* Enable Tx PLL Clock */
+ MHL_SII_PAGE2_WR(0x0011, 0x01);
+ /* Enable Tx Clock Path and Equalizer */
+ MHL_SII_PAGE2_WR(0x0012, 0x11);
+ /* Tx Source Termination ON */
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
+ /* Enable 1X MHL Clock output */
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL6, 0xAC);
+ /* Tx Differential Driver Config */
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL2, 0x3C);
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL4, 0xD9);
+ /* PLL Bandwidth Control */
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL8, 0x02);
+ /*
+ * ============================================
+ * Analog PLL Control
+ * ============================================
+ */
+ /* Enable Rx PLL clock */
+ MHL_SII_REG_NAME_WR(REG_TMDS_CCTRL, 0x00);
+ MHL_SII_PAGE0_WR(0x00F8, 0x0C);
+ MHL_SII_PAGE0_WR(0x0085, 0x02);
+ MHL_SII_PAGE2_WR(0x0000, 0x00);
+ MHL_SII_PAGE2_WR(0x0013, 0x60);
+ /* PLL Cal ref sel */
+ MHL_SII_PAGE2_WR(0x0017, 0x03);
+ /* VCO Cal */
+ MHL_SII_PAGE2_WR(0x001A, 0x20);
+ /* Auto EQ */
+ MHL_SII_PAGE2_WR(0x0022, 0xE0);
+ MHL_SII_PAGE2_WR(0x0023, 0xC0);
+ MHL_SII_PAGE2_WR(0x0024, 0xA0);
+ MHL_SII_PAGE2_WR(0x0025, 0x80);
+ MHL_SII_PAGE2_WR(0x0026, 0x60);
+ MHL_SII_PAGE2_WR(0x0027, 0x40);
+ MHL_SII_PAGE2_WR(0x0028, 0x20);
+ MHL_SII_PAGE2_WR(0x0029, 0x00);
+ /* Rx PLL Bandwidth 4MHz */
+ MHL_SII_PAGE2_WR(0x0031, 0x0A);
+ /* Rx PLL Bandwidth value from I2C */
+ MHL_SII_PAGE2_WR(0x0045, 0x06);
+ MHL_SII_PAGE2_WR(0x004B, 0x06);
+ /* Manual zone control */
+ MHL_SII_PAGE2_WR(0x004C, 0xE0);
+ /* PLL Mode value */
+ MHL_SII_PAGE2_WR(0x004D, 0x00);
+ MHL_SII_PAGE0_WR(0x0008, 0x35);
+ /*
+ * Discovery Control and Status regs
+ * Setting De-glitch time to 50 ms (default)
+ * Switch Control Disabled
+ */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL2, 0xAD);
+ /* 1.8V CBUS VTH */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL5, 0x55);
+ /* RGND and single Discovery attempt */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL6, 0x11);
+ /* Ignore VBUS */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL8, 0x82);
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x24);
+
+ /* Enable CBUS Discovery */
+ if (mhl_disc_en) {
+ /* Enable MHL Discovery */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x27);
+ /* Pull-up resistance off for IDLE state */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0xA4);
+ } else {
+ /* Disable MHL Discovery */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x26);
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C);
+ }
+
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL7, 0x20);
+ /* MHL CBUS Discovery - immediate comm. */
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86);
+
+ MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT5 | BIT4, BIT4);
+
+ /* Enable Auto Soft RESET */
+ MHL_SII_REG_NAME_WR(REG_SRST, 0x084);
+ /* HDMI Transcode mode enable */
+ MHL_SII_PAGE0_WR(0x000D, 0x1C);
+
+ cbus_reset(client);
+ init_cbus_regs(client);
+}
+
+
+static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl, enum mhl_st_type to_mode)
+{
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ switch (to_mode) {
+ case POWER_STATE_D0_NO_MHL:
+ break;
+ case POWER_STATE_D0_MHL:
+ mhl_init_reg_settings(client, true);
+ /* REG_DISC_CTRL1 */
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, BIT0);
+
+ /* TPI_DEVICE_POWER_STATE_CTRL_REG */
+ mhl_i2c_reg_modify(client, TX_PAGE_TPI, 0x001E, BIT1 | BIT0,
+ 0x00);
+ break;
+ case POWER_STATE_D3:
+ if (mhl_ctrl->cur_state == POWER_STATE_D3)
+ break;
+
+ /* Force HPD to 0 when not in MHL mode. */
+ mhl_drive_hpd(mhl_ctrl, HPD_DOWN);
+ /*
+ * Change TMDS termination to high impedance
+ * on disconnection.
+ */
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0xD0);
+ msleep(50);
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, 0x00);
+ MHL_SII_PAGE3_MOD(0x003D, BIT0,
+ 0x00);
+ mhl_ctrl->cur_state = POWER_STATE_D3;
+ break;
+ default:
+ break;
+ }
+}
+
+static void mhl_drive_hpd(struct mhl_tx_ctrl *mhl_ctrl, uint8_t to_state)
+{
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ pr_debug("%s: To state=[0x%x]\n", __func__, to_state);
+ if (to_state == HPD_UP) {
+ /*
+ * Drive HPD to UP state
+ *
+ * The below two reg configs combined
+ * enable TMDS output.
+ */
+
+ /* Enable TMDS on TMDS_CCTRL */
+ MHL_SII_REG_NAME_MOD(REG_TMDS_CCTRL, BIT4, BIT4);
+
+ /*
+ * Set HPD_OUT_OVR_EN = HPD State
+ * EDID read and Un-force HPD (from low)
+ * propogate to src let HPD float by clearing
+ * HPD OUT OVRRD EN
+ */
+ MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT4, 0x00);
+ } else {
+ /*
+ * Drive HPD to DOWN state
+ * Disable TMDS Output on REG_TMDS_CCTRL
+ * Enable/Disable TMDS output (MHL TMDS output only)
+ */
+ MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT4, BIT4);
+ MHL_SII_REG_NAME_MOD(REG_TMDS_CCTRL, BIT4, 0x00);
+ }
+ return;
+}
+
+static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t val;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ pr_debug("%s: cur st [0x%x]\n", __func__,
+ mhl_ctrl->cur_state);
+
+ if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
+ /* Already in D0 - MHL power state */
+ pr_err("%s: cur st not D0\n", __func__);
+ return;
+ }
+ /* spin_lock_irqsave(&mhl_state_lock, flags); */
+ mhl_ctrl->cur_state = POWER_STATE_D0_MHL;
+ /* spin_unlock_irqrestore(&mhl_state_lock, flags); */
+
+ MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
+ MHL_SII_CBUS_WR(0x07, 0xF2);
+
+ /*
+ * Keep the discovery enabled. Need RGND interrupt
+ * Possibly chip disables discovery after MHL_EST??
+ * Need to re-enable here
+ */
+ val = MHL_SII_PAGE3_RD(0x10);
+ MHL_SII_PAGE3_WR(0x10, val | BIT0);
+
+ return;
+}
+
+static void mhl_msm_disconnection(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+ /*
+ * MHL TX CTL1
+ * Disabling Tx termination
+ */
+ MHL_SII_PAGE3_WR(0x30, 0xD0);
+
+ switch_mode(mhl_ctrl, POWER_STATE_D3);
+ /*
+ * Only if MHL-USB handshake is not implemented
+ */
+ mhl_init_reg_settings(client, true);
+ return;
+}
+
+static int mhl_msm_read_rgnd_int(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t rgnd_imp;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+ /* DISC STATUS REG 2 */
+ rgnd_imp = (mhl_i2c_reg_read(client,
+ TX_PAGE_3, 0x001C) & (BIT1 | BIT0));
+ pr_debug("imp range read=%02X\n", (int)rgnd_imp);
+
+ if (0x02 == rgnd_imp) {
+ pr_debug("%s: mhl sink\n", __func__);
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL9, BIT0, BIT0);
+ mhl_ctrl->mhl_mode = 1;
+ } else {
+ pr_debug("%s: non-mhl sink\n", __func__);
+ mhl_ctrl->mhl_mode = 0;
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL9, BIT3, BIT3);
+ switch_mode(mhl_ctrl, POWER_STATE_D3);
+ }
+ return mhl_ctrl->mhl_mode ?
+ MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB;
+}
+
+static void force_usb_switch_open(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ /*disable discovery*/
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT0, 0);
+ /* force USB ID switch to open*/
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL6, BIT6, BIT6);
+ MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86);
+ /* force HPD to 0 when not in mhl mode. */
+ MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT5 | BIT4, BIT4);
+}
+
+static void release_usb_switch_open(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ msleep(50);
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL6, BIT6, 0x00);
+ MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT0, BIT0);
+}
+
+static void scdt_st_chg(struct i2c_client *client)
+{
+ uint8_t tmds_cstat;
+ uint8_t mhl_fifo_status;
+
+ /* tmds cstat */
+ tmds_cstat = MHL_SII_PAGE3_RD(0x0040);
+ pr_debug("%s: tmds cstat: 0x%02x\n", __func__,
+ tmds_cstat);
+
+ if (!(tmds_cstat & BIT1))
+ return;
+
+ mhl_fifo_status = MHL_SII_REG_NAME_RD(REG_INTR5);
+ pr_debug("%s: mhl fifo st: 0x%02x\n", __func__,
+ mhl_fifo_status);
+ if (mhl_fifo_status & 0x0C) {
+ MHL_SII_REG_NAME_WR(REG_INTR5, 0x0C);
+ pr_debug("%s: mhl fifo rst\n", __func__);
+ MHL_SII_REG_NAME_WR(REG_SRST, 0x94);
+ MHL_SII_REG_NAME_WR(REG_SRST, 0x84);
+ }
+}
+
+
+static void dev_detect_isr(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t status, reg ;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ /* INTR_STATUS4 */
+ status = MHL_SII_REG_NAME_RD(REG_INTR4);
+ pr_debug("%s: reg int4 st=%02X\n", __func__, status);
+
+ if ((0x00 == status) &&\
+ (mhl_ctrl->cur_state == POWER_STATE_D3)) {
+ pr_err("%s: invalid intr\n", __func__);
+ return;
+ }
+
+ if (0xFF == status) {
+ pr_debug("%s: invalid intr 0xff\n", __func__);
+ MHL_SII_REG_NAME_WR(REG_INTR4, status);
+ return;
+ }
+
+ if ((status & BIT0) && (mhl_ctrl->chip_rev_id < 1)) {
+ pr_debug("%s: scdt intr\n", __func__);
+ scdt_st_chg(client);
+ }
+
+ if (status & BIT1)
+ pr_debug("mhl: int4 bit1 set\n");
+
+ /* mhl_est interrupt */
+ if (status & BIT2) {
+ pr_debug("%s: mhl_est st=%02X\n", __func__,
+ (int) status);
+ mhl_msm_connection(mhl_ctrl);
+ } else if (status & BIT3) {
+ pr_debug("%s: uUSB-a type dev detct\n", __func__);
+ MHL_SII_REG_NAME_WR(REG_DISC_STAT2, 0x80);
+ switch_mode(mhl_ctrl, POWER_STATE_D3);
+ }
+
+ if (status & BIT5) {
+ /* clr intr - reg int4 */
+ pr_debug("%s: mhl discon: int4 st=%02X\n", __func__,
+ (int)status);
+ reg = MHL_SII_REG_NAME_RD(REG_INTR4);
+ MHL_SII_REG_NAME_WR(REG_INTR4, reg);
+ mhl_msm_disconnection(mhl_ctrl);
+ }
+
+ if ((mhl_ctrl->cur_state != POWER_STATE_D0_MHL) &&\
+ (status & BIT6)) {
+ /* rgnd rdy Intr */
+ pr_debug("%s: rgnd ready intr\n", __func__);
+ switch_mode(mhl_ctrl, POWER_STATE_D0_MHL);
+ mhl_msm_read_rgnd_int(mhl_ctrl);
+ }
+
+ /* Can't succeed at these in D3 */
+ if ((mhl_ctrl->cur_state != POWER_STATE_D3) &&\
+ (status & BIT4)) {
+ /* cbus lockout interrupt?
+ * Hardware detection mechanism figures that
+ * CBUS line is latched and raises this intr
+ * where we force usb switch open and release
+ */
+ pr_warn("%s: cbus locked out!\n", __func__);
+ force_usb_switch_open(mhl_ctrl);
+ release_usb_switch_open(mhl_ctrl);
+ }
+ MHL_SII_REG_NAME_WR(REG_INTR4, status);
+
+ return;
+}
+
+static void mhl_misc_isr(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t intr_5_stat;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ /*
+ * Clear INT 5
+ * INTR5 is related to FIFO underflow/overflow reset
+ * which is handled in 8334 by auto FIFO reset
+ */
+ intr_5_stat = MHL_SII_REG_NAME_RD(REG_INTR5);
+ MHL_SII_REG_NAME_WR(REG_INTR5, intr_5_stat);
+}
+
+
+static void mhl_hpd_stat_isr(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t intr_1_stat;
+ uint8_t cbus_stat;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ /* INTR STATUS 1 */
+ intr_1_stat = MHL_SII_PAGE0_RD(0x0071);
+
+ if (!intr_1_stat)
+ return;
+
+ /* Clear interrupts */
+ MHL_SII_PAGE0_WR(0x0071, intr_1_stat);
+ if (BIT6 & intr_1_stat) {
+ /*
+ * HPD status change event is pending
+ * Read CBUS HPD status for this info
+ * MSC REQ ABRT REASON
+ */
+ cbus_stat = MHL_SII_CBUS_RD(0x0D);
+ if (BIT6 & cbus_stat)
+ mhl_drive_hpd(mhl_ctrl, HPD_UP);
+ }
+ return;
+}
+
+static void clear_all_intrs(struct i2c_client *client)
+{
+ uint8_t regval = 0x00;
+
+ pr_debug_intr("********* exiting isr mask check ?? *************\n");
+ pr_debug_intr("int1 mask = %02X\n",
+ (int) MHL_SII_REG_NAME_RD(REG_INTR1));
+ pr_debug_intr("int3 mask = %02X\n",
+ (int) MHL_SII_PAGE0_RD(0x0077));
+ pr_debug_intr("int4 mask = %02X\n",
+ (int) MHL_SII_REG_NAME_RD(REG_INTR4));
+ pr_debug_intr("int5 mask = %02X\n",
+ (int) MHL_SII_REG_NAME_RD(REG_INTR5));
+ pr_debug_intr("cbus1 mask = %02X\n",
+ (int) MHL_SII_CBUS_RD(0x0009));
+ pr_debug_intr("cbus2 mask = %02X\n",
+ (int) MHL_SII_CBUS_RD(0x001F));
+ pr_debug_intr("********* end of isr mask check *************\n");
+
+ regval = MHL_SII_REG_NAME_RD(REG_INTR1);
+ pr_debug_intr("int1 st = %02X\n", (int)regval);
+ MHL_SII_REG_NAME_WR(REG_INTR1, regval);
+
+ regval = MHL_SII_REG_NAME_RD(REG_INTR2);
+ pr_debug_intr("int2 st = %02X\n", (int)regval);
+ MHL_SII_REG_NAME_WR(REG_INTR2, regval);
+
+ regval = MHL_SII_PAGE0_RD(0x0073);
+ pr_debug_intr("int3 st = %02X\n", (int)regval);
+ MHL_SII_PAGE0_WR(0x0073, regval);
+
+ regval = MHL_SII_REG_NAME_RD(REG_INTR4);
+ pr_debug_intr("int4 st = %02X\n", (int)regval);
+ MHL_SII_REG_NAME_WR(REG_INTR4, regval);
+
+ regval = MHL_SII_REG_NAME_RD(REG_INTR5);
+ pr_debug_intr("int5 st = %02X\n", (int)regval);
+ MHL_SII_REG_NAME_WR(REG_INTR5, regval);
+
+ regval = MHL_SII_CBUS_RD(0x0008);
+ pr_debug_intr("cbusInt st = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x0008, regval);
+
+ regval = MHL_SII_CBUS_RD(0x001E);
+ pr_debug_intr("CBUS intR_2: %d\n", (int)regval);
+ MHL_SII_CBUS_WR(0x001E, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00A0);
+ pr_debug_intr("A0 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00A0, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00A1);
+ pr_debug_intr("A1 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00A1, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00A2);
+ pr_debug_intr("A2 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00A2, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00A3);
+ pr_debug_intr("A3 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00A3, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00B0);
+ pr_debug_intr("B0 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00B0, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00B1);
+ pr_debug_intr("B1 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00B1, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00B2);
+ pr_debug_intr("B2 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00B2, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00B3);
+ pr_debug_intr("B3 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00B3, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00E0);
+ pr_debug_intr("E0 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00E0, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00E1);
+ pr_debug_intr("E1 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00E1, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00E2);
+ pr_debug_intr("E2 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00E2, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00E3);
+ pr_debug_intr("E3 st set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00E3, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00F0);
+ pr_debug_intr("F0 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00F0, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00F1);
+ pr_debug_intr("F1 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00F1, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00F2);
+ pr_debug_intr("F2 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00F2, regval);
+
+ regval = MHL_SII_CBUS_RD(0x00F3);
+ pr_debug_intr("F3 int set = %02X\n", (int)regval);
+ MHL_SII_CBUS_WR(0x00F3, regval);
+ pr_debug_intr("********* end of exiting in isr *************\n");
+}
+
+
+static irqreturn_t mhl_tx_isr(int irq, void *data)
+{
+ struct mhl_tx_ctrl *mhl_ctrl = (struct mhl_tx_ctrl *)data;
+ pr_debug("%s: Getting Interrupts\n", __func__);
+
+ /*
+ * Check RGND, MHL_EST, CBUS_LOCKOUT, SCDT
+ * interrupts. In D3, we get only RGND
+ */
+ dev_detect_isr(mhl_ctrl);
+
+ pr_debug("%s: cur pwr state is [0x%x]\n",
+ __func__, mhl_ctrl->cur_state);
+ if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) {
+ /*
+ * If dev_detect_isr() didn't move the tx to D3
+ * on disconnect, continue to check other
+ * interrupt sources.
+ */
+ mhl_misc_isr(mhl_ctrl);
+
+ /*
+ * Check for any peer messages for DCAP_CHG etc
+ * Dispatch to have the CBUS module working only
+ * once connected.
+ mhl_cbus_isr(mhl_ctrl);
+ */
+ mhl_hpd_stat_isr(mhl_ctrl);
+ }
+
+ clear_all_intrs(mhl_ctrl->i2c_handle);
+
+ return IRQ_HANDLED;
+}
+
+static int mhl_tx_chip_init(struct mhl_tx_ctrl *mhl_ctrl)
+{
+ uint8_t chip_rev_id = 0x00;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+
+ /* Reset the TX chip */
+ mhl_sii_reset_pin(mhl_ctrl, 0);
+ msleep(20);
+ mhl_sii_reset_pin(mhl_ctrl, 1);
+ /* TX PR-guide requires a 100 ms wait here */
+ msleep(100);
+
+ /* Read the chip rev ID */
+ chip_rev_id = MHL_SII_PAGE0_RD(0x04);
+ pr_debug("MHL: chip rev ID read=[%x]\n", chip_rev_id);
+
+ /*
+ * Need to disable MHL discovery if
+ * MHL-USB handshake is implemented
+ */
+ mhl_init_reg_settings(client, true);
+ return 0;
+}
+
+static int mhl_sii_reg_config(struct i2c_client *client, bool enable)
+{
+ static struct regulator *reg_8941_l24;
+ static struct regulator *reg_8941_l02;
+ int rc;
+
+ pr_debug("Inside %s\n", __func__);
+ if (!reg_8941_l24) {
+ reg_8941_l24 = regulator_get(&client->dev,
+ "avcc_18");
+ if (IS_ERR(reg_8941_l24)) {
+ pr_err("could not get reg_8038_l20, rc = %ld\n",
+ PTR_ERR(reg_8941_l24));
+ return -ENODEV;
+ }
+ if (enable)
+ rc = regulator_enable(reg_8941_l24);
+ else
+ rc = regulator_disable(reg_8941_l24);
+ if (rc) {
+ pr_err("'%s' regulator config[%u] failed, rc=%d\n",
+ "avcc_1.8V", enable, rc);
+ return rc;
+ } else {
+ pr_debug("%s: vreg L24 %s\n",
+ __func__, (enable ? "enabled" : "disabled"));
+ }
+ }
+
+ if (!reg_8941_l02) {
+ reg_8941_l02 = regulator_get(&client->dev,
+ "avcc_12");
+ if (IS_ERR(reg_8941_l02)) {
+ pr_err("could not get reg_8941_l02, rc = %ld\n",
+ PTR_ERR(reg_8941_l02));
+ return -ENODEV;
+ }
+ if (enable)
+ rc = regulator_enable(reg_8941_l02);
+ else
+ rc = regulator_disable(reg_8941_l02);
+ if (rc) {
+ pr_debug("'%s' regulator configure[%u] failed, rc=%d\n",
+ "avcc_1.2V", enable, rc);
+ return rc;
+ } else {
+ pr_debug("%s: vreg L02 %s\n",
+ __func__, (enable ? "enabled" : "disabled"));
+ }
+ }
+
+ return rc;
+}
+
+
+static int mhl_vreg_config(struct mhl_tx_ctrl *mhl_ctrl, uint8_t on)
+{
+ int ret;
+ struct i2c_client *client = mhl_ctrl->i2c_handle;
+ int pwr_gpio = mhl_ctrl->pdata->gpios[MHL_TX_PMIC_PWR_GPIO]->gpio;
+
+ pr_debug("%s\n", __func__);
+ if (on) {
+ ret = gpio_request(pwr_gpio,
+ mhl_ctrl->pdata->gpios[MHL_TX_PMIC_PWR_GPIO]->gpio_name);
+ if (ret < 0) {
+ pr_err("%s: mhl pwr gpio req failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ret = gpio_direction_output(pwr_gpio, 1);
+ if (ret < 0) {
+ pr_err("%s: set gpio MHL_PWR_EN dircn failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = mhl_sii_reg_config(client, true);
+ if (ret) {
+ pr_err("%s: regulator enable failed\n", __func__);
+ return -EINVAL;
+ }
+ pr_debug("%s: mhl sii power on successful\n", __func__);
+ } else {
+ pr_warn("%s: turning off pwr controls\n", __func__);
+ mhl_sii_reg_config(client, false);
+ gpio_free(pwr_gpio);
+ }
+ pr_debug("%s: successful\n", __func__);
+ return 0;
+}
+
+/*
+ * Request for GPIO allocations
+ * Set appropriate GPIO directions
+ */
+static int mhl_gpio_config(struct mhl_tx_ctrl *mhl_ctrl, int on)
+{
+ int ret;
+ struct dss_gpio *temp_reset_gpio, *temp_intr_gpio;
+
+ /* caused too many line spills */
+ temp_reset_gpio = mhl_ctrl->pdata->gpios[MHL_TX_RESET_GPIO];
+ temp_intr_gpio = mhl_ctrl->pdata->gpios[MHL_TX_INTR_GPIO];
+
+ if (on) {
+ if (gpio_is_valid(temp_reset_gpio->gpio)) {
+ ret = gpio_request(temp_reset_gpio->gpio,
+ temp_reset_gpio->gpio_name);
+ if (ret < 0) {
+ pr_err("%s:rst_gpio=[%d] req failed:%d\n",
+ __func__, temp_reset_gpio->gpio, ret);
+ return -EBUSY;
+ }
+ ret = gpio_direction_output(temp_reset_gpio->gpio, 0);
+ if (ret < 0) {
+ pr_err("%s: set dirn rst failed: %d\n",
+ __func__, ret);
+ return -EBUSY;
+ }
+ }
+ if (gpio_is_valid(temp_intr_gpio->gpio)) {
+ ret = gpio_request(temp_intr_gpio->gpio,
+ temp_intr_gpio->gpio_name);
+ if (ret < 0) {
+ pr_err("%s: intr_gpio req failed: %d\n",
+ __func__, ret);
+ return -EBUSY;
+ }
+ ret = gpio_direction_input(temp_intr_gpio->gpio);
+ if (ret < 0) {
+ pr_err("%s: set dirn intr failed: %d\n",
+ __func__, ret);
+ return -EBUSY;
+ }
+ mhl_ctrl->i2c_handle->irq = gpio_to_irq(
+ temp_intr_gpio->gpio);
+ pr_debug("%s: gpio_to_irq=%d\n",
+ __func__, mhl_ctrl->i2c_handle->irq);
+ }
+ } else {
+ pr_warn("%s: freeing gpios\n", __func__);
+ gpio_free(temp_intr_gpio->gpio);
+ gpio_free(temp_reset_gpio->gpio);
+ }
+ pr_debug("%s: successful\n", __func__);
+ return 0;
+}
+
+static int mhl_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int rc = 0;
+ struct mhl_tx_platform_data *pdata = NULL;
+ struct mhl_tx_ctrl *mhl_ctrl;
+
+ mhl_ctrl = devm_kzalloc(&client->dev, sizeof(*mhl_ctrl), GFP_KERNEL);
+ if (!mhl_ctrl) {
+ pr_err("%s: FAILED: cannot alloc hdmi tx ctrl\n", __func__);
+ rc = -ENOMEM;
+ goto failed_no_mem;
+ }
+
+ if (client->dev.of_node) {
+ pdata = devm_kzalloc(&client->dev,
+ sizeof(struct mhl_tx_platform_data), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(&client->dev, "Failed to allocate memory\n");
+ rc = -ENOMEM;
+ goto failed_no_mem;
+ }
+
+ rc = mhl_tx_get_dt_data(&client->dev, pdata);
+ if (rc) {
+ pr_err("%s: FAILED: parsing device tree data; rc=%d\n",
+ __func__, rc);
+ goto failed_dt_data;
+ }
+ mhl_ctrl->i2c_handle = client;
+ mhl_ctrl->pdata = pdata;
+ i2c_set_clientdata(client, mhl_ctrl);
+ }
+
+ /*
+ * Regulator init
+ */
+ rc = mhl_vreg_config(mhl_ctrl, 1);
+ if (rc) {
+ pr_err("%s: vreg init failed [%d]\n",
+ __func__, rc);
+ goto failed_probe;
+ }
+
+ /*
+ * GPIO init
+ */
+ rc = mhl_gpio_config(mhl_ctrl, 1);
+ if (rc) {
+ pr_err("%s: gpio init failed [%d]\n",
+ __func__, rc);
+ goto failed_probe;
+ }
+
+ /*
+ * Other initializations
+ * such tx specific
+ */
+ rc = mhl_tx_chip_init(mhl_ctrl);
+ if (rc) {
+ pr_err("%s: tx chip init failed [%d]\n",
+ __func__, rc);
+ goto failed_probe;
+ }
+
+ pr_debug("%s: IRQ from GPIO INTR = %d\n",
+ __func__, mhl_ctrl->i2c_handle->irq);
+ pr_debug("%s: Driver name = [%s]\n", __func__,
+ client->dev.driver->name);
+ rc = request_threaded_irq(mhl_ctrl->i2c_handle->irq, NULL,
+ &mhl_tx_isr,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ client->dev.driver->name, mhl_ctrl);
+ if (rc) {
+ pr_err("request_threaded_irq failed, status: %d\n",
+ rc);
+ goto failed_probe;
+ } else {
+ pr_debug("request_threaded_irq succeeded\n");
+ }
+ pr_debug("%s: i2c client addr is [%x]\n", __func__, client->addr);
+ return 0;
+failed_probe:
+failed_dt_data:
+ if (pdata)
+ devm_kfree(&client->dev, pdata);
+failed_no_mem:
+ if (mhl_ctrl)
+ devm_kfree(&client->dev, mhl_ctrl);
+ pr_err("%s: PROBE FAILED, rc=%d\n", __func__, rc);
+ return rc;
+}
+
+
+static int mhl_i2c_remove(struct i2c_client *client)
+{
+ struct mhl_tx_ctrl *mhl_ctrl = i2c_get_clientdata(client);
+
+ if (!mhl_ctrl) {
+ pr_warn("%s: i2c get client data failed\n", __func__);
+ return -EINVAL;
+ }
+
+ free_irq(mhl_ctrl->i2c_handle->irq, mhl_ctrl);
+ mhl_gpio_config(mhl_ctrl, 0);
+ mhl_vreg_config(mhl_ctrl, 0);
+ if (mhl_ctrl->pdata)
+ devm_kfree(&client->dev, mhl_ctrl->pdata);
+ devm_kfree(&client->dev, mhl_ctrl);
+ return 0;
+}
+
+static struct i2c_device_id mhl_sii_i2c_id[] = {
+ { MHL_DRIVER_NAME, 0 },
+ { }
+};
+
+
+MODULE_DEVICE_TABLE(i2c, mhl_sii_i2c_id);
+
+static struct of_device_id mhl_match_table[] = {
+ {.compatible = COMPATIBLE_NAME,},
+ { },
+};
+
+static struct i2c_driver mhl_sii_i2c_driver = {
+ .driver = {
+ .name = MHL_DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = mhl_match_table,
+ },
+ .probe = mhl_i2c_probe,
+ .remove = mhl_i2c_remove,
+ .id_table = mhl_sii_i2c_id,
+};
+
+module_i2c_driver(mhl_sii_i2c_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MHL SII 8334 TX Driver");
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c
index a58010e..cc19555 100644
--- a/drivers/video/msm/mipi_dsi.c
+++ b/drivers/video/msm/mipi_dsi.c
@@ -446,9 +446,6 @@
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
- if (!mfd->cont_splash_done)
- cont_splash_clk_ctrl(1);
-
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
@@ -584,6 +581,9 @@
pdev_list[pdev_list_cnt++] = pdev;
+ if (!mfd->cont_splash_done)
+ cont_splash_clk_ctrl(1);
+
return 0;
mipi_dsi_probe_err:
diff --git a/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c b/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
index f139f4c..4c1aa63 100644
--- a/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
+++ b/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
@@ -64,7 +64,7 @@
pinfo.is_3d_panel = FB_TYPE_3D_PANEL;
pinfo.lcd.vsync_enable = TRUE;
pinfo.lcd.hw_vsync_mode = TRUE;
- pinfo.lcd.refx100 = 6000; /* adjust refx100 to prevent tearing */
+ pinfo.lcd.refx100 = 6200; /* adjust refx100 to prevent tearing */
pinfo.lcd.v_back_porch = 11;
pinfo.lcd.v_front_porch = 10;
pinfo.lcd.v_pulse_width = 5;
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index 1994b1b..5189b6d 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -653,12 +653,6 @@
struct msm_fb_panel_data *pdata = NULL;
int ret = 0;
- if (hdmi_prim_display) {
- MSM_FB_INFO("%s: hdmi primary handles early suspend only\n",
- __func__);
- return 0;
- }
-
if ((!mfd) || (mfd->key != MFD_KEY))
return 0;
@@ -684,12 +678,6 @@
struct msm_fb_panel_data *pdata = NULL;
int ret = 0;
- if (hdmi_prim_display) {
- MSM_FB_INFO("%s: hdmi primary handles early resume only\n",
- __func__);
- return 0;
- }
-
if ((!mfd) || (mfd->key != MFD_KEY))
return 0;
@@ -714,8 +702,7 @@
.runtime_suspend = msm_fb_runtime_suspend,
.runtime_resume = msm_fb_runtime_resume,
.runtime_idle = msm_fb_runtime_idle,
-#if (defined(CONFIG_SUSPEND) && defined(CONFIG_FB_MSM_HDMI_MSM_PANEL) && \
- !defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY))
+#if (defined(CONFIG_SUSPEND) && defined(CONFIG_FB_MSM_HDMI_MSM_PANEL))
.suspend = msm_fb_ext_suspend,
.resume = msm_fb_ext_resume,
#endif
@@ -749,9 +736,7 @@
static void msmfb_early_suspend(struct early_suspend *h)
{
struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
- early_suspend);
- struct msm_fb_panel_data *pdata = NULL;
-
+ early_suspend);
#if defined(CONFIG_FB_MSM_MDP303)
/*
* For MDP with overlay, set framebuffer with black pixels
@@ -769,37 +754,12 @@
}
#endif
msm_fb_suspend_sub(mfd);
-
- pdata = (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
- if (hdmi_prim_display &&
- (mfd->panel_info.type == HDMI_PANEL ||
- mfd->panel_info.type == DTV_PANEL)) {
- /* Turn off the HPD circuitry */
- if (pdata->power_ctrl) {
- MSM_FB_INFO("%s: Turning off HPD circuitry\n",
- __func__);
- pdata->power_ctrl(FALSE);
- }
- }
}
static void msmfb_early_resume(struct early_suspend *h)
{
struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
- early_suspend);
- struct msm_fb_panel_data *pdata = NULL;
-
- pdata = (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
- if (hdmi_prim_display &&
- (mfd->panel_info.type == HDMI_PANEL ||
- mfd->panel_info.type == DTV_PANEL)) {
- /* Turn on the HPD circuitry */
- if (pdata->power_ctrl) {
- MSM_FB_INFO("%s: Turning on HPD circuitry\n", __func__);
- pdata->power_ctrl(TRUE);
- }
- }
-
+ early_suspend);
msm_fb_resume_sub(mfd);
}
#endif
@@ -1510,10 +1470,7 @@
ret = 0;
#ifdef CONFIG_HAS_EARLYSUSPEND
-
- if (hdmi_prim_display ||
- (mfd->panel_info.type != DTV_PANEL &&
- mfd->panel_info.type != WRITEBACK_PANEL)) {
+ if (mfd->panel_info.type != DTV_PANEL) {
mfd->early_suspend.suspend = msmfb_early_suspend;
mfd->early_suspend.resume = msmfb_early_resume;
mfd->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 2;
@@ -3279,7 +3236,9 @@
ret = wait_for_completion_interruptible_timeout(
&mfd->msmfb_no_update_notify, 4*HZ);
}
- return (ret > 0) ? 0 : -1;
+ if (ret == 0)
+ ret = -ETIMEDOUT;
+ return (ret > 0) ? 0 : ret;
}
static int msmfb_handle_pp_ioctl(struct msm_fb_data_type *mfd,
diff --git a/drivers/video/msm/msm_fb.h b/drivers/video/msm/msm_fb.h
index 1594825..2fd25cc 100644
--- a/drivers/video/msm/msm_fb.h
+++ b/drivers/video/msm/msm_fb.h
@@ -125,6 +125,7 @@
__u32 channel_irq;
struct mdp_dma_data *dma;
+ struct device_attribute dev_attr;
void (*dma_fnc) (struct msm_fb_data_type *mfd);
int (*cursor_update) (struct fb_info *info,
struct fb_cursor *cursor);
@@ -135,6 +136,8 @@
int (*start_histogram) (struct mdp_histogram_start_req *req);
int (*stop_histogram) (struct fb_info *info, uint32_t block);
void (*vsync_ctrl) (int enable);
+ void (*vsync_init) (int cndx);
+ void *vsync_show;
void *cursor_buf;
void *cursor_buf_phys;
@@ -190,6 +193,7 @@
unsigned char *copy_splash_phys;
void *cpu_pm_hdl;
u32 avtimer_phy;
+ int vsync_sysfs_created;
};
struct dentry *msm_fb_get_debugfs_root(void);
@@ -214,8 +218,7 @@
void msm_fb_config_backlight(struct msm_fb_data_type *mfd);
#endif
-void fill_black_screen(void);
-void unfill_black_screen(void);
+void fill_black_screen(bool on, uint8 pipe_num, uint8 mixer_num);
int msm_fb_check_frame_rate(struct msm_fb_data_type *mfd,
struct fb_info *info);
diff --git a/drivers/video/msm/msm_fb_panel.h b/drivers/video/msm/msm_fb_panel.h
index 7fc7a2f..bdd4f3bb 100644
--- a/drivers/video/msm/msm_fb_panel.h
+++ b/drivers/video/msm/msm_fb_panel.h
@@ -56,6 +56,11 @@
MAX_PHYS_TARGET_NUM,
} DISP_TARGET_PHYS;
+enum {
+ BLT_SWITCH_TG_OFF,
+ BLT_SWITCH_TG_ON
+};
+
/* panel info type */
struct lcd_panel_info {
__u32 vsync_enable;
@@ -65,6 +70,7 @@
__u32 v_pulse_width;
__u32 hw_vsync_mode;
__u32 vsync_notifier_period;
+ __u32 blt_ctrl;
__u32 rev;
};
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
index d5b195d..a82feb9 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.c
@@ -198,7 +198,8 @@
ddl->client_state = DDL_CLIENT_OPEN;
ddl->codec_data.hdr.decoding = decoding;
ddl->decoding = decoding;
- ddl_set_default_meta_data_hdr(ddl);
+ if (!res_trk_check_for_sec_session())
+ ddl_set_default_meta_data_hdr(ddl);
ddl_set_initial_default_values(ddl);
*ddl_handle = (u32 *) ddl;
} else {
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
index 2af76f3..3646e8c 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_errors.c
@@ -218,6 +218,7 @@
}
break;
}
+ case VIDC_1080P_ERROR_NON_IDR_FRAME_TYPE:
case VIDC_1080P_ERROR_BIT_STREAM_BUF_EXHAUST:
case VIDC_1080P_ERROR_DESCRIPTOR_TABLE_ENTRY_INVALID:
case VIDC_1080P_ERROR_MB_COEFF_NOT_DONE:
@@ -243,14 +244,16 @@
case VIDC_1080P_ERROR_NON_PAIRED_FIELD_NOT_SUPPORTED:
case VIDC_1080P_ERROR_DESCRIPTOR_BUFFER_EMPTY:
vcd_status = VCD_ERR_BITSTREAM_ERR;
- DDL_MSG_ERROR("VIDC_BIT_STREAM_ERR");
+ DDL_MSG_ERROR("VIDC_BIT_STREAM_ERR (%u)",
+ (u32)ddl_context->cmd_err_status);
break;
case VIDC_1080P_ERROR_B_FRAME_NOT_SUPPORTED:
case VIDC_1080P_ERROR_UNSUPPORTED_FEATURE_IN_PROFILE:
case VIDC_1080P_ERROR_RESOLUTION_NOT_SUPPORTED:
if (ddl->decoding) {
vcd_status = VCD_ERR_BITSTREAM_ERR;
- DDL_MSG_ERROR("VIDC_BIT_STREAM_ERR");
+ DDL_MSG_ERROR("VIDC_BIT_STREAM_ERR (%u)",
+ (u32)ddl_context->cmd_err_status);
}
break;
default:
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
index 8cfa95b..2c41ab4 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
@@ -493,6 +493,7 @@
ddl_get_state_string(ddl->client_state));
ddl_calc_core_proc_time(__func__, DEC_OP_TIME, ddl);
ddl_reset_core_time_variables(DEC_OP_TIME);
+ ddl_vidc_decode_reset_avg_time(ddl);
ddl->client_state = DDL_CLIENT_WAIT_FOR_FRAME;
ddl_vidc_decode_frame_run(ddl);
ret_status = false;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
index 31f60e5..4b5fbf5 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_utils.c
@@ -13,7 +13,7 @@
#include <linux/memory_alloc.h>
#include <linux/delay.h>
#include <mach/msm_subsystem_map.h>
-#include <mach/peripheral-loader.h>
+#include <mach/subsystem_restart.h>
#include "vcd_ddl_utils.h"
#include "vcd_ddl.h"
#include "vcd_res_tracker_api.h"
@@ -70,7 +70,7 @@
alloc_size = (alloc_size+4095) & ~4095;
addr->alloc_handle = ion_alloc(
ddl_context->video_ion_client, alloc_size, SZ_4K,
- res_trk_get_mem_type(), 0);
+ res_trk_get_mem_type(), res_trk_get_ion_flags());
if (IS_ERR_OR_NULL(addr->alloc_handle)) {
DDL_MSG_ERROR("%s() :DDL ION alloc failed\n",
__func__);
@@ -361,12 +361,12 @@
pr_err("Failed to enable iommu clocks\n");
return false;
}
- dram_base->pil_cookie = pil_get("vidc");
+ dram_base->pil_cookie = subsystem_get("vidc");
if (res_trk_disable_iommu_clocks())
pr_err("Failed to disable iommu clocks\n");
if (IS_ERR_OR_NULL(dram_base->pil_cookie)) {
res_trk_disable_footswitch();
- pr_err("pil_get failed\n");
+ pr_err("subsystem_get failed\n");
return false;
}
} else {
@@ -398,7 +398,7 @@
pr_err("Failed to enable iommu clocks\n");
return;
}
- pil_put(cookie);
+ subsystem_put(cookie);
if (res_trk_disable_iommu_clocks())
pr_err("Failed to disable iommu clocks\n");
if (res_trk_disable_footswitch())
diff --git a/drivers/video/msm/vidc/1080p/ddl/vidc.h b/drivers/video/msm/vidc/1080p/ddl/vidc.h
index 22fcd1c..117612b 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vidc.h
+++ b/drivers/video/msm/vidc/1080p/ddl/vidc.h
@@ -103,6 +103,7 @@
#define VIDC_1080P_ERROR_SPS_PARSE_ERROR 129
#define VIDC_1080P_ERROR_PPS_PARSE_ERROR 130
#define VIDC_1080P_ERROR_SLICE_PARSE_ERROR 131
+#define VIDC_1080P_ERROR_NON_IDR_FRAME_TYPE 132
#define VIDC_1080P_ERROR_SYNC_POINT_NOT_RECEIVED 171
#define VIDC_1080P_WARN_COMMAND_FLUSHED 145
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
index 0bc2228..d9cadef 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
@@ -209,7 +209,8 @@
addr->alloc_handle = ion_alloc(
ddl_context->video_ion_client,
alloc_size, SZ_4K,
- res_trk_get_mem_type(), 0);
+ res_trk_get_mem_type(),
+ res_trk_get_ion_flags());
if (IS_ERR_OR_NULL(addr->alloc_handle)) {
DDL_MSG_ERROR("%s() :DDL ION alloc failed\n",
__func__);
@@ -452,6 +453,10 @@
static struct ion_client *res_trk_create_ion_client(void){
struct ion_client *video_client;
video_client = msm_ion_client_create(-1, "video_client");
+ if (IS_ERR_OR_NULL(video_client)) {
+ VCDRES_MSG_ERROR("%s: Unable to create ION client\n", __func__);
+ video_client = NULL;
+ }
return video_client;
}
@@ -826,17 +831,31 @@
if (resource_context.vidc_platform_data->enable_ion) {
if (res_trk_check_for_sec_session()) {
mem_type = ION_HEAP(mem_type);
- if (resource_context.res_mem_type != DDL_FW_MEM)
- mem_type |= ION_SECURE;
- else if (res_trk_is_cp_enabled())
- mem_type |= ION_SECURE;
} else
mem_type = (ION_HEAP(mem_type) |
ION_HEAP(ION_IOMMU_HEAP_ID));
}
+
return mem_type;
}
+unsigned int res_trk_get_ion_flags(void)
+{
+ unsigned int flags = 0;
+ if (resource_context.res_mem_type == DDL_FW_MEM)
+ return flags;
+
+ if (resource_context.vidc_platform_data->enable_ion) {
+ if (res_trk_check_for_sec_session()) {
+ if (resource_context.res_mem_type != DDL_FW_MEM)
+ flags |= ION_SECURE;
+ else if (res_trk_is_cp_enabled())
+ flags |= ION_SECURE;
+ }
+ }
+ return flags;
+}
+
u32 res_trk_is_cp_enabled(void)
{
if (resource_context.vidc_platform_data->cp_enabled)
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker_api.h b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker_api.h
index 2ae2512..ee876f4 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker_api.h
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker_api.h
@@ -30,6 +30,7 @@
u32 res_trk_get_core_type(void);
u32 res_trk_get_firmware_addr(struct ddl_buf_addr *firm_addr);
int res_trk_get_mem_type(void);
+unsigned int res_trk_get_ion_flags(void);
u32 res_trk_get_enable_ion(void);
u32 res_trk_is_cp_enabled(void);
u32 res_trk_get_disable_fullhd(void);
diff --git a/drivers/video/msm/vidc/720p/ddl/vcd_ddl_utils.c b/drivers/video/msm/vidc/720p/ddl/vcd_ddl_utils.c
index 3b40640..9fb8162 100644
--- a/drivers/video/msm/vidc/720p/ddl/vcd_ddl_utils.c
+++ b/drivers/video/msm/vidc/720p/ddl/vcd_ddl_utils.c
@@ -125,9 +125,8 @@
alloc_size,
SZ_4K,
buff_addr->mem_type, 0);
- if (!buff_addr->alloc_handle) {
- ERR("\n%s(): DDL ION alloc failed\n",
- __func__);
+ if (IS_ERR_OR_NULL(buff_addr->alloc_handle)) {
+ ERR("\n%s(): DDL ION alloc failed\n", __func__);
goto bailout;
}
ret = ion_phys(ddl_context->video_ion_client,
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
index aee9dfe..c83faa6 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
@@ -681,6 +681,10 @@
struct ion_client *video_client;
VCDRES_MSG_LOW("%s", __func__);
video_client = msm_ion_client_create(-1, "video_client");
+ if (IS_ERR_OR_NULL(video_client)) {
+ VCDRES_MSG_ERROR("%s: Unable to create ION client\n", __func__);
+ video_client = NULL;
+ }
return video_client;
}
@@ -760,6 +764,11 @@
return 0;
}
+u32 res_trk_get_ion_flags(void)
+{
+ return 0;
+}
+
int res_trk_check_for_sec_session()
{
return 0;
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker_api.h b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker_api.h
index 75fdb3e..a20d9f2 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker_api.h
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker_api.h
@@ -29,6 +29,7 @@
u32 res_trk_get_core_type(void);
u32 res_trk_get_mem_type(void);
u32 res_trk_get_disable_fullhd(void);
+u32 res_trk_get_ion_flags(void);
u32 res_trk_get_enable_ion(void);
u32 res_trk_is_cp_enabled(void);
struct ion_client *res_trk_get_ion_client(void);
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_sub.c b/drivers/video/msm/vidc/common/vcd/vcd_sub.c
index 5fdee02..a9709fb 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_sub.c
+++ b/drivers/video/msm/vidc/common/vcd/vcd_sub.c
@@ -92,8 +92,8 @@
} else {
map_buffer->alloc_handle = ion_alloc(
cctxt->vcd_ion_client, sz, SZ_4K,
- memtype, 0);
- if (!map_buffer->alloc_handle) {
+ memtype, res_trk_get_ion_flags());
+ if (IS_ERR_OR_NULL(map_buffer->alloc_handle)) {
pr_err("%s() ION alloc failed", __func__);
goto bailout;
}
diff --git a/include/drm/kgsl_drm.h b/include/drm/kgsl_drm.h
index f1c7f4e..7ffae9d 100644
--- a/include/drm/kgsl_drm.h
+++ b/include/drm/kgsl_drm.h
@@ -19,6 +19,7 @@
#define DRM_KGSL_GEM_UNLOCK_HANDLE 0x0C
#define DRM_KGSL_GEM_UNLOCK_ON_TS 0x0D
#define DRM_KGSL_GEM_CREATE_FD 0x0E
+#define DRM_KGSL_GEM_GET_ION_FD 0x0F
#define DRM_IOCTL_KGSL_GEM_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE, struct drm_kgsl_gem_create)
@@ -75,6 +76,10 @@
DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FD, \
struct drm_kgsl_gem_create_fd)
+#define DRM_IOCTL_KGSL_GEM_GET_ION_FD \
+DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_ION_FD, \
+struct drm_kgsl_gem_get_ion_fd)
+
/* Maximum number of sub buffers per GEM object */
#define DRM_KGSL_GEM_MAX_BUFFERS 2
@@ -189,4 +194,9 @@
uint32_t handle;
};
+struct drm_kgsl_gem_get_ion_fd {
+ uint32_t ion_fd;
+ uint32_t handle;
+};
+
#endif
diff --git a/include/linux/coresight-stm.h b/include/linux/coresight-stm.h
index bb3ebca..b156eba 100644
--- a/include/linux/coresight-stm.h
+++ b/include/linux/coresight-stm.h
@@ -1,5 +1,5 @@
-#ifndef __MACH_STM_H
-#define __MACH_STM_H
+#ifndef _LINUX_CORESIGHT_STM_H
+#define _LINUX_CORESIGHT_STM_H
enum {
OST_ENTITY_NONE = 0x00,
@@ -7,7 +7,8 @@
OST_ENTITY_TRACE_PRINTK = 0x02,
OST_ENTITY_TRACE_MARKER = 0x04,
OST_ENTITY_DEV_NODE = 0x08,
- OST_ENTITY_ALL = 0x1F,
+ OST_ENTITY_QVIEW = 0xFE,
+ OST_ENTITY_MAX = 0xFF,
};
enum {
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index bb5f394..43daaf2 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -43,6 +43,7 @@
#define DIAG_IOCTL_DCI_REG 23
#define DIAG_IOCTL_DCI_STREAM_INIT 24
#define DIAG_IOCTL_DCI_HEALTH_STATS 25
+#define DIAG_IOCTL_REMOTE_DEV 32
/* PC Tools IDs */
#define APQ8060_TOOLS_ID 4062
@@ -674,18 +675,18 @@
};
static const uint32_t msg_bld_masks_22[] = {
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW
};
/* LOG CODES */
diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h
index 547ab56..18513e3 100644
--- a/include/linux/dma-attrs.h
+++ b/include/linux/dma-attrs.h
@@ -15,6 +15,8 @@
DMA_ATTR_WEAK_ORDERING,
DMA_ATTR_WRITE_COMBINE,
DMA_ATTR_NON_CONSISTENT,
+ DMA_ATTR_NO_KERNEL_MAPPING,
+ DMA_ATTR_STRONGLY_ORDERED,
DMA_ATTR_MAX,
};
diff --git a/include/linux/i2c/atmel_mxt_ts.h b/include/linux/i2c/atmel_mxt_ts.h
index 348a231..fe23993 100644
--- a/include/linux/i2c/atmel_mxt_ts.h
+++ b/include/linux/i2c/atmel_mxt_ts.h
@@ -74,6 +74,7 @@
u32 irq_gpio_flags;
int *key_codes;
bool need_calibration;
+ bool no_force_update;
u8(*read_chg) (void);
int (*init_hw) (bool);
diff --git a/include/linux/i2c/ti_drv2667.h b/include/linux/i2c/ti_drv2667.h
new file mode 100644
index 0000000..0ae0e5e
--- /dev/null
+++ b/include/linux/i2c/ti_drv2667.h
@@ -0,0 +1,26 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __TI_DRV2667__
+
+#define DRV2667_WAV_SEQ_LEN 11
+
+struct drv2667_pdata {
+ const char *name;
+ u8 mode;
+ /* support one waveform for now */
+ u8 wav_seq[DRV2667_WAV_SEQ_LEN];
+ u8 gain;
+ u8 idle_timeout_ms;
+ u32 max_runtime_ms;
+};
+#endif
diff --git a/include/linux/ion.h b/include/linux/ion.h
index 85e5002..211327f 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -222,11 +222,9 @@
* ion_map_kernel - create mapping for the given handle
* @client: the client
* @handle: handle to map
- * @flags: flags for this mapping
*
* Map the given handle into the kernel and return a kernel address that
- * can be used to access this address. If no flags are specified, this
- * will return a non-secure uncached mapping.
+ * can be used to access this address.
*/
void *ion_map_kernel(struct ion_client *client, struct ion_handle *handle);
@@ -418,7 +416,7 @@
}
static inline void *ion_map_kernel(struct ion_client *client,
- struct ion_handle *handle, unsigned long flags)
+ struct ion_handle *handle)
{
return ERR_PTR(-ENODEV);
}
@@ -453,6 +451,12 @@
return -ENODEV;
}
+static inline int ion_handle_get_size(struct ion_client *client,
+ struct ion_handle *handle, unsigned long *size)
+{
+ return -ENODEV;
+}
+
static inline void ion_unmap_iommu(struct ion_client *client,
struct ion_handle *handle, int domain_num,
int partition_num)
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index f581c8f..37b1fdc 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -486,7 +486,7 @@
__attribute__((section("__trace_printk_fmt"))) = \
__builtin_constant_p(fmt) ? fmt : NULL; \
\
- __trace_bprintk(_THIS_IP_, trace_printk_fmt, ##args); \
+ __trace_printk(_THIS_IP_, trace_printk_fmt, ##args); \
} else \
__trace_printk(_THIS_IP_, fmt, ##args); \
} while (0)
diff --git a/include/linux/mfd/pm8xxx/batterydata-lib.h b/include/linux/mfd/pm8xxx/batterydata-lib.h
index c55e47e..afa1843 100644
--- a/include/linux/mfd/pm8xxx/batterydata-lib.h
+++ b/include/linux/mfd/pm8xxx/batterydata-lib.h
@@ -102,7 +102,8 @@
};
#if defined(CONFIG_PM8921_BMS) || \
- defined(CONFIG_PM8921_BMS_MODULE)
+ defined(CONFIG_PM8921_BMS_MODULE) || \
+ defined(CONFIG_QPNP_BMS)
extern struct bms_battery_data palladium_1500_data;
extern struct bms_battery_data desay_5200_data;
diff --git a/include/linux/mfd/pm8xxx/ccadc.h b/include/linux/mfd/pm8xxx/ccadc.h
index 29f7a62..fc31f89 100644
--- a/include/linux/mfd/pm8xxx/ccadc.h
+++ b/include/linux/mfd/pm8xxx/ccadc.h
@@ -19,11 +19,11 @@
/**
* struct pm8xxx_ccadc_platform_data -
- * @r_sense: sense resistor value in (mOhms)
+ * @r_sense_uohm: sense resistor value in (micro Ohms)
* @calib_delay_ms: how often should the adc calculate gain and offset
*/
struct pm8xxx_ccadc_platform_data {
- int r_sense;
+ int r_sense_uohm;
unsigned int calib_delay_ms;
};
diff --git a/include/linux/mfd/pm8xxx/pm8038.h b/include/linux/mfd/pm8xxx/pm8038.h
index 574dab6..9e25b5c 100644
--- a/include/linux/mfd/pm8xxx/pm8038.h
+++ b/include/linux/mfd/pm8xxx/pm8038.h
@@ -83,6 +83,7 @@
struct pm8921_bms_platform_data *bms_pdata;
struct pm8xxx_adc_platform_data *adc_pdata;
struct pm8xxx_led_platform_data *leds_pdata;
+ struct pm8xxx_vibrator_platform_data *vibrator_pdata;
struct pm8xxx_ccadc_platform_data *ccadc_pdata;
struct pm8xxx_spk_platform_data *spk_pdata;
};
diff --git a/include/linux/mfd/pm8xxx/pm8921-bms.h b/include/linux/mfd/pm8xxx/pm8921-bms.h
index 5f2fe9f..82ec57d 100644
--- a/include/linux/mfd/pm8xxx/pm8921-bms.h
+++ b/include/linux/mfd/pm8xxx/pm8921-bms.h
@@ -30,7 +30,7 @@
/**
* struct pm8921_bms_platform_data -
* @batt_type: allows to force chose battery calibration data
- * @r_sense: sense resistor value in (mOhms)
+ * @r_sense_uohm: sense resistor value in (micro Ohms)
* @i_test: current at which the unusable charger cutoff is to be
* calculated or the peak system current (mA)
* @v_cutoff: the loaded voltage at which the battery
@@ -41,7 +41,7 @@
struct pm8921_bms_platform_data {
struct pm8xxx_bms_core_data bms_cdata;
enum battery_type battery_type;
- unsigned int r_sense;
+ int r_sense_uohm;
unsigned int i_test;
unsigned int v_cutoff;
unsigned int max_voltage_uv;
@@ -127,6 +127,15 @@
* soc stored in a coincell backed register
*/
void pm8921_bms_invalidate_shutdown_soc(void);
+
+/**
+ * pm8921_bms_cc_uah - function to get the coulomb counter based charge. Note
+ * that the coulomb counter are reset when the current
+ * consumption is low (below 8mA for more than 5 minutes),
+ * This will lead in a very low coulomb counter charge
+ * value upon wakeup from sleep.
+ */
+int pm8921_bms_cc_uah(int *cc_uah);
#else
static inline int pm8921_bms_get_vsense_avg(int *result)
{
@@ -165,6 +174,10 @@
static inline void pm8921_bms_invalidate_shutdown_soc(void)
{
}
+static inline int pm8921_bms_cc_uah(int *cc_uah)
+{
+ return -ENXIO;
+}
#endif
#endif
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 130fb54..4ad55f4 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -58,7 +58,6 @@
/**
* struct pm8921_charger_platform_data -
- * @safety_time: max charging time in minutes incl. fast and trkl
* valid range 4 to 512 min. PON default 120 min
* @ttrkl_time: max trckl charging time in minutes
* valid range 1 to 64 mins. PON default 15 min
@@ -70,6 +69,9 @@
* trickle to fast. This is also the minimum voltage the
* system operates at
* @uvd_thresh_voltage: the USB falling UVD threshold (mV) (PM8917 only)
+ * @safe_current_ma: The upper limit of current allowed to be pushed in
+ * battery. This ends up writing in a one time
+ * programmable register.
* @resume_voltage_delta: the (mV) drop to wait for before resume charging
* after the battery has been fully charged
* @resume_charge_percent: the % SOC the charger will drop to after the
@@ -127,12 +129,12 @@
*/
struct pm8921_charger_platform_data {
struct pm8xxx_charger_core_data charger_cdata;
- unsigned int safety_time;
unsigned int ttrkl_time;
unsigned int update_time;
unsigned int max_voltage;
unsigned int min_voltage;
unsigned int uvd_thresh_voltage;
+ unsigned int safe_current_ma;
unsigned int alarm_low_mv;
unsigned int alarm_high_mv;
unsigned int resume_voltage_delta;
diff --git a/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h b/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h
index 4b7a32c..a1609b8 100644
--- a/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h
+++ b/include/linux/mfd/wcd9xxx/wcd9xxx_registers.h
@@ -202,5 +202,7 @@
#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00)
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00)
+#define WCD9XXX_A_MAD_ANA_CTRL (0x150)
+#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1)
#endif
diff --git a/include/linux/mhl_8334.h b/include/linux/mhl_8334.h
index cb9d7fa..c9f57c5 100644
--- a/include/linux/mhl_8334.h
+++ b/include/linux/mhl_8334.h
@@ -130,4 +130,162 @@
DEV_PAGE_DDC_SEGM = (0x60),
};
+#define MHL_SII_PAGE0_RD(off) \
+ mhl_i2c_reg_read(client, TX_PAGE_L0, off)
+#define MHL_SII_PAGE0_WR(off, val) \
+ mhl_i2c_reg_write(client, TX_PAGE_L0, off, val)
+#define MHL_SII_PAGE0_MOD(off, mask, val) \
+ mhl_i2c_reg_modify(client, TX_PAGE_L0, off, mask, val)
+
+
+#define MHL_SII_PAGE1_RD(off) \
+ mhl_i2c_reg_read(client, TX_PAGE_L1, off)
+#define MHL_SII_PAGE1_WR(off, val) \
+ mhl_i2c_reg_write(client, TX_PAGE_L1, off, val)
+#define MHL_SII_PAGE1_MOD(off, mask, val) \
+ mhl_i2c_reg_modify(client, TX_PAGE_L1, off, mask, val)
+
+
+#define MHL_SII_PAGE2_RD(off) \
+ mhl_i2c_reg_read(client, TX_PAGE_2, off)
+#define MHL_SII_PAGE2_WR(off, val) \
+ mhl_i2c_reg_write(client, TX_PAGE_2, off, val)
+#define MHL_SII_PAGE2_MOD(off, mask, val) \
+ mhl_i2c_reg_modify(client, TX_PAGE_2, off, mask, val)
+
+
+#define MHL_SII_PAGE3_RD(off) \
+ mhl_i2c_reg_read(client, TX_PAGE_3, off)
+#define MHL_SII_PAGE3_WR(off, val) \
+ mhl_i2c_reg_write(client, TX_PAGE_3, off, val)
+#define MHL_SII_PAGE3_MOD(off, mask, val) \
+ mhl_i2c_reg_modify(client, TX_PAGE_3, off, mask, val)
+
+#define MHL_SII_CBUS_RD(off) \
+ mhl_i2c_reg_read(client, TX_PAGE_CBUS, off)
+#define MHL_SII_CBUS_WR(off, val) \
+ mhl_i2c_reg_write(client, TX_PAGE_CBUS, off, val)
+#define MHL_SII_CBUS_MOD(off, mask, val) \
+ mhl_i2c_reg_modify(client, TX_PAGE_CBUS, off, mask, val)
+
+#define REG_SRST ((TX_PAGE_3 << 16) | 0x0000)
+#define REG_INTR1 ((TX_PAGE_L0 << 16) | 0x0071)
+#define REG_INTR1_MASK ((TX_PAGE_L0 << 16) | 0x0075)
+#define REG_INTR2 ((TX_PAGE_L0 << 16) | 0x0072)
+#define REG_TMDS_CCTRL ((TX_PAGE_L0 << 16) | 0x0080)
+
+#define REG_DISC_CTRL1 ((TX_PAGE_3 << 16) | 0x0010)
+#define REG_DISC_CTRL2 ((TX_PAGE_3 << 16) | 0x0011)
+#define REG_DISC_CTRL3 ((TX_PAGE_3 << 16) | 0x0012)
+#define REG_DISC_CTRL4 ((TX_PAGE_3 << 16) | 0x0013)
+#define REG_DISC_CTRL5 ((TX_PAGE_3 << 16) | 0x0014)
+#define REG_DISC_CTRL6 ((TX_PAGE_3 << 16) | 0x0015)
+#define REG_DISC_CTRL7 ((TX_PAGE_3 << 16) | 0x0016)
+#define REG_DISC_CTRL8 ((TX_PAGE_3 << 16) | 0x0017)
+#define REG_DISC_CTRL9 ((TX_PAGE_3 << 16) | 0x0018)
+#define REG_DISC_CTRL10 ((TX_PAGE_3 << 16) | 0x0019)
+#define REG_DISC_CTRL11 ((TX_PAGE_3 << 16) | 0x001A)
+#define REG_DISC_STAT ((TX_PAGE_3 << 16) | 0x001B)
+#define REG_DISC_STAT2 ((TX_PAGE_3 << 16) | 0x001C)
+
+#define REG_INT_CTRL ((TX_PAGE_3 << 16) | 0x0020)
+#define REG_INTR4 ((TX_PAGE_3 << 16) | 0x0021)
+#define REG_INTR4_MASK ((TX_PAGE_3 << 16) | 0x0022)
+#define REG_INTR5 ((TX_PAGE_3 << 16) | 0x0023)
+#define REG_INTR5_MASK ((TX_PAGE_3 << 16) | 0x0024)
+
+#define REG_MHLTX_CTL1 ((TX_PAGE_3 << 16) | 0x0030)
+#define REG_MHLTX_CTL2 ((TX_PAGE_3 << 16) | 0x0031)
+#define REG_MHLTX_CTL3 ((TX_PAGE_3 << 16) | 0x0032)
+#define REG_MHLTX_CTL4 ((TX_PAGE_3 << 16) | 0x0033)
+#define REG_MHLTX_CTL5 ((TX_PAGE_3 << 16) | 0x0034)
+#define REG_MHLTX_CTL6 ((TX_PAGE_3 << 16) | 0x0035)
+#define REG_MHLTX_CTL7 ((TX_PAGE_3 << 16) | 0x0036)
+#define REG_MHLTX_CTL8 ((TX_PAGE_3 << 16) | 0x0037)
+
+#define REG_TMDS_CSTAT ((TX_PAGE_3 << 16) | 0x0040)
+
+#define REG_CBUS_INTR_ENABLE ((TX_PAGE_CBUS << 16) | 0x0009)
+
+#define REG_DDC_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000B)
+#define REG_CBUS_BUS_STATUS ((TX_PAGE_CBUS << 16) | 0x000A)
+#define REG_PRI_XFR_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000D)
+#define REG_CBUS_PRI_FWR_ABORT_REASON ((TX_PAGE_CBUS << 16) | 0x000E)
+#define REG_CBUS_PRI_START ((TX_PAGE_CBUS << 16) | 0x0012)
+#define REG_CBUS_PRI_ADDR_CMD ((TX_PAGE_CBUS << 16) | 0x0013)
+#define REG_CBUS_PRI_WR_DATA_1ST ((TX_PAGE_CBUS << 16) | 0x0014)
+#define REG_CBUS_PRI_WR_DATA_2ND ((TX_PAGE_CBUS << 16) | 0x0015)
+#define REG_CBUS_PRI_RD_DATA_1ST ((TX_PAGE_CBUS << 16) | 0x0016)
+#define REG_CBUS_PRI_RD_DATA_2ND ((TX_PAGE_CBUS << 16) | 0x0017)
+#define REG_CBUS_PRI_VS_CMD ((TX_PAGE_CBUS << 16) | 0x0018)
+#define REG_CBUS_PRI_VS_DATA ((TX_PAGE_CBUS << 16) | 0x0019)
+#define REG_CBUS_MSC_RETRY_INTERVAL ((TX_PAGE_CBUS << 16) | 0x001A)
+#define REG_CBUS_DDC_FAIL_LIMIT ((TX_PAGE_CBUS << 16) | 0x001C)
+#define REG_CBUS_MSC_FAIL_LIMIT ((TX_PAGE_CBUS << 16) | 0x001D)
+#define REG_CBUS_MSC_INT2_STATUS ((TX_PAGE_CBUS << 16) | 0x001E)
+#define REG_CBUS_MSC_INT2_ENABLE ((TX_PAGE_CBUS << 16) | 0x001F)
+#define REG_MSC_WRITE_BURST_LEN ((TX_PAGE_CBUS << 16) | 0x0020)
+#define REG_MSC_HEARTBEAT_CONTROL ((TX_PAGE_CBUS << 16) | 0x0021)
+#define REG_MSC_TIMEOUT_LIMIT ((TX_PAGE_CBUS << 16) | 0x0022)
+#define REG_CBUS_LINK_CONTROL_1 ((TX_PAGE_CBUS << 16) | 0x0030)
+#define REG_CBUS_LINK_CONTROL_2 ((TX_PAGE_CBUS << 16) | 0x0031)
+#define REG_CBUS_LINK_CONTROL_3 ((TX_PAGE_CBUS << 16) | 0x0032)
+#define REG_CBUS_LINK_CONTROL_4 ((TX_PAGE_CBUS << 16) | 0x0033)
+#define REG_CBUS_LINK_CONTROL_5 ((TX_PAGE_CBUS << 16) | 0x0034)
+#define REG_CBUS_LINK_CONTROL_6 ((TX_PAGE_CBUS << 16) | 0x0035)
+#define REG_CBUS_LINK_CONTROL_7 ((TX_PAGE_CBUS << 16) | 0x0036)
+#define REG_CBUS_LINK_STATUS_1 ((TX_PAGE_CBUS << 16) | 0x0037)
+#define REG_CBUS_LINK_STATUS_2 ((TX_PAGE_CBUS << 16) | 0x0038)
+#define REG_CBUS_LINK_CONTROL_8 ((TX_PAGE_CBUS << 16) | 0x0039)
+#define REG_CBUS_LINK_CONTROL_9 ((TX_PAGE_CBUS << 16) | 0x003A)
+#define REG_CBUS_LINK_CONTROL_10 ((TX_PAGE_CBUS << 16) | 0x003B)
+#define REG_CBUS_LINK_CONTROL_11 ((TX_PAGE_CBUS << 16) | 0x003C)
+#define REG_CBUS_LINK_CONTROL_12 ((TX_PAGE_CBUS << 16) | 0x003D)
+
+
+#define REG_CBUS_LINK_CTRL9_0 ((TX_PAGE_CBUS << 16) | 0x003A)
+#define REG_CBUS_LINK_CTRL9_1 ((TX_PAGE_CBUS << 16) | 0x00BA)
+
+#define REG_CBUS_DRV_STRENGTH_0 ((TX_PAGE_CBUS << 16) | 0x0040)
+#define REG_CBUS_DRV_STRENGTH_1 ((TX_PAGE_CBUS << 16) | 0x0041)
+#define REG_CBUS_ACK_CONTROL ((TX_PAGE_CBUS << 16) | 0x0042)
+#define REG_CBUS_CAL_CONTROL ((TX_PAGE_CBUS << 16) | 0x0043)
+
+#define REG_CBUS_SCRATCHPAD_0 ((TX_PAGE_CBUS << 16) | 0x00C0)
+#define REG_CBUS_DEVICE_CAP_0 ((TX_PAGE_CBUS << 16) | 0x0080)
+#define REG_CBUS_DEVICE_CAP_1 ((TX_PAGE_CBUS << 16) | 0x0081)
+#define REG_CBUS_DEVICE_CAP_2 ((TX_PAGE_CBUS << 16) | 0x0082)
+#define REG_CBUS_DEVICE_CAP_3 ((TX_PAGE_CBUS << 16) | 0x0083)
+#define REG_CBUS_DEVICE_CAP_4 ((TX_PAGE_CBUS << 16) | 0x0084)
+#define REG_CBUS_DEVICE_CAP_5 ((TX_PAGE_CBUS << 16) | 0x0085)
+#define REG_CBUS_DEVICE_CAP_6 ((TX_PAGE_CBUS << 16) | 0x0086)
+#define REG_CBUS_DEVICE_CAP_7 ((TX_PAGE_CBUS << 16) | 0x0087)
+#define REG_CBUS_DEVICE_CAP_8 ((TX_PAGE_CBUS << 16) | 0x0088)
+#define REG_CBUS_DEVICE_CAP_9 ((TX_PAGE_CBUS << 16) | 0x0089)
+#define REG_CBUS_DEVICE_CAP_A ((TX_PAGE_CBUS << 16) | 0x008A)
+#define REG_CBUS_DEVICE_CAP_B ((TX_PAGE_CBUS << 16) | 0x008B)
+#define REG_CBUS_DEVICE_CAP_C ((TX_PAGE_CBUS << 16) | 0x008C)
+#define REG_CBUS_DEVICE_CAP_D ((TX_PAGE_CBUS << 16) | 0x008D)
+#define REG_CBUS_DEVICE_CAP_E ((TX_PAGE_CBUS << 16) | 0x008E)
+#define REG_CBUS_DEVICE_CAP_F ((TX_PAGE_CBUS << 16) | 0x008F)
+#define REG_CBUS_SET_INT_0 ((TX_PAGE_CBUS << 16) | 0x00A0)
+#define REG_CBUS_SET_INT_1 ((TX_PAGE_CBUS << 16) | 0x00A1)
+#define REG_CBUS_SET_INT_2 ((TX_PAGE_CBUS << 16) | 0x00A2)
+#define REG_CBUS_SET_INT_3 ((TX_PAGE_CBUS << 16) | 0x00A3)
+#define REG_CBUS_WRITE_STAT_0 ((TX_PAGE_CBUS << 16) | 0x00B0)
+#define REG_CBUS_WRITE_STAT_1 ((TX_PAGE_CBUS << 16) | 0x00B1)
+#define REG_CBUS_WRITE_STAT_2 ((TX_PAGE_CBUS << 16) | 0x00B2)
+#define REG_CBUS_WRITE_STAT_3 ((TX_PAGE_CBUS << 16) | 0x00B3)
+
+#define GET_PAGE(x) (x >> 16)
+#define GET_OFF(x) (x & 0xffff)
+
+
+#define MHL_SII_REG_NAME_RD(arg)\
+ mhl_i2c_reg_read(client, GET_PAGE(arg), GET_OFF(arg))
+#define MHL_SII_REG_NAME_WR(arg, val)\
+ mhl_i2c_reg_write(client, GET_PAGE(arg), GET_OFF(arg), val)
+#define MHL_SII_REG_NAME_MOD(arg, mask, val)\
+ mhl_i2c_reg_modify(client, GET_PAGE(arg), GET_OFF(arg), mask, val)
+
#endif /* __MHL_MSM_H__ */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index ddfb7c5..48268f0 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1561,6 +1561,32 @@
#define in_gate_area(mm, addr) ({(void)mm; in_gate_area_no_mm(addr);})
#endif /* __HAVE_ARCH_GATE_AREA */
+#ifdef CONFIG_USE_USER_ACCESSIBLE_TIMERS
+static inline int use_user_accessible_timers(void) { return 1; }
+extern int in_user_timers_area(struct mm_struct *mm, unsigned long addr);
+extern struct vm_area_struct *get_user_timers_vma(struct mm_struct *mm);
+extern int get_user_timer_page(struct vm_area_struct *vma,
+ struct mm_struct *mm, unsigned long start, unsigned int gup_flags,
+ struct page **pages, int idx, int *goto_next_page);
+#else
+static inline int use_user_accessible_timers(void) { return 0; }
+static inline int in_user_timers_area(struct mm_struct *mm, unsigned long addr)
+{
+ return 0;
+}
+static inline struct vm_area_struct *get_user_timers_vma(struct mm_struct *mm)
+{
+ return NULL;
+}
+static inline int get_user_timer_page(struct vm_area_struct *vma,
+ struct mm_struct *mm, unsigned long start, unsigned int gup_flags,
+ struct page **pages, int idx, int *goto_next_page)
+{
+ *goto_next_page = 0;
+ return 0;
+}
+#endif
+
int drop_caches_sysctl_handler(struct ctl_table *, int,
void __user *, size_t *, loff_t *);
unsigned long shrink_slab(struct shrink_control *shrink,
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index fb854ba..2046198 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -324,6 +324,7 @@
#define MMC_QUIRK_BLK_NO_CMD23 (1<<7) /* Avoid CMD23 for regular multiblock */
#define MMC_QUIRK_BROKEN_BYTE_MODE_512 (1<<8) /* Avoid sending 512 bytes in */
#define MMC_QUIRK_LONG_READ_TIME (1<<9) /* Data read time > CSD says */
+#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */
/* byte mode */
#define MMC_QUIRK_INAND_DATA_TIMEOUT (1<<8) /* For incorrect data timeout */
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e9051e1..c5b492b 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -91,6 +91,7 @@
unsigned int quirks2; /* More deviations from spec. */
#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
+#define SDHCI_QUIRK2_OWN_CARD_DETECTION (1<<1)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index f8a3a10..08f74e6 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -61,6 +61,14 @@
MIGRATE_TYPES
};
+/*
+ * Returns a list which contains the migrate types on to which
+ * an allocation falls back when the free list for the migrate
+ * type mtype is depleted.
+ * The end of the list is delimited by the type MIGRATE_RESERVE.
+ */
+extern int *get_migratetype_fallbacks(int mtype);
+
#ifdef CONFIG_CMA
# define is_migrate_cma(migratetype) unlikely((migratetype) == MIGRATE_CMA)
# define cma_wmark_pages(zone) zone->min_cma_pages
diff --git a/include/linux/msm_ipa.h b/include/linux/msm_ipa.h
new file mode 100644
index 0000000..613cd9f
--- /dev/null
+++ b/include/linux/msm_ipa.h
@@ -0,0 +1,714 @@
+#ifndef _MSM_IPA_H_
+#define _MSM_IPA_H_
+
+#ifndef __KERNEL__
+#include <stdint.h>
+#include <stddef.h>
+#include <sys/stat.h>
+#endif
+#include <linux/ioctl.h>
+
+/**
+ * unique magic number of the IPA device
+ */
+#define IPA_IOC_MAGIC 0xCF
+
+/**
+ * name of the default routing tables for v4 and v6
+ */
+#define IPA_DFLT_RT_TBL_NAME "ipa_dflt_rt"
+
+/**
+ * the commands supported by IPA driver
+ */
+#define IPA_IOCTL_ADD_HDR 0
+#define IPA_IOCTL_DEL_HDR 1
+#define IPA_IOCTL_ADD_RT_RULE 2
+#define IPA_IOCTL_DEL_RT_RULE 3
+#define IPA_IOCTL_ADD_FLT_RULE 4
+#define IPA_IOCTL_DEL_FLT_RULE 5
+#define IPA_IOCTL_COMMIT_HDR 6
+#define IPA_IOCTL_RESET_HDR 7
+#define IPA_IOCTL_COMMIT_RT 8
+#define IPA_IOCTL_RESET_RT 9
+#define IPA_IOCTL_COMMIT_FLT 10
+#define IPA_IOCTL_RESET_FLT 11
+#define IPA_IOCTL_DUMP 12
+#define IPA_IOCTL_GET_RT_TBL 13
+#define IPA_IOCTL_PUT_RT_TBL 14
+#define IPA_IOCTL_COPY_HDR 15
+#define IPA_IOCTL_QUERY_INTF 16
+#define IPA_IOCTL_QUERY_INTF_TX_PROPS 17
+#define IPA_IOCTL_QUERY_INTF_RX_PROPS 18
+#define IPA_IOCTL_GET_HDR 19
+#define IPA_IOCTL_PUT_HDR 20
+#define IPA_IOCTL_SET_FLT 21
+#define IPA_IOCTL_ALLOC_NAT_MEM 22
+#define IPA_IOCTL_V4_INIT_NAT 23
+#define IPA_IOCTL_NAT_DMA 24
+#define IPA_IOCTL_V4_DEL_NAT 26
+#define IPA_IOCTL_GET_ASYNC_MSG 27
+#define IPA_IOCTL_GET_NAT_OFFSET 28
+#define IPA_IOCTL_MAX 29
+
+/**
+ * max size of the header to be inserted
+ */
+#define IPA_HDR_MAX_SIZE 64
+
+/**
+ * max size of the name of the resource (routing table, header)
+ */
+#define IPA_RESOURCE_NAME_MAX 20
+
+/**
+ * the attributes of the rule (routing or filtering)
+ */
+#define IPA_FLT_TOS (1ul << 0)
+#define IPA_FLT_PROTOCOL (1ul << 1)
+#define IPA_FLT_SRC_ADDR (1ul << 2)
+#define IPA_FLT_DST_ADDR (1ul << 3)
+#define IPA_FLT_SRC_PORT_RANGE (1ul << 4)
+#define IPA_FLT_DST_PORT_RANGE (1ul << 5)
+#define IPA_FLT_TYPE (1ul << 6)
+#define IPA_FLT_CODE (1ul << 7)
+#define IPA_FLT_SPI (1ul << 8)
+#define IPA_FLT_SRC_PORT (1ul << 9)
+#define IPA_FLT_DST_PORT (1ul << 10)
+#define IPA_FLT_TC (1ul << 11)
+#define IPA_FLT_FLOW_LABEL (1ul << 12)
+#define IPA_FLT_NEXT_HDR (1ul << 13)
+#define IPA_FLT_META_DATA (1ul << 14)
+#define IPA_FLT_FRAGMENT (1ul << 15)
+
+/**
+ * enum ipa_client_type - names for the various IPA "clients"
+ * these are from the perspective of the clients, for e.g.
+ * HSIC1_PROD means HSIC client is the producer and IPA is the
+ * consumer
+ */
+enum ipa_client_type {
+ IPA_CLIENT_PROD,
+ IPA_CLIENT_HSIC1_PROD = IPA_CLIENT_PROD,
+ IPA_CLIENT_HSIC2_PROD,
+ IPA_CLIENT_HSIC3_PROD,
+ IPA_CLIENT_HSIC4_PROD,
+ IPA_CLIENT_HSIC5_PROD,
+ IPA_CLIENT_USB_PROD,
+ IPA_CLIENT_A5_WLAN_AMPDU_PROD,
+ IPA_CLIENT_A2_EMBEDDED_PROD,
+ IPA_CLIENT_A2_TETHERED_PROD,
+ IPA_CLIENT_A5_LAN_WAN_PROD,
+ IPA_CLIENT_A5_CMD_PROD,
+ IPA_CLIENT_Q6_LAN_PROD,
+
+ IPA_CLIENT_CONS,
+ IPA_CLIENT_HSIC1_CONS = IPA_CLIENT_CONS,
+ IPA_CLIENT_HSIC2_CONS,
+ IPA_CLIENT_HSIC3_CONS,
+ IPA_CLIENT_HSIC4_CONS,
+ IPA_CLIENT_HSIC5_CONS,
+ IPA_CLIENT_USB_CONS,
+ IPA_CLIENT_A2_EMBEDDED_CONS,
+ IPA_CLIENT_A2_TETHERED_CONS,
+ IPA_CLIENT_A5_LAN_WAN_CONS,
+ IPA_CLIENT_Q6_LAN_CONS,
+
+ IPA_CLIENT_MAX,
+};
+
+/**
+ * enum ipa_ip_type - Address family: IPv4 or IPv6
+ */
+enum ipa_ip_type {
+ IPA_IP_v4,
+ IPA_IP_v6,
+ IPA_IP_MAX
+};
+
+/**
+ * enum ipa_flt_action - action field of filtering rule
+ *
+ * Pass to routing: 5'd0
+ * Pass to source NAT: 5'd1
+ * Pass to destination NAT: 5'd2
+ * Pass to default output pipe (e.g., A5): 5'd3
+ */
+enum ipa_flt_action {
+ IPA_PASS_TO_ROUTING,
+ IPA_PASS_TO_SRC_NAT,
+ IPA_PASS_TO_DST_NAT,
+ IPA_PASS_TO_EXCEPTION
+};
+
+/**
+ * struct ipa_rule_attrib - attributes of a routing/filtering
+ * rule, all in LE
+ * @attrib_mask: what attributes are valid
+ * @src_port_lo: low port of src port range
+ * @src_port_hi: high port of src port range
+ * @dst_port_lo: low port of dst port range
+ * @dst_port_hi: high port of dst port range
+ * @type: ICMP/IGMP type
+ * @code: ICMP/IGMP code
+ * @spi: IPSec SPI
+ * @src_port: exact src port
+ * @dst_port: exact dst port
+ * @meta_data: meta-data val
+ * @meta_data_mask: meta-data mask
+ * @u.v4.tos: type of service
+ * @u.v4.protocol: protocol
+ * @u.v4.src_addr: src address value
+ * @u.v4.src_addr_mask: src address mask
+ * @u.v4.dst_addr: dst address value
+ * @u.v4.dst_addr_mask: dst address mask
+ * @u.v6.tc: traffic class
+ * @u.v6.flow_label: flow label
+ * @u.v6.next_hdr: next header
+ * @u.v6.src_addr: src address val
+ * @u.v6.src_addr_mask: src address mask
+ * @u.v6.dst_addr: dst address val
+ * @u.v6.dst_addr_mask: dst address mask
+ */
+struct ipa_rule_attrib {
+ uint32_t attrib_mask;
+ uint16_t src_port_lo;
+ uint16_t src_port_hi;
+ uint16_t dst_port_lo;
+ uint16_t dst_port_hi;
+ uint8_t type;
+ uint8_t code;
+ uint32_t spi;
+ uint16_t src_port;
+ uint16_t dst_port;
+ uint32_t meta_data;
+ uint32_t meta_data_mask;
+ union {
+ struct {
+ uint8_t tos;
+ uint8_t protocol;
+ uint32_t src_addr;
+ uint32_t src_addr_mask;
+ uint32_t dst_addr;
+ uint32_t dst_addr_mask;
+ } v4;
+ struct {
+ uint8_t tc;
+ uint32_t flow_label;
+ uint8_t next_hdr;
+ uint32_t src_addr[4];
+ uint32_t src_addr_mask[4];
+ uint32_t dst_addr[4];
+ uint32_t dst_addr_mask[4];
+ } v6;
+ } u;
+};
+
+/**
+ * struct ipa_flt_rule - attributes of a filtering rule
+ * @action: action field
+ * @rt_tbl_hdl: handle of table from "get"
+ * @attrib: attributes of the rule
+ */
+struct ipa_flt_rule {
+ enum ipa_flt_action action;
+ uint32_t rt_tbl_hdl;
+ struct ipa_rule_attrib attrib;
+};
+
+/**
+ * struct ipa_rt_rule - attributes of a routing rule
+ * @dst: dst "client"
+ * @hdr_hdl: handle to the dynamic header
+ it is not an index or an offset
+ * @attrib: attributes of the rule
+ */
+struct ipa_rt_rule {
+ enum ipa_client_type dst;
+ uint32_t hdr_hdl;
+ struct ipa_rule_attrib attrib;
+};
+
+/**
+ * struct ipa_hdr_add - header descriptor includes in and out
+ * parameters
+ * @name: name of the header
+ * @hdr: actual header to be inserted
+ * @hdr_len: size of above header
+ * @is_partial: header not fully specified
+ * @hdr_hdl: out paramerer, handle to header, valid when status is 0
+ * @status: out paramerer, status of header add operation,
+ * 0 for success,
+ * -1 for failure
+ */
+struct ipa_hdr_add {
+ char name[IPA_RESOURCE_NAME_MAX];
+ uint8_t hdr[IPA_HDR_MAX_SIZE];
+ uint8_t hdr_len;
+ uint8_t is_partial;
+ uint32_t hdr_hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_add_hdr - header addition parameters (support
+ * multiple headers and commit)
+ * @commit: should headers be written to IPA HW also?
+ * @num_hdrs: num of headers that follow
+ * @ipa_hdr_add hdr: all headers need to go here back to
+ * back, no pointers
+ */
+struct ipa_ioc_add_hdr {
+ uint8_t commit;
+ uint8_t num_hdrs;
+ struct ipa_hdr_add hdr[0];
+};
+
+/**
+ * struct ipa_ioc_copy_hdr - retrieve a copy of the specified
+ * header - caller can then derive the complete header
+ * @name: name of the header resource
+ * @hdr: out parameter, contents of specified header,
+ * valid only when ioctl return val is non-negative
+ * @hdr_len: out parameter, size of above header
+ * valid only when ioctl return val is non-negative
+ * @is_partial: out parameter, indicates whether specified header is partial
+ * valid only when ioctl return val is non-negative
+ */
+struct ipa_ioc_copy_hdr {
+ char name[IPA_RESOURCE_NAME_MAX];
+ uint8_t hdr[IPA_HDR_MAX_SIZE];
+ uint8_t hdr_len;
+ uint8_t is_partial;
+};
+
+/**
+ * struct ipa_ioc_get_hdr - header entry lookup parameters, if lookup was
+ * successful caller must call put to release the reference count when done
+ * @name: name of the header resource
+ * @hdl: out parameter, handle of header entry
+ * valid only when ioctl return val is non-negative
+ */
+struct ipa_ioc_get_hdr {
+ char name[IPA_RESOURCE_NAME_MAX];
+ uint32_t hdl;
+};
+
+/**
+ * struct ipa_hdr_del - header descriptor includes in and out
+ * parameters
+ *
+ * @hdl: handle returned from header add operation
+ * @status: out parameter, status of header remove operation,
+ * 0 for success,
+ * -1 for failure
+ */
+struct ipa_hdr_del {
+ uint32_t hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_del_hdr - header deletion parameters (support
+ * multiple headers and commit)
+ * @commit: should headers be removed from IPA HW also?
+ * @num_hdls: num of headers being removed
+ * @ipa_hdr_del hdl: all handles need to go here back to back, no pointers
+ */
+struct ipa_ioc_del_hdr {
+ uint8_t commit;
+ uint8_t num_hdls;
+ struct ipa_hdr_del hdl[0];
+};
+
+/**
+ * struct ipa_rt_rule_add - routing rule descriptor includes in
+ * and out parameters
+ * @rule: actual rule to be added
+ * @at_rear: add at back of routing table, it is NOT possible to add rules at
+ * the rear of the "default" routing tables
+ * @rt_rule_hdl: output parameter, handle to rule, valid when status is 0
+ * @status: output parameter, status of routing rule add operation,
+ * 0 for success,
+ * -1 for failure
+ */
+struct ipa_rt_rule_add {
+ struct ipa_rt_rule rule;
+ uint8_t at_rear;
+ uint32_t rt_rule_hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_add_rt_rule - routing rule addition parameters (supports
+ * multiple rules and commit);
+ *
+ * all rules MUST be added to same table
+ * @commit: should rules be written to IPA HW also?
+ * @ip: IP family of rule
+ * @rt_tbl_name: name of routing table resource
+ * @num_rules: number of routing rules that follow
+ * @ipa_rt_rule_add rules: all rules need to go back to back here, no pointers
+ */
+struct ipa_ioc_add_rt_rule {
+ uint8_t commit;
+ enum ipa_ip_type ip;
+ char rt_tbl_name[IPA_RESOURCE_NAME_MAX];
+ uint8_t num_rules;
+ struct ipa_rt_rule_add rules[0];
+};
+
+/**
+ * struct ipa_rt_rule_del - routing rule descriptor includes in
+ * and out parameters
+ * @hdl: handle returned from route rule add operation
+ * @status: output parameter, status of route rule delete operation,
+ * 0 for success,
+ * -1 for failure
+ */
+struct ipa_rt_rule_del {
+ uint32_t hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_del_rt_rule - routing rule deletion parameters (supports
+ * multiple headers and commit)
+ * @commit: should rules be removed from IPA HW also?
+ * @ip: IP family of rules
+ * @num_hdls: num of rules being removed
+ * @ipa_rt_rule_del hdl: all handles need to go back to back here, no pointers
+ */
+struct ipa_ioc_del_rt_rule {
+ uint8_t commit;
+ enum ipa_ip_type ip;
+ uint8_t num_hdls;
+ struct ipa_rt_rule_del hdl[0];
+};
+
+/**
+ * struct ipa_flt_rule_add - filtering rule descriptor includes
+ * in and out parameters
+ * @rule: actual rule to be added
+ * @at_rear: add at back of filtering table?
+ * @flt_rule_hdl: out parameter, handle to rule, valid when status is 0
+ * @status: output parameter, status of filtering rule add operation,
+ * 0 for success,
+ * -1 for failure
+ *
+ */
+struct ipa_flt_rule_add {
+ struct ipa_flt_rule rule;
+ uint8_t at_rear;
+ uint32_t flt_rule_hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_add_flt_rule - filtering rule addition parameters (supports
+ * multiple rules and commit)
+ * all rules MUST be added to same table
+ * @commit: should rules be written to IPA HW also?
+ * @ip: IP family of rule
+ * @ep: which "clients" pipe does this rule apply to?
+ * valid only when global is 0
+ * @global: does this apply to global filter table of specific IP family
+ * @num_rules: number of filtering rules that follow
+ * @rules: all rules need to go back to back here, no pointers
+ */
+struct ipa_ioc_add_flt_rule {
+ uint8_t commit;
+ enum ipa_ip_type ip;
+ enum ipa_client_type ep;
+ uint8_t global;
+ uint8_t num_rules;
+ struct ipa_flt_rule_add rules[0];
+};
+
+/**
+ * struct ipa_flt_rule_del - filtering rule descriptor includes
+ * in and out parameters
+ *
+ * @hdl: handle returned from filtering rule add operation
+ * @status: output parameter, status of filtering rule delete operation,
+ * 0 for success,
+ * -1 for failure
+ */
+struct ipa_flt_rule_del {
+ uint32_t hdl;
+ int status;
+};
+
+/**
+ * struct ipa_ioc_del_flt_rule - filtering rule deletion parameters (supports
+ * multiple headers and commit)
+ * @commit: should rules be removed from IPA HW also?
+ * @ip: IP family of rules
+ * @num_hdls: num of rules being removed
+ * @hdl: all handles need to go back to back here, no pointers
+ */
+struct ipa_ioc_del_flt_rule {
+ uint8_t commit;
+ enum ipa_ip_type ip;
+ uint8_t num_hdls;
+ struct ipa_flt_rule_del hdl[0];
+};
+
+/**
+ * struct ipa_ioc_get_rt_tbl - routing table lookup parameters, if lookup was
+ * successful caller must call put to release the reference
+ * count when done
+ * @ip: IP family of table
+ * @name: name of routing table resource
+ * @htl: output parameter, handle of routing table, valid only when ioctl
+ * return val is non-negative
+ */
+struct ipa_ioc_get_rt_tbl {
+ enum ipa_ip_type ip;
+ char name[IPA_RESOURCE_NAME_MAX];
+ uint32_t hdl;
+};
+
+/**
+ * struct ipa_ioc_query_intf - used to lookup number of tx and
+ * rx properties of interface
+ * @name: name of interface
+ * @num_tx_props: output parameter, number of tx properties
+ * valid only when ioctl return val is non-negative
+ * @num_rx_props: output parameter, number of rx properties
+ * valid only when ioctl return val is non-negative
+ */
+struct ipa_ioc_query_intf {
+ char name[IPA_RESOURCE_NAME_MAX];
+ uint32_t num_tx_props;
+ uint32_t num_rx_props;
+};
+
+/**
+ * struct ipa_ioc_tx_intf_prop - interface tx property
+ * @ip: IP family of routing rule
+ * @attrib: routing rule
+ * @dst_pipe: routing output pipe
+ * @hdr_name: name of associated header if any, empty string when no header
+ */
+struct ipa_ioc_tx_intf_prop {
+ enum ipa_ip_type ip;
+ struct ipa_rule_attrib attrib;
+ enum ipa_client_type dst_pipe;
+ char hdr_name[IPA_RESOURCE_NAME_MAX];
+};
+
+/**
+ * struct ipa_ioc_query_intf_tx_props - interface tx propertie
+ * @name: name of interface
+ * @tx[0]: output parameter, the tx properties go here back to back
+ */
+struct ipa_ioc_query_intf_tx_props {
+ char name[IPA_RESOURCE_NAME_MAX];
+ struct ipa_ioc_tx_intf_prop tx[0];
+};
+
+/**
+ * struct ipa_ioc_rx_intf_prop - interface rx property
+ * @ip: IP family of filtering rule
+ * @attrib: filtering rule
+ * @src_pipe: input pipe
+ */
+struct ipa_ioc_rx_intf_prop {
+ enum ipa_ip_type ip;
+ struct ipa_rule_attrib attrib;
+ enum ipa_client_type src_pipe;
+};
+
+/**
+ * struct ipa_ioc_query_intf_rx_props - interface rx propertie
+ * @name: name of interface
+ * @rx: output parameter, the rx properties go here back to back
+ */
+struct ipa_ioc_query_intf_rx_props {
+ char name[IPA_RESOURCE_NAME_MAX];
+ struct ipa_ioc_rx_intf_prop rx[0];
+};
+
+/**
+ * struct ipa_ioc_nat_alloc_mem - nat table memory allocation
+ * properties
+ * @dev_name: input parameter, the name of table
+ * @size: input parameter, size of table in bytes
+ * @offset: output parameter, offset into page in case of system memory
+ */
+struct ipa_ioc_nat_alloc_mem {
+ char dev_name[IPA_RESOURCE_NAME_MAX];
+ size_t size;
+ off_t offset;
+};
+
+/**
+ * struct ipa_ioc_v4_nat_init - nat table initialization
+ * parameters
+ * @tbl_index: input parameter, index of the table
+ * @ipv4_rules_offset: input parameter, ipv4 rules address offset
+ * @expn_rules_offset: input parameter, ipv4 expansion rules address offset
+ * @index_offset: input parameter, index rules offset
+ * @index_expn_offset: input parameter, index expansion rules offset
+ * @table_entries: input parameter, ipv4 rules table size in entries
+ * @expn_table_entries: input parameter, ipv4 expansion rules table size
+ * @ip_addr: input parameter, public ip address
+ */
+struct ipa_ioc_v4_nat_init {
+ uint8_t tbl_index;
+ uint32_t ipv4_rules_offset;
+ uint32_t expn_rules_offset;
+
+ uint32_t index_offset;
+ uint32_t index_expn_offset;
+
+ uint16_t table_entries;
+ uint16_t expn_table_entries;
+ uint32_t ip_addr;
+};
+
+/**
+ * struct ipa_ioc_v4_nat_del - nat table delete parameter
+ * @table_index: input parameter, index of the table
+ * @public_ip_addr: input parameter, public ip address
+ */
+struct ipa_ioc_v4_nat_del {
+ uint8_t table_index;
+ uint32_t public_ip_addr;
+};
+
+/**
+ * struct ipa_ioc_nat_dma_one - nat dma command parameter
+ * @table_index: input parameter, index of the table
+ * @base_addr: type of table, from which the base address of the table
+ * can be inferred
+ * @offset: destination offset within the NAT table
+ * @data: data to be written.
+ */
+struct ipa_ioc_nat_dma_one {
+ uint8_t table_index;
+ uint8_t base_addr;
+
+ uint32_t offset;
+ uint16_t data;
+
+};
+
+/**
+ * struct ipa_ioc_nat_dma_cmd - To hold multiple nat dma commands
+ * @entries: number of dma commands in use
+ * @dma: data pointer to the dma commands
+ */
+struct ipa_ioc_nat_dma_cmd {
+ uint8_t entries;
+ struct ipa_ioc_nat_dma_one dma[0];
+
+};
+
+/**
+ * struct ipa_msg_meta - Format of the message meta-data.
+ * @msg_type: the type of the message
+ * @msg_len: the length of the message in bytes
+ * @rsvd: reserved bits for future use.
+ *
+ * Client in user-space should issue a read on the device (/dev/ipa) with a
+ * buffer of atleast this size in an continuous loop, call will block when there
+ * is no pending async message.
+ *
+ * After reading a message's meta-data using above scheme, client should issue a
+ * GET_MSG IOCTL to actually read the message itself into the buffer of
+ * "msg_len" immediately following the ipa_msg_meta itself in the IOCTL payload
+ */
+struct ipa_msg_meta {
+ uint8_t msg_type;
+ uint16_t msg_len;
+ uint8_t rsvd;
+};
+
+/**
+ * actual IOCTLs supported by IPA driver
+ */
+#define IPA_IOC_ADD_HDR _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_ADD_HDR, \
+ struct ipa_ioc_add_hdr *)
+#define IPA_IOC_DEL_HDR _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_DEL_HDR, \
+ struct ipa_ioc_del_hdr *)
+#define IPA_IOC_ADD_RT_RULE _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_ADD_RT_RULE, \
+ struct ipa_ioc_add_rt_rule *)
+#define IPA_IOC_DEL_RT_RULE _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_DEL_RT_RULE, \
+ struct ipa_ioc_del_rt_rule *)
+#define IPA_IOC_ADD_FLT_RULE _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_ADD_FLT_RULE, \
+ struct ipa_ioc_add_flt_rule *)
+#define IPA_IOC_DEL_FLT_RULE _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_DEL_FLT_RULE, \
+ struct ipa_ioc_del_flt_rule *)
+#define IPA_IOC_COMMIT_HDR _IO(IPA_IOC_MAGIC,\
+ IPA_IOCTL_COMMIT_HDR)
+#define IPA_IOC_RESET_HDR _IO(IPA_IOC_MAGIC,\
+ IPA_IOCTL_RESET_HDR)
+#define IPA_IOC_COMMIT_RT _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_COMMIT_RT, \
+ enum ipa_ip_type)
+#define IPA_IOC_RESET_RT _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_RESET_RT, \
+ enum ipa_ip_type)
+#define IPA_IOC_COMMIT_FLT _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_COMMIT_FLT, \
+ enum ipa_ip_type)
+#define IPA_IOC_RESET_FLT _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_RESET_FLT, \
+ enum ipa_ip_type)
+#define IPA_IOC_DUMP _IO(IPA_IOC_MAGIC, \
+ IPA_IOCTL_DUMP)
+#define IPA_IOC_GET_RT_TBL _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_GET_RT_TBL, \
+ struct ipa_ioc_get_rt_tbl *)
+#define IPA_IOC_PUT_RT_TBL _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_PUT_RT_TBL, \
+ uint32_t)
+#define IPA_IOC_COPY_HDR _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_COPY_HDR, \
+ struct ipa_ioc_copy_hdr *)
+#define IPA_IOC_QUERY_INTF _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_QUERY_INTF, \
+ struct ipa_ioc_query_intf *)
+#define IPA_IOC_QUERY_INTF_TX_PROPS _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_QUERY_INTF_TX_PROPS, \
+ struct ipa_ioc_query_intf_tx_props *)
+#define IPA_IOC_QUERY_INTF_RX_PROPS _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_QUERY_INTF_RX_PROPS, \
+ struct ipa_ioc_query_intf_rx_props *)
+#define IPA_IOC_GET_HDR _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_GET_HDR, \
+ struct ipa_ioc_get_hdr *)
+#define IPA_IOC_PUT_HDR _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_PUT_HDR, \
+ uint32_t)
+#define IPA_IOC_ALLOC_NAT_MEM _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_ALLOC_NAT_MEM, \
+ struct ipa_ioc_nat_alloc_mem *)
+#define IPA_IOC_V4_INIT_NAT _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_V4_INIT_NAT, \
+ struct ipa_ioc_v4_nat_init *)
+#define IPA_IOC_NAT_DMA _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_NAT_DMA, \
+ struct ipa_ioc_nat_dma_cmd *)
+#define IPA_IOC_V4_DEL_NAT _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_V4_DEL_NAT, \
+ struct ipa_ioc_v4_nat_del *)
+#define IPA_IOC_GET_NAT_OFFSET _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_GET_NAT_OFFSET, \
+ uint32_t *)
+#define IPA_IOC_SET_FLT _IOW(IPA_IOC_MAGIC, \
+ IPA_IOCTL_SET_FLT, \
+ uint32_t)
+#define IPA_IOC_GET_ASYNC_MSG _IOWR(IPA_IOC_MAGIC, \
+ IPA_IOCTL_GET_ASYNC_MSG, \
+ struct ipa_msg_meta *)
+
+#endif /* _MSM_IPA_H_ */
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 89a8421..e0d9072 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -548,6 +548,14 @@
* @NL80211_CMD_SET_NOACK_MAP: sets a bitmap for the individual TIDs whether
* No Acknowledgement Policy should be applied.
*
+ * @NL80211_CMD_UPDATE_FT_IES: Pass down the most up-to-date Fast Transition
+ * Information Element to the WLAN driver
+ *
+ * @NL80211_CMD_FT_EVENT: Send a Fast transition event from the WLAN driver
+ * to the supplicant. This will carry the target AP's MAC address along
+ * with the relevant Information Elements. This event to report received
+ * FT IEs( MDIE, FTIE,RSN IE, TIE, RICIE).
+ *
* @NL80211_CMD_MAX: highest used command number
* @__NL80211_CMD_AFTER_LAST: internal use
*/
@@ -689,6 +697,9 @@
NL80211_CMD_SET_NOACK_MAP,
+ NL80211_CMD_UPDATE_FT_IES,
+ NL80211_CMD_FT_EVENT,
+
/* add new commands above here */
/* used to define NL80211_CMD_MAX below */
@@ -1264,6 +1275,10 @@
* @NL80211_ATTR_BG_SCAN_PERIOD: Background scan period in seconds
* or 0 to disable background scan.
*
+ * @NL80211_ATTR_MDID: Mobility Domain Identifier
+ *
+ * @NL80211_ATTR_IE_RIC: Resource Information Container Information Element
+ *
* @NL80211_ATTR_MAX: highest attribute number currently defined
* @__NL80211_ATTR_AFTER_LAST: internal use
*/
@@ -1515,6 +1530,9 @@
NL80211_ATTR_BG_SCAN_PERIOD,
+ NL80211_ATTR_MDID,
+ NL80211_ATTR_IE_RIC,
+
/* add attributes here, update the policy in nl80211.c */
__NL80211_ATTR_AFTER_LAST,
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index d229ad3..1717cd9 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -11,7 +11,7 @@
#include <linux/of.h>
/*
- * irq_of_parse_and_map() is used ba all OF enabled platforms; but SPARC
+ * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
* implements it differently. However, the prototype is the same for all,
* so declare it here regardless of the CONFIG_OF_IRQ setting.
*/
@@ -76,5 +76,13 @@
extern void of_irq_init(const struct of_device_id *matches);
#endif /* CONFIG_OF_IRQ */
-#endif /* CONFIG_OF */
+
+#else /* !CONFIG_OF */
+static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
+ int index)
+{
+ return 0;
+}
+#endif /* !CONFIG_OF */
+
#endif /* __OF_IRQ_H */
diff --git a/include/linux/qmi_encdec.h b/include/linux/qmi_encdec.h
new file mode 100644
index 0000000..4c5f6d3
--- /dev/null
+++ b/include/linux/qmi_encdec.h
@@ -0,0 +1,169 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QMI_ENCDEC_H_
+#define _QMI_ENCDEC_H_
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/socket.h>
+#include <linux/gfp.h>
+
+#define QMI_REQUEST_CONTROL_FLAG 0x00
+#define QMI_RESPONSE_CONTROL_FLAG 0x02
+#define QMI_INDICATION_CONTROL_FLAG 0x04
+#define QMI_HEADER_SIZE 7
+
+/**
+ * elem_type - Enum to identify the data type of elements in a data
+ * structure.
+ */
+enum elem_type {
+ QMI_OPT_FLAG = 1,
+ QMI_DATA_LEN,
+ QMI_UNSIGNED_1_BYTE,
+ QMI_UNSIGNED_2_BYTE,
+ QMI_UNSIGNED_4_BYTE,
+ QMI_UNSIGNED_8_BYTE,
+ QMI_SIGNED_2_BYTE_ENUM,
+ QMI_SIGNED_4_BYTE_ENUM,
+ QMI_STRUCT,
+ QMI_EOTI,
+};
+
+/**
+ * array_type - Enum to identify if an element in a data structure is
+ * an array. If so, then is it a static length array or a
+ * variable length array.
+ */
+enum array_type {
+ NO_ARRAY = 0,
+ STATIC_ARRAY = 1,
+ VAR_LEN_ARRAY = 2,
+};
+
+/**
+ * elem_info - Data structure to specify information about an element
+ * in a data structure. An array of this data structure
+ * can be used to specify info about a complex data
+ * structure to be encoded/decoded.
+ *
+ * @data_type: Data type of this element.
+ * @elem_len: Array length of this element, if an array.
+ * @elem_size: Size of a single instance of this data type.
+ * @is_array: Array type of this element.
+ * @tlv_type: QMI message specific type to identify which element
+ * is present in an incoming message.
+ * @offset: To identify the address of the first instance of this
+ * element in the data structure.
+ * @ei_array: Array to provide information about the nested structure
+ * within a data structure to be encoded/decoded.
+ */
+struct elem_info {
+ enum elem_type data_type;
+ uint32_t elem_len;
+ uint32_t elem_size;
+ enum array_type is_array;
+ uint8_t tlv_type;
+ uint32_t offset;
+ struct elem_info *ei_array;
+};
+
+/**
+ * @msg_desc - Describe about the main/outer structure to be
+ * encoded/decoded.
+ *
+ * @max_msg_len: Maximum possible length of the QMI message.
+ * @ei_array: Array to provide information about a data structure.
+ */
+struct msg_desc {
+ uint16_t msg_id;
+ int max_msg_len;
+ struct elem_info *ei_array;
+};
+
+struct qmi_header {
+ unsigned char cntl_flag;
+ uint16_t txn_id;
+ uint16_t msg_id;
+ uint16_t msg_len;
+} __attribute__((__packed__));
+
+static inline void encode_qmi_header(unsigned char *buf,
+ unsigned char cntl_flag, uint16_t txn_id,
+ uint16_t msg_id, uint16_t msg_len)
+{
+ struct qmi_header *hdr = (struct qmi_header *)buf;
+
+ hdr->cntl_flag = cntl_flag;
+ hdr->txn_id = txn_id;
+ hdr->msg_id = msg_id;
+ hdr->msg_len = msg_len;
+}
+
+static inline void decode_qmi_header(unsigned char *buf,
+ unsigned char *cntl_flag, uint16_t *txn_id,
+ uint16_t *msg_id, uint16_t *msg_len)
+{
+ struct qmi_header *hdr = (struct qmi_header *)buf;
+
+ *cntl_flag = hdr->cntl_flag;
+ *txn_id = hdr->txn_id;
+ *msg_id = hdr->msg_id;
+ *msg_len = hdr->msg_len;
+}
+
+#ifdef CONFIG_QMI_ENCDEC
+/**
+ * qmi_kernel_encode() - Encode to QMI message wire format
+ * @desc: Pointer to structure descriptor.
+ * @out_buf: Buffer to hold the encoded QMI message.
+ * @out_buf_len: Length of the out buffer.
+ * @in_c_struct: C Structure to be encoded.
+ *
+ * @return: size of encoded message on success, < 0 on error.
+ */
+int qmi_kernel_encode(struct msg_desc *desc,
+ void *out_buf, uint32_t out_buf_len,
+ void *in_c_struct);
+
+/**
+ * qmi_kernel_decode() - Decode to C Structure format
+ * @desc: Pointer to structure descriptor.
+ * @out_c_struct: Buffer to hold the decoded C structure.
+ * @in_buf: Buffer containg the QMI message to be decoded.
+ * @in_buf_len: Length of the incoming QMI message.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_kernel_decode(struct msg_desc *desc, void *out_c_struct,
+ void *in_buf, uint32_t in_buf_len);
+
+#else
+static inline int qmi_kernel_encode(struct msg_desc *desc,
+ void *out_buf, uint32_t out_buf_len,
+ void *in_c_struct)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int qmi_kernel_decode(struct msg_desc *desc,
+ void *out_c_struct,
+ void *in_buf, uint32_t in_buf_len)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif
diff --git a/include/linux/qpnp/pin.h b/include/linux/qpnp/pin.h
index fa9c30f..fff29ab 100644
--- a/include/linux/qpnp/pin.h
+++ b/include/linux/qpnp/pin.h
@@ -131,7 +131,7 @@
* the input is interpreted as a logical 1.
* @out_strength: the amount of current supplied for an output gpio,
* should be of the type QPNP_PIN_STRENGTH_*.
- * @select: select alternate function for the pin. Certain pins
+ * @src_sel: select alternate function for the pin. Certain pins
* can be paired (shorted) with each other. Some pins
* can act as alternate functions. In the context of
* gpio, this acts as a source select. For mpps,
@@ -159,7 +159,7 @@
int pull;
int vin_sel;
int out_strength;
- int select;
+ int src_sel;
int master_en;
int aout_ref;
int ain_route;
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index e5516ab..077ccfc 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -28,7 +28,7 @@
DCIN,
VCHG_SNS,
SPARE1_03,
- SPARE2_03,
+ USB_ID_MV,
VCOIN,
VBAT_SNS,
VSYS,
@@ -81,44 +81,44 @@
LR_MUX7_HW_ID,
LR_MUX8_AMUX_THM4,
LR_MUX9_AMUX_THM5,
- LR_MUX10_USB_ID,
+ LR_MUX10_USB_ID_LV,
AMUX_PU1,
AMUX_PU2,
LR_MUX3_BUF_XO_THERM_BUF,
- LR_MUX1_PU1_BAT_THERM,
- LR_MUX2_PU1_BAT_ID,
- LR_MUX3_PU1_XO_THERM,
- LR_MUX4_PU1_AMUX_THM1,
- LR_MUX5_PU1_AMUX_THM2,
- LR_MUX6_PU1_AMUX_THM3,
- LR_MUX7_PU1_AMUX_HW_ID,
- LR_MUX8_PU1_AMUX_THM4,
- LR_MUX9_PU1_AMUX_THM5,
- LR_MUX10_PU1_AMUX_USB_ID,
- LR_MUX3_BUF_PU1_XO_THERM_BUF,
- LR_MUX1_PU2_BAT_THERM,
- LR_MUX2_PU2_BAT_ID,
- LR_MUX3_PU2_XO_THERM,
- LR_MUX4_PU2_AMUX_THM1,
- LR_MUX5_PU2_AMUX_THM2,
- LR_MUX6_PU2_AMUX_THM3,
- LR_MUX7_PU2_AMUX_HW_ID,
- LR_MUX8_PU2_AMUX_THM4,
- LR_MUX9_PU2_AMUX_THM5,
- LR_MUX10_PU2_AMUX_USB_ID,
- LR_MUX3_BUF_PU2_XO_THERM_BUF,
- LR_MUX1_PU1_PU2_BAT_THERM,
- LR_MUX2_PU1_PU2_BAT_ID,
- LR_MUX3_PU1_PU2_XO_THERM,
- LR_MUX4_PU1_PU2_AMUX_THM1,
- LR_MUX5_PU1_PU2_AMUX_THM2,
- LR_MUX6_PU1_PU2_AMUX_THM3,
- LR_MUX7_PU1_PU2_AMUX_HW_ID,
- LR_MUX8_PU1_PU2_AMUX_THM4,
- LR_MUX9_PU1_PU2_AMUX_THM5,
- LR_MUX10_PU1_PU2_AMUX_USB_ID,
- LR_MUX3_BUF_PU1_PU2_XO_THERM_BUF,
- ALL_OFF,
+ LR_MUX1_PU1_BAT_THERM = 112,
+ LR_MUX2_PU1_BAT_ID = 113,
+ LR_MUX3_PU1_XO_THERM = 114,
+ LR_MUX4_PU1_AMUX_THM1 = 115,
+ LR_MUX5_PU1_AMUX_THM2 = 116,
+ LR_MUX6_PU1_AMUX_THM3 = 117,
+ LR_MUX7_PU1_AMUX_HW_ID = 118,
+ LR_MUX8_PU1_AMUX_THM4 = 119,
+ LR_MUX9_PU1_AMUX_THM5 = 120,
+ LR_MUX10_PU1_AMUX_USB_ID_LV = 121,
+ LR_MUX3_BUF_PU1_XO_THERM_BUF = 124,
+ LR_MUX1_PU2_BAT_THERM = 176,
+ LR_MUX2_PU2_BAT_ID = 177,
+ LR_MUX3_PU2_XO_THERM = 178,
+ LR_MUX4_PU2_AMUX_THM1 = 179,
+ LR_MUX5_PU2_AMUX_THM2 = 180,
+ LR_MUX6_PU2_AMUX_THM3 = 181,
+ LR_MUX7_PU2_AMUX_HW_ID = 182,
+ LR_MUX8_PU2_AMUX_THM4 = 183,
+ LR_MUX9_PU2_AMUX_THM5 = 184,
+ LR_MUX10_PU2_AMUX_USB_ID_LV = 185,
+ LR_MUX3_BUF_PU2_XO_THERM_BUF = 188,
+ LR_MUX1_PU1_PU2_BAT_THERM = 240,
+ LR_MUX2_PU1_PU2_BAT_ID = 241,
+ LR_MUX3_PU1_PU2_XO_THERM = 242,
+ LR_MUX4_PU1_PU2_AMUX_THM1 = 243,
+ LR_MUX5_PU1_PU2_AMUX_THM2 = 244,
+ LR_MUX6_PU1_PU2_AMUX_THM3 = 245,
+ LR_MUX7_PU1_PU2_AMUX_HW_ID = 246,
+ LR_MUX8_PU1_PU2_AMUX_THM4 = 247,
+ LR_MUX9_PU1_PU2_AMUX_THM5 = 248,
+ LR_MUX10_PU1_PU2_AMUX_USB_ID_LV = 249,
+ LR_MUX3_BUF_PU1_PU2_XO_THERM_BUF = 252,
+ ALL_OFF = 255,
ADC_MAX_NUM,
};
@@ -137,7 +137,7 @@
};
#define QPNP_ADC_625_UV 625000
-#define QPNP_ADC_HWMON_NAME_LENGTH 16
+#define QPNP_ADC_HWMON_NAME_LENGTH 64
/**
* enum qpnp_adc_decimation_type - Sampling rate supported.
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 1f13da3..0a1428e 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -2041,6 +2041,7 @@
extern unsigned int sysctl_sched_min_granularity;
extern unsigned int sysctl_sched_wakeup_granularity;
extern unsigned int sysctl_sched_child_runs_first;
+extern unsigned int sysctl_sched_wake_to_idle;
enum sched_tunable_scaling {
SCHED_TUNABLESCALING_NONE,
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
index 6938a86..742b9e4 100644
--- a/include/linux/usb/composite.h
+++ b/include/linux/usb/composite.h
@@ -365,6 +365,13 @@
/* protects deactivations and delayed_status counts*/
spinlock_t lock;
+
+ /*
+ * specify the mA units for the bMaxPower field in
+ * the configuration descriptor. Should be 2mA for HS
+ * and 8mA for SS.
+ */
+ int vbus_draw_units;
};
extern int usb_string_id(struct usb_composite_dev *c);
diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h
index 1894f42..4c1b7a0 100644
--- a/include/linux/usb/ehci_pdriver.h
+++ b/include/linux/usb/ehci_pdriver.h
@@ -41,6 +41,7 @@
unsigned big_endian_mmio:1;
unsigned port_power_on:1;
unsigned port_power_off:1;
+ unsigned pool_64_bit_align:1;
};
#endif /* __USB_CORE_EHCI_PDRIVER_H */
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index a998ac2..d6fbc64 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -199,6 +199,8 @@
* is connected.
* @core_clk_always_on_workaround: Don't disable core_clk when
* USB enters LPM.
+ * @delay_lpm_on_disconnect: Use a delay before entering LPM
+ * upon USB cable disconnection.
* @bus_scale_table: parameters for bus bandwidth requirements
* @mhl_dev_name: MHL device name used to register with MHL driver.
*/
@@ -218,6 +220,7 @@
bool pnoc_errata_fix;
bool enable_lpm_on_dev_suspend;
bool core_clk_always_on_workaround;
+ bool delay_lpm_on_disconnect;
struct msm_bus_scale_pdata *bus_scale_table;
const char *mhl_dev_name;
};
@@ -394,7 +397,12 @@
unsigned data;
struct msm_bus_scale_pdata *bus_scale_table;
unsigned log2_irq_thresh;
+
+ /*swfi latency is required while driving resume on to the bus */
u32 swfi_latency;
+
+ /*standalone latency is required when HSCI is active*/
+ u32 standalone_latency;
};
struct msm_usb_host_platform_data {
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 41ff312..8f86fce 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -1810,6 +1810,8 @@
V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0,
V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1
};
+#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24)
+
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
diff --git a/include/linux/wcnss_wlan.h b/include/linux/wcnss_wlan.h
index 7a194ca..6d2eee4 100644
--- a/include/linux/wcnss_wlan.h
+++ b/include/linux/wcnss_wlan.h
@@ -31,6 +31,8 @@
};
#define WCNSS_WLAN_IRQ_INVALID -1
+#define HAVE_WCNSS_SUSPEND_RESUME_NOTIFY 1
+#define HAVE_WCNSS_RESET_INTR 1
struct device *wcnss_wlan_get_device(void);
struct resource *wcnss_wlan_get_memory_map(struct device *dev);
@@ -59,6 +61,8 @@
void *wcnss_prealloc_get(unsigned int size);
int wcnss_prealloc_put(void *ptr);
void wcnss_reset_intr(void);
+void wcnss_suspend_notify(void);
+void wcnss_resume_notify(void);
#define wcnss_wlan_get_drvdata(dev) dev_get_drvdata(dev)
#define wcnss_wlan_set_drvdata(dev, data) dev_set_drvdata((dev), (data))
diff --git a/include/media/Kbuild b/include/media/Kbuild
index 4b6e6a9..70f6334 100644
--- a/include/media/Kbuild
+++ b/include/media/Kbuild
@@ -7,3 +7,4 @@
header-y += msm_gestures.h
header-y += msm_mercury.h
header-y += msm_jpeg.h
+header-y += msm_media_info.h
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 9af15e3..a932011 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1981,6 +1981,7 @@
IRQ_ROUTER_DEV,
CPP_DEV,
CCI_DEV,
+ FLASH_DEV,
};
struct msm_mctl_set_sdev_data {
diff --git a/include/media/msm_media_info.h b/include/media/msm_media_info.h
new file mode 100644
index 0000000..13ce043
--- /dev/null
+++ b/include/media/msm_media_info.h
@@ -0,0 +1,113 @@
+#ifndef __MEDIA_INFO_H__
+#define __MEDIA_INFO_H__
+
+#ifndef ALIGN
+#define ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1)))
+#endif
+
+enum color_fmts {
+ COLOR_FMT_NV12,
+};
+
+static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width)
+{
+ unsigned int alignment, stride = 0;
+ if (!width)
+ goto invalid_input;
+
+ switch (color_fmt) {
+ case COLOR_FMT_NV12:
+ alignment = 128;
+ stride = ALIGN(width, alignment);
+ break;
+ default:
+ break;
+ }
+invalid_input:
+ return stride;
+}
+
+static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width)
+{
+ unsigned int alignment, stride = 0;
+ if (!width)
+ goto invalid_input;
+
+ switch (color_fmt) {
+ case COLOR_FMT_NV12:
+ alignment = 128;
+ stride = ALIGN(width, alignment);
+ break;
+ default:
+ break;
+ }
+invalid_input:
+ return stride;
+}
+
+static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height)
+{
+ unsigned int alignment, sclines = 0;
+ if (!height)
+ goto invalid_input;
+
+ switch (color_fmt) {
+ case COLOR_FMT_NV12:
+ alignment = 32;
+ sclines = ALIGN(height, alignment);
+ break;
+ default:
+ break;
+ }
+invalid_input:
+ return sclines;
+}
+
+static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height)
+{
+ unsigned int alignment, sclines = 0;
+ if (!height)
+ goto invalid_input;
+
+ switch (color_fmt) {
+ case COLOR_FMT_NV12:
+ alignment = 16;
+ sclines = ALIGN(((height + 1) >> 1), alignment);
+ break;
+ default:
+ break;
+ }
+invalid_input:
+ return sclines;
+}
+
+static inline unsigned int VENUS_BUFFER_SIZE(
+ int color_fmt, int width, int height)
+{
+ unsigned int uv_alignment;
+ unsigned int size = 0;
+ unsigned int y_plane, uv_plane, y_stride,
+ uv_stride, y_sclines, uv_sclines;
+ if (!width || !height)
+ goto invalid_input;
+
+ y_stride = VENUS_Y_STRIDE(color_fmt, width);
+ uv_stride = VENUS_UV_STRIDE(color_fmt, width);
+ y_sclines = VENUS_Y_SCANLINES(color_fmt, height);
+ uv_sclines = VENUS_UV_SCANLINES(color_fmt, height);
+ switch (color_fmt) {
+ case COLOR_FMT_NV12:
+ uv_alignment = 0;
+ y_plane = y_stride * y_sclines;
+ uv_plane = uv_stride * uv_sclines + uv_alignment;
+ size = y_plane + uv_plane;
+ size = ALIGN(size, 4096);
+ break;
+ default:
+ break;
+ }
+invalid_input:
+ return size;
+}
+
+#endif
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index db69518..0efeff4 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -363,6 +363,53 @@
#define HCI_REQ_CANCELED 2
#define HCI_REQ_STATUS 3
+#define MAX_RAW_RDS_GRPS 21
+
+#define RDSGRP_DATA_OFFSET 0x1
+
+/*RT PLUS*/
+#define DUMMY_CLASS 0
+#define RT_PLUS_LEN_1_TAG 3
+#define RT_ERT_FLAG_BIT 5
+
+/*TAG1*/
+#define TAG1_MSB_OFFSET 3
+#define TAG1_MSB_MASK 7
+#define TAG1_LSB_OFFSET 5
+#define TAG1_POS_MSB_MASK 31
+#define TAG1_POS_MSB_OFFSET 1
+#define TAG1_POS_LSB_OFFSET 7
+#define TAG1_LEN_OFFSET 1
+#define TAG1_LEN_MASK 63
+
+/*TAG2*/
+#define TAG2_MSB_OFFSET 5
+#define TAG2_MSB_MASK 1
+#define TAG2_LSB_OFFSET 3
+#define TAG2_POS_MSB_MASK 7
+#define TAG2_POS_MSB_OFFSET 3
+#define TAG2_POS_LSB_OFFSET 5
+#define TAG2_LEN_MASK 31
+
+#define AGT_MASK 31
+/*Extract 5 left most bits of lsb of 2nd block*/
+#define AGT(x) (x & AGT_MASK)
+/*16 bits of 4th block*/
+#define AID(lsb, msb) ((msb << 8) | (lsb))
+/*Extract 5 right most bits of msb of 2nd block*/
+#define GTC(blk2msb) (blk2msb >> 3)
+
+#define GRP_3A 0x6
+#define RT_PLUS_AID 0x4bd7
+
+/*ERT*/
+#define ERT_AID 0x6552
+#define CARRIAGE_RETURN 0x000D
+#define MAX_ERT_SEGMENT 31
+#define ERT_FORMAT_DIR_BIT 1
+
+#define EXTRACT_BIT(data, bit_pos) ((data & (1 << bit_pos)) >> bit_pos)
+
struct hci_ev_tune_status {
__u8 sub_event;
__le32 station_freq;
@@ -375,9 +422,19 @@
__u8 intf_det_th;
} __packed;
+struct rds_blk_data {
+ __u8 rdsMsb;
+ __u8 rdsLsb;
+ __u8 blockStatus;
+} __packed;
+
+struct rds_grp_data {
+ struct rds_blk_data rdsBlk[4];
+} __packed;
+
struct hci_ev_rds_rx_data {
__u8 num_rds_grps;
- __u8 rds_grp_data[12];
+ struct rds_grp_data rds_grp_data[MAX_RAW_RDS_GRPS];
} __packed;
struct hci_ev_prg_service {
@@ -628,7 +685,10 @@
IRIS_EVT_NEW_AF_LIST,
IRIS_EVT_TXRDSDAT,
IRIS_EVT_TXRDSDONE,
- IRIS_EVT_RADIO_DISABLED
+ IRIS_EVT_RADIO_DISABLED,
+ IRIS_EVT_NEW_ODA,
+ IRIS_EVT_NEW_RT_PLUS,
+ IRIS_EVT_NEW_ERT,
};
enum emphasis_type {
FM_RX_EMP75 = 0x0,
@@ -660,7 +720,7 @@
IRIS_REGION_OTHER
};
-#define STD_BUF_SIZE (128)
+#define STD_BUF_SIZE (256)
enum iris_buf_t {
IRIS_BUF_SRCH_LIST,
@@ -674,7 +734,9 @@
IRIS_BUF_RDS_CNTRS,
IRIS_BUF_RD_DEFAULT,
IRIS_BUF_CAL_DATA,
- IRIS_BUF_MAX
+ IRIS_BUF_RT_PLUS,
+ IRIS_BUF_ERT,
+ IRIS_BUF_MAX,
};
enum iris_xfr_t {
diff --git a/include/media/tavarua.h b/include/media/tavarua.h
index 1cccb2b..881b851 100644
--- a/include/media/tavarua.h
+++ b/include/media/tavarua.h
@@ -52,7 +52,7 @@
#define SRCH_MASK (1 << SRCH200KHZ_OFFSET)
/* Standard buffer size */
-#define STD_BUF_SIZE (128)
+#define STD_BUF_SIZE (256)
/* Search direction */
#define SRCH_DIR_UP (0)
#define SRCH_DIR_DOWN (1)
diff --git a/include/media/vcap_fmt.h b/include/media/vcap_fmt.h
index 3b1bd7c2..84d9b42 100644
--- a/include/media/vcap_fmt.h
+++ b/include/media/vcap_fmt.h
@@ -24,12 +24,13 @@
#define VCAP_VC_NPL_OFLOW_ERR_EVENT 4
#define VCAP_VC_LBUF_OFLOW_ERR_EVENT 5
#define VCAP_VC_BUF_OVERWRITE_EVENT 6
-#define VCAP_VP_REG_R_ERR_EVENT 7
-#define VCAP_VP_REG_W_ERR_EVENT 8
-#define VCAP_VP_IN_HEIGHT_ERR_EVENT 9
-#define VCAP_VP_IN_WIDTH_ERR_EVENT 10
-#define VCAP_VC_UNEXPECT_BUF_DONE 11
-#define VCAP_MAX_NOTIFY_EVENT 12
+#define VCAP_VC_VSYNC_SEQ_ERR 7
+#define VCAP_VP_REG_R_ERR_EVENT 8
+#define VCAP_VP_REG_W_ERR_EVENT 9
+#define VCAP_VP_IN_HEIGHT_ERR_EVENT 10
+#define VCAP_VP_IN_WIDTH_ERR_EVENT 11
+#define VCAP_VC_UNEXPECT_BUF_DONE 12
+#define VCAP_MAX_NOTIFY_EVENT 13
enum hal_vcap_mode {
HAL_VCAP_MODE_PRO = 0,
@@ -119,8 +120,14 @@
VP_OUT_TYPE,
};
+enum vcap_stride {
+ VC_STRIDE_16,
+ VC_STRIDE_32,
+};
+
struct vcap_priv_fmt {
enum vcap_type type;
+ enum vcap_stride stride;
union {
struct v4l2_format_vc_ext timing;
struct v4l2_pix_format pix;
diff --git a/include/media/vcap_v4l2.h b/include/media/vcap_v4l2.h
index 3db949c..39aa1b9 100644
--- a/include/media/vcap_v4l2.h
+++ b/include/media/vcap_v4l2.h
@@ -39,10 +39,10 @@
#define VCAP_USEC (1000000)
-#define VCAP_STRIDE_ALIGN 0x10
-#define VCAP_STRIDE_CALC(x) (((x / VCAP_STRIDE_ALIGN) + \
- (!(!(x % VCAP_STRIDE_ALIGN)))) * \
- VCAP_STRIDE_ALIGN)
+#define VCAP_STRIDE_ALIGN_16 0x10
+#define VCAP_STRIDE_ALIGN_32 0x20
+#define VCAP_STRIDE_CALC(x, align) (((x / align) + \
+ (!(!(x % align)))) * align)
#define VCAP_BASE (dev->vcapbase)
#define VCAP_OFFSET(off) (VCAP_BASE + off)
@@ -109,7 +109,7 @@
uint8_t tot_buf;
uint8_t buf_num;
- bool top_field;
+ bool field1;
bool field_dropped;
struct timeval vc_ts;
@@ -241,6 +241,7 @@
enum vcap_op_mode op_mode;
struct v4l2_format_vc_ext vc_format;
+ enum vcap_stride stride;
enum v4l2_buf_type vp_buf_type_field;
struct vp_format_data vp_in_fmt;
@@ -254,6 +255,8 @@
uint32_t hold_vc;
uint32_t hold_vp;
+ /* Mutex ensures only one thread is dq buffer or turning streamoff */
+ struct mutex mutex;
spinlock_t cap_slock;
bool streaming;
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index a57c9f9..5c1daf3 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -1318,6 +1318,21 @@
};
/**
+ * struct cfg80211_update_ft_ies_params - FT IE Information
+ *
+ * This structure provides information needed to update the fast transition IE
+ *
+ * @md: The Mobility Domain ID, 2 Octet value
+ * @ie: Fast Transition IEs
+ * @ie_len: Length of ft_ie in octets
+ */
+struct cfg80211_update_ft_ies_params {
+ u16 md;
+ u8 *ie;
+ size_t ie_len;
+};
+
+/**
* struct cfg80211_ops - backend description for wireless configuration
*
* This struct is registered by fullmac card drivers and/or wireless stacks
@@ -1697,6 +1712,8 @@
u16 noack_map);
struct ieee80211_channel *(*get_channel)(struct wiphy *wiphy);
+ int (*update_ft_ies)(struct wiphy *wiphy, struct net_device *dev,
+ struct cfg80211_update_ft_ies_params *ftie);
};
/*
@@ -3348,6 +3365,32 @@
*/
u16 cfg80211_calculate_bitrate(struct rate_info *rate);
+/**
+ * struct cfg80211_ft_event - FT Information Elements
+ * @dev: network device
+ * @ies: FT IEs
+ * @ies_len: length of the FT IE in bytes
+ * @target_ap: target AP's MAC address
+ * @ric_ies: RIC IE
+ * @ric_ies_len: length of the RIC IE in bytes
+ */
+struct cfg80211_ft_event_params {
+ u8 *ies;
+ size_t ies_len;
+ u8 target_ap[ETH_ALEN];
+ u8 *ric_ies;
+ size_t ric_ies_len;
+};
+
+/**
+ * cfg80211_ft_event - notify userspace about FT IE and RIC IE
+ * @dev: network device
+ * @cfg80211_ft_event_params: IE information
+ */
+int cfg80211_ft_event(struct net_device *dev,
+ struct cfg80211_ft_event_params ft_event);
+
+
/* Logging, debugging and troubleshooting/diagnostic helpers. */
/* wiphy_printk helpers, similar to dev_printk */
diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h
index 07179e9..4376ece 100644
--- a/include/sound/apr_audio-v2.h
+++ b/include/sound/apr_audio-v2.h
@@ -6123,6 +6123,11 @@
/* Band cut equalizer effect.*/
#define ASM_PARAM_EQ_BAND_CUT 6
+/* Voice get & set params */
+#define VOICE_CMD_SET_PARAM 0x0001133D
+#define VOICE_CMD_GET_PARAM 0x0001133E
+#define VOICE_EVT_GET_PARAM_ACK 0x00011008
+
/* ERROR CODES */
/* Success. The operation completed with no errors. */
diff --git a/include/sound/apr_audio.h b/include/sound/apr_audio.h
index 8c35ada..bfd7208 100644
--- a/include/sound/apr_audio.h
+++ b/include/sound/apr_audio.h
@@ -61,7 +61,7 @@
#define RT_PROXY_PORT_001_TX 0x2001 /* index = 31 */
#define SECONDARY_PCM_RX 12 /* index = 32 */
#define SECONDARY_PCM_TX 13 /* index = 33 */
-
+#define PSEUDOPORT_01 0x8001 /* index =34 */
#define AFE_PORT_INVALID 0xFFFF
#define SLIMBUS_EXTPROC_RX AFE_PORT_INVALID
@@ -157,6 +157,55 @@
u16 reserved;
} __attribute__ ((packed));
+/*
+ * Opcode for AFE to start DTMF.
+ */
+#define AFE_PORTS_CMD_DTMF_CTL 0x00010102
+
+/** DTMF payload.*/
+struct afe_dtmf_generation_command {
+ struct apr_hdr hdr;
+
+ /*
+ * Duration of the DTMF tone in ms.
+ * -1 -> continuous,
+ * 0 -> disable
+ */
+ int64_t duration_in_ms;
+
+ /*
+ * The DTMF high tone frequency.
+ */
+ uint16_t high_freq;
+
+ /*
+ * The DTMF low tone frequency.
+ */
+ uint16_t low_freq;
+
+ /*
+ * The DTMF volume setting
+ */
+ uint16_t gain;
+
+ /*
+ * The number of ports to enable/disable on.
+ */
+ uint16_t num_ports;
+
+ /*
+ * The Destination ports - array .
+ * For DTMF on multiple ports, portIds needs to
+ * be populated numPorts times.
+ */
+ uint16_t port_ids;
+
+ /*
+ * variable for 32 bit alignment of APR packet.
+ */
+ uint16_t reserved;
+} __packed;
+
#define AFE_PCM_CFG_MODE_PCM 0x0
#define AFE_PCM_CFG_MODE_AUX 0x1
#define AFE_PCM_CFG_SYNC_EXT 0x0
@@ -299,6 +348,14 @@
int num_ch; /* 1 to 8 */
} __packed;
+struct afe_port_pseudo_cfg {
+ u16 bit_width;
+ u16 num_channels;
+ u16 data_format;
+ u16 timing_mode;
+ u16 reserved;
+} __packed;
+
#define AFE_PORT_AUDIO_IF_CONFIG 0x000100d3
#define AFE_PORT_AUDIO_SLIM_SCH_CONFIG 0x000100e4
#define AFE_PORT_MULTI_CHAN_HDMI_AUDIO_IF_CONFIG 0x000100D9
@@ -312,6 +369,7 @@
struct afe_port_slimbus_cfg slimbus;
struct afe_port_slimbus_sch_cfg slim_sch;
struct afe_port_rtproxy_cfg rtproxy;
+ struct afe_port_pseudo_cfg pseudo;
} __attribute__((packed));
struct afe_audioif_config_command {
@@ -574,6 +632,19 @@
u32 rate;
u8 dev_channel_mapping[8];
} __packed;
+
+struct adm_multi_channel_copp_open_v3 {
+ struct apr_hdr hdr;
+ u16 flags;
+ u16 mode;
+ u16 endpoint_id1;
+ u16 endpoint_id2;
+ u32 topology_id;
+ u16 channel_config;
+ u16 bit_width;
+ u32 rate;
+ u8 dev_channel_mapping[8];
+};
#define ADM_CMD_MEMORY_MAP 0x00010C30
struct adm_cmd_memory_map{
struct apr_hdr hdr;
@@ -914,7 +985,38 @@
* An unused channel is set to zero.
*/
};
+struct asm_dts_enc_cfg {
+ uint32_t sample_rate;
+ /*
+ * Samples at which input is to be encoded.
+ * Supported values:
+ * 44100 -- encode at 44.1 Khz
+ * 48000 -- encode at 48 Khz
+ */
+ uint32_t num_channels;
+ /*
+ * Number of channels for multi-channel encoding.
+ * Supported values: 1 to 6
+ */
+
+ uint8_t channel_mapping[6];
+ /*
+ * Channel array of size 16. Channel[i] mapping describes channel I.
+ * Each element i of the array describes channel I inside the buffer
+ * where num_channels. An unused channel is set to zero. Only first
+ * num_channels elements are valid
+
+ * Supported values:
+ * - # PCM_CHANNEL_L
+ * - # PCM_CHANNEL_R
+ * - # PCM_CHANNEL_C
+ * - # PCM_CHANNEL_LS
+ * - # PCM_CHANNEL_RS
+ * - # PCM_CHANNEL_LFE
+ */
+
+};
struct asm_adpcm_cfg {
u16 ch_cfg;
u16 bits_per_sample;
@@ -1107,6 +1209,7 @@
struct asm_sbc_read_cfg sbc;
struct asm_amrwb_read_cfg amrwb;
struct asm_multi_channel_pcm_fmt_blk mpcm;
+ struct asm_dts_enc_cfg dts;
} __attribute__((packed)) cfg;
};
@@ -1209,6 +1312,148 @@
u32 flags;
u32 format;
} __packed;
+#define ASM_STREAM_CMD_OPEN_TRANSCODE_LOOPBACK 0x00010DBA
+struct asm_stream_cmd_open_transcode_loopback {
+ struct apr_hdr hdr;
+ uint32_t mode_flags;
+ /*
+ * All bits are reserved. Clients must set them to zero.
+ */
+
+ uint32_t src_format_id;
+ /*
+ * Specifies the media format of the input audio stream.
+
+ * Supported values:
+ * - #ASM_MEDIA_FMT_LINEAR_PCM
+ * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM
+ */
+
+ uint32_t sink_format_id;
+ /*
+ * Specifies the media format of the output stream.
+
+ * Supported values:
+ * - #ASM_MEDIA_FMT_LINEAR_PCM
+ * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM
+ * - #ASM_MEDIA_FMT_DTS
+ */
+
+ uint32_t audproc_topo_id;
+ /*
+ * Postprocessing topology ID, which specifies the topology (order of
+ * processing) of postprocessing algorithms.
+
+ * Supported values:
+ * - #ASM_STREAM_POSTPROC_TOPO_ID_DEFAULT
+ * - #ASM_STREAM_POSTPROC_TOPO_ID_PEAKMETER
+ * - #ASM_STREAM_POSTPROC_TOPO_ID_NONE
+ * - #ASM_STREAM_POSTPROC_TOPO_ID_MCH_PEAK_VOL
+ */
+
+ uint16_t src_endpoint_type;
+ /*
+ * Specifies the source endpoint that provides the input samples.
+
+ * Supported values:
+ * - 0 -- Tx device matrix or stream router
+ * (gateway to the hardware ports)
+ * - All other values are reserved
+
+ * Clients must set this field to zero. Otherwise, an error is returned.
+ */
+
+ uint16_t sink_endpoint_type;
+ /*
+ * Specifies the sink endpoint type.
+
+ * Supported values:
+ * - 0 -- Rx device matrix or stream router
+ * (gateway to the hardware ports)
+ * - All other values are reserved
+
+ * Clients must set this field to zero. Otherwise, an error is returned.
+ */
+
+ uint16_t bits_per_sample;
+ /*
+ * Number of bits per sample processed by the ASM modules.
+ * Supported values: 16, 24
+ */
+
+ uint16_t reserved;
+ /*
+ * This field must be set to zero.
+ */
+} __packed;
+
+/*
+* ID of the DTS mix LFE channel to front channels parameter in the
+* #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
+* asm_dts_generic_param_t
+* ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT
+*/
+#define ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT 0x00010DB6
+
+/*
+* ID of the DTS DRC ratio parameter in the
+* #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
+* asm_dts_generic_param_t
+* ASM_PARAM_ID_DTS_DRC_RATIO
+*/
+#define ASM_PARAM_ID_DTS_DRC_RATIO 0x00010DB7
+
+/*
+* ID of the DTS enable dialog normalization parameter in the
+* #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
+
+* asm_dts_generic_param_t
+* ASM_PARAM_ID_DTS_ENABLE_DIALNORM
+*/
+#define ASM_PARAM_ID_DTS_ENABLE_DIALNORM 0x00010DB8
+
+/*
+* ID of the DTS enable parse REV2AUX parameter in the
+* #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
+* asm_dts_generic_param_t
+* ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX
+*/
+#define ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX 0x00010DB9
+
+struct asm_dts_generic_param {
+ int32_t generic_parameter;
+ /*
+ * #ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT:
+ * - if enabled, mixes LFE channel to front
+ * while downmixing (if necessary)
+ * - Supported values: 1-> enable, 0-> disable
+ * - Default: disabled
+
+ * #ASM_PARAM_ID_DTS_DRC_RATIO:
+ * - percentage of DRC ratio.
+ * - Supported values: 0-100
+ * - Default: 0, DRC is disabled.
+
+ * #ASM_PARAM_ID_DTS_ENABLE_DIALNORM:
+ * - flag to enable dialog normalization post processing.
+ * - Supported values: 1-> enable, 0-> disable.
+ * - Default: enabled.
+
+ * #ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX:
+ * - flag to enable parsing of rev2aux chunk in the bitstream.
+ * This chunk contains broadcast metadata.
+ * - Supported values: 1-> enable, 0-> disable.
+ * - Default: disabled.
+ */
+};
+
+struct asm_stream_cmd_dts_dec_param {
+ struct apr_hdr hdr;
+ u32 param_id;
+ u32 param_size;
+ struct asm_dts_generic_param generic_param;
+} __packed;
+
#define ASM_STREAM_CMD_OPEN_READWRITE 0x00010BCC
@@ -1238,7 +1483,7 @@
u8 session_id; /*ASM session ID*/
u16 afe_port_id;
u32 num_channels;
- u32 sampleing_rate;
+ u32 sampling_rate;
} __packed;
#define ASM_STREAM_CMD_SET_ENCDEC_PARAM 0x00010C10
diff --git a/include/sound/compress_params.h b/include/sound/compress_params.h
index f5c2d13..b95fa3c 100644
--- a/include/sound/compress_params.h
+++ b/include/sound/compress_params.h
@@ -418,6 +418,8 @@
__u32 ch_mode;
__u32 format;
__u32 align;
+ __u32 transcode_dts;
+ struct snd_dec_dts dts;
union snd_codec_options options;
__u32 reserved[3];
};
diff --git a/include/sound/cs8427.h b/include/sound/cs8427.h
index 2004ec3..a1e988d 100644
--- a/include/sound/cs8427.h
+++ b/include/sound/cs8427.h
@@ -209,7 +209,8 @@
int irq_base;
int num_irqs;
int reset_gpio;
- int (*enable) (int enable);
+ int (*enable) (int enable, int gpio);
+ int ls_gpio;
};
struct snd_pcm_substream;
diff --git a/include/sound/msm-dai-q6-v2.h b/include/sound/msm-dai-q6-v2.h
index 3d5ffdd..6c60318 100644
--- a/include/sound/msm-dai-q6-v2.h
+++ b/include/sound/msm-dai-q6-v2.h
@@ -20,6 +20,10 @@
#define MSM_MI2S_SD3 (1 << 3)
#define MSM_MI2S_CAP_RX 0
#define MSM_MI2S_CAP_TX 1
+#define MSM_PRIM_MI2S 0
+#define MSM_SEC_MI2S 1
+#define MSM_TERT_MI2S 2
+#define MSM_QUAD_MI2S 3
struct msm_dai_auxpcm_pdata {
const char *clk;
@@ -35,6 +39,11 @@
int pcm_clk_rate;
};
+struct msm_mi2s_pdata {
+ u16 rx_sd_lines;
+ u16 tx_sd_lines;
+};
+
struct msm_i2s_data {
u32 capability; /* RX or TX */
u16 sd_lines;
diff --git a/include/sound/q6adm.h b/include/sound/q6adm.h
index 676c4cb..70c68a8 100644
--- a/include/sound/q6adm.h
+++ b/include/sound/q6adm.h
@@ -37,6 +37,8 @@
int adm_close(int port);
+int adm_pseudo_close(int port);
+
int adm_matrix_map(int session_id, int path, int num_copps,
unsigned int *port_id, int copp_id);
@@ -45,6 +47,12 @@
void adm_ec_ref_rx_id(int port_id);
+int adm_connect_afe_port_v2(int mode, int session_id, int port_id,
+ int sample_rate, int channels);
+
+int adm_multi_ch_copp_pseudo_open_v3(int port_id, int path, int rate,
+ int channel_mode, int topology);
+
#ifdef CONFIG_RTAC
int adm_get_copp_id(int port_id);
#endif
diff --git a/include/sound/q6afe-v2.h b/include/sound/q6afe-v2.h
index e107130..1324f8a 100644
--- a/include/sound/q6afe-v2.h
+++ b/include/sound/q6afe-v2.h
@@ -16,6 +16,7 @@
#define IN 0x000
#define OUT 0x001
#define MSM_AFE_MONO 0
+#define MSM_AFE_CH_STEREO 1
#define MSM_AFE_MONO_RIGHT 1
#define MSM_AFE_MONO_LEFT 2
#define MSM_AFE_STEREO 3
diff --git a/include/sound/q6afe.h b/include/sound/q6afe.h
index a7264e8..1e12d48 100644
--- a/include/sound/q6afe.h
+++ b/include/sound/q6afe.h
@@ -70,6 +70,7 @@
IDX_RT_PROXY_PORT_001_TX = 31,
IDX_SECONDARY_PCM_RX = 32,
IDX_SECONDARY_PCM_TX = 33,
+ IDX_PSEUDOPORT_01 = 34,
AFE_MAX_PORTS
};
@@ -87,7 +88,10 @@
int afe_cmd_memory_map_nowait(u32 dma_addr_p, u32 dma_buf_sz);
int afe_cmd_memory_unmap(u32 dma_addr_p);
int afe_cmd_memory_unmap_nowait(u32 dma_addr_p);
-
+void afe_set_dtmf_gen_rx_portid(u16 rx_port_id, int set);
+int afe_dtmf_generate_rx(int64_t duration_in_ms,
+ uint16_t high_freq,
+ uint16_t low_freq, uint16_t gain);
int afe_register_get_events(u16 port_id,
void (*cb) (uint32_t opcode,
uint32_t token, uint32_t *payload, void *priv),
diff --git a/include/sound/q6asm.h b/include/sound/q6asm.h
index b0d74ba..6b4c17b 100644
--- a/include/sound/q6asm.h
+++ b/include/sound/q6asm.h
@@ -55,6 +55,7 @@
#define ENCDEC_SBCBITRATE 0x0001
#define ENCDEC_IMMEDIATE_DECODE 0x0002
#define ENCDEC_CFG_BLK 0x0003
+#define DTS_ENC_SAMPLE_RATE48k 48000
#define CMD_PAUSE 0x0001
#define CMD_FLUSH 0x0002
@@ -194,6 +195,11 @@
int q6asm_open_write_compressed(struct audio_client *ac, uint32_t format);
+int q6asm_open_transcode_loopback(struct audio_client *ac, uint32_t channels);
+
+int q6asm_enc_cfg_blk_dts(struct audio_client *ac,
+ uint32_t sample_rate, uint32_t channels);
+
int q6asm_open_read_write(struct audio_client *ac,
uint32_t rd_format,
uint32_t wr_format);
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 9885a9e..b175073 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -77,6 +77,14 @@
unsigned int sysctl_sched_child_runs_first __read_mostly;
/*
+ * Controls whether, when SD_SHARE_PKG_RESOURCES is on, if all
+ * tasks go to idle CPUs when woken. If this is off, note that the
+ * per-task flag PF_WAKE_ON_IDLE can still cause a task to go to an
+ * idle CPU upon being woken.
+ */
+unsigned int __read_mostly sysctl_sched_wake_to_idle;
+
+/*
* SCHED_OTHER wake-up granularity.
* (default: 1 msec * (1 + ilog(ncpus)), units: nanoseconds)
*
@@ -2654,7 +2662,8 @@
if (target == prev_cpu && idle_cpu(prev_cpu))
return prev_cpu;
- if (!(current->flags & PF_WAKE_UP_IDLE) &&
+ if (!sysctl_sched_wake_to_idle &&
+ !(current->flags & PF_WAKE_UP_IDLE) &&
!(p->flags & PF_WAKE_UP_IDLE))
return target;
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index b693142..b390dad 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -264,6 +264,13 @@
.mode = 0644,
.proc_handler = proc_dointvec,
},
+ {
+ .procname = "sched_wake_to_idle",
+ .data = &sysctl_sched_wake_to_idle,
+ .maxlen = sizeof(unsigned int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec,
+ },
#ifdef CONFIG_SCHED_DEBUG
{
.procname = "sched_min_granularity_ns",
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index b9d1a73..700d2ae 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -1630,7 +1630,7 @@
memcpy(&entry->buf, trace_buf, len);
entry->buf[len] = '\0';
if (!filter_check_discard(call, entry, buffer, event)) {
- stm_log(OST_ENTITY_TRACE_PRINTK, event, size);
+ stm_log(OST_ENTITY_TRACE_PRINTK, entry->buf, len + 1);
ring_buffer_unlock_commit(buffer, event);
ftrace_trace_stack(buffer, irq_flags, 6, pc);
}
@@ -3825,10 +3825,11 @@
if (entry->buf[cnt - 1] != '\n') {
entry->buf[cnt] = '\n';
entry->buf[cnt + 1] = '\0';
- } else
+ stm_log(OST_ENTITY_TRACE_MARKER, entry->buf, cnt + 2);
+ } else {
entry->buf[cnt] = '\0';
-
- stm_log(OST_ENTITY_TRACE_MARKER, event, size);
+ stm_log(OST_ENTITY_TRACE_MARKER, entry->buf, cnt + 1);
+ }
ring_buffer_unlock_commit(buffer, event);
written = cnt;
diff --git a/lib/Kconfig b/lib/Kconfig
index 4a8aba2..8437e36 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -378,4 +378,20 @@
Digital signature verification. Currently only RSA is supported.
Implementation is done using GnuPG MPI library
+config QMI_ENCDEC
+ bool
+ help
+ Library to encode & decode QMI messages from within
+ the kernel. The kernel drivers encode the C structure into
+ QMI message wire format and then send it over a transport.
+ The kernel drivers receive the QMI message over a transport
+ and then decode it into a C structure.
+
+config QMI_ENCDEC_DEBUG
+ bool
+ help
+ Kernel config option to enable debugging QMI Encode/Decode
+ library. This will log the information regarding the element
+ and message being encoded & decoded.
+
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index acd6869..0fbcb04 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,8 @@
obj-$(CONFIG_CLZ_TAB) += clz_tab.o
+obj-$(CONFIG_QMI_ENCDEC) += qmi_encdec.o
+
hostprogs-y := gen_crc32table
clean-files := crc32table.h
diff --git a/lib/qmi_encdec.c b/lib/qmi_encdec.c
new file mode 100644
index 0000000..40273d0
--- /dev/null
+++ b/lib/qmi_encdec.c
@@ -0,0 +1,555 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/qmi_encdec.h>
+
+#include "qmi_encdec_priv.h"
+
+#define TLV_LEN_SIZE sizeof(uint16_t)
+#define TLV_TYPE_SIZE sizeof(uint8_t)
+
+#ifdef CONFIG_QMI_ENCDEC_DEBUG
+
+#define qmi_encdec_dump(prefix_str, buf, buf_len) do { \
+ const u8 *ptr = buf; \
+ int i, linelen, remaining = buf_len; \
+ int rowsize = 16, groupsize = 1; \
+ unsigned char linebuf[256]; \
+ for (i = 0; i < buf_len; i += rowsize) { \
+ linelen = min(remaining, rowsize); \
+ remaining -= linelen; \
+ hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, \
+ linebuf, sizeof(linebuf), false); \
+ pr_debug("%s: %s\n", prefix_str, linebuf); \
+ } \
+} while (0)
+
+#define QMI_ENCODE_LOG_MSG(buf, buf_len) do { \
+ qmi_encdec_dump("QMI_ENCODE_MSG", buf, buf_len); \
+} while (0)
+
+#define QMI_DECODE_LOG_MSG(buf, buf_len) do { \
+ qmi_encdec_dump("QMI_DECODE_MSG", buf, buf_len); \
+} while (0)
+
+#define QMI_ENCODE_LOG_ELEM(level, elem_len, elem_size, buf) do { \
+ pr_debug("QMI_ENCODE_ELEM lvl: %d, len: %d, size: %d\n", \
+ level, elem_len, elem_size); \
+ qmi_encdec_dump("QMI_ENCODE_ELEM", buf, (elem_len * elem_size)); \
+} while (0)
+
+#define QMI_DECODE_LOG_ELEM(level, elem_len, elem_size, buf) do { \
+ pr_debug("QMI_DECODE_ELEM lvl: %d, len: %d, size: %d\n", \
+ level, elem_len, elem_size); \
+ qmi_encdec_dump("QMI_DECODE_ELEM", buf, (elem_len * elem_size)); \
+} while (0)
+
+#define QMI_ENCODE_LOG_TLV(tlv_type, tlv_len) do { \
+ pr_debug("QMI_ENCODE_TLV type: %d, len: %d\n", tlv_type, tlv_len); \
+} while (0)
+
+#define QMI_DECODE_LOG_TLV(tlv_type, tlv_len) do { \
+ pr_debug("QMI_DECODE_TLV type: %d, len: %d\n", tlv_type, tlv_len); \
+} while (0)
+
+#else
+
+#define QMI_ENCODE_LOG_MSG(buf, buf_len) { }
+#define QMI_DECODE_LOG_MSG(buf, buf_len) { }
+#define QMI_ENCODE_LOG_ELEM(level, elem_len, elem_size, buf) { }
+#define QMI_DECODE_LOG_ELEM(level, elem_len, elem_size, buf) { }
+#define QMI_ENCODE_LOG_TLV(tlv_type, tlv_len) { }
+#define QMI_DECODE_LOG_TLV(tlv_type, tlv_len) { }
+
+#endif
+
+static int _qmi_kernel_encode(struct elem_info *ei_array,
+ void *out_buf, void *in_c_struct,
+ int enc_level);
+
+static int _qmi_kernel_decode(struct elem_info *ei_array,
+ void *out_c_struct,
+ void *in_buf, uint32_t in_buf_len,
+ int dec_level);
+
+/**
+ * qmi_kernel_encode() - Encode to QMI message wire format
+ * @desc: Pointer to structure descriptor.
+ * @out_buf: Buffer to hold the encoded QMI message.
+ * @out_buf_len: Length of the out buffer.
+ * @in_c_struct: C Structure to be encoded.
+ *
+ * @return: size of encoded message on success, < 0 for error.
+ */
+int qmi_kernel_encode(struct msg_desc *desc,
+ void *out_buf, uint32_t out_buf_len,
+ void *in_c_struct)
+{
+ int enc_level = 1;
+
+ if (!desc || !desc->ei_array)
+ return -EINVAL;
+
+ if (!out_buf || !in_c_struct)
+ return -EINVAL;
+
+ if (desc->max_msg_len < out_buf_len)
+ return -ETOOSMALL;
+
+ return _qmi_kernel_encode(desc->ei_array, out_buf,
+ in_c_struct, enc_level);
+}
+EXPORT_SYMBOL(qmi_kernel_encode);
+
+/**
+ * qmi_encode_basic_elem() - Encodes elements of basic/primary data type
+ * @buf_dst: Buffer to store the encoded information.
+ * @buf_src: Buffer containing the elements to be encoded.
+ * @elem_len: Number of elements, in the buf_src, to be encoded.
+ * @elem_size: Size of a single instance of the element to be encoded.
+ *
+ * @return: number of bytes of encoded information.
+ *
+ * This function encodes the "elem_len" number of data elements, each of
+ * size "elem_size" bytes from the source buffer "buf_src" and stores the
+ * encoded information in the destination buffer "buf_dst". The elements are
+ * of primary data type which include uint8_t - uint64_t or similar. This
+ * function returns the number of bytes of encoded information.
+ */
+static int qmi_encode_basic_elem(void *buf_dst, void *buf_src,
+ uint32_t elem_len, uint32_t elem_size)
+{
+ uint32_t i, rc = 0;
+
+ for (i = 0; i < elem_len; i++) {
+ QMI_ENCDEC_ENCODE_N_BYTES(buf_dst, buf_src, elem_size);
+ rc += elem_size;
+ }
+
+ return rc;
+}
+
+/**
+ * qmi_encode_struct_elem() - Encodes elements of struct data type
+ * @ei_array: Struct info array descibing the struct element.
+ * @buf_dst: Buffer to store the encoded information.
+ * @buf_src: Buffer containing the elements to be encoded.
+ * @elem_len: Number of elements, in the buf_src, to be encoded.
+ * @enc_level: Depth of the nested structure from the main structure.
+ *
+ * @return: Mumber of bytes of encoded information, on success.
+ * < 0 on error.
+ *
+ * This function encodes the "elem_len" number of struct elements, each of
+ * size "ei_array->elem_size" bytes from the source buffer "buf_src" and
+ * stores the encoded information in the destination buffer "buf_dst". The
+ * elements are of struct data type which includes any C structure. This
+ * function returns the number of bytes of encoded information.
+ */
+static int qmi_encode_struct_elem(struct elem_info *ei_array,
+ void *buf_dst, void *buf_src,
+ uint32_t elem_len, int enc_level)
+{
+ int i, rc, encoded_bytes = 0;
+ struct elem_info *temp_ei = ei_array;
+
+ for (i = 0; i < elem_len; i++) {
+ rc = _qmi_kernel_encode(temp_ei->ei_array,
+ buf_dst, buf_src, enc_level);
+ if (rc < 0) {
+ pr_err("%s: STRUCT Encode failure\n", __func__);
+ return rc;
+ }
+ buf_dst = buf_dst + rc;
+ buf_src = buf_src + temp_ei->elem_size;
+ encoded_bytes += rc;
+ }
+
+ return encoded_bytes;
+}
+
+/**
+ * skip_to_next_elem() - Skip to next element in the structure to be encoded
+ * @ei_array: Struct info describing the element to be skipped.
+ *
+ * @return: Struct info of the next element that can be encoded.
+ *
+ * This function is used while encoding optional elements. If the flag
+ * corresponding to an optional element is not set, then encoding the
+ * optional element can be skipped. This function can be used to perform
+ * that operation.
+ */
+static struct elem_info *skip_to_next_elem(struct elem_info *ei_array)
+{
+ struct elem_info *temp_ei = ei_array;
+ uint8_t tlv_type;
+
+ do {
+ tlv_type = temp_ei->tlv_type;
+ temp_ei = temp_ei + 1;
+ } while (tlv_type == temp_ei->tlv_type);
+
+ return temp_ei;
+}
+
+/**
+ * _qmi_kernel_encode() - Core Encode Function
+ * @ei_array: Struct info array describing the structure to be encoded.
+ * @out_buf: Buffer to hold the encoded QMI message.
+ * @in_c_struct: Pointer to the C structure to be encoded.
+ * @enc_level: Encode level to indicate the depth of the nested structure,
+ * within the main structure, being encoded.
+ *
+ * @return: Number of bytes of encoded information, on success.
+ * < 0 on error.
+ */
+static int _qmi_kernel_encode(struct elem_info *ei_array,
+ void *out_buf, void *in_c_struct,
+ int enc_level)
+{
+ struct elem_info *temp_ei = ei_array;
+ uint8_t opt_flag_value = 0;
+ uint32_t data_len_value = 0, data_len_sz;
+ uint8_t *buf_dst = (uint8_t *)out_buf;
+ uint8_t *tlv_pointer;
+ uint32_t tlv_len;
+ uint8_t tlv_type;
+ uint32_t encoded_bytes = 0;
+ void *buf_src;
+ int encode_tlv = 0;
+ int rc;
+
+ tlv_pointer = buf_dst;
+ tlv_len = 0;
+ buf_dst = buf_dst + (TLV_LEN_SIZE + TLV_TYPE_SIZE);
+
+ while (temp_ei->data_type != QMI_EOTI) {
+ buf_src = in_c_struct + temp_ei->offset;
+ tlv_type = temp_ei->tlv_type;
+
+ if (temp_ei->is_array == NO_ARRAY) {
+ data_len_value = 1;
+ } else if (temp_ei->is_array == STATIC_ARRAY) {
+ data_len_value = temp_ei->elem_len;
+ } else if (data_len_value <= 0 ||
+ temp_ei->elem_len < data_len_value) {
+ pr_err("%s: Invalid data length\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (temp_ei->data_type) {
+ case QMI_OPT_FLAG:
+ rc = qmi_encode_basic_elem(&opt_flag_value, buf_src,
+ 1, sizeof(uint8_t));
+ if (opt_flag_value)
+ temp_ei = temp_ei + 1;
+ else
+ temp_ei = skip_to_next_elem(temp_ei);
+ break;
+
+ case QMI_DATA_LEN:
+ memcpy(&data_len_value, buf_src, temp_ei->elem_size);
+ data_len_sz = temp_ei->elem_size == sizeof(uint8_t) ?
+ sizeof(uint8_t) : sizeof(uint16_t);
+ rc = qmi_encode_basic_elem(buf_dst, &data_len_value,
+ 1, data_len_sz);
+ if (data_len_value) {
+ UPDATE_ENCODE_VARIABLES(temp_ei, buf_dst,
+ encoded_bytes, tlv_len, encode_tlv, rc);
+ encode_tlv = 0;
+ } else {
+ temp_ei = skip_to_next_elem(temp_ei);
+ }
+ break;
+
+ case QMI_UNSIGNED_1_BYTE:
+ case QMI_UNSIGNED_2_BYTE:
+ case QMI_UNSIGNED_4_BYTE:
+ case QMI_UNSIGNED_8_BYTE:
+ case QMI_SIGNED_2_BYTE_ENUM:
+ case QMI_SIGNED_4_BYTE_ENUM:
+ rc = qmi_encode_basic_elem(buf_dst, buf_src,
+ data_len_value, temp_ei->elem_size);
+ QMI_ENCODE_LOG_ELEM(enc_level, data_len_value,
+ temp_ei->elem_size, buf_src);
+ UPDATE_ENCODE_VARIABLES(temp_ei, buf_dst,
+ encoded_bytes, tlv_len, encode_tlv, rc);
+ break;
+
+ case QMI_STRUCT:
+ rc = qmi_encode_struct_elem(temp_ei, buf_dst, buf_src,
+ data_len_value, (enc_level + 1));
+ if (rc < 0)
+ return rc;
+ UPDATE_ENCODE_VARIABLES(temp_ei, buf_dst,
+ encoded_bytes, tlv_len, encode_tlv, rc);
+ break;
+
+ default:
+ pr_err("%s: Unrecognized data type\n", __func__);
+ return -EINVAL;
+
+ }
+
+ if (encode_tlv && enc_level == 1) {
+ QMI_ENCDEC_ENCODE_TLV(tlv_type, tlv_len, tlv_pointer);
+ QMI_ENCODE_LOG_TLV(tlv_type, tlv_len);
+ encoded_bytes += (TLV_TYPE_SIZE + TLV_LEN_SIZE);
+ tlv_pointer = buf_dst;
+ tlv_len = 0;
+ buf_dst = buf_dst + TLV_LEN_SIZE + TLV_TYPE_SIZE;
+ encode_tlv = 0;
+ }
+ }
+ QMI_ENCODE_LOG_MSG(out_buf, encoded_bytes);
+ return encoded_bytes;
+}
+
+/**
+ * qmi_kernel_decode() - Decode to C Structure format
+ * @desc: Pointer to structure descriptor.
+ * @out_c_struct: Buffer to hold the decoded C structure.
+ * @in_buf: Buffer containg the QMI message to be decoded.
+ * @in_buf_len: Length of the incoming QMI message.
+ *
+ * @return: 0 on success, < 0 on error.
+ */
+int qmi_kernel_decode(struct msg_desc *desc, void *out_c_struct,
+ void *in_buf, uint32_t in_buf_len)
+{
+ int dec_level = 1;
+ int rc = 0;
+
+ if (!desc || !desc->ei_array)
+ return -EINVAL;
+
+ if (!out_c_struct || !in_buf || !in_buf_len)
+ return -EINVAL;
+
+ if (desc->max_msg_len < in_buf_len)
+ return -EINVAL;
+
+ rc = _qmi_kernel_decode(desc->ei_array, out_c_struct,
+ in_buf, in_buf_len, dec_level);
+ if (rc < 0)
+ return rc;
+ else
+ return 0;
+}
+EXPORT_SYMBOL(qmi_kernel_decode);
+
+/**
+ * qmi_decode_basic_elem() - Decodes elements of basic/primary data type
+ * @buf_dst: Buffer to store the decoded element.
+ * @buf_src: Buffer containing the elements in QMI wire format.
+ * @elem_len: Number of elements to be decoded.
+ * @elem_size: Size of a single instance of the element to be decoded.
+ *
+ * @return: Total size of the decoded data elements, in bytes.
+ *
+ * This function decodes the "elem_len" number of elements in QMI wire format,
+ * each of size "elem_size" bytes from the source buffer "buf_src" and stores
+ * the decoded elements in the destination buffer "buf_dst". The elements are
+ * of primary data type which include uint8_t - uint64_t or similar. This
+ * function returns the number of bytes of decoded information.
+ */
+static int qmi_decode_basic_elem(void *buf_dst, void *buf_src,
+ uint32_t elem_len, uint32_t elem_size)
+{
+ uint32_t i, rc = 0;
+
+ for (i = 0; i < elem_len; i++) {
+ QMI_ENCDEC_DECODE_N_BYTES(buf_dst, buf_src, elem_size);
+ rc += elem_size;
+ }
+
+ return rc;
+}
+
+/**
+ * qmi_decode_struct_elem() - Decodes elements of struct data type
+ * @ei_array: Struct info array descibing the struct element.
+ * @buf_dst: Buffer to store the decoded element.
+ * @buf_src: Buffer containing the elements in QMI wire format.
+ * @elem_len: Number of elements to be decoded.
+ * @tlv_len: Total size of the encoded inforation corresponding to
+ * this struct element.
+ * @dec_level: Depth of the nested structure from the main structure.
+ *
+ * @return: Total size of the decoded data elements, on success.
+ * < 0 on error.
+ *
+ * This function decodes the "elem_len" number of elements in QMI wire format,
+ * each of size "(tlv_len/elem_len)" bytes from the source buffer "buf_src"
+ * and stores the decoded elements in the destination buffer "buf_dst". The
+ * elements are of struct data type which includes any C structure. This
+ * function returns the number of bytes of decoded information.
+ */
+static int qmi_decode_struct_elem(struct elem_info *ei_array, void *buf_dst,
+ void *buf_src, uint32_t elem_len,
+ uint32_t tlv_len, int dec_level)
+{
+ int i, rc, decoded_bytes = 0;
+ struct elem_info *temp_ei = ei_array;
+
+ for (i = 0; i < elem_len; i++) {
+ rc = _qmi_kernel_decode(temp_ei->ei_array, buf_dst, buf_src,
+ (tlv_len/elem_len), dec_level);
+ if (rc < 0)
+ return rc;
+ if (rc != (tlv_len/elem_len)) {
+ pr_err("%s: Fault in decoding\n", __func__);
+ return -EFAULT;
+ }
+ buf_src = buf_src + rc;
+ buf_dst = buf_dst + temp_ei->elem_size;
+ decoded_bytes += rc;
+ }
+
+ return decoded_bytes;
+}
+
+/**
+ * find_ei() - Find element info corresponding to TLV Type
+ * @ei_array: Struct info array of the message being decoded.
+ * @type: TLV Type of the element being searched.
+ *
+ * @return: Pointer to struct info, if found
+ *
+ * Every element that got encoded in the QMI message will have a type
+ * information associated with it. While decoding the QMI message,
+ * this function is used to find the struct info regarding the element
+ * that corresponds to the type being decoded.
+ */
+static struct elem_info *find_ei(struct elem_info *ei_array,
+ uint32_t type)
+{
+ struct elem_info *temp_ei = ei_array;
+ while (temp_ei->data_type != QMI_EOTI) {
+ if (temp_ei->tlv_type == (uint8_t)type)
+ return temp_ei;
+ temp_ei = temp_ei + 1;
+ }
+ return NULL;
+}
+
+/**
+ * _qmi_kernel_decode() - Core Decode Function
+ * @ei_array: Struct info array describing the structure to be decoded.
+ * @out_c_struct: Buffer to hold the decoded C struct
+ * @in_buf: Buffer containing the QMI message to be decoded
+ * @in_buf_len: Length of the QMI message to be decoded
+ * @dec_level: Decode level to indicate the depth of the nested structure,
+ * within the main structure, being decoded
+ *
+ * @return: Number of bytes of decoded information, on success
+ * < 0 on error.
+ */
+static int _qmi_kernel_decode(struct elem_info *ei_array,
+ void *out_c_struct,
+ void *in_buf, uint32_t in_buf_len,
+ int dec_level)
+{
+ struct elem_info *temp_ei = ei_array;
+ uint8_t opt_flag_value = 1;
+ uint32_t data_len_value = 0, data_len_sz = 0;
+ uint8_t *buf_dst = out_c_struct;
+ uint8_t *tlv_pointer;
+ uint32_t tlv_len = 0;
+ uint32_t tlv_type;
+ uint32_t decoded_bytes = 0;
+ void *buf_src = in_buf;
+ int rc;
+
+ QMI_DECODE_LOG_MSG(in_buf, in_buf_len);
+ while (decoded_bytes < in_buf_len) {
+ if (dec_level == 1) {
+ tlv_pointer = buf_src;
+ QMI_ENCDEC_DECODE_TLV(&tlv_type,
+ &tlv_len, tlv_pointer);
+ QMI_DECODE_LOG_TLV(tlv_type, tlv_len);
+ buf_src += (TLV_TYPE_SIZE + TLV_LEN_SIZE);
+ decoded_bytes += (TLV_TYPE_SIZE + TLV_LEN_SIZE);
+ temp_ei = find_ei(ei_array, tlv_type);
+ if (!temp_ei) {
+ pr_err("%s: Inval element info\n", __func__);
+ return -EINVAL;
+ }
+ }
+
+ buf_dst = out_c_struct + temp_ei->offset;
+ if (temp_ei->data_type == QMI_OPT_FLAG) {
+ memcpy(buf_dst, &opt_flag_value, sizeof(uint8_t));
+ temp_ei = temp_ei + 1;
+ buf_dst = out_c_struct + temp_ei->offset;
+ }
+
+ if (temp_ei->data_type == QMI_DATA_LEN) {
+ data_len_sz = temp_ei->elem_size == sizeof(uint8_t) ?
+ sizeof(uint8_t) : sizeof(uint16_t);
+ rc = qmi_decode_basic_elem(&data_len_value, buf_src,
+ 1, data_len_sz);
+ memcpy(buf_dst, &data_len_value, sizeof(uint32_t));
+ temp_ei = temp_ei + 1;
+ buf_dst = out_c_struct + temp_ei->offset;
+ UPDATE_DECODE_VARIABLES(buf_src, decoded_bytes, rc);
+ }
+
+ if (temp_ei->is_array == NO_ARRAY) {
+ data_len_value = 1;
+ } else if (temp_ei->is_array == STATIC_ARRAY) {
+ data_len_value = temp_ei->elem_len;
+ } else if (data_len_value > temp_ei->elem_len) {
+ pr_err("%s: Data len %d > max spec %d\n",
+ __func__, data_len_value, temp_ei->elem_len);
+ return -ETOOSMALL;
+ }
+
+ switch (temp_ei->data_type) {
+ case QMI_UNSIGNED_1_BYTE:
+ case QMI_UNSIGNED_2_BYTE:
+ case QMI_UNSIGNED_4_BYTE:
+ case QMI_UNSIGNED_8_BYTE:
+ case QMI_SIGNED_2_BYTE_ENUM:
+ case QMI_SIGNED_4_BYTE_ENUM:
+ rc = qmi_decode_basic_elem(buf_dst, buf_src,
+ data_len_value, temp_ei->elem_size);
+ QMI_DECODE_LOG_ELEM(dec_level, data_len_value,
+ temp_ei->elem_size, buf_dst);
+ UPDATE_DECODE_VARIABLES(buf_src, decoded_bytes, rc);
+ break;
+
+ case QMI_STRUCT:
+ rc = qmi_decode_struct_elem(temp_ei, buf_dst, buf_src,
+ data_len_value, tlv_len, (dec_level + 1));
+ if (rc < 0)
+ return rc;
+ UPDATE_DECODE_VARIABLES(buf_src, decoded_bytes, rc);
+ break;
+ default:
+ pr_err("%s: Unrecognized data type\n", __func__);
+ return -EINVAL;
+ }
+ temp_ei = temp_ei + 1;
+ }
+ return decoded_bytes;
+}
+MODULE_DESCRIPTION("QMI kernel enc/dec");
+MODULE_LICENSE("GPL v2");
diff --git a/lib/qmi_encdec_priv.h b/lib/qmi_encdec_priv.h
new file mode 100644
index 0000000..97fe45b
--- /dev/null
+++ b/lib/qmi_encdec_priv.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QMI_ENCDEC_PRIV_H_
+#define _QMI_ENCDEC_PRIV_H_
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/socket.h>
+#include <linux/gfp.h>
+#include <linux/qmi_encdec.h>
+
+#define QMI_ENCDEC_ENCODE_TLV(type, length, p_dst) do { \
+ *p_dst++ = type; \
+ *p_dst++ = ((uint8_t)((length) & 0xFF)); \
+ *p_dst++ = ((uint8_t)(((length) >> 8) & 0xFF)); \
+} while (0)
+
+#define QMI_ENCDEC_DECODE_TLV(p_type, p_length, p_src) do { \
+ *p_type = (uint8_t)*p_src++; \
+ *p_length = (uint8_t)*p_src++; \
+ *p_length |= ((uint8_t)*p_src) << 8; \
+} while (0)
+
+#define QMI_ENCDEC_ENCODE_N_BYTES(p_dst, p_src, size) \
+do { \
+ memcpy(p_dst, p_src, size); \
+ p_dst = (uint8_t *)p_dst + size; \
+ p_src = (uint8_t *)p_src + size; \
+} while (0)
+
+#define QMI_ENCDEC_DECODE_N_BYTES(p_dst, p_src, size) \
+do { \
+ memcpy(p_dst, p_src, size); \
+ p_dst = (uint8_t *)p_dst + size; \
+ p_src = (uint8_t *)p_src + size; \
+} while (0)
+
+#define UPDATE_ENCODE_VARIABLES(temp_si, buf_dst, \
+ encoded_bytes, tlv_len, encode_tlv, rc) \
+do { \
+ buf_dst = (uint8_t *)buf_dst + rc; \
+ encoded_bytes += rc; \
+ tlv_len += rc; \
+ temp_si = temp_si + 1; \
+ encode_tlv = 1; \
+} while (0)
+
+#define UPDATE_DECODE_VARIABLES(buf_src, decoded_bytes, rc) \
+do { \
+ buf_src = (uint8_t *)buf_src + rc; \
+ decoded_bytes += rc; \
+} while (0)
+
+#endif
diff --git a/mm/Kconfig b/mm/Kconfig
index 4cde97f..bbab5a6 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -390,3 +390,14 @@
the memory corresponding to the hole to be removed using memblock-
remove.
+config USE_USER_ACCESSIBLE_TIMERS
+ bool "Enables timers accessible from userspace"
+ depends on MMU
+ help
+ User-accessible timers allow the kernel to map kernel timer
+ registers to a userspace accessible page, to allow faster
+ access to time information. This flag will enable the
+ interface code in the main kernel. However, there are
+ architecture-specific code that will need to be enabled
+ separately.
+
diff --git a/mm/memory.c b/mm/memory.c
index 6105f47..174fcaa 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -1726,6 +1726,19 @@
goto next_page;
}
+ if (use_user_accessible_timers()) {
+ if (!vma && in_user_timers_area(mm, start)) {
+ int goto_next_page = 0;
+ int user_timer_ret = get_user_timer_page(vma,
+ mm, start, gup_flags, pages, i,
+ &goto_next_page);
+ if (goto_next_page)
+ goto next_page;
+ else
+ return user_timer_ret;
+ }
+ }
+
if (!vma ||
(vma->vm_flags & (VM_IO | VM_PFNMAP)) ||
!(vm_flags & vma->vm_flags))
diff --git a/mm/mlock.c b/mm/mlock.c
index ef726e8..38c77ab 100644
--- a/mm/mlock.c
+++ b/mm/mlock.c
@@ -229,7 +229,9 @@
if (!((vma->vm_flags & (VM_DONTEXPAND | VM_RESERVED)) ||
is_vm_hugetlb_page(vma) ||
- vma == get_gate_vma(current->mm))) {
+ vma == get_gate_vma(current->mm) ||
+ ((use_user_accessible_timers() &&
+ (vma == get_user_timers_vma(current->mm)))))) {
__mlock_vma_pages_range(vma, start, end, NULL);
@@ -324,7 +326,9 @@
int lock = !!(newflags & VM_LOCKED);
if (newflags == vma->vm_flags || (vma->vm_flags & VM_SPECIAL) ||
- is_vm_hugetlb_page(vma) || vma == get_gate_vma(current->mm))
+ is_vm_hugetlb_page(vma) || vma == get_gate_vma(current->mm) ||
+ ((use_user_accessible_timers()) &&
+ (vma == get_user_timers_vma(current->mm))))
goto out; /* don't set VM_LOCKED, don't count */
pgoff = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT);
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 831509c..c3142e8 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -913,6 +913,11 @@
[MIGRATE_ISOLATE] = { MIGRATE_RESERVE }, /* Never used */
};
+int *get_migratetype_fallbacks(int mtype)
+{
+ return fallbacks[mtype];
+}
+
/*
* Move the free pages in a range to the free lists of the requested type.
* Note that start_page and end_pages are not aligned on a pageblock
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index 22a4dbe..fa2469e 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -1426,6 +1426,11 @@
} else {
u16 flags;
+ if (!(pi->conn)) {
+ kfree_skb(skb);
+ return;
+ }
+
bt_cb(skb)->force_active = pi->force_active;
BT_DBG("Sending on BR/EDR connection %p", pi->conn->hcon);
diff --git a/net/wireless/mlme.c b/net/wireless/mlme.c
index f5a7ac3..dd99041 100644
--- a/net/wireless/mlme.c
+++ b/net/wireless/mlme.c
@@ -954,3 +954,16 @@
return nl80211_unexpected_4addr_frame(dev, addr, gfp);
}
EXPORT_SYMBOL(cfg80211_rx_unexpected_4addr_frame);
+
+int cfg80211_ft_event(struct net_device *dev,
+ struct cfg80211_ft_event_params ft_event)
+{
+ int err = 0;
+ struct wiphy *wiphy = dev->ieee80211_ptr->wiphy;
+ struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
+
+ nl80211_ft_event(rdev, dev, ft_event);
+
+ return err;
+}
+EXPORT_SYMBOL(cfg80211_ft_event);
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index e322d4d..0410707 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -206,6 +206,9 @@
[NL80211_ATTR_NOACK_MAP] = { .type = NLA_U16 },
[NL80211_ATTR_INACTIVITY_TIMEOUT] = { .type = NLA_U16 },
[NL80211_ATTR_BG_SCAN_PERIOD] = { .type = NLA_U16 },
+ [NL80211_ATTR_MDID] = { .type = NLA_U16 },
+ [NL80211_ATTR_IE_RIC] = { .type = NLA_BINARY,
+ .len = IEEE80211_MAX_DATA_LEN },
};
/* policy for the key attributes */
@@ -6299,6 +6302,26 @@
return 0;
}
+static int nl80211_update_ft_ies(struct sk_buff *skb, struct genl_info *info)
+{
+ struct cfg80211_registered_device *rdev = info->user_ptr[0];
+ struct cfg80211_update_ft_ies_params ft_params;
+ struct net_device *dev = info->user_ptr[1];
+
+ if (!info->attrs[NL80211_ATTR_MDID])
+ return -EINVAL;
+
+ ft_params.md = nla_get_u16(info->attrs[NL80211_ATTR_MDID]);
+
+ if (!info->attrs[NL80211_ATTR_IE])
+ return -EINVAL;
+
+ ft_params.ie = nla_data(info->attrs[NL80211_ATTR_IE]);
+ ft_params.ie_len = nla_len(info->attrs[NL80211_ATTR_IE]);
+
+ return rdev->ops->update_ft_ies(&rdev->wiphy, dev, &ft_params);
+}
+
#define NL80211_FLAG_NEED_WIPHY 0x01
#define NL80211_FLAG_NEED_NETDEV 0x02
#define NL80211_FLAG_NEED_RTNL 0x04
@@ -6887,6 +6910,14 @@
.internal_flags = NL80211_FLAG_NEED_NETDEV |
NL80211_FLAG_NEED_RTNL,
},
+ {
+ .cmd = NL80211_CMD_UPDATE_FT_IES,
+ .doit = nl80211_update_ft_ies,
+ .policy = nl80211_policy,
+ .flags = GENL_ADMIN_PERM,
+ .internal_flags = NL80211_FLAG_NEED_NETDEV_UP |
+ NL80211_FLAG_NEED_RTNL,
+ },
};
@@ -8080,6 +8111,47 @@
.notifier_call = nl80211_netlink_notify,
};
+void nl80211_ft_event(struct cfg80211_registered_device *rdev,
+ struct net_device *netdev, struct cfg80211_ft_event_params ft_event)
+{
+ struct sk_buff *msg;
+ void *hdr;
+
+ msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+ if (!msg)
+ return;
+
+ hdr = nl80211hdr_put(msg, 0, 0, 0, NL80211_CMD_FT_EVENT);
+ if (!hdr) {
+ nlmsg_free(msg);
+ return;
+ }
+
+ NLA_PUT_U32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx);
+ NLA_PUT_U32(msg, NL80211_ATTR_IFINDEX, netdev->ifindex);
+ if (ft_event.target_ap)
+ NLA_PUT(msg, NL80211_ATTR_MAC, ETH_ALEN, ft_event.target_ap);
+ if (ft_event.ies)
+ NLA_PUT(msg, NL80211_ATTR_IE, ft_event.ies_len, ft_event.ies);
+ if (ft_event.ric_ies)
+ NLA_PUT(msg, NL80211_ATTR_IE_RIC, ft_event.ric_ies_len,
+ ft_event.ric_ies);
+
+ if (genlmsg_end(msg, hdr) < 0) {
+ nlmsg_free(msg);
+ return;
+ }
+
+ genlmsg_multicast_netns(wiphy_net(&rdev->wiphy), msg, 0,
+ nl80211_mlme_mcgrp.id, GFP_KERNEL);
+ return;
+
+ nla_put_failure:
+ genlmsg_cancel(msg, hdr);
+ nlmsg_free(msg);
+}
+
+
/* initialisation/exit functions */
int nl80211_init(void)
diff --git a/net/wireless/nl80211.h b/net/wireless/nl80211.h
index 4ffe50d..ffd4c8a 100644
--- a/net/wireless/nl80211.h
+++ b/net/wireless/nl80211.h
@@ -123,4 +123,8 @@
bool nl80211_unexpected_4addr_frame(struct net_device *dev,
const u8 *addr, gfp_t gfp);
+void nl80211_ft_event(struct cfg80211_registered_device *rdev,
+ struct net_device *netdev,
+ struct cfg80211_ft_event_params ft_event);
+
#endif /* __NET_WIRELESS_NL80211_H */
diff --git a/sound/soc/codecs/cs8427.c b/sound/soc/codecs/cs8427.c
index 23870a4..6e08742 100644
--- a/sound/soc/codecs/cs8427.c
+++ b/sound/soc/codecs/cs8427.c
@@ -110,7 +110,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(1);
+ err = pdata->enable(1, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to enable the level shifter\n");
@@ -124,7 +124,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(0);
+ err = pdata->enable(0, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to disable the level shifter\n");
@@ -192,7 +192,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(1);
+ err = pdata->enable(1, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to enable the level shifter\n");
@@ -207,7 +207,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(0);
+ err = pdata->enable(0, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to disable the level shifter\n");
@@ -239,7 +239,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(1);
+ err = pdata->enable(1, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to enable the level shifter\n");
@@ -262,7 +262,7 @@
* with CS8427 chip
*/
if (pdata->enable) {
- err = pdata->enable(0);
+ err = pdata->enable(0, pdata->ls_gpio);
if (err < 0) {
dev_err(&chip->client->dev,
"failed to disable the level shifter\n");
@@ -734,6 +734,16 @@
struct cs8427_platform_data *pdata = chip->client->dev.platform_data;
int ret = 0;
+ if (pdata->enable) {
+ ret = gpio_request(pdata->ls_gpio, "cs8427 ls");
+ if (ret < 0) {
+ dev_err(&chip->client->dev,
+ "failed to request the gpio %d\n",
+ pdata->reset_gpio);
+ return ret;
+ }
+ }
+
ret = gpio_request(pdata->reset_gpio, "cs8427 reset");
if (ret < 0) {
dev_err(&chip->client->dev,
@@ -928,8 +938,10 @@
}
pdata = chip->client->dev.platform_data;
gpio_free(pdata->reset_gpio);
- if (pdata->enable)
- pdata->enable(0);
+ if (pdata->enable) {
+ pdata->enable(0, pdata->ls_gpio);
+ gpio_free(pdata->ls_gpio);
+ }
kfree(chip);
return 0;
}
diff --git a/sound/soc/codecs/wcd9304.c b/sound/soc/codecs/wcd9304.c
index 5dcfefd..412090f 100644
--- a/sound/soc/codecs/wcd9304.c
+++ b/sound/soc/codecs/wcd9304.c
@@ -1238,9 +1238,9 @@
snd_soc_update_bits(codec, lineout_gain_reg, 0x10, 0x10);
break;
case SND_SOC_DAPM_POST_PMU:
- pr_debug("%s: sleeping 16 ms after %s PA turn on\n",
+ pr_debug("%s: sleeping 32 ms after %s PA turn on\n",
__func__, w->name);
- usleep_range(16000, 16000);
+ usleep_range(32000, 32000);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, lineout_gain_reg, 0x10, 0x00);
@@ -2056,6 +2056,24 @@
return 0;
}
+static int sitar_ear_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ pr_debug("%s: Sleeping 20ms after enabling EAR PA\n",
+ __func__);
+ msleep(20);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ pr_debug("%s: Sleeping 20ms after disabling EAR PA\n",
+ __func__);
+ msleep(20);
+ break;
+ }
+ return 0;
+}
+
static const struct snd_soc_dapm_widget sitar_dapm_i2s_widgets[] = {
SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", SITAR_A_CDC_CLK_RX_I2S_CTL,
4, 0, NULL, 0),
@@ -2067,7 +2085,9 @@
/*RX stuff */
SND_SOC_DAPM_OUTPUT("EAR"),
- SND_SOC_DAPM_PGA("EAR PA", SITAR_A_RX_EAR_EN, 4, 0, NULL, 0),
+ SND_SOC_DAPM_PGA_E("EAR PA", SITAR_A_RX_EAR_EN, 4, 0, NULL, 0,
+ sitar_ear_pa_event, SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("DAC1", SITAR_A_RX_EAR_EN, 6, 0, dac1_switch,
ARRAY_SIZE(dac1_switch)),
SND_SOC_DAPM_SUPPLY("EAR DRIVER", SITAR_A_RX_EAR_EN, 3, 0, NULL, 0),
@@ -5137,6 +5157,8 @@
SITAR_REG_VAL(SITAR_A_RX_EAR_GAIN, 0x02),
SITAR_REG_VAL(SITAR_A_RX_EAR_VCM, 0x03),
+ SITAR_REG_VAL(SITAR_A_RX_LINE_BIAS_PA, 0xA7),
+
SITAR_REG_VAL(SITAR_A_CDC_RX1_B5_CTL, 0x78),
SITAR_REG_VAL(SITAR_A_CDC_RX2_B5_CTL, 0x78),
SITAR_REG_VAL(SITAR_A_CDC_RX3_B5_CTL, 0x78),
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 6b3287e..f28fd774 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -1889,6 +1889,8 @@
pr_err:
pr_err("%s: RX%u is used by current requesting AIF_PB itself\n",
__func__, port_id + 1);
+ mutex_unlock(&codec->mutex);
+ return 0;
err:
mutex_unlock(&codec->mutex);
return -EINVAL;
diff --git a/sound/soc/codecs/wcd9320.c b/sound/soc/codecs/wcd9320.c
index 95df162..8fdf4f2 100644
--- a/sound/soc/codecs/wcd9320.c
+++ b/sound/soc/codecs/wcd9320.c
@@ -45,7 +45,8 @@
#define TAIKO_TX_PORT_NUMBER 16
#define TAIKO_I2S_MASTER_MODE_MASK 0x08
-
+#define TAIKO_MCLK_CLK_12P288MHZ 12288000
+#define TAIKO_MCLK_CLK_9P6HZ 9600000
enum {
AIF1_PB = 0,
AIF1_CAP,
@@ -318,7 +319,6 @@
case SND_SOC_DAPM_PRE_PMU:
snd_soc_update_bits(codec, w->reg, 0x01, 0x01);
snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x0f, 0x01);
break;
case SND_SOC_DAPM_POST_PMU:
@@ -328,7 +328,6 @@
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, w->reg, 0x01, 0x00);
snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
- snd_soc_update_bits(codec, TAIKO_A_NCP_STATIC, 0x0f, 0x08);
break;
}
return 0;
@@ -1540,45 +1539,50 @@
return -EINVAL;
}
}
- switch (dai_id) {
- case AIF1_CAP:
- case AIF2_CAP:
- case AIF3_CAP:
- /* only add to the list if value not set
- */
- if (enable && !(widget->value & 1 << port_id)) {
- if (wcd9xxx_tx_vport_validation(
+ if (taiko_p->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ switch (dai_id) {
+ case AIF1_CAP:
+ case AIF2_CAP:
+ case AIF3_CAP:
+ /* only add to the list if value not set
+ */
+ if (enable && !(widget->value & 1 << port_id)) {
+ if (wcd9xxx_tx_vport_validation(
vport_check_table[dai_id],
port_id,
taiko_p->dai)) {
- pr_info("%s: TX%u is used by other virtual port\n",
- __func__, port_id + 1);
- mutex_unlock(&codec->mutex);
- return -EINVAL;
- }
- widget->value |= 1 << port_id;
- list_add_tail(&core->tx_chs[port_id].list,
+ pr_debug("%s: TX%u is used by other\n"
+ "virtual port\n",
+ __func__, port_id + 1);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ widget->value |= 1 << port_id;
+ list_add_tail(&core->tx_chs[port_id].list,
&taiko_p->dai[dai_id].wcd9xxx_ch_list
- );
- } else if (!enable && (widget->value & 1 << port_id)) {
- widget->value &= ~(1 << port_id);
- list_del_init(&core->tx_chs[port_id].list);
- } else {
- if (enable)
- pr_info("%s: TX%u port is used by this virtual port\n",
- __func__, port_id + 1);
- else
- pr_info("%s: TX%u port is not used by this virtual port\n",
- __func__, port_id + 1);
- /* avoid update power function */
+ );
+ } else if (!enable && (widget->value & 1 << port_id)) {
+ widget->value &= ~(1 << port_id);
+ list_del_init(&core->tx_chs[port_id].list);
+ } else {
+ if (enable)
+ pr_debug("%s: TX%u port is used by\n"
+ "this virtual port\n",
+ __func__, port_id + 1);
+ else
+ pr_debug("%s: TX%u port is not used by\n"
+ "this virtual port\n",
+ __func__, port_id + 1);
+ /* avoid update power function */
+ mutex_unlock(&codec->mutex);
+ return 0;
+ }
+ break;
+ default:
+ pr_err("Unknown AIF %d\n", dai_id);
mutex_unlock(&codec->mutex);
- return 0;
+ return -EINVAL;
}
- break;
- default:
- pr_err("Unknown AIF %d\n", dai_id);
- mutex_unlock(&codec->mutex);
- return -EINVAL;
}
pr_debug("%s: name %s sname %s updated value %u shift %d\n", __func__,
widget->name, widget->sname, widget->value, widget->shift);
@@ -2084,7 +2088,6 @@
/* Let MBHC module know so micbias switch to be off */
wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_pre_on);
- snd_soc_update_bits(codec, w->reg, 0x0E, 0x0A);
/* Get cfilt */
wcd9xxx_resmgr_cfilt_get(&taiko->resmgr, cfilt_sel_val);
@@ -2441,10 +2444,10 @@
{"SLIM RX3", NULL, "RX_I2S_CLK"},
{"SLIM RX4", NULL, "RX_I2S_CLK"},
- {"SLIM TX7", NULL, "TX_I2S_CLK"},
- {"SLIM TX8", NULL, "TX_I2S_CLK"},
- {"SLIM TX9", NULL, "TX_I2S_CLK"},
- {"SLIM TX10", NULL, "TX_I2S_CLK"},
+ {"SLIM TX7 MUX", NULL, "TX_I2S_CLK"},
+ {"SLIM TX8 MUX", NULL, "TX_I2S_CLK"},
+ {"SLIM TX9 MUX", NULL, "TX_I2S_CLK"},
+ {"SLIM TX10 MUX", NULL, "TX_I2S_CLK"},
};
static const struct snd_soc_dapm_route audio_map[] = {
@@ -3104,7 +3107,11 @@
static int taiko_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
- pr_debug("%s\n", __func__);
+ struct snd_soc_codec *codec = dai->codec;
+ if (freq == TAIKO_MCLK_CLK_12P288MHZ)
+ snd_soc_write(codec, TAIKO_A_CHIP_CTL, 0x04);
+ else if (freq == TAIKO_MCLK_CLK_9P6HZ)
+ snd_soc_write(codec, TAIKO_A_CHIP_CTL, 0x0A);
return 0;
}
@@ -4471,9 +4478,6 @@
TAIKO_REG_VAL(TAIKO_A_CDC_RX5_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX6_B6_CTL, 0x80),
TAIKO_REG_VAL(TAIKO_A_CDC_RX7_B6_CTL, 0x80),
-
- /* TX VHIGH comparator */
- TAIKO_REG_VAL(TAIKO_A_TX_SUP_SWITCH_CTRL_2, 0x90),
};
static const struct taiko_reg_mask_val taiko_1_0_reg_defaults[] = {
@@ -4497,6 +4501,19 @@
TAIKO_REG_VAL(TAIKO_A_RX_EAR_BIAS_PA, 0x76),
/* Reduce LINE DAC bias to 70% */
TAIKO_REG_VAL(TAIKO_A_RX_LINE_BIAS_PA, 0x78),
+
+ /*
+ * There is a diode to pull down the micbias while doing
+ * insertion detection. This diode can cause leakage.
+ * Set bit 0 to 1 to prevent leakage.
+ * Setting this bit of micbias 2 prevents leakage for all other micbias.
+ */
+ TAIKO_REG_VAL(TAIKO_A_MICB_2_MBHC, 0x41),
+
+ /* Disable TX7 internal biasing path which can cause leakage */
+ TAIKO_REG_VAL(TAIKO_A_TX_SUP_SWITCH_CTRL_1, 0xBF),
+ /* Enable MICB 4 VDDIO switch to prevent leakage */
+ TAIKO_REG_VAL(TAIKO_A_MICB_4_MBHC, 0x81),
};
static void taiko_update_reg_defaults(struct snd_soc_codec *codec)
diff --git a/sound/soc/codecs/wcd9320.h b/sound/soc/codecs/wcd9320.h
index 7bc5a57..1fff80c 100644
--- a/sound/soc/codecs/wcd9320.h
+++ b/sound/soc/codecs/wcd9320.h
@@ -23,6 +23,7 @@
#define TAIKO_CACHE_SIZE TAIKO_NUM_REGISTERS
#define TAIKO_REG_VAL(reg, val) {reg, 0, val}
+#define TAIKO_MCLK_ID 0
extern const u8 taiko_reg_readable[TAIKO_CACHE_SIZE];
extern const u8 taiko_reset_reg_defaults[TAIKO_CACHE_SIZE];
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index 653effa..0f2a19c 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -9,6 +9,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+
#include <linux/module.h>
#include <linux/init.h>
#include <linux/firmware.h>
@@ -566,15 +567,6 @@
ins ? "insert" : "removal");
/* Disable detection to avoid glitch */
snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MBHC_INSERT_DETECT, 1, 0);
- /* Override mbhc power switch to avoid false IRQs */
- snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MICB_1_MBHC, 1 << 2,
- !ins << 2);
- snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MICB_2_MBHC, 1 << 2,
- !ins << 2);
- snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MICB_3_MBHC, 1 << 2,
- !ins << 2);
- snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MICB_4_MBHC, 1 << 2,
- !ins << 2);
snd_soc_write(mbhc->codec, WCD9XXX_A_MBHC_INSERT_DETECT,
(0x68 | (ins ? (1 << 1) : 0)));
/* Re-enable detection */
@@ -938,6 +930,23 @@
return abs(mic_volt - mic_volt_prev) > threshold;
}
+static void wcd9xxx_onoff_vddio_switch(struct wcd9xxx_mbhc *mbhc, bool on)
+{
+ if (on) {
+ snd_soc_update_bits(mbhc->codec, mbhc->mbhc_bias_regs.mbhc_reg,
+ 1 << 7, 1 << 7);
+ snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MAD_ANA_CTRL,
+ 1 << 4, 0);
+ } else {
+ snd_soc_update_bits(mbhc->codec, WCD9XXX_A_MAD_ANA_CTRL,
+ 1 << 4, 1 << 4);
+ snd_soc_update_bits(mbhc->codec, mbhc->mbhc_bias_regs.mbhc_reg,
+ 1 << 7, 0);
+ }
+ if (on)
+ usleep_range(10000, 10000);
+}
+
/* called under codec_resource_lock acquisition and mbhc override = 1 */
static enum wcd9xxx_mbhc_plug_type
wcd9xxx_codec_get_plug_type(struct wcd9xxx_mbhc *mbhc, bool highhph)
@@ -988,8 +997,7 @@
scaled = mic_mv[i];
} else {
if (vddioswitch)
- __wcd9xxx_switch_micbias(mbhc, 1,
- false, false);
+ wcd9xxx_onoff_vddio_switch(mbhc, true);
if (gndswitch)
wcd9xxx_codec_hphr_gnd_switch(codec, true);
mb_v[i] = __wcd9xxx_codec_sta_dce(mbhc, 1, true, true);
@@ -1012,8 +1020,7 @@
if (gndswitch)
wcd9xxx_codec_hphr_gnd_switch(codec, false);
if (vddioswitch)
- __wcd9xxx_switch_micbias(mbhc, 0,
- false, false);
+ wcd9xxx_onoff_vddio_switch(mbhc, false);
/* claim UNSUPPORTED plug insertion when
* good headset is detected but HPHR GND switch makes
* delta difference */
@@ -1577,7 +1584,7 @@
vddio = (mbhc->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
mbhc->mbhc_micbias_switched);
if (vddio)
- __wcd9xxx_switch_micbias(mbhc, 0, false, true);
+ wcd9xxx_onoff_vddio_switch(mbhc, true);
if (mbhc->mbhc_cfg->detect_extn_cable &&
!wcd9xxx_swch_level_remove(mbhc))
@@ -1591,7 +1598,7 @@
* switch is off by time now and shouldn't be turn on again from here
*/
if (vddio && mbhc->current_plug == PLUG_TYPE_HEADSET)
- __wcd9xxx_switch_micbias(mbhc, 1, true, true);
+ wcd9xxx_onoff_vddio_switch(mbhc, true);
WCD9XXX_BCL_UNLOCK(mbhc->resmgr);
return IRQ_HANDLED;
@@ -2483,7 +2490,7 @@
static void wcd9xxx_mbhc_cal(struct wcd9xxx_mbhc *mbhc)
{
- u8 cfilt_mode, bg_mode;
+ u8 cfilt_mode;
struct snd_soc_codec *codec = mbhc->codec;
pr_debug("%s: enter\n", __func__);
@@ -2501,8 +2508,6 @@
*/
cfilt_mode = snd_soc_read(codec, mbhc->mbhc_bias_regs.cfilt_ctl);
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.cfilt_ctl, 0x40, 0x00);
- bg_mode = snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL,
- 0x02, 0x02);
/*
* Micbias, CFILT, LDOH, MBHC MUX mode settings
@@ -2555,14 +2560,13 @@
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, 0x04, 0x00);
snd_soc_update_bits(codec, mbhc->mbhc_bias_regs.cfilt_ctl, 0x40,
cfilt_mode);
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x02,
- bg_mode);
snd_soc_write(codec, WCD9XXX_A_MBHC_SCALING_MUX_1, 0x84);
usleep_range(100, 100);
wcd9xxx_enable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL);
wcd9xxx_turn_onoff_rel_detection(codec, true);
+
pr_debug("%s: leave\n", __func__);
}
@@ -3031,7 +3035,7 @@
break;
/* PA usage change */
case WCD9XXX_EVENT_PRE_HPHL_PA_ON:
- if (!(snd_soc_read(codec, mbhc->mbhc_bias_regs.ctl_reg & 0x80)))
+ if (!(snd_soc_read(codec, mbhc->mbhc_bias_regs.ctl_reg) & 0x80))
/* if micbias is enabled, switch to vddio */
wcd9xxx_switch_micbias(mbhc, 1);
break;
@@ -3187,10 +3191,6 @@
return ret;
}
- mbhc->mbhc_cfg = kzalloc(sizeof(*mbhc->mbhc_cfg), GFP_KERNEL);
- if (!mbhc->mbhc_cfg)
- return -ENOMEM;
-
INIT_DELAYED_WORK(&mbhc->mbhc_firmware_dwork, wcd9xxx_mbhc_fw_read);
INIT_DELAYED_WORK(&mbhc->mbhc_btn_dwork, wcd9xxx_btn_lpress_fn);
INIT_DELAYED_WORK(&mbhc->mbhc_insert_dwork, wcd9xxx_mbhc_insert_work);
@@ -3300,8 +3300,6 @@
wcd9xxx_resmgr_unregister_notifier(mbhc->resmgr, &mbhc->nblock);
wcd9xxx_cleanup_debugfs(mbhc);
-
- kfree(mbhc->mbhc_cfg);
}
EXPORT_SYMBOL_GPL(wcd9xxx_mbhc_deinit);
diff --git a/sound/soc/codecs/wcd9xxx-resmgr.c b/sound/soc/codecs/wcd9xxx-resmgr.c
index 5dfa41c..3952dd5 100644
--- a/sound/soc/codecs/wcd9xxx-resmgr.c
+++ b/sound/soc/codecs/wcd9xxx-resmgr.c
@@ -111,7 +111,7 @@
blocking_notifier_call_chain(&resmgr->notifier, e, resmgr);
}
-static void wcd9xxx_codec_disable_bg(struct wcd9xxx_resmgr *resmgr)
+static void wcd9xxx_disable_bg(struct wcd9xxx_resmgr *resmgr)
{
/* Notify bg mode change */
wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_PRE_BG_OFF);
@@ -122,18 +122,28 @@
wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_POST_BG_OFF);
}
-static void wcd9xxx_codec_enable_bg_audio(struct wcd9xxx_resmgr *resmgr)
+/*
+ * BG enablement should always enable in slow mode.
+ * The fast mode doesn't need to be enabled as fast mode BG is to be driven
+ * by MBHC override.
+ */
+static void wcd9xxx_enable_bg(struct wcd9xxx_resmgr *resmgr)
{
struct snd_soc_codec *codec = resmgr->codec;
- /* Notify bandgap mode change */
- wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_PRE_BG_AUDIO_ON);
- /* Enable bg */
+ /* Enable BG in slow mode and precharge */
snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x80, 0x80);
snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x04, 0x04);
snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x01, 0x01);
usleep_range(1000, 1000);
snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x80, 0x00);
+}
+
+static void wcd9xxx_enable_bg_audio(struct wcd9xxx_resmgr *resmgr)
+{
+ /* Notify bandgap mode change */
+ wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_PRE_BG_AUDIO_ON);
+ wcd9xxx_enable_bg(resmgr);
/* Notify bandgap mode change */
wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_POST_BG_AUDIO_ON);
}
@@ -146,28 +156,15 @@
wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_PRE_BG_MBHC_ON);
/*
- * bandgap mode becomes fast,
* mclk should be off or clk buff source souldn't be VBG
* Let's turn off mclk always
*/
WARN_ON(snd_soc_read(codec, WCD9XXX_A_CLK_BUFF_EN2) & (1 << 2));
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x2, 0x2);
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x80, 0x80);
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x4, 0x4);
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x01, 0x01);
- usleep_range(1000, 1000);
- snd_soc_update_bits(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x80, 0x00);
-
+ wcd9xxx_enable_bg(resmgr);
/* Notify bandgap mode change */
wcd9xxx_resmgr_notifier_call(resmgr, WCD9XXX_EVENT_POST_BG_MBHC_ON);
}
-static void wcd9xxx_disable_bg(struct wcd9xxx_resmgr *resmgr)
-{
- struct snd_soc_codec *codec = resmgr->codec;
- snd_soc_write(codec, WCD9XXX_A_BIAS_CENTRAL_BG_CTL, 0x00);
-}
-
static void wcd9xxx_disable_clock_block(struct wcd9xxx_resmgr *resmgr)
{
struct snd_soc_codec *codec = resmgr->codec;
@@ -223,14 +220,14 @@
/* BG mode can be changed only with clock off */
clock_save = wcd9xxx_save_clock(resmgr);
/* Swtich BG mode */
- wcd9xxx_codec_disable_bg(resmgr);
- wcd9xxx_codec_enable_bg_audio(resmgr);
+ wcd9xxx_disable_bg(resmgr);
+ wcd9xxx_enable_bg_audio(resmgr);
/* restore clock */
wcd9xxx_restore_clock(resmgr, clock_save);
} else if (resmgr->bg_audio_users == 1) {
/* currently off, just enable it */
WARN_ON(resmgr->bandgap_type != WCD9XXX_BANDGAP_OFF);
- wcd9xxx_codec_enable_bg_audio(resmgr);
+ wcd9xxx_enable_bg_audio(resmgr);
}
resmgr->bandgap_type = WCD9XXX_BANDGAP_AUDIO_MODE;
break;
diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig
index 894e114..d5cada7 100644
--- a/sound/soc/msm/Kconfig
+++ b/sound/soc/msm/Kconfig
@@ -200,4 +200,15 @@
default n
help
To add support for SoC audio on APQ8060 board
+
+config SND_SOC_MDM9625
+ tristate "SoC Machine driver for MDM9625 boards"
+ depends on ARCH_MSM9625
+ select SND_SOC_QDSP6V2
+ select SND_SOC_MSM_STUB
+ select SND_SOC_WCD9320
+ select SND_SOC_MSM_HOSTLESS_PCM
+ select SND_DYNAMIC_MINORS
+ help
+ To add support for SoC audio on MDM9625 boards.
endmenu
diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile
index 99302eb..a4c365a 100644
--- a/sound/soc/msm/Makefile
+++ b/sound/soc/msm/Makefile
@@ -58,7 +58,7 @@
snd-soc-qdsp6-objs := msm-dai-q6.o msm-pcm-q6.o msm-multi-ch-pcm-q6.o msm-lowlatency-pcm-q6.o msm-pcm-routing.o msm-dai-fe.o msm-compr-q6.o msm-dai-stub.o
obj-$(CONFIG_SND_SOC_MSM_QDSP6_HDMI_AUDIO) += msm-dai-q6-hdmi.o
-obj-$(CONFIG_SND_SOC_VOICE) += msm-pcm-voice.o msm-pcm-voip.o
+obj-$(CONFIG_SND_SOC_VOICE) += msm-pcm-voice.o msm-pcm-voip.o msm-pcm-dtmf.o
snd-soc-qdsp6-objs += msm-pcm-lpa.o msm-pcm-afe.o
obj-$(CONFIG_SND_SOC_QDSP6) += snd-soc-qdsp6.o
@@ -84,3 +84,6 @@
snd-soc-qdsp6v2-objs := msm-dai-fe.o msm-dai-stub.o
obj-$(CONFIG_SND_SOC_QDSP6V2) += snd-soc-qdsp6v2.o
+#for MDM9625 sound card driver
+snd-soc-mdm9625-objs := mdm9625.o
+obj-$(CONFIG_SND_SOC_MDM9625) += snd-soc-mdm9625.o
diff --git a/sound/soc/msm/mdm9615.c b/sound/soc/msm/mdm9615.c
index 5a47efe..76cd625 100644
--- a/sound/soc/msm/mdm9615.c
+++ b/sound/soc/msm/mdm9615.c
@@ -1702,6 +1702,19 @@
return 0;
}
+
+static int mdm9615_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+
+ pr_debug("%s()\n", __func__);
+ rate->min = rate->max = 48000;
+
+ return 0;
+}
+
static int mdm9615_aux_pcm_get_gpios(void)
{
int ret = 0;
@@ -2014,6 +2027,30 @@
.no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
.ignore_suspend = 1,
},
+ {
+ .name = "DTMF RX Hostless",
+ .stream_name = "DTMF RX Hostless",
+ .cpu_dai_name = "DTMF_RX_HOSTLESS",
+ .platform_name = "msm-pcm-dtmf",
+ .dynamic = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .ignore_suspend = 1,
+ .be_id = MSM_FRONTEND_DAI_DTMF_RX,
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ },
+ {
+ .name = "DTMF TX",
+ .stream_name = "DTMF TX",
+ .cpu_dai_name = "msm-dai-stub",
+ .platform_name = "msm-pcm-dtmf",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .ignore_suspend = 1,
+ },
+
/* Backend BT DAI Links */
{
.name = LPASS_BE_INT_BT_SCO_RX,
@@ -2110,6 +2147,43 @@
.be_hw_params_fixup = mdm9615_auxpcm_be_params_fixup,
.ops = &mdm9615_sec_auxpcm_be_ops,
},
+ /* Incall Music BACK END DAI Link */
+ {
+ .name = LPASS_BE_VOICE_PLAYBACK_TX,
+ .stream_name = "Voice Farend Playback",
+ .cpu_dai_name = "msm-dai-q6.32773",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-rx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
+ .be_hw_params_fixup = mdm9615_be_hw_params_fixup,
+ },
+ /* Incall Record Uplink BACK END DAI Link */
+ {
+ .name = LPASS_BE_INCALL_RECORD_TX,
+ .stream_name = "Voice Uplink Capture",
+ .cpu_dai_name = "msm-dai-q6.32772",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
+ .be_hw_params_fixup = mdm9615_be_hw_params_fixup,
+ },
+ /* Incall Record Downlink BACK END DAI Link */
+ {
+ .name = LPASS_BE_INCALL_RECORD_RX,
+ .stream_name = "Voice Downlink Capture",
+ .cpu_dai_name = "msm-dai-q6.32771",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "msm-stub-codec.1",
+ .codec_dai_name = "msm-stub-tx",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
+ .be_hw_params_fixup = mdm9615_be_hw_params_fixup,
+ .ignore_pmdown_time = 1, /* this dailink has playback support */
+ },
};
static struct snd_soc_dai_link mdm9615_dai_i2s_tabla[] = {
diff --git a/sound/soc/msm/mdm9625.c b/sound/soc/msm/mdm9625.c
new file mode 100644
index 0000000..b1822f6
--- /dev/null
+++ b/sound/soc/msm/mdm9625.c
@@ -0,0 +1,798 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/qpnp/clkdiv.h>
+#include <sound/core.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/pcm.h>
+#include <sound/jack.h>
+#include <asm/mach-types.h>
+#include <mach/socinfo.h>
+#include <qdsp6v2/msm-pcm-routing-v2.h>
+#include "../codecs/wcd9320.h"
+
+/* MI2S GPIO SECTION */
+
+#define GPIO_MI2S_WS 12
+#define GPIO_MI2S_SCLK 15
+#define GPIO_MI2S_DOUT 14
+#define GPIO_MI2S_DIN 13
+#define GPIO_MI2S_MCLK 71
+
+/* Spk control */
+#define MDM9625_SPK_ON 1
+
+/* MDM9625 run Taiko at 12.288 Mhz.
+ * At present MDM supports 12.288mhz
+ * only. Taiko supports 9.6 MHz also.
+ */
+#define MDM_MCLK_CLK_12P288MHZ 12288000
+#define MDM_MCLK_CLK_9P6HZ 9600000
+#define MDM_IBIT_CLK_DIV_1P56MHZ 7
+
+/* Machine driver Name*/
+#define MDM9625_MACHINE_DRV_NAME "mdm9625-asoc-taiko"
+
+struct mdm9625_machine_data {
+ u32 mclk_freq;
+};
+
+/* MI2S clock */
+struct mdm_mi2s_clk {
+ struct clk *cdc_cr_clk;
+ struct clk *cdc_osr_clk;
+ struct clk *cdc_bit_clk;
+ bool clk_enable;
+
+};
+static struct mdm_mi2s_clk prim_clk;
+
+/* I2S GPIO */
+struct request_gpio {
+ unsigned gpio_no;
+ char *gpio_name;
+};
+static bool cdc_mclk_init;
+static struct mutex cdc_mclk_mutex;
+static int mdm9625_mi2s_rx_ch = 1;
+static int mdm9625_mi2s_tx_ch = 1;
+static int msm_spk_control;
+static atomic_t mi2s_ref_count;
+
+/* MI2S GPIO CONFIG */
+static struct request_gpio mi2s_gpio[] = {
+ {
+ .gpio_no = GPIO_MI2S_WS,
+ .gpio_name = "MI2S_WS",
+ },
+ {
+ .gpio_no = GPIO_MI2S_SCLK,
+ .gpio_name = "MI2S_SCLK",
+ },
+ {
+ .gpio_no = GPIO_MI2S_DOUT,
+ .gpio_name = "MI2S_DOUT",
+ },
+ {
+ .gpio_no = GPIO_MI2S_DIN,
+ .gpio_name = "MI2S_DIN",
+ },
+ {
+ .gpio_no = GPIO_MI2S_MCLK,
+ .gpio_name = "MI2S_MCLK",
+ },
+};
+
+static int mdm9625_enable_codec_ext_clk(struct snd_soc_codec *codec,
+ int enable, bool dapm);
+
+void *def_taiko_mbhc_cal(void);
+
+static struct wcd9xxx_mbhc_config mbhc_cfg = {
+ .read_fw_bin = false,
+ .calibration = NULL,
+ .micbias = MBHC_MICBIAS2,
+ .mclk_cb_fn = mdm9625_enable_codec_ext_clk,
+ .mclk_rate = MDM_MCLK_CLK_12P288MHZ,
+ .gpio = 0,
+ .gpio_irq = 0,
+ .gpio_level_insert = 1,
+ .detect_extn_cable = true,
+ .insert_detect = true,
+ .swap_gnd_mic = NULL,
+};
+
+#define WCD9XXX_MBHC_DEF_BUTTONS 8
+#define WCD9XXX_MBHC_DEF_RLOADS 5
+
+
+static bool gpio_enable;
+
+static int mdm9625_set_mi2s_gpio(void)
+{
+ int rtn = 0;
+ int i;
+ int j;
+
+ if (gpio_enable == false) {
+ for (i = 0; i < ARRAY_SIZE(mi2s_gpio); i++) {
+ rtn = gpio_request(mi2s_gpio[i].gpio_no,
+ mi2s_gpio[i].gpio_name);
+ pr_debug("%s: gpio = %d, gpio name = %s\n"
+ "rtn = %d\n", __func__,
+ mi2s_gpio[i].gpio_no,
+ mi2s_gpio[i].gpio_name,
+ rtn);
+ if (rtn) {
+ pr_err("%s: Failed to request gpio %d\n",
+ __func__, mi2s_gpio[i].gpio_no);
+ /* Release all the GPIO on failure */
+ for (j = i; j >= 0; j--)
+ gpio_free(mi2s_gpio[j].gpio_no);
+ goto err;
+ }
+ }
+ gpio_enable = true;
+ }
+err:
+ return rtn;
+}
+
+static int mdm9625_mi2s_free_gpios(void)
+{
+ int i;
+ pr_debug("%s:", __func__);
+ for (i = 0; i < ARRAY_SIZE(mi2s_gpio); i++)
+ gpio_free(mi2s_gpio[i].gpio_no);
+ gpio_enable = false;
+ return 0;
+}
+static int mdm9625_mi2s_clk_ctl(struct snd_soc_pcm_runtime *rtd, bool enable)
+{
+ struct mdm_mi2s_clk *clk = &prim_clk;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_card *card = rtd->card;
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+ int ret = 0;
+
+ if (pdata == NULL) {
+ pr_err("%s:platform data is null\n", __func__);
+ return -ENODEV;
+ }
+
+ if (enable) {
+ if (clk->clk_enable == true) {
+ pr_info("%s:Device clock already enabled\n", __func__);
+ return 0;
+ }
+ /* Set up core clock. */
+ clk->cdc_cr_clk = clk_get(cpu_dai->dev, "core_clk");
+ if (IS_ERR(clk->cdc_cr_clk)) {
+ pr_err("%s: Failed to Core clk %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_cr_clk),
+ cpu_dai->dev->driver->name);
+ return -ENODEV ;
+ }
+ /* osr clock */
+ clk->cdc_osr_clk = clk_get(cpu_dai->dev, "osr_clk");
+ if (IS_ERR(clk->cdc_osr_clk)) {
+ pr_err("%s: Failed to request OSR %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_osr_clk),
+ cpu_dai->dev->driver->name);
+ clk_put(clk->cdc_cr_clk);
+ return -ENODEV ;
+ }
+ /* ibit clock */
+ clk->cdc_bit_clk = clk_get(cpu_dai->dev, "ibit_clk");
+ if (IS_ERR(clk->cdc_bit_clk)) {
+ pr_err("%s: Failed to request Bit %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_bit_clk),
+ cpu_dai->dev->driver->name);
+ clk_put(clk->cdc_cr_clk);
+ clk_put(clk->cdc_osr_clk);
+ return -ENODEV ;
+ }
+ /* Set rate core and ibit clock */
+ clk_set_rate(clk->cdc_cr_clk, pdata->mclk_freq);
+ clk_set_rate(clk->cdc_bit_clk, MDM_IBIT_CLK_DIV_1P56MHZ);
+
+ /* Enable clocks. core clock need not be enabled.
+ * Enabling branch clocks indirectly enables
+ * core clock.
+ */
+ ret = clk_prepare_enable(clk->cdc_osr_clk);
+ if (ret != 0) {
+ pr_err("Fail to enable cdc_osr_clk\n");
+ goto exit_osrclk_err;
+ }
+ ret = clk_prepare_enable(clk->cdc_bit_clk);
+ if (ret != 0) {
+ pr_err("Fail to enable cdc_bit_clk\n");
+ goto exit_bclk_err;
+ }
+ clk->clk_enable = true;
+ return ret;
+ } else {
+ clk->clk_enable = false;
+ ret = 0;
+ goto exit_bclk_err;
+ }
+exit_bclk_err:
+ clk_disable_unprepare(clk->cdc_bit_clk);
+ clk_put(clk->cdc_bit_clk);
+exit_osrclk_err:
+ clk_disable_unprepare(clk->cdc_osr_clk);
+ clk_put(clk->cdc_osr_clk);
+ clk_put(clk->cdc_cr_clk);
+ clk->cdc_cr_clk = NULL;
+ clk->cdc_bit_clk = NULL;
+ clk->cdc_osr_clk = NULL;
+ clk->clk_enable = false;
+ return ret;
+}
+
+static void mdm9625_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ int ret;
+ if (atomic_dec_return(&mi2s_ref_count) == 0) {
+ mdm9625_mi2s_free_gpios();
+ ret = mdm9625_mi2s_clk_ctl(rtd, false);
+ if (ret < 0)
+ pr_err("%s:clock disable failed\n", __func__);
+ }
+}
+
+static int mdm9625_mi2s_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ int ret = 0;
+
+ if (atomic_inc_return(&mi2s_ref_count) == 1) {
+ mdm9625_set_mi2s_gpio();
+ ret = mdm9625_mi2s_clk_ctl(rtd, true);
+ if (ret < 0) {
+ pr_err("set format for codec dai failed\n");
+ return ret;
+ }
+ }
+ /* This sets the CONFIG PARAMETER WS_SRC.
+ * 1 means internal clock master mode.
+ * 0 means external clock slave mode.
+ */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ pr_err("set fmt cpu dai failed\n");
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ pr_err("set fmt for codec dai failed\n");
+
+ return ret;
+}
+
+static int set_codec_mclk(struct snd_soc_pcm_runtime *rtd)
+{
+ int ret = 0;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct snd_soc_card *card = rtd->card;
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+
+ if (cdc_mclk_init == true)
+ return 0;
+ ret = snd_soc_dai_set_sysclk(codec_dai, TAIKO_MCLK_ID, pdata->mclk_freq,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ pr_err("%s: Set codec sys clk failed %x", __func__, ret);
+ return ret;
+ }
+ cdc_mclk_init = true;
+ return 0;
+}
+
+static int mdm9625_mi2s_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+ rate->min = rate->max = 48000;
+ channels->min = channels->max = mdm9625_mi2s_rx_ch;
+ set_codec_mclk(rtd);
+ return 0;
+}
+
+static int mdm9625_mi2s_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+ rate->min = rate->max = 48000;
+ channels->min = channels->max = mdm9625_mi2s_tx_ch;
+ set_codec_mclk(rtd);
+ return 0;
+}
+
+
+static int mdm9625_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm9615_i2s_rx_ch = %d\n", __func__,
+ mdm9625_mi2s_rx_ch);
+ ucontrol->value.integer.value[0] = mdm9625_mi2s_rx_ch - 1;
+ return 0;
+}
+
+static int mdm9625_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ mdm9625_mi2s_rx_ch = ucontrol->value.integer.value[0] + 1;
+ pr_debug("%s: msm9615_i2s_rx_ch = %d\n", __func__,
+ mdm9625_mi2s_rx_ch);
+ return 1;
+}
+
+static int mdm9625_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm9615_i2s_tx_ch = %d\n", __func__,
+ mdm9625_mi2s_tx_ch);
+ ucontrol->value.integer.value[0] = mdm9625_mi2s_tx_ch - 1;
+ return 0;
+}
+
+static int mdm9625_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ mdm9625_mi2s_tx_ch = ucontrol->value.integer.value[0] + 1;
+ pr_debug("%s: msm9615_i2s_tx_ch = %d\n", __func__,
+ mdm9625_mi2s_tx_ch);
+ return 1;
+}
+
+
+static int mdm9625_mi2s_get_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm_spk_control = %d", __func__, msm_spk_control);
+ ucontrol->value.integer.value[0] = msm_spk_control;
+ return 0;
+}
+
+static void mdm_ext_control(struct snd_soc_codec *codec)
+{
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ pr_debug("%s: msm_spk_control = %d", __func__, msm_spk_control);
+ mutex_lock(&dapm->codec->mutex);
+ if (msm_spk_control == MDM9625_SPK_ON) {
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
+ } else {
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Neg");
+ }
+ snd_soc_dapm_sync(dapm);
+ mutex_unlock(&dapm->codec->mutex);
+}
+
+static int mdm9625_mi2s_set_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ pr_debug("%s()\n", __func__);
+ if (msm_spk_control == ucontrol->value.integer.value[0])
+ return 0;
+ msm_spk_control = ucontrol->value.integer.value[0];
+ mdm_ext_control(codec);
+ return 1;
+}
+
+static int mdm9625_enable_codec_ext_clk(struct snd_soc_codec *codec,
+ int enable, bool dapm)
+{
+ int ret = 0;
+ pr_debug("%s: enable = %d codec name %s\n", __func__,
+ enable, codec->name);
+ mutex_lock(&cdc_mclk_mutex);
+ if (enable)
+ taiko_mclk_enable(codec, 1, dapm);
+ else
+ taiko_mclk_enable(codec, 0, dapm);
+ mutex_unlock(&cdc_mclk_mutex);
+ return ret;
+}
+
+static int mdm9625_mclk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ pr_debug("%s: event = %d\n", __func__, event);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return mdm9625_enable_codec_ext_clk(w->codec, 1, true);
+ case SND_SOC_DAPM_POST_PMD:
+ return mdm9625_enable_codec_ext_clk(w->codec, 0, true);
+ }
+ return 0;
+}
+
+
+static const struct snd_soc_dapm_widget mdm9625_dapm_widgets[] = {
+
+ SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
+ mdm9625_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SPK("Ext Spk Bottom Pos", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Bottom Neg", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Top Pos", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Top Neg", NULL),
+ SND_SOC_DAPM_MIC("Handset Mic", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic1", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic2", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic3", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic4", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic5", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic6", NULL),
+};
+
+static const char *const spk_function[] = {"Off", "On"};
+static const char *const mi2s_rx_ch_text[] = {"One", "Two"};
+static const char *const mi2s_tx_ch_text[] = {"One", "Two"};
+
+static const struct soc_enum mdm9625_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, spk_function),
+ SOC_ENUM_SINGLE_EXT(2, mi2s_rx_ch_text),
+ SOC_ENUM_SINGLE_EXT(2, mi2s_tx_ch_text),
+};
+
+static const struct snd_kcontrol_new mdm_snd_controls[] = {
+ SOC_ENUM_EXT("Speaker Function", mdm9625_enum[0],
+ mdm9625_mi2s_get_spk,
+ mdm9625_mi2s_set_spk),
+ SOC_ENUM_EXT("MI2S_RX Channels", mdm9625_enum[1],
+ mdm9625_mi2s_rx_ch_get,
+ mdm9625_mi2s_rx_ch_put),
+ SOC_ENUM_EXT("MI2S_TX Channels", mdm9625_enum[2],
+ mdm9625_mi2s_tx_ch_get,
+ mdm9625_mi2s_tx_ch_put),
+};
+
+static int mdm9625_mi2s_audrx_init(struct snd_soc_pcm_runtime *rtd)
+{
+ int err;
+ struct snd_soc_codec *codec = rtd->codec;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ pr_info("%s(), dev_name%s\n", __func__, dev_name(cpu_dai->dev));
+
+ rtd->pmdown_time = 0;
+ err = snd_soc_add_codec_controls(codec, mdm_snd_controls,
+ ARRAY_SIZE(mdm_snd_controls));
+ if (err < 0)
+ return err;
+
+ snd_soc_dapm_new_controls(dapm, mdm9625_dapm_widgets,
+ ARRAY_SIZE(mdm9625_dapm_widgets));
+
+ /* After DAPM Enable pins alawys
+ * DAPM SYNC needs to be called.
+ */
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
+ snd_soc_dapm_sync(dapm);
+
+ /* start mbhc */
+ mdm9625_set_mi2s_gpio();
+ mdm9625_mi2s_clk_ctl(rtd, true);
+ mbhc_cfg.calibration = def_taiko_mbhc_cal();
+ if (mbhc_cfg.calibration)
+ err = taiko_hs_detect(codec, &mbhc_cfg);
+ else
+ err = -ENOMEM;
+ return err;
+}
+
+void *def_taiko_mbhc_cal(void)
+{
+ void *taiko_cal;
+ struct wcd9xxx_mbhc_btn_detect_cfg *btn_cfg;
+ u16 *btn_low, *btn_high;
+ u8 *n_ready, *n_cic, *gain;
+
+ taiko_cal = kzalloc(WCD9XXX_MBHC_CAL_SIZE(WCD9XXX_MBHC_DEF_BUTTONS,
+ WCD9XXX_MBHC_DEF_RLOADS),
+ GFP_KERNEL);
+ if (!taiko_cal) {
+ pr_err("%s: out of memory\n", __func__);
+ return NULL;
+ }
+
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_GENERAL_PTR(taiko_cal)->X) = (Y))
+ S(t_ldoh, 100);
+ S(t_bg_fast_settle, 100);
+ S(t_shutdown_plug_rem, 255);
+ S(mbhc_nsa, 4);
+ S(mbhc_navg, 4);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_PLUG_DET_PTR(taiko_cal)->X) = (Y))
+ S(mic_current, TAIKO_PID_MIC_5_UA);
+ S(hph_current, TAIKO_PID_MIC_5_UA);
+ S(t_mic_pid, 100);
+ S(t_ins_complete, 250);
+ S(t_ins_retry, 200);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_PLUG_TYPE_PTR(taiko_cal)->X) = (Y))
+ S(v_no_mic, 30);
+ S(v_hs_max, 2400);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_BTN_DET_PTR(taiko_cal)->X) = (Y))
+ S(c[0], 62);
+ S(c[1], 124);
+ S(nc, 1);
+ S(n_meas, 3);
+ S(mbhc_nsc, 11);
+ S(n_btn_meas, 1);
+ S(n_btn_con, 2);
+ S(num_btn, WCD9XXX_MBHC_DEF_BUTTONS);
+ S(v_btn_press_delta_sta, 100);
+ S(v_btn_press_delta_cic, 50);
+#undef S
+ btn_cfg = WCD9XXX_MBHC_CAL_BTN_DET_PTR(taiko_cal);
+ btn_low = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_V_BTN_LOW);
+ btn_high = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg,
+ MBHC_BTN_DET_V_BTN_HIGH);
+ btn_low[0] = -50;
+ btn_high[0] = 10;
+ btn_low[1] = 11;
+ btn_high[1] = 52;
+ btn_low[2] = 53;
+ btn_high[2] = 94;
+ btn_low[3] = 95;
+ btn_high[3] = 133;
+ btn_low[4] = 134;
+ btn_high[4] = 171;
+ btn_low[5] = 172;
+ btn_high[5] = 208;
+ btn_low[6] = 209;
+ btn_high[6] = 244;
+ btn_low[7] = 245;
+ btn_high[7] = 330;
+ n_ready = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_N_READY);
+ n_ready[0] = 80;
+ n_ready[1] = 68;
+ n_cic = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_N_CIC);
+ n_cic[0] = 60;
+ n_cic[1] = 47;
+ gain = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_GAIN);
+ gain[0] = 11;
+ gain[1] = 9;
+
+ return taiko_cal;
+}
+
+
+static struct snd_soc_ops mdm9625_mi2s_be_ops = {
+ .startup = mdm9625_mi2s_startup,
+ .shutdown = mdm9625_mi2s_snd_shutdown,
+};
+
+/* Digital audio interface connects codec <---> CPU */
+static struct snd_soc_dai_link mdm9625_dai[] = {
+ /* FrontEnd DAI Links */
+ {
+ .name = "MDM9625 Media1",
+ .stream_name = "MultiMedia1",
+ .cpu_dai_name = "MultiMedia1",
+ .platform_name = "msm-pcm-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ /* This dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1
+ },
+ {
+ .name = "MSM VoIP",
+ .stream_name = "VoIP",
+ .cpu_dai_name = "VoIP",
+ .platform_name = "msm-voip-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ /* This dainlink has VOIP support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_VOIP,
+ },
+ {
+ .name = "Circuit-Switch Voice",
+ .stream_name = "CS-Voice",
+ .cpu_dai_name = "CS-VOICE",
+ .platform_name = "msm-pcm-voice",
+ .dynamic = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ /* This dainlink has Voice support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_CS_VOICE,
+ },
+ {
+ .name = "MI2S Hostless",
+ .stream_name = "MI2S Hostless",
+ .cpu_dai_name = "MI2S_TX_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,
+ /* This dainlink has MI2S support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ /* Backend DAI Links */
+ {
+ .name = LPASS_BE_MI2S_RX,
+ .stream_name = "MI2S Playback",
+ .cpu_dai_name = "msm-dai-q6-mi2s.0",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_i2s_rx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_MI2S_RX,
+ .init = &mdm9625_mi2s_audrx_init,
+ .be_hw_params_fixup = &mdm9625_mi2s_rx_be_hw_params_fixup,
+ .ops = &mdm9625_mi2s_be_ops,
+ },
+ {
+ .name = LPASS_BE_MI2S_TX,
+ .stream_name = "MI2S Capture",
+ .cpu_dai_name = "msm-dai-q6-mi2s.0",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_i2s_tx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_MI2S_TX,
+ .be_hw_params_fixup = &mdm9625_mi2s_tx_be_hw_params_fixup,
+ .ops = &mdm9625_mi2s_be_ops,
+ },
+};
+
+static struct snd_soc_card snd_soc_card_mdm9625 = {
+ .name = "mdm9625-taiko-i2s-snd-card",
+ .dai_link = mdm9625_dai,
+ .num_links = ARRAY_SIZE(mdm9625_dai),
+};
+
+static __devinit int mdm9625_asoc_machine_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct snd_soc_card *card = &snd_soc_card_mdm9625;
+ struct mdm9625_machine_data *pdata;
+
+ mutex_init(&cdc_mclk_mutex);
+ gpio_enable = false;
+ cdc_mclk_init = false;
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "No platform supplied from device tree\n");
+ return -EINVAL;
+ }
+ pdata = devm_kzalloc(&pdev->dev, sizeof(struct mdm9625_machine_data),
+ GFP_KERNEL);
+ if (!pdata) {
+ dev_err(&pdev->dev, "Can't allocate msm8974_asoc_mach_data\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+ card->dev = &pdev->dev;
+ platform_set_drvdata(pdev, card);
+ snd_soc_card_set_drvdata(card, pdata);
+ ret = snd_soc_of_parse_card_name(card, "qcom,model");
+ if (ret)
+ goto err;
+ ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
+ if (ret)
+ goto err;
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "qcom,taiko-mclk-clk-freq",
+ &pdata->mclk_freq);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Looking up %s property in node %s failed",
+ "qcom,taiko-mclk-clk-freq",
+ pdev->dev.of_node->full_name);
+ goto err;
+ }
+ /* At present only 12.288MHz is supported on MDM. */
+ if (pdata->mclk_freq != MDM_MCLK_CLK_12P288MHZ) {
+ dev_err(&pdev->dev, "unsupported taiko mclk freq %u\n",
+ pdata->mclk_freq);
+ ret = -EINVAL;
+ goto err;
+ }
+ ret = snd_soc_register_card(card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+ ret);
+ goto err;
+ }
+ return 0;
+err:
+ devm_kfree(&pdev->dev, pdata);
+ return ret;
+}
+
+static int __devexit mdm9625_asoc_machine_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+ pdata->mclk_freq = 0;
+ snd_soc_unregister_card(card);
+ return 0;
+}
+
+static const struct of_device_id msm9625_asoc_machine_of_match[] = {
+ { .compatible = "qcom,mdm9625-audio-taiko", },
+ {},
+};
+
+static struct platform_driver msm9625_asoc_machine_driver = {
+ .driver = {
+ .name = MDM9625_MACHINE_DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = msm9625_asoc_machine_of_match,
+ },
+ .probe = mdm9625_asoc_machine_probe,
+ .remove = __devexit_p(mdm9625_asoc_machine_remove),
+};
+
+
+module_platform_driver(msm9625_asoc_machine_driver);
+
+MODULE_DESCRIPTION("ALSA SoC msm");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" MDM9625_MACHINE_DRV_NAME);
+MODULE_DEVICE_TABLE(of, msm9625_asoc_machine_of_match);
+
diff --git a/sound/soc/msm/mpq8064.c b/sound/soc/msm/mpq8064.c
index 016ef94..90c96b4 100644
--- a/sound/soc/msm/mpq8064.c
+++ b/sound/soc/msm/mpq8064.c
@@ -1486,6 +1486,20 @@
.ignore_pmdown_time = 1, /* dainlink has playback support */
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
+
+ },
+ {
+ .name = "MSM8960 Pseudo",
+ .stream_name = "Pseudo",
+ .cpu_dai_name = "Pseudo",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_PSEUDO,
},
/* Backend DAI Links */
{
@@ -1624,6 +1638,18 @@
.be_id = MSM_BACKEND_DAI_AUXPCM_TX,
.be_hw_params_fixup = mpq8064_auxpcm_be_params_fixup,
},
+ {
+ .name = LPASS_BE_PSEUDO,
+ .stream_name = "PSEUDO Playback",
+ .cpu_dai_name = "msm-dai-q6.32769",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "snd-soc-dummy",
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_PSEUDO_PORT,
+ .be_hw_params_fixup = msm_be_hw_params_fixup,
+ .ignore_pmdown_time = 1,
+ },
};
diff --git a/sound/soc/msm/msm-compr-q6.c b/sound/soc/msm/msm-compr-q6.c
index eeabb78..6ac4562 100644
--- a/sound/soc/msm/msm-compr-q6.c
+++ b/sound/soc/msm/msm-compr-q6.c
@@ -143,6 +143,10 @@
atomic_set(&prtd->pending_buffer, 0);
if (runtime->status->hw_ptr >= runtime->control->appl_ptr) {
runtime->render_flag |= SNDRV_RENDER_STOPPED;
+ atomic_set(&prtd->pending_buffer, 1);
+ pr_debug("%s:compr driver underrun hw_ptr = %ld appl_ptr = %ld\n",
+ __func__, runtime->status->hw_ptr,
+ runtime->control->appl_ptr);
break;
}
buf = prtd->audio_client->port[IN].buf;
@@ -474,7 +478,23 @@
default:
return -EINVAL;
}
-
+ if (compr->info.codec_param.codec.transcode_dts) {
+ msm_pcm_routing_reg_pseudo_stream(
+ MSM_FRONTEND_DAI_PSEUDO,
+ prtd->enc_audio_client->perf_mode,
+ prtd->enc_audio_client->session,
+ SNDRV_PCM_STREAM_CAPTURE,
+ 48000, runtime->channels > 6 ?
+ 6 : runtime->channels);
+ pr_debug("%s: cmd: DTS ENCDEC CFG BLK\n", __func__);
+ ret = q6asm_enc_cfg_blk_dts(prtd->enc_audio_client,
+ DTS_ENC_SAMPLE_RATE48k,
+ runtime->channels > 6 ?
+ 6 : runtime->channels);
+ if (ret < 0)
+ pr_err("%s: CMD: DTS ENCDEC CFG BLK failed\n",
+ __func__);
+ }
prtd->enabled = 1;
prtd->cmd_ack = 0;
@@ -650,6 +670,8 @@
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pr_debug("%s: Trigger start\n", __func__);
q6asm_run_nowait(prtd->audio_client, 0, 0, 0);
+ if (prtd->enc_audio_client)
+ q6asm_run_nowait(prtd->enc_audio_client, 0, 0, 0);
atomic_set(&prtd->start, 1);
break;
case SNDRV_PCM_TRIGGER_STOP:
@@ -660,6 +682,8 @@
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pr_debug("SNDRV_PCM_TRIGGER_PAUSE\n");
q6asm_cmd_nowait(prtd->audio_client, CMD_PAUSE);
+ if (prtd->enc_audio_client)
+ q6asm_cmd_nowait(prtd->enc_audio_client, CMD_PAUSE);
atomic_set(&prtd->start, 0);
runtime->render_flag &= ~SNDRV_RENDER_STOPPED;
break;
@@ -811,6 +835,8 @@
atomic_set(&prtd->pending_buffer, 0);
prtd->pcm_irq_pos = 0;
q6asm_cmd(prtd->audio_client, CMD_CLOSE);
+ if (prtd->enc_audio_client)
+ q6asm_cmd(prtd->enc_audio_client, CMD_CLOSE);
compressed_audio.prtd = NULL;
q6asm_audio_client_buf_free_contiguous(dir,
prtd->audio_client);
@@ -827,6 +853,12 @@
soc_prtd->dai_link->be_id,
SNDRV_PCM_STREAM_PLAYBACK);
}
+ if (compr->info.codec_param.codec.transcode_dts) {
+ msm_pcm_routing_dereg_pseudo_stream(MSM_FRONTEND_DAI_PSEUDO,
+ prtd->enc_audio_client->session);
+ }
+ if (prtd->enc_audio_client)
+ q6asm_audio_client_free(prtd->enc_audio_client);
q6asm_audio_client_free(prtd->audio_client);
kfree(prtd);
return 0;
@@ -843,6 +875,7 @@
pr_debug("%s\n", __func__);
atomic_set(&prtd->pending_buffer, 0);
q6asm_cmd(prtd->audio_client, CMD_CLOSE);
+ compressed_audio.prtd = NULL;
q6asm_audio_client_buf_free_contiguous(dir,
prtd->audio_client);
if (compr->info.codec_param.codec.id ==
@@ -968,6 +1001,29 @@
prtd->session_id,
substream->stream);
+ if (compr->info.codec_param.codec.transcode_dts) {
+ prtd->enc_audio_client =
+ q6asm_audio_client_alloc(
+ (app_cb)compr_event_handler, compr);
+ if (!prtd->enc_audio_client) {
+ pr_err("%s: Could not allocate " \
+ "memory\n", __func__);
+ return -ENOMEM;
+ }
+ prtd->enc_audio_client->perf_mode = false;
+ pr_debug("%s Setting up loopback path\n",
+ __func__);
+ ret = q6asm_open_transcode_loopback(
+ prtd->enc_audio_client,
+ params_channels(params));
+ if (ret < 0) {
+ pr_err("%s: Session transcode " \
+ "loopback open failed\n",
+ __func__);
+ return -ENODEV;
+ }
+ }
+
break;
}
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
@@ -1117,6 +1173,22 @@
pr_err("%s: ERROR: copy from user\n", __func__);
return rc;
}
+ /*
+ * DTS Security needed for the transcode path
+ */
+ if (compr->info.codec_param.codec.transcode_dts) {
+ char modelId[128];
+ struct snd_dec_dts opt_dts =
+ compr->info.codec_param.codec.dts;
+ int modelIdLength = opt_dts.modelIdLength;
+ if (copy_from_user(modelId, (void *)opt_dts.modelId,
+ modelIdLength))
+ pr_err("%s: ERROR: copy modelId\n", __func__);
+ modelId[modelIdLength] = '\0';
+ pr_debug("%s: Received modelId =%s,length=%d\n",
+ __func__, modelId, modelIdLength);
+ core_set_dts_model_id(modelIdLength, modelId);
+ }
switch (compr->info.codec_param.codec.id) {
case SND_AUDIOCODEC_MP3:
/* For MP3 we dont need any other parameter */
@@ -1150,7 +1222,7 @@
case SND_AUDIOCODEC_DTS: {
char modelId[128];
struct snd_dec_dts opt_dts =
- compr->info.codec_param.codec.options.dts;
+ compr->info.codec_param.codec.dts;
int modelIdLength = opt_dts.modelIdLength;
pr_debug("SND_AUDIOCODEC_DTS\n");
if (copy_from_user(modelId, (void *)opt_dts.modelId,
@@ -1166,7 +1238,7 @@
case SND_AUDIOCODEC_DTS_LBR:{
char modelId[128];
struct snd_dec_dts opt_dts =
- compr->info.codec_param.codec.options.dts;
+ compr->info.codec_param.codec.dts;
int modelIdLength = opt_dts.modelIdLength;
pr_debug("SND_AUDIOCODEC_DTS_LBR\n");
if (copy_from_user(modelId, (void *)opt_dts.modelId,
diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c
index dc8d9e6..4165254 100644
--- a/sound/soc/msm/msm-dai-fe.c
+++ b/sound/soc/msm/msm-dai-fe.c
@@ -289,6 +289,78 @@
},
{
.playback = {
+ .stream_name = "SLIMBUS1 Hostless Playback",
+ .aif_name = "SLIM1_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .stream_name = "SLIMBUS1 Hostless Capture",
+ .aif_name = "SLIM1_UL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "SLIMBUS1_HOSTLESS",
+ },
+ {
+ .playback = {
+ .stream_name = "SLIMBUS3 Hostless Playback",
+ .aif_name = "SLIM3_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .stream_name = "SLIMBUS3 Hostless Capture",
+ .aif_name = "SLIM3_UL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "SLIMBUS3_HOSTLESS",
+ },
+ {
+ .playback = {
+ .stream_name = "SLIMBUS4 Hostless Playback",
+ .aif_name = "SLIM4_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .stream_name = "SLIMBUS4 Hostless Capture",
+ .aif_name = "SLIM4_UL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "SLIMBUS4_HOSTLESS",
+ },
+ {
+ .playback = {
.stream_name = "INT_FM Hostless Playback",
.aif_name = "INTFM_DL_HL",
.rates = SNDRV_PCM_RATE_8000_48000,
@@ -426,15 +498,25 @@
.name = "VoLTE",
},
{
+ .playback = {
+ .stream_name = "MI2S_RX_HOSTLESS Playback",
+ .aif_name = "MI2S_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
.capture = {
.stream_name = "MI2S_TX Hostless Capture",
.aif_name = "MI2S_UL_HL",
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 8,
- .rate_min = 8000,
- .rate_max = 48000,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
},
.ops = &msm_fe_dai_ops,
.name = "MI2S_TX_HOSTLESS",
@@ -477,6 +559,46 @@
.ops = &msm_fe_dai_ops,
.name = "SGLTE",
},
+ {
+ .playback = {
+ .stream_name = "Pseudo Playback",
+ .aif_name = "MM_DL9",
+ .rates = (SNDRV_PCM_RATE_8000_48000 |
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 8,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .stream_name = "Pseudo Capture",
+ .aif_name = "MM_UL9",
+ .rates = (SNDRV_PCM_RATE_8000_48000|
+ SNDRV_PCM_RATE_KNOT),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 8,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_Multimedia_dai_ops,
+ .name = "Pseudo",
+ },
+ {
+ .playback = {
+ .stream_name = "DTMF_RX Hostless Playback",
+ .aif_name = "DTMF_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "DTMF_RX_HOSTLESS",
+ },
};
static __devinit int msm_fe_dai_dev_probe(struct platform_device *pdev)
diff --git a/sound/soc/msm/msm-dai-q6.c b/sound/soc/msm/msm-dai-q6.c
index 18c2329..8cc0eaa 100644
--- a/sound/soc/msm/msm-dai-q6.c
+++ b/sound/soc/msm/msm-dai-q6.c
@@ -660,6 +660,24 @@
return 0;
}
+static int msm_dai_q6_pseudo_hw_params(struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_dai_data *dai_data = dev_get_drvdata(dai->dev);
+
+ dai_data->rate = params_rate(params);
+ dai_data->channels = params_channels(params) > 6 ?
+ params_channels(params) : 6;
+
+ dai_data->port_config.pseudo.bit_width = 16;
+ dai_data->port_config.pseudo.num_channels =
+ dai_data->channels;
+ dai_data->port_config.pseudo.data_format = 0;
+ dai_data->port_config.pseudo.timing_mode = 1;
+ dai_data->port_config.pseudo.reserved = 16;
+ return 0;
+}
+
/* Current implementation assumes hw_param is called once
* This may not be the case but what to do when ADM and AFE
* port are already opened and parameter changes
@@ -703,6 +721,9 @@
case RT_PROXY_DAI_002_RX:
rc = msm_dai_q6_afe_rtproxy_hw_params(params, dai);
break;
+ case PSEUDOPORT_01:
+ rc = msm_dai_q6_pseudo_hw_params(params, dai);
+ break;
case VOICE_PLAYBACK_TX:
case VOICE_RECORD_RX:
case VOICE_RECORD_TX:
@@ -1819,6 +1840,20 @@
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
};
+static struct snd_soc_dai_driver msm_dai_q6_pseudo_dai = {
+ .playback = {
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 6,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_dai_q6_ops,
+ .probe = msm_dai_q6_dai_probe,
+ .remove = msm_dai_q6_dai_remove,
+};
/* To do: change to register DAIs as batch */
static __devinit int msm_dai_q6_dev_probe(struct platform_device *pdev)
@@ -1915,6 +1950,10 @@
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_incall_record_dai);
break;
+ case PSEUDOPORT_01:
+ rc = snd_soc_register_dai(&pdev->dev,
+ &msm_dai_q6_pseudo_dai);
+ break;
default:
rc = -ENODEV;
break;
diff --git a/sound/soc/msm/msm-pcm-dtmf.c b/sound/soc/msm/msm-pcm-dtmf.c
new file mode 100644
index 0000000..94cc1ca
--- /dev/null
+++ b/sound/soc/msm/msm-pcm-dtmf.c
@@ -0,0 +1,585 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <sound/core.h>
+#include <sound/soc.h>
+#include <sound/pcm.h>
+#include <sound/q6afe.h>
+
+#include "msm-pcm-q6.h"
+#include "msm-pcm-routing.h"
+#include "qdsp6/q6voice.h"
+
+enum {
+ DTMF_IN_RX,
+ DTMF_IN_TX,
+};
+
+enum format {
+ FORMAT_S16_LE = 2
+};
+
+struct dtmf_det_info {
+ char session[MAX_SESSION_NAME_LEN];
+ uint8_t dir;
+ uint16_t high_freq;
+ uint16_t low_freq;
+};
+
+struct dtmf_buf_node {
+ struct list_head list;
+ struct dtmf_det_info dtmf_det_pkt;
+};
+
+enum dtmf_state {
+ DTMF_GEN_RX_STOPPED,
+ DTMF_GEN_RX_STARTED,
+};
+
+#define DTMF_MAX_Q_LEN 10
+#define DTMF_PKT_SIZE sizeof(struct dtmf_det_info)
+
+struct dtmf_drv_info {
+ enum dtmf_state state;
+ struct snd_pcm_substream *capture_substream;
+
+ struct list_head out_queue;
+ struct list_head free_out_queue;
+
+ wait_queue_head_t out_wait;
+
+ struct mutex lock;
+ spinlock_t dsp_lock;
+
+ uint8_t capture_start;
+ uint8_t capture_instance;
+
+ unsigned int pcm_capture_size;
+ unsigned int pcm_capture_count;
+ unsigned int pcm_capture_irq_pos;
+ unsigned int pcm_capture_buf_pos;
+};
+
+static struct snd_pcm_hardware msm_pcm_hardware = {
+ .info = (SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED),
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 1,
+ .buffer_bytes_max = (sizeof(struct dtmf_buf_node) * DTMF_MAX_Q_LEN),
+ .period_bytes_min = DTMF_PKT_SIZE,
+ .period_bytes_max = DTMF_PKT_SIZE,
+ .periods_min = DTMF_MAX_Q_LEN,
+ .periods_max = DTMF_MAX_Q_LEN,
+ .fifo_size = 0,
+};
+
+static int msm_dtmf_rx_generate_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ uint16_t low_freq = ucontrol->value.integer.value[0];
+ uint16_t high_freq = ucontrol->value.integer.value[1];
+ int64_t duration = ucontrol->value.integer.value[2];
+ uint16_t gain = ucontrol->value.integer.value[3];
+
+ pr_debug("%s: low_freq=%d high_freq=%d duration=%d gain=%d\n",
+ __func__, low_freq, high_freq, (int)duration, gain);
+ afe_dtmf_generate_rx(duration, high_freq, low_freq, gain);
+ return 0;
+}
+
+static int msm_dtmf_rx_generate_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s:\n", __func__);
+ ucontrol->value.integer.value[0] = 0;
+ return 0;
+}
+
+static int msm_dtmf_detect_voice_rx_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int enable = ucontrol->value.integer.value[0];
+
+ pr_debug("%s: enable=%d\n", __func__, enable);
+ voc_enable_dtmf_rx_detection(voc_get_session_id(VOICE_SESSION_NAME),
+ enable);
+
+ return 0;
+}
+
+static int msm_dtmf_detect_voice_rx_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = 0;
+ return 0;
+}
+
+static int msm_dtmf_detect_volte_rx_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int enable = ucontrol->value.integer.value[0];
+
+ pr_debug("%s: enable=%d\n", __func__, enable);
+ voc_enable_dtmf_rx_detection(voc_get_session_id(VOLTE_SESSION_NAME),
+ enable);
+
+ return 0;
+}
+
+static int msm_dtmf_detect_volte_rx_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = 0;
+ return 0;
+}
+
+static struct snd_kcontrol_new msm_dtmf_controls[] = {
+ SOC_SINGLE_MULTI_EXT("DTMF_Generate Rx Low High Duration Gain",
+ SND_SOC_NOPM, 0, 5000, 0, 4,
+ msm_dtmf_rx_generate_get,
+ msm_dtmf_rx_generate_put),
+ SOC_SINGLE_EXT("DTMF_Detect Rx Voice enable", SND_SOC_NOPM, 0, 1, 0,
+ msm_dtmf_detect_voice_rx_get,
+ msm_dtmf_detect_voice_rx_put),
+ SOC_SINGLE_EXT("DTMF_Detect Rx VoLTE enable", SND_SOC_NOPM, 0, 1, 0,
+ msm_dtmf_detect_volte_rx_get,
+ msm_dtmf_detect_volte_rx_put),
+};
+
+static int msm_pcm_dtmf_probe(struct snd_soc_platform *platform)
+{
+ snd_soc_add_platform_controls(platform, msm_dtmf_controls,
+ ARRAY_SIZE(msm_dtmf_controls));
+ return 0;
+}
+
+static void dtmf_rx_detected_cb(uint8_t *pkt,
+ char *session,
+ void *private_data)
+{
+ struct dtmf_buf_node *buf_node = NULL;
+ struct vss_istream_evt_rx_dtmf_detected *dtmf_det_pkt =
+ (struct vss_istream_evt_rx_dtmf_detected *)pkt;
+ struct dtmf_drv_info *prtd = private_data;
+ unsigned long dsp_flags;
+
+ pr_debug("%s\n", __func__);
+ if (prtd->capture_substream == NULL)
+ return;
+
+ /* Copy dtmf detected info into out_queue. */
+ spin_lock_irqsave(&prtd->dsp_lock, dsp_flags);
+ /* discarding dtmf detection info till start is received */
+ if (!list_empty(&prtd->free_out_queue) && prtd->capture_start) {
+ buf_node = list_first_entry(&prtd->free_out_queue,
+ struct dtmf_buf_node, list);
+ list_del(&buf_node->list);
+ buf_node->dtmf_det_pkt.high_freq = dtmf_det_pkt->high_freq;
+ buf_node->dtmf_det_pkt.low_freq = dtmf_det_pkt->low_freq;
+ if (session != NULL)
+ strlcpy(buf_node->dtmf_det_pkt.session,
+ session, MAX_SESSION_NAME_LEN);
+
+ buf_node->dtmf_det_pkt.dir = DTMF_IN_RX;
+ pr_debug("high =%d, low=%d session=%s\n",
+ buf_node->dtmf_det_pkt.high_freq,
+ buf_node->dtmf_det_pkt.low_freq,
+ buf_node->dtmf_det_pkt.session);
+ list_add_tail(&buf_node->list, &prtd->out_queue);
+ prtd->pcm_capture_irq_pos += prtd->pcm_capture_count;
+ spin_unlock_irqrestore(&prtd->dsp_lock, dsp_flags);
+ snd_pcm_period_elapsed(prtd->capture_substream);
+ } else {
+ spin_unlock_irqrestore(&prtd->dsp_lock, dsp_flags);
+ pr_err("DTMF detection pkt in Rx dropped, no free node available\n");
+ }
+
+ wake_up(&prtd->out_wait);
+}
+
+static int msm_pcm_capture_copy(struct snd_pcm_substream *substream,
+ int channel, snd_pcm_uframes_t hwoff,
+ void __user *buf, snd_pcm_uframes_t frames)
+{
+ int ret = 0;
+ int count = 0;
+ struct dtmf_buf_node *buf_node = NULL;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+ unsigned long dsp_flags;
+
+ count = frames_to_bytes(runtime, frames);
+
+ ret = wait_event_interruptible_timeout(prtd->out_wait,
+ (!list_empty(&prtd->out_queue)),
+ 1 * HZ);
+
+ if (ret > 0) {
+ if (count <= DTMF_PKT_SIZE) {
+ spin_lock_irqsave(&prtd->dsp_lock, dsp_flags);
+ buf_node = list_first_entry(&prtd->out_queue,
+ struct dtmf_buf_node, list);
+ list_del(&buf_node->list);
+ spin_unlock_irqrestore(&prtd->dsp_lock, dsp_flags);
+ ret = copy_to_user(buf,
+ &buf_node->dtmf_det_pkt,
+ count);
+ if (ret) {
+ pr_err("%s: Copy to user retuned %d\n",
+ __func__, ret);
+ ret = -EFAULT;
+ }
+ spin_lock_irqsave(&prtd->dsp_lock, dsp_flags);
+ list_add_tail(&buf_node->list,
+ &prtd->free_out_queue);
+ spin_unlock_irqrestore(&prtd->dsp_lock, dsp_flags);
+
+ } else {
+ pr_err("%s: Read count %d > DTMF_PKT_SIZE\n",
+ __func__, count);
+ ret = -ENOMEM;
+ }
+ } else if (ret == 0) {
+ pr_err("%s: No UL data available\n", __func__);
+ ret = -ETIMEDOUT;
+ } else {
+ pr_err("%s: Read was interrupted\n", __func__);
+ ret = -ERESTARTSYS;
+ }
+ return ret;
+}
+
+static int msm_pcm_copy(struct snd_pcm_substream *substream, int a,
+ snd_pcm_uframes_t hwoff, void __user *buf, snd_pcm_uframes_t frames)
+{
+ int ret = 0;
+ pr_debug("%s() DTMF\n", __func__);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ ret = msm_pcm_capture_copy(substream, a, hwoff, buf, frames);
+
+ return ret;
+}
+
+static int msm_pcm_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = NULL;
+ int ret = 0;
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ prtd = kzalloc(sizeof(struct dtmf_drv_info), GFP_KERNEL);
+
+ if (prtd == NULL) {
+ pr_err("Failed to allocate memory for msm_audio\n");
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ mutex_init(&prtd->lock);
+ spin_lock_init(&prtd->dsp_lock);
+ init_waitqueue_head(&prtd->out_wait);
+ INIT_LIST_HEAD(&prtd->out_queue);
+ INIT_LIST_HEAD(&prtd->free_out_queue);
+
+ runtime->hw = msm_pcm_hardware;
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0)
+ pr_info("snd_pcm_hw_constraint_integer failed\n");
+
+ prtd->capture_substream = substream;
+ prtd->capture_instance++;
+ runtime->private_data = prtd;
+ }
+
+done:
+ return ret;
+}
+
+static int msm_pcm_close(struct snd_pcm_substream *substream)
+{
+ int ret = 0;
+ struct list_head *ptr = NULL;
+ struct list_head *next = NULL;
+ struct dtmf_buf_node *buf_node = NULL;
+ struct snd_dma_buffer *c_dma_buf;
+ struct snd_pcm_substream *c_substream;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+ unsigned long dsp_flags;
+
+ pr_debug("%s() DTMF\n", __func__);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ mutex_lock(&prtd->lock);
+ wake_up(&prtd->out_wait);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ prtd->capture_instance--;
+
+ if (!prtd->capture_instance) {
+ if (prtd->state == DTMF_GEN_RX_STARTED) {
+ prtd->state = DTMF_GEN_RX_STOPPED;
+ voc_disable_dtmf_det_on_active_sessions();
+ voc_register_dtmf_rx_detection_cb(NULL, NULL);
+ }
+ /* release all buffer */
+ /* release out_queue and free_out_queue */
+ pr_debug("release all buffer\n");
+ c_substream = prtd->capture_substream;
+ if (c_substream == NULL) {
+ pr_debug("c_substream is NULL\n");
+ mutex_unlock(&prtd->lock);
+ return -EINVAL;
+ }
+
+ c_dma_buf = &c_substream->dma_buffer;
+ if (c_dma_buf == NULL) {
+ pr_debug("c_dma_buf is NULL.\n");
+ mutex_unlock(&prtd->lock);
+ return -EINVAL;
+ }
+
+ if (c_dma_buf->area != NULL) {
+ spin_lock_irqsave(&prtd->dsp_lock, dsp_flags);
+ list_for_each_safe(ptr, next,
+ &prtd->out_queue) {
+ buf_node = list_entry(ptr,
+ struct dtmf_buf_node, list);
+ list_del(&buf_node->list);
+ }
+
+ list_for_each_safe(ptr, next,
+ &prtd->free_out_queue) {
+ buf_node = list_entry(ptr,
+ struct dtmf_buf_node, list);
+ list_del(&buf_node->list);
+ }
+
+ spin_unlock_irqrestore(&prtd->dsp_lock,
+ dsp_flags);
+ dma_free_coherent(c_substream->pcm->card->dev,
+ runtime->hw.buffer_bytes_max,
+ c_dma_buf->area,
+ c_dma_buf->addr);
+ c_dma_buf->area = NULL;
+ }
+ }
+ prtd->capture_substream = NULL;
+ mutex_unlock(&prtd->lock);
+ }
+
+ return ret;
+}
+
+static int msm_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+ struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
+ struct dtmf_buf_node *buf_node = NULL;
+ int i = 0, offset = 0;
+ int ret = 0;
+
+ pr_debug("%s: DTMF\n", __func__);
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ mutex_lock(&prtd->lock);
+ dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
+ dma_buf->dev.dev = substream->pcm->card->dev;
+ dma_buf->private_data = NULL;
+
+ dma_buf->area = dma_alloc_coherent(substream->pcm->card->dev,
+ runtime->hw.buffer_bytes_max,
+ &dma_buf->addr, GFP_KERNEL);
+ if (!dma_buf->area) {
+ pr_err("%s:MSM DTMF dma_alloc failed\n", __func__);
+ mutex_unlock(&prtd->lock);
+ return -ENOMEM;
+ }
+
+ dma_buf->bytes = runtime->hw.buffer_bytes_max;
+ memset(dma_buf->area, 0, runtime->hw.buffer_bytes_max);
+
+ for (i = 0; i < DTMF_MAX_Q_LEN; i++) {
+ pr_debug("node =%d\n", i);
+ buf_node = (void *) dma_buf->area + offset;
+ list_add_tail(&buf_node->list,
+ &prtd->free_out_queue);
+ offset = offset + sizeof(struct dtmf_buf_node);
+ }
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+ mutex_unlock(&prtd->lock);
+ }
+
+ return ret;
+}
+
+static int msm_pcm_capture_prepare(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+
+ pr_debug("%s: DTMF\n", __func__);
+ prtd->pcm_capture_size = snd_pcm_lib_buffer_bytes(substream);
+ prtd->pcm_capture_count = snd_pcm_lib_period_bytes(substream);
+ prtd->pcm_capture_irq_pos = 0;
+ prtd->pcm_capture_buf_pos = 0;
+ return 0;
+}
+
+static int msm_pcm_prepare(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+
+ pr_debug("%s: DTMF\n", __func__);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ mutex_lock(&prtd->lock);
+
+ msm_pcm_capture_prepare(substream);
+
+ if (runtime->format != FORMAT_S16_LE) {
+ pr_err("format:%u doesnt match %d\n",
+ (uint32_t)runtime->format, FORMAT_S16_LE);
+ mutex_unlock(&prtd->lock);
+ return -EINVAL;
+ }
+
+ if (prtd->capture_instance &&
+ (prtd->state != DTMF_GEN_RX_STARTED)) {
+ voc_register_dtmf_rx_detection_cb(dtmf_rx_detected_cb,
+ prtd);
+ prtd->state = DTMF_GEN_RX_STARTED;
+ }
+ mutex_unlock(&prtd->lock);
+ }
+
+ return 0;
+}
+
+static int msm_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ int ret = 0;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ pr_debug("%s: Trigger start\n", __func__);
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ prtd->capture_start = 1;
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ pr_debug("SNDRV_PCM_TRIGGER_STOP\n");
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ prtd->capture_start = 0;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static snd_pcm_uframes_t msm_pcm_pointer(struct snd_pcm_substream *substream)
+{
+ snd_pcm_uframes_t ret = 0;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct dtmf_drv_info *prtd = runtime->private_data;
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ if (prtd->pcm_capture_irq_pos >= prtd->pcm_capture_size)
+ prtd->pcm_capture_irq_pos = 0;
+ ret = bytes_to_frames(runtime, (prtd->pcm_capture_irq_pos));
+ }
+
+ return ret;
+}
+
+static struct snd_pcm_ops msm_pcm_ops = {
+ .open = msm_pcm_open,
+ .copy = msm_pcm_copy,
+ .hw_params = msm_pcm_hw_params,
+ .close = msm_pcm_close,
+ .prepare = msm_pcm_prepare,
+ .trigger = msm_pcm_trigger,
+ .pointer = msm_pcm_pointer,
+};
+
+static int msm_asoc_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_card *card = rtd->card->snd_card;
+ int ret = 0;
+
+ if (!card->dev->coherent_dma_mask)
+ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+ return ret;
+}
+
+static struct snd_soc_platform_driver msm_soc_platform = {
+ .ops = &msm_pcm_ops,
+ .pcm_new = msm_asoc_pcm_new,
+ .probe = msm_pcm_dtmf_probe,
+};
+
+static __devinit int msm_pcm_probe(struct platform_device *pdev)
+{
+ return snd_soc_register_platform(&pdev->dev,
+ &msm_soc_platform);
+}
+
+static int msm_pcm_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_platform(&pdev->dev);
+ return 0;
+}
+
+static struct platform_driver msm_pcm_driver = {
+ .driver = {
+ .name = "msm-pcm-dtmf",
+ .owner = THIS_MODULE,
+ },
+ .probe = msm_pcm_probe,
+ .remove = __devexit_p(msm_pcm_remove),
+};
+
+static int __init msm_soc_platform_init(void)
+{
+ return platform_driver_register(&msm_pcm_driver);
+}
+module_init(msm_soc_platform_init);
+
+static void __exit msm_soc_platform_exit(void)
+{
+ platform_driver_unregister(&msm_pcm_driver);
+}
+module_exit(msm_soc_platform_exit);
+
+MODULE_DESCRIPTION("DTMF platform driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/msm/msm-pcm-q6.h b/sound/soc/msm/msm-pcm-q6.h
index 2678498..86e5c54 100644
--- a/sound/soc/msm/msm-pcm-q6.h
+++ b/sound/soc/msm/msm-pcm-q6.h
@@ -59,6 +59,7 @@
uint16_t source; /* Encoding source bit mask */
struct audio_client *audio_client;
+ struct audio_client *enc_audio_client;
uint16_t session_id;
diff --git a/sound/soc/msm/msm-pcm-routing.c b/sound/soc/msm/msm-pcm-routing.c
index 800bea8..23eee9d 100644
--- a/sound/soc/msm/msm-pcm-routing.c
+++ b/sound/soc/msm/msm-pcm-routing.c
@@ -194,6 +194,7 @@
{ SLIMBUS_EXTPROC_RX, 0, 0, 0, 0, 0},
{ SECONDARY_PCM_RX, 0, 0, 0, 0, 0},
{ SECONDARY_PCM_TX, 0, 0, 0, 0, 0},
+ { PSEUDOPORT_01, 0, 0, 0, 0, 0},
};
@@ -215,7 +216,8 @@
{INVALID_SESSION, INVALID_SESSION},
/* MULTIMEDIA8 */
{INVALID_SESSION, INVALID_SESSION},
-
+ /* PSEUDO */
+ {INVALID_SESSION, INVALID_SESSION},
};
static uint8_t is_be_dai_extproc(int be_dai)
@@ -298,6 +300,59 @@
mutex_unlock(&routing_lock);
}
+void msm_pcm_routing_reg_pseudo_stream(int fedai_id, bool perf_mode,
+ int dspst_id, int stream_type,
+ int sample_rate, int channels)
+{
+ int i, session_type, path_type, port_type, mode, ret;
+ struct route_payload payload;
+ pr_debug("%s:fedai_id = %d dspst_id = %d stream_type %d",
+ __func__, fedai_id, dspst_id, stream_type);
+
+ if (stream_type == SNDRV_PCM_STREAM_PLAYBACK) {
+ session_type = SESSION_TYPE_RX;
+ path_type = ADM_PATH_PLAYBACK;
+ port_type = MSM_AFE_PORT_TYPE_RX;
+ } else {
+ session_type = SESSION_TYPE_TX;
+ path_type = ADM_PATH_LIVE_REC;
+ port_type = MSM_AFE_PORT_TYPE_TX;
+ }
+
+ mutex_lock(&routing_lock);
+
+ payload.num_copps = 0;
+ adm_multi_ch_copp_pseudo_open_v3(PSEUDOPORT_01,
+ path_type, sample_rate, channels,
+ DEFAULT_COPP_TOPOLOGY);
+
+ payload.copp_ids[payload.num_copps++] = PSEUDOPORT_01;
+
+ for (i = 0; i < MSM_BACKEND_DAI_MAX; i++) {
+ if (test_bit(fedai_id, &msm_bedais[i].fe_sessions))
+ msm_bedais[i].perf_mode = perf_mode;
+ if (!is_be_dai_extproc(i) &&
+ (msm_bedais[i].active) &&
+ (test_bit(fedai_id, &msm_bedais[i].fe_sessions))) {
+
+ mode = afe_get_port_type(msm_bedais[i].port_id);
+ ret = adm_connect_afe_port_v2(mode, dspst_id,
+ msm_bedais[i].port_id,
+ msm_bedais[i].sample_rate,
+ msm_bedais[i].channel);
+
+ if (ret < 0)
+ pr_err("%s: adm_connect_afe_port_v2 failed\n",
+ __func__);
+ }
+ }
+ if (payload.num_copps)
+ adm_matrix_map(dspst_id, path_type,
+ payload.num_copps, payload.copp_ids, 0);
+
+ mutex_unlock(&routing_lock);
+}
+
void msm_pcm_routing_reg_phy_stream(int fedai_id, bool perf_mode, int dspst_id,
int stream_type)
{
@@ -375,6 +430,32 @@
mutex_unlock(&routing_lock);
}
+void msm_pcm_routing_dereg_pseudo_stream(int fedai_id, int dspst_id)
+{
+ int i, mode, ret;
+ pr_debug("%s:fedai_id = %d dspst_id = %d",
+ __func__, fedai_id, dspst_id);
+
+ mutex_lock(&routing_lock);
+
+ adm_pseudo_close(PSEUDOPORT_01);
+ for (i = 0; i < MSM_BACKEND_DAI_MAX; i++) {
+ if (!is_be_dai_extproc(i) &&
+ (msm_bedais[i].active) &&
+ (test_bit(fedai_id, &msm_bedais[i].fe_sessions))) {
+
+ mode = afe_get_port_type(msm_bedais[i].port_id);
+ ret = adm_disconnect_afe_port(mode, dspst_id,
+ msm_bedais[i].port_id);
+ if (ret < 0)
+ pr_err("%s: adm_connect_afe_port_v2 failed\n",
+ __func__);
+ }
+ }
+
+ mutex_unlock(&routing_lock);
+
+}
void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type)
{
int i, port_type, session_type;
@@ -574,6 +655,14 @@
else
clear_bit(val, &msm_bedais[reg].fe_sessions);
+ if (val == MSM_FRONTEND_DAI_DTMF_RX &&
+ afe_get_port_type(msm_bedais[reg].port_id) ==
+ MSM_AFE_PORT_TYPE_RX) {
+ pr_debug("%s(): set=%d port id=0x%x for dtmf generation\n",
+ __func__, set, msm_bedais[reg].port_id);
+ afe_set_dtmf_gen_rx_portid(msm_bedais[reg].port_id, set);
+ }
+
mutex_unlock(&routing_lock);
if (afe_get_port_type(msm_bedais[reg].port_id) ==
@@ -1210,6 +1299,9 @@
SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_I2S_RX,
MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("Pseudo", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_PSEUDO, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = {
@@ -1291,6 +1383,17 @@
SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_HDMI_RX,
MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,
msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("Pseudo", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_PSEUDO, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+};
+static const struct snd_kcontrol_new pseudo_mixer_controls[] = {
+ SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PSEUDO_PORT,
+ MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PSEUDO_PORT,
+ MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
};
/* incall music delivery mixer */
static const struct snd_kcontrol_new incall_music_delivery_mixer_controls[] = {
@@ -1493,6 +1596,9 @@
SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_PRI_I2S_RX,
MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer,
msm_routing_put_voice_stub_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_PRI_I2S_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new sec_i2s_rx_voice_mixer_controls[] = {
@@ -1508,6 +1614,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SEC_I2S_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SEC_I2S_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new slimbus_rx_voice_mixer_controls[] = {
@@ -1523,6 +1632,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SLIMBUS_0_RX ,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SLIMBUS_0_RX ,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new bt_sco_rx_voice_mixer_controls[] = {
@@ -1541,6 +1653,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_INT_BT_SCO_RX ,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_INT_BT_SCO_RX ,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new mi2s_rx_voice_mixer_controls[] = {
@@ -1556,6 +1671,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_MI2S_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new afe_pcm_rx_voice_mixer_controls[] = {
@@ -1574,6 +1692,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_AFE_PCM_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_AFE_PCM_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new aux_pcm_rx_voice_mixer_controls[] = {
@@ -1592,6 +1713,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_AUXPCM_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_AUXPCM_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new sec_aux_pcm_rx_voice_mixer_controls[] = {
@@ -1607,6 +1731,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_SEC_AUXPCM_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SEC_AUXPCM_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new hdmi_rx_voice_mixer_controls[] = {
@@ -1625,6 +1752,9 @@
SOC_SINGLE_EXT("SGLTE", MSM_BACKEND_DAI_HDMI_RX,
MSM_FRONTEND_DAI_SGLTE, 1, 0, msm_routing_get_voice_mixer,
msm_routing_put_voice_mixer),
+ SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_HDMI_RX,
+ MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer,
+ msm_routing_put_voice_mixer),
};
static const struct snd_kcontrol_new stub_rx_mixer_controls[] = {
@@ -2163,6 +2293,7 @@
SND_SOC_DAPM_AIF_IN("MM_DL6", "MultiMedia6 Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL7", "MultiMedia7 Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL8", "MultiMedia8 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("MM_DL9", "Pseudo Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("VOIP_DL", "VoIP Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, 0, 0, 0),
@@ -2192,6 +2323,8 @@
0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MI2S_UL_HL", "MI2S_TX_HOSTLESS Capture",
0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("DTMF_DL_HL", "DTMF_RX_HOSTLESS Playback",
+ 0, 0, 0, 0),
/* Backend AIF */
/* Stream name equals to backend dai link stream name
@@ -2201,6 +2334,7 @@
0, 0, 0 , 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_0_RX", "Slimbus Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("HDMI", "HDMI Playback", 0, 0, 0 , 0),
+ SND_SOC_DAPM_AIF_OUT("PSEUDO", "PSEUDO Playback", 0, 0, 0 , 0),
SND_SOC_DAPM_AIF_OUT("MI2S_RX", "MI2S Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("PRI_I2S_TX", "Primary I2S Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_I2S_TX", "Secondary I2S Capture", 0, 0, 0, 0),
@@ -2260,6 +2394,8 @@
slimbus_rx_mixer_controls, ARRAY_SIZE(slimbus_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("HDMI Mixer", SND_SOC_NOPM, 0, 0,
hdmi_mixer_controls, ARRAY_SIZE(hdmi_mixer_controls)),
+ SND_SOC_DAPM_MIXER("PSEUDO Mixer", SND_SOC_NOPM, 0, 0,
+ pseudo_mixer_controls, ARRAY_SIZE(pseudo_mixer_controls)),
SND_SOC_DAPM_MIXER("MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
mi2s_rx_mixer_controls, ARRAY_SIZE(mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0,
@@ -2398,6 +2534,7 @@
{"SEC_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
{"SEC_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
{"SEC_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
+ {"SEC_RX Audio Mixer", "Pseudo", "MM_DL9"},
{"SEC_I2S_RX", NULL, "SEC_RX Audio Mixer"},
{"SLIMBUS_0_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
@@ -2418,8 +2555,12 @@
{"HDMI Mixer", "MultiMedia6", "MM_DL6"},
{"HDMI Mixer", "MultiMedia7", "MM_DL7"},
{"HDMI Mixer", "MultiMedia8", "MM_DL8"},
+ {"HDMI Mixer", "Pseudo", "MM_DL9"},
{"HDMI", NULL, "HDMI Mixer"},
+ {"PSEUDO Mixer", "MultiMedia4", "MM_DL4"},
+ {"PSEUDO", NULL, "PSEUDO Mixer"},
+
/* incall */
{"Incall_Music Audio Mixer", "MultiMedia1", "MM_DL1"},
{"Incall_Music Audio Mixer", "MultiMedia2", "MM_DL2"},
@@ -2502,48 +2643,56 @@
{"PRI_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"PRI_RX_Voice Mixer", "Voip", "VOIP_DL"},
{"PRI_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"},
+ {"PRI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"PRI_I2S_RX", NULL, "PRI_RX_Voice Mixer"},
{"SEC_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SEC_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"SEC_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SEC_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"SEC_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"SEC_I2S_RX", NULL, "SEC_RX_Voice Mixer"},
{"SLIM_0_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SLIM_0_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"SLIM_0_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SLIM_0_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"SLIM_0_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"SLIMBUS_0_RX", NULL, "SLIM_0_RX_Voice Mixer"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"INTERNAL_BT_SCO_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX_Voice Mixer"},
{"AFE_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"AFE_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"AFE_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"AFE_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"AFE_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"PCM_RX", NULL, "AFE_PCM_RX_Voice Mixer"},
{"AUX_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"AUX_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"AUX_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"AUX_PCM_RX", NULL, "AUX_PCM_RX_Voice Mixer"},
{"SEC_AUX_PCM_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"SEC_AUX_PCM_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"SEC_AUX_PCM_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"SEC_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"SEC_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX_Voice Mixer"},
{"HDMI_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
{"HDMI_RX_Voice Mixer", "VoLTE", "VoLTE_DL"},
{"HDMI_RX_Voice Mixer", "SGLTE", "SGLTE_DL"},
{"HDMI_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"HDMI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"},
{"HDMI", NULL, "HDMI_RX_Voice Mixer"},
{"HDMI", NULL, "HDMI_DL_HL"},
@@ -2665,6 +2814,7 @@
{"BE_OUT", NULL, "SLIMBUS_3_RX"},
{"BE_OUT", NULL, "SLIMBUS_4_RX"},
{"BE_OUT", NULL, "HDMI"},
+ {"BE_OUT", NULL, "PSEUDO"},
{"BE_OUT", NULL, "MI2S_RX"},
{"PRI_I2S_TX", NULL, "BE_IN"},
{"SEC_I2S_TX", NULL, "BE_IN"},
@@ -2784,7 +2934,14 @@
for_each_set_bit(i, &bedai->fe_sessions, MSM_FRONTEND_DAI_MM_SIZE) {
if (fe_dai_map[i][session_type] != INVALID_SESSION) {
channels = bedai->channel;
- if ((playback || capture)
+ if (bedai->port_id == PSEUDOPORT_01) {
+ adm_multi_ch_copp_pseudo_open_v3(bedai->port_id,
+ path_type,
+ bedai->sample_rate,
+ channels > 6 ? 6 :
+ channels,
+ DEFAULT_COPP_TOPOLOGY);
+ } else if ((playback || capture)
&& ((channels == 2) || (channels == 1)) &&
bedai->perf_mode) {
adm_multi_ch_copp_open(bedai->port_id,
diff --git a/sound/soc/msm/msm-pcm-routing.h b/sound/soc/msm/msm-pcm-routing.h
index e11133e..0c0d3b4 100644
--- a/sound/soc/msm/msm-pcm-routing.h
+++ b/sound/soc/msm/msm-pcm-routing.h
@@ -18,6 +18,7 @@
#define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
#define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
#define LPASS_BE_HDMI "HDMI"
+#define LPASS_BE_PSEUDO "PSEUDO"
#define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
#define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
#define LPASS_BE_INT_FM_RX "INT_FM_RX"
@@ -61,6 +62,7 @@
MSM_FRONTEND_DAI_MULTIMEDIA6,
MSM_FRONTEND_DAI_MULTIMEDIA7,
MSM_FRONTEND_DAI_MULTIMEDIA8,
+ MSM_FRONTEND_DAI_PSEUDO,
MSM_FRONTEND_DAI_CS_VOICE,
MSM_FRONTEND_DAI_VOIP,
MSM_FRONTEND_DAI_AFE_RX,
@@ -68,11 +70,12 @@
MSM_FRONTEND_DAI_VOICE_STUB,
MSM_FRONTEND_DAI_VOLTE,
MSM_FRONTEND_DAI_SGLTE,
+ MSM_FRONTEND_DAI_DTMF_RX,
MSM_FRONTEND_DAI_MAX,
};
-#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA8 + 1)
-#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA8
+#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_PSEUDO + 1)
+#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_PSEUDO
enum {
MSM_BACKEND_DAI_PRI_I2S_RX = 0,
@@ -106,6 +109,7 @@
MSM_BACKEND_DAI_EXTPROC_EC_TX,
MSM_BACKEND_DAI_SEC_AUXPCM_RX,
MSM_BACKEND_DAI_SEC_AUXPCM_TX,
+ MSM_BACKEND_DAI_PSEUDO_PORT,
MSM_BACKEND_DAI_MAX,
};
@@ -118,6 +122,12 @@
void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
int stream_type, int enable);
+void msm_pcm_routing_reg_pseudo_stream(int fedai_id, bool perf_mode,
+ int dspst_id, int stream_type, int sample_rate,
+ int channels);
+
+void msm_pcm_routing_dereg_pseudo_stream(int fedai_id, int dspst_id);
+
void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
int lpa_set_volume(unsigned volume);
diff --git a/sound/soc/msm/msm-pcm-voip.c b/sound/soc/msm/msm-pcm-voip.c
index 359414b..4d2b253 100644
--- a/sound/soc/msm/msm-pcm-voip.c
+++ b/sound/soc/msm/msm-pcm-voip.c
@@ -43,6 +43,25 @@
#define MODE_AMR 0x5
#define MODE_AMR_WB 0xD
#define MODE_PCM 0xC
+#define MODE_G711 0xA
+#define MODE_G711A 0xF
+
+enum msm_audio_g711a_frame_type {
+ MVS_G711A_SPEECH_GOOD,
+ MVS_G711A_SID,
+ MVS_G711A_NO_DATA,
+ MVS_G711A_ERASURE
+};
+
+enum msm_audio_g711a_mode {
+ MVS_G711A_MODE_MULAW,
+ MVS_G711A_MODE_ALAW
+};
+
+enum msm_audio_g711_mode {
+ MVS_G711_MODE_MULAW,
+ MVS_G711_MODE_ALAW
+};
enum format {
FORMAT_S16_LE = 2,
@@ -135,7 +154,7 @@
unsigned int pcm_capture_buf_pos; /* position in buffer */
};
-static int voip_get_media_type(uint32_t mode,
+static int voip_get_media_type(uint32_t mode, uint32_t rate_type,
unsigned int samp_rate);
static int voip_get_rate_type(uint32_t mode,
uint32_t rate,
@@ -309,6 +328,79 @@
list_add_tail(&buf_node->list, &prtd->out_queue);
break;
}
+ case MODE_G711:
+ case MODE_G711A:{
+ /* G711 frames are 10ms each, but the DSP works with
+ * 20ms frames and sends two 10ms frames per buffer.
+ * Extract the two frames and put them in separate
+ * buffers.
+ */
+ /* Remove the first DSP frame info header.
+ * Header format: G711A
+ * Bits 0-1: Frame type
+ * Bits 2-3: Frame rate
+ *
+ * Header format: G711
+ * Bits 2-3: Frame rate
+ */
+ if (prtd->mode == MODE_G711A)
+ buf_node->frame.header.frame_type =
+ (*voc_pkt) & 0x03;
+ voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
+
+ /* There are two frames in the buffer. Length of the
+ * first frame:
+ */
+ buf_node->frame.len = (pkt_len -
+ 2 * DSP_FRAME_HDR_LEN) / 2;
+
+ memcpy(&buf_node->frame.voc_pkt[0],
+ voc_pkt,
+ buf_node->frame.len);
+ voc_pkt = voc_pkt + buf_node->frame.len;
+
+ list_add_tail(&buf_node->list, &prtd->out_queue);
+
+ /* Get another buffer from the free Q and fill in the
+ * second frame.
+ */
+ if (!list_empty(&prtd->free_out_queue)) {
+ buf_node =
+ list_first_entry(&prtd->free_out_queue,
+ struct voip_buf_node,
+ list);
+ list_del(&buf_node->list);
+
+ /* Remove the second DSP frame info header.
+ * Header format:
+ * Bits 0-1: Frame type
+ * Bits 2-3: Frame rate
+ */
+
+ if (prtd->mode == MODE_G711A)
+ buf_node->frame.header.frame_type =
+ (*voc_pkt) & 0x03;
+ voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
+
+ /* There are two frames in the buffer. Length
+ * of the second frame:
+ */
+ buf_node->frame.len = (pkt_len -
+ 2 * DSP_FRAME_HDR_LEN) / 2;
+
+ memcpy(&buf_node->frame.voc_pkt[0],
+ voc_pkt,
+ buf_node->frame.len);
+
+ list_add_tail(&buf_node->list,
+ &prtd->out_queue);
+ } else {
+ /* Drop the second frame */
+ pr_err("%s: UL data dropped, read is slow\n",
+ __func__);
+ }
+ break;
+ }
default: {
buf_node->frame.len = pkt_len;
memcpy(&buf_node->frame.voc_pkt[0],
@@ -383,6 +475,67 @@
list_add_tail(&buf_node->list, &prtd->free_in_queue);
break;
}
+ case MODE_G711:
+ case MODE_G711A:{
+ /* G711 frames are 10ms each but the DSP expects 20ms
+ * worth of data, so send two 10ms frames per buffer.
+ */
+ /* Add the first DSP frame info header. Header format:
+ * Bits 0-1: Frame type
+ * Bits 2-3: Frame rate
+ */
+
+ *voc_pkt = ((prtd->rate_type & 0x0F) << 2) |
+ (buf_node->frame.header.frame_type & 0x03);
+ voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
+
+ *pkt_len = buf_node->frame.len + DSP_FRAME_HDR_LEN;
+
+ memcpy(voc_pkt,
+ &buf_node->frame.voc_pkt[0],
+ buf_node->frame.len);
+ voc_pkt = voc_pkt + buf_node->frame.len;
+
+ list_add_tail(&buf_node->list, &prtd->free_in_queue);
+
+ if (!list_empty(&prtd->in_queue)) {
+ /* Get the second buffer. */
+ buf_node = list_first_entry(&prtd->in_queue,
+ struct voip_buf_node,
+ list);
+ list_del(&buf_node->list);
+
+ /* Add the second DSP frame info header.
+ * Header format:
+ * Bits 0-1: Frame type
+ * Bits 2-3: Frame rate
+ */
+ *voc_pkt = ((prtd->rate_type & 0x0F) << 2) |
+ (buf_node->frame.header.frame_type & 0x03);
+ voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN;
+
+ *pkt_len = *pkt_len +
+ buf_node->frame.len + DSP_FRAME_HDR_LEN;
+
+ memcpy(voc_pkt,
+ &buf_node->frame.voc_pkt[0],
+ buf_node->frame.len);
+
+ list_add_tail(&buf_node->list,
+ &prtd->free_in_queue);
+ } else {
+ /* Only 10ms worth of data is available, signal
+ * erasure frame.
+ */
+ *voc_pkt = ((prtd->rate_type & 0x0F) << 2) |
+ (MVS_G711A_ERASURE & 0x03);
+
+ *pkt_len = *pkt_len + DSP_FRAME_HDR_LEN;
+ pr_debug("%s, Only 10ms read, erase 2nd frame\n",
+ __func__);
+ }
+ break;
+ }
default: {
*pkt_len = buf_node->frame.len;
@@ -753,7 +906,8 @@
if ((runtime->format != FORMAT_SPECIAL) &&
((prtd->mode == MODE_AMR) || (prtd->mode == MODE_AMR_WB) ||
(prtd->mode == MODE_IS127) || (prtd->mode == MODE_4GV_NB) ||
- (prtd->mode == MODE_4GV_WB))) {
+ (prtd->mode == MODE_4GV_WB) || (prtd->mode == MODE_G711) ||
+ (prtd->mode == MODE_G711A))) {
pr_err("mode:%d and format:%u are not mached\n",
prtd->mode, (uint32_t)runtime->format);
ret = -EINVAL;
@@ -781,6 +935,7 @@
}
prtd->rate_type = rate_type;
media_type = voip_get_media_type(prtd->mode,
+ prtd->rate_type,
prtd->play_samp_rate);
if (media_type < 0) {
pr_err("fail at getting media_type\n");
@@ -1041,6 +1196,10 @@
}
break;
}
+ case MODE_G711:
+ case MODE_G711A:
+ *rate_type = rate;
+ break;
default:
pr_err("wrong mode type.\n");
ret = -EINVAL;
@@ -1050,7 +1209,7 @@
return ret;
}
-static int voip_get_media_type(uint32_t mode,
+static int voip_get_media_type(uint32_t mode, uint32_t rate_type,
unsigned int samp_rate)
{
uint32_t media_type;
@@ -1079,6 +1238,13 @@
case MODE_4GV_WB: /* EVRC-WB */
media_type = VSS_MEDIA_ID_4GV_WB_MODEM;
break;
+ case MODE_G711:
+ case MODE_G711A:
+ if (rate_type == MVS_G711A_MODE_MULAW)
+ media_type = VSS_MEDIA_ID_G711_MULAW;
+ else
+ media_type = VSS_MEDIA_ID_G711_ALAW;
+ break;
default:
pr_debug(" input mode is not supported\n");
media_type = -EINVAL;
diff --git a/sound/soc/msm/msm8930.c b/sound/soc/msm/msm8930.c
index b3db9e1..42699c9 100644
--- a/sound/soc/msm/msm8930.c
+++ b/sound/soc/msm/msm8930.c
@@ -183,9 +183,9 @@
pm8xxx_spk_enable(MSM8930_SPK_ON);
}
- pr_debug("%s: slepping 4 ms after turning on external "
+ pr_debug("%s: sleeping 10 ms after turning on external "
" Left Speaker Ampl\n", __func__);
- usleep_range(4000, 4000);
+ usleep_range(10000, 10000);
}
} else {
@@ -218,9 +218,9 @@
pm8xxx_spk_enable(MSM8930_SPK_OFF);
msm8930_ext_spk_pamp = 0;
- pr_debug("%s: slepping 4 ms after turning on external "
+ pr_debug("%s: slepping 10 ms after turning on external "
" Left Speaker Ampl\n", __func__);
- usleep_range(4000, 4000);
+ usleep_range(10000, 10000);
} else {
@@ -788,6 +788,18 @@
return 0;
}
+static int msm8930_proxy_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+
+ pr_debug("%s()\n", __func__);
+ rate->min = rate->max = 48000;
+
+ return 0;
+}
+
static int msm8930_aux_pcm_get_gpios(void)
{
int ret = 0;
@@ -1195,6 +1207,7 @@
.codec_dai_name = "msm-stub-rx",
.no_pcm = 1,
.be_id = MSM_BACKEND_DAI_AFE_PCM_RX,
+ .be_hw_params_fixup = msm8930_proxy_be_hw_params_fixup,
.ignore_pmdown_time = 1, /* this dainlink has playback support */
},
{
@@ -1206,6 +1219,7 @@
.codec_dai_name = "msm-stub-tx",
.no_pcm = 1,
.be_id = MSM_BACKEND_DAI_AFE_PCM_TX,
+ .be_hw_params_fixup = msm8930_proxy_be_hw_params_fixup,
},
/* AUX PCM Backend DAI Links */
{
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index e8ea058..58205e9 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -343,18 +343,20 @@
if (!codec_clk) {
dev_err(codec->dev, "%s: did not get Taiko MCLK\n",
__func__);
- return -EINVAL;
+ ret = -EINVAL;
+ goto exit;
}
clk_users++;
if (clk_users != 1)
- return ret;
+ goto exit;
ret = qpnp_clkdiv_enable(codec_clk);
if (ret) {
dev_err(codec->dev, "%s: Error enabling taiko MCLK\n",
__func__);
- return -ENODEV;
+ ret = -ENODEV;
+ goto exit;
}
taiko_mclk_enable(codec, 1, dapm);
} else {
@@ -367,8 +369,10 @@
} else {
pr_err("%s: Error releasing Tabla MCLK\n", __func__);
ret = -EINVAL;
+ goto exit;
}
}
+exit:
mutex_unlock(&cdc_mclk_mutex);
return ret;
}
@@ -811,8 +815,8 @@
btn_high = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg,
MBHC_BTN_DET_V_BTN_HIGH);
btn_low[0] = -50;
- btn_high[0] = 34;
- btn_low[1] = 35;
+ btn_high[0] = 10;
+ btn_low[1] = 11;
btn_high[1] = 52;
btn_low[2] = 53;
btn_high[2] = 94;
@@ -1070,6 +1074,48 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
},
+ {
+ .name = "SLIMBUS_1 Hostless",
+ .stream_name = "SLIMBUS_1 Hostless",
+ .cpu_dai_name = "SLIMBUS1_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* dai link has playback support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ {
+ .name = "SLIMBUS_3 Hostless",
+ .stream_name = "SLIMBUS_3 Hostless",
+ .cpu_dai_name = "SLIMBUS3_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* dai link has playback support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ {
+ .name = "SLIMBUS_4 Hostless",
+ .stream_name = "SLIMBUS_4 Hostless",
+ .cpu_dai_name = "SLIMBUS4_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1, /* dai link has playback support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
/* Backend BT/FM DAI Links */
{
.name = LPASS_BE_INT_BT_SCO_RX,
@@ -1226,6 +1272,84 @@
.be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup,
.ops = &msm8974_be_ops,
},
+ {
+ .name = LPASS_BE_SLIMBUS_1_RX,
+ .stream_name = "Slimbus1 Playback",
+ .cpu_dai_name = "msm-dai-q6-dev.16386",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_rx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
+ .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ /* dai link has playback support */
+ .ignore_pmdown_time = 1,
+ },
+ {
+ .name = LPASS_BE_SLIMBUS_1_TX,
+ .stream_name = "Slimbus1 Capture",
+ .cpu_dai_name = "msm-dai-q6-dev.16387",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_tx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
+ .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ },
+ {
+ .name = LPASS_BE_SLIMBUS_3_RX,
+ .stream_name = "Slimbus3 Playback",
+ .cpu_dai_name = "msm-dai-q6-dev.16390",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_rx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
+ .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ /* dai link has playback support */
+ .ignore_pmdown_time = 1,
+ },
+ {
+ .name = LPASS_BE_SLIMBUS_3_TX,
+ .stream_name = "Slimbus3 Capture",
+ .cpu_dai_name = "msm-dai-q6-dev.16391",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_tx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
+ .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ },
+ {
+ .name = LPASS_BE_SLIMBUS_4_RX,
+ .stream_name = "Slimbus4 Playback",
+ .cpu_dai_name = "msm-dai-q6-dev.16392",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_rx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
+ .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ /* dai link has playback support */
+ .ignore_pmdown_time = 1,
+ },
+ {
+ .name = LPASS_BE_SLIMBUS_4_TX,
+ .stream_name = "Slimbus4 Capture",
+ .cpu_dai_name = "msm-dai-q6-dev.16393",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_tx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
+ .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup,
+ .ops = &msm8974_be_ops,
+ },
};
struct snd_soc_card snd_soc_card_msm8974 = {
diff --git a/sound/soc/msm/qdsp6/q6adm.c b/sound/soc/msm/qdsp6/q6adm.c
index c6970f1..00394aa 100644
--- a/sound/soc/msm/qdsp6/q6adm.c
+++ b/sound/soc/msm/qdsp6/q6adm.c
@@ -45,7 +45,7 @@
static struct acdb_cal_block mem_addr_audvol[MAX_AUDPROC_TYPES];
static struct adm_ctl this_adm;
-
+static int pseudo_copp[2];
int srs_trumedia_open(int port_id, int srs_tech_id, void *srs_params)
{
@@ -293,6 +293,8 @@
case ADM_CMD_MATRIX_MAP_ROUTINGS:
case ADM_CMD_CONNECT_AFE_PORT:
case ADM_CMD_DISCONNECT_AFE_PORT:
+ case ADM_CMD_CONNECT_AFE_PORT_V2:
+ case ADM_CMD_MULTI_CHANNEL_COPP_OPEN_V3:
atomic_set(&this_adm.copp_stat[index], 1);
wake_up(&this_adm.wait);
break;
@@ -305,9 +307,10 @@
}
switch (data->opcode) {
+
+ case ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN_V3:
case ADM_CMDRSP_COPP_OPEN:
- case ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN:
- case ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN_V3: {
+ case ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN: {
struct adm_copp_open_respond *open = data->payload;
if (open->copp_id == INVALID_COPP_ID) {
pr_err("%s: invalid coppid rxed %d\n",
@@ -316,6 +319,10 @@
wake_up(&this_adm.wait);
break;
}
+ if (index == IDX_PSEUDOPORT_01)
+ pseudo_copp[
+ atomic_read(&this_adm.copp_cnt[index])] =
+ open->copp_id;
atomic_set(&this_adm.copp_id[index], open->copp_id);
atomic_set(&this_adm.copp_stat[index], 1);
pr_debug("%s: coppid rxed=%d\n", __func__,
@@ -337,6 +344,79 @@
return 0;
}
+int adm_connect_afe_port_v2(int mode, int session_id, int port_id,
+ int sample_rate, int channels)
+{
+ struct adm_cmd_connect_afe_port_v2 cmd;
+ int ret = 0;
+ int index;
+
+ pr_debug("%s: port %d session id:%d\n", __func__,
+ port_id, session_id);
+
+ port_id = afe_convert_virtual_to_portid(port_id);
+
+ if (afe_validate_port(port_id) < 0) {
+ pr_err("%s port idi[%d] is invalid\n", __func__, port_id);
+ return -ENODEV;
+ }
+ if (this_adm.apr == NULL) {
+ this_adm.apr = apr_register("ADSP", "ADM", adm_callback,
+ 0xFFFFFFFF, &this_adm);
+ if (this_adm.apr == NULL) {
+ pr_err("%s: Unable to register ADM\n", __func__);
+ ret = -ENODEV;
+ return ret;
+ }
+ rtac_set_adm_handle(this_adm.apr);
+ }
+ index = afe_get_port_index(port_id);
+ pr_debug("%s: Port ID %d, index %d\n", __func__, port_id, index);
+
+ cmd.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
+ cmd.hdr.pkt_size = sizeof(cmd);
+ cmd.hdr.src_svc = APR_SVC_ADM;
+ cmd.hdr.src_domain = APR_DOMAIN_APPS;
+ cmd.hdr.src_port = port_id;
+ cmd.hdr.dest_svc = APR_SVC_ADM;
+ cmd.hdr.dest_domain = APR_DOMAIN_ADSP;
+ cmd.hdr.dest_port = port_id;
+ cmd.hdr.token = port_id;
+ cmd.hdr.opcode = ADM_CMD_CONNECT_AFE_PORT_V2;
+
+ cmd.mode = mode;
+ cmd.session_id = session_id;
+ cmd.afe_port_id = port_id;
+ cmd.num_channels = channels;
+ cmd.sampling_rate = sample_rate;
+
+ atomic_set(&this_adm.copp_stat[index], 0);
+ ret = apr_send_pkt(this_adm.apr, (uint32_t *)&cmd);
+ if (ret < 0) {
+ pr_err("%s:ADM enable for port %d failed\n",
+ __func__, port_id);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+ ret = wait_event_timeout(this_adm.wait,
+ atomic_read(&this_adm.copp_stat[index]),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ pr_err("%s ADM connect AFE failed for port %d\n", __func__,
+ port_id);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+ atomic_inc(&this_adm.copp_cnt[index]);
+ return 0;
+
+fail_cmd:
+
+ return ret;
+
+}
+
static int send_adm_cal_block(int port_id, struct acdb_cal_block *aud_cal)
{
s32 result = 0;
@@ -718,6 +798,138 @@
return ret;
}
+int adm_multi_ch_copp_pseudo_open_v3(int port_id, int path,
+ int rate, int channel_mode,
+ int topology)
+{
+ struct adm_multi_channel_copp_open_v3 open;
+ int ret = 0;
+ int index;
+
+ pr_debug("%s: port %d path:%d rate:%d mode:%d\n", __func__,
+ port_id, path, rate, channel_mode);
+
+ port_id = afe_convert_virtual_to_portid(port_id);
+
+ if (afe_validate_port(port_id) < 0) {
+ pr_err("%s port idi[%d] is invalid\n", __func__, port_id);
+ return -ENODEV;
+ }
+
+ index = afe_get_port_index(port_id);
+ pr_debug("%s: Port ID %d, index %d\n", __func__, port_id, index);
+
+ if (this_adm.apr == NULL) {
+ this_adm.apr = apr_register("ADSP", "ADM", adm_callback,
+ 0xFFFFFFFF, &this_adm);
+ if (this_adm.apr == NULL) {
+ pr_err("%s: Unable to register ADM\n", __func__);
+ ret = -ENODEV;
+ return ret;
+ }
+ rtac_set_adm_handle(this_adm.apr);
+ }
+
+
+ {
+ open.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
+ open.hdr.pkt_size = sizeof(open);
+ open.hdr.src_svc = APR_SVC_ADM;
+ open.hdr.src_domain = APR_DOMAIN_APPS;
+ open.hdr.src_port = port_id;
+ open.hdr.dest_svc = APR_SVC_ADM;
+ open.hdr.dest_domain = APR_DOMAIN_ADSP;
+ open.hdr.dest_port = port_id;
+ open.hdr.token = port_id;
+ open.hdr.opcode = ADM_CMD_MULTI_CHANNEL_COPP_OPEN_V3;
+ memset(open.dev_channel_mapping, 0, 8);
+
+ if (channel_mode == 1) {
+ open.dev_channel_mapping[0] = PCM_CHANNEL_FC;
+ } else if (channel_mode == 2) {
+ open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
+ open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
+ } else if (channel_mode == 4) {
+ open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
+ open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
+ open.dev_channel_mapping[2] = PCM_CHANNEL_RB;
+ open.dev_channel_mapping[3] = PCM_CHANNEL_LB;
+ } else if (channel_mode == 6) {
+ open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
+ open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
+ open.dev_channel_mapping[2] = PCM_CHANNEL_LFE;
+ open.dev_channel_mapping[3] = PCM_CHANNEL_FC;
+ open.dev_channel_mapping[4] = PCM_CHANNEL_LB;
+ open.dev_channel_mapping[5] = PCM_CHANNEL_RB;
+ } else if (channel_mode == 8) {
+ open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
+ open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
+ open.dev_channel_mapping[2] = PCM_CHANNEL_LFE;
+ open.dev_channel_mapping[3] = PCM_CHANNEL_FC;
+ open.dev_channel_mapping[4] = PCM_CHANNEL_LB;
+ open.dev_channel_mapping[5] = PCM_CHANNEL_RB;
+ open.dev_channel_mapping[6] = PCM_CHANNEL_FLC;
+ open.dev_channel_mapping[7] = PCM_CHANNEL_FRC;
+ } else {
+ pr_err("%s invalid num_chan %d\n", __func__,
+ channel_mode);
+ return -EINVAL;
+ }
+
+ open.mode = path;
+ open.endpoint_id1 = port_id;
+ open.endpoint_id2 = 0xFFFF;
+ open.bit_width = 16;
+
+ if (path == ADM_PATH_PLAYBACK)
+ open.topology_id = get_adm_rx_topology();
+ else {
+ open.topology_id = get_adm_tx_topology();
+ if ((open.topology_id ==
+ VPM_TX_SM_ECNS_COPP_TOPOLOGY) ||
+ (open.topology_id ==
+ VPM_TX_DM_FLUENCE_COPP_TOPOLOGY))
+ rate = 16000;
+ }
+
+ if (open.topology_id == 0)
+ open.topology_id = topology;
+
+ open.channel_config = channel_mode & 0x00FF;
+ open.rate = rate;
+ open.flags = 0;
+
+ pr_debug("%s: channel_config=%d port_id=%d rate=%d" \
+ "topology_id=0x%X\n", __func__, open.channel_config,\
+ open.endpoint_id1, open.rate,\
+ open.topology_id);
+
+ atomic_set(&this_adm.copp_stat[index], 0);
+ ret = apr_send_pkt(this_adm.apr, (uint32_t *)&open);
+ if (ret < 0) {
+ pr_err("%s:ADM enable for port %d failed\n",
+ __func__, port_id);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+ ret = wait_event_timeout(this_adm.wait,
+ atomic_read(&this_adm.copp_stat[index]),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ pr_err("%s ADM open failed for port %d\n", __func__,
+ port_id);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+ }
+ atomic_inc(&this_adm.copp_cnt[index]);
+ return 0;
+
+fail_cmd:
+ return ret;
+
+}
int adm_multi_ch_copp_open(int port_id, int path, int rate, int channel_mode,
int topology, int perfmode)
@@ -1127,6 +1339,56 @@
pr_debug("%s ec_ref_rx:%d", __func__, this_adm.ec_ref_rx);
}
+int adm_pseudo_close(int port_id)
+{
+ struct apr_hdr close;
+
+ int ret = 0, i = 0;
+ int index = 0;
+ int pseudo_copp_cnt;
+ index = afe_get_port_index(port_id);
+ if (afe_validate_port(port_id) < 0)
+ return -EINVAL;
+
+ pseudo_copp_cnt = atomic_read(&this_adm.copp_cnt[index]);
+ pr_debug("%s port_id=%d index %d copp_cnt %d\n", __func__, port_id,
+ index, pseudo_copp_cnt);
+
+ for (i = 0; i < pseudo_copp_cnt; i++) {
+ close.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
+ close.pkt_size = sizeof(close);
+ close.src_svc = APR_SVC_ADM;
+ close.src_domain = APR_DOMAIN_APPS;
+ close.src_port = port_id;
+ close.dest_svc = APR_SVC_ADM;
+ close.dest_domain = APR_DOMAIN_ADSP;
+ close.dest_port = pseudo_copp[i];
+ close.token = port_id;
+ close.opcode = ADM_CMD_COPP_CLOSE;
+
+ atomic_set(&this_adm.copp_id[index], RESET_COPP_ID);
+ atomic_set(&this_adm.copp_stat[index], 0);
+
+
+ pr_debug("%s:coppid %d portid=%d index=%d coppcnt=%d\n",
+ __func__,
+ atomic_read(&this_adm.copp_id[index]),
+ port_id, index,
+ atomic_read(&this_adm.copp_cnt[index]));
+
+ ret = apr_send_pkt(this_adm.apr, (uint32_t *)&close);
+
+ ret = wait_event_timeout(this_adm.wait,
+ atomic_read(&this_adm.copp_stat[index]),
+ msecs_to_jiffies(TIMEOUT_MS));
+ }
+
+ atomic_set(&this_adm.copp_cnt[index], 0);
+ return ret;
+
+}
+
int adm_close(int port_id)
{
struct apr_hdr close;
diff --git a/sound/soc/msm/qdsp6/q6afe.c b/sound/soc/msm/qdsp6/q6afe.c
index a4f4b60..6cabc97 100644
--- a/sound/soc/msm/qdsp6/q6afe.c
+++ b/sound/soc/msm/qdsp6/q6afe.c
@@ -33,6 +33,7 @@
uint32_t token, uint32_t *payload, void *priv);
void *tx_private_data;
void *rx_private_data;
+ u16 dtmf_gen_rx_portid;
};
static struct afe_ctl this_afe;
@@ -91,6 +92,7 @@
case AFE_SERVICE_CMD_MEMORY_MAP:
case AFE_SERVICE_CMD_MEMORY_UNMAP:
case AFE_SERVICE_CMD_UNREG_RTPORT:
+ case AFE_PORTS_CMD_DTMF_CTL:
atomic_set(&this_afe.state, 0);
wake_up(&this_afe.wait);
break;
@@ -156,6 +158,7 @@
case VOICE_PLAYBACK_TX:
case RT_PROXY_PORT_001_RX:
case SLIMBUS_4_RX:
+ case PSEUDOPORT_01:
ret = MSM_AFE_PORT_TYPE_RX;
break;
@@ -225,6 +228,7 @@
case RT_PROXY_PORT_001_TX:
case SLIMBUS_4_RX:
case SLIMBUS_4_TX:
+ case PSEUDOPORT_01:
{
ret = 0;
break;
@@ -295,6 +299,7 @@
case RT_PROXY_PORT_001_TX: return IDX_RT_PROXY_PORT_001_TX;
case SLIMBUS_4_RX: return IDX_SLIMBUS_4_RX;
case SLIMBUS_4_TX: return IDX_SLIMBUS_4_TX;
+ case PSEUDOPORT_01: return IDX_PSEUDOPORT_01;
default: return -EINVAL;
}
@@ -331,6 +336,9 @@
case RT_PROXY_PORT_001_TX:
ret_size = SIZEOF_CFG_CMD(afe_port_rtproxy_cfg);
break;
+ case PSEUDOPORT_01:
+ ret_size = SIZEOF_CFG_CMD(afe_port_pseudo_cfg);
+ break;
case PCM_RX:
case PCM_TX:
case SECONDARY_PCM_RX:
@@ -506,6 +514,11 @@
else
config.hdr.opcode = AFE_PORT_CMD_I2S_CONFIG;
break;
+ case PSEUDOPORT_01:
+ config.hdr.opcode = AFE_PORT_AUDIO_IF_CONFIG;
+ pr_debug("%s, config, opcode=%x\n", __func__,
+ config.hdr.opcode);
+ break;
default:
config.hdr.opcode = AFE_PORT_AUDIO_IF_CONFIG;
break;
@@ -1610,6 +1623,83 @@
.write = afe_debug_write
};
#endif
+
+void afe_set_dtmf_gen_rx_portid(u16 port_id, int set)
+{
+ if (set)
+ this_afe.dtmf_gen_rx_portid = port_id;
+ else if (this_afe.dtmf_gen_rx_portid == port_id)
+ this_afe.dtmf_gen_rx_portid = -1;
+}
+
+int afe_dtmf_generate_rx(int64_t duration_in_ms,
+ uint16_t high_freq,
+ uint16_t low_freq, uint16_t gain)
+{
+ int ret = 0;
+ struct afe_dtmf_generation_command cmd_dtmf;
+
+ pr_debug("%s: DTMF AFE Gen\n", __func__);
+
+ if (afe_validate_port(this_afe.dtmf_gen_rx_portid) < 0) {
+ pr_err("%s: Failed : Invalid Port id = %d\n",
+ __func__, this_afe.dtmf_gen_rx_portid);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+
+ if (this_afe.apr == NULL) {
+ this_afe.apr = apr_register("ADSP", "AFE", afe_callback,
+ 0xFFFFFFFF, &this_afe);
+ pr_debug("%s: Register AFE\n", __func__);
+ if (this_afe.apr == NULL) {
+ pr_err("%s: Unable to register AFE\n", __func__);
+ ret = -ENODEV;
+ return ret;
+ }
+ }
+
+ pr_debug("dur=%lld: hfreq=%d lfreq=%d gain=%d portid=%x\n",
+ duration_in_ms, high_freq, low_freq, gain,
+ this_afe.dtmf_gen_rx_portid);
+
+ cmd_dtmf.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
+ cmd_dtmf.hdr.pkt_size = sizeof(cmd_dtmf);
+ cmd_dtmf.hdr.src_port = 0;
+ cmd_dtmf.hdr.dest_port = 0;
+ cmd_dtmf.hdr.token = 0;
+ cmd_dtmf.hdr.opcode = AFE_PORTS_CMD_DTMF_CTL;
+ cmd_dtmf.duration_in_ms = duration_in_ms;
+ cmd_dtmf.high_freq = high_freq;
+ cmd_dtmf.low_freq = low_freq;
+ cmd_dtmf.gain = gain;
+ cmd_dtmf.num_ports = 1;
+ cmd_dtmf.port_ids = this_afe.dtmf_gen_rx_portid;
+
+ atomic_set(&this_afe.state, 1);
+ ret = apr_send_pkt(this_afe.apr, (uint32_t *) &cmd_dtmf);
+ if (ret < 0) {
+ pr_err("%s: AFE DTMF failed for num_ports:%d ids:%x\n",
+ __func__, cmd_dtmf.num_ports, cmd_dtmf.port_ids);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+
+ ret = wait_event_timeout(this_afe.wait,
+ (atomic_read(&this_afe.state) == 0),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (ret < 0) {
+ pr_err("%s: wait_event timeout\n", __func__);
+ ret = -EINVAL;
+ goto fail_cmd;
+ }
+ return 0;
+
+fail_cmd:
+ return ret;
+}
+
int afe_sidetone(u16 tx_port_id, u16 rx_port_id, u16 enable, uint16_t gain)
{
struct afe_port_sidetone_command cmd_sidetone;
@@ -1744,6 +1834,7 @@
atomic_set(&this_afe.state, 0);
atomic_set(&this_afe.status, 0);
this_afe.apr = NULL;
+ this_afe.dtmf_gen_rx_portid = -1;
#ifdef CONFIG_DEBUG_FS
debugfs_afelb = debugfs_create_file("afe_loopback",
S_IFREG | S_IWUGO, NULL, (void *) "afe_loopback",
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index b7d5d33..cde5b02 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -35,7 +35,6 @@
#include <mach/memory.h>
#include <mach/debug_mm.h>
-#include <mach/peripheral-loader.h>
#include <mach/qdsp6v2/audio_acdb.h>
#include <mach/qdsp6v2/rtac.h>
@@ -487,6 +486,7 @@
struct audio_buffer *buf;
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
int len;
+ unsigned int bufsz_4k_aligned;
#endif
if (!(ac) || ((dir != IN) && (dir != OUT)))
@@ -527,8 +527,15 @@
mutex_unlock(&ac->cmd_lock);
goto fail;
}
+ bufsz_4k_aligned = (bufsz + 4095) &
+ (~4095);
+ pr_debug("%s: bufsz_4k_aligned %d"\
+ "bufsz = %d\n",
+ __func__, bufsz_4k_aligned,
+ bufsz);
buf[cnt].handle = ion_alloc
- (buf[cnt].client, bufsz, SZ_4K,
+ (buf[cnt].client,
+ bufsz_4k_aligned, SZ_4K,
(0x1 << ION_AUDIO_HEAP_ID), 0);
if (IS_ERR_OR_NULL((void *)
buf[cnt].handle)) {
@@ -758,6 +765,7 @@
{
uint32_t token;
uint32_t *payload = data->payload;
+ struct audio_client *ac;
if (data->opcode == RESET_EVENTS) {
pr_debug("%s: Reset event is received: %d %d apr[%p]\n",
@@ -777,6 +785,8 @@
if (data->opcode == APR_BASIC_RSP_RESULT) {
token = data->token;
+ ac = (struct audio_client *)data->token;
+ pr_debug("%s: audio_client addr %x\n", __func__, (uint32_t)ac);
switch (payload[0]) {
case ASM_SESSION_CMD_MEMORY_MAP:
case ASM_SESSION_CMD_MEMORY_UNMAP:
@@ -784,9 +794,15 @@
case ASM_SESSION_CMD_MEMORY_UNMAP_REGIONS:
pr_debug("%s:command[0x%x]success [0x%x]\n",
__func__, payload[0], payload[1]);
- if (atomic_read(&this_mmap.cmd_state)) {
- atomic_set(&this_mmap.cmd_state, 0);
- wake_up(&this_mmap.cmd_wait);
+ if (atomic_read(&ac->cmd_state)) {
+ atomic_set(&ac->cmd_state, 0);
+ if (payload[1] != ADSP_EOK) {
+ pr_err("payload[1]:%d error case\n",
+ payload[1]);
+ atomic_set(&ac->cmd_response, 1);
+ } else
+ atomic_set(&ac->cmd_response, 0);
+ wake_up(&ac->cmd_wait);
}
break;
default:
@@ -894,6 +910,7 @@
case ASM_STREAM_CMD_SET_ENCDEC_PARAM:
case ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED:
case ASM_STREAM_CMD_OPEN_READ_COMPRESSED:
+ case ASM_STREAM_CMD_OPEN_TRANSCODE_LOOPBACK:
if (atomic_read(&ac->cmd_state) && wakeup_flag) {
atomic_set(&ac->cmd_state, 0);
pr_debug("response payload[1]:%d",
@@ -1066,6 +1083,114 @@
return 0;
}
+int q6asm_open_transcode_loopback(struct audio_client *ac, uint32_t channels)
+{
+ int rc = 0x00;
+ struct asm_stream_cmd_open_transcode_loopback open;
+
+ if ((ac == NULL) || (ac->apr == NULL)) {
+ pr_err("%s: APR handle NULL\n", __func__);
+ return -EINVAL;
+ }
+ pr_debug("%s: session[%d] channels = %d", __func__, ac->session,
+ channels);
+
+ q6asm_add_hdr(ac, &open.hdr, sizeof(open), TRUE);
+
+ open.hdr.opcode = ASM_STREAM_CMD_OPEN_TRANSCODE_LOOPBACK;
+
+ open.mode_flags = 0;
+
+ if (channels > 2)
+ open.src_format_id = MULTI_CHANNEL_PCM;
+ else
+ open.src_format_id = LINEAR_PCM;
+
+
+ open.sink_format_id = DTS;
+ open.audproc_topo_id = DEFAULT_POPP_TOPOLOGY;
+ open.src_endpoint_type = 0;
+ open.sink_endpoint_type = 0;
+ open.bits_per_sample = 16;
+ open.reserved = 0;
+
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &open);
+ if (rc < 0) {
+ pr_err("%s: open failed op[0x%x]rc[%d]\n", \
+ __func__, open.hdr.opcode, rc);
+ goto fail_cmd;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("%s: timeout. waited for OPEN_WRITE rc[%d]\n", __func__,
+ rc);
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
+int q6asm_enc_cfg_blk_dts(struct audio_client *ac,
+ uint32_t sample_rate,
+ uint32_t channels)
+{
+ struct asm_stream_cmd_encdec_cfg_blk enc_cfg;
+ int rc = 0;
+
+ pr_debug("%s: sample_rate=%d,channels=%d\n", __func__,
+ sample_rate, channels);
+
+ q6asm_add_hdr(ac, &enc_cfg.hdr, sizeof(enc_cfg), TRUE);
+
+ enc_cfg.hdr.opcode = ASM_STREAM_CMD_SET_ENCDEC_PARAM;
+ enc_cfg.param_id = ASM_ENCDEC_CFG_BLK_ID;
+ enc_cfg.param_size = sizeof(struct asm_encode_cfg_blk);
+ enc_cfg.enc_blk.frames_per_buf = 0;
+ enc_cfg.enc_blk.format_id = DTS;
+ enc_cfg.enc_blk.cfg_size = sizeof(struct asm_dts_enc_cfg);
+ enc_cfg.enc_blk.cfg.dts.sample_rate = sample_rate;
+ enc_cfg.enc_blk.cfg.dts.num_channels = channels;
+ if (channels == 2) {
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[0] = PCM_CHANNEL_FL;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[1] = PCM_CHANNEL_FR;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[2] = 0;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[3] = 0;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[4] = 0;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[5] = 0;
+ } else if (channels == 4) {
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[0] = PCM_CHANNEL_FL;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[1] = PCM_CHANNEL_FR;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[2] = PCM_CHANNEL_LS;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[3] = PCM_CHANNEL_RS;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[4] = 0;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[5] = 0;
+ } else if (channels == 6) {
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[0] = PCM_CHANNEL_FL;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[1] = PCM_CHANNEL_FR;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[2] = PCM_CHANNEL_LFE;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[3] = PCM_CHANNEL_LS;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[4] = PCM_CHANNEL_RS;
+ enc_cfg.enc_blk.cfg.dts.channel_mapping[5] = PCM_CHANNEL_FC;
+ }
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &enc_cfg);
+ if (rc < 0) {
+ pr_err("Comamnd %d failed\n", ASM_STREAM_CMD_SET_ENCDEC_PARAM);
+ rc = -EINVAL;
+ goto fail_cmd;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("timeout. waited for FORMAT_UPDATE\n");
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
void *q6asm_is_cpu_buf_avail(int dir, struct audio_client *ac, uint32_t *size,
uint32_t *index)
{
@@ -1219,14 +1344,16 @@
static void q6asm_add_mmaphdr(struct apr_hdr *hdr, uint32_t pkt_size,
uint32_t cmd_flg)
{
+ struct audio_client *ac;
pr_debug("%s:pkt size=%d cmd_flg=%d\n", __func__, pkt_size, cmd_flg);
+ ac = (struct audio_client *)hdr->token;
+ pr_debug("%s: audio_client = %x\n", __func__, (uint32_t)ac);
hdr->hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, \
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
hdr->src_port = 0;
hdr->dest_port = 0;
if (cmd_flg) {
- hdr->token = 0;
- atomic_set(&this_mmap.cmd_state, 1);
+ atomic_set(&ac->cmd_state, 1);
}
hdr->pkt_size = pkt_size;
return;
@@ -2705,6 +2832,8 @@
mem_map.mempool_id = 0; /* EBI */
mem_map.reserved = 0;
+ pr_debug("%s: audio_client addr %x\n", __func__, (uint32_t)ac);
+ mem_map.hdr.token = (uint32_t)ac;
q6asm_add_mmaphdr(&mem_map.hdr,
sizeof(struct asm_stream_cmd_memory_map), TRUE);
@@ -2719,14 +2848,20 @@
goto fail_cmd;
}
- rc = wait_event_timeout(this_mmap.cmd_wait,
- (atomic_read(&this_mmap.cmd_state) == 0), 5 * HZ);
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
if (!rc) {
pr_err("timeout. waited for memory_map\n");
rc = -EINVAL;
goto fail_cmd;
}
+ if (atomic_read(&ac->cmd_response)) {
+ pr_err("%s: ASM_SESSION_CMD_MEMORY_MAP cmd failed\n", __func__);
+ rc = -EINVAL;
+ goto fail_cmd;
+ }
rc = 0;
+
fail_cmd:
return rc;
}
@@ -2742,6 +2877,8 @@
}
pr_debug("%s: Session[%d]\n", __func__, ac->session);
+ pr_debug("%s: audio_client addr %x\n", __func__, (uint32_t)ac);
+ mem_unmap.hdr.token = (uint32_t)ac;
q6asm_add_mmaphdr(&mem_unmap.hdr,
sizeof(struct asm_stream_cmd_memory_unmap), TRUE);
mem_unmap.hdr.opcode = ASM_SESSION_CMD_MEMORY_UNMAP;
@@ -2755,14 +2892,21 @@
goto fail_cmd;
}
- rc = wait_event_timeout(this_mmap.cmd_wait,
- (atomic_read(&this_mmap.cmd_state) == 0), 5 * HZ);
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
if (!rc) {
- pr_err("timeout. waited for memory_map\n");
+ pr_err("timeout. waited for memory_unmap\n");
+ rc = -EINVAL;
+ goto fail_cmd;
+ }
+ if (atomic_read(&ac->cmd_response)) {
+ pr_err("%s: ASM_SESSION_CMD_MEMORY_UNMAP cmd failed\n",
+ __func__);
rc = -EINVAL;
goto fail_cmd;
}
rc = 0;
+
fail_cmd:
return rc;
}
@@ -2851,6 +2995,8 @@
}
mmap_regions = (struct asm_stream_cmd_memory_map_regions *)
mmap_region_cmd;
+ mmap_regions->hdr.token = (uint32_t)ac;
+ pr_debug("%s: audio_client addr %x\n", __func__, (uint32_t)ac);
q6asm_add_mmaphdr(&mmap_regions->hdr, cmd_size, TRUE);
mmap_regions->hdr.opcode = ASM_SESSION_CMD_MEMORY_MAP_REGIONS;
mmap_regions->mempool_id = 0;
@@ -2876,14 +3022,21 @@
goto fail_cmd;
}
- rc = wait_event_timeout(this_mmap.cmd_wait,
- (atomic_read(&this_mmap.cmd_state) == 0), 5*HZ);
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
if (!rc) {
- pr_err("timeout. waited for memory_map\n");
+ pr_err("timeout. waited for map_regions\n");
+ rc = -EINVAL;
+ goto fail_cmd;
+ }
+ if (atomic_read(&ac->cmd_response)) {
+ pr_err("%s: ASM_SESSION_CMD_MEMORY_MAP_REGIONS cmd failed\n",
+ __func__);
rc = -EINVAL;
goto fail_cmd;
}
rc = 0;
+
fail_cmd:
kfree(mmap_region_cmd);
return rc;
@@ -2919,6 +3072,8 @@
}
unmap_regions = (struct asm_stream_cmd_memory_unmap_regions *)
unmap_region_cmd;
+ unmap_regions->hdr.token = (uint32_t)ac;
+ pr_debug("%s: audio_client addr %x\n", __func__, (uint32_t)ac);
q6asm_add_mmaphdr(&unmap_regions->hdr, cmd_size, TRUE);
unmap_regions->hdr.opcode = ASM_SESSION_CMD_MEMORY_UNMAP_REGIONS;
unmap_regions->nregions = bufcnt & 0x00ff;
@@ -2940,10 +3095,17 @@
goto fail_cmd;
}
- rc = wait_event_timeout(this_mmap.cmd_wait,
- (atomic_read(&this_mmap.cmd_state) == 0), 5*HZ);
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
if (!rc) {
- pr_err("timeout. waited for memory_unmap\n");
+ pr_err("timeout. waited for unmap_regions\n");
+ rc = -EINVAL;
+ goto fail_cmd;
+ }
+ if (atomic_read(&ac->cmd_response)) {
+ pr_err("%s: ASM_SESSION_CMD_MEMORY_UNMAP_REGIONS cmd failed\n",
+ __func__);
+ rc = -EINVAL;
goto fail_cmd;
}
rc = 0;
diff --git a/sound/soc/msm/qdsp6/q6voice.c b/sound/soc/msm/qdsp6/q6voice.c
index cb2e39b..3b1e722 100644
--- a/sound/soc/msm/qdsp6/q6voice.c
+++ b/sound/soc/msm/qdsp6/q6voice.c
@@ -146,6 +146,21 @@
v->cvp_handle = cvp_handle;
}
+char *voc_get_session_name(u16 session_id)
+{
+ char *session_name = NULL;
+
+ if (session_id == common.voice[VOC_PATH_PASSIVE].session_id) {
+ session_name = VOICE_SESSION_NAME;
+ } else if (session_id ==
+ common.voice[VOC_PATH_VOLTE_PASSIVE].session_id) {
+ session_name = VOLTE_SESSION_NAME;
+ } else if (session_id == common.voice[VOC_PATH_FULL].session_id) {
+ session_name = VOIP_SESSION_NAME;
+ }
+ return session_name;
+}
+
uint16_t voc_get_session_id(char *name)
{
u16 session_id = 0;
@@ -894,6 +909,105 @@
return 0;
}
+static int voice_send_dtmf_rx_detection_cmd(struct voice_data *v,
+ uint32_t enable)
+{
+ int ret = 0;
+ void *apr_cvs;
+ u16 cvs_handle;
+ struct cvs_set_rx_dtmf_detection_cmd cvs_dtmf_rx_detection;
+
+ if (v == NULL) {
+ pr_err("%s: v is NULL\n", __func__);
+ return -EINVAL;
+ }
+ apr_cvs = common.apr_q6_cvs;
+
+ if (!apr_cvs) {
+ pr_err("%s: apr_cvs is NULL.\n", __func__);
+ return -EINVAL;
+ }
+
+ cvs_handle = voice_get_cvs_handle(v);
+
+ /* Set SET_DTMF_RX_DETECTION */
+ cvs_dtmf_rx_detection.hdr.hdr_field =
+ APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE),
+ APR_PKT_VER);
+ cvs_dtmf_rx_detection.hdr.pkt_size =
+ APR_PKT_SIZE(APR_HDR_SIZE,
+ sizeof(cvs_dtmf_rx_detection) - APR_HDR_SIZE);
+ cvs_dtmf_rx_detection.hdr.src_port = v->session_id;
+ cvs_dtmf_rx_detection.hdr.dest_port = cvs_handle;
+ cvs_dtmf_rx_detection.hdr.token = 0;
+ cvs_dtmf_rx_detection.hdr.opcode =
+ VSS_ISTREAM_CMD_SET_RX_DTMF_DETECTION;
+ cvs_dtmf_rx_detection.cvs_dtmf_det.enable = enable;
+
+ v->cvs_state = CMD_STATUS_FAIL;
+
+ ret = apr_send_pkt(apr_cvs, (uint32_t *) &cvs_dtmf_rx_detection);
+ if (ret < 0) {
+ pr_err("%s: Error %d sending SET_DTMF_RX_DETECTION\n",
+ __func__,
+ ret);
+ return -EINVAL;
+ }
+
+ ret = wait_event_timeout(v->cvs_wait,
+ (v->cvs_state == CMD_STATUS_SUCCESS),
+ msecs_to_jiffies(TIMEOUT_MS));
+
+ if (!ret) {
+ pr_err("%s: wait_event timeout\n", __func__);
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+void voc_disable_dtmf_det_on_active_sessions(void)
+{
+ struct voice_data *v = NULL;
+ int i;
+ for (i = 0; i < MAX_VOC_SESSIONS; i++) {
+ v = &common.voice[i];
+ if ((v->dtmf_rx_detect_en) &&
+ ((v->voc_state == VOC_RUN) ||
+ (v->voc_state == VOC_CHANGE) ||
+ (v->voc_state == VOC_STANDBY))) {
+ pr_debug("disable dtmf det on ses_id=%d\n",
+ v->session_id);
+ voice_send_dtmf_rx_detection_cmd(v, 0);
+ }
+ }
+}
+
+int voc_enable_dtmf_rx_detection(uint16_t session_id, uint32_t enable)
+{
+ struct voice_data *v = voice_get_session(session_id);
+ int ret = 0;
+
+ if (v == NULL) {
+ pr_err("%s: invalid session_id 0x%x\n", __func__, session_id);
+ return -EINVAL;
+ }
+
+ mutex_lock(&v->lock);
+ v->dtmf_rx_detect_en = enable;
+
+ if ((v->voc_state == VOC_RUN) ||
+ (v->voc_state == VOC_CHANGE) ||
+ (v->voc_state == VOC_STANDBY))
+ ret = voice_send_dtmf_rx_detection_cmd(v,
+ v->dtmf_rx_detect_en);
+
+ mutex_unlock(&v->lock);
+
+ return ret;
+}
+
static int voice_config_cvs_vocoder(struct voice_data *v)
{
int ret = 0;
@@ -2207,6 +2321,9 @@
if (v->rec_info.rec_enable)
voice_cvs_start_record(v, v->rec_info.rec_mode);
+ if (v->dtmf_rx_detect_en)
+ voice_send_dtmf_rx_detection_cmd(v, v->dtmf_rx_detect_en);
+
rtac_add_voice(voice_get_cvs_handle(v),
voice_get_cvp_handle(v),
v->dev_rx.port_id, v->dev_tx.port_id,
@@ -2445,6 +2562,10 @@
/* send stop voice cmd */
voice_send_stop_voice_cmd(v);
+ /* send stop dtmf detecton cmd */
+ if (v->dtmf_rx_detect_en)
+ voice_send_dtmf_rx_detection_cmd(v, 0);
+
/* Clear mute setting */
v->dev_tx.mute = common.default_mute_val;
@@ -3700,6 +3821,13 @@
common.mvs_info.private_data = private_data;
}
+void voc_register_dtmf_rx_detection_cb(dtmf_rx_det_cb_fn dtmf_rx_ul_cb,
+ void *private_data)
+{
+ common.dtmf_info.dtmf_rx_ul_cb = dtmf_rx_ul_cb;
+ common.dtmf_info.private_data = private_data;
+}
+
void voc_config_vocoder(uint32_t media_type,
uint32_t rate,
uint32_t network_type,
@@ -3876,6 +4004,7 @@
case VSS_ISTREAM_CMD_STOP_PLAYBACK:
case VSS_ISTREAM_CMD_START_RECORD:
case VSS_ISTREAM_CMD_STOP_RECORD:
+ case VSS_ISTREAM_CMD_SET_RX_DTMF_DETECTION:
pr_debug("%s: cmd = 0x%x\n", __func__, ptr[0]);
v->cvs_state = CMD_STATUS_SUCCESS;
wake_up(&v->cvs_wait);
@@ -3947,8 +4076,30 @@
} else if (data->opcode == VOICE_EVT_GET_PARAM_ACK) {
rtac_make_voice_callback(RTAC_CVS, data->payload,
data->payload_size);
- } else
+ } else if (data->opcode == VSS_ISTREAM_EVT_RX_DTMF_DETECTED) {
+ struct vss_istream_evt_rx_dtmf_detected *dtmf_rx_detected;
+ uint32_t *voc_pkt = data->payload;
+ uint32_t pkt_len = data->payload_size;
+
+ if ((voc_pkt != NULL) &&
+ (pkt_len ==
+ sizeof(struct vss_istream_evt_rx_dtmf_detected))) {
+
+ dtmf_rx_detected =
+ (struct vss_istream_evt_rx_dtmf_detected *) voc_pkt;
+ pr_debug("RX_DTMF_DETECTED low_freq=%d high_freq=%d\n",
+ dtmf_rx_detected->low_freq,
+ dtmf_rx_detected->high_freq);
+ if (c->dtmf_info.dtmf_rx_ul_cb)
+ c->dtmf_info.dtmf_rx_ul_cb((uint8_t *)voc_pkt,
+ voc_get_session_name(v->session_id),
+ c->dtmf_info.private_data);
+ } else {
+ pr_err("Invalid packet\n");
+ }
+ } else {
pr_debug("Unknown opcode 0x%x\n", data->opcode);
+ }
fail:
return 0;
@@ -3971,7 +4122,6 @@
v = voice_get_session(data->dest_port);
if (v == NULL) {
pr_err("%s: v is NULL\n", __func__);
-
return -EINVAL;
}
@@ -4141,6 +4291,7 @@
common.voice[i].dev_tx.port_id = 1;
common.voice[i].dev_rx.port_id = 0;
common.voice[i].sidetone_gain = 0x512;
+ common.voice[i].dtmf_rx_detect_en = 0;
common.voice[i].voc_state = VOC_INIT;
diff --git a/sound/soc/msm/qdsp6/q6voice.h b/sound/soc/msm/qdsp6/q6voice.h
index 34b1b52..2fc2266 100644
--- a/sound/soc/msm/qdsp6/q6voice.h
+++ b/sound/soc/msm/qdsp6/q6voice.h
@@ -567,6 +567,55 @@
/* Reserved, set to 0. */
};
+/*
+ * Event sent by the stream to the client that enables Rx DTMF
+ * detection whenever DTMF is detected in the Rx path.
+ *
+ * The DTMF detection feature can only be used to detect DTMF
+ * frequencies as listed in the vss_istream_evt_rx_dtmf_detected_t
+ * structure.
+ */
+
+#define VSS_ISTREAM_EVT_RX_DTMF_DETECTED (0x0001101A)
+
+struct vss_istream_cmd_set_rx_dtmf_detection {
+ /*
+ * Enables/disables Rx DTMF detection
+ *
+ * Possible values are
+ * 0 - disable
+ * 1 - enable
+ *
+ */
+ uint32_t enable;
+};
+
+#define VSS_ISTREAM_CMD_SET_RX_DTMF_DETECTION (0x00011027)
+
+struct vss_istream_evt_rx_dtmf_detected {
+ uint16_t low_freq;
+ /*
+ * Detected low frequency. Possible values:
+ * 697 Hz
+ * 770 Hz
+ * 852 Hz
+ * 941 Hz
+ */
+ uint16_t high_freq;
+ /*
+ * Detected high frequency. Possible values:
+ * 1209 Hz
+ * 1336 Hz
+ * 1477 Hz
+ * 1633 Hz
+ */
+};
+
+struct cvs_set_rx_dtmf_detection_cmd {
+ struct apr_hdr hdr;
+ struct vss_istream_cmd_set_rx_dtmf_detection cvs_dtmf_det;
+} __packed;
+
struct cvs_create_passive_ctl_session_cmd {
struct apr_hdr hdr;
struct vss_istream_cmd_create_passive_control_session_t cvs_session;
@@ -858,6 +907,10 @@
uint32_t *pkt_len,
void *private_data);
+/* CB for DTMF RX Detection */
+typedef void (*dtmf_rx_det_cb_fn)(uint8_t *pkt,
+ char *session,
+ void *private_data);
struct mvs_driver_info {
uint32_t media_type;
@@ -869,6 +922,11 @@
void *private_data;
};
+struct dtmf_driver_info {
+ dtmf_rx_det_cb_fn dtmf_rx_ul_cb;
+ void *private_data;
+};
+
struct incall_rec_info {
uint32_t rec_enable;
uint32_t rec_mode;
@@ -915,6 +973,8 @@
/* FENC enable value */
uint32_t fens_enable;
+ uint32_t dtmf_rx_detect_en;
+
struct voice_dev_route_state voc_route_state;
u16 session_id;
@@ -961,6 +1021,8 @@
struct mvs_driver_info mvs_info;
+ struct dtmf_driver_info dtmf_info;
+
struct voice_data voice[MAX_VOC_SESSIONS];
};
@@ -968,6 +1030,9 @@
dl_cb_fn dl_cb,
void *private_data);
+void voc_register_dtmf_rx_detection_cb(dtmf_rx_det_cb_fn dtmf_rx_ul_cb,
+ void *private_data);
+
void voc_config_vocoder(uint32_t media_type,
uint32_t rate,
uint32_t network_type,
@@ -1005,11 +1070,20 @@
int voc_enable_cvp(uint16_t session_id);
int voc_set_route_flag(uint16_t session_id, uint8_t path_dir, uint8_t set);
uint8_t voc_get_route_flag(uint16_t session_id, uint8_t path_dir);
+int voc_enable_dtmf_rx_detection(uint16_t session_id, uint32_t enable);
+void voc_disable_dtmf_det_on_active_sessions(void);
+#define MAX_SESSION_NAME_LEN 32
#define VOICE_SESSION_NAME "Voice session"
#define VOIP_SESSION_NAME "VoIP session"
#define VOLTE_SESSION_NAME "VoLTE session"
#define SGLTE_SESSION_NAME "SGLTE session"
+
+#define VOC_PATH_PASSIVE 0
+#define VOC_PATH_FULL 1
+#define VOC_PATH_VOLTE_PASSIVE 2
+#define VOC_PATH_SGLTE_PASSIVE 3
+
uint16_t voc_get_session_id(char *name);
int voc_start_playback(uint32_t set);
diff --git a/sound/soc/msm/qdsp6v2/audio_ocmem.c b/sound/soc/msm/qdsp6v2/audio_ocmem.c
index d38bcbb..9e08be3 100644
--- a/sound/soc/msm/qdsp6v2/audio_ocmem.c
+++ b/sound/soc/msm/qdsp6v2/audio_ocmem.c
@@ -30,6 +30,11 @@
#define AUDIO_OCMEM_BUF_SIZE (512 * SZ_1K)
+static int enable_ocmem_audio_voice;
+module_param(enable_ocmem_audio_voice, int,
+ S_IRUGO | S_IWUSR | S_IWGRP);
+MODULE_PARM_DESC(enable_ocmem_audio_voice, "control OCMEM usage for audio/voice");
+
enum {
OCMEM_STATE_DEFAULT = 0,
OCMEM_STATE_ALLOC = 1,
@@ -71,6 +76,7 @@
spinlock_t audio_lock;
struct workqueue_struct *audio_ocmem_workqueue;
struct workqueue_struct *voice_ocmem_workqueue;
+ bool ocmem_en;
};
static struct audio_ocmem_prv audio_ocmem_lcl;
@@ -416,21 +422,31 @@
struct voice_ocmem_workdata *workdata = NULL;
- if (audio_ocmem_lcl.voice_ocmem_workqueue == NULL) {
- pr_err("%s: voice ocmem workqueue is NULL\n", __func__);
- return -EINVAL;
+ if (enable) {
+ if (enable_ocmem_audio_voice)
+ audio_ocmem_lcl.ocmem_en = true;
+ else
+ audio_ocmem_lcl.ocmem_en = false;
}
- workdata = kzalloc(sizeof(struct voice_ocmem_workdata),
- GFP_ATOMIC);
- if (workdata == NULL) {
- pr_err("%s: mem failure\n", __func__);
- return -ENOMEM;
- }
- workdata->id = cid;
- workdata->en = enable;
+ if (audio_ocmem_lcl.ocmem_en) {
+ if (audio_ocmem_lcl.voice_ocmem_workqueue == NULL) {
+ pr_err("%s: voice ocmem workqueue is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ workdata = kzalloc(sizeof(struct voice_ocmem_workdata),
+ GFP_ATOMIC);
+ if (workdata == NULL) {
+ pr_err("%s: mem failure\n", __func__);
+ return -ENOMEM;
+ }
+ workdata->id = cid;
+ workdata->en = enable;
- INIT_WORK(&workdata->work, voice_ocmem_process_workdata);
- queue_work(audio_ocmem_lcl.voice_ocmem_workqueue, &workdata->work);
+ INIT_WORK(&workdata->work, voice_ocmem_process_workdata);
+ queue_work(audio_ocmem_lcl.voice_ocmem_workqueue,
+ &workdata->work);
+ }
return 0;
}
@@ -510,24 +526,35 @@
{
struct audio_ocmem_workdata *workdata = NULL;
- if (audio_ocmem_lcl.audio_ocmem_workqueue == NULL) {
- pr_err("%s: audio ocmem workqueue is NULL\n", __func__);
- return -EINVAL;
+ if (enable) {
+ if (enable_ocmem_audio_voice)
+ audio_ocmem_lcl.ocmem_en = true;
+ else
+ audio_ocmem_lcl.ocmem_en = false;
}
- workdata = kzalloc(sizeof(struct audio_ocmem_workdata),
+
+ if (audio_ocmem_lcl.ocmem_en) {
+ if (audio_ocmem_lcl.audio_ocmem_workqueue == NULL) {
+ pr_err("%s: audio ocmem workqueue is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ workdata = kzalloc(sizeof(struct audio_ocmem_workdata),
GFP_ATOMIC);
- if (workdata == NULL) {
- pr_err("%s: mem failure\n", __func__);
- return -ENOMEM;
+ if (workdata == NULL) {
+ pr_err("%s: mem failure\n", __func__);
+ return -ENOMEM;
+ }
+ workdata->id = id;
+ workdata->en = enable;
+
+ /* if previous work waiting for ocmem - signal it to exit */
+ atomic_set(&audio_ocmem_lcl.audio_exit, 1);
+
+ INIT_WORK(&workdata->work, audio_ocmem_process_workdata);
+ queue_work(audio_ocmem_lcl.audio_ocmem_workqueue,
+ &workdata->work);
}
- workdata->id = id;
- workdata->en = enable;
-
- /* if previous work waiting for ocmem - signal it to exit */
- atomic_set(&audio_ocmem_lcl.audio_exit, 1);
-
- INIT_WORK(&workdata->work, audio_ocmem_process_workdata);
- queue_work(audio_ocmem_lcl.audio_ocmem_workqueue, &workdata->work);
return 0;
}
@@ -584,6 +611,7 @@
atomic_set(&audio_ocmem_lcl.audio_state, OCMEM_STATE_DEFAULT);
atomic_set(&audio_ocmem_lcl.audio_exit, 0);
spin_lock_init(&audio_ocmem_lcl.audio_lock);
+ audio_ocmem_lcl.ocmem_en = false;
/* populate platform data */
ret = audio_ocmem_platform_data_populate(pdev);
diff --git a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
index 354dece..621d24b 100644
--- a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c
@@ -37,9 +37,39 @@
DECLARE_BITMAP(status_mask, STATUS_MAX);
u32 rate;
u32 channels;
+ u32 bitwidth;
union afe_port_config port_config;
};
+struct msm_dai_q6_mi2s_dai_config {
+ u16 pdata_mi2s_lines;
+ struct msm_dai_q6_dai_data mi2s_dai_data;
+};
+
+struct msm_dai_q6_mi2s_dai_data {
+ struct msm_dai_q6_mi2s_dai_config tx_dai;
+ struct msm_dai_q6_mi2s_dai_config rx_dai;
+ struct snd_pcm_hw_constraint_list rate_constraint;
+ struct snd_pcm_hw_constraint_list bitwidth_constraint;
+};
+
+/* MI2S format field for AFE_PORT_CMD_I2S_CONFIG command
+ * 0: linear PCM
+ * 1: non-linear PCM
+ * 2: PCM data in IEC 60968 container
+ * 3: compressed data in IEC 60958 container
+ */
+static const char *const mi2s_format[] = {
+ "LPCM",
+ "Compr",
+ "LPCM-60958",
+ "Compr-60958"
+};
+
+static const struct soc_enum mi2s_config_enum[] = {
+ SOC_ENUM_SINGLE_EXT(4, mi2s_format),
+};
+
static struct clk *pcm_src_clk;
static struct clk *pcm_branch_clk;
static struct clk *pcm_oe_src_clk;
@@ -597,8 +627,12 @@
break;
case SLIMBUS_0_RX:
case SLIMBUS_1_RX:
+ case SLIMBUS_3_RX:
+ case SLIMBUS_4_RX:
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_3_TX:
+ case SLIMBUS_4_TX:
rc = msm_dai_q6_slim_bus_hw_params(params, dai,
substream->stream);
break;
@@ -708,6 +742,8 @@
switch (dai->id) {
case SLIMBUS_0_RX:
case SLIMBUS_1_RX:
+ case SLIMBUS_3_RX:
+ case SLIMBUS_4_RX:
/*
* channel number to be between 128 and 255.
* For RX port use channel numbers
@@ -730,6 +766,8 @@
break;
case SLIMBUS_0_TX:
case SLIMBUS_1_TX:
+ case SLIMBUS_3_TX:
+ case SLIMBUS_4_TX:
/*
* channel number to be between 128 and 255.
* For TX port use channel numbers
@@ -845,12 +883,13 @@
static struct snd_soc_dai_driver msm_dai_q6_slimbus_1_rx_dai = {
.playback = {
- .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 1,
+ .channels_max = 2,
.rate_min = 8000,
- .rate_max = 16000,
+ .rate_max = 48000,
},
.ops = &msm_dai_q6_ops,
.probe = msm_dai_q6_dai_probe,
@@ -859,12 +898,13 @@
static struct snd_soc_dai_driver msm_dai_q6_slimbus_1_tx_dai = {
.capture = {
- .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
- .channels_max = 1,
+ .channels_max = 2,
.rate_min = 8000,
- .rate_max = 16000,
+ .rate_max = 48000,
},
.ops = &msm_dai_q6_ops,
.probe = msm_dai_q6_dai_probe,
@@ -1145,6 +1185,611 @@
.remove = msm_dai_q6_dai_remove,
};
+static int msm_dai_q6_mi2s_format_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct msm_dai_q6_dai_data *dai_data = kcontrol->private_data;
+ int value = ucontrol->value.integer.value[0];
+ dai_data->port_config.i2s.data_format = value;
+ pr_debug("%s: value = %d, channel = %d, line = %d\n",
+ __func__, value, dai_data->port_config.i2s.mono_stereo,
+ dai_data->port_config.i2s.channel_mode);
+ return 0;
+}
+
+static int msm_dai_q6_mi2s_format_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct msm_dai_q6_dai_data *dai_data = kcontrol->private_data;
+ ucontrol->value.integer.value[0] =
+ dai_data->port_config.i2s.data_format;
+ return 0;
+}
+
+static const struct snd_kcontrol_new mi2s_config_controls[] = {
+ SOC_ENUM_EXT("PRI MI2S RX Format", mi2s_config_enum[0],
+ msm_dai_q6_mi2s_format_get,
+ msm_dai_q6_mi2s_format_put),
+ SOC_ENUM_EXT("SEC RX Format", mi2s_config_enum[0],
+ msm_dai_q6_mi2s_format_get,
+ msm_dai_q6_mi2s_format_put),
+ SOC_ENUM_EXT("PRI MI2S TX Format", mi2s_config_enum[0],
+ msm_dai_q6_mi2s_format_get,
+ msm_dai_q6_mi2s_format_put),
+};
+
+static int msm_dai_q6_dai_mi2s_probe(struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+ struct snd_kcontrol *kcontrol = NULL;
+ int rc = 0;
+
+ if (mi2s_dai_data->rx_dai.mi2s_dai_data.port_config.i2s.channel_mode) {
+ kcontrol = snd_ctl_new1(&mi2s_config_controls[0],
+ &mi2s_dai_data->rx_dai.mi2s_dai_data);
+ rc = snd_ctl_add(dai->card->snd_card, kcontrol);
+
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(dai->dev, "%s: err add RX fmt ctl\n", __func__);
+ goto rtn;
+ }
+ }
+ if (mi2s_dai_data->tx_dai.mi2s_dai_data.port_config.i2s.channel_mode) {
+ rc = snd_ctl_add(dai->card->snd_card,
+ snd_ctl_new1(&mi2s_config_controls[2],
+ &mi2s_dai_data->tx_dai.mi2s_dai_data));
+
+ if (IS_ERR_VALUE(rc)) {
+ if (kcontrol)
+ snd_ctl_remove(dai->card->snd_card, kcontrol);
+ dev_err(dai->dev, "%s: err add TX fmt ctl\n", __func__);
+ }
+ }
+rtn:
+ return rc;
+}
+
+
+static int msm_dai_q6_dai_mi2s_remove(struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+ int rc;
+
+ /* If AFE port is still up, close it */
+ if (test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->rx_dai.mi2s_dai_data.status_mask)) {
+ rc = afe_close(MI2S_RX); /* can block */
+ if (IS_ERR_VALUE(rc))
+ dev_err(dai->dev, "fail to close MI2S_RX port\n");
+ clear_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->rx_dai.mi2s_dai_data.status_mask);
+ }
+ if (test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->tx_dai.mi2s_dai_data.status_mask)) {
+ rc = afe_close(MI2S_TX); /* can block */
+ if (IS_ERR_VALUE(rc))
+ dev_err(dai->dev, "fail to close MI2S_TX port\n");
+ clear_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->tx_dai.mi2s_dai_data.status_mask);
+ }
+ kfree(mi2s_dai_data);
+ snd_soc_unregister_dai(dai->dev);
+ return 0;
+}
+
+static int msm_dai_q6_mi2s_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+
+ dev_dbg(dai->dev, "%s: cnst list %p\n", __func__,
+ mi2s_dai_data->rate_constraint.list);
+
+ if (mi2s_dai_data->rate_constraint.list) {
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &mi2s_dai_data->rate_constraint);
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
+ &mi2s_dai_data->bitwidth_constraint);
+ }
+
+ return 0;
+}
+
+
+static int msm_mi2s_get_port_id(u32 mi2s_id, int stream, u16 *port_id)
+{
+ int ret = 0;
+
+ switch (stream) {
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ switch (mi2s_id) {
+ case MSM_PRIM_MI2S:
+ *port_id = MI2S_RX;
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+ break;
+ case SNDRV_PCM_STREAM_CAPTURE:
+ switch (mi2s_id) {
+ case MSM_PRIM_MI2S:
+ *port_id = MI2S_TX;
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+ pr_debug("%s: port_id = %x\n", __func__, *port_id);
+ return ret;
+}
+
+static int msm_dai_q6_mi2s_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+ struct msm_dai_q6_dai_data *dai_data =
+ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
+ &mi2s_dai_data->rx_dai.mi2s_dai_data :
+ &mi2s_dai_data->tx_dai.mi2s_dai_data);
+ u16 port_id = 0;
+ int rc = 0;
+
+ dev_dbg(dai->dev, "%s: device name %s dai id %x,port id = %x\n",
+ __func__, dai->name, dai->id, port_id);
+
+ if (msm_mi2s_get_port_id(dai->id, substream->stream,
+ &port_id) != 0) {
+ dev_err(dai->dev, "%s: Invalid Port ID\n", __func__);
+ return -EINVAL;
+ }
+
+ if (!test_bit(STATUS_PORT_STARTED, dai_data->status_mask)) {
+ /* PORT START should be set if prepare called
+ * in active state.
+ */
+ rc = afe_port_start(port_id, &dai_data->port_config,
+ dai_data->rate);
+
+ if (IS_ERR_VALUE(rc))
+ dev_err(dai->dev, "fail to open AFE port %x\n",
+ dai->id);
+ else
+ set_bit(STATUS_PORT_STARTED,
+ dai_data->status_mask);
+ }
+ return rc;
+}
+
+static int msm_dai_q6_mi2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+ struct msm_dai_q6_mi2s_dai_config *mi2s_dai_config =
+ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
+ &mi2s_dai_data->rx_dai : &mi2s_dai_data->tx_dai);
+ struct msm_dai_q6_dai_data *dai_data = &mi2s_dai_config->mi2s_dai_data;
+
+ dai_data->channels = params_channels(params);
+ switch (dai_data->channels) {
+ case 8:
+ case 7:
+ if (mi2s_dai_config->pdata_mi2s_lines < AFE_PORT_I2S_8CHS)
+ goto error_invalid_data;
+ dai_data->port_config.i2s.channel_mode = AFE_PORT_I2S_8CHS;
+ break;
+ case 6:
+ case 5:
+ if (mi2s_dai_config->pdata_mi2s_lines < AFE_PORT_I2S_6CHS)
+ goto error_invalid_data;
+ dai_data->port_config.i2s.channel_mode = AFE_PORT_I2S_6CHS;
+ break;
+ case 4:
+ case 3:
+ if (mi2s_dai_config->pdata_mi2s_lines < AFE_PORT_I2S_QUAD01)
+ goto error_invalid_data;
+ if (mi2s_dai_config->pdata_mi2s_lines == AFE_PORT_I2S_QUAD23)
+ dai_data->port_config.i2s.channel_mode =
+ mi2s_dai_config->pdata_mi2s_lines;
+ else
+ dai_data->port_config.i2s.channel_mode =
+ AFE_PORT_I2S_QUAD01;
+ break;
+ case 2:
+ case 1:
+ if (mi2s_dai_config->pdata_mi2s_lines < AFE_PORT_I2S_SD0)
+ goto error_invalid_data;
+ switch (mi2s_dai_config->pdata_mi2s_lines) {
+ case AFE_PORT_I2S_SD0:
+ case AFE_PORT_I2S_SD1:
+ case AFE_PORT_I2S_SD2:
+ case AFE_PORT_I2S_SD3:
+ dai_data->port_config.i2s.channel_mode =
+ mi2s_dai_config->pdata_mi2s_lines;
+ break;
+ case AFE_PORT_I2S_QUAD01:
+ case AFE_PORT_I2S_6CHS:
+ case AFE_PORT_I2S_8CHS:
+ dai_data->port_config.i2s.channel_mode =
+ AFE_PORT_I2S_SD0;
+ break;
+ case AFE_PORT_I2S_QUAD23:
+ dai_data->port_config.i2s.channel_mode =
+ AFE_PORT_I2S_SD2;
+ break;
+ }
+ if (dai_data->channels == 2)
+ dai_data->port_config.i2s.mono_stereo =
+ MSM_AFE_CH_STEREO;
+ else
+ dai_data->port_config.i2s.mono_stereo = MSM_AFE_MONO;
+ break;
+ default:
+ goto error_invalid_data;
+ }
+ dai_data->rate = params_rate(params);
+ dai_data->port_config.i2s.bit_width = 16;
+ dai_data->bitwidth = 16;
+ dai_data->port_config.i2s.i2s_cfg_minor_version =
+ AFE_API_VERSION_I2S_CONFIG;
+ dai_data->port_config.i2s.sample_rate = dai_data->rate;
+ if (!mi2s_dai_data->rate_constraint.list) {
+ mi2s_dai_data->rate_constraint.list = &dai_data->rate;
+ mi2s_dai_data->bitwidth_constraint.list = &dai_data->bitwidth;
+ }
+
+ pr_debug("%s: dai_data->channels = %d, line = %d\n"
+ ",mono_stereo =%x sample rate = %x\n", __func__,
+ dai_data->channels, dai_data->port_config.i2s.channel_mode,
+ dai_data->port_config.i2s.mono_stereo, dai_data->rate);
+ return 0;
+error_invalid_data:
+ pr_debug("%s: dai_data->channels = %d, line = %d\n", __func__,
+ dai_data->channels, dai_data->port_config.i2s.channel_mode);
+ return -EINVAL;
+}
+
+
+static int msm_dai_q6_mi2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+
+ if (test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->rx_dai.mi2s_dai_data.status_mask) ||
+ test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->tx_dai.mi2s_dai_data.status_mask)) {
+ dev_err(dai->dev, "%s: err chg i2s mode while dai running",
+ __func__);
+ return -EPERM;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ mi2s_dai_data->rx_dai.mi2s_dai_data.port_config.i2s.ws_src = 1;
+ mi2s_dai_data->tx_dai.mi2s_dai_data.port_config.i2s.ws_src = 1;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ mi2s_dai_data->rx_dai.mi2s_dai_data.port_config.i2s.ws_src = 0;
+ mi2s_dai_data->tx_dai.mi2s_dai_data.port_config.i2s.ws_src = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void msm_dai_q6_mi2s_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm_dai_q6_mi2s_dai_data *mi2s_dai_data =
+ dev_get_drvdata(dai->dev);
+ struct msm_dai_q6_dai_data *dai_data =
+ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
+ &mi2s_dai_data->rx_dai.mi2s_dai_data :
+ &mi2s_dai_data->tx_dai.mi2s_dai_data);
+ u16 port_id = 0;
+ int rc = 0;
+
+ if (msm_mi2s_get_port_id(dai->id, substream->stream,
+ &port_id) != 0) {
+ dev_err(dai->dev, "%s: Invalid Port ID\n", __func__);
+ }
+
+ dev_dbg(dai->dev, "%s: device name %s port id = %x\n",
+ __func__, dai->name, port_id);
+
+ if (test_bit(STATUS_PORT_STARTED, dai_data->status_mask)) {
+ rc = afe_close(port_id);
+ if (IS_ERR_VALUE(rc))
+ dev_err(dai->dev, "fail to close AFE port\n");
+ clear_bit(STATUS_PORT_STARTED, dai_data->status_mask);
+ }
+
+ if (!test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->rx_dai.mi2s_dai_data.status_mask) &&
+ !test_bit(STATUS_PORT_STARTED,
+ mi2s_dai_data->rx_dai.mi2s_dai_data.status_mask)) {
+ mi2s_dai_data->rate_constraint.list = NULL;
+ mi2s_dai_data->bitwidth_constraint.list = NULL;
+ }
+}
+
+static struct snd_soc_dai_ops msm_dai_q6_mi2s_ops = {
+ .startup = msm_dai_q6_mi2s_startup,
+ .prepare = msm_dai_q6_mi2s_prepare,
+ .hw_params = msm_dai_q6_mi2s_hw_params,
+ .set_fmt = msm_dai_q6_mi2s_set_fmt,
+ .shutdown = msm_dai_q6_mi2s_shutdown,
+};
+
+/* Channel min and max are initialized base on platform data */
+static struct snd_soc_dai_driver msm_dai_q6_mi2s_dai = {
+ .playback = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .capture = {
+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &msm_dai_q6_mi2s_ops,
+ .probe = msm_dai_q6_dai_mi2s_probe,
+ .remove = msm_dai_q6_dai_mi2s_remove,
+};
+
+
+static int msm_dai_q6_mi2s_get_lineconfig(u16 sd_lines, u16 *config_ptr,
+ unsigned int *ch_cnt)
+{
+ u8 num_of_sd_lines;
+
+ num_of_sd_lines = num_of_bits_set(sd_lines);
+ switch (num_of_sd_lines) {
+ case 0:
+ pr_debug("%s: no line is assigned\n", __func__);
+ break;
+ case 1:
+ switch (sd_lines) {
+ case MSM_MI2S_SD0:
+ *config_ptr = AFE_PORT_I2S_SD0;
+ break;
+ case MSM_MI2S_SD1:
+ *config_ptr = AFE_PORT_I2S_SD1;
+ break;
+ case MSM_MI2S_SD2:
+ *config_ptr = AFE_PORT_I2S_SD2;
+ break;
+ case MSM_MI2S_SD3:
+ *config_ptr = AFE_PORT_I2S_SD3;
+ break;
+ default:
+ pr_err("%s: invalid SD line\n",
+ __func__);
+ goto error_invalid_data;
+ }
+ break;
+ case 2:
+ switch (sd_lines) {
+ case MSM_MI2S_SD0 | MSM_MI2S_SD1:
+ *config_ptr = AFE_PORT_I2S_QUAD01;
+ break;
+ case MSM_MI2S_SD2 | MSM_MI2S_SD3:
+ *config_ptr = AFE_PORT_I2S_QUAD23;
+ break;
+ default:
+ pr_err("%s: invalid SD line\n",
+ __func__);
+ goto error_invalid_data;
+ }
+ break;
+ case 3:
+ switch (sd_lines) {
+ case MSM_MI2S_SD0 | MSM_MI2S_SD1 | MSM_MI2S_SD2:
+ *config_ptr = AFE_PORT_I2S_6CHS;
+ break;
+ default:
+ pr_err("%s: invalid SD lines\n",
+ __func__);
+ goto error_invalid_data;
+ }
+ break;
+ case 4:
+ switch (sd_lines) {
+ case MSM_MI2S_SD0 | MSM_MI2S_SD1 | MSM_MI2S_SD2 | MSM_MI2S_SD3:
+ *config_ptr = AFE_PORT_I2S_8CHS;
+ break;
+ default:
+ pr_err("%s: invalid SD lines\n",
+ __func__);
+ goto error_invalid_data;
+ }
+ break;
+ default:
+ pr_err("%s: invalid SD lines\n", __func__);
+ goto error_invalid_data;
+ }
+ *ch_cnt = num_of_sd_lines;
+ return 0;
+
+error_invalid_data:
+ return -EINVAL;
+}
+
+static int msm_dai_q6_mi2s_platform_data_validation(
+ struct platform_device *pdev, struct snd_soc_dai_driver *dai_driver)
+{
+ struct msm_dai_q6_mi2s_dai_data *dai_data = dev_get_drvdata(&pdev->dev);
+ struct msm_mi2s_pdata *mi2s_pdata =
+ (struct msm_mi2s_pdata *) pdev->dev.platform_data;
+ unsigned int ch_cnt;
+ int rc = 0;
+ u16 sd_line;
+
+ if (mi2s_pdata == NULL) {
+ pr_err("%s: mi2s_pdata NULL", __func__);
+ return -EINVAL;
+ }
+
+ rc = msm_dai_q6_mi2s_get_lineconfig(mi2s_pdata->rx_sd_lines,
+ &sd_line, &ch_cnt);
+
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(&pdev->dev, "invalid MI2S RX sd line config\n");
+ goto rtn;
+ }
+
+ if (ch_cnt) {
+ dai_data->rx_dai.mi2s_dai_data.port_config.i2s.channel_mode =
+ mi2s_pdata->rx_sd_lines;
+ dai_data->rx_dai.pdata_mi2s_lines = mi2s_pdata->rx_sd_lines;
+ dai_driver->playback.channels_min = 1;
+ dai_driver->playback.channels_max = ch_cnt << 1;
+ } else {
+ dai_driver->playback.channels_min = 0;
+ dai_driver->playback.channels_max = 0;
+ }
+ rc = msm_dai_q6_mi2s_get_lineconfig(mi2s_pdata->tx_sd_lines,
+ &sd_line, &ch_cnt);
+
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(&pdev->dev, "invalid MI2S TX sd line config\n");
+ goto rtn;
+ }
+
+ if (ch_cnt) {
+ dai_data->tx_dai.mi2s_dai_data.port_config.i2s.channel_mode =
+ mi2s_pdata->tx_sd_lines;
+ dai_data->tx_dai.pdata_mi2s_lines = mi2s_pdata->tx_sd_lines;
+ dai_driver->capture.channels_min = 1;
+ dai_driver->capture.channels_max = ch_cnt << 1;
+ } else {
+ dai_driver->capture.channels_min = 0;
+ dai_driver->capture.channels_max = 0;
+ }
+
+ dev_dbg(&pdev->dev, "%s: playback sdline %x capture sdline %x\n",
+ __func__, dai_data->rx_dai.pdata_mi2s_lines,
+ dai_data->tx_dai.pdata_mi2s_lines);
+ dev_dbg(&pdev->dev, "%s: playback ch_max %d capture ch_mx %d\n",
+ __func__, dai_driver->playback.channels_max,
+ dai_driver->capture.channels_max);
+rtn:
+ return rc;
+}
+
+static __devinit int msm_dai_q6_mi2s_dev_probe(struct platform_device *pdev)
+{
+ struct msm_dai_q6_mi2s_dai_data *dai_data;
+ const char *q6_mi2s_dev_id = "qcom,msm-dai-q6-mi2s-dev-id";
+ u32 tx_line = 0;
+ u32 rx_line = 0;
+ u32 mi2s_intf = 0;
+ struct msm_mi2s_pdata *mi2s_pdata;
+ int rc = 0;
+
+
+ rc = of_property_read_u32(pdev->dev.of_node, q6_mi2s_dev_id,
+ &mi2s_intf);
+ if (rc) {
+ dev_err(&pdev->dev,
+ "%s: missing %x in dt node\n", __func__, mi2s_intf);
+ return rc;
+ }
+
+ if (mi2s_intf > MSM_QUAD_MI2S) {
+ dev_err(&pdev->dev, "%s: Invalid MI2S ID from Device Tree\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (mi2s_intf == MSM_PRIM_MI2S) {
+ dev_set_name(&pdev->dev, "%s.%d", "msm-dai-q6-mi2s",
+ MSM_PRIM_MI2S);
+ pdev->id = MSM_PRIM_MI2S;
+ }
+
+ mi2s_pdata = kzalloc(sizeof(struct msm_mi2s_pdata), GFP_KERNEL);
+ if (!mi2s_pdata) {
+ dev_err(&pdev->dev, "fail to allocate mi2s_pdata data\n");
+ rc = -ENOMEM;
+ goto rtn;
+ }
+
+ dev_dbg(&pdev->dev, "dev name %s dev id %x\n", dev_name(&pdev->dev),
+ pdev->id);
+
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,msm-mi2s-rx-lines",
+ &rx_line);
+ if (rc) {
+ dev_err(&pdev->dev, "%s: Rx line from DT file %s\n", __func__,
+ "qcom,msm-mi2s-rx-lines");
+ return rc;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,msm-mi2s-tx-lines",
+ &tx_line);
+ if (rc) {
+ dev_err(&pdev->dev, "%s: Tx line from DT file %s\n", __func__,
+ "qcom,msm-mi2s-tx-lines");
+ return rc;
+ }
+ dev_dbg(&pdev->dev, "dev name %s Rx line %x , Tx ine %x\n",
+ dev_name(&pdev->dev), rx_line, tx_line);
+ mi2s_pdata->rx_sd_lines = rx_line;
+ mi2s_pdata->tx_sd_lines = tx_line;
+ dai_data = kzalloc(sizeof(struct msm_dai_q6_mi2s_dai_data),
+ GFP_KERNEL);
+ if (!dai_data) {
+ dev_err(&pdev->dev, "fail to allocate dai data\n");
+ rc = -ENOMEM;
+ goto rtn;
+ } else
+ dev_set_drvdata(&pdev->dev, dai_data);
+ pdev->dev.platform_data = mi2s_pdata;
+ rc = msm_dai_q6_mi2s_platform_data_validation(pdev,
+ &msm_dai_q6_mi2s_dai);
+ if (IS_ERR_VALUE(rc))
+ goto err_pdata;
+ dai_data->rate_constraint.count = 1;
+ dai_data->bitwidth_constraint.count = 1;
+ rc = snd_soc_register_dai(&pdev->dev, &msm_dai_q6_mi2s_dai);
+ if (IS_ERR_VALUE(rc))
+ goto err_pdata;
+ return 0;
+err_pdata:
+ dev_err(&pdev->dev, "fail to msm_dai_q6_mi2s_dev_probe\n");
+ kfree(dai_data);
+rtn:
+ return rc;
+}
+
+static __devexit int msm_dai_q6_mi2s_dev_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_dai(&pdev->dev);
+ return 0;
+}
+
static int msm_dai_q6_dev_probe(struct platform_device *pdev)
{
int rc, id;
@@ -1173,10 +1818,14 @@
&msm_dai_q6_slimbus_tx_dai);
break;
case SLIMBUS_1_RX:
+ case SLIMBUS_3_RX:
+ case SLIMBUS_4_RX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_rx_dai);
break;
case SLIMBUS_1_TX:
+ case SLIMBUS_3_TX:
+ case SLIMBUS_4_TX:
rc = snd_soc_register_dai(&pdev->dev,
&msm_dai_q6_slimbus_1_tx_dai);
break;
@@ -1267,6 +1916,57 @@
},
};
+static int msm_dai_mi2s_q6_probe(struct platform_device *pdev)
+{
+ int rc;
+ rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+ if (rc) {
+ dev_err(&pdev->dev, "%s: failed to add child nodes, rc=%d\n",
+ __func__, rc);
+ } else
+ dev_dbg(&pdev->dev, "%s: added child node\n", __func__);
+ return rc;
+}
+
+static int msm_dai_mi2s_q6_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id msm_dai_mi2s_dt_match[] = {
+ { .compatible = "qcom,msm-dai-mi2s", },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, msm_dai_mi2s_dt_match);
+
+static struct platform_driver msm_dai_mi2s_q6 = {
+ .probe = msm_dai_mi2s_q6_probe,
+ .remove = msm_dai_mi2s_q6_remove,
+ .driver = {
+ .name = "msm-dai-mi2s",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_dai_mi2s_dt_match,
+ },
+};
+
+static const struct of_device_id msm_dai_q6_mi2s_dev_dt_match[] = {
+ { .compatible = "qcom,msm-dai-q6-mi2s", },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, msm_dai_q6_mi2s_dev_dt_match);
+
+static struct platform_driver msm_dai_q6_mi2s_driver = {
+ .probe = msm_dai_q6_mi2s_dev_probe,
+ .remove = __devexit_p(msm_dai_q6_mi2s_dev_remove),
+ .driver = {
+ .name = "msm-dai-q6-mi2s",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_dai_q6_mi2s_dev_dt_match,
+ },
+};
+
static int __init msm_dai_q6_init(void)
{
int rc;
@@ -1279,26 +1979,44 @@
if (rc) {
pr_err("%s: fail to register cpu dai driver\n", __func__);
- platform_driver_unregister(&msm_auxpcm_dev_driver);
- goto fail;
+ goto aux_pcm_resource_fail;
}
rc = platform_driver_register(&msm_dai_q6);
if (rc) {
pr_err("%s: fail to register dai q6 driver", __func__);
- platform_driver_unregister(&msm_auxpcm_dev_driver);
- platform_driver_unregister(&msm_auxpcm_resource_driver);
- goto fail;
+ goto dai_q6_fail;
}
rc = platform_driver_register(&msm_dai_q6_dev);
if (rc) {
pr_err("%s: fail to register dai q6 dev driver", __func__);
- platform_driver_unregister(&msm_dai_q6);
- platform_driver_unregister(&msm_auxpcm_dev_driver);
- platform_driver_unregister(&msm_auxpcm_resource_driver);
- goto fail;
+ goto dai_q6_dev_fail;
}
+
+ rc = platform_driver_register(&msm_dai_q6_mi2s_driver);
+ if (rc) {
+ pr_err("%s: fail to register dai MI2S dev drv\n", __func__);
+ goto dai_q6_mi2s_drv_fail;
+ }
+
+ rc = platform_driver_register(&msm_dai_mi2s_q6);
+ if (rc) {
+ pr_err("%s: fail to register dai MI2S\n", __func__);
+ goto dai_mi2s_q6_fail;
+ }
+ return rc;
+
+dai_mi2s_q6_fail:
+ platform_driver_unregister(&msm_dai_q6_mi2s_driver);
+dai_q6_mi2s_drv_fail:
+ platform_driver_unregister(&msm_dai_q6_dev);
+dai_q6_dev_fail:
+ platform_driver_unregister(&msm_dai_q6);
+dai_q6_fail:
+ platform_driver_unregister(&msm_auxpcm_resource_driver);
+aux_pcm_resource_fail:
+ platform_driver_unregister(&msm_auxpcm_dev_driver);
fail:
return rc;
}
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
index af1e19c..1e6fc04 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
@@ -297,6 +297,7 @@
static int msm_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *soc_prtd = substream->private_data;
struct msm_audio *prtd;
int ret = 0;
@@ -314,8 +315,25 @@
kfree(prtd);
return -ENOMEM;
}
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
runtime->hw = msm_pcm_hardware_playback;
+ ret = q6asm_open_write(prtd->audio_client, FORMAT_LINEAR_PCM);
+ if (ret < 0) {
+ pr_err("%s: pcm out open failed\n", __func__);
+ q6asm_audio_client_free(prtd->audio_client);
+ kfree(prtd);
+ return -ENOMEM;
+ }
+
+ pr_debug("%s: session ID %d\n", __func__,
+ prtd->audio_client->session);
+ prtd->session_id = prtd->audio_client->session;
+ msm_pcm_routing_reg_phy_stream(soc_prtd->dai_link->be_id,
+ prtd->session_id, substream->stream);
+ prtd->cmd_ack = 1;
+
+ }
+ /* Capture path */
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = msm_pcm_hardware_capture;
else {
@@ -601,25 +619,15 @@
struct audio_buffer *buf;
int dir, ret;
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dir = IN;
- pr_debug("%s Opening %d-ch PCM Write stream\n",
- __func__, params_channels(params));
-
- ret = q6asm_open_write(prtd->audio_client, FORMAT_LINEAR_PCM);
- if (ret < 0) {
- pr_err("%s: pcm out open failed\n", __func__);
- q6asm_audio_client_free(prtd->audio_client);
- kfree(prtd);
- return -ENOMEM;
- }
- } else {
+ else {
dir = OUT;
pr_debug("%s Opening %d-ch PCM read stream\n",
__func__, params_channels(params));
ret = q6asm_open_read(prtd->audio_client, FORMAT_LINEAR_PCM);
if (ret < 0) {
- pr_err("%s: pcm in open failed\n", __func__);
+ pr_err("%s: q6asm_open_read failed\n", __func__);
q6asm_audio_client_free(prtd->audio_client);
prtd->audio_client = NULL;
return -ENOMEM;
@@ -631,10 +639,7 @@
msm_pcm_routing_reg_phy_stream(soc_prtd->dai_link->be_id,
prtd->session_id, substream->stream);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- prtd->cmd_ack = 1;
- pr_debug("%s: before buf alloc\n", __func__);
ret = q6asm_audio_client_buf_alloc_contiguous(dir,
prtd->audio_client,
runtime->hw.period_bytes_min,
@@ -644,7 +649,6 @@
ret);
return -ENOMEM;
}
- pr_debug("%s: after buf alloc\n", __func__);
buf = prtd->audio_client->port[dir].buf;
if (buf == NULL || buf[0].data == NULL)
return -ENOMEM;
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
index 3db5418..2e0c229 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
@@ -138,6 +138,7 @@
{ SLIMBUS_4_RX, 0, 0, 0, 0, 0},
{ SLIMBUS_4_TX, 0, 0, 0, 0, 0},
{ SLIMBUS_3_RX, 0, 0, 0, 0, 0},
+ { SLIMBUS_3_TX, 0, 0, 0, 0, 0},
{ SLIMBUS_EXTPROC_RX, 0, 0, 0, 0, 0},
{ SLIMBUS_EXTPROC_RX, 0, 0, 0, 0, 0},
{ SLIMBUS_EXTPROC_RX, 0, 0, 0, 0, 0},
@@ -1351,6 +1352,9 @@
SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_MI2S_RX,
MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer,
msm_routing_put_port_mixer),
+ SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_RX,
+ MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer,
+ msm_routing_put_port_mixer),
};
static const struct snd_kcontrol_new fm_switch_mixer_controls =
@@ -1581,6 +1585,18 @@
0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIM0_UL_HL", "SLIMBUS0_HOSTLESS Capture",
0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SLIM1_UL_HL", "SLIMBUS1_HOSTLESS Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SLIM3_DL_HL", "SLIMBUS3_HOSTLESS Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SLIM3_UL_HL", "SLIMBUS3_HOSTLESS Capture",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SLIM4_DL_HL", "SLIMBUS4_HOSTLESS Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("SLIM4_UL_HL", "SLIMBUS4_HOSTLESS Capture",
+ 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("INTFM_DL_HL", "INT_FM_HOSTLESS Playback",
0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("INTFM_UL_HL", "INT_FM_HOSTLESS Capture",
@@ -1595,6 +1611,9 @@
SND_SOC_DAPM_AIF_OUT("MI2S_UL_HL", "MI2S_TX_HOSTLESS Capture",
0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("MI2S_DL_HL", "MI2S_RX_HOSTLESS Playback",
+ 0, 0, 0, 0),
+
/* Backend AIF */
/* Stream name equals to backend dai link stream name
*/
@@ -1641,10 +1660,17 @@
SND_SOC_DAPM_AIF_IN("SLIMBUS_1_TX", "Slimbus1 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("STUB_1_TX", "Stub1 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_3_RX", "Slimbus3 Playback", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("SLIMBUS_3_TX", "Slimbus3 Capture", 0, 0, 0, 0),
/* Switch Definitions */
SND_SOC_DAPM_SWITCH("SLIMBUS_DL_HL", SND_SOC_NOPM, 0, 0,
&fm_switch_mixer_controls),
+ SND_SOC_DAPM_SWITCH("SLIMBUS1_DL_HL", SND_SOC_NOPM, 0, 0,
+ &fm_switch_mixer_controls),
+ SND_SOC_DAPM_SWITCH("SLIMBUS3_DL_HL", SND_SOC_NOPM, 0, 0,
+ &fm_switch_mixer_controls),
+ SND_SOC_DAPM_SWITCH("SLIMBUS4_DL_HL", SND_SOC_NOPM, 0, 0,
+ &fm_switch_mixer_controls),
SND_SOC_DAPM_SWITCH("PCM_RX_DL_HL", SND_SOC_NOPM, 0, 0,
&pcm_rx_switch_mixer_controls),
/* Mixer definitions */
@@ -1899,11 +1925,22 @@
{"VOIP_UL", NULL, "Voip_Tx Mixer"},
{"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"},
{"SLIMBUS_0_RX", NULL, "SLIMBUS_DL_HL"},
+ {"SLIMBUS1_DL_HL", "Switch", "SLIM1_DL_HL"},
+ {"SLIMBUS_1_RX", NULL, "SLIMBUS1_DL_HL"},
+ {"SLIMBUS3_DL_HL", "Switch", "SLIM3_DL_HL"},
+ {"SLIMBUS_3_RX", NULL, "SLIMBUS3_DL_HL"},
+ {"SLIMBUS4_DL_HL", "Switch", "SLIM4_DL_HL"},
+ {"SLIMBUS_4_RX", NULL, "SLIMBUS4_DL_HL"},
{"SLIM0_UL_HL", NULL, "SLIMBUS_0_TX"},
+ {"SLIM1_UL_HL", NULL, "SLIMBUS_1_TX"},
+ {"SLIM3_UL_HL", NULL, "SLIMBUS_3_TX"},
+ {"SLIM4_UL_HL", NULL, "SLIMBUS_4_TX"},
{"INT_FM_RX", NULL, "INTFM_DL_HL"},
{"INTFM_UL_HL", NULL, "INT_FM_TX"},
{"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"},
{"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"},
+ {"MI2S_RX", NULL, "MI2S_DL_HL"},
+ {"MI2S_UL_HL", NULL, "MI2S_TX"},
{"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"},
{"PCM_RX", NULL, "PCM_RX_DL_HL"},
{"MI2S_UL_HL", NULL, "MI2S_TX"},
@@ -1932,6 +1969,9 @@
{"SLIMBUS_1_RX Mixer", "Voice Stub", "VOICE_STUB_DL"},
{"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Mixer"},
{"INTERNAL_BT_SCO_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"},
+ {"MI2S_RX_Voice Mixer", "CSVoice", "CS-VOICE_DL1"},
+ {"MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"},
+ {"MI2S_RX", NULL, "MI2S_RX_Voice Mixer"},
{"MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"},
{"MI2S_RX", NULL, "MI2S_RX_Voice Mixer"},
@@ -1954,17 +1994,24 @@
{"SEC_I2S_RX", NULL, "SEC_I2S_RX Port Mixer"},
{"MI2S_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"},
+ {"MI2S_RX Port Mixer", "MI2S_TX", "MI2S_TX"},
{"MI2S_RX", NULL, "MI2S_RX Port Mixer"},
/* Backend Enablement */
{"BE_OUT", NULL, "PRI_I2S_RX"},
{"BE_OUT", NULL, "SEC_I2S_RX"},
{"BE_OUT", NULL, "SLIMBUS_0_RX"},
+ {"BE_OUT", NULL, "SLIMBUS_1_RX"},
+ {"BE_OUT", NULL, "SLIMBUS_3_RX"},
+ {"BE_OUT", NULL, "SLIMBUS_4_RX"},
{"BE_OUT", NULL, "HDMI"},
{"BE_OUT", NULL, "MI2S_RX"},
{"PRI_I2S_TX", NULL, "BE_IN"},
{"MI2S_TX", NULL, "BE_IN"},
{"SLIMBUS_0_TX", NULL, "BE_IN" },
+ {"SLIMBUS_1_TX", NULL, "BE_IN" },
+ {"SLIMBUS_3_TX", NULL, "BE_IN" },
+ {"SLIMBUS_4_TX", NULL, "BE_IN" },
{"BE_OUT", NULL, "INT_BT_SCO_RX"},
{"INT_BT_SCO_TX", NULL, "BE_IN"},
{"BE_OUT", NULL, "INT_FM_RX"},
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
index 32e18d8..261c359 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
@@ -39,6 +39,7 @@
#define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
#define LPASS_BE_STUB_1_TX "STUB_1_TX"
#define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
+#define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
#define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
#define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
@@ -90,6 +91,7 @@
MSM_BACKEND_DAI_SLIMBUS_4_RX,
MSM_BACKEND_DAI_SLIMBUS_4_TX,
MSM_BACKEND_DAI_SLIMBUS_3_RX,
+ MSM_BACKEND_DAI_SLIMBUS_3_TX,
MSM_BACKEND_DAI_EXTPROC_RX,
MSM_BACKEND_DAI_EXTPROC_TX,
MSM_BACKEND_DAI_EXTPROC_EC_TX,
diff --git a/sound/soc/msm/qdsp6v2/q6adm.c b/sound/soc/msm/qdsp6v2/q6adm.c
index 6acc136..cc69123 100644
--- a/sound/soc/msm/qdsp6v2/q6adm.c
+++ b/sound/soc/msm/qdsp6v2/q6adm.c
@@ -120,10 +120,10 @@
}
switch (payload[0]) {
case ADM_CMD_SET_PP_PARAMS_V5:
+ pr_debug("%s: ADM_CMD_SET_PP_PARAMS_V5\n",
+ __func__);
if (rtac_make_adm_callback(
payload, data->payload_size)) {
- pr_debug("%s: payload[0]: 0x%x\n",
- __func__, payload[0]);
break;
}
case ADM_CMD_DEVICE_CLOSE_V5:
@@ -148,6 +148,20 @@
wake_up(&this_adm.wait[index]);
}
break;
+ case ADM_CMD_GET_PP_PARAMS_V5:
+ pr_debug("%s: ADM_CMD_GET_PP_PARAMS_V5\n",
+ __func__);
+ /* Should only come here if there is an APR */
+ /* error or malformed APR packet. Otherwise */
+ /* response will be returned as */
+ /* ADM_CMDRSP_GET_PP_PARAMS_V5 */
+ if (payload[1] != 0) {
+ pr_err("%s: ADM get param error = %d, resuming\n",
+ __func__, payload[1]);
+ rtac_make_adm_callback(payload,
+ data->payload_size);
+ }
+ break;
default:
pr_err("%s: Unknown Cmd: 0x%x\n", __func__,
payload[0]);
@@ -174,8 +188,11 @@
wake_up(&this_adm.wait[index]);
}
break;
- case ADM_CMD_GET_PP_PARAMS_V5:
- pr_debug("%s: ADM_CMD_GET_PP_PARAMS_V5\n", __func__);
+ case ADM_CMDRSP_GET_PP_PARAMS_V5:
+ pr_debug("%s: ADM_CMDRSP_GET_PP_PARAMS_V5\n", __func__);
+ if (payload[0] != 0)
+ pr_err("%s: ADM_CMDRSP_GET_PP_PARAMS_V5 returned error = 0x%x\n",
+ __func__, payload[0]);
rtac_make_adm_callback(payload,
data->payload_size);
break;
@@ -669,6 +686,11 @@
for (i = 0; i < num_copps; i++)
send_adm_cal(port_id[i], path);
+ for (i = 0; i < num_copps; i++)
+ rtac_add_adm_device(port_id[i], atomic_read(&this_adm.copp_id
+ [afe_get_port_index(port_id[i])]),
+ path, session_id);
+
fail_cmd:
kfree(matrix_map);
return ret;
diff --git a/sound/soc/msm/qdsp6v2/q6afe.c b/sound/soc/msm/qdsp6v2/q6afe.c
index 4819e0a..8d8ff5d 100644
--- a/sound/soc/msm/qdsp6v2/q6afe.c
+++ b/sound/soc/msm/qdsp6v2/q6afe.c
@@ -630,6 +630,11 @@
int ret = 0;
int index = 0;
+ if (rx_port == MI2S_RX)
+ rx_port = AFE_PORT_ID_PRIMARY_MI2S_RX;
+ if (tx_port == MI2S_TX)
+ tx_port = AFE_PORT_ID_PRIMARY_MI2S_TX;
+
ret = afe_q6_interface_prepare();
if (ret != 0)
return ret;
diff --git a/sound/soc/msm/qdsp6v2/q6asm.c b/sound/soc/msm/qdsp6v2/q6asm.c
index 875bf47..fd340cf 100644
--- a/sound/soc/msm/qdsp6v2/q6asm.c
+++ b/sound/soc/msm/qdsp6v2/q6asm.c
@@ -34,7 +34,6 @@
#include <mach/memory.h>
#include <mach/debug_mm.h>
-#include <mach/peripheral-loader.h>
#include <mach/qdsp6v2/audio_acdb.h>
#include <mach/qdsp6v2/rtac.h>
#include <mach/msm_subsystem_map.h>
@@ -933,6 +932,10 @@
__func__, payload[0], payload[1]);
if (data->opcode == APR_BASIC_RSP_RESULT) {
token = data->token;
+ if (payload[1] != 0) {
+ pr_err("%s: cmd = 0x%x returned error = 0x%x\n",
+ __func__, payload[0], payload[1]);
+ }
switch (payload[0]) {
case ASM_STREAM_CMD_SET_PP_PARAMS_V2:
if (rtac_make_asm_callback(ac->session, payload,
@@ -966,6 +969,20 @@
ac->cb(data->opcode, data->token,
(uint32_t *)data->payload, ac->priv);
break;
+ case ASM_STREAM_CMD_GET_PP_PARAMS_V2:
+ pr_debug("%s: ASM_STREAM_CMD_GET_PP_PARAMS_V2\n",
+ __func__);
+ /* Should only come here if there is an APR */
+ /* error or malformed APR packet. Otherwise */
+ /* response will be returned as */
+ /* ASM_STREAM_CMDRSP_GET_PP_PARAMS_V2 */
+ if (payload[1] != 0) {
+ pr_err("%s: ASM get param error = %d, resuming\n",
+ __func__, payload[1]);
+ rtac_make_asm_callback(ac->session, payload,
+ data->payload_size);
+ }
+ break;
default:
pr_debug("%s:command[0x%x] not expecting rsp\n",
__func__, payload[0]);
@@ -1009,6 +1026,10 @@
break;
}
case ASM_STREAM_CMDRSP_GET_PP_PARAMS_V2:
+ pr_debug("%s: ASM_STREAM_CMDRSP_GET_PP_PARAMS_V2\n", __func__);
+ if (payload[0] != 0)
+ pr_err("%s: ASM_STREAM_CMDRSP_GET_PP_PARAMS_V2 returned error = 0x%x\n",
+ __func__, payload[0]);
rtac_make_asm_callback(ac->session, payload,
data->payload_size);
break;
diff --git a/sound/soc/msm/qdsp6v2/q6voice.c b/sound/soc/msm/qdsp6v2/q6voice.c
index 4e41c80..b799e59 100644
--- a/sound/soc/msm/qdsp6v2/q6voice.c
+++ b/sound/soc/msm/qdsp6v2/q6voice.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -21,6 +21,7 @@
#include <mach/qdsp6v2/audio_acdb.h>
#include <mach/qdsp6v2/rtac.h>
#include <mach/socinfo.h>
+#include <mach/qdsp6v2/apr_tal.h>
#include "sound/apr_audio-v2.h"
#include "sound/q6afe-v2.h"
@@ -83,6 +84,10 @@
static int32_t qdsp_cvs_callback(struct apr_client_data *data, void *priv);
static int32_t qdsp_cvp_callback(struct apr_client_data *data, void *priv);
+static int voice_send_set_widevoice_enable_cmd(struct voice_data *v);
+static int voice_send_set_pp_enable_cmd(struct voice_data *v,
+ uint32_t module_id, int enable);
+
static u16 voice_get_mvm_handle(struct voice_data *v)
{
if (v == NULL) {
@@ -204,6 +209,8 @@
static int voice_apr_register(void)
{
+ void *modem_mvm, *modem_cvs, *modem_cvp;
+
pr_debug("%s\n", __func__);
mutex_lock(&common.common_lock);
@@ -220,6 +227,18 @@
pr_err("%s: Unable to register MVM\n", __func__);
goto err;
}
+
+ /*
+ * Register with modem for SSR callback. The APR handle
+ * is not stored since it is used only to receive notifications
+ * and not for communication
+ */
+ modem_mvm = apr_register("MODEM", "MVM",
+ qdsp_mvm_callback,
+ 0xFFFFFFFF, &common);
+ if (modem_mvm == NULL)
+ pr_err("%s: Unable to register MVM for MODEM\n",
+ __func__);
}
if (common.apr_q6_cvs == NULL) {
@@ -233,6 +252,18 @@
pr_err("%s: Unable to register CVS\n", __func__);
goto err;
}
+ rtac_set_voice_handle(RTAC_CVS, common.apr_q6_cvs);
+ /*
+ * Register with modem for SSR callback. The APR handle
+ * is not stored since it is used only to receive notifications
+ * and not for communication
+ */
+ modem_cvs = apr_register("MODEM", "CVS",
+ qdsp_cvs_callback,
+ 0xFFFFFFFF, &common);
+ if (modem_cvs == NULL)
+ pr_err("%s: Unable to register CVS for MODEM\n",
+ __func__);
}
@@ -247,6 +278,18 @@
pr_err("%s: Unable to register CVP\n", __func__);
goto err;
}
+ rtac_set_voice_handle(RTAC_CVP, common.apr_q6_cvp);
+ /*
+ * Register with modem for SSR callback. The APR handle
+ * is not stored since it is used only to receive notifications
+ * and not for communication
+ */
+ modem_cvp = apr_register("MODEM", "CVP",
+ qdsp_cvp_callback,
+ 0xFFFFFFFF, &common);
+ if (modem_cvp == NULL)
+ pr_err("%s: Unable to register CVP for MODEM\n",
+ __func__);
}
@@ -258,6 +301,7 @@
if (common.apr_q6_cvs != NULL) {
apr_deregister(common.apr_q6_cvs);
common.apr_q6_cvs = NULL;
+ rtac_set_voice_handle(RTAC_CVS, NULL);
}
if (common.apr_q6_mvm != NULL) {
apr_deregister(common.apr_q6_mvm);
@@ -601,8 +645,9 @@
cvs_handle = voice_get_cvs_handle(v);
/* MVM, CVS sessions are destroyed only for Full control sessions. */
- if (is_voip_session(v->session_id)) {
- pr_debug("%s: MVM detach stream\n", __func__);
+ if (is_voip_session(v->session_id) || v->voc_state == VOC_ERROR) {
+ pr_debug("%s: MVM detach stream, VOC_STATE: %d\n", __func__,
+ v->voc_state);
/* Detach voice stream. */
detach_stream.hdr.hdr_field =
@@ -764,6 +809,114 @@
return -EINVAL;
}
+static int voice_send_set_widevoice_enable_cmd(struct voice_data *v)
+{
+ struct mvm_set_widevoice_enable_cmd mvm_set_wv_cmd;
+ int ret = 0;
+ void *apr_mvm;
+ u16 mvm_handle;
+
+ if (v == NULL) {
+ pr_err("%s: v is NULL\n", __func__);
+ return -EINVAL;
+ }
+ apr_mvm = common.apr_q6_mvm;
+
+ if (!apr_mvm) {
+ pr_err("%s: apr_mvm is NULL.\n", __func__);
+ return -EINVAL;
+ }
+ mvm_handle = voice_get_mvm_handle(v);
+
+ mvm_set_wv_cmd.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE),
+ APR_PKT_VER);
+ mvm_set_wv_cmd.hdr.pkt_size = APR_PKT_SIZE(APR_HDR_SIZE,
+ sizeof(mvm_set_wv_cmd) -
+ APR_HDR_SIZE);
+ mvm_set_wv_cmd.hdr.src_port = v->session_id;
+ mvm_set_wv_cmd.hdr.dest_port = mvm_handle;
+ mvm_set_wv_cmd.hdr.token = 0;
+ mvm_set_wv_cmd.hdr.opcode = VSS_IWIDEVOICE_CMD_SET_WIDEVOICE;
+
+ mvm_set_wv_cmd.vss_set_wv.enable = v->wv_enable;
+
+ v->mvm_state = CMD_STATUS_FAIL;
+ ret = apr_send_pkt(apr_mvm, (uint32_t *) &mvm_set_wv_cmd);
+ if (ret < 0) {
+ pr_err("Fail: sending mvm set widevoice enable,\n");
+ goto fail;
+ }
+ ret = wait_event_timeout(v->mvm_wait,
+ (v->mvm_state == CMD_STATUS_SUCCESS),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ pr_err("%s: wait_event timeout\n", __func__);
+ goto fail;
+ }
+ return 0;
+fail:
+ return -EINVAL;
+}
+
+static int voice_send_set_pp_enable_cmd(struct voice_data *v,
+ uint32_t module_id, int enable)
+{
+ struct cvs_set_pp_enable_cmd cvs_set_pp_cmd;
+ int ret = 0;
+ void *apr_cvs;
+ u16 cvs_handle;
+
+ if (v == NULL) {
+ pr_err("%s: v is NULL\n", __func__);
+ return -EINVAL;
+ }
+ apr_cvs = common.apr_q6_cvs;
+
+ if (!apr_cvs) {
+ pr_err("%s: apr_cvs is NULL.\n", __func__);
+ return -EINVAL;
+ }
+ cvs_handle = voice_get_cvs_handle(v);
+
+ cvs_set_pp_cmd.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
+ APR_HDR_LEN(APR_HDR_SIZE),
+ APR_PKT_VER);
+ cvs_set_pp_cmd.hdr.pkt_size = APR_PKT_SIZE(APR_HDR_SIZE,
+ sizeof(cvs_set_pp_cmd) -
+ APR_HDR_SIZE);
+ cvs_set_pp_cmd.hdr.src_port = v->session_id;
+ cvs_set_pp_cmd.hdr.dest_port = cvs_handle;
+ cvs_set_pp_cmd.hdr.token = 0;
+ cvs_set_pp_cmd.hdr.opcode = VSS_ICOMMON_CMD_SET_UI_PROPERTY;
+
+ cvs_set_pp_cmd.vss_set_pp.module_id = module_id;
+ cvs_set_pp_cmd.vss_set_pp.param_id = VOICE_PARAM_MOD_ENABLE;
+ cvs_set_pp_cmd.vss_set_pp.param_size = MOD_ENABLE_PARAM_LEN;
+ cvs_set_pp_cmd.vss_set_pp.reserved = 0;
+ cvs_set_pp_cmd.vss_set_pp.enable = enable;
+ cvs_set_pp_cmd.vss_set_pp.reserved_field = 0;
+ pr_debug("voice_send_set_pp_enable_cmd, module_id=%d, enable=%d\n",
+ module_id, enable);
+
+ v->cvs_state = CMD_STATUS_FAIL;
+ ret = apr_send_pkt(apr_cvs, (uint32_t *) &cvs_set_pp_cmd);
+ if (ret < 0) {
+ pr_err("Fail: sending cvs set pp enable,\n");
+ goto fail;
+ }
+ ret = wait_event_timeout(v->cvs_wait,
+ (v->cvs_state == CMD_STATUS_SUCCESS),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ pr_err("%s: wait_event timeout\n", __func__);
+ goto fail;
+ }
+ return 0;
+fail:
+ return -EINVAL;
+}
+
static int voice_set_dtx(struct voice_data *v)
{
int ret = 0;
@@ -2042,6 +2195,20 @@
voice_send_netid_timing_cmd(v);
}
+ /* enable widevoice if wv_enable is set */
+ if (v->wv_enable)
+ voice_send_set_widevoice_enable_cmd(v);
+
+ /* enable slowtalk if st_enable is set */
+ if (v->st_enable)
+ voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_ST,
+ v->st_enable);
+
+ voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_FENS,
+ v->fens_enable);
+
/* Start in-call music delivery if this feature is enabled */
if (v->music_info.play_enable)
voice_cvs_start_playback(v);
@@ -2050,6 +2217,10 @@
if (v->rec_info.rec_enable)
voice_cvs_start_record(v, v->rec_info.rec_mode);
+ rtac_add_voice(voice_get_cvs_handle(v),
+ voice_get_cvp_handle(v),
+ v->dev_rx.port_id, v->dev_tx.port_id,
+ v->session_id);
return 0;
@@ -2400,6 +2571,7 @@
goto fail;
}
+ rtac_remove_voice(voice_get_cvs_handle(v));
cvp_handle = 0;
voice_set_cvp_handle(v, cvp_handle);
return 0;
@@ -3155,6 +3327,7 @@
mutex_lock(&v->lock);
if (v->voc_state == VOC_RUN) {
+ rtac_remove_voice(voice_get_cvs_handle(v));
/* send cmd to dsp to disable vocproc */
ret = voice_send_disable_vocproc_cmd(v);
if (ret < 0) {
@@ -3198,16 +3371,36 @@
voice_send_cvp_register_cal_cmd(v);
voice_send_cvp_register_vol_cal_cmd(v);
- ret = voice_send_enable_vocproc_cmd(v);
- if (ret < 0) {
- pr_err("%s: enable vocproc failed %d\n", __func__, ret);
- goto fail;
- }
+ ret = voice_send_enable_vocproc_cmd(v);
+ if (ret < 0) {
+ pr_err("%s: enable vocproc failed %d\n", __func__, ret);
+ goto fail;
+ }
- /* Send tty mode if tty device is used */
- voice_send_tty_mode_cmd(v);
+ /* Send tty mode if tty device is used */
+ voice_send_tty_mode_cmd(v);
- v->voc_state = VOC_RUN;
+ /* enable widevoice if wv_enable is set */
+ if (v->wv_enable)
+ voice_send_set_widevoice_enable_cmd(v);
+
+ /* enable slowtalk */
+ if (v->st_enable)
+ voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_ST,
+ v->st_enable);
+
+ /* enable FENS */
+ if (v->fens_enable)
+ voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_FENS,
+ v->fens_enable);
+
+ rtac_add_voice(voice_get_cvs_handle(v),
+ voice_get_cvp_handle(v),
+ v->dev_rx.port_id, v->dev_tx.port_id,
+ v->session_id);
+ v->voc_state = VOC_RUN;
}
fail:
@@ -3370,7 +3563,8 @@
v->wv_enable = wv_enable;
mvm_handle = voice_get_mvm_handle(v);
-
+ if (mvm_handle != 0)
+ voice_send_set_widevoice_enable_cmd(v);
mutex_unlock(&v->lock);
@@ -3414,6 +3608,17 @@
else if (module_id == MODULE_ID_VOICE_MODULE_FENS)
v->fens_enable = enable;
+ if (v->voc_state == VOC_RUN) {
+ if (module_id == MODULE_ID_VOICE_MODULE_ST)
+ ret = voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_ST,
+ enable);
+ else if (module_id == MODULE_ID_VOICE_MODULE_FENS)
+ ret = voice_send_set_pp_enable_cmd(v,
+ MODULE_ID_VOICE_MODULE_FENS,
+ enable);
+ }
+
mutex_unlock(&v->lock);
return ret;
@@ -3548,7 +3753,9 @@
mutex_lock(&v->lock);
- if (v->voc_state == VOC_RUN) {
+ if (v->voc_state == VOC_RUN || v->voc_state == VOC_ERROR) {
+ pr_debug("%s: VOC_STATE: %d\n", __func__, v->voc_state);
+
ret = voice_destroy_vocproc(v);
if (ret < 0)
pr_err("%s: destroy voice failed\n", __func__);
@@ -3573,6 +3780,13 @@
mutex_lock(&v->lock);
+ if (v->voc_state == VOC_ERROR) {
+ pr_debug("%s: VOC in ERR state\n", __func__);
+
+ voice_destroy_mvm_cvs_session(v);
+ v->voc_state = VOC_INIT;
+ }
+
if ((v->voc_state == VOC_INIT) ||
(v->voc_state == VOC_RELEASE)) {
ret = voice_apr_register();
@@ -3663,6 +3877,7 @@
struct common_data *c = NULL;
struct voice_data *v = NULL;
int i = 0;
+ uint16_t session_id = 0;
if ((data == NULL) || (priv == NULL)) {
pr_err("%s: data or priv is NULL\n", __func__);
@@ -3671,6 +3886,36 @@
c = priv;
+ pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
+ data->payload_size, data->opcode);
+
+ if (data->opcode == RESET_EVENTS) {
+
+ if (data->reset_proc == APR_DEST_MODEM) {
+ pr_debug("%s: Received MODEM reset event\n", __func__);
+
+ session_id = voc_get_session_id(VOICE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+
+ session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+ } else {
+ pr_debug("%s: Reset event received in Voice service\n",
+ __func__);
+ apr_reset(c->apr_q6_mvm);
+ c->apr_q6_mvm = NULL;
+
+ /* Sub-system restart is applicable to all sessions. */
+ for (i = 0; i < MAX_VOC_SESSIONS; i++)
+ c->voice[i].mvm_handle = 0;
+ }
+ return 0;
+ }
+
pr_debug("%s: session_id 0x%x\n", __func__, data->dest_port);
v = voice_get_session(data->dest_port);
@@ -3680,23 +3925,6 @@
return -EINVAL;
}
- pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
- data->payload_size, data->opcode);
-
- if (data->opcode == RESET_EVENTS) {
- pr_debug("%s: Reset event received in Voice service\n",
- __func__);
-
- apr_reset(c->apr_q6_mvm);
- c->apr_q6_mvm = NULL;
-
- /* Sub-system restart is applicable to all sessions. */
- for (i = 0; i < MAX_VOC_SESSIONS; i++)
- c->voice[i].mvm_handle = 0;
-
- return 0;
- }
-
if (data->opcode == APR_BASIC_RSP_RESULT) {
if (data->payload_size) {
ptr = data->payload;
@@ -3781,6 +4009,7 @@
struct common_data *c = NULL;
struct voice_data *v = NULL;
int i = 0;
+ uint16_t session_id = 0;
if ((data == NULL) || (priv == NULL)) {
pr_err("%s: data or priv is NULL\n", __func__);
@@ -3790,6 +4019,35 @@
c = priv;
pr_debug("%s: session_id 0x%x\n", __func__, data->dest_port);
+ pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
+ data->payload_size, data->opcode);
+
+ if (data->opcode == RESET_EVENTS) {
+ if (data->reset_proc == APR_DEST_MODEM) {
+ pr_debug("%s: Received Modem reset event\n", __func__);
+
+ session_id = voc_get_session_id(VOICE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+
+ session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+ } else {
+ pr_debug("%s: Reset event received in Voice service\n",
+ __func__);
+
+ apr_reset(c->apr_q6_cvs);
+ c->apr_q6_cvs = NULL;
+
+ /* Sub-system restart is applicable to all sessions. */
+ for (i = 0; i < MAX_VOC_SESSIONS; i++)
+ c->voice[i].cvs_handle = 0;
+ }
+ return 0;
+ }
v = voice_get_session(data->dest_port);
if (v == NULL) {
@@ -3798,28 +4056,15 @@
return -EINVAL;
}
- pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
- data->payload_size, data->opcode);
-
- if (data->opcode == RESET_EVENTS) {
- pr_debug("%s: Reset event received in Voice service\n",
- __func__);
-
- apr_reset(c->apr_q6_cvs);
- c->apr_q6_cvs = NULL;
-
- /* Sub-system restart is applicable to all sessions. */
- for (i = 0; i < MAX_VOC_SESSIONS; i++)
- c->voice[i].cvs_handle = 0;
-
- return 0;
- }
-
if (data->opcode == APR_BASIC_RSP_RESULT) {
if (data->payload_size) {
ptr = data->payload;
pr_info("%x %x\n", ptr[0], ptr[1]);
+ if (ptr[1] != 0) {
+ pr_err("%s: cmd = 0x%x returned error = 0x%x\n",
+ __func__, ptr[0], ptr[1]);
+ }
/*response from CVS */
switch (ptr[0]) {
case VSS_ISTREAM_CMD_CREATE_PASSIVE_CONTROL_SESSION:
@@ -3856,6 +4101,24 @@
wake_up(&v->cvs_wait);
break;
case VOICE_CMD_SET_PARAM:
+ pr_debug("%s: VOICE_CMD_SET_PARAM\n", __func__);
+ rtac_make_voice_callback(RTAC_CVS, ptr,
+ data->payload_size);
+ break;
+ case VOICE_CMD_GET_PARAM:
+ pr_debug("%s: VOICE_CMD_GET_PARAM\n",
+ __func__);
+ /* Should only come here if there is an APR */
+ /* error or malformed APR packet. Otherwise */
+ /* response will be returned as */
+ /* VOICE_EVT_GET_PARAM_ACK */
+ if (ptr[1] != 0) {
+ pr_err("%s: CVP get param error = %d, resuming\n",
+ __func__, ptr[1]);
+ rtac_make_voice_callback(RTAC_CVP,
+ data->payload,
+ data->payload_size);
+ }
break;
default:
pr_debug("%s: cmd = 0x%x\n", __func__, ptr[0]);
@@ -3971,7 +4234,16 @@
pr_debug("Recd VSS_ISTREAM_EVT_NOT_READY\n");
} else if (data->opcode == VSS_ISTREAM_EVT_READY) {
pr_debug("Recd VSS_ISTREAM_EVT_READY\n");
- } else
+ } else if (data->opcode == VOICE_EVT_GET_PARAM_ACK) {
+ pr_debug("%s: VOICE_EVT_GET_PARAM_ACK\n", __func__);
+ ptr = data->payload;
+ if (ptr[0] != 0) {
+ pr_err("%s: VOICE_EVT_GET_PARAM_ACK returned error = 0x%x\n",
+ __func__, ptr[0]);
+ }
+ rtac_make_voice_callback(RTAC_CVS, data->payload,
+ data->payload_size);
+ } else
pr_err("Unknown opcode 0x%x\n", data->opcode);
fail:
@@ -3984,6 +4256,7 @@
struct common_data *c = NULL;
struct voice_data *v = NULL;
int i = 0;
+ uint16_t session_id = 0;
if ((data == NULL) || (priv == NULL)) {
pr_err("%s: data or priv is NULL\n", __func__);
@@ -3992,6 +4265,33 @@
c = priv;
+ if (data->opcode == RESET_EVENTS) {
+ if (data->reset_proc == APR_DEST_MODEM) {
+ pr_debug("%s: Received Modem reset event\n", __func__);
+
+ session_id = voc_get_session_id(VOICE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+
+ session_id = voc_get_session_id(VOLTE_SESSION_NAME);
+ v = voice_get_session(session_id);
+ if (v != NULL)
+ v->voc_state = VOC_ERROR;
+ } else {
+ pr_debug("%s: Reset event received in Voice service\n",
+ __func__);
+
+ apr_reset(c->apr_q6_cvp);
+ c->apr_q6_cvp = NULL;
+
+ /* Sub-system restart is applicable to all sessions. */
+ for (i = 0; i < MAX_VOC_SESSIONS; i++)
+ c->voice[i].cvp_handle = 0;
+ }
+ return 0;
+ }
+
v = voice_get_session(data->dest_port);
if (v == NULL) {
pr_err("%s: v is NULL\n", __func__);
@@ -3999,28 +4299,15 @@
return -EINVAL;
}
- pr_debug("%s: Payload Length = %d, opcode=%x\n", __func__,
- data->payload_size, data->opcode);
-
- if (data->opcode == RESET_EVENTS) {
- pr_debug("%s: Reset event received in Voice service\n",
- __func__);
-
- apr_reset(c->apr_q6_cvp);
- c->apr_q6_cvp = NULL;
-
- /* Sub-system restart is applicable to all sessions. */
- for (i = 0; i < MAX_VOC_SESSIONS; i++)
- c->voice[i].cvp_handle = 0;
-
- return 0;
- }
-
if (data->opcode == APR_BASIC_RSP_RESULT) {
if (data->payload_size) {
ptr = data->payload;
pr_info("%x %x\n", ptr[0], ptr[1]);
+ if (ptr[1] != 0) {
+ pr_err("%s: cmd = 0x%x returned error = 0x%x\n",
+ __func__, ptr[0], ptr[1]);
+ }
switch (ptr[0]) {
case VSS_IVOCPROC_CMD_CREATE_FULL_CONTROL_SESSION_V2:
/*response from CVP */
@@ -4052,6 +4339,24 @@
wake_up(&v->cvp_wait);
break;
case VOICE_CMD_SET_PARAM:
+ pr_debug("%s: VOICE_CMD_SET_PARAM\n", __func__);
+ rtac_make_voice_callback(RTAC_CVP, ptr,
+ data->payload_size);
+ break;
+ case VOICE_CMD_GET_PARAM:
+ pr_debug("%s: VOICE_CMD_GET_PARAM\n",
+ __func__);
+ /* Should only come here if there is an APR */
+ /* error or malformed APR packet. Otherwise */
+ /* response will be returned as */
+ /* VOICE_EVT_GET_PARAM_ACK */
+ if (ptr[1] != 0) {
+ pr_err("%s: CVP get param error = %d, resuming\n",
+ __func__, ptr[1]);
+ rtac_make_voice_callback(RTAC_CVP,
+ data->payload,
+ data->payload_size);
+ }
break;
default:
pr_debug("%s: not match cmd = 0x%x\n",
@@ -4059,6 +4364,15 @@
break;
}
}
+ } else if (data->opcode == VOICE_EVT_GET_PARAM_ACK) {
+ pr_debug("%s: VOICE_EVT_GET_PARAM_ACK\n", __func__);
+ ptr = data->payload;
+ if (ptr[0] != 0) {
+ pr_err("%s: VOICE_EVT_GET_PARAM_ACK returned error = 0x%x\n",
+ __func__, ptr[0]);
+ }
+ rtac_make_voice_callback(RTAC_CVP, data->payload,
+ data->payload_size);
}
return 0;
}
diff --git a/sound/soc/msm/qdsp6v2/q6voice.h b/sound/soc/msm/qdsp6v2/q6voice.h
index 9f82694..aef463f 100644
--- a/sound/soc/msm/qdsp6v2/q6voice.h
+++ b/sound/soc/msm/qdsp6v2/q6voice.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -67,6 +67,7 @@
VOC_RUN,
VOC_CHANGE,
VOC_RELEASE,
+ VOC_ERROR,
};
struct mem_buffer {
@@ -884,10 +885,6 @@
#define VSS_MEDIA_ID_4GV_WB_MODEM 0x00010FC4
/*CDMA EVRC-WB vocoder modem format */
-#define VOICE_CMD_SET_PARAM 0x00011006
-#define VOICE_CMD_GET_PARAM 0x00011007
-#define VOICE_EVT_GET_PARAM_ACK 0x00011008
-
#define VSS_IVOCPROC_CMD_CREATE_FULL_CONTROL_SESSION_V2 0x000112BF
struct vss_ivocproc_cmd_create_full_control_session_v2_t {