ASoC: wm8510 pll settings
When setting WM8510_MCLKDIV the pll was turned off.
When setting pll frequency you got twice the expected freq, because
the code calculated with postscaler of 8, but the hardware divide by 4.
Signed-off-by: Jonas Andersson <jonas@microbit.se>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/atmel/playpaq_wm8510.c b/sound/soc/atmel/playpaq_wm8510.c
index 43dd8ce..7065753 100644
--- a/sound/soc/atmel/playpaq_wm8510.c
+++ b/sound/soc/atmel/playpaq_wm8510.c
@@ -164,41 +164,41 @@
*/
switch (params_rate(params)) {
case 48000:
- pll_out = 12288000;
- mclk_div = WM8510_MCLKDIV_1;
- bclk = WM8510_BCLKDIV_8;
- break;
-
- case 44100:
- pll_out = 11289600;
- mclk_div = WM8510_MCLKDIV_1;
- bclk = WM8510_BCLKDIV_8;
- break;
-
- case 22050:
- pll_out = 11289600;
+ pll_out = 24576000;
mclk_div = WM8510_MCLKDIV_2;
bclk = WM8510_BCLKDIV_8;
break;
- case 16000:
- pll_out = 12288000;
- mclk_div = WM8510_MCLKDIV_3;
+ case 44100:
+ pll_out = 22579200;
+ mclk_div = WM8510_MCLKDIV_2;
bclk = WM8510_BCLKDIV_8;
break;
- case 11025:
- pll_out = 11289600;
+ case 22050:
+ pll_out = 22579200;
mclk_div = WM8510_MCLKDIV_4;
bclk = WM8510_BCLKDIV_8;
break;
- case 8000:
- pll_out = 12288000;
+ case 16000:
+ pll_out = 24576000;
mclk_div = WM8510_MCLKDIV_6;
bclk = WM8510_BCLKDIV_8;
break;
+ case 11025:
+ pll_out = 22579200;
+ mclk_div = WM8510_MCLKDIV_8;
+ bclk = WM8510_BCLKDIV_8;
+ break;
+
+ case 8000:
+ pll_out = 24576000;
+ mclk_div = WM8510_MCLKDIV_12;
+ bclk = WM8510_BCLKDIV_8;
+ break;
+
default:
pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
params_rate(params));