msm: acpuclock-7627: Add support of 1.4GHz for 8625
For 8625 2.0 PLL4 is capable to run at 1.4GHz. Add acpuclock
table for the same and also add support to dynamically
re-program the PLL4 assuming 801.6MHz jump is fine from
H/W perspective.
Change-Id: I3712907d4aa3f4c085f874652797e9e7d4203598
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-7627.c b/arch/arm/mach-msm/acpuclock-7627.c
index f9ff226..639cc94 100644
--- a/arch/arm/mach-msm/acpuclock-7627.c
+++ b/arch/arm/mach-msm/acpuclock-7627.c
@@ -38,11 +38,15 @@
#include "smd_private.h"
#include "acpuclock.h"
+#include "clock.h"
#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
+#define PLL4_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x378)
+#define PLL4_M_VAL_ADDR (MSM_CLK_CTL_BASE + 0x37C)
+#define PLL4_N_VAL_ADDR (MSM_CLK_CTL_BASE + 0x380)
#define POWER_COLLAPSE_KHZ 19200
@@ -67,6 +71,12 @@
const char *name;
};
+struct pll_config {
+ unsigned int l;
+ unsigned int m;
+ unsigned int n;
+};
+
static struct acpu_clk_src pll_clk[ACPU_PLL_END] = {
[ACPU_PLL_0] = { .name = "pll0_clk" },
[ACPU_PLL_1] = { .name = "pll1_clk" },
@@ -74,6 +84,13 @@
[ACPU_PLL_4] = { .name = "pll4_clk" },
};
+static struct pll_config pll4_cfg_tbl[] = {
+ { 36, 1, 2 }, /* 700.8 MHz */
+ { 52, 1, 2 }, /* 1008 MHz */
+ { 63, 0, 1 }, /* 1209.6 MHz */
+ { 73, 0, 1 }, /* 1401.6 MHz */
+};
+
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
@@ -91,15 +108,20 @@
unsigned int ahbclk_div;
int vdd;
unsigned int axiclk_khz;
+ struct pll_config *pll_rate;
unsigned long lpj; /* loops_per_jiffy */
/* Pointers in acpu_freq_tbl[] for max up/down steppings. */
struct clkctl_acpu_speed *down[ACPU_PLL_END];
struct clkctl_acpu_speed *up[ACPU_PLL_END];
};
+static bool dynamic_reprogram;
static struct clock_state drv_state = { 0 };
static struct clkctl_acpu_speed *acpu_freq_tbl;
+/* Switch to this when reprogramming PLL4 */
+static struct clkctl_acpu_speed *backup_s;
+
/*
* ACPU freq tables used for different PLLs frequency combinations. The
* correct table is selected during init.
@@ -119,7 +141,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 2, 133333, 2, 5, 160000 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627 with CDMA capable modem */
@@ -133,7 +155,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 2, 133333, 2, 5, 160000 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627 with GSM capable modem - PLL2 @ 800 */
@@ -147,7 +169,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 1, 133333, 2, 5, 160000 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627 with CDMA capable modem - PLL2 @ 800 */
@@ -161,7 +183,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 1, 133333, 2, 5, 160000 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 160000, 2, 6, 160000 },
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627a PLL2 @ 1200MHz with GSM capable modem */
@@ -176,7 +198,7 @@
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627a PLL2 @ 1200MHz with CDMA capable modem */
@@ -191,7 +213,7 @@
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 120000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627aa PLL4 @ 1008MHz with GSM capable modem */
@@ -206,7 +228,7 @@
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627aa PLL4 @ 1008MHz with CDMA capable modem */
@@ -221,7 +243,7 @@
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 8625 PLL4 @ 1209MHz with GSM capable modem */
@@ -235,7 +257,7 @@
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 0, 604800, ACPU_PLL_4, 6, 1, 75600, 3, 6, 160000 },
{ 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 8625 PLL4 @ 1209MHz with CDMA capable modem */
@@ -249,7 +271,40 @@
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 0, 604800, ACPU_PLL_4, 6, 1, 75600, 3, 6, 160000 },
{ 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
+};
+
+/* 8625 PLL4 @ 1401.6MHz with GSM capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_245_pll2_1200_pll4_1401[] = {
+ { 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 30720 },
+ { 0, 61440, ACPU_PLL_1, 1, 3, 7680, 3, 0, 61440 },
+ { 0, 122880, ACPU_PLL_1, 1, 1, 15360, 3, 1, 61440 },
+ { 1, 245760, ACPU_PLL_1, 1, 0, 30720, 3, 1, 61440 },
+ { 0, 300000, ACPU_PLL_2, 2, 3, 37500, 3, 2, 122880 },
+ { 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 2, 122880 },
+ { 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 3, 122880 },
+ { 0, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 4, 160000 },
+ { 1, 700800, ACPU_PLL_4, 6, 0, 87500, 3, 4, 160000, &pll4_cfg_tbl[0]},
+ { 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 5, 200000, &pll4_cfg_tbl[1]},
+ { 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 6, 200000, &pll4_cfg_tbl[2]},
+ { 1, 1401600, ACPU_PLL_4, 6, 0, 175000, 3, 7, 200000, &pll4_cfg_tbl[3]},
+ { 0 }
+};
+
+/* 8625 PLL4 @ 1401.6MHz with CDMA capable modem */
+static struct clkctl_acpu_speed pll0_960_pll1_196_pll2_1200_pll4_1401[] = {
+ { 0, 19200, ACPU_PLL_TCXO, 0, 0, 2400, 3, 0, 24576 },
+ { 0, 65536, ACPU_PLL_1, 1, 3, 8192, 3, 1, 49152 },
+ { 0, 98304, ACPU_PLL_1, 1, 1, 12288, 3, 2, 49152 },
+ { 1, 196608, ACPU_PLL_1, 1, 0, 24576, 3, 3, 98304 },
+ { 1, 320000, ACPU_PLL_0, 4, 2, 40000, 3, 2, 122880 },
+ { 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 3, 122880 },
+ { 0, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 4, 160000 },
+ { 1, 700800, ACPU_PLL_4, 6, 0, 87500, 3, 4, 160000, &pll4_cfg_tbl[0]},
+ { 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 5, 200000, &pll4_cfg_tbl[1]},
+ { 1, 1209600, ACPU_PLL_4, 6, 0, 151200, 3, 6, 200000, &pll4_cfg_tbl[2]},
+ { 1, 1401600, ACPU_PLL_4, 6, 0, 175000, 3, 7, 200000, &pll4_cfg_tbl[3]},
+ { 0 }
};
/* 8625 PLL4 @ 1152MHz with GSM capable modem */
@@ -263,7 +318,7 @@
{ 0, 576000, ACPU_PLL_4, 6, 1, 72000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1152000, ACPU_PLL_4, 6, 0, 144000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 8625 PLL4 @ 1115MHz with CDMA capable modem */
@@ -277,7 +332,7 @@
{ 0, 576000, ACPU_PLL_4, 6, 1, 72000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1152000, ACPU_PLL_4, 6, 0, 144000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
@@ -292,7 +347,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 2, 50000, 3, 4, 122880 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627a PLL2 @ 1200MHz with GSM capable modem */
@@ -307,7 +362,7 @@
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627a PLL2 @ 1200MHz with CDMA capable modem */
@@ -322,7 +377,7 @@
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 120000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 800000, ACPU_PLL_4, 6, 0, 100000, 3, 7, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627aa PLL4 @ 1008MHz with GSM capable modem */
@@ -337,7 +392,7 @@
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7627aa PLL4 @ 1008MHz with CDMA capable modem */
@@ -352,7 +407,7 @@
{ 0, 504000, ACPU_PLL_4, 6, 1, 63000, 3, 6, 160000 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 160000 },
{ 1, 1008000, ACPU_PLL_4, 6, 0, 126000, 3, 7, 200000},
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
/* 7625a PLL2 @ 1200MHz with GSM capable modem */
@@ -366,7 +421,7 @@
{ 0, 400000, ACPU_PLL_2, 2, 2, 50000, 3, 4, 122880 },
{ 1, 480000, ACPU_PLL_0, 4, 1, 60000, 3, 5, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 75000, 3, 6, 200000 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, {0, 0, 0, 0} }
+ { 0 }
};
#define PLL_CONFIG(m0, m1, m2, m4) { \
@@ -399,6 +454,8 @@
PLL_CONFIG(960, 196, 1200, 1209),
PLL_CONFIG(960, 245, 1200, 1152),
PLL_CONFIG(960, 196, 1200, 1152),
+ PLL_CONFIG(960, 245, 1200, 1401),
+ PLL_CONFIG(960, 196, 1200, 1401),
{ 0, 0, 0, 0, 0 }
};
@@ -439,6 +496,31 @@
}
#endif
+static void update_jiffies(int cpu, unsigned long loops)
+{
+#ifdef CONFIG_SMP
+ for_each_possible_cpu(cpu) {
+ per_cpu(cpu_data, cpu).loops_per_jiffy =
+ loops;
+ }
+#endif
+ /* Adjust the global one */
+ loops_per_jiffy = loops;
+}
+
+/* Assumes PLL4 is off and the acpuclock isn't sourced from PLL4 */
+static void acpuclk_config_pll4(struct pll_config *pll)
+{
+ /* Make sure write to disable PLL_4 has completed
+ * before reconfiguring that PLL. */
+ mb();
+ writel_relaxed(pll->l, PLL4_L_VAL_ADDR);
+ writel_relaxed(pll->m, PLL4_M_VAL_ADDR);
+ writel_relaxed(pll->n, PLL4_N_VAL_ADDR);
+ /* Make sure PLL is programmed before returning. */
+ mb();
+}
+
static int acpuclk_set_vdd_level(int vdd)
{
uint32_t current_vdd;
@@ -524,6 +606,7 @@
struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
int res, rc = 0;
unsigned int plls_enabled = 0, pll;
+ int delta;
if (reason == SETRATE_CPUFREQ)
mutex_lock(&drv_state.lock);
@@ -592,6 +675,61 @@
pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n",
strt_s->a11clk_khz, tgt_s->a11clk_khz);
+ delta = abs((int)(strt_s->a11clk_khz - tgt_s->a11clk_khz));
+
+ if (dynamic_reprogram) {
+ if (tgt_s->pll == ACPU_PLL_4) {
+ if (strt_s->pll == ACPU_PLL_4 ||
+ delta > drv_state.max_speed_delta_khz) {
+ /*
+ * Enable the backup PLL if required
+ * and switch to it.
+ */
+ clk_enable(pll_clk[backup_s->pll].clk);
+ acpuclk_set_div(backup_s);
+ }
+ /* Make sure PLL4 is off before reprogramming */
+ if ((plls_enabled & (1 << tgt_s->pll))) {
+ clk_disable(pll_clk[tgt_s->pll].clk);
+ plls_enabled &= (0 << tgt_s->pll);
+ }
+ acpuclk_config_pll4(tgt_s->pll_rate);
+ pll_clk[tgt_s->pll].clk->rate = tgt_s->a11clk_khz*1000;
+
+ } else if (strt_s->pll == ACPU_PLL_4) {
+ if (delta > drv_state.max_speed_delta_khz) {
+ /*
+ * Enable the bcackup PLL if required
+ * and switch to it.
+ */
+ clk_enable(pll_clk[backup_s->pll].clk);
+ acpuclk_set_div(backup_s);
+ }
+ }
+
+ if (!(plls_enabled & (1 << tgt_s->pll))) {
+ rc = clk_enable(pll_clk[tgt_s->pll].clk);
+ if (rc < 0) {
+ pr_err("PLL%d enable failed (%d)\n",
+ tgt_s->pll, rc);
+ goto out;
+ }
+ plls_enabled |= 1 << tgt_s->pll;
+ }
+ acpuclk_set_div(tgt_s);
+ drv_state.current_speed = tgt_s;
+ /* Re-adjust lpj for the new clock speed. */
+ update_jiffies(cpu, cur_s->lpj);
+
+ /* Disable the backup PLL */
+ if ((delta > drv_state.max_speed_delta_khz)
+ || (strt_s->pll == ACPU_PLL_4 &&
+ tgt_s->pll == ACPU_PLL_4))
+ clk_disable_unprepare(pll_clk[backup_s->pll].clk);
+
+ goto done;
+ }
+
while (cur_s != tgt_s) {
/*
* Always jump to target freq if within max_speed_delta_khz,
@@ -648,17 +786,10 @@
acpuclk_set_div(cur_s);
drv_state.current_speed = cur_s;
/* Re-adjust lpj for the new clock speed. */
-#ifdef CONFIG_SMP
- for_each_possible_cpu(cpu) {
- per_cpu(cpu_data, cpu).loops_per_jiffy =
- cur_s->lpj;
- }
-#endif
- /* Adjust the global one */
- loops_per_jiffy = cur_s->lpj;
+ update_jiffies(cpu, cur_s->lpj);
}
-
+done:
/* Nothing else to do for SWFI. */
if (reason == SETRATE_SWFI)
goto out;
@@ -781,7 +912,7 @@
static void __devinit select_freq_plan(void)
{
unsigned long pll_mhz[ACPU_PLL_END];
- struct pll_freq_tbl_map *t;
+ struct pll_freq_tbl_map *t = acpu_freq_tbl_list;
int i;
/* Get PLL clocks */
@@ -817,7 +948,7 @@
}
} else {
/* Select the right table to use. */
- for (t = acpu_freq_tbl_list; t->tbl != 0; t++) {
+ for (; t->tbl != 0; t++) {
if (t->pll0_rate == pll_mhz[ACPU_PLL_0]
&& t->pll1_rate == pll_mhz[ACPU_PLL_1]
&& t->pll2_rate == pll_mhz[ACPU_PLL_2]
@@ -828,6 +959,25 @@
}
}
+ /*
+ * When PLL4 can run max @ 1401.6MHz, we have to support
+ * dynamic reprograming of PLL4.
+ *
+ * Also find the backup pll used during PLL4 reprogramming.
+ * We are using PLL2@600MHz as backup PLL, since 800MHz jump
+ * is fine.
+ */
+ if (t->pll4_rate == 1401) {
+ dynamic_reprogram = 1;
+ for ( ; t->tbl->a11clk_khz; t->tbl++) {
+ if (t->tbl->pll == ACPU_PLL_2 &&
+ t->tbl->a11clk_src_div == 1) {
+ backup_s = t->tbl;
+ break;
+ }
+ }
+ }
+
if (acpu_freq_tbl == NULL) {
pr_crit("Unknown PLL configuration!\n");
BUG();
@@ -988,3 +1138,4 @@
return platform_driver_register(&acpuclk_7627_driver);
}
postcore_initcall(acpuclk_7627_init);
+
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
index e73a2af..841f717 100644
--- a/arch/arm/mach-msm/acpuclock.h
+++ b/arch/arm/mach-msm/acpuclock.h
@@ -90,4 +90,4 @@
*/
void acpuclk_register(struct acpuclk_data *data);
-#endif
+#endif /*__ARCH_ARM_MACH_MSM_ACPUCLOCK_H*/
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 2938135..d5831e2 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -319,6 +319,7 @@
{60, 1152000000},
{62, 1200000000},
{63, 1209600000},
+ {73, 1401600000},
{0, 0},
};
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 8912e96..96984fb 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -236,12 +236,22 @@
.max_speed_delta_khz = 604800,
};
+static struct acpuclk_pdata msm8625ab_acpuclk_pdata = {
+ .max_speed_delta_khz = 801600,
+};
+
struct platform_device msm8625_device_acpuclk = {
.name = "acpuclk-7627",
.id = -1,
.dev.platform_data = &msm8625_acpuclk_pdata,
};
+struct platform_device msm8625ab_device_acpuclk = {
+ .name = "acpuclk-7627",
+ .id = -1,
+ .dev.platform_data = &msm8625ab_acpuclk_pdata,
+};
+
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
@@ -1623,6 +1633,7 @@
enum {
MSM8625,
MSM8625A,
+ MSM8625AB,
};
static int __init msm8625_cpu_id(void)
@@ -1643,6 +1654,11 @@
case 0x781:
cpu = MSM8625A;
break;
+ case 0x775:
+ case 0x776:
+ case 0x782:
+ cpu = MSM8625AB;
+ break;
default:
pr_err("Invalid Raw ID\n");
return -ENODEV;
@@ -1665,10 +1681,11 @@
platform_device_register(&msm7x27aa_device_acpuclk);
else if (msm8625_cpu_id() == MSM8625A)
platform_device_register(&msm8625_device_acpuclk);
+ else if (msm8625_cpu_id() == MSM8625AB)
+ platform_device_register(&msm8625ab_device_acpuclk);
} else {
platform_device_register(&msm7x27a_device_acpuclk);
}
-
return 0;
}
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 42e34e6..ab38346 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -424,6 +424,7 @@
extern struct platform_device apq8064_device_acpuclk;
extern struct platform_device msm8625_device_acpuclk;
extern struct platform_device msm8627_device_acpuclk;
+extern struct platform_device msm8625ab_device_acpuclk;
extern struct platform_device msm8x50_device_acpuclk;
extern struct platform_device msm8x60_device_acpuclk;
extern struct platform_device msm8930_device_acpuclk;