msm: devices-msm7x27a: Enable L2 No write allocate and Double line fill
L2 cache settings for improving memory performance on msm8625.
To improve write bandwidth, L2 is forced to No-Write-Allocate
through L2_AUX_CTRL(Enable bit 23).
To improve read bandwidth, Prefech offset of 3(Bit 0-4)and
Double line fill(Bit 23, 30)are enabled through L2_PREFETCH_CTRL.
Change-Id: Ia05cc41f8dee65486af9b0b7269b7f5763b5a988
Signed-off-by: Prachee Ramsinghani <pracheer@codeaurora.org>
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index d722e2f..917500c 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -1633,6 +1633,7 @@
static int __init msm7x27x_cache_init(void)
{
int aux_ctrl = 0;
+ int pctrl = 0;
/* Way Size 010(0x2) 32KB */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
@@ -1643,10 +1644,22 @@
/* Way Size 011(0x3) 64KB */
aux_ctrl |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | \
- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT);
+ (0X1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | \
+ (0x1 << L2X0_AUX_CTRL_L2_FORCE_NWA_SHIFT);
+
+ /* Write Prefetch Control settings */
+ pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
+ pctrl |= (0x3 << L2X0_PREFETCH_CTRL_OFFSET_SHIFT) | \
+ (0x1 << L2X0_PREFETCH_CTRL_WRAP8_INC_SHIFT) | \
+ (0x1 << L2X0_PREFETCH_CTRL_WRAP8_SHIFT);
+ writel_relaxed(pctrl , MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
}
l2x0_init(MSM_L2CC_BASE, aux_ctrl, L2X0_AUX_CTRL_MASK);
+ if (cpu_is_msm8625()) {
+ pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
+ pr_info("Prfetch Ctrl: 0x%08x\n", pctrl);
+ }
return 0;
}
@@ -1687,4 +1700,3 @@
return 0;
}
postcore_initcall(msm7627a_init_gpio);
-