tree b746b8800bc99633f31505d151624c8ccd75cd47
parent 326764a85b7676388db3ebad6488f312631d7661
author Russell King <rmk@dyn-67.arm.linux.org.uk> 1151601861 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1151601861 +0100

[ARM] Set bit 4 on section mappings correctly depending on CPU

On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>