Merge "msm: pcie: fix PCIe RAM issue on APQ8064v1"
diff --git a/arch/arm/mach-msm/pcie.c b/arch/arm/mach-msm/pcie.c
index c2ba6c1..c09b759 100644
--- a/arch/arm/mach-msm/pcie.c
+++ b/arch/arm/mach-msm/pcie.c
@@ -46,6 +46,7 @@
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PCIE20_ELBI_VERSION 0x00
#define PCIE20_ELBI_SYS_CTRL 0x04
#define PCIE20_CAP 0x70
@@ -55,6 +56,8 @@
#define PCIE20_BUSNUMBERS 0x18
#define PCIE20_MEMORY_BASE_LIMIT 0x20
+#define PCIE20_PLR_AXI_MSTR_RESP_COMP_CTRL0 0x818
+#define PCIE20_PLR_AXI_MSTR_RESP_COMP_CTRL1 0x81c
#define PCIE20_PLR_IATU_VIEWPORT 0x900
#define PCIE20_PLR_IATU_CTRL1 0x904
#define PCIE20_PLR_IATU_CTRL2 0x908
@@ -478,6 +481,27 @@
msm_pcie_dev.axi_conf = NULL;
}
+static void msm_pcie_adjust_tlp_size(struct msm_pcie_dev_t *dev)
+{
+ /*
+ * Apply this fix only for device such as APQ8064 version 1.
+ * Set the Max TLP size to 2K, instead of using default of 4K
+ * to avoid a RAM problem in PCIE20 core of that version.
+ */
+ if (readl_relaxed(dev->elbi + PCIE20_ELBI_VERSION) == 0x01002107) {
+
+ /*
+ * CFG_REMOTE_RD_REQ_BRIDGE_SIZE:
+ * 5=4KB/4=2KB/3=1KB/2=512B/1=256B/0=128B
+ */
+ writel_relaxed(4, dev->pcie20 +
+ PCIE20_PLR_AXI_MSTR_RESP_COMP_CTRL0);
+
+ writel_relaxed(1, dev->pcie20 +
+ PCIE20_PLR_AXI_MSTR_RESP_COMP_CTRL1);
+ }
+};
+
static int __init msm_pcie_setup(int nr, struct pci_sys_data *sys)
{
int rc;
@@ -555,6 +579,12 @@
gpio_set_value_cansleep(dev->gpio[MSM_PCIE_GPIO_RST_N].num,
!dev->gpio[MSM_PCIE_GPIO_RST_N].on);
+ /*
+ * adjust tlp size before link comes up
+ * so there will be no transactions.
+ */
+ msm_pcie_adjust_tlp_size(dev);
+
/* enable link training */
msm_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));