ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0
This avoids unnecessary instructions for CPUs which implement the IFAR
(instruction fault address register).
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582bb23..d644d02 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -45,7 +45,7 @@
.endm
.macro pabt_helper
- mov r0, r4 @ pass address of aborted instruction.
+ @ PABORT handler takes fault address in r4
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc
diff --git a/arch/arm/mm/pabort-legacy.S b/arch/arm/mm/pabort-legacy.S
index 87970eb..8a5d8aa 100644
--- a/arch/arm/mm/pabort-legacy.S
+++ b/arch/arm/mm/pabort-legacy.S
@@ -4,7 +4,7 @@
/*
* Function: legacy_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = Simulated IFSR with section translation fault status
@@ -14,6 +14,7 @@
.align 5
ENTRY(legacy_pabort)
+ mov r0, r4
mov r1, #5
mov pc, lr
ENDPROC(legacy_pabort)
diff --git a/arch/arm/mm/pabort-v6.S b/arch/arm/mm/pabort-v6.S
index 06e3d1e..eaac1cb 100644
--- a/arch/arm/mm/pabort-v6.S
+++ b/arch/arm/mm/pabort-v6.S
@@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR
@@ -14,6 +14,7 @@
.align 5
ENTRY(v6_pabort)
+ mov r0, r4
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
mov pc, lr
ENDPROC(v6_pabort)
diff --git a/arch/arm/mm/pabort-v7.S b/arch/arm/mm/pabort-v7.S
index a8b3b30..b515e0b 100644
--- a/arch/arm/mm/pabort-v7.S
+++ b/arch/arm/mm/pabort-v7.S
@@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR