tree 0c6b7c62dbec9d598546c7e58cb13c0c78212a1e
parent 7adbedaf4469dcdcd6a1ab9bdeb8ad854d4f9827
author David Daney <ddaney@caviumnetworks.com> 1231198198 -0800
committer Ralf Baechle <ralf@linux-mips.org> 1233351178 +0000

MIPS: Read watch registers with interrupts disabled.

If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>