Merge "msm: 8974: Add gpio configuration for HSIC controller and HUB"
diff --git a/Documentation/block/row-iosched.txt b/Documentation/block/row-iosched.txt
index 987bd88..fe8b88b 100644
--- a/Documentation/block/row-iosched.txt
+++ b/Documentation/block/row-iosched.txt
@@ -8,16 +8,28 @@
The ROW IO scheduler was developed with the mobile devices needs in
mind. In mobile devices we favor user experience upon everything else,
thus we want to give READ IO requests as much priority as possible.
-The main idea of the ROW scheduling policy is:
-If there are READ requests in pipe - dispatch them but don't starve
-the WRITE requests too much.
+The main idea of the ROW scheduling policy is just that:
+- If there are READ requests in pipe - dispatch them, while write
+starvation is considered.
Software description
====================
+The elevator defines a registering mechanism for different IO scheduler
+to implement. This makes implementing a new algorithm quite straight
+forward and requires almost no changes to block/elevator framework. A
+new IO scheduler just has to implement a set of callback functions
+defined by the elevator.
+These callbacks cover all the required IO operations such as
+adding/removing request to/from the scheduler, merging two requests,
+dispatching a request etc.
+
+Design
+======
+
The requests are kept in queues according to their priority. The
dispatching of requests is done in a Round Robin manner with a
different slice for each queue. The dispatch quantum for a specific
-queue is defined according to the queues priority. READ queues are
+queue is set according to the queues priority. READ queues are
given bigger dispatch quantum than the WRITE queues, within a dispatch
cycle.
@@ -30,88 +42,93 @@
- Regular priority WRITE queue
- Low priority READ queue
+The marking of request as high/low priority will be done by the
+application adding the request and not the scheduler. See TODO section.
+If the request is not marked in any way (high/low) the scheduler
+assigns it to one of the regular priority queues:
+read/write/sync write.
+
If in a certain dispatch cycle one of the queues was empty and didn't
-use its quantum that queue will be marked as "un-served". If we're in a
-middle of a dispatch cycle dispatching from queue Y and a request
+use its quantum that queue will be marked as "un-served". If we're in
+a middle of a dispatch cycle dispatching from queue Y and a request
arrives for queue X that was un-served in the previous cycle, if X's
priority is higher than Y's, queue X will be preempted in the favor of
-queue Y. This won't mean that cycle is restarted. The "dispatched"
-counter of queue X will remain unchanged. Once queue Y uses up it's quantum
-(or there will be no more requests left on it) we'll switch back to queue X
-and allow it to finish it's quantum.
+queue Y.
-For READ requests queues we allow idling in within a dispatch quantum in
-order to give the application a chance to insert more requests. Idling
-means adding some extra time for serving a certain queue even if the
-queue is empty. The idling is enabled if we identify the application is
-inserting requests in a high frequency.
+For READ request queues ROW IO scheduler allows idling within a
+dispatch quantum in order to give the application a chance to insert
+more requests. Idling means adding some extra time for serving a
+certain queue even if the queue is empty. The idling is enabled if
+the ROW IO scheduler identifies the application is inserting requests
+in a high frequency.
+Not all queues can idle. ROW scheduler exposes an enablement struct
+for idling.
+For idling on READ queues, the ROW IO scheduler uses timer mechanism.
+When the timer expires we schedule a delayed work that will signal the
+device driver to fetch another request for dispatch.
-For idling on READ queues we use timer mechanism. When the timer expires,
-if there are requests in the scheduler we will signal the underlying driver
-(for example the MMC driver) to fetch another request for dispatch.
-
-The ROW algorithm takes the scheduling policy one step further, making
-it a bit more "user-needs oriented", by allowing the application to
-hint on the urgency of its requests. For example: even among the READ
-requests several requests may be more urgent for completion then others.
-The former will go to the High priority READ queue, that is given the
-bigger dispatch quantum than any other queue.
-
-ROW scheduler will support special services for block devices that
-supports High Priority Requests. That is, the scheduler may inform the
-device upon urgent requests using new callback make_urgent_request.
+ROW scheduler will support additional services for block devices that
+supports Urgent Requests. That is, the scheduler may inform the
+device driver upon urgent requests using a newly defined callback.
In addition it will support rescheduling of requests that were
-interrupted. For example, if the device issues a long write request and
-a sudden high priority read interrupt pops in, the scheduler will
-inform the device about the urgent request, so the device can stop the
-current write request and serve the high priority read request. In such
-a case the device may also send back to the scheduler the reminder of
-the interrupted write request, such that the scheduler may continue
-sending high priority requests without the need to interrupt the
-ongoing write again and again. The write remainder will be sent later on
-according to the scheduler policy.
-
-Design
-======
-Existing algorithms (cfq, deadline) sort the io requests according LBA.
-When deciding on the next request to dispatch they choose the closest
-request to the current disk head position (from handling last
-dispatched request). This is done in order to reduce the disk head
-movement to a minimum.
-We feel that this functionality isn't really needed in mobile devices.
-Usually applications that write/read large chunks of data insert the
-requests in already sorted LBA order. Thus dealing with sort trees adds
-unnecessary complexity.
-
-We're planing to try this enhancement in the future to check if the
-performance is influenced by it.
+interrupted. For example if the device driver issues a long write
+request and a sudden urgent request is received by the scheduler.
+The scheduler will inform the device driver about the urgent request,
+so the device driver can stop the current write request and serve the
+urgent request. In such a case the device driver may also insert back
+to the scheduler the remainder of the interrupted write request, such
+that the scheduler may continue sending urgent requests without the
+need to interrupt the ongoing write again and again. The write
+remainder will be sent later on according to the scheduler policy.
SMP/multi-core
==============
-At the moment the code is acceded from 2 contexts:
+At the moment the code is accessed from 2 contexts:
- Application context (from block/elevator layer): adding the requests.
-- Underlying driver context (for example the mmc driver thread): dispatching
- the requests and notifying on completion.
+- device driver thread: dispatching the requests and notifying on
+ completion.
One lock is used to synchronize between the two. This lock is provided
-by the underlying driver along with the dispatch queue.
+by the block device driver along with the dispatch queue.
Config options
==============
1. hp_read_quantum: dispatch quantum for the high priority READ queue
-2. rp_read_quantum: dispatch quantum for the regular priority READ queue
-3. hp_swrite_quantum: dispatch quantum for the high priority Synchronous
- WRITE queue
+ (default is 100 requests)
+2. rp_read_quantum: dispatch quantum for the regular priority READ
+ queue (default is 100 requests)
+3. hp_swrite_quantum: dispatch quantum for the high priority
+ Synchronous WRITE queue (default is 2 requests)
4. rp_swrite_quantum: dispatch quantum for the regular priority
- Synchronous WRITE queue
+ Synchronous WRITE queue (default is 1 requests)
5. rp_write_quantum: dispatch quantum for the regular priority WRITE
- queue
+ queue (default is 1 requests)
6. lp_read_quantum: dispatch quantum for the low priority READ queue
+ (default is 1 requests)
7. lp_swrite_quantum: dispatch quantum for the low priority Synchronous
- WRITE queue
+ WRITE queue (default is 1 requests)
8. read_idle: how long to idle on read queue in Msec (in case idling
- is enabled on that queue).
+ is enabled on that queue). (default is 5 Msec)
9. read_idle_freq: frequency of inserting READ requests that will
trigger idling. This is the time in Msec between inserting two READ
- requests
+ requests. (default is 8 Msec)
+Note: Dispatch quantum is number of requests that will be dispatched
+from a certain queue in a dispatch cycle.
+
+To do
+=====
+The ROW algorithm takes the scheduling policy one step further, making
+it a bit more "user-needs oriented", by allowing the application to
+hint on the urgency of its requests. For example: even among the READ
+requests several requests may be more urgent for completion than other.
+The former will go to the High priority READ queue, that is given the
+bigger dispatch quantum than any other queue.
+
+Still need to design the way applications will "hint" on the urgency of
+their requests. May be done by ioctl(). We need to look into concrete
+use-cases in order to determine the best solution for this.
+This will be implemented as a second phase.
+
+Design and implement additional services for block devices that
+supports High Priority Requests.
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/dma/sps/sps.txt b/Documentation/devicetree/bindings/dma/sps/sps.txt
new file mode 100644
index 0000000..094acb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/sps/sps.txt
@@ -0,0 +1,27 @@
+SPS (Smart Peripheral Switch) may be used as a DMA engine to move data
+in either the Peripheral-to-Peripheral (a.k.a. BAM-to-BAM) mode or the
+Peripheral-to-Memory (a.k.a. BAM-System) mode. SPS includes BAM (Bus
+Access Module) hardware block, BAM DMA peripheral, and pipe memory.
+
+Required property:
+ - compatible: should be "qcom,msm_sps"
+
+Optional properties:
+ - reg: offset and size of the register set in the memory map
+ - interrupts: IRQ line
+ - qcom,device-type: specify the device configuration of BAM DMA and
+ pipe memory. Can be one of
+ 1 - With BAM DMA and without pipe memory
+ 2 - With BAM DMA and with pipe memory
+ 3 - Without BAM DMA and without pipe memory
+
+Example:
+
+ qcom,sps@f9980000 {
+ compatible = "qcom,msm_sps";
+ reg = <0xf9984000 0x15000>,
+ <0xf9999000 0xb000>,
+ <0xfe803000 0x4800>;
+ interrupts = <0 94 0>;
+ qcom,device-type = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp.txt b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
index 10732cf..da0708f 100644
--- a/Documentation/devicetree/bindings/leds/leds-qpnp.txt
+++ b/Documentation/devicetree/bindings/leds/leds-qpnp.txt
@@ -6,14 +6,14 @@
SPMI bus. This driver supports various LED modules such as
WLED (white LED), RGB LED and flash LED.
-Required Properties:
-- compatible : should be "qcom,leds-qpnp"
-
Each LED module is represented as a node of "leds-qpnp". This
node will further contain the type of LED supported and its
-properties.
+properties. At least one child node is required for each LED
+module. Each must have the required properties below, in addition
+to the properties for the LED type, WLED, Flash or RGB.
-Required properties:
+Required properties for each child node, WLED, Flash and RGB:
+- compatible : should be "qcom,leds-qpnp"
- qcom,id : must be one of values supported in enum qpnp_led
- label : type of led that will be used, ie "wled"
- qcom,max-current : maximum current that the LED can sustain
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index 802716c..5bef9b8 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -14,6 +14,7 @@
"metadata_base" are expected.
- interrupts: The modem watchdog interrupt
- vdd_mss-supply: Reference to the regulator that supplies the processor.
+- vdd_mx-supply: Reference to the regulator that supplies the memory rail.
- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp"
- qcom,pil-self-auth: <0> if the hardware does not require self-authenticating
images and self-authentication is not desired;
@@ -32,6 +33,7 @@
"restart_reg", metadata_base";
interrupts = <0 24 1>;
vdd_mss-supply = <&pm8841_s3>;
+ vdd_mx-supply = <&pm8841_s1>;
qcom,is-loadable;
qcom,firmware-name = "mba";
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 81b5dc9..2f2603f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -265,7 +265,12 @@
KBUILD_IMAGE := zImage
endif
-all: $(KBUILD_IMAGE)
+# Build the DT binary blobs if we have OF configured
+ifeq ($(CONFIG_USE_OF),y)
+KBUILD_DTBS := dtbs
+endif
+
+all: $(KBUILD_IMAGE) $(KBUILD_DTBS)
boot := arch/arm/boot
@@ -281,10 +286,10 @@
zinstall uinstall install: vmlinux
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
-%.dtb:
+%.dtb: scripts
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
-dtbs:
+dtbs: scripts
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
# We use MRPROPER_FILES and CLEAN_FILES now
@@ -303,7 +308,7 @@
echo ' uImage - U-Boot wrapped zImage'
echo ' bootpImage - Combined zImage and initial RAM disk'
echo ' (supply initrd image via make variable INITRD=<path>)'
- echo ' dtbs - Build device tree blobs for enabled boards'
+ echo '* dtbs - Build device tree blobs for enabled boards'
echo ' install - Install uncompressed kernel'
echo ' zinstall - Install compressed kernel'
echo ' uinstall - Install U-Boot wrapped compressed kernel'
diff --git a/arch/arm/boot/dts/msm8910.dtsi b/arch/arm/boot/dts/msm8910.dtsi
index 714ad09..3786b02 100644
--- a/arch/arm/boot/dts/msm8910.dtsi
+++ b/arch/arm/boot/dts/msm8910.dtsi
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "msm8910-ion.dtsi"
+/include/ "msm-gdsc.dtsi"
/ {
model = "Qualcomm MSM 8910";
@@ -127,6 +128,11 @@
qcom,current-limit = <800>;
};
+ qcom,sps {
+ compatible = "qcom,msm_sps";
+ qcom,device-type = <3>;
+ };
+
qcom,smem@fa00000 {
compatible = "qcom,smem";
reg = <0xfa00000 0x200000>,
@@ -193,6 +199,7 @@
interrupts = <0 168 1>;
qcom,irq-no-suspend;
};
+ };
qcom,wdt@f9017000 {
compatible = "qcom,msm-watchdog";
@@ -204,4 +211,12 @@
};
};
+&gdsc_vfe {
+ status = "ok";
+};
+
+&gdsc_oxili_cx {
+ status = "ok";
+};
+
/include/ "msm8910-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm8974-cdp.dtsi b/arch/arm/boot/dts/msm8974-cdp.dtsi
index 00e9c7a..bd02d89 100644
--- a/arch/arm/boot/dts/msm8974-cdp.dtsi
+++ b/arch/arm/boot/dts/msm8974-cdp.dtsi
@@ -42,7 +42,6 @@
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
atmel,i2c-pull-up;
- atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
diff --git a/arch/arm/boot/dts/msm8974-fluid.dtsi b/arch/arm/boot/dts/msm8974-fluid.dtsi
index cac7d3c..8479dfa 100644
--- a/arch/arm/boot/dts/msm8974-fluid.dtsi
+++ b/arch/arm/boot/dts/msm8974-fluid.dtsi
@@ -42,7 +42,6 @@
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
atmel,i2c-pull-up;
- atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
diff --git a/arch/arm/boot/dts/msm8974-liquid.dtsi b/arch/arm/boot/dts/msm8974-liquid.dtsi
index 7da00d3..f412d177 100644
--- a/arch/arm/boot/dts/msm8974-liquid.dtsi
+++ b/arch/arm/boot/dts/msm8974-liquid.dtsi
@@ -121,7 +121,6 @@
atmel,panel-coords = <0 0 1080 1920>;
atmel,display-coords = <0 0 1080 1920>;
atmel,i2c-pull-up;
- atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0xa2>;
atmel,variant-id = <0x00>;
diff --git a/arch/arm/boot/dts/msm8974-mtp.dtsi b/arch/arm/boot/dts/msm8974-mtp.dtsi
index cdb1710..9fb7d0e 100644
--- a/arch/arm/boot/dts/msm8974-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8974-mtp.dtsi
@@ -42,7 +42,6 @@
atmel,panel-coords = <0 0 760 1424>;
atmel,display-coords = <0 0 720 1280>;
atmel,i2c-pull-up;
- atmel,no-force-update;
atmel,cfg_1 {
atmel,family-id = <0x82>;
atmel,variant-id = <0x19>;
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 6d5f3cb..eeb05d4 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -151,24 +151,25 @@
qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;
qcom,sup-voltages = <2950 2950>;
qcom,bus-width = <8>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
qcom,msm-bus,name = "sdcc1";
- qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
- <78 512 6656 13312>, /* 13 MB/s*/
- <78 512 13312 26624>, /* 26 MB/s */
- <78 512 26624 53248>, /* 52 MB/s */
- <78 512 53248 106496>, /* 104 MB/s */
- <78 512 106496 212992>, /* 208 MB/s */
- <78 512 2147483647 4294967295>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ <78 512 1600 3200>, /* 400 KB/s*/
+ <78 512 80000 160000>, /* 20 MB/s */
+ <78 512 100000 200000>, /* 25 MB/s */
+ <78 512 200000 400000>, /* 50 MB/s */
+ <78 512 400000 800000>, /* 100 MB/s */
+ <78 512 800000 1600000>, /* 200 MB/s */
+ <78 512 2048000 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
qcom,dat1-mpm-int = <42>;
};
@@ -197,7 +198,7 @@
qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
- qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;
qcom,sup-voltages = <2950 2950>;
qcom,bus-width = <4>;
qcom,xpc;
@@ -205,17 +206,18 @@
qcom,current-limit = <800>;
qcom,msm-bus,name = "sdcc2";
- qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
- <81 512 6656 13312>, /* 13 MB/s*/
- <81 512 13312 26624>, /* 26 MB/s */
- <81 512 26624 53248>, /* 52 MB/s */
- <81 512 53248 106496>, /* 104 MB/s */
- <81 512 106496 212992>, /* 208 MB/s */
- <81 512 2147483647 4294967295>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ <81 512 1600 3200>, /* 400 KB/s*/
+ <81 512 80000 160000>, /* 20 MB/s */
+ <81 512 100000 200000>, /* 25 MB/s */
+ <81 512 200000 400000>, /* 50 MB/s */
+ <81 512 400000 800000>, /* 100 MB/s */
+ <81 512 800000 1600000>, /* 200 MB/s */
+ <81 512 2048000 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
qcom,dat1-mpm-int = <44>;
};
@@ -244,23 +246,24 @@
<&msmgpio 35 0>; /* DATA3 */
qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
- qcom,clk-rates = <400000 25000000 50000000 100000000>;
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>;
qcom,sup-voltages = <1800 1800>;
qcom,bus-width = <4>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
qcom,msm-bus,name = "sdcc3";
- qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
- <79 512 6656 13312>, /* 13 MB/s*/
- <79 512 13312 26624>, /* 26 MB/s */
- <79 512 26624 53248>, /* 52 MB/s */
- <79 512 53248 106496>, /* 104 MB/s */
- <79 512 106496 212992>, /* 208 MB/s */
- <79 512 2147483647 4294967295>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ <79 512 1600 3200>, /* 400 KB/s*/
+ <79 512 80000 160000>, /* 20 MB/s */
+ <79 512 100000 200000>, /* 25 MB/s */
+ <79 512 200000 400000>, /* 50 MB/s */
+ <79 512 400000 800000>, /* 100 MB/s */
+ <79 512 800000 1600000>, /* 200 MB/s */
+ <79 512 2048000 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
status = "disable";
};
@@ -289,23 +292,24 @@
<&msmgpio 92 0>; /* DATA3 */
qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
- qcom,clk-rates = <400000 25000000 50000000 100000000>;
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000>;
qcom,sup-voltages = <1800 1800>;
qcom,bus-width = <4>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
qcom,msm-bus,name = "sdcc4";
- qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,active-only = <0>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <80 512 0 0>, /* No vote */
- <80 512 6656 13312>, /* 13 MB/s*/
- <80 512 13312 26624>, /* 26 MB/s */
- <80 512 26624 53248>, /* 52 MB/s */
- <80 512 53248 106496>, /* 104 MB/s */
- <80 512 106496 212992>, /* 208 MB/s */
- <80 512 2147483647 4294967295>; /* Max. bandwidth */
- qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+ <80 512 1600 3200>, /* 400 KB/s*/
+ <80 512 80000 160000>, /* 20 MB/s */
+ <80 512 100000 200000>, /* 25 MB/s */
+ <80 512 200000 400000>, /* 50 MB/s */
+ <80 512 400000 800000>, /* 100 MB/s */
+ <80 512 800000 1600000>, /* 200 MB/s */
+ <80 512 2048000 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>;
status = "disable";
};
@@ -882,6 +886,7 @@
interrupts = <0 24 1>;
vdd_mss-supply = <&pm8841_s3>;
+ vdd_mx-supply = <&pm8841_s1>;
qcom,is-loadable;
qcom,firmware-name = "mba";
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index ac17480..e7a9237 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -252,11 +252,6 @@
tick_nohz_idle_enter();
rcu_idle_enter();
while (!need_resched()) {
-#ifdef CONFIG_HOTPLUG_CPU
- if (cpu_is_offline(smp_processor_id()))
- cpu_die();
-#endif
-
/*
* We need to disable interrupts here
* to ensure we don't miss a wakeup call.
@@ -285,6 +280,10 @@
tick_nohz_idle_exit();
idle_notifier_call_chain(IDLE_END);
schedule_preempt_disabled();
+#ifdef CONFIG_HOTPLUG_CPU
+ if (cpu_is_offline(smp_processor_id()))
+ cpu_die();
+#endif
}
}
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 90aed03..a567db0 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -142,6 +142,7 @@
select MSM_PM8X60 if PM
select MSM_RUN_QUEUE_STATS
select ARM_HAS_SG_CHAIN
+ select USE_DEV_CTRL_VOLUME
config ARCH_MSM8960
bool "MSM8960"
@@ -2699,4 +2700,9 @@
Enables MSM-specific user accessible timers via a shared
memory page containing the cycle counter.
+config USE_DEV_CTRL_VOLUME
+ bool "Use Device Control Volume"
+ help
+ Use Device Control Volume as opposed to ALSA volume control.
+
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 548f40e..7555e51 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -297,6 +297,7 @@
obj-$(CONFIG_ARCH_MSM8974) += gdsc.o
obj-$(CONFIG_ARCH_MSM9625) += gdsc.o
obj-$(CONFIG_ARCH_MSM8226) += gdsc.o
+obj-$(CONFIG_ARCH_MSM8910) += gdsc.o
obj-$(CONFIG_ARCH_MSM8974) += krait-regulator.o
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += clock-local2.o clock-pll.o clock-9625.o clock-rpm.o clock-voter.o acpuclock-9625.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index cf1f401..e74d61a 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -47,15 +47,25 @@
# MSM8974
zreladdr-$(CONFIG_ARCH_MSM8974) := 0x00008000
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-cdp.dtb
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-fluid.dtb
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-liquid.dtb
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-mtp.dtb
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-rumi.dtb
+ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-sim.dtb
# MSM9615
zreladdr-$(CONFIG_ARCH_MSM9615) := 0x40808000
# MSM9625
zreladdr-$(CONFIG_ARCH_MSM9625) := 0x00208000
+ dtb-$(CONFIG_ARCH_MSM9625) += msm9625-cdp.dtb
+ dtb-$(CONFIG_ARCH_MSM9625) += msm9625-mtp.dtb
+ dtb-$(CONFIG_ARCH_MSM9625) += msm9625-rumi.dtb
# MSM8226
zreladdr-$(CONFIG_ARCH_MSM8226) := 0x00008000
+ dtb-$(CONFIG_ARCH_MSM8226) += msm8226-sim.dtb
# FSM9XXX
zreladdr-$(CONFIG_ARCH_FSM9XXX) := 0x10008000
@@ -67,3 +77,5 @@
# MSM8910
zreladdr-$(CONFIG_ARCH_MSM8910) := 0x00008000
+ dtb-$(CONFIG_ARCH_MSM8910) += msm8910-rumi.dtb
+ dtb-$(CONFIG_ARCH_MSM8910) += msm8910-sim.dtb
diff --git a/arch/arm/mach-msm/acpuclock-7627.c b/arch/arm/mach-msm/acpuclock-7627.c
index dd27123..00b6458 100644
--- a/arch/arm/mach-msm/acpuclock-7627.c
+++ b/arch/arm/mach-msm/acpuclock-7627.c
@@ -857,8 +857,7 @@
goto out;
/* Change the AXI bus frequency if we can. */
- if (reason != SETRATE_PC &&
- strt_s->axiclk_khz != tgt_s->axiclk_khz) {
+ if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
res = clk_set_rate(drv_state.ebi1_clk,
tgt_s->axiclk_khz * 1000);
if (res < 0)
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index fab974d..e5212a4 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -101,6 +101,7 @@
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
#define HOLE_SIZE 0x20000
+#define MSM_ION_MFC_META_SIZE 0x40000 /* 256 Kbytes */
#define MSM_CONTIG_MEM_SIZE 0x65000
#ifdef CONFIG_MSM_IOMMU
#define MSM_ION_MM_SIZE 0x3800000
@@ -114,7 +115,7 @@
#define MSM_ION_HEAP_NUM 8
#endif
#define MSM_ION_MM_FW_SIZE (0x200000 - HOLE_SIZE) /* (2MB - 128KB) */
-#define MSM_ION_MFC_SIZE SZ_8K
+#define MSM_ION_MFC_SIZE (SZ_8K + MSM_ION_MFC_META_SIZE)
#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
#else
#define MSM_CONTIG_MEM_SIZE 0x110C000
@@ -330,9 +331,7 @@
* to each other.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data apq8064_ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+struct ion_platform_heap apq8064_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -395,7 +394,11 @@
.extra_data = (void *) &co_apq8064_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data apq8064_ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = apq8064_heaps,
};
static struct platform_device apq8064_ion_dev = {
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 512ae72..790afe1 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -132,7 +132,7 @@
#endif
#define MSM_PMEM_ADSP_SIZE 0x7800000
-#define MSM_PMEM_AUDIO_SIZE 0x314000
+#define MSM_PMEM_AUDIO_SIZE 0x408000
#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
#else
@@ -376,9 +376,7 @@
* to each other.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data msm8930_ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+struct ion_platform_heap msm8930_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -441,7 +439,12 @@
.extra_data = (void *) &co_msm8930_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data msm8930_ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = msm8930_heaps,
+
};
static struct platform_device msm8930_ion_dev = {
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index 57f7b51..adf4ac0 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -151,6 +151,7 @@
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
#define HOLE_SIZE 0x20000
+#define MSM_ION_MFC_META_SIZE 0x40000 /* 256 Kbytes */
#define MSM_CONTIG_MEM_SIZE 0x65000
#ifdef CONFIG_MSM_IOMMU
#define MSM_ION_MM_SIZE 0x3800000 /* Need to be multiple of 64K */
@@ -164,7 +165,7 @@
#define MSM_ION_HEAP_NUM 8
#endif
#define MSM_ION_MM_FW_SIZE (0x200000 - HOLE_SIZE) /* 128kb */
-#define MSM_ION_MFC_SIZE SZ_8K
+#define MSM_ION_MFC_SIZE (SZ_8K + MSM_ION_MFC_META_SIZE)
#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
#define MSM_LIQUID_ION_MM_SIZE (MSM_ION_MM_SIZE + 0x600000)
@@ -398,9 +399,7 @@
* to each other.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data msm8960_ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+struct ion_platform_heap msm8960_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -463,7 +462,11 @@
.extra_data = (void *) &co_msm8960_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data msm8960_ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = msm8960_heaps,
};
static struct platform_device msm8960_ion_dev = {
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index 1022616..1dcd54f 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -81,9 +81,7 @@
.align = PAGE_SIZE,
};
-static struct ion_platform_data ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+static struct ion_platform_heap msm9615_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -102,7 +100,11 @@
.memory_type = ION_EBI_TYPE,
.extra_data = (void *) &co_ion_pdata,
},
- }
+};
+
+static struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = msm9615_heaps,
};
static struct platform_device ion_dev = {
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 4e14ff3..9fd5218 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -767,10 +767,7 @@
* These heaps are listed in the order they will be allocated.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .has_outer_cache = 1,
- .heaps = {
+struct ion_platform_heap msm7627a_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -802,7 +799,12 @@
.extra_data = (void *)&co_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .has_outer_cache = 1,
+ .heaps = msm7627a_heaps,
};
static struct platform_device ion_dev = {
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index ee13e04..9822aa9 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -7161,9 +7161,7 @@
* These heaps are listed in the order they will be allocated.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+struct ion_platform_heap msm7x30_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -7195,7 +7193,11 @@
.extra_data = (void *)&co_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = msm7x30_heaps,
};
static struct platform_device ion_dev = {
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index d831ad2..08e6a0d 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -5347,9 +5347,7 @@
* to each other.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .heaps = {
+struct ion_platform_heap msm8x60_heaps [] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -5424,7 +5422,11 @@
.extra_data = (void *)&co_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .heaps = msm8x60_heaps,
};
static struct platform_device ion_dev = {
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index a25290f..47a3120 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -802,10 +802,7 @@
* These heaps are listed in the order they will be allocated.
* Don't swap the order unless you know what you are doing!
*/
-static struct ion_platform_data ion_pdata = {
- .nr = MSM_ION_HEAP_NUM,
- .has_outer_cache = 1,
- .heaps = {
+struct ion_platform_heap qrd7627a_heaps[] = {
{
.id = ION_SYSTEM_HEAP_ID,
.type = ION_HEAP_TYPE_SYSTEM,
@@ -837,7 +834,12 @@
.extra_data = (void *)&co_ion_pdata,
},
#endif
- }
+};
+
+static struct ion_platform_data ion_pdata = {
+ .nr = MSM_ION_HEAP_NUM,
+ .has_outer_cache = 1,
+ .heaps = qrd7627a_heaps,
};
static struct platform_device ion_dev = {
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 216de11..95f9327 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -800,11 +800,6 @@
static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_sdcc1_clk, &pnoc_clk.c, 0);
-static DEFINE_CLK_VOTER(pnoc_sdcc2_clk, &pnoc_clk.c, 0);
-static DEFINE_CLK_VOTER(pnoc_sdcc3_clk, &pnoc_clk.c, 0);
-static DEFINE_CLK_VOTER(pnoc_sdcc4_clk, &pnoc_clk.c, 0);
-
static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, 0);
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
@@ -2969,7 +2964,7 @@
};
static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
- F_MDSS(148500000, edppll_350, 2, 0, 0),
+ F_MDSS(138500000, edppll_350, 2, 0, 0),
F_MDSS(350000000, edppll_350, 11, 0, 0),
F_END
};
@@ -3074,9 +3069,11 @@
*/
F_HDMI( 0, hdmipll, 1, 0, 0),
F_HDMI( 25200000, hdmipll, 1, 0, 0),
+ F_HDMI( 27000000, hdmipll, 1, 0, 0),
F_HDMI( 27030000, hdmipll, 1, 0, 0),
F_HDMI( 74250000, hdmipll, 1, 0, 0),
F_HDMI(148500000, hdmipll, 1, 0, 0),
+ F_HDMI(268500000, hdmipll, 1, 0, 0),
F_HDMI(297000000, hdmipll, 1, 0, 0),
F_END
};
@@ -4985,16 +4982,12 @@
static struct clk_lookup msm_clocks_8974_rumi[] = {
CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("iface_clk", gcc_sdcc4_ahb_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("core_clk", gcc_sdcc4_apps_clk.c, "msm_sdcc.4"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc4_clk.c, "msm_sdcc.4"),
CLK_DUMMY("xo", XO_CLK, NULL, OFF),
CLK_DUMMY("xo", XO_CLK, "pil_pronto", OFF),
CLK_DUMMY("core_clk", BLSP2_UART_CLK, "f991f000.serial", OFF),
@@ -5110,16 +5103,12 @@
CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc3_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("iface_clk", gcc_sdcc4_ahb_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("core_clk", gcc_sdcc4_apps_clk.c, "msm_sdcc.4"),
- CLK_LOOKUP("bus_clk", pnoc_sdcc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("iface_clk", gcc_tsif_ahb_clk.c, ""),
CLK_LOOKUP("ref_clk", gcc_tsif_ref_clk.c, ""),
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index d3a4bba..2e85006 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -1318,6 +1318,17 @@
},
};
+static struct branch_clk gcc_ipa_sleep_clk = {
+ .cbcr_reg = IPA_SLEEP_CBCR,
+ .has_sibling = 1,
+ .base = &virt_bases[GCC_BASE],
+ .c = {
+ .dbg_name = "gcc_ipa_sleep_clk",
+ .ops = &clk_ops_branch,
+ CLK_INIT(gcc_ipa_sleep_clk.c),
+ },
+};
+
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
.has_sibling = 0,
@@ -2072,6 +2083,7 @@
CLK_LOOKUP("core_clk", gcc_ipa_clk.c, "fd4c0000.qcom,ipa"),
CLK_LOOKUP("bus_clk", gcc_sys_noc_ipa_axi_clk.c, "fd4c0000.qcom,ipa"),
CLK_LOOKUP("iface_clk", gcc_ipa_cnoc_clk.c, "fd4c0000.qcom,ipa"),
+ CLK_LOOKUP("inactivity_clk", gcc_ipa_sleep_clk.c, "fd4c0000.qcom,ipa"),
CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
diff --git a/arch/arm/mach-msm/clock-mdss-8974.c b/arch/arm/mach-msm/clock-mdss-8974.c
index e7a596d..c30e566 100644
--- a/arch/arm/mach-msm/clock-mdss-8974.c
+++ b/arch/arm/mach-msm/clock-mdss-8974.c
@@ -37,30 +37,65 @@
#define HDMI_PHY_PLL_SIZE 0x000000D4
/* hdmi phy registers */
-#define HDMI_PHY_PD_CTRL0 (0x0010)
-#define HDMI_PHY_GLB_CFG (0x0018)
-#define HDMI_PHY_STATUS (0x005C)
+#define HDMI_PHY_ANA_CFG0 (0x0000)
+#define HDMI_PHY_ANA_CFG1 (0x0004)
+#define HDMI_PHY_ANA_CFG2 (0x0008)
+#define HDMI_PHY_ANA_CFG3 (0x000C)
+#define HDMI_PHY_PD_CTRL0 (0x0010)
+#define HDMI_PHY_PD_CTRL1 (0x0014)
+#define HDMI_PHY_GLB_CFG (0x0018)
+#define HDMI_PHY_DCC_CFG0 (0x001C)
+#define HDMI_PHY_DCC_CFG1 (0x0020)
+#define HDMI_PHY_TXCAL_CFG0 (0x0024)
+#define HDMI_PHY_TXCAL_CFG1 (0x0028)
+#define HDMI_PHY_TXCAL_CFG2 (0x002C)
+#define HDMI_PHY_TXCAL_CFG3 (0x0030)
+#define HDMI_PHY_BIST_CFG0 (0x0034)
+#define HDMI_PHY_BIST_CFG1 (0x0038)
+#define HDMI_PHY_BIST_PATN0 (0x003C)
+#define HDMI_PHY_BIST_PATN1 (0x0040)
+#define HDMI_PHY_BIST_PATN2 (0x0044)
+#define HDMI_PHY_BIST_PATN3 (0x0048)
+#define HDMI_PHY_STATUS (0x005C)
/* hdmi phy unified pll registers */
-#define HDMI_UNI_PLL_REFCLK_CF (0x0000)
-#define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004)
-#define HDMI_UNI_PLL_VCOLPF_CFG (0x000C)
-#define HDMI_UNI_PLL_GLB_CFG (0x0020)
-#define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024)
-#define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028)
-#define HDMI_UNI_PLL_SDM_CFG0 (0x0038)
-#define HDMI_UNI_PLL_SDM_CFG1 (0x003C)
-#define HDMI_UNI_PLL_SDM_CFG2 (0x0040)
-#define HDMI_UNI_PLL_SDM_CFG3 (0x0044)
-#define HDMI_UNI_PLL_SDM_CFG4 (0x0048)
-#define HDMI_UNI_PLL_LKDET_CFG0 (0x005C)
-#define HDMI_UNI_PLL_LKDET_CFG1 (0x0060)
-#define HDMI_UNI_PLL_LKDET_CFG2 (0x0064)
-#define HDMI_UNI_PLL_CAL_CFG8 (0x008C)
-#define HDMI_UNI_PLL_CAL_CFG9 (0x0090)
-#define HDMI_UNI_PLL_CAL_CFG10 (0x0094)
-#define HDMI_UNI_PLL_CAL_CFG11 (0x0098)
-#define HDMI_UNI_PLL_STATUS (0x00C0)
+#define HDMI_UNI_PLL_REFCLK_CFG (0x0000)
+#define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004)
+#define HDMI_UNI_PLL_CHFPUMP_CFG (0x0008)
+#define HDMI_UNI_PLL_VCOLPF_CFG (0x000C)
+#define HDMI_UNI_PLL_VREG_CFG (0x0010)
+#define HDMI_UNI_PLL_PWRGEN_CFG (0x0014)
+#define HDMI_UNI_PLL_GLB_CFG (0x0020)
+#define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024)
+#define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028)
+#define HDMI_UNI_PLL_LPFR_CFG (0x002C)
+#define HDMI_UNI_PLL_LPFC1_CFG (0x0030)
+#define HDMI_UNI_PLL_LPFC2_CFG (0x0034)
+#define HDMI_UNI_PLL_SDM_CFG0 (0x0038)
+#define HDMI_UNI_PLL_SDM_CFG1 (0x003C)
+#define HDMI_UNI_PLL_SDM_CFG2 (0x0040)
+#define HDMI_UNI_PLL_SDM_CFG3 (0x0044)
+#define HDMI_UNI_PLL_SDM_CFG4 (0x0048)
+#define HDMI_UNI_PLL_SSC_CFG0 (0x004C)
+#define HDMI_UNI_PLL_SSC_CFG1 (0x0050)
+#define HDMI_UNI_PLL_SSC_CFG2 (0x0054)
+#define HDMI_UNI_PLL_SSC_CFG3 (0x0058)
+#define HDMI_UNI_PLL_LKDET_CFG0 (0x005C)
+#define HDMI_UNI_PLL_LKDET_CFG1 (0x0060)
+#define HDMI_UNI_PLL_LKDET_CFG2 (0x0064)
+#define HDMI_UNI_PLL_CAL_CFG0 (0x006C)
+#define HDMI_UNI_PLL_CAL_CFG1 (0x0070)
+#define HDMI_UNI_PLL_CAL_CFG2 (0x0074)
+#define HDMI_UNI_PLL_CAL_CFG3 (0x0078)
+#define HDMI_UNI_PLL_CAL_CFG4 (0x007C)
+#define HDMI_UNI_PLL_CAL_CFG5 (0x0080)
+#define HDMI_UNI_PLL_CAL_CFG6 (0x0084)
+#define HDMI_UNI_PLL_CAL_CFG7 (0x0088)
+#define HDMI_UNI_PLL_CAL_CFG8 (0x008C)
+#define HDMI_UNI_PLL_CAL_CFG9 (0x0090)
+#define HDMI_UNI_PLL_CAL_CFG10 (0x0094)
+#define HDMI_UNI_PLL_CAL_CFG11 (0x0098)
+#define HDMI_UNI_PLL_STATUS (0x00C0)
#define VCO_CLK 424000000
static unsigned char *mdss_dsi_base;
@@ -391,32 +426,106 @@
case 25200000:
/* 640x480p60 */
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CF);
- REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
- REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
- REG_W(0x4C, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
- REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
+ REG_W(0xB0, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
+ REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
- REG_W(0xFC, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0xF4, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
+ REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
+ break;
+
+ case 27000000:
+ /* 576p50/576i50 case */
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0X0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0X0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x54, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0x18, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
+ REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
+ REG_W(0X1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
+ REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
+ REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
+ REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
+ REG_W(0x2a, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
+ REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0X1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0X0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0XDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0XD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0X1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
break;
case 27030000:
/* 480p60/480i60 case */
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CF);
- REG_W(0x18, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
- REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
- REG_W(0x14, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
- REG_W(0x63, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x54, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
+ REG_W(0x66, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0x1D, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
@@ -425,10 +534,29 @@
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0x2A, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
break;
case 74250000:
@@ -436,51 +564,148 @@
* 720p60/720p50/1080i60/1080i50
* 1080p24/1080p30/1080p25 case
*/
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CF);
- REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
- REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
- REG_W(0xFD, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
- REG_W(0x55, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0x56, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
- REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
- REG_W(0x73, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
- break;
-
- case 148500000:
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CF);
- REG_W(0x18, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
- REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
- REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
- REG_W(0xFD, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
- REG_W(0x55, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
- REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
- REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
- REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
- REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xE6, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
+ break;
+
+ case 148500000:
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x52, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0x56, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
+ REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
+ REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
+ REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
+ REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
+ REG_W(0xE6, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
+ REG_W(0x02, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
+ break;
+
+ case 268500000:
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x61, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0xF6, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
+ REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
+ REG_W(0x1A, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG1);
+ REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG2);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
+ REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
+ REG_W(0x3E, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
+ REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x11, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
break;
case 297000000:
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CF);
- REG_W(0x18, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
- REG_W(0x36, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
+ REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_REFCLK_CFG);
+ REG_W(0x19, hdmi_phy_pll_base + HDMI_UNI_PLL_VCOLPF_CFG);
+ REG_W(0x0E, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFR_CFG);
+ REG_W(0x20, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC1_CFG);
+ REG_W(0x0D, hdmi_phy_pll_base + HDMI_UNI_PLL_LPFC2_CFG);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG0);
REG_W(0x65, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG1);
- REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
+ REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG2);
REG_W(0xAC, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG3);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_SDM_CFG4);
REG_W(0x10, hdmi_phy_pll_base + HDMI_UNI_PLL_LKDET_CFG0);
@@ -489,14 +714,31 @@
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV1_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV2_CFG);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_POSTDIV3_CFG);
+ REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG2);
REG_W(0x60, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG8);
REG_W(0x00, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG9);
REG_W(0xCD, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG10);
REG_W(0x05, hdmi_phy_pll_base + HDMI_UNI_PLL_CAL_CFG11);
+ REG_W(0x1F, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
+ udelay(50);
+
+ REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL1);
+ REG_W(0x10, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0xDB, hdmi_phy_base + HDMI_PHY_ANA_CFG0);
+ REG_W(0x43, hdmi_phy_base + HDMI_PHY_ANA_CFG1);
+ REG_W(0x06, hdmi_phy_base + HDMI_PHY_ANA_CFG2);
+ REG_W(0x03, hdmi_phy_base + HDMI_PHY_ANA_CFG3);
+ REG_W(0x04, hdmi_phy_pll_base + HDMI_UNI_PLL_VREG_CFG);
+ REG_W(0xD0, hdmi_phy_base + HDMI_PHY_DCC_CFG0);
+ REG_W(0x1A, hdmi_phy_base + HDMI_PHY_DCC_CFG1);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG0);
+ REG_W(0x00, hdmi_phy_base + HDMI_PHY_TXCAL_CFG1);
+ REG_W(0x02, hdmi_phy_base + HDMI_PHY_TXCAL_CFG2);
+ REG_W(0x05, hdmi_phy_base + HDMI_PHY_TXCAL_CFG3);
+ udelay(200);
break;
- case 27000000:
- /* 576p50/576i50 case */
default:
pr_err("%s: not supported rate=%ld\n", __func__, rate);
}
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 12f5aa9..22fc1ac 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -373,9 +373,8 @@
spin_lock_irqsave(&dmov_conf[adm].list_lock, flags);
list_add_tail(&cmd->list, &dmov_conf[adm].staged_commands[ch]);
- spin_unlock_irqrestore(&dmov_conf[adm].list_lock, flags);
-
queue_work(dmov_conf[adm].cmd_wq, &cmd->work);
+ spin_unlock_irqrestore(&dmov_conf[adm].list_lock, flags);
}
void msm_dmov_enqueue_cmd_ext(unsigned id, struct msm_dmov_cmd *cmd)
diff --git a/arch/arm/mach-msm/event_timer.c b/arch/arm/mach-msm/event_timer.c
index e06dad4..9f46f68 100644
--- a/arch/arm/mach-msm/event_timer.c
+++ b/arch/arm/mach-msm/event_timer.c
@@ -193,21 +193,7 @@
unsigned long flags;
struct event_timer_info *event =
(struct event_timer_info *)data;
-
- local_irq_save(flags);
- create_hrtimer(event->node.expires);
- local_irq_restore(flags);
-}
-
-/**
- * setup_timer() : Helper function to setup timer on primary
- * core during hrtimer callback.
- * @event: event handle causing the wakeup.
- */
-static void setup_event_hrtimer(struct event_timer_info *event)
-{
struct timerqueue_node *next;
- unsigned long flags;
spin_lock_irqsave(&event_timer_lock, flags);
if (is_event_active(event))
@@ -223,9 +209,18 @@
if (msm_event_debug_mask && MSM_EVENT_TIMER_DEBUG)
pr_info("%s: Setting timer for %lu", __func__,
(unsigned long)ktime_to_ns(event->node.expires));
+ create_hrtimer(event->node.expires);
+ }
+}
- smp_call_function_single(0, create_timer_smp, event, 1);
- }
+/**
+ * setup_timer() : Helper function to setup timer on primary
+ * core during hrtimer callback.
+ * @event: event handle causing the wakeup.
+ */
+static void setup_event_hrtimer(struct event_timer_info *event)
+{
+ smp_call_function_single(0, create_timer_smp, event, 1);
}
/**
diff --git a/arch/arm/mach-msm/include/mach/irqs-8064.h b/arch/arm/mach-msm/include/mach/irqs-8064.h
index 973034b..f4129fe 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8064.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8064.h
@@ -15,15 +15,6 @@
/* MSM ACPU Interrupt Numbers */
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#define INT_VGIC (GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8092.h b/arch/arm/mach-msm/include/mach/irqs-8092.h
index dfe21c2..955e669 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8092.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8092.h
@@ -15,24 +15,12 @@
/* MSM ACPU Interrupt Numbers */
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
-#define AVS_SVICINT (GIC_PPI_START + 6)
-#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
/* PPI 15 is unused */
#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
-#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8226.h b/arch/arm/mach-msm/include/mach/irqs-8226.h
deleted file mode 100644
index abc62d2..0000000
--- a/arch/arm/mach-msm/include/mach/irqs-8226.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MSM_IRQS_8226_H
-#define __ASM_ARCH_MSM_IRQS_8226_H
-
-/* MSM ACPU Interrupt Numbers */
-
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
-#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
-/* PPI 15 is unused */
-
-#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
-#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
-#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
index f591a9e..a83dd2e 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -13,9 +13,6 @@
#ifndef __ASM_ARCH_MSM_IRQS_8625_H
#define __ASM_ARCH_MSM_IRQS_8625_H
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#ifdef CONFIG_MSM_FIQ
#define FIQ_START 0
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8910.h b/arch/arm/mach-msm/include/mach/irqs-8910.h
deleted file mode 100644
index 635c044..0000000
--- a/arch/arm/mach-msm/include/mach/irqs-8910.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MSM_IRQS_8910_H
-#define __ASM_ARCH_MSM_IRQS_8910_H
-
-/* MSM ACPU Interrupt Numbers */
-
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
-#define INT_ARMQC_PERFMON (GIC_PPI_START + 10)
-
-#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
-#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
-#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8930.h b/arch/arm/mach-msm/include/mach/irqs-8930.h
index bfc32f6..fbde7cb 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8930.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8930.h
@@ -15,13 +15,6 @@
/* MSM ACPU Interrupt Numbers */
-/* 0-15: STI/SGI (software triggered/generated interrupts)
- 16-31: PPI (private peripheral interrupts)
- 32+: SPI (shared peripheral interrupts) */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#define INT_VGIC (GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
index 012dd74..64be113 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -15,13 +15,6 @@
/* MSM ACPU Interrupt Numbers */
-/* 0-15: STI/SGI (software triggered/generated interrupts)
- 16-31: PPI (private peripheral interrupts)
- 32+: SPI (shared peripheral interrupts) */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#define INT_VGIC (GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8974.h b/arch/arm/mach-msm/include/mach/irqs-8974.h
index 150b2ee..f18b3df 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8974.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8974.h
@@ -15,22 +15,12 @@
/* MSM ACPU Interrupt Numbers */
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#define INT_ARMQC_PERFMON (GIC_PPI_START + 7)
/* PPI 15 is unused */
#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
-#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index c9729f4..d08f645 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -16,13 +16,6 @@
/* MSM ACPU Interrupt Numbers */
-/* 0-15: STI/SGI (software triggered/generated interrupts)
- 16-31: PPI (private peripheral interrupts)
- 32+: SPI (shared peripheral interrupts) */
-
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
-
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/include/mach/irqs-9615.h b/arch/arm/mach-msm/include/mach/irqs-9615.h
index 39058a6..b9c66c3 100644
--- a/arch/arm/mach-msm/include/mach/irqs-9615.h
+++ b/arch/arm/mach-msm/include/mach/irqs-9615.h
@@ -15,15 +15,7 @@
/* MSM ACPU Interrupt Numbers */
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
#define FIQ_START 16
-#define GIC_PPI_START 16
-#define GIC_SPI_START 32
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
diff --git a/arch/arm/mach-msm/include/mach/irqs-9625.h b/arch/arm/mach-msm/include/mach/irqs-9625.h
index b1f65d1..15c7010 100644
--- a/arch/arm/mach-msm/include/mach/irqs-9625.h
+++ b/arch/arm/mach-msm/include/mach/irqs-9625.h
@@ -15,18 +15,8 @@
/* MSM ACPU Interrupt Numbers */
-/*
- * 0-15: STI/SGI (software triggered/generated interrupts)
- * 16-31: PPI (private peripheral interrupts)
- * 32+: SPI (shared peripheral interrupts)
- */
-
-#define GIC_PPI_START 16
-
#define INT_ARMQC_PERFMON (GIC_PPI_START + 7)
-#define GIC_SPI_START 32
-
#define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ
#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 7837c79..f5822fc 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -17,6 +17,14 @@
#ifndef __ASM_ARCH_MSM_IRQS_H
#define __ASM_ARCH_MSM_IRQS_H
+/*
+ * 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MPQ8092)
@@ -37,14 +45,8 @@
#define NR_MSM_GPIOS NR_GPIO_IRQS
#elif defined(CONFIG_ARCH_MSM8910) || defined(CONFIG_ARCH_MSM8226)
-#ifdef CONFIG_ARCH_MSM8910
-#include "irqs-8910.h"
-#endif
-#ifdef CONFIG_ARCH_MSM8226
-#include "irqs-8226.h"
-#endif
-
+#define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 208)
#define NR_MSM_IRQS 256
#define NR_GPIO_IRQS 117
#define NR_QPNP_IRQS 32768
diff --git a/arch/arm/mach-msm/msm_mpdecision.c b/arch/arm/mach-msm/msm_mpdecision.c
index 94b546a..910804b 100644
--- a/arch/arm/mach-msm/msm_mpdecision.c
+++ b/arch/arm/mach-msm/msm_mpdecision.c
@@ -360,6 +360,7 @@
int cpu;
while (1) {
+ msm_dcvs_update_algo_params();
wait_event(msm_mpd.wait_hpq, *event || kthread_should_stop());
if (kthread_should_stop())
break;
@@ -392,7 +393,6 @@
}
msm_mpd.hpupdate = HPUPDATE_WAITING;
msm_dcvs_apply_gpu_floor(0);
- msm_dcvs_update_algo_params();
}
return 0;
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index 07cbe19..b8309e5 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -56,6 +56,9 @@
#define RMB_PMI_CODE_START 0x14
#define RMB_PMI_CODE_LENGTH 0x18
+#define VDD_MSS_UV 1050000
+#define MAX_VDD_MX_UV 1050000
+
#define PROXY_TIMEOUT_MS 10000
#define POLL_INTERVAL_US 50
@@ -99,7 +102,7 @@
ret = regulator_enable(drv->vreg);
if (ret)
- dev_err(dev, "Failed to enable regulator.\n");
+ dev_err(dev, "Failed to enable modem regulator.\n");
return ret;
}
@@ -264,9 +267,44 @@
return ret;
}
+static int pil_q6v5_mss_make_proxy_votes(struct pil_desc *pil)
+{
+ int ret;
+ struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
+
+ ret = regulator_set_voltage(drv->vreg_mx, VDD_MSS_UV, MAX_VDD_MX_UV);
+ if (ret) {
+ dev_err(pil->dev, "Failed to request vreg_mx voltage\n");
+ return ret;
+ }
+
+ ret = regulator_enable(drv->vreg_mx);
+ if (ret) {
+ dev_err(pil->dev, "Failed to enable vreg_mx\n");
+ regulator_set_voltage(drv->vreg_mx, 0, MAX_VDD_MX_UV);
+ return ret;
+ }
+
+ ret = pil_q6v5_make_proxy_votes(pil);
+ if (ret) {
+ regulator_disable(drv->vreg_mx);
+ regulator_set_voltage(drv->vreg_mx, 0, MAX_VDD_MX_UV);
+ }
+
+ return ret;
+}
+
+static void pil_q6v5_mss_remove_proxy_votes(struct pil_desc *pil)
+{
+ struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
+ pil_q6v5_remove_proxy_votes(pil);
+ regulator_disable(drv->vreg_mx);
+ regulator_set_voltage(drv->vreg_mx, 0, MAX_VDD_MX_UV);
+}
+
static struct pil_reset_ops pil_mss_ops = {
- .proxy_vote = pil_q6v5_make_proxy_votes,
- .proxy_unvote = pil_q6v5_remove_proxy_votes,
+ .proxy_vote = pil_q6v5_mss_make_proxy_votes,
+ .proxy_unvote = pil_q6v5_mss_remove_proxy_votes,
.auth_and_reset = pil_mss_reset,
.shutdown = pil_mss_shutdown,
};
@@ -674,7 +712,11 @@
if (IS_ERR(q6->vreg))
return PTR_ERR(q6->vreg);
- ret = regulator_set_voltage(q6->vreg, 1050000, 1050000);
+ q6->vreg_mx = devm_regulator_get(&pdev->dev, "vdd_mx");
+ if (IS_ERR(q6->vreg_mx))
+ return PTR_ERR(q6->vreg_mx);
+
+ ret = regulator_set_voltage(q6->vreg, VDD_MSS_UV, VDD_MSS_UV);
if (ret)
dev_err(&pdev->dev, "Failed to set regulator's voltage.\n");
diff --git a/arch/arm/mach-msm/pil-q6v5.h b/arch/arm/mach-msm/pil-q6v5.h
index ecdaf9b..d9ad6ae 100644
--- a/arch/arm/mach-msm/pil-q6v5.h
+++ b/arch/arm/mach-msm/pil-q6v5.h
@@ -31,6 +31,7 @@
void __iomem *axi_halt_base;
void __iomem *restart_reg;
struct regulator *vreg;
+ struct regulator *vreg_mx;
bool is_booted;
struct pil_desc desc;
};
diff --git a/arch/arm/mach-msm/pil-venus.c b/arch/arm/mach-msm/pil-venus.c
index 47799cc..103fd9f 100644
--- a/arch/arm/mach-msm/pil-venus.c
+++ b/arch/arm/mach-msm/pil-venus.c
@@ -28,6 +28,8 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/subsystem_restart.h>
+#include <mach/msm_bus_board.h>
+#include <mach/msm_bus.h>
#include "peripheral-loader.h"
#include "scm-pas.h"
@@ -77,6 +79,7 @@
u32 fw_sz;
u32 fw_min_paddr;
u32 fw_max_paddr;
+ u32 bus_perf_client;
};
#define subsys_to_drv(d) container_of(d, struct venus_data, subsys_desc)
@@ -147,6 +150,41 @@
clk_disable_unprepare(drv->clks[i]);
}
+static struct msm_bus_vectors pil_venus_unvote_bw_vector[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 0,
+ },
+};
+
+static struct msm_bus_vectors pil_venus_vote_bw_vector[] = {
+ {
+ .src = MSM_BUS_MASTER_VIDEO_P0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 0,
+ .ib = 16 * 19 * 1000000UL, /* At least 19.2MHz on bus. */
+ },
+};
+
+static struct msm_bus_paths pil_venus_bw_tbl[] = {
+ {
+ .num_paths = ARRAY_SIZE(pil_venus_unvote_bw_vector),
+ .vectors = pil_venus_unvote_bw_vector,
+ },
+ {
+ .num_paths = ARRAY_SIZE(pil_venus_vote_bw_vector),
+ .vectors = pil_venus_vote_bw_vector,
+ },
+};
+
+static struct msm_bus_scale_pdata pil_venus_client_pdata = {
+ .usecase = pil_venus_bw_tbl,
+ .num_usecases = ARRAY_SIZE(pil_venus_bw_tbl),
+ .name = "pil-venus",
+};
+
static int pil_venus_make_proxy_vote(struct pil_desc *pil)
{
struct venus_data *drv = dev_get_drvdata(pil->dev);
@@ -161,13 +199,28 @@
rc = regulator_enable(drv->gdsc);
if (rc) {
dev_err(pil->dev, "GDSC enable failed\n");
- return rc;
+ goto err_regulator;
}
rc = venus_clock_prepare_enable(pil->dev);
- if (rc)
- regulator_disable(drv->gdsc);
+ if (rc) {
+ dev_err(pil->dev, "clock prepare and enable failed\n");
+ goto err_clock;
+ }
+ rc = msm_bus_scale_client_update_request(drv->bus_perf_client, 1);
+ if (rc) {
+ dev_err(pil->dev, "bandwith request failed\n");
+ goto err_bw;
+ }
+
+ return 0;
+
+err_bw:
+ venus_clock_disable_unprepare(pil->dev);
+err_clock:
+ regulator_disable(drv->gdsc);
+err_regulator:
return rc;
}
@@ -175,6 +228,8 @@
{
struct venus_data *drv = dev_get_drvdata(pil->dev);
+ msm_bus_scale_client_update_request(drv->bus_perf_client, 0);
+
venus_clock_disable_unprepare(pil->dev);
/* Disable GDSC */
@@ -438,6 +493,13 @@
if (rc)
return rc;
+ drv->bus_perf_client =
+ msm_bus_scale_register_client(&pil_venus_client_pdata);
+ if (!drv->bus_perf_client) {
+ dev_err(&pdev->dev, "Failed to register bus client\n");
+ return -EINVAL;
+ }
+
drv->iommu_fw_ctx = msm_iommu_get_ctx("venus_fw");
if (!drv->iommu_fw_ctx) {
dev_err(&pdev->dev, "No iommu fw context found\n");
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
index a4a6b906..ad5f1b5 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
@@ -25,6 +25,9 @@
#include <asm/ioctls.h>
#include <linux/debugfs.h>
#include "audio_utils_aio.h"
+#ifdef CONFIG_USE_DEV_CTRL_VOLUME
+#include <mach/qdsp6v2/audio_dev_ctl.h>
+#endif /*CONFIG_USE_DEV_CTRL_VOLUME*/
#ifdef CONFIG_DEBUG_FS
ssize_t audio_aio_debug_open(struct inode *inode, struct file *file)
@@ -424,6 +427,67 @@
}
}
+#ifdef CONFIG_USE_DEV_CTRL_VOLUME
+
+static void audio_aio_listner(u32 evt_id, union auddev_evt_data *evt_payload,
+ void *private_data)
+{
+ struct q6audio_aio *audio = (struct q6audio_aio *) private_data;
+ int rc = 0;
+
+ switch (evt_id) {
+ case AUDDEV_EVT_STREAM_VOL_CHG:
+ audio->volume = evt_payload->session_vol;
+ pr_debug("%s[%p]: AUDDEV_EVT_STREAM_VOL_CHG, stream vol %d, enabled = %d\n",
+ __func__, audio, audio->volume, audio->enabled);
+ if (audio->enabled == 1) {
+ if (audio->ac) {
+ rc = q6asm_set_volume(audio->ac, audio->volume);
+ if (rc < 0) {
+ pr_err("%s[%p]: Send Volume command failed rc=%d\n",
+ __func__, audio, rc);
+ }
+ }
+ }
+ break;
+ default:
+ pr_err("%s[%p]:ERROR:wrong event\n", __func__, audio);
+ break;
+ }
+}
+
+int register_volume_listener(struct q6audio_aio *audio)
+{
+ int rc = 0;
+ audio->device_events = AUDDEV_EVT_STREAM_VOL_CHG;
+ audio->drv_status &= ~ADRV_STATUS_PAUSE;
+
+ rc = auddev_register_evt_listner(audio->device_events,
+ AUDDEV_CLNT_DEC,
+ audio->ac->session,
+ audio_aio_listner,
+ (void *)audio);
+ if (rc < 0) {
+ pr_err("%s[%p]: Event listener failed\n", __func__, audio);
+ rc = -EACCES;
+ }
+ return rc;
+}
+void unregister_volume_listener(struct q6audio_aio *audio)
+{
+ auddev_unregister_evt_listner(AUDDEV_CLNT_DEC, audio->ac->session);
+}
+#else /*CONFIG_USE_DEV_CTRL_VOLUME*/
+int register_volume_listener(struct q6audio_aio *audio)
+{
+ return 0;/* do nothing */
+}
+void unregister_volume_listener(struct q6audio_aio *audio)
+{
+ return;/* do nothing */
+}
+#endif /*CONFIG_USE_DEV_CTRL_VOLUME*/
+
int audio_aio_release(struct inode *inode, struct file *file)
{
struct q6audio_aio *audio = file->private_data;
@@ -448,6 +512,8 @@
mutex_destroy(&audio->read_lock);
mutex_destroy(&audio->write_lock);
mutex_destroy(&audio->get_event_lock);
+ unregister_volume_listener(audio);
+
#ifdef CONFIG_DEBUG_FS
if (audio->dentry)
debugfs_remove(audio->dentry);
@@ -1049,7 +1115,13 @@
goto fail;
}
pr_debug("Ion client create in audio_aio_open %p", audio->client);
+
+ rc = register_volume_listener(audio);
+ if (rc < 0)
+ goto fail;
+
return 0;
+
fail:
q6asm_audio_client_free(audio->ac);
kfree(audio->codec_cfg);
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
index dedf991..d518254 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.h
@@ -1,6 +1,6 @@
/* Copyright (C) 2008 Google, Inc.
* Copyright (C) 2008 HTC Corporation
- * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -176,7 +176,8 @@
struct ion_client *client;
struct audio_aio_drv_operations drv_ops;
union msm_audio_event_payload eos_write_payload;
-
+ uint32_t device_events;
+ uint16_t volume;
uint32_t drv_status;
int event_abort;
int eos_rsp;
diff --git a/drivers/gpu/ion/Makefile b/drivers/gpu/ion/Makefile
index c9e8a94..51349f6 100644
--- a/drivers/gpu/ion/Makefile
+++ b/drivers/gpu/ion/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_ION) += ion.o ion_heap.o ion_system_heap.o ion_carveout_heap.o ion_iommu_heap.o ion_cp_heap.o
+obj-$(CONFIG_CMA) += ion_cma_heap.o
obj-$(CONFIG_ION_TEGRA) += tegra/
obj-$(CONFIG_ION_MSM) += msm/
diff --git a/drivers/gpu/ion/ion_cma_heap.c b/drivers/gpu/ion/ion_cma_heap.c
new file mode 100644
index 0000000..bef6b6f
--- /dev/null
+++ b/drivers/gpu/ion/ion_cma_heap.c
@@ -0,0 +1,342 @@
+/*
+ * drivers/gpu/ion/ion_cma_heap.c
+ *
+ * Copyright (C) Linaro 2012
+ * Author: <benjamin.gaignard@linaro.org> for ST-Ericsson.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/ion.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+#include <linux/msm_ion.h>
+#include <mach/iommu_domains.h>
+
+#include <asm/cacheflush.h>
+
+/* for ion_heap_ops structure */
+#include "ion_priv.h"
+
+#define ION_CMA_ALLOCATE_FAILED -1
+
+struct ion_cma_buffer_info {
+ void *cpu_addr;
+ dma_addr_t handle;
+ struct sg_table *table;
+ bool is_cached;
+};
+
+static int cma_heap_has_outer_cache;
+/*
+ * Create scatter-list for the already allocated DMA buffer.
+ * This function could be replace by dma_common_get_sgtable
+ * as soon as it will avalaible.
+ */
+int ion_cma_get_sgtable(struct device *dev, struct sg_table *sgt,
+ void *cpu_addr, dma_addr_t handle, size_t size)
+{
+ struct page *page = virt_to_page(cpu_addr);
+ int ret;
+
+ ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
+ if (unlikely(ret))
+ return ret;
+
+ sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
+ return 0;
+}
+
+/* ION CMA heap operations functions */
+static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer,
+ unsigned long len, unsigned long align,
+ unsigned long flags)
+{
+ struct device *dev = heap->priv;
+ struct ion_cma_buffer_info *info;
+
+ dev_dbg(dev, "Request buffer allocation len %ld\n", len);
+
+ info = kzalloc(sizeof(struct ion_cma_buffer_info), GFP_KERNEL);
+ if (!info) {
+ dev_err(dev, "Can't allocate buffer info\n");
+ return ION_CMA_ALLOCATE_FAILED;
+ }
+
+ if (!ION_IS_CACHED(flags))
+ info->cpu_addr = dma_alloc_writecombine(dev, len,
+ &(info->handle), 0);
+ else
+ info->cpu_addr = dma_alloc_nonconsistent(dev, len,
+ &(info->handle), 0);
+
+ if (!info->cpu_addr) {
+ dev_err(dev, "Fail to allocate buffer\n");
+ goto err;
+ }
+
+ info->table = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
+ if (!info->table) {
+ dev_err(dev, "Fail to allocate sg table\n");
+ goto err;
+ }
+
+ info->is_cached = ION_IS_CACHED(flags);
+
+ ion_cma_get_sgtable(dev,
+ info->table, info->cpu_addr, info->handle, len);
+
+ /* keep this for memory release */
+ buffer->priv_virt = info;
+ dev_dbg(dev, "Allocate buffer %p\n", buffer);
+ return 0;
+
+err:
+ kfree(info);
+ return ION_CMA_ALLOCATE_FAILED;
+}
+
+static void ion_cma_free(struct ion_buffer *buffer)
+{
+ struct device *dev = buffer->heap->priv;
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ dev_dbg(dev, "Release buffer %p\n", buffer);
+ /* release memory */
+ dma_free_coherent(dev, buffer->size, info->cpu_addr, info->handle);
+ /* release sg table */
+ kfree(info->table);
+ kfree(info);
+}
+
+/* return physical address in addr */
+static int ion_cma_phys(struct ion_heap *heap, struct ion_buffer *buffer,
+ ion_phys_addr_t *addr, size_t *len)
+{
+ struct device *dev = heap->priv;
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ dev_dbg(dev, "Return buffer %p physical address 0x%x\n", buffer,
+ info->handle);
+
+ *addr = info->handle;
+ *len = buffer->size;
+
+ return 0;
+}
+
+struct sg_table *ion_cma_heap_map_dma(struct ion_heap *heap,
+ struct ion_buffer *buffer)
+{
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ return info->table;
+}
+
+void ion_cma_heap_unmap_dma(struct ion_heap *heap,
+ struct ion_buffer *buffer)
+{
+ return;
+}
+
+static int ion_cma_mmap(struct ion_heap *mapper, struct ion_buffer *buffer,
+ struct vm_area_struct *vma)
+{
+ struct device *dev = buffer->heap->priv;
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ if (info->is_cached)
+ return dma_mmap_nonconsistent(dev, vma, info->cpu_addr,
+ info->handle, buffer->size);
+ else
+ return dma_mmap_writecombine(dev, vma, info->cpu_addr,
+ info->handle, buffer->size);
+}
+
+static void *ion_cma_map_kernel(struct ion_heap *heap,
+ struct ion_buffer *buffer)
+{
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ return info->cpu_addr;
+}
+
+static void ion_cma_unmap_kernel(struct ion_heap *heap,
+ struct ion_buffer *buffer)
+{
+ return;
+}
+
+int ion_cma_map_iommu(struct ion_buffer *buffer,
+ struct ion_iommu_map *data,
+ unsigned int domain_num,
+ unsigned int partition_num,
+ unsigned long align,
+ unsigned long iova_length,
+ unsigned long flags)
+{
+ int ret = 0;
+ struct iommu_domain *domain;
+ unsigned long extra;
+ unsigned long extra_iova_addr;
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+ struct sg_table *table = info->table;
+ int prot = IOMMU_WRITE | IOMMU_READ;
+
+ data->mapped_size = iova_length;
+
+ if (!msm_use_iommu()) {
+ data->iova_addr = info->handle;
+ return 0;
+ }
+
+ extra = iova_length - buffer->size;
+
+ ret = msm_allocate_iova_address(domain_num, partition_num,
+ data->mapped_size, align,
+ &data->iova_addr);
+
+ if (ret)
+ goto out;
+
+ domain = msm_get_iommu_domain(domain_num);
+
+ if (!domain) {
+ ret = -EINVAL;
+ goto out1;
+ }
+
+ ret = iommu_map_range(domain, data->iova_addr, table->sgl,
+ buffer->size, prot);
+
+ if (ret) {
+ pr_err("%s: could not map %lx in domain %p\n",
+ __func__, data->iova_addr, domain);
+ goto out1;
+ }
+
+ extra_iova_addr = data->iova_addr + buffer->size;
+ if (extra) {
+ ret = msm_iommu_map_extra(domain, extra_iova_addr, extra, SZ_4K,
+ prot);
+ if (ret)
+ goto out2;
+ }
+ return ret;
+
+out2:
+ iommu_unmap_range(domain, data->iova_addr, buffer->size);
+out1:
+ msm_free_iova_address(data->iova_addr, domain_num, partition_num,
+ data->mapped_size);
+out:
+ return ret;
+}
+
+
+void ion_cma_unmap_iommu(struct ion_iommu_map *data)
+{
+ unsigned int domain_num;
+ unsigned int partition_num;
+ struct iommu_domain *domain;
+
+ if (!msm_use_iommu())
+ return;
+
+ domain_num = iommu_map_domain(data);
+ partition_num = iommu_map_partition(data);
+
+ domain = msm_get_iommu_domain(domain_num);
+
+ if (!domain) {
+ WARN(1, "Could not get domain %d. Corruption?\n", domain_num);
+ return;
+ }
+
+ iommu_unmap_range(domain, data->iova_addr, data->mapped_size);
+ msm_free_iova_address(data->iova_addr, domain_num, partition_num,
+ data->mapped_size);
+
+ return;
+}
+
+int ion_cma_cache_ops(struct ion_heap *heap,
+ struct ion_buffer *buffer, void *vaddr,
+ unsigned int offset, unsigned int length,
+ unsigned int cmd)
+{
+ void (*outer_cache_op)(phys_addr_t, phys_addr_t);
+
+ switch (cmd) {
+ case ION_IOC_CLEAN_CACHES:
+ dmac_clean_range(vaddr, vaddr + length);
+ outer_cache_op = outer_clean_range;
+ break;
+ case ION_IOC_INV_CACHES:
+ dmac_inv_range(vaddr, vaddr + length);
+ outer_cache_op = outer_inv_range;
+ break;
+ case ION_IOC_CLEAN_INV_CACHES:
+ dmac_flush_range(vaddr, vaddr + length);
+ outer_cache_op = outer_flush_range;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (cma_heap_has_outer_cache) {
+ struct ion_cma_buffer_info *info = buffer->priv_virt;
+
+ outer_cache_op(info->handle, info->handle + length);
+ }
+
+ return 0;
+}
+
+static struct ion_heap_ops ion_cma_ops = {
+ .allocate = ion_cma_allocate,
+ .free = ion_cma_free,
+ .map_dma = ion_cma_heap_map_dma,
+ .unmap_dma = ion_cma_heap_unmap_dma,
+ .phys = ion_cma_phys,
+ .map_user = ion_cma_mmap,
+ .map_kernel = ion_cma_map_kernel,
+ .unmap_kernel = ion_cma_unmap_kernel,
+ .map_iommu = ion_cma_map_iommu,
+ .unmap_iommu = ion_cma_unmap_iommu,
+ .cache_op = ion_cma_cache_ops,
+};
+
+struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *data)
+{
+ struct ion_heap *heap;
+
+ heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL);
+
+ if (!heap)
+ return ERR_PTR(-ENOMEM);
+
+ heap->ops = &ion_cma_ops;
+ /* set device as private heaps data, later it will be
+ * used to make the link with reserved CMA memory */
+ heap->priv = data->priv;
+ heap->type = ION_HEAP_TYPE_DMA;
+ cma_heap_has_outer_cache = data->has_outer_cache;
+ return heap;
+}
+
+void ion_cma_heap_destroy(struct ion_heap *heap)
+{
+ kfree(heap);
+}
diff --git a/drivers/gpu/ion/ion_cp_heap.c b/drivers/gpu/ion/ion_cp_heap.c
index aa3469c..96a3cdc 100644
--- a/drivers/gpu/ion/ion_cp_heap.c
+++ b/drivers/gpu/ion/ion_cp_heap.c
@@ -2,7 +2,7 @@
* drivers/gpu/ion/ion_cp_heap.c
*
* Copyright (C) 2011 Google, Inc.
- * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,7 +15,7 @@
*
*/
#include <linux/spinlock.h>
-
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/genalloc.h>
#include <linux/io.h>
@@ -28,6 +28,7 @@
#include <linux/seq_file.h>
#include <linux/fmem.h>
#include <linux/iommu.h>
+#include <linux/dma-mapping.h>
#include <asm/mach/map.h>
@@ -99,6 +100,10 @@
int iommu_2x_map_domain;
unsigned int has_outer_cache;
atomic_t protect_cnt;
+ void *cpu_addr;
+ size_t heap_size;
+ dma_addr_t handle;
+ int cma;
};
enum {
@@ -126,6 +131,8 @@
void *data;
};
+#define DMA_ALLOC_TRIES 5
+
static int ion_cp_protect_mem(unsigned int phy_base, unsigned int size,
unsigned int permission_type, int version,
void *data);
@@ -134,6 +141,71 @@
unsigned int permission_type, int version,
void *data);
+static int allocate_heap_memory(struct ion_heap *heap)
+{
+ struct device *dev = heap->priv;
+ struct ion_cp_heap *cp_heap =
+ container_of(heap, struct ion_cp_heap, heap);
+ int ret;
+ int tries = 0;
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+
+
+ if (cp_heap->cpu_addr)
+ return 0;
+
+ while (!cp_heap->cpu_addr && (++tries < DMA_ALLOC_TRIES)) {
+ cp_heap->cpu_addr = dma_alloc_attrs(dev,
+ cp_heap->heap_size,
+ &(cp_heap->handle),
+ 0,
+ &attrs);
+ if (!cp_heap->cpu_addr)
+ msleep(20);
+ }
+
+ if (!cp_heap->cpu_addr)
+ goto out;
+
+ cp_heap->base = cp_heap->handle;
+
+ cp_heap->pool = gen_pool_create(12, -1);
+ if (!cp_heap->pool)
+ goto out_free;
+
+ ret = gen_pool_add(cp_heap->pool, cp_heap->base,
+ cp_heap->heap_size, -1);
+ if (ret < 0)
+ goto out_pool;
+
+ return 0;
+
+out_pool:
+ gen_pool_destroy(cp_heap->pool);
+out_free:
+ dma_free_coherent(dev, cp_heap->heap_size, cp_heap->cpu_addr,
+ cp_heap->handle);
+out:
+ return ION_CP_ALLOCATE_FAIL;
+}
+
+static void free_heap_memory(struct ion_heap *heap)
+{
+ struct device *dev = heap->priv;
+ struct ion_cp_heap *cp_heap =
+ container_of(heap, struct ion_cp_heap, heap);
+
+ /* release memory */
+ dma_free_coherent(dev, cp_heap->heap_size, cp_heap->cpu_addr,
+ cp_heap->handle);
+ gen_pool_destroy(cp_heap->pool);
+ cp_heap->pool = NULL;
+ cp_heap->cpu_addr = 0;
+}
+
+
+
/**
* Get the total number of kernel mappings.
* Must be called with heap->lock locked.
@@ -155,6 +227,12 @@
if (ret_value)
return 1;
}
+
+ if (cp_heap->cma) {
+ ret_value = allocate_heap_memory(heap);
+ if (ret_value)
+ return 1;
+ }
return 0;
}
@@ -167,6 +245,9 @@
if (fmem_set_state(FMEM_T_STATE) != 0)
pr_err("%s: unable to transition heap to T-state\n",
__func__);
+
+ if (cp_heap->cma)
+ free_heap_memory(heap);
}
/* Must be protected by ion_cp_buffer lock */
@@ -688,7 +769,24 @@
if (cp_heap->reusable) {
ret_value = ion_map_fmem_buffer(buffer, cp_heap->base,
cp_heap->reserved_vrange, buffer->flags);
+ } else if (cp_heap->cma) {
+ int npages = PAGE_ALIGN(buffer->size) / PAGE_SIZE;
+ struct page **pages = vmalloc(
+ sizeof(struct page *) * npages);
+ int i;
+ pgprot_t pgprot;
+ if (ION_IS_CACHED(buffer->flags))
+ pgprot = PAGE_KERNEL;
+ else
+ pgprot = pgprot_writecombine(PAGE_KERNEL);
+
+ for (i = 0; i < npages; i++) {
+ pages[i] = phys_to_page(buf->buffer +
+ i * PAGE_SIZE);
+ }
+ ret_value = vmap(pages, npages, VM_IOREMAP, pgprot);
+ vfree(pages);
} else {
if (ION_IS_CACHED(buffer->flags))
ret_value = ioremap_cached(buf->buffer,
@@ -721,6 +819,8 @@
if (cp_heap->reusable)
unmap_kernel_range((unsigned long)buffer->vaddr, buffer->size);
+ else if (cp_heap->cma)
+ vunmap(buffer->vaddr);
else
__arm_iounmap(buffer->vaddr);
@@ -1148,14 +1248,6 @@
mutex_init(&cp_heap->lock);
- cp_heap->pool = gen_pool_create(12, -1);
- if (!cp_heap->pool)
- goto free_heap;
-
- cp_heap->base = heap_data->base;
- ret = gen_pool_add(cp_heap->pool, cp_heap->base, heap_data->size, -1);
- if (ret < 0)
- goto destroy_pool;
cp_heap->allocated_bytes = 0;
cp_heap->umap_count = 0;
@@ -1165,9 +1257,11 @@
cp_heap->heap.ops = &cp_heap_ops;
cp_heap->heap.type = (enum ion_heap_type) ION_HEAP_TYPE_CP;
cp_heap->heap_protected = HEAP_NOT_PROTECTED;
- cp_heap->secure_base = cp_heap->base;
+ cp_heap->secure_base = heap_data->base;
cp_heap->secure_size = heap_data->size;
cp_heap->has_outer_cache = heap_data->has_outer_cache;
+ cp_heap->heap_size = heap_data->size;
+
atomic_set(&cp_heap->protect_cnt, 0);
if (heap_data->extra_data) {
struct ion_cp_heap_pdata *extra_data =
@@ -1191,9 +1285,26 @@
extra_data->iommu_map_all;
cp_heap->iommu_2x_map_domain =
extra_data->iommu_2x_map_domain;
+ cp_heap->cma = extra_data->is_cma;
}
+ if (cp_heap->cma) {
+ cp_heap->pool = NULL;
+ cp_heap->cpu_addr = 0;
+ cp_heap->heap.priv = heap_data->priv;
+ } else {
+ cp_heap->pool = gen_pool_create(12, -1);
+ if (!cp_heap->pool)
+ goto free_heap;
+
+ cp_heap->base = heap_data->base;
+ ret = gen_pool_add(cp_heap->pool, cp_heap->base,
+ heap_data->size, -1);
+ if (ret < 0)
+ goto destroy_pool;
+
+ }
return &cp_heap->heap;
destroy_pool:
diff --git a/drivers/gpu/ion/ion_heap.c b/drivers/gpu/ion/ion_heap.c
index 4c83d75..0670468 100644
--- a/drivers/gpu/ion/ion_heap.c
+++ b/drivers/gpu/ion/ion_heap.c
@@ -40,6 +40,11 @@
case ION_HEAP_TYPE_CP:
heap = ion_cp_heap_create(heap_data);
break;
+#ifdef CONFIG_CMA
+ case ION_HEAP_TYPE_DMA:
+ heap = ion_cma_heap_create(heap_data);
+ break;
+#endif
default:
pr_err("%s: Invalid heap type %d\n", __func__,
heap_data->type);
@@ -55,6 +60,7 @@
heap->name = heap_data->name;
heap->id = heap_data->id;
+ heap->priv = heap_data->priv;
return heap;
}
@@ -79,6 +85,11 @@
case ION_HEAP_TYPE_CP:
ion_cp_heap_destroy(heap);
break;
+#ifdef CONFIG_CMA
+ case ION_HEAP_TYPE_DMA:
+ ion_cma_heap_destroy(heap);
+ break;
+#endif
default:
pr_err("%s: Invalid heap type %d\n", __func__,
heap->type);
diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h
index 991a310..7713875 100644
--- a/drivers/gpu/ion/ion_priv.h
+++ b/drivers/gpu/ion/ion_priv.h
@@ -162,6 +162,7 @@
* allocating. These are specified by platform data and
* MUST be unique
* @name: used for debugging
+ * @priv: private heap data
*
* Represents a pool of memory from which buffers can be made. In some
* systems the only heap is regular system memory allocated via vmalloc.
@@ -175,6 +176,7 @@
struct ion_heap_ops *ops;
int id;
const char *name;
+ void *priv;
};
/**
@@ -257,6 +259,10 @@
void ion_carveout_free(struct ion_heap *heap, ion_phys_addr_t addr,
unsigned long size);
+#ifdef CONFIG_CMA
+struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *);
+void ion_cma_heap_destroy(struct ion_heap *);
+#endif
struct ion_heap *msm_get_contiguous_heap(void);
/**
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index 8699178..e422fd26 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -424,6 +424,7 @@
unsigned int i;
for (i = 0; i < pdata->nr; ++i)
kfree(pdata->heaps[i].extra_data);
+ kfree(pdata->heaps);
kfree(pdata);
}
@@ -553,6 +554,7 @@
const struct device_node *dt_node)
{
struct ion_platform_data *pdata = 0;
+ struct ion_platform_heap *heaps = NULL;
struct device_node *node;
uint32_t val = 0;
int ret = 0;
@@ -565,11 +567,17 @@
if (!num_heaps)
return ERR_PTR(-EINVAL);
- pdata = kzalloc(sizeof(struct ion_platform_data) +
- num_heaps*sizeof(struct ion_platform_heap), GFP_KERNEL);
+ pdata = kzalloc(sizeof(struct ion_platform_data), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
+ heaps = kzalloc(sizeof(struct ion_platform_heap)*num_heaps, GFP_KERNEL);
+ if (!heaps) {
+ kfree(pdata);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ pdata->heaps = heaps;
pdata->nr = num_heaps;
for_each_child_of_node(dt_node, node) {
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 61378fe..cf16995 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -168,6 +168,9 @@
extern const unsigned int a3xx_registers[];
extern const unsigned int a3xx_registers_count;
+extern const unsigned int a3xx_hlsq_registers[];
+extern const unsigned int a3xx_hlsq_registers_count;
+
extern const unsigned int a330_registers[];
extern const unsigned int a330_registers_count;
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index feced43..2466a5c 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -40,8 +40,8 @@
0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
- 0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5, 0x0e00, 0x0e05,
- 0x0e0c, 0x0e0c, 0x0e22, 0x0e23, 0x0e41, 0x0e45, 0x0e64, 0x0e65,
+ 0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5,
+ 0x0e41, 0x0e45, 0x0e64, 0x0e65,
0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
@@ -49,7 +49,7 @@
0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
- 0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a, 0x2240, 0x227e,
+ 0x2240, 0x227e,
0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
0x22ff, 0x22ff, 0x2340, 0x2343, 0x2348, 0x2349, 0x2350, 0x2356,
@@ -58,7 +58,7 @@
0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3, 0x24e4, 0x24ef,
0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e, 0x2510, 0x2511,
0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea, 0x25ec, 0x25ed,
- 0x25f0, 0x25f0, 0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
+ 0x25f0, 0x25f0,
0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0, 0x26c4, 0x26ce,
0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9, 0x26ec, 0x26ec,
0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743, 0x2748, 0x2749,
@@ -69,6 +69,18 @@
const unsigned int a3xx_registers_count = ARRAY_SIZE(a3xx_registers) / 2;
+/* Removed the following HLSQ register ranges from being read during
+ * recovery since reading the registers may cause the device to hang:
+ */
+const unsigned int a3xx_hlsq_registers[] = {
+ 0x0e00, 0x0e05, 0x0e0c, 0x0e0c, 0x0e22, 0x0e23,
+ 0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a,
+ 0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
+};
+
+const unsigned int a3xx_hlsq_registers_count =
+ ARRAY_SIZE(a3xx_hlsq_registers) / 2;
+
/* The set of additional registers to be dumped for A330 */
const unsigned int a330_registers[] = {
diff --git a/drivers/gpu/msm/adreno_a3xx_snapshot.c b/drivers/gpu/msm/adreno_a3xx_snapshot.c
index 1243dd0..de95951 100644
--- a/drivers/gpu/msm/adreno_a3xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a3xx_snapshot.c
@@ -341,6 +341,41 @@
return snapshot;
}
+static void _snapshot_a3xx_regs(struct kgsl_snapshot_registers *regs,
+ struct kgsl_snapshot_registers_list *list)
+{
+ regs[list->count].regs = (unsigned int *) a3xx_registers;
+ regs[list->count].count = a3xx_registers_count;
+ list->count++;
+}
+
+static void _snapshot_hlsq_regs(struct kgsl_snapshot_registers *regs,
+ struct kgsl_snapshot_registers_list *list,
+ struct adreno_device *adreno_dev)
+{
+ /* HLSQ specific registers */
+ /*
+ * Don't dump any a3xx HLSQ registers just yet. Reading the HLSQ
+ * registers can cause the device to hang if the HLSQ block is
+ * busy. Add specific checks for each a3xx core as the requirements
+ * are discovered. Disable by default for now.
+ */
+ if (!adreno_is_a3xx(adreno_dev)) {
+ regs[list->count].regs = (unsigned int *) a3xx_hlsq_registers;
+ regs[list->count].count = a3xx_hlsq_registers_count;
+ list->count++;
+ }
+}
+
+static void _snapshot_a330_regs(struct kgsl_snapshot_registers *regs,
+ struct kgsl_snapshot_registers_list *list)
+{
+ /* For A330, append the additional list of new registers to grab */
+ regs[list->count].regs = (unsigned int *) a330_registers;
+ regs[list->count].count = a330_registers_count;
+ list->count++;
+}
+
/* A3XX GPU snapshot function - this is where all of the A3XX specific
* bits and pieces are grabbed into the snapshot memory
*/
@@ -350,21 +385,20 @@
{
struct kgsl_device *device = &adreno_dev->dev;
struct kgsl_snapshot_registers_list list;
- struct kgsl_snapshot_registers regs[2];
+ struct kgsl_snapshot_registers regs[5];
int size;
- regs[0].regs = (unsigned int *) a3xx_registers;
- regs[0].count = a3xx_registers_count;
-
list.registers = regs;
- list.count = 1;
+ list.count = 0;
- /* For A330, append the additional list of new registers to grab */
- if (adreno_is_a330(adreno_dev)) {
- regs[1].regs = (unsigned int *) a330_registers;
- regs[1].count = a330_registers_count;
- list.count++;
- }
+ /* Disable Clock gating temporarily for the debug bus to work */
+ adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00);
+
+ /* Store relevant registers in list to snapshot */
+ _snapshot_a3xx_regs(regs, &list);
+ _snapshot_hlsq_regs(regs, &list, adreno_dev);
+ if (adreno_is_a330(adreno_dev))
+ _snapshot_a330_regs(regs, &list);
/* Master set of (non debug) registers */
snapshot = kgsl_snapshot_add_section(device,
@@ -385,9 +419,6 @@
remain, REG_CP_ME_CNTL, REG_CP_ME_STATUS,
64, 44);
- /* Disable Clock gating temporarily for the debug bus to work */
- adreno_regwrite(device, A3XX_RBBM_CLOCK_CTL, 0x00);
-
/* VPC memory */
snapshot = kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUG, snapshot, remain,
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 27343c5..8af361a 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -513,7 +513,7 @@
if (context && context->flags & CTXT_FLAGS_PER_CONTEXT_TS)
context_id = context->id;
- if ((context->flags & CTXT_FLAGS_USER_GENERATED_TS) &&
+ if ((context && context->flags & CTXT_FLAGS_USER_GENERATED_TS) &&
(!(flags & KGSL_CMD_FLAGS_INTERNAL_ISSUE))) {
if (timestamp_cmp(rb->timestamp[context_id],
timestamp) >= 0) {
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 0b445d6..deafa7a 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -28,6 +28,7 @@
#include <linux/msm_ion.h>
#include <linux/io.h>
#include <mach/socinfo.h>
+#include <linux/mman.h>
#include "kgsl.h"
#include "kgsl_debugfs.h"
@@ -1078,6 +1079,58 @@
}
/**
+ * kgsl_sharedmem_region_empty - Check if an addression region is empty
+ *
+ * @private: private data for the process to check.
+ * @gpuaddr: start address of the region
+ * @size: length of the region.
+ *
+ * Checks that there are no existing allocations within an address
+ * region. Note that unlike other kgsl_sharedmem* search functions,
+ * this one manages locking on its own.
+ */
+int
+kgsl_sharedmem_region_empty(struct kgsl_process_private *private,
+ unsigned int gpuaddr, size_t size)
+{
+ int result = 1;
+ unsigned int gpuaddr_end = gpuaddr + size;
+
+ struct rb_node *node = private->mem_rb.rb_node;
+
+ if (!kgsl_mmu_gpuaddr_in_range(gpuaddr))
+ return 0;
+
+ /* don't overflow */
+ if (gpuaddr_end < gpuaddr)
+ return 0;
+
+ spin_lock(&private->mem_lock);
+ node = private->mem_rb.rb_node;
+ while (node != NULL) {
+ struct kgsl_mem_entry *entry;
+ unsigned int memdesc_start, memdesc_end;
+
+ entry = rb_entry(node, struct kgsl_mem_entry, node);
+
+ memdesc_start = entry->memdesc.gpuaddr;
+ memdesc_end = memdesc_start
+ + kgsl_memdesc_mmapsize(&entry->memdesc);
+
+ if (gpuaddr_end <= memdesc_start)
+ node = node->rb_left;
+ else if (memdesc_end <= gpuaddr)
+ node = node->rb_right;
+ else {
+ result = 0;
+ break;
+ }
+ }
+ spin_unlock(&private->mem_lock);
+ return result;
+}
+
+/**
* kgsl_sharedmem_find_id - find a memory entry by id
* @process: the owning process
* @id: id to find
@@ -1648,6 +1701,8 @@
entry->memdesc.size = size;
entry->memdesc.physaddr = phys + offset;
entry->memdesc.hostptr = (void *) (virt + offset);
+ /* USE_CPU_MAP is not impemented for PMEM. */
+ entry->memdesc.flags &= ~KGSL_MEMFLAGS_USE_CPU_MAP;
ret = memdesc_sg_phys(&entry->memdesc, phys + offset, size);
if (ret)
@@ -1764,6 +1819,8 @@
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = size;
entry->memdesc.useraddr = useraddr + (offset & PAGE_MASK);
+ if (kgsl_memdesc_use_cpu_map(&entry->memdesc))
+ entry->memdesc.gpuaddr = entry->memdesc.useraddr;
return memdesc_sg_virt(&entry->memdesc, entry->memdesc.useraddr,
size);
@@ -1816,6 +1873,8 @@
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = ALIGN(size, PAGE_SIZE);
entry->memdesc.useraddr = useraddr;
+ if (kgsl_memdesc_use_cpu_map(&entry->memdesc))
+ entry->memdesc.gpuaddr = entry->memdesc.useraddr;
ret = memdesc_sg_virt(&entry->memdesc, useraddr, size);
if (ret)
@@ -1861,6 +1920,8 @@
entry->priv_data = handle;
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = 0;
+ /* USE_CPU_MAP is not impemented for ION. */
+ entry->memdesc.flags &= ~KGSL_MEMFLAGS_USE_CPU_MAP;
sg_table = ion_sg_table(kgsl_ion_client, handle);
@@ -1884,6 +1945,13 @@
return -ENOMEM;
}
+static inline int
+can_use_cpu_map(void)
+{
+ return (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_IOMMU
+ && kgsl_mmu_is_perprocess());
+}
+
static long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv,
unsigned int cmd, void *data)
{
@@ -1911,9 +1979,12 @@
*/
param->flags &= KGSL_MEMFLAGS_GPUREADONLY
| KGSL_MEMTYPE_MASK
- | KGSL_MEMALIGN_MASK;
+ | KGSL_MEMALIGN_MASK
+ | KGSL_MEMFLAGS_USE_CPU_MAP;
entry->memdesc.flags = param->flags;
+ if (!can_use_cpu_map())
+ entry->memdesc.flags &= ~KGSL_MEMFLAGS_USE_CPU_MAP;
switch (memtype) {
case KGSL_USER_MEM_TYPE_PMEM:
@@ -2091,7 +2162,7 @@
return _kgsl_gpumem_sync_cache(entry, param->op);
}
-/* Legacy cache function, does a flush (clean + inv) */
+/* Legacy cache function, does a flush (clean + invalidate) */
static long
kgsl_ioctl_sharedmem_flush_cache(struct kgsl_device_private *dev_priv,
@@ -2133,7 +2204,8 @@
flags &= KGSL_MEMFLAGS_GPUREADONLY
| KGSL_CACHEMODE_MASK
| KGSL_MEMTYPE_MASK
- | KGSL_MEMALIGN_MASK;
+ | KGSL_MEMALIGN_MASK
+ | KGSL_MEMFLAGS_USE_CPU_MAP;
entry = kgsl_mem_entry_create();
if (entry == NULL)
@@ -2164,6 +2236,7 @@
struct kgsl_mem_entry *entry = NULL;
int result;
+ param->flags &= ~KGSL_MEMFLAGS_USE_CPU_MAP;
result = _gpumem_alloc(dev_priv, &entry, param->size, param->flags);
if (result)
return result;
@@ -2199,14 +2272,19 @@
struct kgsl_mem_entry *entry = NULL;
int result;
+ if (!can_use_cpu_map())
+ param->flags &= ~KGSL_MEMFLAGS_USE_CPU_MAP;
+
result = _gpumem_alloc(dev_priv, &entry, param->size, param->flags);
if (result != 0)
goto err;
- result = kgsl_mmu_map(private->pagetable, &entry->memdesc,
- kgsl_memdesc_protflags(&entry->memdesc));
- if (result)
- goto err;
+ if (!kgsl_memdesc_use_cpu_map(&entry->memdesc)) {
+ result = kgsl_mmu_map(private->pagetable, &entry->memdesc,
+ kgsl_memdesc_protflags(&entry->memdesc));
+ if (result)
+ goto err;
+ }
result = kgsl_mem_entry_attach_process(entry, private);
if (result != 0)
@@ -2218,7 +2296,7 @@
param->id = entry->id;
param->flags = entry->memdesc.flags;
param->size = entry->memdesc.size;
- param->mmapsize = entry->memdesc.size;
+ param->mmapsize = kgsl_memdesc_mmapsize(&entry->memdesc);
param->gpuaddr = entry->memdesc.gpuaddr;
return result;
err:
@@ -2261,7 +2339,7 @@
param->id = entry->id;
param->flags = entry->memdesc.flags;
param->size = entry->memdesc.size;
- param->mmapsize = entry->memdesc.size;
+ param->mmapsize = kgsl_memdesc_mmapsize(&entry->memdesc);
param->useraddr = entry->memdesc.useraddr;
return result;
}
@@ -2640,6 +2718,142 @@
.close = kgsl_gpumem_vm_close,
};
+static int
+get_mmap_entry(struct kgsl_process_private *private,
+ struct kgsl_mem_entry **out_entry, unsigned long pgoff,
+ unsigned long len)
+{
+ int ret = -EINVAL;
+ struct kgsl_mem_entry *entry;
+
+ entry = kgsl_sharedmem_find_id(private, pgoff);
+ if (entry == NULL) {
+ spin_lock(&private->mem_lock);
+ entry = kgsl_sharedmem_find(private, pgoff << PAGE_SHIFT);
+ spin_unlock(&private->mem_lock);
+ }
+
+ if (!entry)
+ return -EINVAL;
+
+ kgsl_mem_entry_get(entry);
+
+ if (!entry->memdesc.ops ||
+ !entry->memdesc.ops->vmflags ||
+ !entry->memdesc.ops->vmfault) {
+ ret = -EINVAL;
+ goto err_put;
+ }
+
+ if (entry->memdesc.useraddr != 0) {
+ ret = -EBUSY;
+ goto err_put;
+ }
+
+ if (len != kgsl_memdesc_mmapsize(&entry->memdesc)) {
+ ret = -ERANGE;
+ goto err_put;
+ }
+
+ *out_entry = entry;
+ return 0;
+err_put:
+ kgsl_mem_entry_put(entry);
+ return ret;
+}
+
+static unsigned long
+kgsl_get_unmapped_area(struct file *file, unsigned long addr,
+ unsigned long len, unsigned long pgoff,
+ unsigned long flags)
+{
+ unsigned long ret = 0;
+ unsigned long vma_offset = pgoff << PAGE_SHIFT;
+ struct kgsl_device_private *dev_priv = file->private_data;
+ struct kgsl_process_private *private = dev_priv->process_priv;
+ struct kgsl_device *device = dev_priv->device;
+ struct kgsl_mem_entry *entry = NULL;
+ unsigned int align;
+ unsigned int retry = 0;
+
+ if (vma_offset == device->memstore.gpuaddr)
+ return get_unmapped_area(NULL, addr, len, pgoff, flags);
+
+ ret = get_mmap_entry(private, &entry, pgoff, len);
+ if (ret)
+ return ret;
+
+ if (!kgsl_memdesc_use_cpu_map(&entry->memdesc) || (flags & MAP_FIXED)) {
+ /*
+ * If we're not going to use the same mapping on the gpu,
+ * any address is fine.
+ * For MAP_FIXED, hopefully the caller knows what they're doing,
+ * but we may fail in mmap() if there is already something
+ * at the virtual address chosen.
+ */
+ ret = get_unmapped_area(NULL, addr, len, pgoff, flags);
+ goto put;
+ }
+ if (entry->memdesc.gpuaddr != 0) {
+ KGSL_MEM_INFO(device,
+ "pgoff %lx already mapped to gpuaddr %x\n",
+ pgoff, entry->memdesc.gpuaddr);
+ ret = -EBUSY;
+ goto put;
+ }
+
+ align = kgsl_memdesc_get_align(&entry->memdesc);
+ if (align >= ilog2(SZ_1M))
+ align = ilog2(SZ_1M);
+ else if (align >= ilog2(SZ_64K))
+ align = ilog2(SZ_64K);
+ else if (align <= PAGE_SHIFT)
+ align = 0;
+
+ if (align)
+ len += 1 << align;
+ do {
+ ret = get_unmapped_area(NULL, addr, len, pgoff, flags);
+ if (IS_ERR_VALUE(ret))
+ break;
+ if (align)
+ ret = ALIGN(ret, (1 << align));
+
+ /*make sure there isn't a GPU only mapping at this address */
+ if (kgsl_sharedmem_region_empty(private, ret, len))
+ break;
+
+ trace_kgsl_mem_unmapped_area_collision(entry, addr, len, ret);
+
+ /*
+ * If we collided, bump the hint address so that
+ * get_umapped_area knows to look somewhere else.
+ */
+ addr = (addr == 0) ? ret + len : addr + len;
+
+ /*
+ * The addr hint can be set by userspace to be near
+ * the end of the address space. Make sure we search
+ * the whole address space at least once by wrapping
+ * back around once.
+ */
+ if (!retry && (addr + len >= TASK_SIZE)) {
+ addr = 0;
+ retry = 1;
+ } else {
+ ret = -EBUSY;
+ }
+ } while (addr + len < TASK_SIZE);
+
+ if (IS_ERR_VALUE(ret))
+ KGSL_MEM_INFO(device,
+ "pid %d pgoff %lx len %ld failed error %ld\n",
+ private->pid, pgoff, len, ret);
+put:
+ kgsl_mem_entry_put(entry);
+ return ret;
+}
+
static int kgsl_mmap(struct file *file, struct vm_area_struct *vma)
{
unsigned int ret, cache;
@@ -2654,35 +2868,21 @@
if (vma_offset == device->memstore.gpuaddr)
return kgsl_mmap_memstore(device, vma);
- /* Find a chunk of GPU memory */
- entry = kgsl_sharedmem_find_id(private, vma->vm_pgoff);
+ ret = get_mmap_entry(private, &entry, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start);
+ if (ret)
+ return ret;
- if (entry == NULL) {
- spin_lock(&private->mem_lock);
- entry = kgsl_sharedmem_find(private, vma_offset);
- spin_unlock(&private->mem_lock);
- }
+ if (kgsl_memdesc_use_cpu_map(&entry->memdesc)) {
+ entry->memdesc.gpuaddr = vma->vm_start;
- if (entry)
- kgsl_mem_entry_get(entry);
- else
- return -EINVAL;
-
- if (!entry->memdesc.ops ||
- !entry->memdesc.ops->vmflags ||
- !entry->memdesc.ops->vmfault) {
- ret = -EINVAL;
- goto err_put;
- }
-
- if (entry->memdesc.useraddr != 0) {
- ret = -EBUSY;
- goto err_put;
- }
-
- if (entry->memdesc.size != (vma->vm_end - vma->vm_start)) {
- ret = -ERANGE;
- goto err_put;
+ ret = kgsl_mmu_map(private->pagetable, &entry->memdesc,
+ kgsl_memdesc_protflags(&entry->memdesc));
+ if (ret) {
+ kgsl_mem_entry_put(entry);
+ return ret;
+ }
+ kgsl_mem_entry_track_gpuaddr(private, entry);
}
vma->vm_flags |= entry->memdesc.ops->vmflags(&entry->memdesc);
@@ -2714,10 +2914,9 @@
entry->memdesc.useraddr = vma->vm_start;
+ trace_kgsl_mem_mmap(entry);
+
return 0;
-err_put:
- kgsl_mem_entry_put(entry);
- return ret;
}
static irqreturn_t kgsl_irq_handler(int irq, void *data)
@@ -2733,6 +2932,7 @@
.release = kgsl_release,
.open = kgsl_open,
.mmap = kgsl_mmap,
+ .get_unmapped_area = kgsl_get_unmapped_area,
.unlocked_ioctl = kgsl_ioctl,
};
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index cd1f763..72e7776 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -242,6 +242,10 @@
static inline int kgsl_gpuaddr_in_memdesc(const struct kgsl_memdesc *memdesc,
unsigned int gpuaddr, unsigned int size)
{
+ /* don't overflow */
+ if ((gpuaddr + size) < gpuaddr)
+ return 0;
+
if (gpuaddr >= memdesc->gpuaddr &&
((gpuaddr + size) <= (memdesc->gpuaddr + memdesc->size))) {
return 1;
diff --git a/drivers/gpu/msm/kgsl_debugfs.c b/drivers/gpu/msm/kgsl_debugfs.c
index d4834e5..3bc107f 100644
--- a/drivers/gpu/msm/kgsl_debugfs.c
+++ b/drivers/gpu/msm/kgsl_debugfs.c
@@ -232,36 +232,59 @@
return table[kgsl_memdesc_get_cachemode(m)];
}
+static void print_mem_entry(struct seq_file *s, struct kgsl_mem_entry *entry)
+{
+ char flags[6];
+ char usage[16];
+ struct kgsl_memdesc *m = &entry->memdesc;
+
+ flags[0] = kgsl_memdesc_is_global(m) ? 'g' : '-';
+ flags[1] = m->flags & KGSL_MEMFLAGS_GPUREADONLY ? 'r' : '-';
+ flags[2] = get_alignflag(m);
+ flags[3] = get_cacheflag(m);
+ flags[4] = kgsl_memdesc_use_cpu_map(m) ? 'p' : '-';
+ flags[5] = '\0';
+
+ kgsl_get_memory_usage(usage, sizeof(usage), m->flags);
+
+ seq_printf(s, "%08x %8d %5d %5s %10s %16s %5d\n",
+ m->gpuaddr, m->size, entry->id, flags,
+ memtype_str(entry->memtype), usage, m->sglen);
+}
+
static int process_mem_print(struct seq_file *s, void *unused)
{
struct kgsl_mem_entry *entry;
struct rb_node *node;
struct kgsl_process_private *private = s->private;
- char flags[5];
- char usage[16];
+ int next = 0;
- spin_lock(&private->mem_lock);
seq_printf(s, "%8s %8s %5s %5s %10s %16s %5s\n",
"gpuaddr", "size", "id", "flags", "type", "usage", "sglen");
+
+ /* print all entries with a GPU address */
+ spin_lock(&private->mem_lock);
+
for (node = rb_first(&private->mem_rb); node; node = rb_next(node)) {
- struct kgsl_memdesc *m;
-
entry = rb_entry(node, struct kgsl_mem_entry, node);
- m = &entry->memdesc;
-
- flags[0] = kgsl_memdesc_is_global(m) ? 'g' : '-';
- flags[1] = m->flags & KGSL_MEMFLAGS_GPUREADONLY ? 'r' : '-';
- flags[2] = get_alignflag(m);
- flags[3] = get_cacheflag(m);
- flags[4] = '\0';
-
- kgsl_get_memory_usage(usage, sizeof(usage), m->flags);
-
- seq_printf(s, "%08x %8d %5d %5s %10s %16s %5d\n",
- m->gpuaddr, m->size, entry->id, flags,
- memtype_str(entry->memtype), usage, m->sglen);
+ print_mem_entry(s, entry);
}
+
spin_unlock(&private->mem_lock);
+
+ /* now print all the unbound entries */
+ while (1) {
+ rcu_read_lock();
+ entry = idr_get_next(&private->mem_idr, &next);
+ rcu_read_unlock();
+
+ if (entry == NULL)
+ break;
+ if (entry->memdesc.gpuaddr == 0)
+ print_mem_entry(s, entry);
+ next++;
+ }
+
return 0;
}
diff --git a/drivers/gpu/msm/kgsl_mmu.c b/drivers/gpu/msm/kgsl_mmu.c
index bf39587..533f02f 100644
--- a/drivers/gpu/msm/kgsl_mmu.c
+++ b/drivers/gpu/msm/kgsl_mmu.c
@@ -27,9 +27,6 @@
#include "kgsl_sharedmem.h"
#include "adreno.h"
-#define KGSL_MMU_ALIGN_SHIFT 13
-#define KGSL_MMU_ALIGN_MASK (~((1 << KGSL_MMU_ALIGN_SHIFT) - 1))
-
static enum kgsl_mmutype kgsl_mmu_type;
static void pagetable_remove_sysfs_objects(struct kgsl_pagetable *pagetable);
@@ -447,10 +444,10 @@
if ((KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype()) &&
((KGSL_MMU_GLOBAL_PT == name) ||
(KGSL_MMU_PRIV_BANK_TABLE_NAME == name))) {
- pagetable->kgsl_pool = gen_pool_create(PAGE_SHIFT, -1);
+ pagetable->kgsl_pool = gen_pool_create(ilog2(SZ_8K), -1);
if (pagetable->kgsl_pool == NULL) {
KGSL_CORE_ERR("gen_pool_create(%d) failed\n",
- KGSL_MMU_ALIGN_SHIFT);
+ ilog2(SZ_8K));
goto err_alloc;
}
if (gen_pool_add(pagetable->kgsl_pool,
@@ -461,10 +458,10 @@
}
}
- pagetable->pool = gen_pool_create(KGSL_MMU_ALIGN_SHIFT, -1);
+ pagetable->pool = gen_pool_create(PAGE_SHIFT, -1);
if (pagetable->pool == NULL) {
KGSL_CORE_ERR("gen_pool_create(%d) failed\n",
- KGSL_MMU_ALIGN_SHIFT);
+ PAGE_SHIFT);
goto err_kgsl_pool;
}
@@ -585,7 +582,7 @@
unsigned int protflags)
{
int ret;
- struct gen_pool *pool;
+ struct gen_pool *pool = NULL;
int size;
int page_align = ilog2(PAGE_SIZE);
@@ -635,6 +632,10 @@
pagetable->name);
return -EINVAL;
}
+ } else if (kgsl_memdesc_use_cpu_map(memdesc)) {
+ if (memdesc->gpuaddr == 0)
+ return -EINVAL;
+ pool = NULL;
}
}
if (pool) {
@@ -715,9 +716,11 @@
pool = pagetable->pool;
- if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype()
- && kgsl_memdesc_is_global(memdesc)) {
- pool = pagetable->kgsl_pool;
+ if (KGSL_MMU_TYPE_IOMMU == kgsl_mmu_get_mmutype()) {
+ if (kgsl_memdesc_is_global(memdesc))
+ pool = pagetable->kgsl_pool;
+ else if (kgsl_memdesc_use_cpu_map(memdesc))
+ pool = NULL;
}
if (pool)
gen_pool_free(pool, memdesc->gpuaddr, size);
@@ -854,8 +857,13 @@
{
if (KGSL_MMU_TYPE_NONE == kgsl_mmu_type)
return 1;
- return ((gpuaddr >= KGSL_PAGETABLE_BASE) &&
- (gpuaddr < (KGSL_PAGETABLE_BASE + kgsl_mmu_get_ptsize())));
+ if (gpuaddr >= kgsl_mmu_get_base_addr() &&
+ gpuaddr < kgsl_mmu_get_base_addr() + kgsl_mmu_get_ptsize())
+ return 1;
+ if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_IOMMU
+ && kgsl_mmu_is_perprocess())
+ return (gpuaddr > 0 && gpuaddr < TASK_SIZE);
+ return 0;
}
EXPORT_SYMBOL(kgsl_mmu_gpuaddr_in_range);
diff --git a/drivers/gpu/msm/kgsl_mmu.h b/drivers/gpu/msm/kgsl_mmu.h
index b8eff60..c8d637e 100644
--- a/drivers/gpu/msm/kgsl_mmu.h
+++ b/drivers/gpu/msm/kgsl_mmu.h
@@ -19,11 +19,10 @@
* These defines control the address range for allocations that
* are mapped into all pagetables.
*/
-#define KGSL_IOMMU_GLOBAL_MEM_BASE 0xC0000000
+#define KGSL_IOMMU_GLOBAL_MEM_BASE 0xf8000000
#define KGSL_IOMMU_GLOBAL_MEM_SIZE SZ_4M
-#define KGSL_MMU_ALIGN_SHIFT 13
-#define KGSL_MMU_ALIGN_MASK (~((1 << KGSL_MMU_ALIGN_SHIFT) - 1))
+#define KGSL_MMU_ALIGN_MASK (~((1 << PAGE_SHIFT) - 1))
/* Identifier for the global page table */
/* Per process page tables will probably pass in the thread group
@@ -350,32 +349,52 @@
/*
* kgsl_mmu_base_addr() - Get gpu virtual address base.
*
- * Returns the start address of the gpu
- * virtual address space.
+ * Returns the start address of the allocatable gpu
+ * virtual address space. Other mappings that mirror
+ * the CPU address space are possible outside this range.
*/
static inline unsigned int kgsl_mmu_get_base_addr(void)
{
- return KGSL_PAGETABLE_BASE;
+ if (KGSL_MMU_TYPE_GPU == kgsl_mmu_get_mmutype()
+ || !kgsl_mmu_is_perprocess())
+ return KGSL_PAGETABLE_BASE;
+ /*
+ * This is the start of the kernel address
+ * space, so allocations from this range will
+ * never conflict with userpace addresses
+ */
+ return PAGE_OFFSET;
}
/*
* kgsl_mmu_get_ptsize() - Get gpu pagetable size
*
- * Returns the usable size of the gpu address space.
+ * Returns the usable size of the gpu allocatable
+ * address space.
*/
static inline unsigned int kgsl_mmu_get_ptsize(void)
{
/*
- * For IOMMU, we could do up to 4G virtual range if we wanted to, but
- * it makes more sense to return a smaller range and leave the rest of
- * the virtual range for future improvements
+ * For IOMMU per-process pagetables, the allocatable range
+ * and the kernel global range must both be outside
+ * the userspace address range. There is a 1Mb gap
+ * between these address ranges to make overrun
+ * detection easier.
+ * For the shared pagetable case use 2GB and because
+ * mirroring the CPU address space is not possible and
+ * we're better off with extra room.
*/
enum kgsl_mmutype mmu_type = kgsl_mmu_get_mmutype();
if (KGSL_MMU_TYPE_GPU == mmu_type)
return CONFIG_MSM_KGSL_PAGE_TABLE_SIZE;
- else if (KGSL_MMU_TYPE_IOMMU == mmu_type)
- return SZ_2G;
+ else if (KGSL_MMU_TYPE_IOMMU == mmu_type) {
+ if (kgsl_mmu_is_perprocess())
+ return KGSL_IOMMU_GLOBAL_MEM_BASE
+ - kgsl_mmu_get_base_addr() - SZ_1M;
+ else
+ return SZ_2G;
+ }
return 0;
}
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index df44166..f04fae1 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -113,6 +113,7 @@
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
struct kgsl_pwrlevel *pwrlevel;
int delta;
+ int level;
/* Adjust the power level to the current constraints */
new_level = _adjust_pwrlevel(pwr, new_level);
@@ -124,6 +125,16 @@
update_clk_statistics(device, true);
+ level = pwr->active_pwrlevel;
+
+ /*
+ * Set the active powerlevel first in case the clocks are off - if we
+ * don't do this then the pwrlevel change won't take effect when the
+ * clocks come back
+ */
+
+ pwr->active_pwrlevel = new_level;
+
if (test_bit(KGSL_PWRFLAGS_CLK_ON, &pwr->power_flags) ||
(device->state == KGSL_STATE_NAP)) {
@@ -141,11 +152,11 @@
* avoid glitches.
*/
- while (pwr->active_pwrlevel != new_level) {
- pwr->active_pwrlevel += delta;
+ while (level != new_level) {
+ level += delta;
clk_set_rate(pwr->grp_clks[0],
- pwr->pwrlevels[pwr->active_pwrlevel].gpu_freq);
+ pwr->pwrlevels[level].gpu_freq);
}
}
diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c
index 11ca0b0..08353ee 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.c
+++ b/drivers/gpu/msm/kgsl_sharedmem.c
@@ -555,7 +555,8 @@
page_size = (align >= ilog2(SZ_64K) && size >= SZ_64K)
? SZ_64K : PAGE_SIZE;
/* update align flags for what we actually use */
- kgsl_memdesc_set_align(memdesc, ilog2(page_size));
+ if (page_size != PAGE_SIZE)
+ kgsl_memdesc_set_align(memdesc, ilog2(page_size));
/*
* There needs to be enough room in the sg structure to be able to
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index f07f049..d937699 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -181,6 +181,18 @@
}
/*
+ * kgsl_memdesc_has_guard_page - is the last page a guard page?
+ * @memdesc - the memdesc
+ *
+ * Returns nonzero if there is a guard page, 0 otherwise
+ */
+static inline int
+kgsl_memdesc_has_guard_page(const struct kgsl_memdesc *memdesc)
+{
+ return (memdesc->priv & KGSL_MEMDESC_GUARD_PAGE) != 0;
+}
+
+/*
* kgsl_memdesc_protflags - get mmu protection flags
* @memdesc - the memdesc
* Returns a mask of GSL_PT_PAGE* values based on the
@@ -195,6 +207,35 @@
return protflags;
}
+/*
+ * kgsl_memdesc_use_cpu_map - use the same virtual mapping on CPU and GPU?
+ * @memdesc - the memdesc
+ */
+static inline int
+kgsl_memdesc_use_cpu_map(const struct kgsl_memdesc *memdesc)
+{
+ return (memdesc->flags & KGSL_MEMFLAGS_USE_CPU_MAP) != 0;
+}
+
+/*
+ * kgsl_memdesc_mmapsize - get the size of the mmap region
+ * @memdesc - the memdesc
+ *
+ * The entire memdesc must be mapped. Additionally if the
+ * CPU mapping is going to be mirrored, there must be room
+ * for the guard page to be mapped so that the address spaces
+ * match up.
+ */
+static inline unsigned int
+kgsl_memdesc_mmapsize(const struct kgsl_memdesc *memdesc)
+{
+ unsigned int size = memdesc->size;
+ if (kgsl_memdesc_use_cpu_map(memdesc) &&
+ kgsl_memdesc_has_guard_page(memdesc))
+ size += SZ_4K;
+ return size;
+}
+
static inline int
kgsl_allocate(struct kgsl_memdesc *memdesc,
struct kgsl_pagetable *pagetable, size_t size)
diff --git a/drivers/gpu/msm/kgsl_trace.h b/drivers/gpu/msm/kgsl_trace.h
index 7cc55f6..9662fce 100644
--- a/drivers/gpu/msm/kgsl_trace.h
+++ b/drivers/gpu/msm/kgsl_trace.h
@@ -338,6 +338,68 @@
)
);
+TRACE_EVENT(kgsl_mem_mmap,
+
+ TP_PROTO(struct kgsl_mem_entry *mem_entry),
+
+ TP_ARGS(mem_entry),
+
+ TP_STRUCT__entry(
+ __field(unsigned long, useraddr)
+ __field(unsigned int, gpuaddr)
+ __field(unsigned int, size)
+ __array(char, usage, 16)
+ __field(unsigned int, id)
+ __field(unsigned int, flags)
+ ),
+
+ TP_fast_assign(
+ __entry->useraddr = mem_entry->memdesc.useraddr;
+ __entry->gpuaddr = mem_entry->memdesc.gpuaddr;
+ __entry->size = mem_entry->memdesc.size;
+ kgsl_get_memory_usage(__entry->usage, sizeof(__entry->usage),
+ mem_entry->memdesc.flags);
+ __entry->id = mem_entry->id;
+ __entry->flags = mem_entry->memdesc.flags;
+ ),
+
+ TP_printk(
+ "useraddr=%lx gpuaddr=0x%08x size=%d usage=%s id=%d"
+ " flags=0x%08x",
+ __entry->useraddr, __entry->gpuaddr, __entry->size,
+ __entry->usage, __entry->id, __entry->flags
+ )
+);
+
+TRACE_EVENT(kgsl_mem_unmapped_area_collision,
+
+ TP_PROTO(struct kgsl_mem_entry *mem_entry,
+ unsigned long hint,
+ unsigned long len,
+ unsigned long addr),
+
+ TP_ARGS(mem_entry, hint, len, addr),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, id)
+ __field(unsigned long, hint)
+ __field(unsigned long, len)
+ __field(unsigned long, addr)
+ ),
+
+ TP_fast_assign(
+ __entry->id = mem_entry->id;
+ __entry->hint = hint;
+ __entry->len = len;
+ __entry->addr = addr;
+ ),
+
+ TP_printk(
+ "id=%d hint=0x%lx len=%ld addr=0x%lx",
+ __entry->id, __entry->hint, __entry->len, __entry->addr
+ )
+);
+
TRACE_EVENT(kgsl_mem_map,
TP_PROTO(struct kgsl_mem_entry *mem_entry, int fd),
diff --git a/drivers/leds/leds-qpnp.c b/drivers/leds/leds-qpnp.c
index d658217..e7d514e 100644
--- a/drivers/leds/leds-qpnp.c
+++ b/drivers/leds/leds-qpnp.c
@@ -1260,10 +1260,10 @@
static int __devinit qpnp_leds_probe(struct spmi_device *spmi)
{
- struct qpnp_led_data *led;
+ struct qpnp_led_data *led, *led_array;
struct resource *led_resource;
struct device_node *node, *temp;
- int rc, i, num_leds = 0;
+ int rc, i, num_leds = 0, parsed_leds = 0;
const char *led_label;
node = spmi->dev.of_node;
@@ -1274,34 +1274,34 @@
while ((temp = of_get_next_child(node, temp)))
num_leds++;
- led = devm_kzalloc(&spmi->dev,
+ if (!num_leds)
+ return -ECHILD;
+
+ led_array = devm_kzalloc(&spmi->dev,
(sizeof(struct qpnp_led_data) * num_leds), GFP_KERNEL);
- if (!led) {
+ if (!led_array) {
dev_err(&spmi->dev, "Unable to allocate memory\n");
return -ENOMEM;
}
- led->num_leds = num_leds;
- num_leds = 0;
-
for_each_child_of_node(node, temp) {
+ led = &led_array[parsed_leds];
+ led->num_leds = num_leds;
led->spmi_dev = spmi;
led_resource = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
if (!led_resource) {
dev_err(&spmi->dev, "Unable to get LED base address\n");
- return -ENXIO;
+ rc = -ENXIO;
+ goto fail_id_check;
}
led->base = led_resource->start;
- dev_set_drvdata(&spmi->dev, led);
-
-
rc = of_property_read_string(temp, "label", &led_label);
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Failure reading label, rc = %d\n", rc);
- return rc;
+ goto fail_id_check;
}
rc = of_property_read_string(temp, "linux,name",
@@ -1309,7 +1309,7 @@
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Failure reading led name, rc = %d\n", rc);
- return rc;
+ goto fail_id_check;
}
rc = of_property_read_u32(temp, "qcom,max-current",
@@ -1317,14 +1317,14 @@
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Failure reading max_current, rc = %d\n", rc);
- return rc;
+ goto fail_id_check;
}
rc = of_property_read_u32(temp, "qcom,id", &led->id);
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Failure reading led id, rc = %d\n", rc);
- return rc;
+ goto fail_id_check;
}
rc = qpnp_get_common_configs(led, temp);
@@ -1332,7 +1332,7 @@
dev_err(&led->spmi_dev->dev,
"Failure reading common led configuration," \
" rc = %d\n", rc);
- return rc;
+ goto fail_id_check;
}
led->cdev.brightness_set = qpnp_led_set;
@@ -1343,7 +1343,7 @@
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Unable to read wled config data\n");
- return rc;
+ goto fail_id_check;
}
} else if (strncmp(led_label, "flash", sizeof("flash"))
== 0) {
@@ -1351,18 +1351,19 @@
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Unable to read flash config data\n");
- return rc;
+ goto fail_id_check;
}
} else if (strncmp(led_label, "rgb", sizeof("rgb")) == 0) {
rc = qpnp_get_config_rgb(led, temp);
if (rc < 0) {
dev_err(&led->spmi_dev->dev,
"Unable to read rgb config data\n");
- return rc;
+ goto fail_id_check;
}
} else {
dev_err(&led->spmi_dev->dev, "No LED matching label\n");
- return -EINVAL;
+ rc = -EINVAL;
+ goto fail_id_check;
}
spin_lock_init(&led->lock);
@@ -1388,24 +1389,25 @@
led->cdev.brightness = LED_OFF;
qpnp_led_set(&led->cdev, led->cdev.brightness);
- led++;
- num_leds++;
+
+ parsed_leds++;
}
+ dev_set_drvdata(&spmi->dev, led_array);
return 0;
fail_id_check:
- for (i = 0; i < num_leds; i++)
- led_classdev_unregister(&led[i].cdev);
+ for (i = 0; i < parsed_leds; i++)
+ led_classdev_unregister(&led_array[i].cdev);
return rc;
}
static int __devexit qpnp_leds_remove(struct spmi_device *spmi)
{
- struct qpnp_led_data *led = dev_get_drvdata(&spmi->dev);
- int i;
+ struct qpnp_led_data *led_array = dev_get_drvdata(&spmi->dev);
+ int i, parsed_leds = led_array->num_leds;
- for (i = 0; i < led->num_leds; i++)
- led_classdev_unregister(&led[i].cdev);
+ for (i = 0; i < parsed_leds; i++)
+ led_classdev_unregister(&led_array[i].cdev);
return 0;
}
diff --git a/drivers/media/video/msm_wfd/enc-venus-subdev.c b/drivers/media/video/msm_wfd/enc-venus-subdev.c
index 150c667..64c18da 100644
--- a/drivers/media/video/msm_wfd/enc-venus-subdev.c
+++ b/drivers/media/video/msm_wfd/enc-venus-subdev.c
@@ -1141,6 +1141,15 @@
return 0;
}
+static long venc_set_framerate_mode(struct v4l2_subdev *sd,
+ void *arg)
+{
+ /* TODO: Unsupported for now, but return false success
+ * to preserve binary compatibility for userspace apps
+ * across targets */
+ return 0;
+}
+
long venc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
long rc = 0;
@@ -1210,6 +1219,9 @@
case ENC_MUNMAP:
rc = venc_munmap(sd, arg);
break;
+ case SET_FRAMERATE_MODE:
+ rc = venc_set_framerate_mode(sd, arg);
+ break;
default:
WFD_MSG_ERR("Unknown ioctl %d to enc-subdev\n", cmd);
rc = -ENOTSUPP;
diff --git a/drivers/media/video/msm_wfd/wfd-ioctl.c b/drivers/media/video/msm_wfd/wfd-ioctl.c
index 99dc0d0..bb2e606 100644
--- a/drivers/media/video/msm_wfd/wfd-ioctl.c
+++ b/drivers/media/video/msm_wfd/wfd-ioctl.c
@@ -1098,7 +1098,6 @@
rc = -EINVAL;
goto set_parm_fail;
}
- venc_mode = VENC_MODE_CFR;
frame_interval =
a->parm.capture.timeperframe.numerator * NSEC_PER_SEC /
a->parm.capture.timeperframe.denominator;
@@ -1128,6 +1127,7 @@
max_frame_interval = (int64_t)frameskip.maxframeinterval;
vsg_mode = VSG_MODE_VFR;
+ venc_mode = VENC_MODE_VFR;
rc = v4l2_subdev_call(&wfd_dev->vsg_sdev, core,
ioctl, VSG_SET_MAX_FRAME_INTERVAL,
@@ -1135,24 +1135,25 @@
if (rc)
goto set_parm_fail;
-
- rc = v4l2_subdev_call(&wfd_dev->vsg_sdev, core,
- ioctl, VSG_SET_MODE, &vsg_mode);
-
- if (rc)
- goto set_parm_fail;
} else {
vsg_mode = VSG_MODE_CFR;
- rc = v4l2_subdev_call(&wfd_dev->vsg_sdev, core,
- ioctl, VSG_SET_MODE, &vsg_mode);
+ venc_mode = VENC_MODE_CFR;
+ }
- if (rc)
- goto set_parm_fail;
+ rc = v4l2_subdev_call(&wfd_dev->vsg_sdev, core,
+ ioctl, VSG_SET_MODE, &vsg_mode);
+ if (rc) {
+ WFD_MSG_ERR("Setting FR mode for VSG failed\n");
+ goto set_parm_fail;
}
rc = v4l2_subdev_call(&wfd_dev->enc_sdev, core,
ioctl, SET_FRAMERATE_MODE,
&venc_mode);
+ if (rc) {
+ WFD_MSG_ERR("Setting FR mode for VENC failed\n");
+ goto set_parm_fail;
+ }
set_parm_fail:
return rc;
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index ae68060..d2a5836 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -1022,9 +1022,6 @@
goto out;
}
- if (mmc_can_sanitize(card))
- err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_SANITIZE_START, 1, 0);
out_retry:
if (err && !mmc_blk_reset(md, card->host, type))
goto retry;
diff --git a/drivers/net/ethernet/msm/msm_rmnet.c b/drivers/net/ethernet/msm/msm_rmnet.c
index 4af2d8c..cc9ed74 100644
--- a/drivers/net/ethernet/msm/msm_rmnet.c
+++ b/drivers/net/ethernet/msm/msm_rmnet.c
@@ -94,6 +94,7 @@
struct sk_buff *skb;
spinlock_t lock;
struct tasklet_struct tsklt;
+ struct tasklet_struct rx_tasklet;
u32 operation_mode; /* IOCTL specified mode (protocol, QoS header) */
struct platform_driver pdrv;
struct completion complete;
@@ -257,7 +258,6 @@
}
static void smd_net_data_handler(unsigned long arg);
-static DECLARE_TASKLET(smd_net_data_tasklet, smd_net_data_handler, 0);
/* Called in soft-irq context */
static void smd_net_data_handler(unsigned long arg)
@@ -280,8 +280,8 @@
pr_err("[%s] rmnet_recv() cannot allocate skb\n",
dev->name);
/* out of memory, reschedule a later attempt */
- smd_net_data_tasklet.data = (unsigned long)dev;
- tasklet_schedule(&smd_net_data_tasklet);
+ p->rx_tasklet.data = (unsigned long)dev;
+ tasklet_schedule(&p->rx_tasklet);
break;
} else {
skb->dev = dev;
@@ -449,8 +449,8 @@
if (smd_read_avail(p->ch) &&
(smd_read_avail(p->ch) >= smd_cur_packet_size(p->ch))) {
- smd_net_data_tasklet.data = (unsigned long) _dev;
- tasklet_schedule(&smd_net_data_tasklet);
+ p->rx_tasklet.data = (unsigned long) _dev;
+ tasklet_schedule(&p->rx_tasklet);
}
break;
@@ -788,6 +788,8 @@
spin_lock_init(&p->lock);
tasklet_init(&p->tsklt, _rmnet_resume_flow,
(unsigned long)dev);
+ tasklet_init(&p->rx_tasklet, smd_net_data_handler,
+ (unsigned long)dev);
wake_lock_init(&p->wake_lock, WAKE_LOCK_SUSPEND, ch_name[n]);
#ifdef CONFIG_MSM_RMNET_DEBUG
p->timeout_us = timeout_us;
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index 2eddb9d..05b47cc 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -130,7 +130,7 @@
int default_rbatt_mohm;
int amux_2_trim_delta;
uint16_t prev_last_good_ocv_raw;
- unsigned int rconn_mohm;
+ int rconn_mohm;
struct mutex last_ocv_uv_mutex;
int last_ocv_uv;
int pon_ocv_uv;
@@ -1396,14 +1396,16 @@
int fcc_uah, int cc_uah, int uuc_uah)
{
int chg_soc;
+ int vbat_batt_terminal_uv = vbat_uv
+ + (ibat_ua * chip->rconn_mohm) / 1000;
if (chip->soc_at_cv == -EINVAL) {
/* In constant current charging return the calc soc */
- if (vbat_uv <= chip->max_voltage_uv)
+ if (vbat_batt_terminal_uv <= chip->max_voltage_uv)
pr_debug("CC CHG SOC %d\n", soc);
/* Note the CC to CV point */
- if (vbat_uv >= chip->max_voltage_uv) {
+ if (vbat_batt_terminal_uv >= chip->max_voltage_uv) {
chip->soc_at_cv = soc;
chip->prev_chg_soc = soc;
chip->ibat_at_cv_ua = ibat_ua;
@@ -1419,17 +1421,18 @@
*/
/*
- * if voltage lessened (possibly because of a system load)
- * keep reporting the prev chg soc
+ * if voltage lessened by more than 10mV (possibly because of
+ * a sudden increase in system load) keep reporting the prev chg soc
*/
- if (vbat_uv <= chip->max_voltage_uv) {
- pr_debug("vbat %d < max = %d CC CHG SOC %d\n",
- vbat_uv, chip->max_voltage_uv, chip->prev_chg_soc);
+ if (vbat_batt_terminal_uv <= chip->max_voltage_uv - 10000) {
+ pr_debug("vbat_terminals %d < max = %d CC CHG SOC %d\n",
+ vbat_batt_terminal_uv,
+ chip->max_voltage_uv, chip->prev_chg_soc);
return chip->prev_chg_soc;
}
chg_soc = linear_interpolate(chip->soc_at_cv, chip->ibat_at_cv_ua,
- 100, -100000,
+ 100, -1 * chip->chg_term_ua,
ibat_ua);
/* always report a higher soc */
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 705a47c..c6dd57b 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -87,6 +87,7 @@
#define EOC_CHECK_PERIOD_MS 10000
/* check for USB unplug every 200 msecs */
#define UNPLUG_CHECK_WAIT_PERIOD_MS 200
+#define UNPLUG_CHECK_RAMP_MS 25
#define USB_TRIM_ENTRIES 16
enum chg_fsm_state {
@@ -1311,20 +1312,6 @@
return 0;
}
- if (charging_disabled)
- return 0;
-
- /* check external charger first before the dc path */
- if (is_ext_charging(the_chip)) {
- val->intval = 1;
- return 0;
- }
-
- if (pm_is_chg_charge_dis(the_chip)) {
- val->intval = 0;
- return 0;
- }
-
if (the_chip->dc_present) {
val->intval = 1;
return 0;
@@ -1799,6 +1786,12 @@
return;
}
+ if (usb_max_current && mA > usb_max_current) {
+ pr_debug("restricting usb current to %d instead of %d\n",
+ usb_max_current, mA);
+ mA = usb_max_current;
+ }
+
if (mA <= 2) {
usb_chg_current = 0;
rc = pm_chg_iusbmax_set(the_chip, 0);
@@ -2214,8 +2207,7 @@
}
if (usb_present) {
schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ msecs_to_jiffies(UNPLUG_CHECK_RAMP_MS));
pm8921_chg_enable_irq(chip, CHG_GONE_IRQ);
} else {
/* USB unplugged reset target current */
@@ -2294,8 +2286,7 @@
}
schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ msecs_to_jiffies(UNPLUG_CHECK_RAMP_MS));
power_supply_set_online(chip->ext_psy, dc_present);
power_supply_set_charge_type(chip->ext_psy,
@@ -2560,8 +2551,8 @@
USB_WALL_THRESHOLD_MA, usb_target_ma);
if (!delayed_work_pending(&chip->unplug_check_work))
schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ msecs_to_jiffies
+ (UNPLUG_CHECK_WAIT_PERIOD_MS));
} else {
handle_usb_insertion_removal(chip);
}
@@ -2760,6 +2751,7 @@
u8 reg_loop, active_path;
int rc, ibat, active_chg_plugged_in, usb_ma;
int chg_gone = 0;
+ bool ramp = false;
reg_loop = 0;
@@ -2857,15 +2849,20 @@
__pm8921_charger_vbus_draw(usb_ma);
pr_debug("usb_now=%d, usb_target = %d\n",
usb_ma, usb_target_ma);
+ ramp = true;
} else {
usb_target_ma = usb_ma;
}
}
check_again_later:
+ pr_debug("ramp: %d\n", ramp);
/* schedule to check again later */
- schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ if (ramp)
+ schedule_delayed_work(&chip->unplug_check_work,
+ msecs_to_jiffies(UNPLUG_CHECK_RAMP_MS));
+ else
+ schedule_delayed_work(&chip->unplug_check_work,
+ msecs_to_jiffies(UNPLUG_CHECK_WAIT_PERIOD_MS));
}
static irqreturn_t loop_change_irq_handler(int irq, void *data)
@@ -3079,8 +3076,7 @@
} else {
if (dc_present)
schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ msecs_to_jiffies(UNPLUG_CHECK_WAIT_PERIOD_MS));
power_supply_changed(&chip->dc_psy);
}
@@ -3628,8 +3624,7 @@
notify_usb_of_the_plugin_event(chip->usb_present);
if (chip->usb_present || chip->dc_present) {
schedule_delayed_work(&chip->unplug_check_work,
- round_jiffies_relative(msecs_to_jiffies
- (UNPLUG_CHECK_WAIT_PERIOD_MS)));
+ msecs_to_jiffies(UNPLUG_CHECK_WAIT_PERIOD_MS));
pm8921_chg_enable_irq(chip, CHG_GONE_IRQ);
}
@@ -4479,6 +4474,8 @@
chip->temp_check_period = pdata->temp_check_period;
chip->max_bat_chg_current = pdata->max_bat_chg_current;
+ /* Assign to corresponding module parameter */
+ usb_max_current = pdata->usb_max_current;
chip->cool_bat_chg_current = pdata->cool_bat_chg_current;
chip->warm_bat_chg_current = pdata->warm_bat_chg_current;
chip->cool_bat_voltage = pdata->cool_bat_voltage;
@@ -4573,7 +4570,6 @@
enable_irq_wake(chip->pmic_chg_irq[USBIN_VALID_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[DCIN_VALID_IRQ]);
- enable_irq_wake(chip->pmic_chg_irq[BAT_TEMP_OK_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[VBATDET_LOW_IRQ]);
enable_irq_wake(chip->pmic_chg_irq[FASTCHG_IRQ]);
diff --git a/drivers/regulator/onsemi-ncp6335d.c b/drivers/regulator/onsemi-ncp6335d.c
index a0c90f0..4574862 100644
--- a/drivers/regulator/onsemi-ncp6335d.c
+++ b/drivers/regulator/onsemi-ncp6335d.c
@@ -369,8 +369,16 @@
.remove = __devexit_p(ncp6335d_regulator_remove),
.id_table = ncp6335d_id,
};
+static int __init ncp6335d_regulator_init(void)
+{
+ return i2c_add_driver(&ncp6335d_regulator_driver);
+}
+subsys_initcall(ncp6335d_regulator_init);
-module_i2c_driver(ncp6335d_regulator_driver);
-
+static void __exit ncp6335d_regulator_exit(void)
+{
+ i2c_del_driver(&ncp6335d_regulator_driver);
+}
+module_exit(ncp6335d_regulator_exit);
MODULE_DESCRIPTION("OnSemi-NCP6335D regulator driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index cc9ffaa..d56129e 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -18,6 +18,8 @@
* This file is based on msm_serial.c, originally
* Written by Robert Love <rlove@google.com> */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
#if defined(CONFIG_SERIAL_MSM_HSL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
@@ -188,11 +190,12 @@
unsigned long flags;
int ret = 0;
- ret = clk_set_rate(msm_hsl_port->clk, 7372800);
- if (!ret)
+ ret = clk_set_rate(msm_hsl_port->clk, port->uartclk);
+ if (!ret) {
clk_en(port, 1);
- else {
- pr_err("%s(): Error: Setting the clock rate\n", __func__);
+ } else {
+ pr_err("Error: setting uartclk rate as %u\n",
+ port->uartclk);
return -EINVAL;
}
@@ -221,11 +224,12 @@
unsigned long flags;
int ret = 0;
- ret = clk_set_rate(msm_hsl_port->clk, 7372800);
- if (!ret)
+ ret = clk_set_rate(msm_hsl_port->clk, port->uartclk);
+ if (!ret) {
clk_en(port, 1);
- else {
- pr_err("%s(): Error setting clk rate\n", __func__);
+ } else {
+ pr_err("Error setting uartclk rate as %u\n",
+ port->uartclk);
return -EINVAL;
}
@@ -258,8 +262,7 @@
&loopback_enable_fops);
if (IS_ERR_OR_NULL(msm_uport->loopback_dir))
- pr_err("%s(): Cannot create loopback.%d debug entry",
- __func__, id);
+ pr_err("Cannot create loopback.%d debug entry", id);
}
static void msm_hsl_stop_tx(struct uart_port *port)
{
@@ -710,15 +713,15 @@
ret = gpio_request(pdata->uart_tx_gpio,
"UART_TX_GPIO");
if (unlikely(ret)) {
- pr_err("%s: gpio request failed for:%d\n",
- __func__, pdata->uart_tx_gpio);
+ pr_err("gpio request failed for:%d\n",
+ pdata->uart_tx_gpio);
return ret;
}
ret = gpio_request(pdata->uart_rx_gpio, "UART_RX_GPIO");
if (unlikely(ret)) {
- pr_err("%s: gpio request failed for:%d\n",
- __func__, pdata->uart_rx_gpio);
+ pr_err("gpio request failed for:%d\n",
+ pdata->uart_rx_gpio);
gpio_free(pdata->uart_tx_gpio);
return ret;
}
@@ -756,7 +759,7 @@
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
- printk(KERN_ERR "%s: failed to request_irq\n", __func__);
+ pr_err("failed to request_irq\n");
return ret;
}
return 0;
@@ -913,14 +916,14 @@
if (!uart_resource)
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource)) {
- pr_err("%s: can't get uartdm resource\n", __func__);
+ pr_err("can't get uartdm resource\n");
return -ENXIO;
}
size = uart_resource->end - uart_resource->start + 1;
if (unlikely(!request_mem_region(port->mapbase, size,
"msm_serial_hsl"))) {
- pr_err("%s: can't get mem region for uartdm\n", __func__);
+ pr_err("can't get mem region for uartdm\n");
return -EBUSY;
}
@@ -938,7 +941,7 @@
gsbi_resource = platform_get_resource(pdev,
IORESOURCE_MEM, 1);
if (unlikely(!gsbi_resource)) {
- pr_err("%s: can't get gsbi resource\n", __func__);
+ pr_err("can't get gsbi resource\n");
return -ENXIO;
}
@@ -991,22 +994,20 @@
switch (state) {
case 0:
- ret = clk_set_rate(msm_hsl_port->clk, 7372800);
+ ret = clk_set_rate(msm_hsl_port->clk, port->uartclk);
if (ret)
- pr_err("%s(): Error setting UART clock rate\n",
- __func__);
+ pr_err("Error setting UART clock rate to %u\n",
+ port->uartclk);
clk_en(port, 1);
break;
case 3:
clk_en(port, 0);
ret = clk_set_rate(msm_hsl_port->clk, 0);
if (ret)
- pr_err("%s(): Error setting UART clock rate to zero.\n",
- __func__);
+ pr_err("Error setting UART clock rate to zero.\n");
break;
default:
- pr_err("%s(): msm_serial_hsl: Unknown PM state %d\n",
- __func__, state);
+ pr_err("Unknown PM state %d\n", state);
}
}
@@ -1093,15 +1094,15 @@
msm_hsl_console_state[6] = rxfs;
msm_hsl_console_state[7] = con_state;
- pr_info("%s(): Timeout: %d uS\n", __func__, msm_hsl_port->tx_timeout);
- pr_info("%s(): SR: %08x\n", __func__, sr);
- pr_info("%s(): ISR: %08x\n", __func__, isr);
- pr_info("%s(): MR1: %08x\n", __func__, mr1);
- pr_info("%s(): MR2: %08x\n", __func__, mr2);
- pr_info("%s(): NCF: %08x\n", __func__, ncf);
- pr_info("%s(): TXFS: %08x\n", __func__, txfs);
- pr_info("%s(): RXFS: %08x\n", __func__, rxfs);
- pr_info("%s(): Console state: %d\n", __func__, con_state);
+ pr_info("Timeout: %d uS\n", msm_hsl_port->tx_timeout);
+ pr_info("SR: %08x\n", sr);
+ pr_info("ISR: %08x\n", isr);
+ pr_info("MR1: %08x\n", mr1);
+ pr_info("MR2: %08x\n", mr2);
+ pr_info("NCF: %08x\n", ncf);
+ pr_info("TXFS: %08x\n", txfs);
+ pr_info("RXFS: %08x\n", rxfs);
+ pr_info("Console state: %d\n", con_state);
}
/*
@@ -1228,8 +1229,7 @@
msm_hsl_write(port, 1, regmap[vid][UARTDM_NCF_TX]);
msm_hsl_read(port, regmap[vid][UARTDM_NCF_TX]);
- printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
- port->line);
+ pr_info("console setup on port #%d\n", port->line);
return ret;
}
@@ -1302,9 +1302,9 @@
switch (enable) {
case 0:
- pr_debug("%s(): Calling stop_console\n", __func__);
+ pr_debug("Calling stop_console\n");
console_stop(port->cons);
- pr_debug("%s(): Calling unregister_console\n", __func__);
+ pr_debug("Calling unregister_console\n");
unregister_console(port->cons);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
@@ -1316,7 +1316,7 @@
msm_hsl_power(port, 3, 1);
break;
case 1:
- pr_debug("%s(): Calling register_console\n", __func__);
+ pr_debug("Calling register_console\n");
/*
* Disable UART Core clk
* 0 - to enable the UART clock
@@ -1379,11 +1379,11 @@
if (unlikely(line < 0 || line >= UART_NR))
return -ENXIO;
- printk(KERN_INFO "msm_serial_hsl: detected port #%d (ttyHSL%d)\n",
- pdev->id, line);
+ pr_info("detected port #%d (ttyHSL%d)\n", pdev->id, line);
port = get_port_from_line(line);
port->dev = &pdev->dev;
+ port->uartclk = 7372800;
msm_hsl_port = UART_TO_MSM(port);
match = of_match_device(msm_hsl_match_table, &pdev->dev);
@@ -1406,11 +1406,11 @@
msm_hsl_port->is_uartdm = 0;
if (unlikely(IS_ERR(msm_hsl_port->clk))) {
- printk(KERN_ERR "%s: Error getting clk\n", __func__);
+ pr_err("Error getting clk\n");
return PTR_ERR(msm_hsl_port->clk);
}
if (unlikely(IS_ERR(msm_hsl_port->pclk))) {
- printk(KERN_ERR "%s: Error getting pclk\n", __func__);
+ pr_err("Error getting pclk\n");
return PTR_ERR(msm_hsl_port->pclk);
}
@@ -1420,14 +1420,14 @@
if (!uart_resource)
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource)) {
- printk(KERN_ERR "getting uartdm_resource failed\n");
+ pr_err("getting uartdm_resource failed\n");
return -ENXIO;
}
port->mapbase = uart_resource->start;
port->irq = platform_get_irq(pdev, 0);
if (unlikely((int)port->irq < 0)) {
- printk(KERN_ERR "%s: getting irq failed\n", __func__);
+ pr_err("getting irq failed\n");
return -ENXIO;
}
@@ -1437,7 +1437,7 @@
#ifdef CONFIG_SERIAL_MSM_HSL_CONSOLE
ret = device_create_file(&pdev->dev, &dev_attr_console);
if (unlikely(ret))
- pr_err("%s():Can't create console attribute\n", __func__);
+ pr_err("Can't create console attribute\n");
#endif
msm_hsl_debugfs_init(msm_hsl_port, get_line(pdev));
@@ -1568,13 +1568,13 @@
debug_base = debugfs_create_dir("msm_serial_hsl", NULL);
if (IS_ERR_OR_NULL(debug_base))
- pr_err("%s():Cannot create debugfs dir\n", __func__);
+ pr_err("Cannot create debugfs dir\n");
ret = platform_driver_register(&msm_hsl_platform_driver);
if (unlikely(ret))
uart_unregister_driver(&msm_hsl_uart_driver);
- printk(KERN_INFO "msm_serial_hsl: driver initialized\n");
+ pr_info("driver initialized\n");
return ret;
}
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index a827d6a..372122c 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -886,7 +886,7 @@
outp32(MDP_INTR_CLEAR, mgmt->intr);
mdp_intr_mask &= ~mgmt->intr;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
- mdp_disable_irq(mgmt->irq_term);
+ mdp_disable_irq_nosync(mgmt->irq_term);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (mdp_rev >= MDP_REV_42)
diff --git a/drivers/video/msm/mdss/Makefile b/drivers/video/msm/mdss/Makefile
index 88a7c45..a0d707e 100644
--- a/drivers/video/msm/mdss/Makefile
+++ b/drivers/video/msm/mdss/Makefile
@@ -7,6 +7,7 @@
mdss-mdp-objs += mdss_mdp_wb.o
obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o
obj-$(CONFIG_FB_MSM_MDSS) += mdss_fb.o
+obj-$(CONFIG_DEBUG_FS) += mdss_debug.o
mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o
mdss-dsi-objs += mdss_dsi_panel.o
diff --git a/drivers/video/msm/mdss/mdss.h b/drivers/video/msm/mdss/mdss.h
index d041125..9e13418 100644
--- a/drivers/video/msm/mdss/mdss.h
+++ b/drivers/video/msm/mdss/mdss.h
@@ -61,6 +61,7 @@
struct delayed_work clk_ctrl_worker;
struct platform_device *pdev;
char __iomem *mdp_base;
+ size_t mdp_reg_size;
char __iomem *vbif_base;
u32 irq;
@@ -93,6 +94,7 @@
struct mdss_iommu_map_type *iommu_map;
struct early_suspend early_suspend;
+ void *debug_data;
};
extern struct mdss_data_type *mdss_res;
diff --git a/drivers/video/msm/mdss/mdss_debug.c b/drivers/video/msm/mdss/mdss_debug.c
new file mode 100644
index 0000000..abef27d
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_debug.c
@@ -0,0 +1,348 @@
+/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/debugfs.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#include "mdss.h"
+#include "mdss_mdp.h"
+#include "mdss_debug.h"
+
+#define DEFAULT_BASE_REG_CNT 128
+#define GROUP_BYTES 4
+#define ROW_BYTES 16
+
+struct mdss_debug_data {
+ struct dentry *root;
+ struct list_head base_list;
+};
+
+struct mdss_debug_base {
+ struct mdss_debug_data *mdd;
+ void __iomem *base;
+ size_t off;
+ size_t cnt;
+ size_t max_offset;
+ char *buf;
+ size_t buf_len;
+ struct list_head head;
+};
+
+static int mdss_debug_base_open(struct inode *inode, struct file *file)
+{
+ /* non-seekable */
+ file->f_mode &= ~(FMODE_LSEEK | FMODE_PREAD | FMODE_PWRITE);
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static int mdss_debug_base_release(struct inode *inode, struct file *file)
+{
+ struct mdss_debug_base *dbg = file->private_data;
+ if (dbg && dbg->buf) {
+ kfree(dbg->buf);
+ dbg->buf_len = 0;
+ dbg->buf = NULL;
+ }
+ return 0;
+}
+
+static ssize_t mdss_debug_base_offset_write(struct file *file,
+ const char __user *user_buf, size_t count, loff_t *ppos)
+{
+ struct mdss_debug_base *dbg = file->private_data;
+ u32 off, cnt;
+ char buf[24];
+
+ if (!dbg)
+ return -ENODEV;
+
+ if (count >= sizeof(buf))
+ return -EFAULT;
+
+ if (copy_from_user(buf, user_buf, count))
+ return -EFAULT;
+
+ buf[count] = 0; /* end of string */
+
+ sscanf(buf, "%5x %d", &off, &cnt);
+
+ if (off > dbg->max_offset)
+ return -EINVAL;
+
+ if (cnt <= 0)
+ cnt = DEFAULT_BASE_REG_CNT;
+
+ if (cnt > (dbg->max_offset - off))
+ cnt = dbg->max_offset - off;
+
+ dbg->off = off;
+ dbg->cnt = cnt;
+
+ pr_debug("offset=%x cnt=%x\n", off, cnt);
+
+ return count;
+}
+
+static ssize_t mdss_debug_base_offset_read(struct file *file,
+ char __user *buff, size_t count, loff_t *ppos)
+{
+ struct mdss_debug_base *dbg = file->private_data;
+ int len = 0;
+ char buf[24];
+
+ if (!dbg)
+ return -ENODEV;
+
+ if (*ppos)
+ return 0; /* the end */
+
+ len = snprintf(buf, sizeof(buf), "0x%08x %d\n", dbg->off, dbg->off);
+ if (len < 0)
+ return 0;
+
+ if (copy_to_user(buff, buf, len))
+ return -EFAULT;
+
+ *ppos += len; /* increase offset */
+
+ return len;
+}
+
+static ssize_t mdss_debug_base_reg_write(struct file *file,
+ const char __user *user_buf, size_t count, loff_t *ppos)
+{
+ struct mdss_debug_base *dbg = file->private_data;
+ size_t off;
+ u32 data, cnt;
+ char buf[24];
+
+ if (!dbg)
+ return -ENODEV;
+
+ if (count >= sizeof(buf))
+ return -EFAULT;
+
+ if (copy_from_user(buf, user_buf, count))
+ return -EFAULT;
+
+ buf[count] = 0; /* end of string */
+
+ cnt = sscanf(buf, "%x %x", &off, &data);
+
+ if (cnt < 2)
+ return -EFAULT;
+
+ if (off >= dbg->max_offset)
+ return -EFAULT;
+
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ writel_relaxed(data, dbg->base + off);
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+
+ pr_debug("addr=%x data=%x\n", off, data);
+
+ return count;
+}
+
+static ssize_t mdss_debug_base_reg_read(struct file *file,
+ char __user *user_buf, size_t count, loff_t *ppos)
+{
+ struct mdss_debug_base *dbg = file->private_data;
+ size_t len;
+
+ if (!dbg) {
+ pr_err("invalid handle\n");
+ return -ENODEV;
+ }
+
+ if (!dbg->buf) {
+ char dump_buf[64];
+ char *ptr;
+ int cnt, tot;
+
+ dbg->buf_len = sizeof(dump_buf) *
+ DIV_ROUND_UP(dbg->cnt, ROW_BYTES);
+ dbg->buf = kzalloc(dbg->buf_len, GFP_KERNEL);
+
+ if (!dbg->buf) {
+ pr_err("not enough memory to hold reg dump\n");
+ return -ENOMEM;
+ }
+
+ ptr = dbg->base + dbg->off;
+ tot = 0;
+
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ for (cnt = dbg->cnt; cnt > 0; cnt -= ROW_BYTES) {
+ hex_dump_to_buffer(ptr, min(cnt, ROW_BYTES),
+ ROW_BYTES, GROUP_BYTES, dump_buf,
+ sizeof(dump_buf), false);
+ len = scnprintf(dbg->buf + tot, dbg->buf_len - tot,
+ "0x%08x: %s\n",
+ ((int)ptr) - ((int)dbg->base),
+ dump_buf);
+
+ ptr += ROW_BYTES;
+ tot += len;
+ if (tot >= dbg->buf_len)
+ break;
+ }
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+
+ dbg->buf_len = tot;
+ }
+
+ if (*ppos >= dbg->buf_len)
+ return 0; /* done reading */
+
+ len = min(count, dbg->buf_len - (size_t) *ppos);
+ if (copy_to_user(user_buf, dbg->buf + *ppos, len)) {
+ pr_err("failed to copy to user\n");
+ return -EFAULT;
+ }
+
+ *ppos += len; /* increase offset */
+
+ return len;
+}
+
+static const struct file_operations mdss_off_fops = {
+ .open = mdss_debug_base_open,
+ .release = mdss_debug_base_release,
+ .read = mdss_debug_base_offset_read,
+ .write = mdss_debug_base_offset_write,
+};
+
+static const struct file_operations mdss_reg_fops = {
+ .open = mdss_debug_base_open,
+ .release = mdss_debug_base_release,
+ .read = mdss_debug_base_reg_read,
+ .write = mdss_debug_base_reg_write,
+};
+
+int mdss_debug_register_base(const char *name, void __iomem *base,
+ size_t max_offset)
+{
+ struct mdss_data_type *mdata = mdss_res;
+ struct mdss_debug_data *mdd;
+ struct mdss_debug_base *dbg;
+ struct dentry *ent_off, *ent_reg;
+ char dn[80] = "";
+ int prefix_len = 0;
+
+ if (!mdata || !mdata->debug_data)
+ return -ENODEV;
+
+ mdd = mdata->debug_data;
+
+ dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
+ if (!dbg)
+ return -ENOMEM;
+
+ dbg->base = base;
+ dbg->max_offset = max_offset;
+ dbg->off = 0;
+ dbg->cnt = DEFAULT_BASE_REG_CNT;
+
+ if (name)
+ prefix_len = snprintf(dn, sizeof(dn), "%s_", name);
+
+ strlcpy(dn + prefix_len, "off", sizeof(dn) - prefix_len);
+ ent_off = debugfs_create_file(dn, 0644, mdd->root, dbg, &mdss_off_fops);
+ if (IS_ERR_OR_NULL(ent_off)) {
+ pr_err("debugfs_create_file: offset fail\n");
+ goto off_fail;
+ }
+
+ strlcpy(dn + prefix_len, "reg", sizeof(dn) - prefix_len);
+ ent_reg = debugfs_create_file(dn, 0644, mdd->root, dbg, &mdss_reg_fops);
+ if (IS_ERR_OR_NULL(ent_reg)) {
+ pr_err("debugfs_create_file: reg fail\n");
+ goto reg_fail;
+ }
+
+ list_add(&dbg->head, &mdd->base_list);
+
+ return 0;
+reg_fail:
+ debugfs_remove(ent_off);
+off_fail:
+ kfree(dbg);
+ return -ENODEV;
+}
+
+static int mdss_debugfs_cleanup(struct mdss_debug_data *mdd)
+{
+ struct mdss_debug_base *base, *tmp;
+
+ if (!mdd)
+ return 0;
+
+ list_for_each_entry_safe(base, tmp, &mdd->base_list, head) {
+ list_del(&base->head);
+ kfree(base);
+ }
+
+ if (mdd->root)
+ debugfs_remove_recursive(mdd->root);
+
+ kfree(mdd);
+
+ return 0;
+}
+
+int mdss_debugfs_init(struct mdss_data_type *mdata)
+{
+ struct mdss_debug_data *mdd;
+
+ if (mdata->debug_data) {
+ pr_warn("mdss debugfs already initialized\n");
+ return -EBUSY;
+ }
+
+ mdd = kzalloc(sizeof(*mdd), GFP_KERNEL);
+ if (!mdd) {
+ pr_err("no memory to create mdss debug data\n");
+ return -ENOMEM;
+ }
+ INIT_LIST_HEAD(&mdd->base_list);
+
+ mdd->root = debugfs_create_dir("mdp", NULL);
+ if (IS_ERR_OR_NULL(mdd->root)) {
+ pr_err("debugfs_create_dir fail, error %ld\n",
+ PTR_ERR(mdd->root));
+ mdd->root = NULL;
+ mdss_debugfs_cleanup(mdd);
+ return -ENODEV;
+ }
+
+ mdata->debug_data = mdd;
+
+ return 0;
+}
+
+int mdss_debugfs_remove(struct mdss_data_type *mdata)
+{
+ struct mdss_debug_data *mdd = mdata->debug_data;
+
+ mdss_debugfs_cleanup(mdd);
+
+ return 0;
+}
diff --git a/drivers/video/msm/mdss/mdss_debug.h b/drivers/video/msm/mdss/mdss_debug.h
new file mode 100644
index 0000000..167fa8a
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_debug.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef MDSS_DEBUG_H
+#define MDSS_DEBUG_H
+
+#include "mdss.h"
+
+#ifdef CONFIG_DEBUG_FS
+int mdss_debugfs_init(struct mdss_data_type *mdata);
+int mdss_debugfs_remove(struct mdss_data_type *mdata);
+int mdss_debug_register_base(const char *name, void __iomem *base,
+ size_t max_offset);
+#else
+static inline int mdss_debugfs_init(struct mdss_data_type *mdata)
+{
+ return 0;
+}
+static inline int mdss_debugfs_remove(struct mdss_data_type *mdata)
+{
+ return 0;
+}
+static inline int mdss_debug_register_base(const char *name, void __iomem *base,
+ size_t max_offset)
+{
+ return 0;
+}
+#endif
+#endif /* MDSS_DEBUG_H */
diff --git a/drivers/video/msm/mdss/mdss_edp.c b/drivers/video/msm/mdss/mdss_edp.c
index 1cf3101..227619f 100644
--- a/drivers/video/msm/mdss/mdss_edp.c
+++ b/drivers/video/msm/mdss/mdss_edp.c
@@ -303,10 +303,10 @@
}
mdss_edp_prepare_clocks(edp_drv);
- mdss_edp_clk_enable(edp_drv);
mdss_edp_phy_sw_reset(edp_drv->edp_base);
mdss_edp_hw_powerup(edp_drv->edp_base, 1);
mdss_edp_pll_configure(edp_drv->edp_base, edp_drv->edid.timing[0].pclk);
+ mdss_edp_clk_enable(edp_drv);
for (i = 0; i < edp_drv->dpcd.max_lane_count; ++i)
mdss_edp_enable_lane_bist(edp_drv->edp_base, i, 1);
@@ -346,8 +346,8 @@
for (i = 0; i < edp_drv->dpcd.max_lane_count; ++i)
mdss_edp_enable_lane_bist(edp_drv->edp_base, i, 0);
- mdss_edp_hw_powerup(edp_drv->edp_base, 0);
mdss_edp_clk_disable(edp_drv);
+ mdss_edp_hw_powerup(edp_drv->edp_base, 0);
mdss_edp_unprepare_clocks(edp_drv);
return ret;
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 4ec4046..f363206 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -131,8 +131,8 @@
/* This maps android backlight level 0 to 255 into
driver backlight level 0 to bl_max with rounding */
- bl_lvl = (2 * value * mfd->panel_info.bl_max + MAX_BACKLIGHT_BRIGHTNESS)
- /(2 * MAX_BACKLIGHT_BRIGHTNESS);
+ bl_lvl = (2 * value * mfd->panel_info->bl_max +
+ MAX_BACKLIGHT_BRIGHTNESS) / (2 * MAX_BACKLIGHT_BRIGHTNESS);
if (!bl_lvl && value)
bl_lvl = 1;
@@ -155,7 +155,7 @@
struct fb_info *fbi = dev_get_drvdata(dev);
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)fbi->par;
- switch (mfd->panel_info.type) {
+ switch (mfd->panel.type) {
case NO_PANEL:
ret = snprintf(buf, PAGE_SIZE, "no panel\n");
break;
@@ -239,13 +239,13 @@
mfd = (struct msm_fb_data_type *)fbi->par;
mfd->key = MFD_KEY;
mfd->fbi = fbi;
- mfd->panel_info = pdata->panel_info;
+ mfd->panel_info = &pdata->panel_info;
mfd->panel.type = pdata->panel_info.type;
mfd->panel.id = mfd->index;
mfd->fb_page = MDSS_FB_NUM;
mfd->index = fbi_list_index;
mfd->mdp_fb_page_protection = MDP_FB_PAGE_PROTECTION_WRITECOMBINE;
- mfd->panel_info.frame_count = 0;
+
mfd->bl_level = 0;
mfd->bl_scale = 1024;
mfd->bl_min_lvl = 30;
@@ -263,14 +263,6 @@
if (rc)
return rc;
- /*
- * todo: Currently mfd keeps a full copy of panel data rather than
- * pointer to it.
- * Following line shares the fbi with panel drivers for their
- * sysfs or any external communications with the panel driver.
- */
- pdata->panel_info.fbi = fbi;
-
rc = pm_runtime_set_active(mfd->fbi->dev);
if (rc < 0)
pr_err("pm_runtime: fail to set active.\n");
@@ -439,52 +431,11 @@
return result;
}
-#if defined(CONFIG_PM) && defined(CONFIG_SUSPEND)
-static int mdss_fb_ext_suspend(struct device *dev)
-{
- struct msm_fb_data_type *mfd = dev_get_drvdata(dev);
- int ret = 0;
-
- if ((!mfd) || (mfd->key != MFD_KEY))
- return 0;
-
- if (mfd->panel_info.type == HDMI_PANEL ||
- mfd->panel_info.type == DTV_PANEL)
- ret = mdss_fb_suspend_sub(mfd);
-
- return ret;
-}
-
-static int mdss_fb_ext_resume(struct device *dev)
-{
- struct msm_fb_data_type *mfd = dev_get_drvdata(dev);
- int ret = 0;
-
- if ((!mfd) || (mfd->key != MFD_KEY))
- return 0;
-
- if (mfd->panel_info.type == HDMI_PANEL ||
- mfd->panel_info.type == DTV_PANEL)
- ret = mdss_fb_resume_sub(mfd);
-
- return ret;
-}
-#else
-#define mdss_fb_ext_suspend NULL
-#define mdss_fb_ext_resume NULL
-#endif
-
-static const struct dev_pm_ops mdss_fb_dev_pm_ops = {
- .suspend = mdss_fb_ext_suspend,
- .resume = mdss_fb_ext_resume,
-};
-
static struct platform_driver mdss_fb_driver = {
.probe = mdss_fb_probe,
.remove = mdss_fb_remove,
.driver = {
.name = "mdss_fb",
- .pm = &mdss_fb_dev_pm_ops,
},
};
@@ -716,9 +667,9 @@
void *virt = NULL;
unsigned long phys = 0;
size_t size;
+ u32 yres = mfd->fbi->var.yres_virtual;
- size = PAGE_ALIGN(mfd->fbi->fix.line_length * mfd->panel_info.yres);
- size *= mfd->fb_page;
+ size = PAGE_ALIGN(mfd->fbi->fix.line_length * yres);
if (mfd->index == 0) {
int dom;
@@ -751,7 +702,7 @@
{
int ret = -ENODEV;
int bpp;
- struct mdss_panel_info *panel_info = &mfd->panel_info;
+ struct mdss_panel_info *panel_info = mfd->panel_info;
struct fb_info *fbi = mfd->fbi;
struct fb_fix_screeninfo *fix;
struct fb_var_screeninfo *var;
@@ -1050,8 +1001,6 @@
mfd->panel.type);
mdss_fb_update_backlight(mfd);
-
- ++mfd->panel_info.frame_count;
return 0;
}
@@ -1147,8 +1096,8 @@
if ((var->xres == 0) || (var->yres == 0))
return -EINVAL;
- if ((var->xres > mfd->panel_info.xres) ||
- (var->yres > mfd->panel_info.yres))
+ if ((var->xres > mfd->panel_info->xres) ||
+ (var->yres > mfd->panel_info->yres))
return -EINVAL;
if (var->xoffset > (var->xres_virtual - var->xres))
diff --git a/drivers/video/msm/mdss/mdss_fb.h b/drivers/video/msm/mdss/mdss_fb.h
index 5e57de6..b7bd4e6 100644
--- a/drivers/video/msm/mdss/mdss_fb.h
+++ b/drivers/video/msm/mdss/mdss_fb.h
@@ -55,7 +55,7 @@
u32 fb_page;
struct panel_id panel;
- struct mdss_panel_info panel_info;
+ struct mdss_panel_info *panel_info;
u32 dest;
struct fb_info *fbi;
diff --git a/drivers/video/msm/mdss/mdss_mdp.c b/drivers/video/msm/mdss/mdss_mdp.c
index bcb3aee..b59d193 100644
--- a/drivers/video/msm/mdss/mdss_mdp.c
+++ b/drivers/video/msm/mdss/mdss_mdp.c
@@ -49,6 +49,7 @@
#include "mdss.h"
#include "mdss_fb.h"
#include "mdss_mdp.h"
+#include "mdss_debug.h"
struct mdss_data_type *mdss_res;
@@ -772,6 +773,19 @@
return 0;
}
+static int mdss_mdp_debug_init(struct mdss_data_type *mdata)
+{
+ int rc;
+
+ rc = mdss_debugfs_init(mdata);
+ if (rc)
+ return rc;
+
+ mdss_debug_register_base(NULL, mdata->mdp_base, mdata->mdp_reg_size);
+
+ return 0;
+}
+
static int mdss_hw_init(struct mdss_data_type *mdata)
{
char *base = mdata->vbif_base;
@@ -875,8 +889,9 @@
goto probe_done;
}
+ mdata->mdp_reg_size = resource_size(res);
mdata->mdp_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ mdata->mdp_reg_size);
if (unlikely(!mdata->mdp_base)) {
pr_err("unable to map MDP base\n");
rc = -ENOMEM;
@@ -933,6 +948,11 @@
pr_err("unable to register early suspend\n");
goto probe_done;
}
+
+ rc = mdss_mdp_debug_init(mdata);
+ if (rc)
+ pr_err("unable to initialize mdp debugging\n");
+
probe_done:
if (IS_ERR_VALUE(rc)) {
mdss_res = NULL;
@@ -1099,6 +1119,7 @@
mdss_mdp_pp_term(&pdev->dev);
mdss_mdp_bus_scale_unregister(mdata);
mdss_mdp_remove_early_suspend(mdata);
+ mdss_debugfs_remove(mdata);
return 0;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index 2e92591..157a7eb 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -137,6 +137,8 @@
struct mdss_mdp_mixer *mixer_right;
struct mutex lock;
+ struct mdss_panel_data *panel_data;
+
int (*start_fnc) (struct mdss_mdp_ctl *ctl);
int (*stop_fnc) (struct mdss_mdp_ctl *ctl);
int (*prepare_fnc) (struct mdss_mdp_ctl *ctl, void *arg);
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index 00f5874..bd7371b 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -107,7 +107,7 @@
int is_writeback = false;
if (mixer->type == MDSS_MDP_MIXER_TYPE_INTF) {
struct mdss_panel_info *pinfo;
- pinfo = &mixer->ctl->mfd->panel_info;
+ pinfo = &mixer->ctl->panel_data->panel_info;
v_total = (pinfo->yres + pinfo->lcdc.v_back_porch +
pinfo->lcdc.v_front_porch +
pinfo->lcdc.v_pulse_width);
@@ -378,12 +378,19 @@
static int mdss_mdp_ctl_init(struct msm_fb_data_type *mfd)
{
struct mdss_mdp_ctl *ctl;
+ struct mdss_panel_data *pdata;
u32 width, height;
int ret = 0;
if (!mfd)
return -ENODEV;
+ pdata = dev_get_platdata(&mfd->pdev->dev);
+ if (!pdata) {
+ pr_err("no panel connected for fb%d\n", mfd->index);
+ return -ENODEV;
+ }
+
width = mfd->fbi->var.xres;
height = mfd->fbi->var.yres;
@@ -400,6 +407,7 @@
}
ctl->mfd = mfd;
mfd->ctl = ctl;
+ ctl->panel_data = pdata;
} else {
ctl = mfd->ctl;
}
@@ -441,7 +449,7 @@
mdss_mdp_mixer_free(ctl->mixer_right);
}
- switch (mfd->panel_info.type) {
+ switch (pdata->panel_info.type) {
case EDP_PANEL:
ctl->intf_num = MDSS_MDP_INTF0;
ctl->intf_type = MDSS_INTF_EDP;
@@ -449,7 +457,7 @@
ctl->start_fnc = mdss_mdp_video_start;
break;
case MIPI_VIDEO_PANEL:
- if (mfd->panel_info.pdest == DISPLAY_1)
+ if (pdata->panel_info.pdest == DISPLAY_1)
ctl->intf_num = MDSS_MDP_INTF1;
else
ctl->intf_num = MDSS_MDP_INTF2;
@@ -469,7 +477,7 @@
ctl->start_fnc = mdss_mdp_writeback_start;
break;
default:
- pr_err("unsupported panel type (%d)\n", mfd->panel_info.type);
+ pr_err("unsupported panel type (%d)\n", pdata->panel_info.type);
ret = -EINVAL;
goto ctl_init_fail;
}
@@ -477,14 +485,14 @@
ctl->opmode |= (ctl->intf_num << 4);
if (ctl->intf_num == MDSS_MDP_NO_INTF) {
- ctl->dst_format = mfd->panel_info.out_format;
+ ctl->dst_format = pdata->panel_info.out_format;
} else {
struct mdp_dither_cfg_data dither = {
.block = mfd->index + MDP_LOGICAL_BLOCK_DISP_0,
.flags = MDP_PP_OPS_DISABLE,
};
- switch (mfd->panel_info.bpp) {
+ switch (pdata->panel_info.bpp) {
case 18:
ctl->dst_format = MDSS_MDP_PANEL_FORMAT_RGB666;
dither.flags = MDP_PP_OPS_ENABLE | MDP_PP_OPS_WRITE;
@@ -539,14 +547,10 @@
int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg)
{
struct mdss_panel_data *pdata;
- if (!ctl || !ctl->mfd)
+ if (!ctl || !ctl->panel_data)
return -ENODEV;
- pdata = dev_get_platdata(&ctl->mfd->pdev->dev);
- if (!pdata) {
- pr_err("no panel connected\n");
- return -ENODEV;
- }
+ pdata = ctl->panel_data;
pr_debug("sending ctl=%d event=%d\n", ctl->num, event);
@@ -596,7 +600,7 @@
ret = ctl->start_fnc(ctl);
else
pr_warn("no start function for ctl=%d type=%d\n", ctl->num,
- mfd->panel_info.type);
+ ctl->panel_data->panel_info.type);
if (ret) {
pr_err("unable to start intf\n");
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index 052d78c..4757c63 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -337,17 +337,13 @@
int mdss_mdp_video_start(struct mdss_mdp_ctl *ctl)
{
- struct msm_fb_data_type *mfd;
struct mdss_panel_info *pinfo;
struct mdss_mdp_video_ctx *ctx;
struct mdss_mdp_mixer *mixer;
struct intf_timing_params itp = {0};
- struct fb_info *fbi;
int i;
- mfd = ctl->mfd;
- fbi = mfd->fbi;
- pinfo = &mfd->panel_info;
+ pinfo = &ctl->panel_data->panel_info;
mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_LEFT);
if (!mixer) {
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 9c62ea2..61c1e9f 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -682,7 +682,7 @@
} else {
ret = mdss_mdp_overlay_queue(mfd, req);
- if ((ret == 0) && (mfd->panel_info.type == WRITEBACK_PANEL)) {
+ if ((ret == 0) && (mfd->panel.type == WRITEBACK_PANEL)) {
mutex_unlock(&mfd->ov_lock);
ret = mdss_mdp_overlay_kickoff(mfd->ctl);
return ret;
@@ -1167,7 +1167,7 @@
ret = mdss_mdp_overlay_kickoff(mfd->ctl);
break;
default:
- if (mfd->panel_info.type == WRITEBACK_PANEL)
+ if (mfd->panel.type == WRITEBACK_PANEL)
ret = mdss_mdp_wb_ioctl_handler(mfd, cmd, argp);
break;
}
@@ -1215,7 +1215,7 @@
mfd->dma_fnc = mdss_mdp_overlay_pan_display;
mfd->ioctl_handler = mdss_mdp_overlay_ioctl_handler;
- if (mfd->panel_info.type == WRITEBACK_PANEL)
+ if (mfd->panel.type == WRITEBACK_PANEL)
mfd->kickoff_fnc = mdss_mdp_wb_kickoff;
INIT_LIST_HEAD(&mfd->pipes_used);
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
index 7a1d521..8836b33 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl.h
@@ -275,6 +275,7 @@
struct ddl_enc_buffers hw_bufs;
struct ddl_yuv_buffer_size input_buf_size;
struct vidc_1080p_enc_frame_info enc_frame_info;
+ u32 plusptype_enable;
u32 meta_data_enable_flag;
u32 suffix;
u32 meta_data_offset;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
index 332497f..2b65d7e 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
@@ -1075,6 +1075,21 @@
}
break;
}
+ case VCD_I_H263_PLUSPTYPE:
+ {
+ struct vcd_property_plusptype *plusptype =
+ (struct vcd_property_plusptype *)property_value;
+
+ if ((sizeof(struct vcd_property_plusptype) ==
+ property_hdr->sz) && encoder->codec.codec ==
+ VCD_CODEC_H263) {
+ encoder->plusptype_enable = plusptype->plusptype_enable;
+ DDL_MSG_LOW("\nencoder->plusptype_enable = %u",
+ encoder->plusptype_enable);
+ vcd_status = VCD_S_SUCCESS;
+ }
+ break;
+ }
default:
DDL_MSG_ERROR("INVALID ID %d\n", (int)property_hdr->prop_id);
vcd_status = VCD_ERR_ILLEGAL_OP;
@@ -2169,5 +2184,6 @@
encoder->frame_rate.fps_denominator = 1;
ddl_set_default_enc_property(ddl);
encoder->sps_pps.sps_pps_for_idr_enable_flag = false;
+ encoder->plusptype_enable = 0;
}
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
index 76972ca..1bf242d 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
@@ -599,7 +599,7 @@
encoder->frame_rate.fps_denominator;
if ((encoder->codec.codec == VCD_CODEC_H263) &&
(DDL_FRAMERATE_SCALE(DDL_INITIAL_FRAME_RATE)
- != scaled_frame_rate))
+ != scaled_frame_rate) && encoder->plusptype_enable)
h263_cpfc_enable = true;
vidc_sm_set_extended_encoder_control(&ddl->shared_mem
[ddl->command_channel], hdr_ext_control,
diff --git a/drivers/video/msm/vidc/common/enc/venc.c b/drivers/video/msm/vidc/common/enc/venc.c
index c7237e4..763fbda 100644
--- a/drivers/video/msm/vidc/common/enc/venc.c
+++ b/drivers/video/msm/vidc/common/enc/venc.c
@@ -1624,6 +1624,29 @@
}
break;
}
+ case VEN_IOCTL_SET_H263_PLUSPTYPE:
+ {
+ struct vcd_property_hdr vcd_property_hdr;
+ struct venc_plusptype plusptype;
+ u32 enable;
+ u32 vcd_status = VCD_ERR_FAIL;
+ if (copy_from_user(&venc_msg, arg, sizeof(venc_msg)))
+ return -EFAULT;
+ if (copy_from_user(&plusptype, venc_msg.in,
+ sizeof(plusptype)))
+ return -EFAULT;
+ vcd_property_hdr.prop_id = VCD_I_H263_PLUSPTYPE;
+ vcd_property_hdr.sz = sizeof(u32);
+ enable = plusptype.plusptype_enable;
+ DBG("VEN_IOCTL_SET PLUSPTYPE = %d\n", enable);
+ vcd_status = vcd_set_property(client_ctx->vcd_handle,
+ &vcd_property_hdr, &enable);
+ if (vcd_status) {
+ pr_err(" Setting plusptype failed");
+ return -EIO;
+ }
+ break;
+ }
case VEN_IOCTL_SET_AC_PREDICTION:
case VEN_IOCTL_GET_AC_PREDICTION:
case VEN_IOCTL_SET_RVLC:
diff --git a/drivers/video/msm/vidc/common/vcd/vcd.h b/drivers/video/msm/vidc/common/vcd/vcd.h
index 8f44a56..a22adeb 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd.h
+++ b/drivers/video/msm/vidc/common/vcd/vcd.h
@@ -398,4 +398,8 @@
u32 vcd_update_decoder_perf_level(struct vcd_dev_ctxt *dev_ctxt, u32 perf_lvl);
u32 vcd_set_perf_turbo_level(struct vcd_clnt_ctxt *cctxt);
+
+struct vcd_transc *vcd_get_first_in_use_trans_for_clnt(
+ struct vcd_clnt_ctxt *cctxt);
+
#endif
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_sub.c b/drivers/video/msm/vidc/common/vcd/vcd_sub.c
index b84ae44..a4c44f3 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_sub.c
+++ b/drivers/video/msm/vidc/common/vcd/vcd_sub.c
@@ -1684,7 +1684,7 @@
void vcd_send_frame_done_in_eos(struct vcd_clnt_ctxt *cctxt,
struct vcd_frame_data *input_frame, u32 valid_opbuf)
{
- VCD_MSG_LOW("vcd_send_frame_done_in_eos:");
+ VCD_MSG_HIGH("vcd_send_frame_done_in_eos:");
if (!input_frame->virtual && !valid_opbuf) {
VCD_MSG_MED("Sending NULL output with EOS");
@@ -1804,12 +1804,41 @@
}
}
+struct vcd_transc *vcd_get_first_in_use_trans_for_clnt(
+ struct vcd_clnt_ctxt *cctxt)
+{
+ u32 i;
+ struct vcd_dev_ctxt *dev_ctxt;
+ VCD_MSG_HIGH("%s: ", __func__);
+ dev_ctxt = cctxt->dev_ctxt;
+ if (!dev_ctxt->trans_tbl) {
+ VCD_MSG_ERROR("%s: Null trans_tbl", __func__);
+ return NULL;
+ }
+ i = 0;
+ while (i < dev_ctxt->trans_tbl_size) {
+ if ((cctxt == dev_ctxt->trans_tbl[i].cctxt) &&
+ (dev_ctxt->trans_tbl[i].in_use)) {
+ VCD_MSG_MED("%s: found transc = 0x%p",
+ __func__, &dev_ctxt->trans_tbl[i]);
+ break;
+ }
+ i++;
+ }
+ if (i == dev_ctxt->trans_tbl_size) {
+ VCD_MSG_ERROR("%s: in_use transction not found",
+ __func__);
+ return NULL;
+ } else
+ return &dev_ctxt->trans_tbl[i];
+}
+
u32 vcd_handle_recvd_eos(
struct vcd_clnt_ctxt *cctxt,
struct vcd_frame_data *input_frame, u32 *pb_eos_handled)
{
u32 rc;
-
+ struct vcd_transc *transc;
VCD_MSG_LOW("vcd_handle_recvd_eos:");
*pb_eos_handled = false;
@@ -1827,13 +1856,21 @@
*pb_eos_handled = true;
else if (cctxt->decoding && !input_frame->virtual)
cctxt->sched_clnt_hdl->tkns++;
- else if (!cctxt->decoding) {
- vcd_send_frame_done_in_eos(cctxt, input_frame, false);
- if (cctxt->status.mask & VCD_EOS_WAIT_OP_BUF) {
- vcd_do_client_state_transition(cctxt,
- VCD_CLIENT_STATE_EOS,
- CLIENT_STATE_EVENT_NUMBER
- (encode_frame));
+ else if (!cctxt->decoding && !cctxt->status.frame_delayed) {
+ if (!cctxt->status.frame_submitted) {
+ vcd_send_frame_done_in_eos(cctxt, input_frame, false);
+ if (cctxt->status.mask & VCD_EOS_WAIT_OP_BUF)
+ vcd_do_client_state_transition(cctxt,
+ VCD_CLIENT_STATE_EOS,
+ CLIENT_STATE_EVENT_NUMBER
+ (encode_frame));
+ } else {
+ transc = vcd_get_first_in_use_trans_for_clnt(cctxt);
+ if (transc) {
+ transc->flags |= VCD_FRAME_FLAG_EOS;
+ VCD_MSG_HIGH("%s: Add EOS flag to transc",
+ __func__);
+ }
}
*pb_eos_handled = true;
}
diff --git a/include/linux/ion.h b/include/linux/ion.h
index 211327f..3a29f20 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -33,12 +33,14 @@
* @ION_HEAP_TYPE_CP: memory allocated from a prereserved
* carveout heap, allocations are physically
* contiguous. Used for content protection.
+ * @ION_HEAP_TYPE_DMA: memory allocated via DMA API
* @ION_HEAP_END: helper for iterating over heaps
*/
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
+ ION_HEAP_TYPE_DMA,
ION_HEAP_TYPE_CUSTOM, /* must be last so device specific heaps always
are at the end of this enum */
ION_NUM_HEAPS,
@@ -47,6 +49,7 @@
#define ION_HEAP_SYSTEM_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define ION_HEAP_SYSTEM_CONTIG_MASK (1 << ION_HEAP_TYPE_SYSTEM_CONTIG)
#define ION_HEAP_CARVEOUT_MASK (1 << ION_HEAP_TYPE_CARVEOUT)
+#define ION_HEAP_TYPE_DMA_MASK (1 << ION_HEAP_TYPE_DMA)
/**
* heap flags - the lower 16 bits are used by core ion, the upper 16
@@ -84,6 +87,7 @@
* @memory_type:Memory type used for the heap
* @has_outer_cache: set to 1 if outer cache is used, 0 otherwise.
* @extra_data: Extra data specific to each heap type
+ * @priv: heap private data
*/
struct ion_platform_heap {
enum ion_heap_type type;
@@ -94,6 +98,7 @@
enum ion_memory_types memory_type;
unsigned int has_outer_cache;
void *extra_data;
+ void *priv;
};
/**
@@ -115,7 +120,7 @@
int (*request_region)(void *);
int (*release_region)(void *);
void *(*setup_region)(void);
- struct ion_platform_heap heaps[];
+ struct ion_platform_heap *heaps;
};
#ifdef CONFIG_ION
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 12094e2..ae2c3d8 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -89,6 +89,7 @@
* area
* @max_bat_chg_current: Max charge current of the battery in mA
* Usually 70% of full charge capacity
+ * @usb_max_current: Maximum USB current in mA
* @cool_bat_chg_current: chg current (mA) when the battery is cool
* @warm_bat_chg_current: chg current (mA) when the battery is warm
* @cool_bat_voltage: chg voltage (mV) when the battery is cool
@@ -140,6 +141,7 @@
int warm_temp;
unsigned int temp_check_period;
unsigned int max_bat_chg_current;
+ unsigned int usb_max_current;
unsigned int cool_bat_chg_current;
unsigned int warm_bat_chg_current;
unsigned int cool_bat_voltage;
diff --git a/include/linux/msm_ion.h b/include/linux/msm_ion.h
index ec043dd..21648ad 100644
--- a/include/linux/msm_ion.h
+++ b/include/linux/msm_ion.h
@@ -146,6 +146,7 @@
size_t secure_size; /* Size used for securing heap when heap is shared*/
int reusable;
int mem_is_fmem;
+ int is_cma;
enum ion_fixed_position fixed_position;
int iommu_map_all;
int iommu_2x_map_domain;
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index ee136cac..4e62b4f 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -27,6 +27,7 @@
/* General allocation hints */
#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000
+#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000
/* Memory caching hints */
#define KGSL_CACHEMODE_MASK 0x0C000000
@@ -554,6 +555,8 @@
* KGSL_MEMFLAGS_GPUREADONLY: the GPU will be unable to write to the buffer
* KGSL_MEMTYPE*: usage hint for debugging aid
* KGSL_MEMALIGN*: alignment hint, may be ignored or adjusted by the kernel.
+ * KGSL_MEMFLAGS_USE_CPU_MAP: If set on call and return, the returned GPU
+ * address will be 0. Calling mmap() will set the GPU address.
*/
struct kgsl_gpumem_alloc_id {
unsigned int id;
diff --git a/include/linux/msm_vidc_enc.h b/include/linux/msm_vidc_enc.h
index 519c537..ea7db81 100644
--- a/include/linux/msm_vidc_enc.h
+++ b/include/linux/msm_vidc_enc.h
@@ -458,6 +458,9 @@
#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE \
_IO(VEN_IOCTLBASE_ENC, 50)
+#define VEN_IOCTL_SET_H263_PLUSPTYPE \
+ _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg)
+
struct venc_switch{
unsigned char status;
};
@@ -519,6 +522,11 @@
unsigned long maxqp;
unsigned long minqp;
};
+
+struct venc_plusptype {
+ unsigned long plusptype_enable;
+};
+
struct venc_intraperiod{
unsigned long num_pframes;
unsigned long num_bframes;
diff --git a/include/media/msm/vcd_property.h b/include/media/msm/vcd_property.h
index 545dcd2..2ce1a88 100644
--- a/include/media/msm/vcd_property.h
+++ b/include/media/msm/vcd_property.h
@@ -57,6 +57,7 @@
#define VCD_I_SET_TURBO_CLK (VCD_START_BASE + 0x29)
#define VCD_I_ENABLE_DELIMITER_FLAG (VCD_START_BASE + 0x2A)
#define VCD_I_ENABLE_VUI_TIMING_INFO (VCD_START_BASE + 0x2B)
+#define VCD_I_H263_PLUSPTYPE (VCD_START_BASE + 0x2C)
#define VCD_START_REQ (VCD_START_BASE + 0x1000)
@@ -294,6 +295,10 @@
u32 min_qp;
};
+struct vcd_property_plusptype {
+ u32 plusptype_enable;
+};
+
struct vcd_property_session_qp {
u32 i_frame_qp;
u32 p_frame_qp;
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index fa2469e..44e2feb 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -93,6 +93,13 @@
static void l2cap_conn_del(struct hci_conn *hcon, int err, u8 is_process);
static u16 l2cap_get_smallest_flushto(struct l2cap_chan_list *l);
static void l2cap_set_acl_flushto(struct hci_conn *hcon, u16 flush_to);
+static void l2cap_queue_acl_data(struct work_struct *worker);
+static struct att_channel_parameters{
+ struct sk_buff *skb;
+ struct l2cap_conn *conn;
+ __le16 cid;
+ int dir;
+} att_chn_params;
/* ---- L2CAP channels ---- */
static struct sock *__l2cap_get_chan_by_dcid(struct l2cap_chan_list *l, u16 cid)
@@ -1209,6 +1216,8 @@
kfree(conn);
}
+ att_chn_params.conn = NULL;
+ BT_DBG("att_chn_params.conn set to NULL");
}
static inline void l2cap_chan_add(struct l2cap_conn *conn, struct sock *sk)
@@ -3600,8 +3609,7 @@
if (mtu < L2CAP_DEFAULT_MIN_MTU) {
result = L2CAP_CONF_UNACCEPT;
pi->omtu = L2CAP_DEFAULT_MIN_MTU;
- }
- else {
+ } else {
pi->omtu = mtu;
pi->conf_state |= L2CAP_CONF_MTU_DONE;
}
@@ -7275,6 +7283,7 @@
struct sk_buff *skb_rsp;
struct l2cap_hdr *lh;
int dir;
+ struct work_struct *open_worker;
u8 err_rsp[] = {L2CAP_ATT_ERROR, 0x00, 0x00, 0x00,
L2CAP_ATT_NOT_SUPPORTED};
@@ -7310,8 +7319,18 @@
BT_DBG("sk %p, len %d", sk, skb->len);
- if (sk->sk_state != BT_BOUND && sk->sk_state != BT_CONNECTED)
- goto drop;
+ if (sk->sk_state != BT_BOUND && sk->sk_state != BT_CONNECTED) {
+ att_chn_params.cid = cid;
+ att_chn_params.conn = conn;
+ att_chn_params.dir = dir;
+ att_chn_params.skb = skb;
+ open_worker = kzalloc(sizeof(*open_worker), GFP_ATOMIC);
+ if (!open_worker)
+ BT_ERR("Out of memory");
+ INIT_WORK(open_worker, l2cap_queue_acl_data);
+ schedule_work(open_worker);
+ goto done;
+ }
if (l2cap_pi(sk)->imtu < skb->len)
goto drop;
@@ -7787,6 +7806,80 @@
return 0;
}
+static void l2cap_queue_acl_data(struct work_struct *worker)
+{
+ struct sock *sk = NULL;
+ int attempts = 0;
+ struct sk_buff *skb_rsp;
+ struct l2cap_hdr *lh;
+ u8 err_rsp[] = {L2CAP_ATT_ERROR, 0x00, 0x00, 0x00,
+ L2CAP_ATT_NOT_SUPPORTED};
+
+ for (attempts = 0; attempts < 40; attempts++) {
+ msleep(50);
+ if (!att_chn_params.conn) {
+ BT_DBG("att_chn_params.conn is NULL");
+ return;
+ }
+ sk = l2cap_find_sock_by_fixed_cid_and_dir
+ (att_chn_params.cid,
+ att_chn_params.conn->src,
+ att_chn_params.conn->dst,
+ att_chn_params.dir);
+ bh_lock_sock(sk);
+ if (sk->sk_state == BT_CONNECTED) {
+ sock_queue_rcv_skb(sk, att_chn_params.skb);
+ if (sk)
+ bh_unlock_sock(sk);
+ return;
+ }
+ bh_unlock_sock(sk);
+ }
+ bh_lock_sock(sk);
+
+ if (att_chn_params.skb->data[0] != L2CAP_ATT_INDICATE)
+ goto not_indicate;
+
+ /* If this is an incoming Indication, we are required to confirm */
+ skb_rsp = bt_skb_alloc(sizeof(u8) + L2CAP_HDR_SIZE, GFP_ATOMIC);
+ if (!skb_rsp)
+ goto free_skb;
+
+ lh = (struct l2cap_hdr *) skb_put(skb_rsp, L2CAP_HDR_SIZE);
+ lh->len = cpu_to_le16(sizeof(u8));
+ lh->cid = cpu_to_le16(L2CAP_CID_LE_DATA);
+ err_rsp[0] = L2CAP_ATT_CONFIRM;
+ memcpy(skb_put(skb_rsp, sizeof(u8)), err_rsp, sizeof(u8));
+ hci_send_acl(att_chn_params.conn->hcon, NULL, skb_rsp, 0);
+ goto free_skb;
+
+not_indicate:
+ if (att_chn_params.skb->data[0] & L2CAP_ATT_RESPONSE_BIT ||
+ att_chn_params.skb->data[0] == L2CAP_ATT_CONFIRM)
+ goto free_skb;
+
+ /* If this is an incoming PDU that requires a response, respond with
+ * a generic error so remote device doesn't hang */
+
+ skb_rsp = bt_skb_alloc(sizeof(err_rsp) + L2CAP_HDR_SIZE, GFP_ATOMIC);
+ if (!skb_rsp)
+ goto free_skb;
+
+ lh = (struct l2cap_hdr *) skb_put(skb_rsp, L2CAP_HDR_SIZE);
+ lh->len = cpu_to_le16(sizeof(err_rsp));
+ lh->cid = cpu_to_le16(L2CAP_CID_LE_DATA);
+ err_rsp[1] = att_chn_params.skb->data[0];
+ memcpy(skb_put(skb_rsp, sizeof(err_rsp)), err_rsp, sizeof(err_rsp));
+ hci_send_acl(att_chn_params.conn->hcon, NULL, skb_rsp, 0);
+
+free_skb:
+ kfree_skb(att_chn_params.skb);
+
+ if (sk)
+ bh_unlock_sock(sk);
+
+}
+
static int l2cap_debugfs_open(struct inode *inode, struct file *file)
{
return single_open(file, l2cap_debugfs_show, inode->i_private);
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 493801a..23526f3 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -390,12 +390,17 @@
goto failed;
}
+ hci_dev_unlock_bh(hdev);
+
if (cp->val)
queue_work(hdev->workqueue, &hdev->power_on);
else
queue_work(hdev->workqueue, &hdev->power_off);
err = 0;
+ hci_dev_put(hdev);
+
+ return err;
failed:
hci_dev_unlock_bh(hdev);
diff --git a/net/bluetooth/smp.c b/net/bluetooth/smp.c
index 276ff71..56b2cfa 100644
--- a/net/bluetooth/smp.c
+++ b/net/bluetooth/smp.c
@@ -756,8 +756,7 @@
hcon->smp_conn = conn;
hcon->pending_sec_level = sec_level;
-
- if ((hcon->link_mode & HCI_LM_MASTER) && !hcon->sec_req) {
+ if (hcon->link_mode & HCI_LM_MASTER) {
struct link_key *key;
key = hci_find_link_key_type(hcon->hdev, conn->dst,
diff --git a/scripts/build-all.py b/scripts/build-all.py
index 296d9ad..c59ffae 100755
--- a/scripts/build-all.py
+++ b/scripts/build-all.py
@@ -35,13 +35,14 @@
import subprocess
import os
import os.path
+import re
import shutil
import sys
version = 'build-all.py, version 0.01'
build_dir = '../all-kernels'
-make_command = ["vmlinux", "modules"]
+make_command = ["vmlinux", "modules", "dtbs"]
make_env = os.environ
make_env.update({
'ARCH': 'arm',
@@ -83,12 +84,15 @@
def scan_configs():
"""Get the full list of defconfigs appropriate for this tree."""
names = {}
- for n in glob.glob('arch/arm/configs/[fm]sm[0-9-]*_defconfig'):
- names[os.path.basename(n)[:-10]] = n
- for n in glob.glob('arch/arm/configs/qsd*_defconfig'):
- names[os.path.basename(n)[:-10]] = n
- for n in glob.glob('arch/arm/configs/apq*_defconfig'):
- names[os.path.basename(n)[:-10]] = n
+ arch_pats = (
+ r'[fm]sm[0-9]*_defconfig',
+ r'apq*_defconfig',
+ r'qsd*_defconfig',
+ r'omap2*_defconfig',
+ )
+ for p in arch_pats:
+ for n in glob.glob('arch/arm/configs/' + p):
+ names[os.path.basename(n)[:-10]] = n
return names
class Builder:
@@ -142,23 +146,41 @@
savedefconfig = '%s/defconfig' % dest_dir
shutil.copyfile(defconfig, dotconfig)
+ staging_dir = 'install_staging'
+ modi_dir = '%s' % staging_dir
+ hdri_dir = '%s/usr' % staging_dir
+ shutil.rmtree(os.path.join(dest_dir, staging_dir), ignore_errors=True)
+
devnull = open('/dev/null', 'r')
subprocess.check_call(['make', 'O=%s' % dest_dir,
'%s_defconfig' % target], env=make_env, stdin=devnull)
devnull.close()
if not all_options.updateconfigs:
- build = Builder(log_name)
-
- result = build.run(['make', 'O=%s' % dest_dir] + make_command)
-
- if result != 0:
- if all_options.keep_going:
- failed_targets.append(target)
- fail_or_error = error
+ # Build targets can be dependent upon the completion of previous
+ # build targets, so build them one at a time.
+ cmd_line = ['make',
+ 'INSTALL_HDR_PATH=%s' % hdri_dir,
+ 'INSTALL_MOD_PATH=%s' % modi_dir,
+ 'O=%s' % dest_dir]
+ build_targets = []
+ for c in make_command:
+ if re.match(r'^-{1,2}\w', c):
+ cmd_line.append(c)
else:
- fail_or_error = fail
- fail_or_error("Failed to build %s, see %s" % (target, build.logname))
+ build_targets.append(c)
+ for t in build_targets:
+ build = Builder(log_name)
+
+ result = build.run(cmd_line + [t])
+ if result != 0:
+ if all_options.keep_going:
+ failed_targets.append(target)
+ fail_or_error = error
+ else:
+ fail_or_error = fail
+ fail_or_error("Failed to build %s, see %s" %
+ (target, build.logname))
# Copy the defconfig back.
if all_options.configs or all_options.updateconfigs:
diff --git a/sound/soc/codecs/wcd9304.c b/sound/soc/codecs/wcd9304.c
index fd9d825..3fc3f32 100644
--- a/sound/soc/codecs/wcd9304.c
+++ b/sound/soc/codecs/wcd9304.c
@@ -1212,6 +1212,42 @@
return 0;
}
+static void sitar_enable_classg(struct snd_soc_codec *codec,
+ bool enable)
+{
+
+ if (enable) {
+ snd_soc_update_bits(codec,
+ SITAR_A_CDC_CLK_OTHR_RESET_CTL, 0x10, 0x00);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x07, 0x00);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x08, 0x00);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x10, 0x00);
+
+ } else {
+ snd_soc_update_bits(codec,
+ SITAR_A_CDC_CLK_OTHR_RESET_CTL, 0x10, 0x10);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x07, 0x03);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x08, 0x08);
+ snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x10, 0x10);
+ }
+}
+
+static bool sitar_is_hph_pa_on(struct snd_soc_codec *codec)
+{
+ u8 hph_reg_val = 0;
+ hph_reg_val = snd_soc_read(codec, SITAR_A_RX_HPH_CNP_EN);
+
+ return (hph_reg_val & 0x30) ? true : false;
+}
+
+static bool sitar_is_line_pa_on(struct snd_soc_codec *codec)
+{
+ u8 line_reg_val = 0;
+ line_reg_val = snd_soc_read(codec, SITAR_A_RX_LINE_CNP_EN);
+
+ return (line_reg_val & 0x03) ? true : false;
+}
+
static int sitar_codec_enable_lineout(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
@@ -1235,6 +1271,15 @@
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ if (sitar_is_hph_pa_on(codec)) {
+ snd_soc_update_bits(codec, SITAR_A_CDC_RX1_B6_CTL,
+ 0x20, 0x00);
+ sitar_enable_classg(codec, false);
+ } else {
+ snd_soc_update_bits(codec, SITAR_A_CDC_RX1_B6_CTL,
+ 0x20, 0x20);
+ sitar_enable_classg(codec, true);
+ }
snd_soc_update_bits(codec, lineout_gain_reg, 0x10, 0x10);
break;
case SND_SOC_DAPM_POST_PMU:
@@ -1243,6 +1288,11 @@
usleep_range(32000, 32000);
break;
case SND_SOC_DAPM_POST_PMD:
+ if (sitar_is_hph_pa_on(codec))
+ sitar_enable_classg(codec, true);
+ else
+ sitar_enable_classg(codec, false);
+
snd_soc_update_bits(codec, lineout_gain_reg, 0x10, 0x00);
break;
}
@@ -1585,14 +1635,6 @@
return rc;
}
-static bool sitar_is_hph_pa_on(struct snd_soc_codec *codec)
-{
- u8 hph_reg_val = 0;
- hph_reg_val = snd_soc_read(codec, SITAR_A_RX_HPH_CNP_EN);
-
- return (hph_reg_val & 0x30) ? true : false;
-}
-
static bool sitar_is_hph_dac_on(struct snd_soc_codec *codec, int left)
{
u8 hph_reg_val = 0;
@@ -1947,6 +1989,11 @@
SITAR_RELEASE_LOCK(sitar->codec_resource_lock);
}
+ if (sitar_is_line_pa_on(codec))
+ sitar_enable_classg(codec, false);
+ else
+ sitar_enable_classg(codec, true);
+
break;
case SND_SOC_DAPM_POST_PMD:
@@ -1979,6 +2026,11 @@
w->name);
usleep_range(10000, 10000);
+ if (sitar_is_line_pa_on(codec))
+ sitar_enable_classg(codec, true);
+ else
+ sitar_enable_classg(codec, false);
+
break;
}
return 0;
@@ -2033,24 +2085,21 @@
pr_debug("%s %d\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
- snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_RESET_CTL, 0x10,
- 0x00);
snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_CTL, 0x01,
0x01);
snd_soc_update_bits(codec, SITAR_A_CDC_CLSG_CTL, 0x08, 0x08);
usleep_range(200, 200);
- snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x10, 0x00);
break;
case SND_SOC_DAPM_PRE_PMD:
- snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_RESET_CTL, 0x10,
- 0x10);
- usleep_range(20, 20);
- snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x08, 0x08);
- snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x10, 0x10);
snd_soc_update_bits(codec, SITAR_A_CDC_CLSG_CTL, 0x08, 0x00);
+ /*
+ * This delay is for the class G controller to settle down
+ * after turn OFF. The delay is as per the hardware spec for
+ * the codec
+ */
+ usleep_range(20, 20);
snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_CTL, 0x01,
0x00);
- snd_soc_update_bits(codec, SITAR_A_CP_STATIC, 0x08, 0x00);
break;
}
return 0;