Merge "msm: audio: qdsp6v2: Add support for dual mono setting for multi aac." into msm-3.0
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 414f8da..2cd81c8 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -120,7 +120,8 @@
asflags-y := -Wa,-march=all
# Supply kernel BSS size to the decompressor via a linker symbol.
-KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
+SIZEBIN := $(if $(shell which $(CROSS_COMPILE)size),$(CROSS_COMPILE)size,size)
+KBSS_SZ = $(shell $(SIZEBIN) $(obj)/../../../../vmlinux | awk 'END{print $$3}')
LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
diff --git a/arch/arm/configs/apq8064_defconfig b/arch/arm/configs/apq8064_defconfig
index d04e6a4..2f3d37a 100644
--- a/arch/arm/configs/apq8064_defconfig
+++ b/arch/arm/configs/apq8064_defconfig
@@ -214,3 +214,11 @@
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y
+CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_MSM_SMD_DEBUG=y
+CONFIG_MSM_SMD_TTY=y
+CONFIG_MSM_N_WAY_SMD=y
+CONFIG_MSM_N_WAY_SMSM=y
+CONFIG_MSM_SMD_LOGGING=y
diff --git a/arch/arm/configs/fsm9xxx-perf_defconfig b/arch/arm/configs/fsm9xxx-perf_defconfig
index d5a0b3f..50145f9 100644
--- a/arch/arm/configs/fsm9xxx-perf_defconfig
+++ b/arch/arm/configs/fsm9xxx-perf_defconfig
@@ -132,6 +132,7 @@
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MSM_ADC=y
+CONFIG_PMIC8058=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_PM8058_XO=y
# CONFIG_USB_SUPPORT is not set
@@ -149,6 +150,7 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/fsm9xxx_defconfig b/arch/arm/configs/fsm9xxx_defconfig
index dddbdfe..4019a4f 100644
--- a/arch/arm/configs/fsm9xxx_defconfig
+++ b/arch/arm/configs/fsm9xxx_defconfig
@@ -130,6 +130,7 @@
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
CONFIG_SENSORS_MSM_ADC=y
+CONFIG_PMIC8058=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_PM8058_XO=y
# CONFIG_USB_SUPPORT is not set
@@ -147,6 +148,7 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/msm7627-perf_defconfig b/arch/arm/configs/msm7627-perf_defconfig
index b05d52a..1cc4b97 100644
--- a/arch/arm/configs/msm7627-perf_defconfig
+++ b/arch/arm/configs/msm7627-perf_defconfig
@@ -194,6 +194,7 @@
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_MSM_HS=y
+CONFIG_DIAG_CHAR=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -247,6 +248,9 @@
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MSM_72K=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_RMNET_SMD_CTL_CHANNEL="DATA12_CNTL"
+CONFIG_RMNET_SMD_DATA_CHANNEL="DATA12"
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
CONFIG_MMC_UNSAFE_RESUME=y
diff --git a/arch/arm/configs/msm7627_defconfig b/arch/arm/configs/msm7627_defconfig
index 15aec4b..6f0cb31 100644
--- a/arch/arm/configs/msm7627_defconfig
+++ b/arch/arm/configs/msm7627_defconfig
@@ -194,6 +194,7 @@
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_MSM_HS=y
+CONFIG_DIAG_CHAR=y
# CONFIG_HW_RANDOM is not set
CONFIG_DCC_TTY=y
CONFIG_I2C=y
@@ -245,6 +246,9 @@
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MSM_72K=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_RMNET_SMD_CTL_CHANNEL="DATA12_CNTL"
+CONFIG_RMNET_SMD_DATA_CHANNEL="DATA12"
CONFIG_MMC=y
CONFIG_MMC_PERF_PROFILING=y
CONFIG_MMC_UNSAFE_RESUME=y
diff --git a/arch/arm/configs/msm7627a-perf_defconfig b/arch/arm/configs/msm7627a-perf_defconfig
index 8be0165..985b8f2 100644
--- a/arch/arm/configs/msm7627a-perf_defconfig
+++ b/arch/arm/configs/msm7627a-perf_defconfig
@@ -231,7 +231,7 @@
CONFIG_FB_MSM_TRIPLE_BUFFER=y
CONFIG_FB_MSM_MDP30=y
CONFIG_FB_MSM_MDP303=y
-CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL=y
+CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm7627a_defconfig b/arch/arm/configs/msm7627a_defconfig
index ed4fd41..9254abb 100644
--- a/arch/arm/configs/msm7627a_defconfig
+++ b/arch/arm/configs/msm7627a_defconfig
@@ -229,7 +229,7 @@
CONFIG_FB_MSM_TRIPLE_BUFFER=y
CONFIG_FB_MSM_MDP30=y
CONFIG_FB_MSM_MDP303=y
-CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL=y
+CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/configs/msm7630-perf_defconfig b/arch/arm/configs/msm7630-perf_defconfig
index 9f31996..cc86af8 100644
--- a/arch/arm/configs/msm7630-perf_defconfig
+++ b/arch/arm/configs/msm7630-perf_defconfig
@@ -171,6 +171,7 @@
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_IBS=y
+CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
# CONFIG_RFKILL_PM is not set
@@ -243,6 +244,7 @@
CONFIG_SENSORS_MSM_ADC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_MSM_POPMEM=y
+CONFIG_PMIC8058=y
CONFIG_MARIMBA_CORE=y
CONFIG_MARIMBA_CODEC=y
CONFIG_TIMPANI_CODEC=y
@@ -334,6 +336,7 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/msm7630_defconfig b/arch/arm/configs/msm7630_defconfig
index b7a7b34..9645211 100644
--- a/arch/arm/configs/msm7630_defconfig
+++ b/arch/arm/configs/msm7630_defconfig
@@ -170,6 +170,7 @@
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_IBS=y
+CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
# CONFIG_RFKILL_PM is not set
@@ -242,6 +243,7 @@
CONFIG_SENSORS_MSM_ADC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_MSM_POPMEM=y
+CONFIG_PMIC8058=y
CONFIG_MARIMBA_CORE=y
CONFIG_MARIMBA_CODEC=y
CONFIG_TIMPANI_CODEC=y
@@ -318,6 +320,7 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/msm8660-perf_defconfig b/arch/arm/configs/msm8660-perf_defconfig
index 5577fd8..3315171 100644
--- a/arch/arm/configs/msm8660-perf_defconfig
+++ b/arch/arm/configs/msm8660-perf_defconfig
@@ -210,6 +210,7 @@
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_IBS=y
+CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
CONFIG_BLK_DEV_LOOP=y
@@ -299,6 +300,7 @@
CONFIG_THERMAL_PM8901=y
CONFIG_THERMAL_PM8058=y
CONFIG_THERMAL_TSENS=y
+CONFIG_PMIC8058=y
CONFIG_MARIMBA_CORE=y
CONFIG_TIMPANI_CODEC=y
CONFIG_MEDIA_SUPPORT=y
@@ -390,6 +392,7 @@
CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/msm8660_defconfig b/arch/arm/configs/msm8660_defconfig
index 2dc6b36..698855a 100644
--- a/arch/arm/configs/msm8660_defconfig
+++ b/arch/arm/configs/msm8660_defconfig
@@ -201,6 +201,7 @@
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_IBS=y
+CONFIG_MSM_BT_POWER=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_RFKILL=y
CONFIG_BLK_DEV_LOOP=y
@@ -290,6 +291,7 @@
CONFIG_THERMAL_PM8901=y
CONFIG_THERMAL_PM8058=y
CONFIG_THERMAL_TSENS=y
+CONFIG_PMIC8058=y
CONFIG_MARIMBA_CORE=y
CONFIG_TIMPANI_CODEC=y
CONFIG_MEDIA_SUPPORT=y
@@ -379,6 +381,7 @@
CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_SSBI=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index ddbe87c..bf15477 100755
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -192,6 +192,7 @@
CONFIG_BT_HIDP=y
CONFIG_BT_HCISMD=m
CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_MISC_DEVICES=y
@@ -219,6 +220,8 @@
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WCNSS_CORE=m
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=n
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_MODE_SLIP6=y
@@ -322,6 +325,7 @@
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_QCOM_DUN_BRIDGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_CI13XXX_MSM=y
diff --git a/arch/arm/configs/msm9615_defconfig b/arch/arm/configs/msm9615_defconfig
index 52a4d20..72908f9 100644
--- a/arch/arm/configs/msm9615_defconfig
+++ b/arch/arm/configs/msm9615_defconfig
@@ -20,6 +20,7 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
+CONFIG_PANIC_TIMEOUT=5
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_PERF_EVENTS is not set
@@ -39,8 +40,11 @@
# CONFIG_MSM_PROC_COMM is not set
CONFIG_MSM_SMD=y
CONFIG_MSM_SMD_PKG4=y
+CONFIG_MSM_IPC_ROUTER=y
+CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG=y
+CONFIG_MSM_DLOAD_MODE=y
CONFIG_SWP_EMULATE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
@@ -80,6 +84,7 @@
# CONFIG_SERIAL_MSM_CLOCK_CONTROL is not set
CONFIG_SERIAL_MSM_HSL=y
CONFIG_SERIAL_MSM_HSL_CONSOLE=y
+CONFIG_DIAG_CHAR=y
CONFIG_HVC_DCC=y
CONFIG_HW_RANDOM=y
CONFIG_DCC_TTY=y
@@ -99,7 +104,26 @@
# CONFIG_MFD_PM8XXX_PWM is not set
CONFIG_REGULATOR=y
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CI13XXX_MSM=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_SWITCH=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_WIRELESS is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_PERF_PROFILING=y
@@ -132,7 +156,7 @@
# CONFIG_MMC_MSM_SDC3_SUPPORT is not set
# CONFIG_MMC_MSM_SDC4_SUPPORT is not set
# CONFIG_MMC_MSM_SDC5_SUPPORT is not set
-# CONFIG_MMC_MSM_SPS_SUPPORT is not set
+CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_MSM_SSBI=y
CONFIG_SPS=y
CONFIG_SPS_SUPPORT_BAMDMA=y
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad180..2635c8b 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
#include <linux/threads.h>
#include <asm/irq.h>
-#define NR_IPI 5
+#define NR_IPI 6
typedef struct {
unsigned int __softirq_pending;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index a9d1a5c..5478f55 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -48,6 +48,7 @@
struct secondary_data secondary_data;
enum ipi_msg_type {
+ IPI_CPU_START = 1,
IPI_TIMER = 2,
IPI_RESCHEDULE,
IPI_CALL_FUNC,
@@ -399,7 +400,8 @@
}
static const char *ipi_types[NR_IPI] = {
-#define S(x,s) [x - IPI_TIMER] = s
+#define S(x,s) [x - IPI_CPU_START] = s
+ S(IPI_CPU_START, "CPU start interrupts"),
S(IPI_TIMER, "Timer broadcast interrupts"),
S(IPI_RESCHEDULE, "Rescheduling interrupts"),
S(IPI_CALL_FUNC, "Function call interrupts"),
@@ -563,10 +565,13 @@
unsigned int cpu = smp_processor_id();
struct pt_regs *old_regs = set_irq_regs(regs);
- if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
- __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
+ if (ipinr >= IPI_CPU_START && ipinr < IPI_CPU_START + NR_IPI)
+ __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_CPU_START]);
switch (ipinr) {
+ case IPI_CPU_START:
+ /* Wake up from WFI/WFE using SGI */
+ break;
case IPI_TIMER:
ipi_timer();
break;
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 2acc8e0..ad07bbb 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -15,6 +15,7 @@
select MSM_VIC
select CPU_V6
select MSM_REMOTE_SPINLOCK_SWP
+ select MULTI_IRQ_HANDLER
config ARCH_MSM7X27
bool "MSM7x27"
@@ -27,6 +28,7 @@
select MSM_REMOTE_SPINLOCK_SWP if MSM_SOC_REV_NONE
select MSM_GPIOMUX
select REGULATOR
+ select MULTI_IRQ_HANDLER
config ARCH_MSM7X30
bool "MSM7x30"
@@ -48,6 +50,7 @@
select MSM_SPM_V1
select REGULATOR
select MSM_PROC_COMM_REGULATOR
+ select MULTI_IRQ_HANDLER
config ARCH_QSD8X50
bool "QSD8X50"
@@ -172,6 +175,7 @@
select MSM_GPIOMUX
select MSM_RPM
select MSM_SPM_V2
+ select MSM_NATIVE_RESTART
endmenu
choice
@@ -228,6 +232,7 @@
bool
select MSM_DALRPC
select MSM_PROC_COMM_REGULATOR
+ select MULTI_IRQ_HANDLER
config MSM_VIC
bool
@@ -944,7 +949,7 @@
via muxing than BAM could without muxing.
config MSM_N_WAY_SMD
- depends on (MSM_SMD && (ARCH_MSM_SCORPION || ARCH_MSM8960 || ARCH_MSM7X27 || ARCH_MSM7X25 || ARCH_MSM9615))
+ depends on (MSM_SMD && !(ARCH_MSM7X01A))
default y
bool "MSM N-WAY SMD support"
help
@@ -952,7 +957,7 @@
normal APPS-MODEM SMD communication.
config MSM_N_WAY_SMSM
- depends on (MSM_SMD && (ARCH_MSM_SCORPION || ARCH_MSM8960 || ARCH_MSM7X27 || ARCH_MSM7X25 || ARCH_MSM9615))
+ depends on (MSM_SMD && !(ARCH_MSM7X01A))
default y
bool "MSM N-WAY SMSM support"
help
@@ -1533,7 +1538,7 @@
config MSM_IOMMU
bool "MSM IOMMU Support"
- depends on ARCH_MSM8X60 || ARCH_MSM8960
+ depends on ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_APQ8064
select IOMMU_API
default n
help
@@ -1597,7 +1602,7 @@
config MSM_DLOAD_MODE
bool "Enable download mode on crashes"
- depends on ARCH_MSM8X60 || ARCH_MSM8960
+ depends on ARCH_MSM8X60 || ARCH_MSM8960 || ARCH_MSM9615
default n
help
This makes the SoC enter download mode when it resets
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index e81bdcd..025f1c7 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -75,6 +75,7 @@
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o remote_spinlock.o
obj-y += socinfo.o
ifndef CONFIG_ARCH_MSM9615
+ifndef CONFIG_ARCH_APQ8064
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
obj-$(CONFIG_MSM_SMD) += pmic.o
@@ -82,6 +83,7 @@
endif
endif
endif
+endif
ifndef CONFIG_ARCH_MSM8960
ifndef CONFIG_ARCH_MSM8X60
ifndef CONFIG_ARCH_APQ8064
@@ -158,7 +160,7 @@
obj-$(CONFIG_ARCH_MSM8X60) += devices-msm8x60.o clock-local.o clock-8x60.o acpuclock-8x60.o
obj-$(CONFIG_ARCH_MSM8X60) += clock-rpm.o
obj-$(CONFIG_ARCH_MSM8X60) += saw-regulator.o
-obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator.o
+obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator.o rpm-regulator-8660.o
obj-$(CONFIG_ARCH_MSM8X60) += footswitch-8x60.o
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
@@ -202,6 +204,7 @@
obj-$(CONFIG_MACH_MSM7X27A_RUMI3) += board-msm7x27a.o
obj-$(CONFIG_MACH_MSM7X27A_SURF) += board-msm7x27a.o
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o
+obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
@@ -209,7 +212,8 @@
obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o
obj-$(CONFIG_ARCH_MSM8960) += footswitch-8x60.o
obj-$(CONFIG_ARCH_MSM8960) += acpuclock-8960.o
-obj-$(CONFIG_ARCH_MSM8960) += saw-regulator.o rpm-regulator-8960.o memory_topology.o
+obj-$(CONFIG_ARCH_MSM8960) += memory_topology.o
+obj-$(CONFIG_ARCH_MSM8960) += saw-regulator.o rpm-regulator.o rpm-regulator-8960.o
obj-$(CONFIG_MACH_MSM8960_SIM) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_RUMI3) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_CDP) += board-msm8960.o devices-8960.o board-msm8960-regulator.o
@@ -219,6 +223,7 @@
obj-$(CONFIG_ARCH_APQ8064) += board-apq8064.o devices-8064.o board-apq8064-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += board-9615.o devices-9615.o board-9615-regulator.o
obj-$(CONFIG_ARCH_MSM9615) += clock-local.o clock-9615.o acpuclock-9615.o clock-rpm.o
+obj-$(CONFIG_ARCH_MSM9615) += rpm-regulator.o rpm-regulator-9615.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
index 1d0e1a8..cfc7dd0 100644
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -66,11 +66,14 @@
#define STBY_KHZ 1
#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 1050000
+#define HFPLL_LOW_VDD 945000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
+/* PTE EFUSE register. */
+#define QFPROM_PTE_EFUSE_ADDR (MSM_QFPROM_BASE + 0x00C0)
+
enum scalables {
CPU0 = 0,
CPU1,
@@ -276,36 +279,21 @@
[9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 3 },
[10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 3 },
[11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 3 },
- [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 3 },
- [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 4 },
- [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 4 },
- [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 4 },
- [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 4 },
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 5 },
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 5 },
- [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 5 },
- [20] = { { 1404000, HFPLL, 1, 0, 0x34 }, 1150000, 1150000, 5 },
- [21] = { { 1458000, HFPLL, 1, 0, 0x36 }, 1150000, 1150000, 5 },
- [22] = { { 1512000, HFPLL, 1, 0, 0x38 }, 1150000, 1150000, 5 },
- [23] = { { 1566000, HFPLL, 1, 0, 0x3A }, 1150000, 1150000, 5 },
- [24] = { { 1620000, HFPLL, 1, 0, 0x3C }, 1150000, 1150000, 5 },
- [25] = { { 1674000, HFPLL, 1, 0, 0x3E }, 1150000, 1150000, 5 },
};
-/* TODO: Update core voltages when data is available. */
static struct acpu_level acpu_freq_tbl_8960[] = {
- { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 1050000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 1050000 },
- { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 1050000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 1050000 },
- { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1050000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1050000 },
- { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1050000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1050000 },
- { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(13), 1150000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(13), 1150000 },
- { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(13), 1150000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(13), 1150000 },
+ { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 950000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 962500 },
+ { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 962500 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 987500 },
+ { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1000000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 1050000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1087500 },
+ { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1125000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1137500 },
{ 0, { 0 } }
};
@@ -413,6 +401,10 @@
/* Wait for switch to complete. */
mb();
udelay(1);
+
+ /* Re-enable secondary source clock gating. */
+ regval &= ~SECCLKAGD;
+ set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
}
/* Enable an already-configured HFPLL. */
@@ -990,6 +982,30 @@
/* Select frequency tables. */
if (cpu_is_msm8960()) {
+ uint32_t pte_efuse, pvs;
+
+ pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR);
+ pvs = (pte_efuse >> 10) & 0x7;
+ if (pvs == 0x7)
+ pvs = (pte_efuse >> 13) & 0x7;
+
+ switch (pvs) {
+ case 0x0:
+ case 0x7:
+ pr_info("ACPU PVS: Slow\n");
+ break;
+ case 0x1:
+ pr_info("ACPU PVS: Nominal\n");
+ break;
+ case 0x3:
+ pr_info("ACPU PVS: Fast\n");
+ break;
+ default:
+ pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n");
+ break;
+ }
+
+ /* TODO: Select tables based on PVS data. */
scalable = scalable_8960;
acpu_freq_tbl = acpu_freq_tbl_8960;
l2_freq_tbl = l2_freq_tbl_8960;
diff --git a/arch/arm/mach-msm/acpuclock-9615.c b/arch/arm/mach-msm/acpuclock-9615.c
index e12caeb..924a46a 100644
--- a/arch/arm/mach-msm/acpuclock-9615.c
+++ b/arch/arm/mach-msm/acpuclock-9615.c
@@ -122,7 +122,7 @@
goto out;
}
- pr_info("Switching from CPU rate %u KHz -> %u KHz\n",
+ pr_debug("Switching from CPU rate %u KHz -> %u KHz\n",
strt_s->khz, tgt_s->khz);
/* Switch CPU speed. */
@@ -131,7 +131,7 @@
clk_disable(clocks[strt_s->src].clk);
drv_state.current_speed = tgt_s;
- pr_info("CPU speed change complete\n");
+ pr_debug("CPU speed change complete\n");
out:
if (reason == SETRATE_CPUFREQ)
diff --git a/arch/arm/mach-msm/bam_dmux.c b/arch/arm/mach-msm/bam_dmux.c
index 5ed4456..304a687 100644
--- a/arch/arm/mach-msm/bam_dmux.c
+++ b/arch/arm/mach-msm/bam_dmux.c
@@ -24,6 +24,7 @@
#include <linux/sched.h>
#include <linux/skbuff.h>
#include <linux/debugfs.h>
+#include <linux/clk.h>
#include <mach/sps.h>
#include <mach/bam_dmux.h>
@@ -119,6 +120,7 @@
#define BUFFER_SIZE 2048
#define NUM_BUFFERS 32
static struct sps_bam_props a2_props;
+static u32 a2_device_handle;
static struct sps_pipe *bam_tx_pipe;
static struct sps_pipe *bam_rx_pipe;
static struct sps_connect tx_connection;
@@ -155,6 +157,26 @@
static struct workqueue_struct *bam_mux_rx_workqueue;
static struct workqueue_struct *bam_mux_tx_workqueue;
+/* A2 power collaspe */
+#define UL_TIMEOUT_DELAY 1000 /* in ms */
+static void toggle_apps_ack(void);
+static void reconnect_to_bam(void);
+static void disconnect_to_bam(void);
+static void ul_wakeup(void);
+static void ul_timeout(struct work_struct *work);
+static void vote_dfab(void);
+static void unvote_dfab(void);
+
+static int bam_is_connected;
+static DEFINE_MUTEX(wakeup_lock);
+static struct completion ul_wakeup_ack_completion;
+static struct completion bam_connection_completion;
+static struct delayed_work ul_timeout_work;
+static int ul_packet_written;
+static struct clk *dfab_clk;
+static DEFINE_RWLOCK(ul_wakeup_lock);
+/* End A2 power collaspe */
+
#define bam_ch_is_open(x) \
(bam_ch[(x)].status == (BAM_CH_LOCAL_OPEN | BAM_CH_REMOTE_OPEN))
@@ -316,6 +338,7 @@
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
mutex_unlock(&bam_mux_lock);
+ ul_packet_written = 1;
return rc;
}
@@ -365,6 +388,10 @@
}
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
/* if skb do not have any tailroom for padding,
copy the skb into a new expanded skb */
if ((skb->len & 0x3) && (skb_tailroom(skb) < (4 - (skb->len & 0x3)))) {
@@ -421,6 +448,8 @@
INIT_WORK(&pkt->work, bam_mux_write_done);
rc = sps_transfer_one(bam_tx_pipe, dma_address, skb->len,
pkt, SPS_IOVEC_FLAG_INT | SPS_IOVEC_FLAG_EOT);
+ ul_packet_written = 1;
+ read_unlock(&ul_wakeup_lock);
return rc;
}
@@ -464,6 +493,10 @@
bam_ch[id].status |= BAM_CH_LOCAL_OPEN;
spin_unlock_irqrestore(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
hdr->magic_num = BAM_MUX_HDR_MAGIC_NO;
hdr->cmd = BAM_MUX_HDR_CMD_OPEN;
hdr->reserved = 0;
@@ -472,6 +505,7 @@
hdr->pad_len = 0;
rc = bam_mux_write_cmd((void *)hdr, sizeof(struct bam_mux_hdr));
+ read_unlock(&ul_wakeup_lock);
open_done:
DBG("%s: opened ch %d\n", __func__, id);
@@ -491,6 +525,10 @@
return -ENODEV;
spin_lock_irqsave(&bam_ch[id].lock, flags);
+ read_lock(&ul_wakeup_lock);
+ if (!bam_is_connected)
+ ul_wakeup();
+
bam_ch[id].notify = NULL;
bam_ch[id].priv = NULL;
bam_ch[id].status &= ~BAM_CH_LOCAL_OPEN;
@@ -509,6 +547,7 @@
hdr->pad_len = 0;
rc = bam_mux_write_cmd((void *)hdr, sizeof(struct bam_mux_hdr));
+ read_unlock(&ul_wakeup_lock);
DBG("%s: closed ch %d\n", __func__, id);
return rc;
@@ -708,6 +747,101 @@
#endif
+static void ul_timeout(struct work_struct *work)
+{
+ write_lock(&ul_wakeup_lock);
+ if (ul_packet_written) {
+ ul_packet_written = 0;
+ schedule_delayed_work(&ul_timeout_work,
+ msecs_to_jiffies(UL_TIMEOUT_DELAY));
+ } else {
+ smsm_change_state(SMSM_APPS_STATE, SMSM_A2_POWER_CONTROL, 0);
+ bam_is_connected = 0;
+ }
+ write_unlock(&ul_wakeup_lock);
+}
+static void ul_wakeup(void)
+{
+ mutex_lock(&wakeup_lock);
+ if (bam_is_connected) { /* bam got connected before lock grabbed */
+ mutex_unlock(&wakeup_lock);
+ return;
+ }
+ INIT_COMPLETION(ul_wakeup_ack_completion);
+ smsm_change_state(SMSM_APPS_STATE, 0, SMSM_A2_POWER_CONTROL);
+ wait_for_completion_interruptible_timeout(&ul_wakeup_ack_completion,
+ HZ);
+ wait_for_completion_interruptible_timeout(&bam_connection_completion,
+ HZ);
+
+ bam_is_connected = 1;
+ schedule_delayed_work(&ul_timeout_work,
+ msecs_to_jiffies(UL_TIMEOUT_DELAY));
+ mutex_unlock(&wakeup_lock);
+}
+
+static void reconnect_to_bam(void)
+{
+ int i;
+
+ vote_dfab();
+ i = sps_device_reset(a2_device_handle);
+ if (i)
+ pr_err("%s: device reset failed rc = %d\n", __func__, i);
+ i = sps_connect(bam_tx_pipe, &tx_connection);
+ if (i)
+ pr_err("%s: tx connection failed rc = %d\n", __func__, i);
+ i = sps_connect(bam_rx_pipe, &rx_connection);
+ if (i)
+ pr_err("%s: rx connection failed rc = %d\n", __func__, i);
+ i = sps_register_event(bam_tx_pipe, &tx_register_event);
+ if (i)
+ pr_err("%s: tx event reg failed rc = %d\n", __func__, i);
+ i = sps_register_event(bam_rx_pipe, &rx_register_event);
+ if (i)
+ pr_err("%s: rx event reg failed rc = %d\n", __func__, i);
+ for (i = 0; i < NUM_BUFFERS; ++i)
+ queue_rx();
+ toggle_apps_ack();
+ complete_all(&bam_connection_completion);
+}
+
+static void disconnect_to_bam(void)
+{
+ struct list_head *node;
+ struct rx_pkt_info *info;
+
+ INIT_COMPLETION(bam_connection_completion);
+ sps_disconnect(bam_tx_pipe);
+ sps_disconnect(bam_rx_pipe);
+ unvote_dfab();
+ __memzero(rx_desc_mem_buf.base, rx_desc_mem_buf.size);
+ __memzero(tx_desc_mem_buf.base, tx_desc_mem_buf.size);
+ while (!list_empty(&bam_rx_pool)) {
+ node = bam_rx_pool.next;
+ list_del(node);
+ info = container_of(node, struct rx_pkt_info, list_node);
+ dma_unmap_single(NULL, info->dma_address, BUFFER_SIZE,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb_any(info->skb);
+ kfree(info);
+ }
+}
+
+static void vote_dfab(void)
+{
+ int rc;
+
+ rc = clk_enable(dfab_clk);
+ if (rc)
+ pr_err("bam_dmux vote for dfab failed rc = %d\n", rc);
+}
+
+static void unvote_dfab(void)
+{
+ clk_disable(dfab_clk);
+}
+
static void bam_init(void)
{
u32 h;
@@ -716,6 +850,7 @@
void *a2_virt_addr;
int i;
+ vote_dfab();
/* init BAM */
a2_virt_addr = ioremap_nocache(A2_PHYS_BASE, A2_PHYS_SIZE);
if (!a2_virt_addr) {
@@ -735,6 +870,7 @@
pr_err("%s: register bam error %d\n", __func__, ret);
goto register_bam_failed;
}
+ a2_device_handle = h;
bam_tx_pipe = sps_alloc_endpoint();
if (bam_tx_pipe == NULL) {
@@ -836,6 +972,8 @@
bam_mux_initialized = 1;
for (i = 0; i < NUM_BUFFERS; ++i)
queue_rx();
+ toggle_apps_ack();
+ complete_all(&bam_connection_completion);
return;
rx_event_reg_failed:
@@ -860,11 +998,22 @@
return;
}
+static void toggle_apps_ack(void)
+{
+ static unsigned int clear_bit; /* 0 = set the bit, else clear bit */
+ smsm_change_state(SMSM_APPS_STATE,
+ clear_bit & SMSM_A2_POWER_CONTROL_ACK,
+ ~clear_bit & SMSM_A2_POWER_CONTROL_ACK);
+ clear_bit = ~clear_bit;
+}
+
static void bam_dmux_smsm_cb(void *priv, uint32_t old_state, uint32_t new_state)
{
DBG("%s: smsm activity\n", __func__);
- if (bam_mux_initialized)
- pr_err("%s: bam_dmux already initialized\n", __func__);
+ if (bam_mux_initialized && new_state & SMSM_A2_POWER_CONTROL)
+ reconnect_to_bam();
+ else if (bam_mux_initialized && !(new_state & SMSM_A2_POWER_CONTROL))
+ disconnect_to_bam();
else if (new_state & SMSM_A2_POWER_CONTROL)
bam_init();
else
@@ -872,6 +1021,12 @@
}
+static void bam_dmux_smsm_ack_cb(void *priv, uint32_t old_state,
+ uint32_t new_state)
+{
+ complete_all(&ul_wakeup_ack_completion);
+}
+
static int bam_dmux_probe(struct platform_device *pdev)
{
int rc;
@@ -880,6 +1035,16 @@
if (bam_mux_initialized)
return 0;
+ dfab_clk = clk_get(&pdev->dev, "dfab_clk");
+ if (IS_ERR(dfab_clk)) {
+ pr_err("%s: did not get dfab clock\n", __func__);
+ return -EFAULT;
+ }
+
+ rc = clk_set_rate(dfab_clk, 64000000);
+ if (rc)
+ pr_err("%s: unable to set dfab clock rate\n", __func__);
+
bam_mux_rx_workqueue = create_singlethread_workqueue("bam_dmux_rx");
if (!bam_mux_rx_workqueue)
return -ENOMEM;
@@ -904,6 +1069,10 @@
}
}
+ init_completion(&ul_wakeup_ack_completion);
+ init_completion(&bam_connection_completion);
+ INIT_DELAYED_WORK(&ul_timeout_work, ul_timeout);
+
rc = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_A2_POWER_CONTROL,
bam_dmux_smsm_cb, NULL);
@@ -914,6 +1083,22 @@
return -ENOMEM;
}
+ rc = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_A2_POWER_CONTROL_ACK,
+ bam_dmux_smsm_ack_cb, NULL);
+
+ if (rc) {
+ destroy_workqueue(bam_mux_rx_workqueue);
+ destroy_workqueue(bam_mux_tx_workqueue);
+ smsm_state_cb_deregister(SMSM_MODEM_STATE,
+ SMSM_A2_POWER_CONTROL,
+ bam_dmux_smsm_cb, NULL);
+ pr_err("%s: smsm ack cb register failed, rc: %d\n", __func__,
+ rc);
+ for (rc = 0; rc < BAM_DMUX_NUM_CHANNELS; ++rc)
+ platform_device_put(bam_ch[rc].pdev);
+ return -ENOMEM;
+ }
+
return 0;
}
diff --git a/arch/arm/mach-msm/board-9615-regulator.c b/arch/arm/mach-msm/board-9615-regulator.c
index 2cef2bb..d7d630d 100644
--- a/arch/arm/mach-msm/board-9615-regulator.c
+++ b/arch/arm/mach-msm/board-9615-regulator.c
@@ -12,6 +12,7 @@
*/
#include <linux/regulator/pm8018-regulator.h>
+#include <mach/rpm-regulator.h>
#include "board-9615.h"
@@ -155,34 +156,130 @@
.pin_ctrl = _pin_ctrl, \
}
+#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
+ _peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
+ _force_mode, _power_mode, _state, _sleep_selectable, \
+ _always_on, _supply_regulator, _system_uA) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_modes_mask = _modes, \
+ .valid_ops_mask = _ops, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .input_uV = _min_uV, \
+ .apply_uV = _apply_uV, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id), \
+ .consumer_supplies = vreg_consumers_##_id, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8018_##_id, \
+ .default_uV = _default_uV, \
+ .peak_uA = _peak_uA, \
+ .avg_uA = _avg_uA, \
+ .pull_down_enable = _pull_down, \
+ .pin_ctrl = _pin_ctrl, \
+ .freq = RPM_VREG_FREQ_##_freq, \
+ .pin_fn = _pin_fn, \
+ .force_mode = _force_mode, \
+ .power_mode = _power_mode, \
+ .state = _state, \
+ .sleep_selectable = _sleep_selectable, \
+ .system_uA = _system_uA, \
+ }
+
+#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _init_peak_uA) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
+ RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_9615_NONE, \
+ RPM_VREG_FORCE_MODE_9615_NONE, RPM_VREG_POWER_MODE_9615_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+/* Pin control initialization */
+#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id##_PC), \
+ .consumer_supplies = vreg_consumers_##_id##_PC, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8018_##_id##_PC, \
+ .pin_fn = RPM_VREG_PIN_FN_9615_##_pin_fn, \
+ .pin_ctrl = _pin_ctrl, \
+ }
+
+
/* PM8018 regulator constraints */
struct pm8018_regulator_platform_data
msm_pm8018_regulator_pdata[] __devinitdata = {
- /* ID a_on pd min_uV max_uV en_t supply sys_uA */
- PM8018_VREG_INIT_SMPS(S1, 1, 1, 1150000, 1150000, 500, NULL, 100000),
- PM8018_VREG_INIT_SMPS(S2, 0, 1, 1225000, 1300000, 500, NULL, 0),
- PM8018_VREG_INIT_SMPS(S3, 1, 1, 1800000, 1800000, 500, NULL, 100000),
- PM8018_VREG_INIT_SMPS(S4, 0, 1, 2100000, 2200000, 500, NULL, 0),
- PM8018_VREG_INIT_SMPS(S5, 1, 1, 1350000, 1350000, 500, NULL, 100000),
+};
- PM8018_VREG_INIT_LDO(L2, 1, 1, 1800000, 1800000, 200, NULL, 10000),
- PM8018_VREG_INIT_LDO(L3, 0, 1, 1800000, 1800000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L4, 0, 1, 3075000, 3075000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L5, 0, 1, 2850000, 2850000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L6, 0, 1, 1800000, 2850000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L7, 0, 1, 1850000, 1900000, 200, "8018_s4", 0),
- PM8018_VREG_INIT_LDO(L8, 0, 1, 1200000, 1200000, 200, "8018_s3", 0),
- PM8018_VREG_INIT_LDO(L9, 1, 1, 1150000, 1150000, 200, "8018_s5",
- 10000),
- PM8018_VREG_INIT_LDO(L10, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L11, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L12, 0, 1, 1050000, 1050000, 200, "8018_s5", 0),
- PM8018_VREG_INIT_LDO(L13, 0, 1, 2950000, 2950000, 200, NULL, 0),
- PM8018_VREG_INIT_LDO(L14, 0, 1, 2850000, 2850000, 200, NULL, 0),
+static struct rpm_regulator_init_data
+msm_rpm_regulator_init_data[] __devinitdata = {
+ /* ID a_on pd ss min_uV max_uV supply sys_uA freq */
+ RPM_SMPS(S1, 1, 1, 1, 1150000, 1150000, NULL, 100000, 1p60),
+ RPM_SMPS(S2, 0, 1, 0, 1225000, 1300000, NULL, 0, 1p60),
+ RPM_SMPS(S3, 1, 1, 0, 1800000, 1800000, NULL, 100000, 1p60),
+ RPM_SMPS(S4, 0, 1, 0, 2100000, 2200000, NULL, 0, 1p60),
+ RPM_SMPS(S5, 1, 1, 0, 1350000, 1350000, NULL, 100000, 1p60),
- /* ID a_on pd en_t supply */
- PM8018_VREG_INIT_VS(LVS1, 0, 1, 0, "8018_s3"),
+ /* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
+ RPM_LDO(L2, 1, 1, 0, 1800000, 1800000, NULL, 0, 10000),
+ RPM_LDO(L3, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L4, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
+ RPM_LDO(L5, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+ RPM_LDO(L6, 0, 1, 0, 1800000, 2850000, NULL, 0, 0),
+ RPM_LDO(L7, 0, 1, 0, 1850000, 1900000, "8018_s4", 0, 0),
+ RPM_LDO(L8, 0, 1, 0, 1200000, 1200000, "8018_s3", 0, 0),
+ RPM_LDO(L9, 1, 1, 1, 1150000, 1150000, "8018_s5", 10000, 10000),
+ RPM_LDO(L10, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L11, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L12, 0, 1, 0, 1050000, 1050000, "8018_s5", 0, 0),
+ RPM_LDO(L13, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L14, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+
+ /* ID a_on pd ss supply */
+ RPM_VS(LVS1, 0, 1, 0, "8018_s3"),
};
int msm_pm8018_regulator_pdata_len __devinitdata =
ARRAY_SIZE(msm_pm8018_regulator_pdata);
+
+struct rpm_regulator_platform_data
+msm_rpm_regulator_9615_pdata __devinitdata = {
+ .init_data = msm_rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(msm_rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_9615,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8018_L9,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8018_S1,
+};
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index aa6ce58..4eb3d77 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -14,6 +14,7 @@
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/msm_ssbi.h>
+#include <linux/platform_data/qcom_crypto_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/mmc.h>
@@ -22,25 +23,14 @@
#include <mach/gpio.h>
#include <mach/gpiomux.h>
#include <mach/msm_spi.h>
+#include <linux/usb/android.h>
+#include <linux/usb/msm_hsusb.h>
#include "timer.h"
#include "devices.h"
#include "board-9615.h"
#include "cpuidle.h"
#include "pm.h"
-static struct platform_device *common_devices[] = {
- &msm9615_device_dmov,
- &msm_device_smd,
- &msm9615_device_uart_gsbi4,
- &msm9615_device_ssbi_pmic1,
- &msm9615_device_qup_i2c_gsbi5,
- &msm9615_device_qup_spi_gsbi3,
- &msm_device_sps,
- &msm9615_device_tsens,
- &msm_device_nand,
- &msm_rpm_device,
-};
-
static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
.irq_base = PM8018_IRQ_BASE,
.devirq = MSM_GPIO_TO_INT(87),
@@ -57,6 +47,7 @@
static struct pm8xxx_rtc_platform_data pm8xxx_rtc_pdata __devinitdata = {
.rtc_write_enable = false,
+ .rtc_alarm_powerup = false,
};
static struct pm8xxx_pwrkey_platform_data pm8xxx_pwrkey_pdata = {
@@ -87,6 +78,20 @@
},
};
+static struct platform_device msm9615_device_rpm_regulator __devinitdata = {
+ .name = "rpm-regulator",
+ .id = -1,
+ .dev = {
+ .platform_data = &msm_rpm_regulator_9615_pdata,
+ },
+};
+
+static struct gpiomux_setting ps_hold = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
static struct gpiomux_setting gsbi4 = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
@@ -111,6 +116,15 @@
.pull = GPIOMUX_PULL_NONE,
};
+struct msm_gpiomux_config msm9615_ps_hold_config[] __initdata = {
+ {
+ .gpio = 83,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &ps_hold,
+ },
+ },
+};
+
struct msm_gpiomux_config msm9615_gsbi_configs[] __initdata = {
{
.gpio = 8, /* GSBI3 QUP SPI_CLK */
@@ -181,6 +195,117 @@
},
};
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+#define QCE_SIZE 0x10000
+#define QCE_0_BASE 0x18500000
+
+#define QCE_HW_KEY_SUPPORT 0
+#define QCE_SHA_HMAC_SUPPORT 1
+#define QCE_SHARE_CE_RESOURCE 1
+#define QCE_CE_SHARED 0
+
+static struct resource qcrypto_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource qcedev_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV_CE_IN_CHAN,
+ .end = DMOV_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV_CE_IN_CRCI,
+ .end = DMOV_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV_CE_OUT_CRCI,
+ .end = DMOV_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+
+static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcrypto_device = {
+ .name = "qcrypto",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcrypto_resources),
+ .resource = qcrypto_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcrypto_ce_hw_suppport,
+ },
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcedev_device = {
+ .name = "qce",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcedev_resources),
+ .resource = qcedev_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcedev_ce_hw_suppport,
+ },
+};
+#endif
+
#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
|| defined(CONFIG_MMC_MSM_SDC2_SUPPORT))
@@ -460,6 +585,8 @@
msm_gpiomux_install(msm9615_gsbi_configs,
ARRAY_SIZE(msm9615_gsbi_configs));
+ msm_gpiomux_install(msm9615_ps_hold_config,
+ ARRAY_SIZE(msm9615_ps_hold_config));
return 0;
}
@@ -472,6 +599,59 @@
.src_clk_rate = 24000000,
};
+static struct msm_otg_platform_data msm_otg_pdata = {
+ .mode = USB_PERIPHERAL,
+ .otg_control = OTG_NO_CONTROL,
+ .phy_type = SNPS_28NM_INTEGRATED_PHY,
+ .pclk_src_name = "dfab_usb_hs_clk",
+};
+
+static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
+{
+ return 0;
+}
+
+static struct android_usb_platform_data android_usb_pdata = {
+ .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
+};
+
+static struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+ .dev = {
+ .platform_data = &android_usb_pdata,
+ },
+};
+
+static struct platform_device *common_devices[] = {
+ &msm9615_device_dmov,
+ &msm_device_smd,
+ &msm_device_otg,
+ &msm_device_gadget_peripheral,
+ &android_usb_device,
+ &msm9615_device_uart_gsbi4,
+ &msm9615_device_ssbi_pmic1,
+ &msm9615_device_qup_i2c_gsbi5,
+ &msm9615_device_qup_spi_gsbi3,
+ &msm_device_sps,
+ &msm9615_device_tsens,
+ &msm_device_nand,
+ &msm_rpm_device,
+#ifdef CONFIG_HW_RANDOM_MSM
+ &msm_device_rng,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+ &qcrypto_device,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+ &qcedev_device,
+#endif
+};
+
static void __init msm9615_i2c_init(void)
{
msm9615_device_qup_i2c_gsbi5.dev.platform_data =
@@ -484,11 +664,15 @@
gpiomux_init();
msm9615_i2c_init();
regulator_suppress_info_printing();
+ platform_device_register(&msm9615_device_rpm_regulator);
msm9615_device_qup_spi_gsbi3.dev.platform_data =
&msm9615_qup_spi_gsbi3_pdata;
msm9615_device_ssbi_pmic1.dev.platform_data =
&msm9615_ssbi_pm8018_pdata;
pm8018_platform_data.num_regulators = msm_pm8018_regulator_pdata_len;
+
+ msm_device_otg.dev.platform_data = &msm_otg_pdata;
+ msm_device_gadget_peripheral.dev.parent = &msm_device_otg.dev;
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
msm9615_init_mmc();
diff --git a/arch/arm/mach-msm/board-9615.h b/arch/arm/mach-msm/board-9615.h
index d8e74fe..0d9fae7 100644
--- a/arch/arm/mach-msm/board-9615.h
+++ b/arch/arm/mach-msm/board-9615.h
@@ -29,4 +29,7 @@
extern int msm_pm8018_regulator_pdata_len __devinitdata;
+extern struct rpm_regulator_platform_data
+msm_rpm_regulator_9615_pdata __devinitdata;
+
#endif
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index 907fa72..4328b85 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -36,6 +36,18 @@
#include "board-apq8064.h"
+static struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+};
+
+static struct msm_otg_platform_data msm_otg_pdata = {
+ .mode = USB_PERIPHERAL,
+ .otg_control = OTG_PHY_CONTROL,
+ .phy_type = SNPS_28NM_INTEGRATED_PHY,
+ .pclk_src_name = "dfab_usb_hs_clk",
+};
+
/* APQ8064 have 4 SDCC controllers */
enum sdcc_controllers {
SDCC1,
@@ -271,8 +283,10 @@
apq8064_add_sdcc(3, apq8064_sdc3_pdata);
}
+#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init apq8064_map_io(void)
{
+ msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
msm_map_apq8064_io();
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
@@ -307,6 +321,10 @@
&apq8064_slim_ctrl,
&apq8064_device_ssbi_pmic1,
&apq8064_device_ssbi_pmic2,
+ &msm_device_smd_apq8064,
+ &apq8064_device_otg,
+ &apq8064_device_gadget_peripheral,
+ &android_usb_device,
};
static struct platform_device *sim_devices[] __initdata = {
@@ -323,13 +341,6 @@
.max_clock_speed = 26000000,
};
-static struct msm_otg_platform_data msm_otg_pdata = {
- .mode = USB_PERIPHERAL,
- .otg_control = OTG_PHY_CONTROL,
- .phy_type = SNPS_28NM_INTEGRATED_PHY,
- .pclk_src_name = "dfab_usb_hs_clk",
-};
-
#define KS8851_IRQ_GPIO 43
static struct spi_board_info spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-msm/board-fsm9xxx.c b/arch/arm/mach-msm/board-fsm9xxx.c
index 5244434..eb936e4 100644
--- a/arch/arm/mach-msm/board-fsm9xxx.c
+++ b/arch/arm/mach-msm/board-fsm9xxx.c
@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/msm_ssbi.h>
#include <linux/mfd/pmic8058.h>
#include <linux/regulator/pmic8058-regulator.h>
#include <linux/i2c.h>
@@ -247,6 +248,7 @@
.name = "pm8058-regulator", \
.id = _id, \
.platform_data = &pm8058_vreg_init[_id], \
+ .pdata_size = sizeof(pm8058_vreg_init[_id]), \
}
#ifdef CONFIG_SENSORS_MSM_ADC
@@ -463,18 +465,21 @@
static struct pm8058_platform_data pm8058_fsm9xxx_data = {
.irq_base = PMIC8058_IRQ_BASE,
+ .irq = MSM_GPIO_TO_INT(47),
.num_subdevs = ARRAY_SIZE(pm8058_subdevs),
.sub_devices = pm8058_subdevs,
};
-static struct i2c_board_info pm8058_boardinfo[] __initdata = {
- {
- I2C_BOARD_INFO("pm8058-core", 0x55),
- .irq = MSM_GPIO_TO_INT(47),
- .platform_data = &pm8058_fsm9xxx_data,
+#ifdef CONFIG_MSM_SSBI
+static struct msm_ssbi_platform_data fsm9xxx_ssbi_pm8058_pdata = {
+ .controller_type = FSM_SBI_CTRL_SSBI,
+ .slave = {
+ .name = "pm8058-core",
+ .platform_data = &pm8058_fsm9xxx_data,
},
};
+#endif
static int __init buses_init(void)
{
@@ -483,9 +488,6 @@
pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
__func__, PMIC_GPIO_INT);
- i2c_register_board_info(0 /* I2C_SSBI ID */, pm8058_boardinfo,
- ARRAY_SIZE(pm8058_boardinfo));
-
return 0;
}
@@ -602,10 +604,6 @@
*/
#ifdef CONFIG_I2C_SSBI
-static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi1_pdata = {
- .controller_type = FSM_SBI_CTRL_SSBI,
-};
-
static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi2_pdata = {
.controller_type = FSM_SBI_CTRL_SSBI,
};
@@ -613,7 +611,9 @@
static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi3_pdata = {
.controller_type = FSM_SBI_CTRL_SSBI,
};
+#endif
+#if defined(CONFIG_I2C_SSBI) || defined(CONFIG_MSM_SSBI)
/* Intialize GPIO configuration for SSBI */
static struct msm_gpio ssbi_gpio_config_data[] = {
{ GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
@@ -811,8 +811,10 @@
&msm_device_smd,
&msm_device_dmov,
&msm_device_nand,
+#ifdef CONFIG_MSM_SSBI
+ &msm_device_ssbi_pmic1,
+#endif
#ifdef CONFIG_I2C_SSBI
- &msm_device_ssbi1,
&msm_device_ssbi2,
&msm_device_ssbi3,
#endif
@@ -873,6 +875,14 @@
regulator_has_full_constraints();
+#if defined(CONFIG_I2C_SSBI) || defined(CONFIG_MSM_SSBI)
+ fsm9xxx_init_ssbi_gpio();
+#endif
+#ifdef CONFIG_MSM_SSBI
+ msm_device_ssbi_pmic1.dev.platform_data =
+ &fsm9xxx_ssbi_pm8058_pdata;
+#endif
+
platform_add_devices(devices, ARRAY_SIZE(devices));
#ifdef CONFIG_MSM_SPM
@@ -887,8 +897,6 @@
fsm9xxx_init_uart1();
#endif
#ifdef CONFIG_I2C_SSBI
- fsm9xxx_init_ssbi_gpio();
- msm_device_ssbi1.dev.platform_data = &msm_i2c_ssbi1_pdata;
msm_device_ssbi2.dev.platform_data = &msm_i2c_ssbi2_pdata;
msm_device_ssbi3.dev.platform_data = &msm_i2c_ssbi3_pdata;
#endif
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 5f205f4..22de352 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -58,16 +58,17 @@
#include <linux/android_pmem.h>
#include <mach/camera.h>
+#ifdef CONFIG_USB_G_ANDROID
+#include <linux/usb/android.h>
+#include <mach/usbdiag.h>
+#endif
+
#include "devices.h"
#include "clock.h"
#include "acpuclock.h"
#include "msm-keypad-devices.h"
#include "pm.h"
-#ifdef CONFIG_USB_ANDROID
-#include <linux/usb/android_composite.h>
-#endif
-
#ifdef CONFIG_ARCH_MSM7X25
#define MSM_PMEM_MDP_SIZE 0xb21000
#define MSM_PMEM_ADSP_SIZE 0x97b000
@@ -103,135 +104,16 @@
},
};
-#ifdef CONFIG_USB_FUNCTION
-static struct usb_mass_storage_platform_data usb_mass_storage_pdata = {
- .nluns = 0x02,
- .buf_size = 16384,
- .vendor = "GOOGLE",
- .product = "Mass storage",
- .release = 0xffff,
+static struct platform_device smc91x_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
};
-static struct platform_device mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &usb_mass_storage_pdata,
- },
-};
-#endif
-#ifdef CONFIG_USB_ANDROID
-static char *usb_functions_default[] = {
- "diag",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_default_adb[] = {
- "diag",
- "adb",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_rndis[] = {
- "rndis",
-};
-
-static char *usb_functions_rndis_adb[] = {
- "rndis",
- "adb",
-};
-
-static char *usb_functions_all[] = {
-#ifdef CONFIG_USB_ANDROID_RNDIS
- "rndis",
-#endif
-#ifdef CONFIG_USB_ANDROID_DIAG
- "diag",
-#endif
- "adb",
-#ifdef CONFIG_USB_F_SERIAL
- "modem",
- "nmea",
-#endif
-#ifdef CONFIG_USB_ANDROID_RMNET
- "rmnet",
-#endif
- "usb_mass_storage",
-#ifdef CONFIG_USB_ANDROID_ACM
- "acm",
-#endif
-};
-
-static struct android_usb_product usb_products[] = {
- {
- .product_id = 0x9026,
- .num_functions = ARRAY_SIZE(usb_functions_default),
- .functions = usb_functions_default,
- },
- {
- .product_id = 0x9025,
- .num_functions = ARRAY_SIZE(usb_functions_default_adb),
- .functions = usb_functions_default_adb,
- },
- {
- .product_id = 0xf00e,
- .num_functions = ARRAY_SIZE(usb_functions_rndis),
- .functions = usb_functions_rndis,
- },
- {
- .product_id = 0x9024,
- .num_functions = ARRAY_SIZE(usb_functions_rndis_adb),
- .functions = usb_functions_rndis_adb,
- },
-};
-
-static struct usb_mass_storage_platform_data mass_storage_pdata = {
- .nluns = 1,
- .vendor = "Qualcomm Incorporated",
- .product = "Mass storage",
- .release = 0x0100,
- .can_stall = 1,
-};
-
-static struct platform_device usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &mass_storage_pdata,
- },
-};
-
-static struct usb_ether_platform_data rndis_pdata = {
- /* ethaddr is filled by board_serialno_setup */
- .vendorID = 0x05C6,
- .vendorDescr = "Qualcomm Incorporated",
-};
-
-static struct platform_device rndis_device = {
- .name = "rndis",
- .id = -1,
- .dev = {
- .platform_data = &rndis_pdata,
- },
-};
-
+#ifdef CONFIG_USB_G_ANDROID
static struct android_usb_platform_data android_usb_pdata = {
- .vendor_id = 0x05C6,
- .product_id = 0x9026,
- .version = 0x0100,
- .product_name = "Qualcomm HSUSB Device",
- .manufacturer_name = "Qualcomm Incorporated",
- .num_products = ARRAY_SIZE(usb_products),
- .products = usb_products,
- .num_functions = ARRAY_SIZE(usb_functions_all),
- .functions = usb_functions_all,
- .serial_number = "1234567890ABCDEF",
+ .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
};
static struct platform_device android_usb_device = {
@@ -241,114 +123,6 @@
.platform_data = &android_usb_pdata,
},
};
-
-static int __init board_serialno_setup(char *serialno)
-{
- int i;
- char *src = serialno;
-
- /* create a fake MAC address from our serial number.
- * first byte is 0x02 to signify locally administered.
- */
- rndis_pdata.ethaddr[0] = 0x02;
- for (i = 0; *src; i++) {
- /* XOR the USB serial across the remaining bytes */
- rndis_pdata.ethaddr[i % (ETH_ALEN - 1) + 1] ^= *src++;
- }
-
- android_usb_pdata.serial_number = serialno;
- return 1;
-}
-__setup("androidboot.serialno=", board_serialno_setup);
-#endif
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#ifdef CONFIG_USB_FUNCTION
-static struct usb_function_map usb_functions_map[] = {
- {"diag", 0},
- {"adb", 1},
- {"modem", 2},
- {"nmea", 3},
- {"mass_storage", 4},
- {"ethernet", 5},
- {"rmnet", 6},
-};
-
-/* dynamic composition */
-static struct usb_composition usb_func_composition[] = {
- {
- .product_id = 0x9012,
- .functions = 0x5, /* 0101 */
- },
-
- {
- .product_id = 0x9013,
- .functions = 0x15, /* 10101 */
- },
-
- {
- .product_id = 0x9014,
- .functions = 0x30, /* 110000 */
- },
-
- {
- .product_id = 0x9016,
- .functions = 0xD, /* 01101 */
- },
-
- {
- .product_id = 0x9017,
- .functions = 0x1D, /* 11101 */
- },
-
- {
- .product_id = 0xF000,
- .functions = 0x10, /* 10000 */
- },
-
- {
- .product_id = 0xF009,
- .functions = 0x20, /* 100000 */
- },
-
- {
- .product_id = 0x9018,
- .functions = 0x1F, /* 011111 */
- },
-#ifdef CONFIG_USB_FUNCTION_RMNET
- {
- .product_id = 0x9021,
- /* DIAG + RMNET */
- .functions = 0x41,
- },
- {
- .product_id = 0x9022,
- /* DIAG + ADB + RMNET */
- .functions = 0x43,
- },
-#endif
-
-};
-
-static struct msm_hsusb_platform_data msm_hsusb_pdata = {
- .version = 0x0100,
- .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_65NM),
- .vendor_id = 0x5c6,
- .product_name = "Qualcomm HSUSB Device",
- .serial_number = "1234567890ABCDEF",
- .manufacturer_name = "Qualcomm Incorporated",
- .compositions = usb_func_composition,
- .num_compositions = ARRAY_SIZE(usb_func_composition),
- .function_map = usb_functions_map,
- .num_functions = ARRAY_SIZE(usb_functions_map),
- .config_gpio = NULL,
-};
#endif
#ifdef CONFIG_USB_EHCI_MSM_72K
@@ -1410,22 +1184,10 @@
#endif
#endif
-#ifdef CONFIG_USB_FUNCTION
- &msm_device_hsusb_peripheral,
- &mass_storage_device,
-#endif
-
-#ifdef CONFIG_USB_ANDROID
- &usb_mass_storage_device,
- &rndis_device,
-#ifdef CONFIG_USB_ANDROID_DIAG
- &usb_diag_device,
-#endif
-#ifdef CONFIG_USB_F_SERIAL
- &usb_gadget_fserial_device,
-#endif
+#ifdef CONFIG_USB_G_ANDROID
&android_usb_device,
#endif
+
&msm_device_i2c,
&smc91x_device,
&msm_device_tssc,
@@ -1891,13 +1653,6 @@
usb_mpp_init();
-#ifdef CONFIG_USB_FUNCTION
- msm_hsusb_pdata.swfi_latency =
- msm7x27_pm_data
- [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
-
- msm_device_hsusb_peripheral.dev.platform_data = &msm_hsusb_pdata;
-#endif
#ifdef CONFIG_USB_MSM_OTG_72K
msm_device_otg.dev.platform_data = &msm_otg_pdata;
@@ -2107,6 +1862,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
@@ -2117,6 +1873,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
@@ -2127,6 +1884,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
@@ -2137,4 +1895,5 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x27_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 67b1dcc..92879bc 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -1916,6 +1916,7 @@
SND(FM_DIGITAL_STEREO_HEADSET, 26),
SND(FM_DIGITAL_SPEAKER_PHONE, 27),
SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
+ SND(STEREO_HEADSET_AND_SPEAKER, 31),
SND(CURRENT, 0x7FFFFFFE),
SND(FM_ANALOG_STEREO_HEADSET, 35),
SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
@@ -3249,6 +3250,7 @@
.init_machine = msm7627a_rumi3_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27A_SURF, "QCT MSM7x27a SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3258,6 +3260,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X27A_FFA, "QCT MSM7x27a FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3267,6 +3270,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7625A_SURF, "QCT MSM7625a SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3276,6 +3280,7 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7625A_FFA, "QCT MSM7625a FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -3285,4 +3290,5 @@
.init_machine = msm7x2x_init,
.timer = &msm_timer,
.init_early = msm7x2x_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index ee9df6f..b71061a 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -21,6 +21,7 @@
#ifdef CONFIG_SPI_QSD
#include <linux/spi/spi.h>
#endif
+#include <linux/msm_ssbi.h>
#include <linux/mfd/pmic8058.h>
#include <linux/mfd/marimba.h>
#include <linux/i2c.h>
@@ -816,19 +817,22 @@
static struct pm8058_platform_data pm8058_7x30_data = {
.irq_base = PMIC8058_IRQ_BASE,
+ .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
.num_subdevs = ARRAY_SIZE(pm8058_subdevs),
.sub_devices = pm8058_subdevs,
.irq_trigger_flags = IRQF_TRIGGER_LOW,
};
-static struct i2c_board_info pm8058_boardinfo[] __initdata = {
- {
- I2C_BOARD_INFO("pm8058-core", 0x55),
- .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
- .platform_data = &pm8058_7x30_data,
+#ifdef CONFIG_MSM_SSBI
+static struct msm_ssbi_platform_data msm7x30_ssbi_pm8058_pdata = {
+ .controller_type = MSM_SBI_CTRL_SSBI2,
+ .slave = {
+ .name = "pm8058-core",
+ .platform_data = &pm8058_7x30_data,
},
};
+#endif
static struct i2c_board_info cy8info[] __initdata = {
{
@@ -1607,9 +1611,6 @@
= sizeof(surf_keypad_data);
}
- i2c_register_board_info(6 /* I2C_SSBI ID */, pm8058_boardinfo,
- ARRAY_SIZE(pm8058_boardinfo));
-
return 0;
}
@@ -5306,8 +5307,11 @@
&android_usb_device,
#endif
&qsd_device_spi,
+
+#ifdef CONFIG_MSM_SSBI
+ &msm_device_ssbi_pmic1,
+#endif
#ifdef CONFIG_I2C_SSBI
- &msm_device_ssbi6,
&msm_device_ssbi7,
#endif
&android_pmem_device,
@@ -5513,11 +5517,6 @@
}
#ifdef CONFIG_I2C_SSBI
-static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi6_pdata = {
- .rsl_id = "D:PMIC_SSBI",
- .controller_type = MSM_SBI_CTRL_SSBI2,
-};
-
static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
.rsl_id = "D:CODEC_SSBI",
.controller_type = MSM_SBI_CTRL_SSBI,
@@ -6977,6 +6976,11 @@
msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
}
+#ifdef CONFIG_MSM_SSBI
+ msm_device_ssbi_pmic1.dev.platform_data =
+ &msm7x30_ssbi_pm8058_pdata;
+#endif
+
platform_add_devices(msm_footswitch_devices,
msm_num_footswitch_devices);
platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -7034,7 +7038,6 @@
bt_power_init();
#ifdef CONFIG_I2C_SSBI
- msm_device_ssbi6.dev.platform_data = &msm_i2c_ssbi6_pdata;
msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
#endif
if (machine_is_msm7x30_fluid())
@@ -7226,6 +7229,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -7236,6 +7240,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -7246,6 +7251,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
@@ -7256,6 +7262,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
@@ -7266,6 +7273,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
.boot_params = PHYS_OFFSET + 0x100,
@@ -7275,6 +7283,7 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
.boot_params = PHYS_OFFSET + 0x100,
@@ -7284,4 +7293,5 @@
.init_machine = msm7x30_init,
.timer = &msm_timer,
.init_early = msm7x30_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960-regulator.c b/arch/arm/mach-msm/board-msm8960-regulator.c
index 3b6da9a..ca24e79 100644
--- a/arch/arm/mach-msm/board-msm8960-regulator.c
+++ b/arch/arm/mach-msm/board-msm8960-regulator.c
@@ -146,6 +146,7 @@
REGULATOR_SUPPLY("8921_s3", NULL),
REGULATOR_SUPPLY("HSUSB_VDDCX", "msm_otg"),
REGULATOR_SUPPLY("riva_vddcx", "wcnss_wlan.0"),
+ REGULATOR_SUPPLY("HSIC_VDDCX", "msm_hsic_host"),
};
VREG_CONSUMERS(S4) = {
REGULATOR_SUPPLY("8921_s4", NULL),
@@ -383,8 +384,8 @@
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
- RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_NONE, \
- RPM_VREG_FORCE_MODE_NONE, RPM_VREG_POWER_MODE_PWM, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
+ RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
_supply_regulator, _system_uA)
@@ -394,15 +395,15 @@
| REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
| REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
| REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
- RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_NONE, \
- RPM_VREG_FORCE_MODE_NONE, RPM_VREG_POWER_MODE_PWM, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
+ RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
_supply_regulator, _system_uA)
#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
- RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_NONE, \
- RPM_VREG_FORCE_MODE_NONE, RPM_VREG_POWER_MODE_PWM, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8960_NONE, \
+ RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
_supply_regulator, 0)
@@ -410,8 +411,8 @@
_supply_regulator, _freq) \
RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
| REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
- RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_NONE, \
- RPM_VREG_FORCE_MODE_NONE, RPM_VREG_POWER_MODE_PWM, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8960_NONE, \
+ RPM_VREG_FORCE_MODE_8960_NONE, RPM_VREG_POWER_MODE_8960_PWM, \
RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
_supply_regulator, 0)
@@ -429,7 +430,7 @@
.supply_regulator = _supply_regulator, \
}, \
.id = RPM_VREG_ID_PM8921_##_id##_PC, \
- .pin_fn = RPM_VREG_PIN_FN_##_pin_fn, \
+ .pin_fn = RPM_VREG_PIN_FN_8960_##_pin_fn, \
.pin_ctrl = _pin_ctrl, \
}
@@ -444,9 +445,9 @@
/* SAW regulator constraints */
struct regulator_init_data msm_saw_regulator_pdata_s5 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8921_s5", 1050000, 1150000);
+ SAW_VREG_INIT(S5, "8921_s5", 950000, 1150000);
struct regulator_init_data msm_saw_regulator_pdata_s6 =
- SAW_VREG_INIT(S6, "8921_s6", 1050000, 1150000);
+ SAW_VREG_INIT(S6, "8921_s6", 950000, 1150000);
/* PM8921 regulator constraints */
struct pm8921_regulator_platform_data
@@ -520,6 +521,9 @@
ARRAY_SIZE(msm_pm8921_regulator_pdata);
struct rpm_regulator_platform_data msm_rpm_regulator_pdata __devinitdata = {
- .init_data = msm_rpm_regulator_init_data,
- .num_regulators = ARRAY_SIZE(msm_rpm_regulator_init_data),
+ .init_data = msm_rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(msm_rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_8960,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8921_L24,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3,
};
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 09bc34f..2615cd4 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -233,7 +233,13 @@
.pull = GPIOMUX_PULL_DOWN,
};
-static struct gpiomux_setting gsbi3 = {
+static struct gpiomux_setting gsbi3_suspended_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_KEEPER,
+};
+
+static struct gpiomux_setting gsbi3_active_cfg = {
.func = GPIOMUX_FUNC_1,
.drv = GPIOMUX_DRV_8MA,
.pull = GPIOMUX_PULL_NONE,
@@ -347,13 +353,15 @@
{
.gpio = 16, /* GSBI3 I2C QUP SDA */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
.gpio = 17, /* GSBI3 I2C QUP SCL */
.settings = {
- [GPIOMUX_SUSPENDED] = &gsbi3,
+ [GPIOMUX_SUSPENDED] = &gsbi3_suspended_cfg,
+ [GPIOMUX_ACTIVE] = &gsbi3_active_cfg,
},
},
{
@@ -703,6 +711,37 @@
},
};
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct gpiomux_setting hsic_act_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_12MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct gpiomux_setting hsic_sus_cfg = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct msm_gpiomux_config msm8960_hsic_configs[] = {
+ {
+ .gpio = 150, /*HSIC_STROBE */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+ {
+ .gpio = 151, /* HSIC_DATA */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &hsic_act_cfg,
+ [GPIOMUX_SUSPENDED] = &hsic_sus_cfg,
+ },
+ },
+};
+#endif
+
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
enum {
SX150X_CAM,
@@ -748,8 +787,11 @@
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000
#define MSM_PMEM_ADSP_SIZE 0x3800000
#define MSM_PMEM_AUDIO_SIZE 0x28B000
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
+#else
#define MSM_PMEM_SIZE 0x1800000 /* 24 Mbytes */
-
+#endif
#define MSM_ION_EBI_SIZE SZ_8M
#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
@@ -1334,10 +1376,14 @@
#define MSM_FB_WRITEBACK_OFFSET 0
#endif
-
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+/* 4 bpp x 2 page HDMI case */
+#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
+#else
/* Note: must be multiple of 4096 */
#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
MSM_FB_WRITEBACK_SIZE, 4096)
+#endif
static int writeback_offset(void)
{
@@ -1696,6 +1742,43 @@
},
};
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
+ /* If HDMI is used as primary */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+};
+static struct msm_bus_paths mdp_bus_scale_usecases[] = {
+ {
+ ARRAY_SIZE(mdp_init_vectors),
+ mdp_init_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+};
+#else
static struct msm_bus_vectors mdp_ui_vectors[] = {
{
.src = MSM_BUS_MASTER_MDP_PORT0,
@@ -1761,6 +1844,7 @@
mdp_1080p_vectors,
},
};
+#endif
static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
mdp_bus_scale_usecases,
@@ -1770,16 +1854,29 @@
#endif
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+int mdp_core_clk_rate_table[] = {
+ 200000000,
+ 200000000,
+ 200000000,
+ 200000000,
+};
+#else
int mdp_core_clk_rate_table[] = {
85330000,
85330000,
160000000,
200000000,
};
+#endif
static struct msm_panel_common_pdata mdp_pdata = {
.gpio = MDP_VSYNC_GPIO,
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ .mdp_core_clk_rate = 200000000,
+#else
.mdp_core_clk_rate = 85330000,
+#endif
.mdp_core_clk_table = mdp_core_clk_rate_table,
.num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
#ifdef CONFIG_MSM_BUS_SCALING
@@ -1907,6 +2004,17 @@
.ib = 0,
},
};
+
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+static struct msm_bus_vectors dtv_bus_def_vectors[] = {
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+};
+#else
static struct msm_bus_vectors dtv_bus_def_vectors[] = {
{
.src = MSM_BUS_MASTER_MDP_PORT0,
@@ -1915,6 +2023,8 @@
.ib = 707616000 * 2,
},
};
+#endif
+
static struct msm_bus_paths dtv_bus_scale_usecases[] = {
{
ARRAY_SIZE(dtv_bus_init_vectors),
@@ -2466,6 +2576,11 @@
msm_gpiomux_install(wcnss_5wire_interface,
ARRAY_SIZE(wcnss_5wire_interface));
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ msm_gpiomux_install(msm8960_hsic_configs,
+ ARRAY_SIZE(msm8960_hsic_configs));
+#endif
+
return 0;
}
@@ -2893,6 +3008,15 @@
};
#endif
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+static struct msm_hsic_host_platform_data msm_hsic_pdata = {
+ .strobe = 150,
+ .data = 151,
+};
+#else
+static struct msm_hsic_host_platform_data msm_hsic_pdata;
+#endif
+
#define PID_MAGIC_ID 0x71432909
#define SERIAL_NUM_MAGIC_ID 0x61945374
#define SERIAL_NUMBER_LENGTH 127
@@ -3657,7 +3781,7 @@
static void __init msm8960_gfx_init(void)
{
- uint32_t soc_platform_version = socinfo_get_platform_version();
+ uint32_t soc_platform_version = socinfo_get_version();
if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1) {
struct kgsl_device_platform_data *kgsl_3d0_pdata =
msm_kgsl_3d0.dev.platform_data;
@@ -3684,6 +3808,7 @@
static struct pm8xxx_rtc_platform_data pm8xxx_rtc_pdata __devinitdata = {
.rtc_write_enable = false,
+ .rtc_alarm_powerup = false,
};
static struct pm8xxx_pwrkey_platform_data pm8xxx_pwrkey_pdata = {
@@ -4354,6 +4479,7 @@
msm8960_device_otg.dev.platform_data = &msm_otg_pdata;
msm8960_device_gadget_peripheral.dev.parent = &msm8960_device_otg.dev;
msm_device_hsusb_host.dev.parent = &msm8960_device_otg.dev;
+ msm_device_hsic_host.dev.platform_data = &msm_hsic_pdata;
gpiomux_init();
if (machine_is_msm8960_cdp())
fpga_init();
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 79bad3f..dab800f 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -16,6 +16,7 @@
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/msm_ssbi.h>
#include <linux/mfd/pmic8058.h>
#include <linux/input/pmic8058-keypad.h>
@@ -2477,11 +2478,6 @@
#ifdef CONFIG_I2C_SSBI
/* PMIC SSBI */
-static struct msm_i2c_ssbi_platform_data msm_ssbi1_pdata = {
- .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
-};
-
-/* PMIC SSBI */
static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
.controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
};
@@ -2593,13 +2589,21 @@
#define MSM_FB_WRITEBACK_OFFSET 0
#endif
-
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+/* 4 bpp x 2 page HDMI case */
+#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
+#else
/* Note: must be multiple of 4096 */
#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
MSM_FB_WRITEBACK_SIZE + \
MSM_FB_DSUB_PMEM_ADDER, 4096)
+#endif
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
+#else
#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
+#endif
static int writeback_offset(void)
{
@@ -3841,35 +3845,73 @@
REGULATOR_SUPPLY("8901_mvs0", NULL),
};
+/* Pin control regulators */
+static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
+ REGULATOR_SUPPLY("8058_l8_pc", NULL),
+};
+static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
+ REGULATOR_SUPPLY("8058_l20_pc", NULL),
+};
+static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
+ REGULATOR_SUPPLY("8058_l21_pc", NULL),
+};
+static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
+ REGULATOR_SUPPLY("8058_s2_pc", NULL),
+};
+static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
+ REGULATOR_SUPPLY("8901_l0_pc", NULL),
+};
+static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
+ REGULATOR_SUPPLY("8901_s4_pc", NULL),
+};
+
#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
_default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
- _freq, _pin_fn, _rpm_mode, _state, _sleep_selectable, \
+ _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
_always_on) \
- [RPM_VREG_ID_##_id] = { \
+ { \
.init_data = { \
.constraints = { \
- .valid_modes_mask = _modes, \
- .valid_ops_mask = _ops, \
- .min_uV = _min_uV, \
- .max_uV = _max_uV, \
- .input_uV = _min_uV, \
- .apply_uV = _apply_uV, \
- .always_on = _always_on, \
+ .valid_modes_mask = _modes, \
+ .valid_ops_mask = _ops, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .input_uV = _min_uV, \
+ .apply_uV = _apply_uV, \
+ .always_on = _always_on, \
}, \
- .consumer_supplies = vreg_consumers_##_id, \
- .num_consumer_supplies = \
+ .consumer_supplies = vreg_consumers_##_id, \
+ .num_consumer_supplies = \
ARRAY_SIZE(vreg_consumers_##_id), \
}, \
- .default_uV = _default_uV, \
- .peak_uA = _peak_uA, \
- .avg_uA = _avg_uA, \
- .pull_down_enable = _pull_down, \
+ .id = RPM_VREG_ID_##_id, \
+ .default_uV = _default_uV, \
+ .peak_uA = _peak_uA, \
+ .avg_uA = _avg_uA, \
+ .pull_down_enable = _pull_down, \
+ .pin_ctrl = _pin_ctrl, \
+ .freq = RPM_VREG_FREQ_##_freq, \
+ .pin_fn = _pin_fn, \
+ .force_mode = _force_mode, \
+ .state = _state, \
+ .sleep_selectable = _sleep_selectable, \
+ }
+
+/* Pin control initialization */
+#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id##_PC), \
+ .consumer_supplies = vreg_consumers_##_id##_PC, \
+ }, \
+ .id = RPM_VREG_ID_##_id##_PC, \
+ .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
.pin_ctrl = _pin_ctrl, \
- .freq = _freq, \
- .pin_fn = _pin_fn, \
- .mode = _rpm_mode, \
- .state = _state, \
- .sleep_selectable = _sleep_selectable, \
}
/*
@@ -3882,198 +3924,165 @@
* .init_data.constraints.initial_mode.
*/
-#define RPM_VREG_INIT_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
- _max_uV, _init_peak_uA, _pin_ctrl) \
+#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _init_peak_uA) \
RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
- _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
- RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
- RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
-
-#define RPM_VREG_INIT_LDO_PF(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
- _max_uV, _init_peak_uA, _pin_ctrl, _pin_fn) \
- RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
- REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
- REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
- REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
- REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
- _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
- _pin_fn, RPM_VREG_MODE_NONE, RPM_VREG_STATE_OFF, \
+ _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
+ RPM_VREG_PIN_FN_8660_ENABLE, \
+ RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
_sleep_selectable, _always_on)
-#define RPM_VREG_INIT_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
- _max_uV, _init_peak_uA, _pin_ctrl, _freq) \
+#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _init_peak_uA, _freq) \
RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
- _init_peak_uA, _pd, _pin_ctrl, _freq, \
- RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
- RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
+ _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
+ RPM_VREG_PIN_FN_8660_ENABLE, \
+ RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
+ _sleep_selectable, _always_on)
-#define RPM_VREG_INIT_VS(_id, _always_on, _pd, _sleep_selectable, _pin_ctrl) \
+#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
- 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
- RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
- RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
+ 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
+ RPM_VREG_PIN_FN_8660_ENABLE, \
+ RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
+ _sleep_selectable, _always_on)
-#define RPM_VREG_INIT_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
- _max_uV, _pin_ctrl) \
+#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
- _min_uV, 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
- RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
- RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
+ _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
+ RPM_VREG_PIN_FN_8660_ENABLE, \
+ RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
+ _sleep_selectable, _always_on)
-#define LDO50HMIN RPM_VREG_LDO_50_HPM_MIN_LOAD
-#define LDO150HMIN RPM_VREG_LDO_150_HPM_MIN_LOAD
-#define LDO300HMIN RPM_VREG_LDO_300_HPM_MIN_LOAD
-#define SMPS_HMIN RPM_VREG_SMPS_HPM_MIN_LOAD
-#define FTS_HMIN RPM_VREG_FTSMPS_HPM_MIN_LOAD
+#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
+#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
+#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
+#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
+#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
-static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
- RPM_VREG_INIT_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN, 0),
- RPM_VREG_INIT_LDO_PF(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN,
- RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
- RPM_VREG_INIT_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO_PF(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN,
- RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
- RPM_VREG_INIT_LDO_PF(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN,
- RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
- RPM_VREG_INIT_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
- RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
-
- RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
-
- RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
- RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
-
- RPM_VREG_INIT_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000, 0),
-
- RPM_VREG_INIT_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN,
- RPM_VREG_PIN_CTRL_A0),
- RPM_VREG_INIT_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
- RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
-
- RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
- RPM_VREG_FREQ_1p60),
- RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
- RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p60),
-
- RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
- RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
- RPM_VREG_INIT_VS(PM8901_LVS2, 0, 1, 0, 0),
- RPM_VREG_INIT_VS(PM8901_LVS3, 0, 1, 0, 0),
- RPM_VREG_INIT_VS(PM8901_MVS0, 0, 1, 0, 0),
+/* RPM early regulator constraints */
+static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
+ /* ID a_on pd ss min_uV max_uV init_ip freq */
+ RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
+ RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
};
-#define RPM_VREG(_id) \
- [_id] = { \
- .name = "rpm-regulator", \
- .id = _id, \
- .dev = { \
- .platform_data = &rpm_vreg_init_pdata[_id], \
- }, \
- }
+/* RPM regulator constraints */
+static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
+ /* ID a_on pd ss min_uV max_uV init_ip */
+ RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
+ RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
+ RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
+ RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
+ RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
+ RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
+ RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
+ RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
+ RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
+ RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
+ RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
+ RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
+ RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
+ RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
+ RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
+ RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
+ RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
+ RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
+ RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
+ RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
+ RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
+ RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
+ RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
+ RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
+ RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
+ RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
-static struct platform_device rpm_vreg_device[RPM_VREG_ID_MAX] = {
- RPM_VREG(RPM_VREG_ID_PM8058_L0),
- RPM_VREG(RPM_VREG_ID_PM8058_L1),
- RPM_VREG(RPM_VREG_ID_PM8058_L2),
- RPM_VREG(RPM_VREG_ID_PM8058_L3),
- RPM_VREG(RPM_VREG_ID_PM8058_L4),
- RPM_VREG(RPM_VREG_ID_PM8058_L5),
- RPM_VREG(RPM_VREG_ID_PM8058_L6),
- RPM_VREG(RPM_VREG_ID_PM8058_L7),
- RPM_VREG(RPM_VREG_ID_PM8058_L8),
- RPM_VREG(RPM_VREG_ID_PM8058_L9),
- RPM_VREG(RPM_VREG_ID_PM8058_L10),
- RPM_VREG(RPM_VREG_ID_PM8058_L11),
- RPM_VREG(RPM_VREG_ID_PM8058_L12),
- RPM_VREG(RPM_VREG_ID_PM8058_L13),
- RPM_VREG(RPM_VREG_ID_PM8058_L14),
- RPM_VREG(RPM_VREG_ID_PM8058_L15),
- RPM_VREG(RPM_VREG_ID_PM8058_L16),
- RPM_VREG(RPM_VREG_ID_PM8058_L17),
- RPM_VREG(RPM_VREG_ID_PM8058_L18),
- RPM_VREG(RPM_VREG_ID_PM8058_L19),
- RPM_VREG(RPM_VREG_ID_PM8058_L20),
- RPM_VREG(RPM_VREG_ID_PM8058_L21),
- RPM_VREG(RPM_VREG_ID_PM8058_L22),
- RPM_VREG(RPM_VREG_ID_PM8058_L23),
- RPM_VREG(RPM_VREG_ID_PM8058_L24),
- RPM_VREG(RPM_VREG_ID_PM8058_L25),
- RPM_VREG(RPM_VREG_ID_PM8058_S0),
- RPM_VREG(RPM_VREG_ID_PM8058_S1),
- RPM_VREG(RPM_VREG_ID_PM8058_S2),
- RPM_VREG(RPM_VREG_ID_PM8058_S3),
- RPM_VREG(RPM_VREG_ID_PM8058_S4),
- RPM_VREG(RPM_VREG_ID_PM8058_LVS0),
- RPM_VREG(RPM_VREG_ID_PM8058_LVS1),
- RPM_VREG(RPM_VREG_ID_PM8058_NCP),
- RPM_VREG(RPM_VREG_ID_PM8901_L0),
- RPM_VREG(RPM_VREG_ID_PM8901_L1),
- RPM_VREG(RPM_VREG_ID_PM8901_L2),
- RPM_VREG(RPM_VREG_ID_PM8901_L3),
- RPM_VREG(RPM_VREG_ID_PM8901_L4),
- RPM_VREG(RPM_VREG_ID_PM8901_L5),
- RPM_VREG(RPM_VREG_ID_PM8901_L6),
- RPM_VREG(RPM_VREG_ID_PM8901_S2),
- RPM_VREG(RPM_VREG_ID_PM8901_S3),
- RPM_VREG(RPM_VREG_ID_PM8901_S4),
- RPM_VREG(RPM_VREG_ID_PM8901_LVS0),
- RPM_VREG(RPM_VREG_ID_PM8901_LVS1),
- RPM_VREG(RPM_VREG_ID_PM8901_LVS2),
- RPM_VREG(RPM_VREG_ID_PM8901_LVS3),
- RPM_VREG(RPM_VREG_ID_PM8901_MVS0),
+ /* ID a_on pd ss min_uV max_uV init_ip freq */
+ RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
+ RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
+ RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
+
+ /* ID a_on pd ss */
+ RPM_VS(PM8058_LVS0, 0, 1, 0),
+ RPM_VS(PM8058_LVS1, 0, 1, 0),
+
+ /* ID a_on pd ss min_uV max_uV */
+ RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
+
+ /* ID a_on pd ss min_uV max_uV init_ip */
+ RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
+ RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
+ RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
+ RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
+ RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
+ RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
+ RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
+
+ /* ID a_on pd ss min_uV max_uV init_ip freq */
+ RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
+ RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
+ RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
+
+ /* ID a_on pd ss */
+ RPM_VS(PM8901_LVS0, 1, 1, 0),
+ RPM_VS(PM8901_LVS1, 0, 1, 0),
+ RPM_VS(PM8901_LVS2, 0, 1, 0),
+ RPM_VS(PM8901_LVS3, 0, 1, 0),
+ RPM_VS(PM8901_MVS0, 0, 1, 0),
+
+ /* ID a_on pin_func pin_ctrl */
+ RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
+ RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
+ RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
+ RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
+ RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
+ RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
+};
+
+static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
+ .init_data = rpm_regulator_early_init_data,
+ .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
+ .version = RPM_VREG_VERSION_8660,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
+};
+
+static struct rpm_regulator_platform_data rpm_regulator_pdata = {
+ .init_data = rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_8660,
+};
+
+static struct platform_device rpm_regulator_early_device = {
+ .name = "rpm-regulator",
+ .id = 0,
+ .dev = {
+ .platform_data = &rpm_regulator_early_pdata,
+ },
+};
+
+static struct platform_device rpm_regulator_device = {
+ .name = "rpm-regulator",
+ .id = 1,
+ .dev = {
+ .platform_data = &rpm_regulator_pdata,
+ },
};
static struct platform_device *early_regulators[] __initdata = {
&msm_device_saw_s0,
&msm_device_saw_s1,
-#ifdef CONFIG_PMIC8058
- &rpm_vreg_device[RPM_VREG_ID_PM8058_S0],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_S1],
-#endif
+ &rpm_regulator_early_device,
};
static struct platform_device *early_devices[] __initdata = {
@@ -4118,7 +4127,6 @@
&msm_gsbi12_qup_i2c_device,
#endif
#ifdef CONFIG_I2C_SSBI
- &msm_device_ssbi1,
&msm_device_ssbi2,
&msm_device_ssbi3,
#endif
@@ -4963,8 +4971,10 @@
#ifdef CONFIG_SERIAL_MSM_HS
&msm_device_uart_dm1,
#endif
+#ifdef CONFIG_MSM_SSBI
+ &msm_device_ssbi_pmic1,
+#endif
#ifdef CONFIG_I2C_SSBI
- &msm_device_ssbi1,
&msm_device_ssbi2,
&msm_device_ssbi3,
#endif
@@ -5061,57 +5071,7 @@
#ifdef CONFIG_SENSORS_MSM_ADC
&msm_adc_device,
#endif
-#ifdef CONFIG_PMIC8058
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L0],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L1],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L2],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L3],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L4],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L5],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L6],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L7],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L8],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L9],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L10],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L11],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L12],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L13],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L14],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L15],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L16],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L17],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L18],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L19],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L20],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L21],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L22],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L23],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L24],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_L25],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_S2],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_S3],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_S4],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS0],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS1],
- &rpm_vreg_device[RPM_VREG_ID_PM8058_NCP],
-#endif
-#ifdef CONFIG_PMIC8901
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L0],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L1],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L2],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L3],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L4],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L5],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_L6],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_S2],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_S3],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_S4],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS0],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS1],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS2],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS3],
- &rpm_vreg_device[RPM_VREG_ID_PM8901_MVS0],
-#endif
+ &rpm_regulator_device,
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
@@ -6361,20 +6321,23 @@
static struct pm8058_platform_data pm8058_platform_data = {
.irq_base = PM8058_IRQ_BASE,
+ .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
.num_subdevs = ARRAY_SIZE(pm8058_subdevs),
.sub_devices = pm8058_subdevs,
.irq_trigger_flags = IRQF_TRIGGER_LOW,
};
-static struct i2c_board_info pm8058_boardinfo[] __initdata = {
- {
- I2C_BOARD_INFO("pm8058-core", 0x55),
- .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
- .platform_data = &pm8058_platform_data,
+#ifdef CONFIG_MSM_SSBI
+static struct msm_ssbi_platform_data msm8x60_ssbi_pm8058_pdata __devinitdata = {
+ .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
+ .slave = {
+ .name = "pm8058-core",
+ .platform_data = &pm8058_platform_data,
},
};
-#endif /* CONFIG_PMIC8058 */
+#endif
+#endif /* CONFIG_PMIC8058 */
#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
@@ -7158,14 +7121,6 @@
};
static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
-#ifdef CONFIG_PMIC8058
- {
- I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
- MSM_SSBI1_I2C_BUS_ID,
- pm8058_boardinfo,
- ARRAY_SIZE(pm8058_boardinfo),
- },
-#endif
#ifdef CONFIG_PMIC8901
{
I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
@@ -7436,11 +7391,15 @@
msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
#endif
#ifdef CONFIG_I2C_SSBI
- msm_device_ssbi1.dev.platform_data = &msm_ssbi1_pdata;
msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
#endif
+#ifdef CONFIG_MSM_SSBI
+ msm_device_ssbi_pmic1.dev.platform_data =
+ &msm8x60_ssbi_pm8058_pdata;
+#endif
+
if (machine_is_msm8x60_fluid()) {
#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
(defined(CONFIG_SMB137B_CHARGER) || \
@@ -9127,7 +9086,6 @@
}
#ifdef CONFIG_MSM_BUS_SCALING
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
static struct msm_bus_vectors mdp_init_vectors[] = {
/* For now, 0th array entry is reserved.
* Please leave 0 as is and don't use it
@@ -9147,6 +9105,52 @@
},
};
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
+ /* If HDMI is used as primary */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_SMI,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+ /* Master and slaves can be from different fabrics */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+};
+
+static struct msm_bus_paths mdp_bus_scale_usecases[] = {
+ {
+ ARRAY_SIZE(mdp_init_vectors),
+ mdp_init_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+ {
+ ARRAY_SIZE(hdmi_as_primary_vectors),
+ hdmi_as_primary_vectors,
+ },
+};
+#else
+#ifdef CONFIG_FB_MSM_LCDC_DSUB
static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
/* Default case static display/UI/2d/3d if FB SMI */
{
@@ -9230,25 +9234,6 @@
};
#else
-static struct msm_bus_vectors mdp_init_vectors[] = {
- /* For now, 0th array entry is reserved.
- * Please leave 0 as is and don't use it
- */
- {
- .src = MSM_BUS_MASTER_MDP_PORT0,
- .dst = MSM_BUS_SLAVE_SMI,
- .ab = 0,
- .ib = 0,
- },
- /* Master and slaves can be from different fabrics */
- {
- .src = MSM_BUS_MASTER_MDP_PORT0,
- .dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = 0,
- .ib = 0,
- },
-};
-
static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
/* Default case static display/UI/2d/3d if FB SMI */
{
@@ -9359,6 +9344,7 @@
mdp_1080p_vectors,
},
};
+#endif
static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
mdp_bus_scale_usecases,
ARRAY_SIZE(mdp_bus_scale_usecases),
@@ -9385,6 +9371,26 @@
.ib = 0,
},
};
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+static struct msm_bus_vectors dtv_bus_def_vectors[] = {
+ /* For now, 0th array entry is reserved.
+ * Please leave 0 as is and don't use it
+ */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_SMI,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+ /* Master and slaves can be from different fabrics */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+};
+#else
static struct msm_bus_vectors dtv_bus_def_vectors[] = {
/* For now, 0th array entry is reserved.
* Please leave 0 as is and don't use it
@@ -9403,6 +9409,7 @@
.ib = 707616000,
},
};
+#endif
static struct msm_bus_paths dtv_bus_scale_usecases[] = {
{
ARRAY_SIZE(dtv_bus_init_vectors),
@@ -9543,6 +9550,13 @@
160000000,
200000000,
};
+#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
+int mdp_core_clk_rate_table[] = {
+ 200000000,
+ 200000000,
+ 200000000,
+ 200000000,
+};
#else
int mdp_core_clk_rate_table[] = {
59080000,
@@ -9554,7 +9568,11 @@
static struct msm_panel_common_pdata mdp_pdata = {
.gpio = MDP_VSYNC_GPIO,
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ .mdp_core_clk_rate = 200000000,
+#else
.mdp_core_clk_rate = 59080000,
+#endif
.mdp_core_clk_table = mdp_core_clk_rate_table,
.num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
#ifdef CONFIG_MSM_BUS_SCALING
@@ -10118,10 +10136,15 @@
* un-reworked SURF cannot resume from.
*/
if (machine_is_msm8x60_surf()) {
- rpm_vreg_init_pdata[RPM_VREG_ID_PM8901_L4]
- .init_data.constraints.always_on = 1;
- rpm_vreg_init_pdata[RPM_VREG_ID_PM8901_L6]
- .init_data.constraints.always_on = 1;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
+ if (rpm_regulator_init_data[i].id
+ == RPM_VREG_ID_PM8901_L4
+ || rpm_regulator_init_data[i].id
+ == RPM_VREG_ID_PM8901_L6)
+ rpm_regulator_init_data[i]
+ .init_data.constraints.always_on = 1;
}
/*
diff --git a/arch/arm/mach-msm/board-qrd7627a.c b/arch/arm/mach-msm/board-qrd7627a.c
index b09352c..b07ac00 100644
--- a/arch/arm/mach-msm/board-qrd7627a.c
+++ b/arch/arm/mach-msm/board-qrd7627a.c
@@ -13,7 +13,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio_event.h>
-#include <linux/usb/android_composite.h>
+#include <linux/usb/android.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
@@ -957,100 +957,8 @@
#endif
-static char *usb_functions_default[] = {
- "diag",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_default_adb[] = {
- "diag",
- "adb",
- "modem",
- "nmea",
- "rmnet",
- "usb_mass_storage",
-};
-
-static char *usb_functions_rndis[] = {
- "rndis",
-};
-
-static char *usb_functions_rndis_adb[] = {
- "rndis",
- "adb",
-};
-
-static char *usb_functions_all[] = {
-#ifdef CONFIG_USB_ANDROID_RNDIS
- "rndis",
-#endif
-#ifdef CONFIG_USB_ANDROID_DIAG
- "diag",
-#endif
- "adb",
-#ifdef CONFIG_USB_F_SERIAL
- "modem",
- "nmea",
-#endif
-#ifdef CONFIG_USB_ANDROID_RMNET
- "rmnet",
-#endif
- "usb_mass_storage",
-};
-
-static struct android_usb_product usb_products[] = {
- {
- .product_id = 0x9026,
- .num_functions = ARRAY_SIZE(usb_functions_default),
- .functions = usb_functions_default,
- },
- {
- .product_id = 0x9025,
- .num_functions = ARRAY_SIZE(usb_functions_default_adb),
- .functions = usb_functions_default_adb,
- },
- {
- .product_id = 0xf00e,
- .num_functions = ARRAY_SIZE(usb_functions_rndis),
- .functions = usb_functions_rndis,
- },
- {
- .product_id = 0x9024,
- .num_functions = ARRAY_SIZE(usb_functions_rndis_adb),
- .functions = usb_functions_rndis_adb,
- },
-};
-
-static struct usb_mass_storage_platform_data mass_storage_pdata = {
- .nluns = 1,
- .vendor = "Qualcomm Incorporated",
- .product = "Mass storage",
- .release = 0x0100,
-
-};
-
-static struct platform_device usb_mass_storage_device = {
- .name = "usb_mass_storage",
- .id = -1,
- .dev = {
- .platform_data = &mass_storage_pdata,
- },
-};
-
static struct android_usb_platform_data android_usb_pdata = {
- .vendor_id = 0x05C6,
- .product_id = 0x9026,
- .version = 0x0100,
- .product_name = "Qualcomm HSUSB Device",
- .manufacturer_name = "Qualcomm Incorporated",
- .num_products = ARRAY_SIZE(usb_products),
- .products = usb_products,
- .num_functions = ARRAY_SIZE(usb_functions_all),
- .functions = usb_functions_all,
- .serial_number = "1234567890ABCDEF",
+ .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
};
static struct platform_device android_usb_device = {
@@ -1061,38 +969,6 @@
},
};
-static struct usb_ether_platform_data rndis_pdata = {
- .vendorID = 0x05C6,
- .vendorDescr = "Qualcomm Incorporated",
-};
-
-static struct platform_device rndis_device = {
- .name = "rndis",
- .id = -1,
- .dev = {
- .platform_data = &rndis_pdata,
- },
-};
-
-static int __init board_serialno_setup(char *serialno)
-{
- int i;
- char *src = serialno;
-
- /* create a fake MAC address from our serial number.
- * first byte is 0x02 to signify locally administered.
- */
- rndis_pdata.ethaddr[0] = 0x02;
- for (i = 0; *src; i++) {
- /* XOR the USB serial across the remaining bytes */
- rndis_pdata.ethaddr[i % (ETH_ALEN - 1) + 1] ^= *src++;
- }
-
- android_usb_pdata.serial_number = serialno;
- return 1;
-}
-__setup("androidboot.serialno=", board_serialno_setup);
-
#ifdef CONFIG_USB_EHCI_MSM_72K
static void msm_hsusb_vbus_power(unsigned phy_info, int on)
{
@@ -1637,7 +1513,8 @@
SND(FM_DIGITAL_STEREO_HEADSET, 26),
SND(FM_DIGITAL_SPEAKER_PHONE, 27),
SND(FM_DIGITAL_BT_A2DP_HEADSET, 28),
- SND(CURRENT, 34),
+ SND(STEREO_HEADSET_AND_SPEAKER, 31),
+ SND(CURRENT, 0x7FFFFFFE),
SND(FM_ANALOG_STEREO_HEADSET, 35),
SND(FM_ANALOG_STEREO_HEADSET_CODEC, 36),
};
@@ -1824,10 +1701,6 @@
&android_usb_device,
&android_pmem_device,
&android_pmem_adsp_device,
- &usb_mass_storage_device,
- &rndis_device,
- &usb_diag_device,
- &usb_gadget_fserial_device,
&android_pmem_audio_device,
&msm_device_snd,
&msm_device_adspdec,
@@ -1993,4 +1866,5 @@
.init_machine = msm_qrd1_init,
.timer = &msm_timer,
.init_early = qrd7627a_init_early,
+ .handle_irq = vic_handle_irq,
MACHINE_END
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 5d7736f..50be14b 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2750,7 +2750,7 @@
{ CLK_LOOKUP("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL) },
{ CLK_LOOKUP("ebi1_mddi_clk", ebi_mddi_clk.c, NULL) },
{ CLK_LOOKUP("ebi1_tv_clk", ebi_tv_clk.c, NULL) },
- { CLK_LOOKUP("ebi1_vcd_clk", ebi_vcd_clk.c, NULL) },
+ { CLK_LOOKUP("mem_clk", ebi_vcd_clk.c, "msm_vidc.0") },
{ CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL) },
{ CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov") },
@@ -2850,10 +2850,10 @@
OWN(APPS3, 11, "csi_pclk", csi0_p_clk, NULL),
OWN(APPS3, 0, "mdp_clk", mdp_clk, NULL),
OWN(APPS3, 0, "core_clk", mdp_clk, "footswitch-pcom.4"),
- OWN(APPS3, 2, "mfc_clk", mfc_clk, NULL),
+ OWN(APPS3, 2, "core_clk", mfc_clk, "msm_vidc.0"),
OWN(APPS3, 2, "core_clk", mfc_clk, "footswitch-pcom.5"),
- OWN(APPS3, 2, "mfc_div2_clk", mfc_div2_clk, NULL),
- OWN(APPS3, 2, "mfc_pclk", mfc_p_clk, NULL),
+ OWN(APPS3, 2, "core_div2_clk", mfc_div2_clk, "msm_vidc.0"),
+ OWN(APPS3, 2, "iface_clk", mfc_p_clk, "msm_vidc.0"),
OWN(APPS3, 2, "iface_clk", mfc_p_clk, "footswitch-pcom.5"),
OWN(APPS3, 4, "vpe_clk", vpe_clk, NULL),
OWN(APPS3, 4, "core_clk", vpe_clk, "footswitch-pcom.9"),
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 9aa5700..734b1fe 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -297,6 +297,11 @@
#define LCC_PCM_MD_REG REG_LPA(0x0058)
#define LCC_PCM_NS_REG REG_LPA(0x0054)
#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
+#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
+#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
+#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
+#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
+#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
@@ -308,6 +313,7 @@
#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
+#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
@@ -326,7 +332,7 @@
#define pll0_to_mm_mux 3
#define pll15_to_mm_mux 3 /* or MM_PLL3 */
#define gnd_to_mm_mux 4
-#define pll3_to_mm_mux 5 /* used in 8960 */
+#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
#define hdmi_pll_to_mm_mux 3
#define cxo_to_xo_mux 0
#define pxo_to_xo_mux 1
@@ -4939,7 +4945,7 @@
CLK_LOOKUP("cxo", cxo_clk.c, NULL),
CLK_LOOKUP("pll2", pll2_clk.c, NULL),
CLK_LOOKUP("pll8", pll8_clk.c, NULL),
- CLK_DUMMY("pll4", PLL4, NULL, 0),
+ CLK_LOOKUP("pll4", pll4_clk.c, NULL),
CLK_LOOKUP("measure", measure_clk.c, "debug"),
CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
@@ -4982,12 +4988,12 @@
CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
- CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
- CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
- CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
+ CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
CLK_LOOKUP("ce_clk", ce1_core_clk.c, NULL),
CLK_LOOKUP("sata_phy_ref_clk", sata_phy_ref_clk.c, NULL),
@@ -5001,8 +5007,8 @@
CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
- CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
- CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
+ CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
+ CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
@@ -5098,17 +5104,18 @@
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
- CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
- CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
- CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
- CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
+ CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
+ CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
+ CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
+ CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
+ CLK_DUMMY("sps_slimbus_clk", SPS_SLIMBUS_CLK, NULL, OFF),
CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF),
CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
@@ -5190,6 +5197,8 @@
CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
+ CLK_LOOKUP("tsif_pclk", tsif_p_clk.c, NULL),
+ CLK_LOOKUP("tsif_ref_clk", tsif_ref_clk.c, NULL),
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
@@ -5297,7 +5306,7 @@
CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
- CLK_LOOKUP("vcodec_clk", vcodec_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
@@ -5338,7 +5347,7 @@
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
- CLK_LOOKUP("vcodec_pclk", vcodec_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
@@ -5445,13 +5454,19 @@
/* Deassert MM SW_RESET_ALL signal. */
writel_relaxed(0, SW_RESET_ALL_REG);
+ /*
+ * Some bits are only used on either 8960 or 8064 and are marked as
+ * reserved bits on the other SoC. Writing to these reserved bits
+ * should have no effect.
+ */
/* Initialize MM AHB registers: Enable the FPB clock and disable HW
* gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
* prevent its memory from being collapsed when the clock is halted.
* The sleep and wake-up delays are set to safe values. */
rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
writel_relaxed(0x000007F9, AHB_EN2_REG);
- rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
+ if (cpu_is_apq8064())
+ rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
/* Deassert all locally-owned MM AHB resets. */
rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
@@ -5465,7 +5480,8 @@
rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
- rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
+ if (cpu_is_apq8064())
+ rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
/* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
@@ -5477,22 +5493,26 @@
rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
- rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
- if (cpu_is_apq8064())
+ if (cpu_is_msm8960()) {
+ rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
+ rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
+ }
+ if (cpu_is_apq8064()) {
+ rmwreg(0x00000000, TV_CC_REG, 0x00004010);
rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
+ }
/*
* Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
@@ -5500,8 +5520,10 @@
* and wake-up value to max.
*/
rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
- rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ if (cpu_is_apq8064()) {
+ rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
+ rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
+ }
/* De-assert MM AXI resets to all hardware blocks. */
writel_relaxed(0, SW_RESET_AXI_REG);
@@ -5527,7 +5549,8 @@
writel_relaxed(BIT(15), PDM_CLK_NS_REG);
/* Source SLIMBus xo src from slimbus reference clock */
- writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
+ if (cpu_is_msm8960())
+ writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
/* Source the dsi_byte_clks from the DSI PHY PLLs */
rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
@@ -5671,6 +5694,33 @@
regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
regval |= BIT(12);
writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
+
+ /* Check if PLL4 is active */
+ is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
+ if (!is_pll_enabled) {
+ /* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
+ writel_relaxed(0x10, LCC_PLL0_L_VAL_REG);
+ writel_relaxed(0x130, LCC_PLL0_M_VAL_REG);
+ writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
+
+ regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
+
+ /* Enable the main output and the MN accumulator */
+ regval |= BIT(23) | BIT(22);
+
+ /* Set pre-divider and post-divider values to 1 and 1 */
+ regval &= ~BIT(19);
+ regval &= ~BM(21, 20);
+
+ /* Set VCO frequency */
+ regval &= ~BM(17, 16);
+ writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
+
+ set_fsm_mode(LCC_PLL0_MODE_REG);
+ }
+
+ /* Enable PLL4 source on the LPASS Primary PLL Mux */
+ writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
}
}
@@ -5744,13 +5794,18 @@
clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
/*
- * The halt status bits for PDM and TSSC may be incorrect at boot.
+ * The halt status bits for these clocks may be incorrect at boot.
* Toggle these clocks on and off to refresh them.
*/
rcg_clk_enable(&pdm_clk.c);
rcg_clk_disable(&pdm_clk.c);
rcg_clk_enable(&tssc_clk.c);
rcg_clk_disable(&tssc_clk.c);
+ if (cpu_is_msm8960() &&
+ SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
+ clk_enable(&usb_hsic_hsic_clk.c);
+ clk_disable(&usb_hsic_hsic_clk.c);
+ }
if (machine_is_msm8960_sim()) {
clk_set_rate(&sdc1_clk.c, 48000000);
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 4ca366f..1273198 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -3653,7 +3653,7 @@
CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
- CLK_LOOKUP("vcodec_clk", vcodec_clk.c, NULL),
+ CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
@@ -3699,7 +3699,7 @@
CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
- CLK_LOOKUP("vcodec_pclk", vcodec_p_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 96e626d..84121ef 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1524,7 +1524,7 @@
CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
- CLK_LOOKUP("prng_clk", prng_clk.c, NULL),
+ CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
CLK_LOOKUP("ce_pclk", ce1_p_clk.c, NULL),
@@ -1576,6 +1576,15 @@
CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
+ CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
+ CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
+
+ /* TODO: Make this real when RPM's ready. */
+ CLK_DUMMY("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL, OFF),
+ CLK_DUMMY("mem_clk", ebi1_adm_clk.c, "msm_dmov", OFF),
+
};
static void set_fsm_mode(void __iomem *mode_reg)
@@ -1666,9 +1675,36 @@
set_fsm_mode(SC_PLL0_MODE_REG);
- } else if (readl_relaxed(SC_PLL0_MODE_REG) & BIT(20))
+ } else if (!(readl_relaxed(SC_PLL0_MODE_REG) & BIT(20)))
WARN(1, "PLL9 enabled in non-FSM mode!\n");
+ /* Check if PLL14 is enabled in FSM mode */
+ is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
+
+ if (!is_pll_enabled) {
+ writel_relaxed(0x19, BB_PLL14_L_VAL_REG);
+ writel_relaxed(0x0, BB_PLL14_M_VAL_REG);
+ writel_relaxed(0x1, BB_PLL14_N_VAL_REG);
+
+ regval = readl_relaxed(BB_PLL14_CONFIG_REG);
+
+ /* Enable main output and the MN accumulator */
+ regval |= BIT(23) | BIT(22);
+
+ /* Set pre-divider and post-divider values to 1 and 1 */
+ regval &= ~BIT(19);
+ regval &= ~BM(21, 20);
+
+ /* Set VCO frequency */
+ regval &= ~BM(17, 16);
+
+ writel_relaxed(regval, BB_PLL14_CONFIG_REG);
+
+ set_fsm_mode(BB_PLL14_MODE_REG);
+
+ } else if (!(readl_relaxed(BB_PLL14_MODE_REG) & BIT(20)))
+ WARN(1, "PLL14 enabled in non-FSM mode!\n");
+
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regval = readl_relaxed(LCC_PRI_PLL_CLK_CTL_REG);
writel_relaxed(regval | BIT(0), LCC_PRI_PLL_CLK_CTL_REG);
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 637832d..2477221 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -190,7 +190,9 @@
cur_freq = acpuclk_get_rate(policy->cpu);
if (cpufreq_frequency_table_target(policy, table, cur_freq,
- CPUFREQ_RELATION_H, &index)) {
+ CPUFREQ_RELATION_H, &index) &&
+ cpufreq_frequency_table_target(policy, table, cur_freq,
+ CPUFREQ_RELATION_L, &index)) {
pr_info("cpufreq: cpu%d at invalid freq: %d\n",
policy->cpu, cur_freq);
return -EINVAL;
@@ -278,6 +280,11 @@
static SYSDEV_CLASS_ATTR(mfreq, 0200, NULL, store_mfreq);
+static struct freq_attr *msm_freq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
static struct cpufreq_driver msm_cpufreq_driver = {
/* lps calculations are handled here. */
.flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
@@ -285,6 +292,7 @@
.verify = msm_cpufreq_verify,
.target = msm_cpufreq_target,
.name = "msm",
+ .attr = msm_freq_attr,
};
static struct notifier_block msm_cpufreq_pm_notifier = {
diff --git a/arch/arm/mach-msm/devices-8064.c b/arch/arm/mach-msm/devices-8064.c
index 02b7569..99e8d23 100644
--- a/arch/arm/mach-msm/devices-8064.c
+++ b/arch/arm/mach-msm/devices-8064.c
@@ -549,6 +549,11 @@
.dev.platform_data = &msm_sps_pdata,
};
+struct platform_device msm_device_smd_apq8064 = {
+ .name = "msm_smd",
+ .id = -1,
+};
+
static struct clk_lookup msm_clocks_8064_dummy[] = {
CLK_DUMMY("pll2", PLL2, NULL, 0),
CLK_DUMMY("pll8", PLL8, NULL, 0),
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index cc1264d..b531dec 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -81,6 +81,9 @@
#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
#define MSM_PMIC_SSBI_SIZE SZ_4K
+#define MSM8960_HSUSB_PHYS 0x12500000
+#define MSM8960_HSUSB_SIZE SZ_4K
+
static struct resource resources_otg[] = {
{
.start = MSM8960_HSUSB_PHYS,
@@ -154,8 +157,8 @@
static struct resource resources_hsic_host[] = {
{
- .start = MSM_HSIC_PHYS,
- .end = MSM_HSIC_PHYS + MSM_HSIC_SIZE - 1,
+ .start = 0x12520000,
+ .end = 0x12520000 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
@@ -1284,7 +1287,7 @@
{
.clk_name = "rot_clk",
.clk_type = ROTATOR_CORE_CLK,
- .clk_rate = 160 * 1000 * 1000,
+ .clk_rate = 200 * 1000 * 1000,
},
{
.clk_name = "rotator_pclk",
@@ -1780,7 +1783,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 1200000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(1200),
},
};
@@ -1789,7 +1792,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 2048000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(2048),
},
};
@@ -1798,7 +1801,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 2656000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(2656),
},
};
@@ -1807,7 +1810,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 3968000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(3968),
},
};
@@ -1854,7 +1857,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 204800000U,
+ .ib = KGSL_CONVERT_TO_MBPS(1200),
},
};
@@ -1889,7 +1892,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 204800000U,
+ .ib = KGSL_CONVERT_TO_MBPS(1200),
},
};
diff --git a/arch/arm/mach-msm/devices-9615.c b/arch/arm/mach-msm/devices-9615.c
index d542b96..2e586c7 100644
--- a/arch/arm/mach-msm/devices-9615.c
+++ b/arch/arm/mach-msm/devices-9615.c
@@ -16,10 +16,12 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msm_tsens.h>
+#include <linux/dma-mapping.h>
#include <asm/hardware/gic.h>
#include <asm/mach/flash.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
+#include <mach/msm_hsusb.h>
#include <mach/irqs.h>
#include <mach/socinfo.h>
#include <mach/rpm.h>
@@ -69,6 +71,52 @@
.num_resources = ARRAY_SIZE(msm_dmov_resource),
};
+static struct resource resources_otg[] = {
+ {
+ .start = MSM9615_HSUSB_PHYS,
+ .end = MSM9615_HSUSB_PHYS + MSM9615_HSUSB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = USB1_HS_IRQ,
+ .end = USB1_HS_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_otg = {
+ .name = "msm_otg",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_otg),
+ .resource = resources_otg,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource resources_hsusb[] = {
+ {
+ .start = MSM9615_HSUSB_PHYS,
+ .end = MSM9615_HSUSB_PHYS + MSM9615_HSUSB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = USB1_HS_IRQ,
+ .end = USB1_HS_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device msm_device_gadget_peripheral = {
+ .name = "msm_hsusb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resources_hsusb),
+ .resource = resources_hsusb,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
static struct resource resources_uart_gsbi4[] = {
{
.start = GSBI4_UARTDM_IRQ,
@@ -257,6 +305,22 @@
.id = -1,
};
+#ifdef CONFIG_HW_RANDOM_MSM
+/* PRNG device */
+#define MSM_PRNG_PHYS 0x1A500000
+static struct resource rng_resources = {
+ .flags = IORESOURCE_MEM,
+ .start = MSM_PRNG_PHYS,
+ .end = MSM_PRNG_PHYS + SZ_512 - 1,
+};
+
+struct platform_device msm_device_rng = {
+ .name = "msm_rng",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &rng_resources,
+};
+#endif
#define MSM_SDC1_BASE 0x12180000
#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
diff --git a/arch/arm/mach-msm/devices-fsm9xxx.c b/arch/arm/mach-msm/devices-fsm9xxx.c
index 86f2e18..426be10 100644
--- a/arch/arm/mach-msm/devices-fsm9xxx.c
+++ b/arch/arm/mach-msm/devices-fsm9xxx.c
@@ -74,27 +74,26 @@
* SSBIs
*/
-#ifdef CONFIG_I2C_SSBI
-
-#define MSM_SSBI1_PHYS 0x94080000
-#define MSM_SSBI1_SIZE SZ_4K
-
-static struct resource msm_ssbi1_resources[] = {
+#ifdef CONFIG_MSM_SSBI
+#define MSM_SSBI1_PHYS 0x94080000
+#define MSM_SSBI_PMIC1_PHYS MSM_SSBI1_PHYS
+static struct resource msm_ssbi_pmic1_resources[] = {
{
- .name = "ssbi_base",
- .start = MSM_SSBI1_PHYS,
- .end = MSM_SSBI1_PHYS + MSM_SSBI1_SIZE - 1,
- .flags = IORESOURCE_MEM,
+ .start = MSM_SSBI_PMIC1_PHYS,
+ .end = MSM_SSBI_PMIC1_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
},
};
-struct platform_device msm_device_ssbi1 = {
- .name = "i2c_ssbi",
- .id = 0,
- .num_resources = ARRAY_SIZE(msm_ssbi1_resources),
- .resource = msm_ssbi1_resources,
+struct platform_device msm_device_ssbi_pmic1 = {
+ .name = "msm_ssbi",
+ .id = 0,
+ .resource = msm_ssbi_pmic1_resources,
+ .num_resources = ARRAY_SIZE(msm_ssbi_pmic1_resources),
};
+#endif
+#ifdef CONFIG_I2C_SSBI
#define MSM_SSBI2_PHYS 0x94090000
#define MSM_SSBI2_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index a945349..73c96fb 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -15,6 +15,9 @@
#include <linux/bootmem.h>
#include <mach/irqs.h>
#include <mach/iommu.h>
+#include <mach/socinfo.h>
+#include <mach/irqs-8960.h>
+#include <mach/irqs-8064.h>
static struct resource msm_iommu_jpegd_resources[] = {
{
@@ -226,6 +229,27 @@
},
};
+static struct resource msm_iommu_gfx3d1_resources[] = {
+ {
+ .start = 0x07D00000,
+ .end = 0x07D00000 + SZ_1M - 1,
+ .name = "physbase",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "nonsecure_irq",
+ .start = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
+ .end = SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "secure_irq",
+ .start = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
+ .end = SMMU_GFX3D1_CB_SC_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static struct resource msm_iommu_gfx2d0_resources[] = {
{
.start = 0x07D00000,
@@ -268,6 +292,27 @@
},
};
+static struct resource msm_iommu_vcap_resources[] = {
+ {
+ .start = 0x07200000,
+ .end = 0x07200000 + SZ_1M - 1,
+ .name = "physbase",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "nonsecure_irq",
+ .start = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
+ .end = SMMU_VCAP_CB_SC_NON_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "secure_irq",
+ .start = SMMU_VCAP_CB_SC_SECURE_IRQ,
+ .end = SMMU_VCAP_CB_SC_SECURE_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static struct platform_device msm_root_iommu_dev = {
.name = "msm_iommu",
.id = -1,
@@ -323,6 +368,11 @@
.ncb = 3,
};
+static struct msm_iommu_dev gfx3d1_iommu = {
+ .name = "gfx3d1",
+ .ncb = 3,
+};
+
static struct msm_iommu_dev gfx2d0_iommu = {
.name = "gfx2d0",
.ncb = 2,
@@ -333,6 +383,11 @@
.ncb = 2,
};
+static struct msm_iommu_dev vcap_iommu = {
+ .name = "vcap",
+ .ncb = 2,
+};
+
static struct platform_device msm_device_iommu_jpegd = {
.name = "msm_iommu",
.id = 0,
@@ -433,6 +488,16 @@
.resource = msm_iommu_gfx3d_resources,
};
+static struct platform_device msm_device_iommu_gfx3d1 = {
+ .name = "msm_iommu",
+ .id = 10,
+ .dev = {
+ .parent = &msm_root_iommu_dev.dev,
+ },
+ .num_resources = ARRAY_SIZE(msm_iommu_gfx3d1_resources),
+ .resource = msm_iommu_gfx3d1_resources,
+};
+
static struct platform_device msm_device_iommu_gfx2d0 = {
.name = "msm_iommu",
.id = 10,
@@ -443,7 +508,7 @@
.resource = msm_iommu_gfx2d0_resources,
};
-struct platform_device msm_device_iommu_gfx2d1 = {
+static struct platform_device msm_device_iommu_gfx2d1 = {
.name = "msm_iommu",
.id = 11,
.dev = {
@@ -453,6 +518,16 @@
.resource = msm_iommu_gfx2d1_resources,
};
+static struct platform_device msm_device_iommu_vcap = {
+ .name = "msm_iommu",
+ .id = 11,
+ .dev = {
+ .parent = &msm_root_iommu_dev.dev,
+ },
+ .num_resources = ARRAY_SIZE(msm_iommu_vcap_resources),
+ .resource = msm_iommu_vcap_resources,
+};
+
static struct msm_iommu_ctx_dev jpegd_src_ctx = {
.name = "jpegd_src",
.num = 0,
@@ -568,6 +643,19 @@
31, -1}
};
+static struct msm_iommu_ctx_dev gfx3d1_user_ctx = {
+ .name = "gfx3d1_user",
+ .num = 0,
+ .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
+};
+
+static struct msm_iommu_ctx_dev gfx3d1_priv_ctx = {
+ .name = "gfx3d1_priv",
+ .num = 1,
+ .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+ 31, -1}
+};
+
static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
.name = "gfx2d0_2d0",
.num = 0,
@@ -580,6 +668,18 @@
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
+static struct msm_iommu_ctx_dev vcap_vc_ctx = {
+ .name = "vcap_vc",
+ .num = 0,
+ .mids = {0, -1}
+};
+
+static struct msm_iommu_ctx_dev vcap_vp_ctx = {
+ .name = "vcap_vp",
+ .num = 1,
+ .mids = {1, -1}
+};
+
static struct platform_device msm_device_jpegd_src_ctx = {
.name = "msm_iommu_ctx",
.id = 0,
@@ -732,6 +832,22 @@
},
};
+static struct platform_device msm_device_gfx3d1_user_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 19,
+ .dev = {
+ .parent = &msm_device_iommu_gfx3d1.dev,
+ },
+};
+
+static struct platform_device msm_device_gfx3d1_priv_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 20,
+ .dev = {
+ .parent = &msm_device_iommu_gfx3d1.dev,
+ },
+};
+
static struct platform_device msm_device_gfx2d0_2d0_ctx = {
.name = "msm_iommu_ctx",
.id = 19,
@@ -748,7 +864,23 @@
},
};
-static struct platform_device *msm_iommu_devs[] = {
+static struct platform_device msm_device_vcap_vc_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 21,
+ .dev = {
+ .parent = &msm_device_iommu_vcap.dev,
+ },
+};
+
+static struct platform_device msm_device_vcap_vp_ctx = {
+ .name = "msm_iommu_ctx",
+ .id = 22,
+ .dev = {
+ .parent = &msm_device_iommu_vcap.dev,
+ },
+};
+
+static struct platform_device *msm_iommu_common_devs[] = {
&msm_device_iommu_jpegd,
&msm_device_iommu_vpe,
&msm_device_iommu_mdp0,
@@ -759,11 +891,19 @@
&msm_device_iommu_vcodec_a,
&msm_device_iommu_vcodec_b,
&msm_device_iommu_gfx3d,
+};
+
+static struct platform_device *msm_iommu_gfx2d_devs[] = {
&msm_device_iommu_gfx2d0,
&msm_device_iommu_gfx2d1,
};
-static struct msm_iommu_dev *msm_iommu_data[] = {
+static struct platform_device *msm_iommu_8064_devs[] = {
+ &msm_device_iommu_gfx3d1,
+ &msm_device_iommu_vcap,
+};
+
+static struct msm_iommu_dev *msm_iommu_common_data[] = {
&jpegd_iommu,
&vpe_iommu,
&mdp0_iommu,
@@ -774,11 +914,19 @@
&vcodec_a_iommu,
&vcodec_b_iommu,
&gfx3d_iommu,
+};
+
+static struct msm_iommu_dev *msm_iommu_gfx2d_data[] = {
&gfx2d0_iommu,
&gfx2d1_iommu,
};
-static struct platform_device *msm_iommu_ctx_devs[] = {
+static struct msm_iommu_dev *msm_iommu_8064_data[] = {
+ &gfx3d1_iommu,
+ &vcap_iommu,
+};
+
+static struct platform_device *msm_iommu_common_ctx_devs[] = {
&msm_device_jpegd_src_ctx,
&msm_device_jpegd_dst_ctx,
&msm_device_vpe_src_ctx,
@@ -798,11 +946,21 @@
&msm_device_vcodec_b_mm2_ctx,
&msm_device_gfx3d_user_ctx,
&msm_device_gfx3d_priv_ctx,
+};
+
+static struct platform_device *msm_iommu_gfx2d_ctx_devs[] = {
&msm_device_gfx2d0_2d0_ctx,
&msm_device_gfx2d1_2d1_ctx,
};
-static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
+static struct platform_device *msm_iommu_8064_ctx_devs[] = {
+ &msm_device_gfx3d1_user_ctx,
+ &msm_device_gfx3d1_priv_ctx,
+ &msm_device_vcap_vc_ctx,
+ &msm_device_vcap_vp_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_common_ctx_data[] = {
&jpegd_src_ctx,
&jpegd_dst_ctx,
&vpe_src_ctx,
@@ -822,31 +980,35 @@
&vcodec_b_mm2_ctx,
&gfx3d_user_ctx,
&gfx3d_priv_ctx,
+};
+
+static struct msm_iommu_ctx_dev *msm_iommu_gfx2d_ctx_data[] = {
&gfx2d0_2d0_ctx,
&gfx2d1_2d1_ctx,
};
-static int __init msm8x60_iommu_init(void)
+static struct msm_iommu_ctx_dev *msm_iommu_8064_ctx_data[] = {
+ &gfx3d1_user_ctx,
+ &gfx3d1_priv_ctx,
+ &vcap_vc_ctx,
+ &vcap_vp_ctx,
+};
+
+static int iommu_init_devs(struct platform_device *devs[],
+ struct msm_iommu_dev *data[], int size)
{
int ret, i;
- ret = platform_device_register(&msm_root_iommu_dev);
- if (ret != 0) {
- pr_err("Failed to register root IOMMU device!\n");
- goto failure;
- }
-
- for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
- ret = platform_device_add_data(msm_iommu_devs[i],
- msm_iommu_data[i],
- sizeof(struct msm_iommu_dev));
+ for (i = 0; i < size; i++) {
+ ret = platform_device_add_data(devs[i],
+ data[i], sizeof(struct msm_iommu_dev));
if (ret != 0) {
pr_err("platform_device_add_data failed, "
"i = %d\n", i);
goto failure_unwind;
}
- ret = platform_device_register(msm_iommu_devs[i]);
+ ret = platform_device_register(devs[i]);
if (ret != 0) {
pr_err("platform_device_register iommu failed, "
@@ -854,53 +1016,139 @@
goto failure_unwind;
}
}
+ return 0;
- for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
- ret = platform_device_add_data(msm_iommu_ctx_devs[i],
- msm_iommu_ctx_data[i],
- sizeof(*msm_iommu_ctx_devs[i]));
+failure_unwind:
+ while (--i >= 0)
+ platform_device_unregister(devs[i]);
+
+ return ret;
+}
+
+
+static int iommu_init_ctx_devs(struct platform_device *ctx_devs[],
+ struct msm_iommu_ctx_dev *ctx_data[], int size)
+{
+ int ret, i;
+
+ for (i = 0; i < size; i++) {
+ ret = platform_device_add_data(ctx_devs[i],
+ ctx_data[i], sizeof(struct msm_iommu_ctx_dev));
if (ret != 0) {
pr_err("platform_device_add_data iommu failed, "
"i = %d\n", i);
- goto failure_unwind2;
+ goto failure_unwind;
}
- ret = platform_device_register(msm_iommu_ctx_devs[i]);
+ ret = platform_device_register(ctx_devs[i]);
if (ret != 0) {
pr_err("platform_device_register ctx failed, "
"i = %d\n", i);
- goto failure_unwind2;
+ goto failure_unwind;
}
}
return 0;
-failure_unwind2:
- while (--i >= 0)
- platform_device_unregister(msm_iommu_ctx_devs[i]);
failure_unwind:
while (--i >= 0)
- platform_device_unregister(msm_iommu_devs[i]);
+ platform_device_unregister(ctx_devs[i]);
+ return ret;
+}
+
+static int __init iommu_init(void)
+{
+ int ret;
+
+ ret = platform_device_register(&msm_root_iommu_dev);
+ if (ret != 0) {
+ pr_err("Failed to register root IOMMU device!\n");
+ goto failure;
+ }
+
+ /* Initialize common devs */
+ ret = iommu_init_devs(msm_iommu_common_devs,
+ msm_iommu_common_data,
+ ARRAY_SIZE(msm_iommu_common_devs));
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize soc-specific devs */
+ if (cpu_is_apq8064()) {
+ ret = iommu_init_devs(msm_iommu_8064_devs,
+ msm_iommu_8064_data,
+ ARRAY_SIZE(msm_iommu_8064_devs));
+ } else {
+ ret = iommu_init_devs(msm_iommu_gfx2d_devs,
+ msm_iommu_gfx2d_data,
+ ARRAY_SIZE(msm_iommu_gfx2d_devs));
+ }
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize common ctx_devs */
+ ret = iommu_init_ctx_devs(msm_iommu_common_ctx_devs,
+ msm_iommu_common_ctx_data,
+ ARRAY_SIZE(msm_iommu_common_ctx_devs));
+ if (ret != 0)
+ goto failure2;
+
+ /* Initialize soc-specific ctx_devs */
+ if (cpu_is_apq8064()) {
+ ret = iommu_init_ctx_devs(msm_iommu_8064_ctx_devs,
+ msm_iommu_8064_ctx_data,
+ ARRAY_SIZE(msm_iommu_8064_ctx_devs));
+ } else {
+ ret = iommu_init_ctx_devs(msm_iommu_gfx2d_ctx_devs,
+ msm_iommu_gfx2d_ctx_data,
+ ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs));
+ }
+ if (ret != 0)
+ goto failure2;
+
+ return 0;
+
+failure2:
platform_device_unregister(&msm_root_iommu_dev);
failure:
return ret;
}
-static void __exit msm8x60_iommu_exit(void)
+static void __exit iommu_exit(void)
{
int i;
- for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
- platform_device_unregister(msm_iommu_ctx_devs[i]);
+ /* Common ctx_devs */
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_common_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_common_ctx_devs[i]);
- for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
- platform_device_unregister(msm_iommu_devs[i]);
+ /* soc-specific ctx_devs. */
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_8064_ctx_devs[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_ctx_devs); i++)
+ platform_device_unregister(msm_iommu_gfx2d_ctx_devs[i]);
+ }
+
+ /* Common devs. */
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_common_devs); ++i)
+ platform_device_unregister(msm_iommu_common_devs[i]);
+
+ /* soc-specific devs. */
+ if (cpu_is_apq8064()) {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_8064_devs); i++)
+ platform_device_unregister(msm_iommu_8064_devs[i]);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm_iommu_gfx2d_devs); i++)
+ platform_device_unregister(msm_iommu_gfx2d_devs[i]);
+ }
platform_device_unregister(&msm_root_iommu_dev);
}
-subsys_initcall(msm8x60_iommu_init);
-module_exit(msm8x60_iommu_exit);
+subsys_initcall(iommu_init);
+module_exit(iommu_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-msm7x27.c b/arch/arm/mach-msm/devices-msm7x27.c
index 250cbad..3772884 100644
--- a/arch/arm/mach-msm/devices-msm7x27.c
+++ b/arch/arm/mach-msm/devices-msm7x27.c
@@ -33,7 +33,6 @@
#include <asm/mach/mmc.h>
#include <mach/msm_hsusb.h>
#include <mach/usbdiag.h>
-#include <mach/usb_gadget_fserial.h>
#include <mach/rpc_hsusb.h>
static struct resource resources_uart1[] = {
@@ -299,35 +298,6 @@
return platform_device_register(pdev);
}
-#ifdef CONFIG_USB_ANDROID_DIAG
-struct usb_diag_platform_data usb_diag_pdata = {
- .ch_name = DIAG_LEGACY,
- .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
-};
-
-struct platform_device usb_diag_device = {
- .name = "usb_diag",
- .id = -1,
- .dev = {
- .platform_data = &usb_diag_pdata,
- },
-};
-#endif
-
-#ifdef CONFIG_USB_F_SERIAL
-static struct usb_gadget_fserial_platform_data fserial_pdata = {
- .no_ports = 2,
-};
-
-struct platform_device usb_gadget_fserial_device = {
- .name = "usb_fserial",
- .id = -1,
- .dev = {
- .platform_data = &fserial_pdata,
- },
-};
-#endif
-
struct platform_device asoc_msm_pcm = {
.name = "msm-dsp-audio",
.id = 0,
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 0da9de3..d7832a3 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -309,24 +309,25 @@
.resource = resources_qup,
};
-#ifdef CONFIG_I2C_SSBI
-#define MSM_SSBI6_PHYS 0xAD900000
-static struct resource msm_ssbi6_resources[] = {
+#ifdef CONFIG_MSM_SSBI
+#define MSM_SSBI_PMIC1_PHYS 0xAD900000
+static struct resource msm_ssbi_pmic1_resources[] = {
{
- .name = "ssbi_base",
- .start = MSM_SSBI6_PHYS,
- .end = MSM_SSBI6_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
+ .start = MSM_SSBI_PMIC1_PHYS,
+ .end = MSM_SSBI_PMIC1_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
},
};
-struct platform_device msm_device_ssbi6 = {
- .name = "i2c_ssbi",
- .id = 6,
- .num_resources = ARRAY_SIZE(msm_ssbi6_resources),
- .resource = msm_ssbi6_resources,
+struct platform_device msm_device_ssbi_pmic1 = {
+ .name = "msm_ssbi",
+ .id = 0,
+ .resource = msm_ssbi_pmic1_resources,
+ .num_resources = ARRAY_SIZE(msm_ssbi_pmic1_resources),
};
+#endif
+#ifdef CONFIG_I2C_SSBI
#define MSM_SSBI7_PHYS 0xAC800000
static struct resource msm_ssbi7_resources[] = {
{
diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c
index 8280aa0..445f1d4 100644
--- a/arch/arm/mach-msm/devices-msm8x60.c
+++ b/arch/arm/mach-msm/devices-msm8x60.c
@@ -489,7 +489,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 990000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(990),
},
};
@@ -498,7 +498,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 1300000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(1300),
},
};
@@ -507,7 +507,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 2008000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(2008),
},
};
@@ -516,7 +516,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 2484000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(2484),
},
};
@@ -527,7 +527,7 @@
},
{
ARRAY_SIZE(grp3d_low_vectors),
- grp3d_init_vectors,
+ grp3d_low_vectors,
},
{
ARRAY_SIZE(grp3d_nominal_low_vectors),
@@ -563,7 +563,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 990000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(990),
},
};
@@ -598,7 +598,7 @@
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = 990000000U,
+ .ib = KGSL_CONVERT_TO_MBPS(990),
},
};
@@ -878,25 +878,25 @@
.resource = gsbi12_qup_i2c_resources,
};
-#ifdef CONFIG_I2C_SSBI
-/* 8058 PMIC SSBI on /dev/i2c-6 */
-#define MSM_SSBI1_PMIC1C_PHYS 0x00500000
-static struct resource msm_ssbi1_resources[] = {
+#ifdef CONFIG_MSM_SSBI
+#define MSM_SSBI_PMIC1_PHYS 0x00500000
+static struct resource resources_ssbi_pmic1_resource[] = {
{
- .name = "ssbi_base",
- .start = MSM_SSBI1_PMIC1C_PHYS,
- .end = MSM_SSBI1_PMIC1C_PHYS + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
+ .start = MSM_SSBI_PMIC1_PHYS,
+ .end = MSM_SSBI_PMIC1_PHYS + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
},
};
-struct platform_device msm_device_ssbi1 = {
- .name = "i2c_ssbi",
- .id = MSM_SSBI1_I2C_BUS_ID,
- .num_resources = ARRAY_SIZE(msm_ssbi1_resources),
- .resource = msm_ssbi1_resources,
+struct platform_device msm_device_ssbi_pmic1 = {
+ .name = "msm_ssbi",
+ .id = 0,
+ .resource = resources_ssbi_pmic1_resource,
+ .num_resources = ARRAY_SIZE(resources_ssbi_pmic1_resource),
};
+#endif
+#ifdef CONFIG_I2C_SSBI
/* 8901 PMIC SSBI on /dev/i2c-7 */
#define MSM_SSBI2_PMIC2B_PHYS 0x00C00000
static struct resource msm_ssbi2_resources[] = {
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index d5cad07..1ebc2a7 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -112,6 +112,7 @@
extern struct platform_device msm_device_sps_apq8064;
extern struct platform_device msm_device_bam_dmux;
extern struct platform_device msm_device_smd;
+extern struct platform_device msm_device_smd_apq8064;
extern struct platform_device msm_device_dmov;
extern struct platform_device msm8960_device_dmov;
extern struct platform_device apq8064_device_dmov;
@@ -127,6 +128,7 @@
extern struct platform_device msm_device_tsif[2];
+extern struct platform_device msm_device_ssbi_pmic1;
extern struct platform_device msm_device_ssbi1;
extern struct platform_device msm_device_ssbi2;
extern struct platform_device msm_device_ssbi3;
@@ -190,4 +192,5 @@
extern struct platform_device ion_dev;
extern struct platform_device msm_rpm_device;
+extern struct platform_device msm_device_rng;
#endif
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index df6a64c..349b2d0 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -419,6 +419,7 @@
void __init msm_map_msm7x30_io(void);
void __init msm_map_fsm9xxx_io(void);
void __init msm_init_irq(void);
+void vic_handle_irq(struct pt_regs *regs);
struct mmc_platform_data;
int __init msm_add_sdcc(unsigned int controller,
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index 0d1da49..1b6497d 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -543,7 +543,10 @@
CAMIO_CSI1_SRC_CLK,
CAMIO_CSI_PIX_CLK,
+ CAMIO_CSI_PIX1_CLK,
CAMIO_CSI_RDI_CLK,
+ CAMIO_CSI_RDI1_CLK,
+ CAMIO_CSI_RDI2_CLK,
CAMIO_CSIPHY0_TIMER_CLK,
CAMIO_CSIPHY1_TIMER_CLK,
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index eb5921f..d384366 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -10,11 +10,15 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#if defined(CONFIG_MSM_VIC)
+#if defined(CONFIG_MSM_VIC) && !defined(CONFIG_MULTI_IRQ_HANDLER)
#include <mach/entry-macro-vic.S>
#elif defined(CONFIG_ARM_GIC)
#include <mach/entry-macro-qgic.S>
#else
-#error "No interrupt controller selected!"
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8064.h b/arch/arm/mach-msm/include/mach/irqs-8064.h
index 97657ea..8597111 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8064.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8064.h
@@ -280,7 +280,7 @@
#define CS3_BAM_XPU_IRQ (GIC_SPI_START + 234)
#define CE3_IRQ (GIC_SPI_START + 235)
#define SMMU_VCAP_CB_SC_SECURE_IRQ (GIC_SPI_START + 236)
-#define SMMU_VCAM_CP_SC_NON_SECURE_IRQ (GIC_SPI_START + 237)
+#define SMMU_VCAP_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 237)
#define PCIE20_INT_MSI (GIC_SPI_START + 238)
#define PCIE20_INTA (GIC_SPI_START + 239)
#define PCIE20_INTB (GIC_SPI_START + 240)
@@ -299,13 +299,14 @@
#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
/* smd/smsm interrupts */
-#define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0
-#define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1
-#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
-#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
-#define INT_DSPS_A11 SPS_MTI_31
-#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
-#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
+#define INT_A9_M2A_0 (GIC_SPI_START + 37) /*GSS_TO_APPS_IRQ_0*/
+#define INT_A9_M2A_5 (GIC_SPI_START + 38) /*GSS_TO_APPS_IRQ_1*/
+#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
+#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
+#define INT_DSPS_A11 SPS_MTI_31
+#define INT_DSPS_A11_SMSM SPS_MTI_30
+#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
+#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
index 6d121f9..dae0f47 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -273,14 +273,14 @@
#define INT_ADM_AARM ADM_0_SCSS_0_IRQ
/* smd/smsm interrupts */
-#define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0
-#define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1
-#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
-#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
-#define INT_DSPS_A11 SPS_MTI_31
-#define INT_DSPS_A11_SMSM SPS_MTI_30
-#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
-#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
+#define INT_A9_M2A_0 (GIC_SPI_START + 37) /*MSS_TO_APPS_IRQ_0*/
+#define INT_A9_M2A_5 (GIC_SPI_START + 38) /*MSS_TO_APPS_IRQ_1*/
+#define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ
+#define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ
+#define INT_DSPS_A11 SPS_MTI_31
+#define INT_DSPS_A11_SMSM SPS_MTI_30
+#define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ
+#define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_bus_board.h b/arch/arm/mach-msm/include/mach/msm_bus_board.h
index add2836..644e1b1 100644
--- a/arch/arm/mach-msm/include/mach/msm_bus_board.h
+++ b/arch/arm/mach-msm/include/mach/msm_bus_board.h
@@ -35,6 +35,7 @@
const unsigned int nmasters;
const unsigned int nslaves;
const unsigned int ntieredslaves;
+ bool il_flag;
};
enum msm_bus_bw_tier_type {
@@ -59,6 +60,7 @@
*fabreg, int fabid);
int msm_bus_board_get_iid(int id);
void msm_bus_rpm_set_mt_mask(void);
+int msm_bus_board_rpm_get_il_ids(uint16_t *id);
/*
* These macros specify the convention followed for allocating
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index e6b7beb..56cbd2f 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -98,12 +98,6 @@
#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
-#define MSM8960_HSUSB_PHYS 0x12500000
-#define MSM8960_HSUSB_SIZE SZ_4K
-
-#define MSM_HSIC_PHYS 0x12520000
-#define MSM_HSIC_SIZE SZ_4K
-
#define MSM8960_HDMI_PHYS 0x04A00000
#define MSM8960_HDMI_SIZE SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-9615.h b/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
index bbc25fd..e842f8e 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-9615.h
@@ -83,4 +83,7 @@
#define MSM9615_QFPROM_PHYS 0x00700000
#define MSM9615_QFPROM_SIZE SZ_4K
+#define MSM9615_IMEM_PHYS 0x2B000000
+#define MSM9615_IMEM_SIZE SZ_4K
+
#endif
diff --git a/arch/arm/mach-msm/include/mach/restart.h b/arch/arm/mach-msm/include/mach/restart.h
index 3deeeaf..84df9bc 100644
--- a/arch/arm/mach-msm/include/mach/restart.h
+++ b/arch/arm/mach-msm/include/mach/restart.h
@@ -17,7 +17,7 @@
#define RESTART_NORMAL 0x0
#define RESTART_DLOAD 0x1
-#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
+#ifdef CONFIG_MSM_NATIVE_RESTART
void msm_set_restart_mode(int mode);
#else
#define msm_set_restart_mode(mode)
diff --git a/arch/arm/mach-msm/include/mach/rpm-8960.h b/arch/arm/mach-msm/include/mach/rpm-8960.h
index bee47a5..d5ebba0 100644
--- a/arch/arm/mach-msm/include/mach/rpm-8960.h
+++ b/arch/arm/mach-msm/include/mach/rpm-8960.h
@@ -440,8 +440,10 @@
MSM_RPM_STATUS_ID_HDMI_SWITCH = 120,
MSM_RPM_STATUS_ID_DDR_DMM_0 = 121,
MSM_RPM_STATUS_ID_DDR_DMM_1 = 122,
+ MSM_RPM_STATUS_ID_EBI1_CH0_RANGE = 123,
+ MSM_RPM_STATUS_ID_EBI1_CH1_RANGE = 124,
- MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_DDR_DMM_1
+ MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_EBI1_CH1_RANGE,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8960_H */
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator-8660.h b/arch/arm/mach-msm/include/mach/rpm-regulator-8660.h
index 3bcebd4..85dcd89 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator-8660.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator-8660.h
@@ -11,67 +11,61 @@
* GNU General Public License for more details.
*/
-#ifndef __ARCH_ARM_MACH_MSM_RPM_REGULATOR_8660_H
-#define __ARCH_ARM_MACH_MSM_RPM_REGULATOR_8660_H
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
-#define RPM_VREG_PIN_CTRL_NONE 0x00
-#define RPM_VREG_PIN_CTRL_A0 0x01
-#define RPM_VREG_PIN_CTRL_A1 0x02
-#define RPM_VREG_PIN_CTRL_D0 0x04
-#define RPM_VREG_PIN_CTRL_D1 0x08
+#define RPM_VREG_PIN_CTRL_PM8058_A0 0x01
+#define RPM_VREG_PIN_CTRL_PM8058_A1 0x02
+#define RPM_VREG_PIN_CTRL_PM8058_D0 0x04
+#define RPM_VREG_PIN_CTRL_PM8058_D1 0x08
-/*
- * Pin Function
- * ENABLE - pin control switches between disable and enable
- * MODE - pin control switches between LPM and HPM
- * SLEEP_B - regulator is forced into LPM by asserting sleep_b signal
- * NONE - do not use pin control
+#define RPM_VREG_PIN_CTRL_PM8901_A0 0x01
+#define RPM_VREG_PIN_CTRL_PM8901_A1 0x02
+#define RPM_VREG_PIN_CTRL_PM8901_D0 0x04
+#define RPM_VREG_PIN_CTRL_PM8901_D1 0x08
+
+
+/**
+ * enum rpm_vreg_pin_fn_8660 - RPM regulator pin function choices
+ * %RPM_VREG_PIN_FN_8660_ENABLE: pin control switches between disable and
+ * enable
+ * %RPM_VREG_PIN_FN_8660_MODE: pin control switches between LPM and HPM
+ * %RPM_VREG_PIN_FN_8660_SLEEP_B: regulator is forced into LPM when
+ * sleep_b signal is asserted
+ * %RPM_VREG_PIN_FN_8660_NONE: do not use pin control for the regulator
+ * and do not allow another master to
+ * request pin control
*
* The pin function specified in platform data corresponds to the active state
* pin function value. Pin function will be NONE until a consumer requests
- * pin control with regulator_set_mode(vreg, REGULATOR_MODE_IDLE).
+ * pin control to be enabled.
*/
-enum rpm_vreg_pin_fn {
- RPM_VREG_PIN_FN_ENABLE = 0,
- RPM_VREG_PIN_FN_MODE,
- RPM_VREG_PIN_FN_SLEEP_B,
- RPM_VREG_PIN_FN_NONE,
+enum rpm_vreg_pin_fn_8660 {
+ RPM_VREG_PIN_FN_8660_ENABLE = 0,
+ RPM_VREG_PIN_FN_8660_MODE,
+ RPM_VREG_PIN_FN_8660_SLEEP_B,
+ RPM_VREG_PIN_FN_8660_NONE,
};
-enum rpm_vreg_mode {
- RPM_VREG_MODE_PIN_CTRL = 0,
- RPM_VREG_MODE_NONE = 0,
- RPM_VREG_MODE_LPM,
- RPM_VREG_MODE_HPM,
+/**
+ * enum rpm_vreg_force_mode_8660 - RPM regulator force mode choices
+ * %RPM_VREG_FORCE_MODE_8660_PIN_CTRL: allow pin control usage
+ * %RPM_VREG_FORCE_MODE_8660_NONE: do not force any mode
+ * %RPM_VREG_FORCE_MODE_8660_LPM: force into low power mode
+ * %RPM_VREG_FORCE_MODE_8660_HPM: force into high power mode
+ *
+ * Force mode is used to override aggregation with other masters and to set
+ * special operating modes.
+ */
+enum rpm_vreg_force_mode_8660 {
+ RPM_VREG_FORCE_MODE_8660_PIN_CTRL = 0,
+ RPM_VREG_FORCE_MODE_8660_NONE = 0,
+ RPM_VREG_FORCE_MODE_8660_LPM,
+ RPM_VREG_FORCE_MODE_8660_HPM,
};
-enum rpm_vreg_state {
- RPM_VREG_STATE_OFF = 0,
- RPM_VREG_STATE_ON,
-};
-
-enum rpm_vreg_freq {
- RPM_VREG_FREQ_NONE,
- RPM_VREG_FREQ_19p20,
- RPM_VREG_FREQ_9p60,
- RPM_VREG_FREQ_6p40,
- RPM_VREG_FREQ_4p80,
- RPM_VREG_FREQ_3p84,
- RPM_VREG_FREQ_3p20,
- RPM_VREG_FREQ_2p74,
- RPM_VREG_FREQ_2p40,
- RPM_VREG_FREQ_2p13,
- RPM_VREG_FREQ_1p92,
- RPM_VREG_FREQ_1p75,
- RPM_VREG_FREQ_1p60,
- RPM_VREG_FREQ_1p48,
- RPM_VREG_FREQ_1p37,
- RPM_VREG_FREQ_1p28,
- RPM_VREG_FREQ_1p20,
-};
-
-enum rpm_vreg_id {
- RPM_VREG_ID_PM8058_L0 = 0,
+enum rpm_vreg_id_8660 {
+ RPM_VREG_ID_PM8058_L0,
RPM_VREG_ID_PM8058_L1,
RPM_VREG_ID_PM8058_L2,
RPM_VREG_ID_PM8058_L3,
@@ -122,55 +116,68 @@
RPM_VREG_ID_PM8901_LVS2,
RPM_VREG_ID_PM8901_LVS3,
RPM_VREG_ID_PM8901_MVS0,
- RPM_VREG_ID_MAX,
+ RPM_VREG_ID_8660_MAX_REAL = RPM_VREG_ID_PM8901_MVS0,
+
+ /* The following are IDs for regulator devices to enable pin control. */
+ RPM_VREG_ID_PM8058_L0_PC,
+ RPM_VREG_ID_PM8058_L1_PC,
+ RPM_VREG_ID_PM8058_L2_PC,
+ RPM_VREG_ID_PM8058_L3_PC,
+ RPM_VREG_ID_PM8058_L4_PC,
+ RPM_VREG_ID_PM8058_L5_PC,
+ RPM_VREG_ID_PM8058_L6_PC,
+ RPM_VREG_ID_PM8058_L7_PC,
+ RPM_VREG_ID_PM8058_L8_PC,
+ RPM_VREG_ID_PM8058_L9_PC,
+ RPM_VREG_ID_PM8058_L10_PC,
+ RPM_VREG_ID_PM8058_L11_PC,
+ RPM_VREG_ID_PM8058_L12_PC,
+ RPM_VREG_ID_PM8058_L13_PC,
+ RPM_VREG_ID_PM8058_L14_PC,
+ RPM_VREG_ID_PM8058_L15_PC,
+ RPM_VREG_ID_PM8058_L16_PC,
+ RPM_VREG_ID_PM8058_L17_PC,
+ RPM_VREG_ID_PM8058_L18_PC,
+ RPM_VREG_ID_PM8058_L19_PC,
+ RPM_VREG_ID_PM8058_L20_PC,
+ RPM_VREG_ID_PM8058_L21_PC,
+ RPM_VREG_ID_PM8058_L22_PC,
+ RPM_VREG_ID_PM8058_L23_PC,
+ RPM_VREG_ID_PM8058_L24_PC,
+ RPM_VREG_ID_PM8058_L25_PC,
+ RPM_VREG_ID_PM8058_S0_PC,
+ RPM_VREG_ID_PM8058_S1_PC,
+ RPM_VREG_ID_PM8058_S2_PC,
+ RPM_VREG_ID_PM8058_S3_PC,
+ RPM_VREG_ID_PM8058_S4_PC,
+ RPM_VREG_ID_PM8058_LVS0_PC,
+ RPM_VREG_ID_PM8058_LVS1_PC,
+
+ RPM_VREG_ID_PM8901_L0_PC,
+ RPM_VREG_ID_PM8901_L1_PC,
+ RPM_VREG_ID_PM8901_L2_PC,
+ RPM_VREG_ID_PM8901_L3_PC,
+ RPM_VREG_ID_PM8901_L4_PC,
+ RPM_VREG_ID_PM8901_L5_PC,
+ RPM_VREG_ID_PM8901_L6_PC,
+ RPM_VREG_ID_PM8901_S0_PC,
+ RPM_VREG_ID_PM8901_S1_PC,
+ RPM_VREG_ID_PM8901_S2_PC,
+ RPM_VREG_ID_PM8901_S3_PC,
+ RPM_VREG_ID_PM8901_S4_PC,
+ RPM_VREG_ID_PM8901_LVS0_PC,
+ RPM_VREG_ID_PM8901_LVS1_PC,
+ RPM_VREG_ID_PM8901_LVS2_PC,
+ RPM_VREG_ID_PM8901_LVS3_PC,
+ RPM_VREG_ID_PM8901_MVS0_PC,
+ RPM_VREG_ID_8660_MAX = RPM_VREG_ID_PM8901_MVS0_PC,
};
/* Minimum high power mode loads in uA. */
-#define RPM_VREG_LDO_50_HPM_MIN_LOAD 5000
-#define RPM_VREG_LDO_150_HPM_MIN_LOAD 10000
-#define RPM_VREG_LDO_300_HPM_MIN_LOAD 10000
-#define RPM_VREG_SMPS_HPM_MIN_LOAD 50000
-#define RPM_VREG_FTSMPS_HPM_MIN_LOAD 100000
-
-/*
- * default_uV = initial voltage to set the regulator to if enable is called
- * before set_voltage (e.g. when boot_on or always_on is set).
- * peak_uA = initial load requirement sent in RPM request; used to determine
- * initial mode.
- * avg_uA = initial avg load requirement sent in RPM request; overwritten
- * along with peak_uA when regulator_set_mode or
- * regulator_set_optimum_mode is called.
- * pin_fn = RPM_VREG_PIN_FN_ENABLE - pin control ON/OFF
- * = RPM_VREG_PIN_FN_MODE - pin control LPM/HPM
- * = RPM_VREG_PIN_FN_SLEEP_B - regulator is forced into LPM by
- * asserting sleep_b signal
- * = RPM_VREG_PIN_FN_NONE - do not use pin control
- * mode = used to specify a force mode which overrides the votes of other
- * RPM masters.
- * state = initial state sent in RPM request.
- * sleep_selectable = flag which indicates that regulator should be accessable
- * by external private API and that spinlocks should be used.
- */
-struct rpm_vreg_pdata {
- struct regulator_init_data init_data;
- int default_uV;
- unsigned peak_uA;
- unsigned avg_uA;
- unsigned pull_down_enable;
- unsigned pin_ctrl;
- enum rpm_vreg_freq freq;
- enum rpm_vreg_pin_fn pin_fn;
- enum rpm_vreg_mode mode;
- enum rpm_vreg_state state;
- int sleep_selectable;
-};
-
-enum rpm_vreg_voter {
- RPM_VREG_VOTER_REG_FRAMEWORK = 0, /* for internal use only */
- RPM_VREG_VOTER1, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER2, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER3, /* for use by other drivers */
- RPM_VREG_VOTER_COUNT,
-};
+#define RPM_VREG_8660_LDO_50_HPM_MIN_LOAD 5000
+#define RPM_VREG_8660_LDO_150_HPM_MIN_LOAD 10000
+#define RPM_VREG_8660_LDO_300_HPM_MIN_LOAD 10000
+#define RPM_VREG_8660_SMPS_HPM_MIN_LOAD 50000
+#define RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD 100000
#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator-8960.h b/arch/arm/mach-msm/include/mach/rpm-regulator-8960.h
index de7571b..6de47bd 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator-8960.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator-8960.h
@@ -11,118 +11,83 @@
* GNU General Public License for more details.
*/
-#ifndef __ARCH_ARM_MACH_MSM_RPM_REGULATOR_8960_H
-#define __ARCH_ARM_MACH_MSM_RPM_REGULATOR_8960_H
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8960_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8960_H
/* Pin control input signals. */
-#define RPM_VREG_PIN_CTRL_NONE 0x00
-#define RPM_VREG_PIN_CTRL_EN0 0x01
-#define RPM_VREG_PIN_CTRL_EN1 0x02
-#define RPM_VREG_PIN_CTRL_EN2 0x04
-#define RPM_VREG_PIN_CTRL_EN3 0x08
-#define RPM_VREG_PIN_CTRL_ALL 0x0F
-
-#define RPM_VREG_PIN_CTRL_PM8921_D1 RPM_VREG_PIN_CTRL_EN0
-#define RPM_VREG_PIN_CTRL_PM8921_A0 RPM_VREG_PIN_CTRL_EN1
-#define RPM_VREG_PIN_CTRL_PM8921_A1 RPM_VREG_PIN_CTRL_EN2
-#define RPM_VREG_PIN_CTRL_PM8921_A2 RPM_VREG_PIN_CTRL_EN3
+#define RPM_VREG_PIN_CTRL_PM8921_D1 0x01
+#define RPM_VREG_PIN_CTRL_PM8921_A0 0x02
+#define RPM_VREG_PIN_CTRL_PM8921_A1 0x04
+#define RPM_VREG_PIN_CTRL_PM8921_A2 0x08
/**
- * enum rpm_vreg_pin_fn - RPM regulator pin function choices
- * %RPM_VREG_PIN_FN_DONT_CARE: do not care about pin control state of the
- * regulator; allow another master processor to
- * specify pin control
- * %RPM_VREG_PIN_FN_ENABLE: pin control switches between disable and enable
- * %RPM_VREG_PIN_FN_MODE: pin control switches between LPM and HPM
- * %RPM_VREG_PIN_FN_SLEEP_B: regulator is forced into LPM when sleep_b signal
- * is asserted
- * %RPM_VREG_PIN_FN_NONE: do not use pin control for the regulator and do
- * not allow another master to request pin control
+ * enum rpm_vreg_pin_fn_8960 - RPM regulator pin function choices
+ * %RPM_VREG_PIN_FN_8960_DONT_CARE: do not care about pin control state of
+ * the regulator; allow another master
+ * processor to specify pin control
+ * %RPM_VREG_PIN_FN_8960_ENABLE: pin control switches between disable and
+ * enable
+ * %RPM_VREG_PIN_FN_8960_MODE: pin control switches between LPM and HPM
+ * %RPM_VREG_PIN_FN_8960_SLEEP_B: regulator is forced into LPM when
+ * sleep_b signal is asserted
+ * %RPM_VREG_PIN_FN_8960_NONE: do not use pin control for the regulator
+ * and do not allow another master to
+ * request pin control
*
* The pin function specified in platform data corresponds to the active state
* pin function value. Pin function will be NONE until a consumer requests
* pin control to be enabled.
*/
-enum rpm_vreg_pin_fn {
- RPM_VREG_PIN_FN_DONT_CARE,
- RPM_VREG_PIN_FN_ENABLE,
- RPM_VREG_PIN_FN_MODE,
- RPM_VREG_PIN_FN_SLEEP_B,
- RPM_VREG_PIN_FN_NONE,
+enum rpm_vreg_pin_fn_8960 {
+ RPM_VREG_PIN_FN_8960_DONT_CARE,
+ RPM_VREG_PIN_FN_8960_ENABLE,
+ RPM_VREG_PIN_FN_8960_MODE,
+ RPM_VREG_PIN_FN_8960_SLEEP_B,
+ RPM_VREG_PIN_FN_8960_NONE,
};
/**
- * enum rpm_vreg_force_mode - RPM regulator force mode choices
- * %RPM_VREG_FORCE_MODE_PIN_CTRL: allow pin control usage
- * %RPM_VREG_FORCE_MODE_NONE: do not force any mode
- * %RPM_VREG_FORCE_MODE_LPM: force into low power mode
- * %RPM_VREG_FORCE_MODE_AUTO: allow regulator to automatically select its
- * own mode based on realtime current draw
- * (only available for SMPS regulators)
- * %RPM_VREG_FORCE_MODE_HPM: force into high power mode
- * %RPM_VREG_FORCE_MODE_BYPASS: set regulator to use bypass mode, i.e. to act
- * as a switch and not regulate (only available
- * for LDO regulators)
+ * enum rpm_vreg_force_mode_8960 - RPM regulator force mode choices
+ * %RPM_VREG_FORCE_MODE_8960_PIN_CTRL: allow pin control usage
+ * %RPM_VREG_FORCE_MODE_8960_NONE: do not force any mode
+ * %RPM_VREG_FORCE_MODE_8960_LPM: force into low power mode
+ * %RPM_VREG_FORCE_MODE_8960_AUTO: allow regulator to automatically select
+ * its own mode based on realtime current
+ * draw (only available for SMPS
+ * regulators)
+ * %RPM_VREG_FORCE_MODE_8960_HPM: force into high power mode
+ * %RPM_VREG_FORCE_MODE_8960_BYPASS: set regulator to use bypass mode, i.e.
+ * to act as a switch and not regulate
+ * (only available for LDO regulators)
*
* Force mode is used to override aggregation with other masters and to set
* special operating modes.
*/
-enum rpm_vreg_force_mode {
- RPM_VREG_FORCE_MODE_PIN_CTRL = 0,
- RPM_VREG_FORCE_MODE_NONE = 0,
- RPM_VREG_FORCE_MODE_LPM,
- RPM_VREG_FORCE_MODE_AUTO, /* SMPS only */
- RPM_VREG_FORCE_MODE_HPM,
- RPM_VREG_FORCE_MODE_BYPASS, /* LDO only */
+enum rpm_vreg_force_mode_8960 {
+ RPM_VREG_FORCE_MODE_8960_PIN_CTRL = 0,
+ RPM_VREG_FORCE_MODE_8960_NONE = 0,
+ RPM_VREG_FORCE_MODE_8960_LPM,
+ RPM_VREG_FORCE_MODE_8960_AUTO, /* SMPS only */
+ RPM_VREG_FORCE_MODE_8960_HPM,
+ RPM_VREG_FORCE_MODE_8960_BYPASS, /* LDO only */
};
/**
- * enum rpm_vreg_power_mode - power mode for SMPS regulators
- * %RPM_VREG_POWER_MODE_HYSTERETIC: Use hysteretic mode for HPM and when
- * usage goes high in AUTO
- * %RPM_VREG_POWER_MODE_PWM: Use PWM mode for HPM and when usage goes
- * high in AUTO
+ * enum rpm_vreg_power_mode_8960 - power mode for SMPS regulators
+ * %RPM_VREG_POWER_MODE_8960_HYSTERETIC: Use hysteretic mode for HPM and when
+ * usage goes high in AUTO
+ * %RPM_VREG_POWER_MODE_8960_PWM: Use PWM mode for HPM and when usage
+ * goes high in AUTO
*/
-enum rpm_vreg_power_mode {
- RPM_VREG_POWER_MODE_HYSTERETIC,
- RPM_VREG_POWER_MODE_PWM,
-};
-
-/**
- * enum rpm_vreg_state - enable state for switch or NCP
- */
-enum rpm_vreg_state {
- RPM_VREG_STATE_OFF,
- RPM_VREG_STATE_ON,
-};
-
-/**
- * enum rpm_vreg_freq - switching frequency for SMPS or NCP
- */
-enum rpm_vreg_freq {
- RPM_VREG_FREQ_NONE,
- RPM_VREG_FREQ_19p20,
- RPM_VREG_FREQ_9p60,
- RPM_VREG_FREQ_6p40,
- RPM_VREG_FREQ_4p80,
- RPM_VREG_FREQ_3p84,
- RPM_VREG_FREQ_3p20,
- RPM_VREG_FREQ_2p74,
- RPM_VREG_FREQ_2p40,
- RPM_VREG_FREQ_2p13,
- RPM_VREG_FREQ_1p92,
- RPM_VREG_FREQ_1p75,
- RPM_VREG_FREQ_1p60,
- RPM_VREG_FREQ_1p48,
- RPM_VREG_FREQ_1p37,
- RPM_VREG_FREQ_1p28,
- RPM_VREG_FREQ_1p20,
+enum rpm_vreg_power_mode_8960 {
+ RPM_VREG_POWER_MODE_8960_HYSTERETIC,
+ RPM_VREG_POWER_MODE_8960_PWM,
};
/**
* enum rpm_vreg_id - RPM regulator ID numbers (both real and pin control)
*/
-enum rpm_vreg_id {
+enum rpm_vreg_id_8960 {
RPM_VREG_ID_PM8921_L1,
RPM_VREG_ID_PM8921_L2,
RPM_VREG_ID_PM8921_L3,
@@ -211,76 +176,12 @@
};
/* Minimum high power mode loads in uA. */
-#define RPM_VREG_LDO_50_HPM_MIN_LOAD 5000
-#define RPM_VREG_LDO_150_HPM_MIN_LOAD 10000
-#define RPM_VREG_LDO_300_HPM_MIN_LOAD 10000
-#define RPM_VREG_LDO_600_HPM_MIN_LOAD 10000
-#define RPM_VREG_LDO_1200_HPM_MIN_LOAD 10000
-#define RPM_VREG_SMPS_1500_HPM_MIN_LOAD 100000
-#define RPM_VREG_SMPS_2000_HPM_MIN_LOAD 100000
-
-/**
- * struct rpm_regulator_init_data - RPM regulator initialization data
- * @init_data: regulator constraints
- * @id: regulator id; from enum rpm_vreg_id
- * @sleep_selectable: flag which indicates that regulator should be accessable
- * by external private API and that spinlocks should be
- * used instead of mutex locks
- * @system_uA: current drawn from regulator not accounted for by any
- * regulator framework consumer
- * @pull_down_enable: 0 = no pulldown, 1 = pulldown when regulator disabled
- * @freq: enum value representing the switching frequency of an
- * SMPS or NCP
- * @pin_ctrl: pin control inputs to use for the regulator; should be
- * a combination of RPM_VREG_PIN_CTRL_* values
- * @pin_fn: action to perform when pin control pin(s) is/are active
- * @force_mode: used to specify a force mode which overrides the votes
- * of other RPM masters.
- * @default_uV: initial voltage to set the regulator to if enable is
- * called before set_voltage (e.g. when boot_on or
- * always_on is set).
- * @peak_uA: initial peak load requirement sent in RPM request; used
- * to determine initial mode.
- * @avg_uA: average load requirement sent in RPM request
- * @state: initial enable state sent in RPM request for switch or
- * NCP
- */
-struct rpm_regulator_init_data {
- struct regulator_init_data init_data;
- enum rpm_vreg_id id;
- int sleep_selectable;
- int system_uA;
- unsigned pull_down_enable;
- enum rpm_vreg_freq freq;
- unsigned pin_ctrl;
- enum rpm_vreg_pin_fn pin_fn;
- enum rpm_vreg_force_mode force_mode;
- enum rpm_vreg_power_mode power_mode;
- int default_uV;
- unsigned peak_uA;
- unsigned avg_uA;
- enum rpm_vreg_state state;
-};
-
-/**
- * struct rpm_regulator_platform_data - RPM regulator platform data
- */
-struct rpm_regulator_platform_data {
- struct rpm_regulator_init_data *init_data;
- int num_regulators;
-};
-
-/**
- * enum rpm_vreg_voter - RPM regulator voter IDs for private APIs
- */
-enum rpm_vreg_voter {
- RPM_VREG_VOTER_REG_FRAMEWORK, /* for internal use only */
- RPM_VREG_VOTER1, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER2, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER3, /* for use by other drivers */
- RPM_VREG_VOTER4, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER5, /* for use by the acpu-clock driver */
- RPM_VREG_VOTER_COUNT,
-};
+#define RPM_VREG_8960_LDO_50_HPM_MIN_LOAD 5000
+#define RPM_VREG_8960_LDO_150_HPM_MIN_LOAD 10000
+#define RPM_VREG_8960_LDO_300_HPM_MIN_LOAD 10000
+#define RPM_VREG_8960_LDO_600_HPM_MIN_LOAD 10000
+#define RPM_VREG_8960_LDO_1200_HPM_MIN_LOAD 10000
+#define RPM_VREG_8960_SMPS_1500_HPM_MIN_LOAD 100000
+#define RPM_VREG_8960_SMPS_2000_HPM_MIN_LOAD 100000
#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator-9615.h b/arch/arm/mach-msm/include/mach/rpm-regulator-9615.h
new file mode 100644
index 0000000..f5fa8ca
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator-9615.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_9615_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_9615_H
+
+/* Pin control input signals. */
+#define RPM_VREG_PIN_CTRL_PM8018_D1 0x01
+#define RPM_VREG_PIN_CTRL_PM8018_A0 0x02
+#define RPM_VREG_PIN_CTRL_PM8018_A1 0x04
+#define RPM_VREG_PIN_CTRL_PM8018_A2 0x08
+
+/**
+ * enum rpm_vreg_pin_fn_9615 - RPM regulator pin function choices
+ * %RPM_VREG_PIN_FN_9615_DONT_CARE: do not care about pin control state of
+ * the regulator; allow another master
+ * processor to specify pin control
+ * %RPM_VREG_PIN_FN_9615_ENABLE: pin control switches between disable and
+ * enable
+ * %RPM_VREG_PIN_FN_9615_MODE: pin control switches between LPM and HPM
+ * %RPM_VREG_PIN_FN_9615_SLEEP_B: regulator is forced into LPM when
+ * sleep_b signal is asserted
+ * %RPM_VREG_PIN_FN_9615_NONE: do not use pin control for the regulator
+ * and do not allow another master to
+ * request pin control
+ *
+ * The pin function specified in platform data corresponds to the active state
+ * pin function value. Pin function will be NONE until a consumer requests
+ * pin control to be enabled.
+ */
+enum rpm_vreg_pin_fn_9615 {
+ RPM_VREG_PIN_FN_9615_DONT_CARE,
+ RPM_VREG_PIN_FN_9615_ENABLE,
+ RPM_VREG_PIN_FN_9615_MODE,
+ RPM_VREG_PIN_FN_9615_SLEEP_B,
+ RPM_VREG_PIN_FN_9615_NONE,
+};
+
+/**
+ * enum rpm_vreg_force_mode_9615 - RPM regulator force mode choices
+ * %RPM_VREG_FORCE_MODE_9615_PIN_CTRL: allow pin control usage
+ * %RPM_VREG_FORCE_MODE_9615_NONE: do not force any mode
+ * %RPM_VREG_FORCE_MODE_9615_LPM: force into low power mode
+ * %RPM_VREG_FORCE_MODE_9615_AUTO: allow regulator to automatically select
+ * its own mode based on realtime current
+ * draw (only available for SMPS
+ * regulators)
+ * %RPM_VREG_FORCE_MODE_9615_HPM: force into high power mode
+ * %RPM_VREG_FORCE_MODE_9615_BYPASS: set regulator to use bypass mode, i.e.
+ * to act as a switch and not regulate
+ * (only available for LDO regulators)
+ *
+ * Force mode is used to override aggregation with other masters and to set
+ * special operating modes.
+ */
+enum rpm_vreg_force_mode_9615 {
+ RPM_VREG_FORCE_MODE_9615_PIN_CTRL = 0,
+ RPM_VREG_FORCE_MODE_9615_NONE = 0,
+ RPM_VREG_FORCE_MODE_9615_LPM,
+ RPM_VREG_FORCE_MODE_9615_AUTO, /* SMPS only */
+ RPM_VREG_FORCE_MODE_9615_HPM,
+ RPM_VREG_FORCE_MODE_9615_BYPASS, /* LDO only */
+};
+
+/**
+ * enum rpm_vreg_power_mode_9615 - power mode for SMPS regulators
+ * %RPM_VREG_POWER_MODE_9615_HYSTERETIC: Use hysteretic mode for HPM and when
+ * usage goes high in AUTO
+ * %RPM_VREG_POWER_MODE_9615_PWM: Use PWM mode for HPM and when usage
+ * goes high in AUTO
+ */
+enum rpm_vreg_power_mode_9615 {
+ RPM_VREG_POWER_MODE_9615_HYSTERETIC,
+ RPM_VREG_POWER_MODE_9615_PWM,
+};
+
+/**
+ * enum rpm_vreg_id - RPM regulator ID numbers (both real and pin control)
+ */
+enum rpm_vreg_id_9615 {
+ RPM_VREG_ID_PM8018_L2,
+ RPM_VREG_ID_PM8018_L3,
+ RPM_VREG_ID_PM8018_L4,
+ RPM_VREG_ID_PM8018_L5,
+ RPM_VREG_ID_PM8018_L6,
+ RPM_VREG_ID_PM8018_L7,
+ RPM_VREG_ID_PM8018_L8,
+ RPM_VREG_ID_PM8018_L9,
+ RPM_VREG_ID_PM8018_L10,
+ RPM_VREG_ID_PM8018_L11,
+ RPM_VREG_ID_PM8018_L12,
+ RPM_VREG_ID_PM8018_L13,
+ RPM_VREG_ID_PM8018_L14,
+ RPM_VREG_ID_PM8018_S1,
+ RPM_VREG_ID_PM8018_S2,
+ RPM_VREG_ID_PM8018_S3,
+ RPM_VREG_ID_PM8018_S4,
+ RPM_VREG_ID_PM8018_S5,
+ RPM_VREG_ID_PM8018_LVS1,
+ RPM_VREG_ID_PM8018_MAX_REAL = RPM_VREG_ID_PM8018_LVS1,
+
+ /* The following are IDs for regulator devices to enable pin control. */
+ RPM_VREG_ID_PM8018_L2_PC,
+ RPM_VREG_ID_PM8018_L3_PC,
+ RPM_VREG_ID_PM8018_L4_PC,
+ RPM_VREG_ID_PM8018_L5_PC,
+ RPM_VREG_ID_PM8018_L6_PC,
+ RPM_VREG_ID_PM8018_L7_PC,
+ RPM_VREG_ID_PM8018_L8_PC,
+ RPM_VREG_ID_PM8018_L13_PC,
+ RPM_VREG_ID_PM8018_L14_PC,
+ RPM_VREG_ID_PM8018_S1_PC,
+ RPM_VREG_ID_PM8018_S2_PC,
+ RPM_VREG_ID_PM8018_S3_PC,
+ RPM_VREG_ID_PM8018_S4_PC,
+ RPM_VREG_ID_PM8018_S5_PC,
+ RPM_VREG_ID_PM8018_LVS1_PC,
+ RPM_VREG_ID_PM8018_MAX = RPM_VREG_ID_PM8018_LVS1_PC,
+};
+
+/* Minimum high power mode loads in uA. */
+#define RPM_VREG_9615_LDO_50_HPM_MIN_LOAD 5000
+#define RPM_VREG_9615_LDO_150_HPM_MIN_LOAD 10000
+#define RPM_VREG_9615_LDO_300_HPM_MIN_LOAD 10000
+#define RPM_VREG_9615_LDO_1200_HPM_MIN_LOAD 10000
+#define RPM_VREG_9615_SMPS_1500_HPM_MIN_LOAD 100000
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator.h b/arch/arm/mach-msm/include/mach/rpm-regulator.h
index 1187efc..8b5a1e7 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -10,18 +10,130 @@
* GNU General Public License for more details.
*/
-#ifndef __ARCH_ARM_MACH_MSM_RPM_REGULATOR_H
-#define __ARCH_ARM_MACH_MSM_RPM_REGULATOR_H
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_H
#include <linux/regulator/machine.h>
#define RPM_REGULATOR_DEV_NAME "rpm-regulator"
-#if defined(CONFIG_ARCH_MSM8X60)
#include <mach/rpm-regulator-8660.h>
-#elif defined(CONFIG_ARCH_MSM8960)
#include <mach/rpm-regulator-8960.h>
-#endif
+#include <mach/rpm-regulator-9615.h>
+
+/**
+ * enum rpm_vreg_version - supported RPM regulator versions
+ */
+enum rpm_vreg_version {
+ RPM_VREG_VERSION_8660,
+ RPM_VREG_VERSION_8960,
+ RPM_VREG_VERSION_9615,
+ RPM_VREG_VERSION_MAX = RPM_VREG_VERSION_9615,
+};
+
+#define RPM_VREG_PIN_CTRL_NONE 0x00
+
+/**
+ * enum rpm_vreg_state - enable state for switch or NCP
+ */
+enum rpm_vreg_state {
+ RPM_VREG_STATE_OFF,
+ RPM_VREG_STATE_ON,
+};
+
+/**
+ * enum rpm_vreg_freq - switching frequency for SMPS or NCP
+ */
+enum rpm_vreg_freq {
+ RPM_VREG_FREQ_NONE,
+ RPM_VREG_FREQ_19p20,
+ RPM_VREG_FREQ_9p60,
+ RPM_VREG_FREQ_6p40,
+ RPM_VREG_FREQ_4p80,
+ RPM_VREG_FREQ_3p84,
+ RPM_VREG_FREQ_3p20,
+ RPM_VREG_FREQ_2p74,
+ RPM_VREG_FREQ_2p40,
+ RPM_VREG_FREQ_2p13,
+ RPM_VREG_FREQ_1p92,
+ RPM_VREG_FREQ_1p75,
+ RPM_VREG_FREQ_1p60,
+ RPM_VREG_FREQ_1p48,
+ RPM_VREG_FREQ_1p37,
+ RPM_VREG_FREQ_1p28,
+ RPM_VREG_FREQ_1p20,
+};
+
+/**
+ * struct rpm_regulator_init_data - RPM regulator initialization data
+ * @init_data: regulator constraints
+ * @id: regulator id; from enum rpm_vreg_id
+ * @sleep_selectable: flag which indicates that regulator should be accessable
+ * by external private API and that spinlocks should be
+ * used instead of mutex locks
+ * @system_uA: current drawn from regulator not accounted for by any
+ * regulator framework consumer
+ * @enable_time: time in us taken to enable a regulator to the maximum
+ * allowed voltage for the system. This is dependent upon
+ * the load and capacitance for a regulator on the board.
+ * @pull_down_enable: 0 = no pulldown, 1 = pulldown when regulator disabled
+ * @freq: enum value representing the switching frequency of an
+ * SMPS or NCP
+ * @pin_ctrl: pin control inputs to use for the regulator; should be
+ * a combination of RPM_VREG_PIN_CTRL_* values
+ * @pin_fn: action to perform when pin control pin(s) is/are active
+ * @force_mode: used to specify a force mode which overrides the votes
+ * of other RPM masters.
+ * @default_uV: initial voltage to set the regulator to if enable is
+ * called before set_voltage (e.g. when boot_on or
+ * always_on is set).
+ * @peak_uA: initial peak load requirement sent in RPM request; used
+ * to determine initial mode.
+ * @avg_uA: average load requirement sent in RPM request
+ * @state: initial enable state sent in RPM request for switch or
+ * NCP
+ */
+struct rpm_regulator_init_data {
+ struct regulator_init_data init_data;
+ int id;
+ int sleep_selectable;
+ int system_uA;
+ int enable_time;
+ unsigned pull_down_enable;
+ enum rpm_vreg_freq freq;
+ unsigned pin_ctrl;
+ int pin_fn;
+ int force_mode;
+ int power_mode;
+ int default_uV;
+ unsigned peak_uA;
+ unsigned avg_uA;
+ enum rpm_vreg_state state;
+};
+
+/**
+ * struct rpm_regulator_platform_data - RPM regulator platform data
+ */
+struct rpm_regulator_platform_data {
+ struct rpm_regulator_init_data *init_data;
+ int num_regulators;
+ enum rpm_vreg_version version;
+ int vreg_id_vdd_mem;
+ int vreg_id_vdd_dig;
+};
+
+/**
+ * enum rpm_vreg_voter - RPM regulator voter IDs for private APIs
+ */
+enum rpm_vreg_voter {
+ RPM_VREG_VOTER_REG_FRAMEWORK, /* for internal use only */
+ RPM_VREG_VOTER1, /* for use by the acpu-clock driver */
+ RPM_VREG_VOTER2, /* for use by the acpu-clock driver */
+ RPM_VREG_VOTER3, /* for use by other drivers */
+ RPM_VREG_VOTER4, /* for use by the acpu-clock driver */
+ RPM_VREG_VOTER5, /* for use by the acpu-clock driver */
+ RPM_VREG_VOTER_COUNT,
+};
/**
* rpm_vreg_set_voltage - vote for a min_uV value of specified regualtor
@@ -44,8 +156,8 @@
* This function may only be called for regulators which have the sleep flag
* specified in their private data.
*/
-int rpm_vreg_set_voltage(enum rpm_vreg_id vreg_id, enum rpm_vreg_voter voter,
- int min_uV, int max_uV, int sleep_also);
+int rpm_vreg_set_voltage(int vreg_id, enum rpm_vreg_voter voter, int min_uV,
+ int max_uV, int sleep_also);
/**
* rpm_vreg_set_frequency - sets the frequency of a switching regulator
@@ -54,6 +166,6 @@
*
* Returns 0 on success or errno.
*/
-int rpm_vreg_set_frequency(enum rpm_vreg_id vreg_id, enum rpm_vreg_freq freq);
+int rpm_vreg_set_frequency(int vreg_id, enum rpm_vreg_freq freq);
#endif
diff --git a/arch/arm/mach-msm/include/mach/usb_dun_bridge.h b/arch/arm/mach-msm/include/mach/usb_dun_bridge.h
new file mode 100644
index 0000000..b4a8eef
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/usb_dun_bridge.h
@@ -0,0 +1,113 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __USB_DUN_BRIDGE_H
+#define __USB_DUN_BRIDGE_H
+
+/**
+ * struct dun_bridge_ops - context and callbacks for DUN bridge
+ *
+ * @ctxt: caller private context
+ * @read_complete: called when read is completed. buf and len correspond
+ * to original passed-in values. actual length of buffer returned, or
+ * negative error value.
+ * @write_complete: called when write is completed. buf and len correspond
+ * to original passed-in values. actual length of buffer returned, or
+ * negative error value.
+ * @ctrl_status: asynchronous notification of control status. ctrl_bits
+ * is a bitfield of CDC ACM control status bits.
+ */
+struct dun_bridge_ops {
+ void *ctxt;
+ void (*read_complete)(void *ctxt, char *buf, size_t len, size_t actual);
+ void (*write_complete)(void *ctxt, char *buf,
+ size_t len, size_t actual);
+ void (*ctrl_status)(void *ctxt, unsigned int ctrl_bits);
+};
+
+#ifdef CONFIG_USB_QCOM_DUN_BRIDGE
+
+/**
+ * dun_bridge_open - Open the DUN bridge
+ *
+ * @ops: pointer to ops struct containing private context and callback
+ * pointers
+ */
+int dun_bridge_open(struct dun_bridge_ops *ops);
+
+/**
+ * dun_bridge_close - Closes the DUN bridge
+ */
+int dun_bridge_close(void);
+
+/**
+ * dun_bridge_read - Request to read data from the DUN bridge. This call is
+ * asynchronous: user's read callback (ops->read_complete) will be called
+ * when data is returned.
+ *
+ * @data: pointer to caller-allocated buffer to fill in
+ * @len: size of the buffer
+ */
+int dun_bridge_read(void *data, int len);
+
+/**
+ * dun_bridge_write - Request to write data to the DUN bridge. This call is
+ * asynchronous: user's write callback (ops->write_complete) will be called
+ * upon completion of the write indicating status and number of bytes
+ * written.
+ *
+ * @data: pointer to caller-allocated buffer to write
+ * @len: length of the data in buffer
+ */
+int dun_bridge_write(void *data, int len);
+
+/**
+ * dun_bridge_send_ctrl_bits - Request to write line control data to the DUN
+ * bridge. This call is asynchronous, however no callback will be issued
+ * upon completion.
+ *
+ * @ctrl_bits: CDC ACM line control bits
+ */
+int dun_bridge_send_ctrl_bits(unsigned ctrl_bits);
+
+#else
+
+#include <linux/errno.h>
+
+static int __maybe_unused dun_bridge_open(struct dun_bridge_ops *ops)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_close(void)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_read(void *data, int len)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_write(void *data, int len)
+{
+ return -ENODEV;
+}
+
+static int __maybe_unused dun_bridge_send_ctrl_bits(unsigned ctrl_bits)
+{
+ return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 9137e08..3bb10fb 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -327,6 +327,7 @@
MSM_CHIP_DEVICE(RPM, MSM9615),
MSM_CHIP_DEVICE(RPM_MPM, MSM9615),
MSM_CHIP_DEVICE(APCS_GLB, MSM9615),
+ MSM_CHIP_DEVICE(IMEM, MSM9615),
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.length = MSM_SHARED_RAM_SIZE,
diff --git a/arch/arm/mach-msm/ipc_router.c b/arch/arm/mach-msm/ipc_router.c
index ea9d246..3d34a30 100644
--- a/arch/arm/mach-msm/ipc_router.c
+++ b/arch/arm/mach-msm/ipc_router.c
@@ -176,6 +176,8 @@
static DEFINE_MUTEX(xprt_info_list_lock);
DECLARE_COMPLETION(msm_ipc_remote_router_up);
+static DECLARE_COMPLETION(msm_ipc_local_router_up);
+#define IPC_ROUTER_INIT_TIMEOUT (10 * HZ)
static uint32_t next_port_id;
static DEFINE_MUTEX(next_port_id_lock);
@@ -2399,8 +2401,16 @@
struct msm_ipc_router_xprt_info *xprt_info = xprt->priv;
struct msm_ipc_router_xprt_work *xprt_work;
struct rr_packet *pkt;
+ unsigned long ret;
- BUG_ON(!msm_ipc_router_workqueue);
+ if (!msm_ipc_router_workqueue) {
+ ret = wait_for_completion_timeout(&msm_ipc_local_router_up,
+ IPC_ROUTER_INIT_TIMEOUT);
+ if (!ret || !msm_ipc_router_workqueue) {
+ pr_err("%s: IPC Router not initialized\n", __func__);
+ return;
+ }
+ }
switch (event) {
case IPC_ROUTER_XPRT_EVENT_OPEN:
@@ -2515,6 +2525,7 @@
if (ret < 0)
pr_err("%s: Init sockets failed\n", __func__);
+ complete_all(&msm_ipc_local_router_up);
return ret;
}
diff --git a/arch/arm/mach-msm/ipc_router_smd_xprt.c b/arch/arm/mach-msm/ipc_router_smd_xprt.c
index 076193e..997d4b5 100644
--- a/arch/arm/mach-msm/ipc_router_smd_xprt.c
+++ b/arch/arm/mach-msm/ipc_router_smd_xprt.c
@@ -46,7 +46,14 @@
static struct msm_ipc_router_smd_xprt smd_remote_xprt;
+struct msm_ipc_router_smd_xprt_work {
+ struct msm_ipc_router_xprt *xprt;
+ struct work_struct work;
+};
+
static void smd_xprt_read_data(struct work_struct *work);
+static void smd_xprt_open_event(struct work_struct *work);
+static void smd_xprt_close_event(struct work_struct *work);
static DECLARE_DELAYED_WORK(work_read_data, smd_xprt_read_data);
static struct workqueue_struct *smd_xprt_workqueue;
@@ -251,9 +258,32 @@
}
}
+static void smd_xprt_open_event(struct work_struct *work)
+{
+ struct msm_ipc_router_smd_xprt_work *xprt_work =
+ container_of(work, struct msm_ipc_router_smd_xprt_work, work);
+
+ msm_ipc_router_xprt_notify(xprt_work->xprt,
+ IPC_ROUTER_XPRT_EVENT_OPEN, NULL);
+ D("%s: Notified IPC Router of OPEN Event\n", __func__);
+ kfree(xprt_work);
+}
+
+static void smd_xprt_close_event(struct work_struct *work)
+{
+ struct msm_ipc_router_smd_xprt_work *xprt_work =
+ container_of(work, struct msm_ipc_router_smd_xprt_work, work);
+
+ msm_ipc_router_xprt_notify(xprt_work->xprt,
+ IPC_ROUTER_XPRT_EVENT_CLOSE, NULL);
+ D("%s: Notified IPC Router of CLOSE Event\n", __func__);
+ kfree(xprt_work);
+}
+
static void msm_ipc_router_smd_remote_notify(void *_dev, unsigned event)
{
unsigned long flags;
+ struct msm_ipc_router_smd_xprt_work *xprt_work;
switch (event) {
case SMD_EVENT_DATA:
@@ -268,9 +298,16 @@
spin_lock_irqsave(&modem_reset_lock, flags);
modem_reset = 0;
spin_unlock_irqrestore(&modem_reset_lock, flags);
- msm_ipc_router_xprt_notify(&smd_remote_xprt.xprt,
- IPC_ROUTER_XPRT_EVENT_OPEN, NULL);
- D("%s: Notified IPC Router of OPEN Event\n", __func__);
+ xprt_work = kmalloc(sizeof(struct msm_ipc_router_smd_xprt_work),
+ GFP_ATOMIC);
+ if (!xprt_work) {
+ pr_err("%s: Couldn't notify %d event to IPC Router\n",
+ __func__, event);
+ return;
+ }
+ xprt_work->xprt = &smd_remote_xprt.xprt;
+ INIT_WORK(&xprt_work->work, smd_xprt_open_event);
+ queue_work(smd_xprt_workqueue, &xprt_work->work);
break;
case SMD_EVENT_CLOSE:
@@ -278,9 +315,16 @@
modem_reset = 1;
spin_unlock_irqrestore(&modem_reset_lock, flags);
wake_up(&write_avail_wait_q);
- msm_ipc_router_xprt_notify(&smd_remote_xprt.xprt,
- IPC_ROUTER_XPRT_EVENT_CLOSE, NULL);
- D("%s: Notified IPC Router of CLOSE Event\n", __func__);
+ xprt_work = kmalloc(sizeof(struct msm_ipc_router_smd_xprt_work),
+ GFP_ATOMIC);
+ if (!xprt_work) {
+ pr_err("%s: Couldn't notify %d event to IPC Router\n",
+ __func__, event);
+ return;
+ }
+ xprt_work->xprt = &smd_remote_xprt.xprt;
+ INIT_WORK(&xprt_work->work, smd_xprt_close_event);
+ queue_work(smd_xprt_workqueue, &xprt_work->work);
break;
}
}
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 109231a..660d530 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -610,6 +610,33 @@
mb();
}
+static inline void msm_vic_handle_irq(void __iomem *base_addr, struct pt_regs
+ *regs)
+{
+ u32 irqnr;
+
+ do {
+ /* 0xD0 has irq# or old irq# if the irq has been handled
+ * 0xD4 has irq# or -1 if none pending *but* if you just
+ * read 0xD4 you never get the first irq for some reason
+ */
+ irqnr = readl_relaxed(base_addr + 0xD0);
+ irqnr = readl_relaxed(base_addr + 0xD4);
+ if (irqnr == -1)
+ break;
+ handle_IRQ(irqnr, regs);
+ } while (1);
+}
+
+/* enable imprecise aborts */
+#define local_cpsie_enable() __asm__ __volatile__("cpsie a @ enable")
+
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+ local_cpsie_enable();
+ msm_vic_handle_irq((void __iomem *)MSM_VIC_BASE, regs);
+}
+
#if defined(CONFIG_MSM_FIQ_SUPPORT)
void msm_trigger_irq(int irq)
{
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
index ddf56c8..13b59ed 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8660.c
@@ -906,3 +906,7 @@
SLAVE_ID_KEY]);
}
+int msm_bus_board_rpm_get_il_ids(uint16_t id[])
+{
+ return -ENXIO;
+}
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
index 1819d95..8ab1899 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_board_8960.c
@@ -939,3 +939,9 @@
SLAVE_ID_KEY]);
}
+int msm_bus_board_rpm_get_il_ids(uint16_t id[])
+{
+ id[0] = MSM_RPM_STATUS_ID_EBI1_CH0_RANGE;
+ id[1] = MSM_RPM_STATUS_ID_EBI1_CH1_RANGE;
+ return 0;
+}
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_core.h b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
index cc1eb78..56a5b8da 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_core.h
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_core.h
@@ -170,6 +170,7 @@
long int add_bw);
void msm_bus_rpm_fill_cdata_buffer(int *curr, char *buf, const int max_size,
void *cdata, int nmasters, int nslaves, int ntslaves);
+bool msm_bus_rpm_is_mem_interleaved(void);
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_MSM_BUS_SCALING)
void msm_bus_dbg_client_data(struct msm_bus_scale_pdata *pdata, int index,
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
index d8323e3..fe6dbed 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_fabric.c
@@ -650,6 +650,7 @@
pdata = (struct msm_bus_fabric_registration *)pdev->dev.platform_data;
fabric->fabdev.name = pdata->name;
fabric->fabdev.algo = &msm_bus_algo;
+ pdata->il_flag = msm_bus_rpm_is_mem_interleaved();
fabric->ahb = pdata->ahb;
fabric->pdata = pdata;
msm_bus_board_assign_iids(fabric->pdata, fabric->fabdev.id);
diff --git a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
index ec0db42..332d3c1 100644
--- a/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
+++ b/arch/arm/mach-msm/msm_bus/msm_bus_rpm.c
@@ -22,6 +22,10 @@
#include "msm_bus_core.h"
#include "../rpm_resources.h"
+#define INTERLEAVED_BW(fab_pdata, bw, ports) \
+ ((fab_pdata->il_flag) ? ((bw) / (ports)) : (bw))
+#define INTERLEAVED_VAL(fab_pdata, n) \
+ ((fab_pdata->il_flag) ? (n) : 1)
void msm_bus_rpm_set_mt_mask()
{
@@ -35,6 +39,47 @@
#endif
}
+bool msm_bus_rpm_is_mem_interleaved(void)
+{
+ int status = 0;
+ struct msm_rpm_iv_pair il[2];
+ uint16_t id[2];
+
+ il[0].value = 0;
+ il[1].value = 0;
+ status = msm_bus_board_rpm_get_il_ids(id);
+ if (status) {
+ MSM_BUS_DBG("Dynamic check not supported, "
+ "default: Interleaved memory\n");
+ goto inter;
+ }
+
+ il[0].id = id[0];
+ il[1].id = id[1];
+ status = msm_rpm_get_status(il, ARRAY_SIZE(il));
+ if (status) {
+ MSM_BUS_ERR("Status read for interleaving returned: %d\n"
+ "Using interleaved memory by default\n",
+ status);
+ goto inter;
+ }
+
+ /*
+ * If the start address of EBI1-CH0 is the same as
+ * the start address of EBI1-CH1, the memory is interleaved.
+ * The start addresses are stored in the 16 MSBs of the status
+ * register
+ */
+ if ((il[0].value & 0xFFFF0000) != (il[1].value & 0xFFFF0000)) {
+ MSM_BUS_DBG("Non-interleaved memory\n");
+ return false;
+ }
+
+inter:
+ MSM_BUS_DBG("Interleaved memory\n");
+ return true;
+}
+
#ifndef CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED
struct commit_data {
uint16_t *bwsum;
@@ -198,13 +243,14 @@
void *sel_cdata, int *master_tiers,
long int add_bw)
{
- int index, i, j;
+ int index, i, j, tiers, ports;
struct commit_data *sel_cd = (struct commit_data *)sel_cdata;
- add_bw /= info->node_info->num_mports;
- for (i = 0; i < hop->node_info->num_tiers; i++) {
- for (j = 0; j < info->node_info->num_mports; j++) {
-
+ add_bw = INTERLEAVED_BW(fab_pdata, add_bw, info->node_info->num_mports);
+ ports = INTERLEAVED_VAL(fab_pdata, info->node_info->num_mports);
+ tiers = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_tiers);
+ for (i = 0; i < tiers; i++) {
+ for (j = 0; j < ports; j++) {
uint16_t hop_tier;
/*
* For interleaved gateway ports and slave ports,
@@ -246,8 +292,9 @@
&& hop->node_info->num_sports > 1)
tieredbw += add_bw;
else
- tieredbw += add_bw/
- hop->node_info->num_sports;
+ tieredbw += INTERLEAVED_BW(fab_pdata,
+ add_bw, hop->node_info->
+ num_sports);
/* If bw is 0, update tier to default */
if (!tieredbw)
@@ -265,7 +312,8 @@
}
/* Update bwsum for slaves on fabric */
- for (i = 0; i < hop->node_info->num_sports; i++) {
+ ports = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_sports);
+ for (i = 0; i < ports; i++) {
sel_cd->bwsum[hop->node_info->slavep[i]]
= (uint16_t)msm_bus_create_bw_tier_pair_bytes(0,
(*hop->link_info.sel_bw/hop->node_info->num_sports));
@@ -627,13 +675,14 @@
void *sel_cdata, int *master_tiers,
long int add_bw)
{
- int index, i, j;
+ int index, i, j, tiers, ports;
struct commit_data *sel_cd = (struct commit_data *)sel_cdata;
- add_bw /= info->node_info->num_mports;
- for (i = 0; i < hop->node_info->num_tiers; i++) {
- for (j = 0; j < info->node_info->num_mports; j++) {
-
+ add_bw = INTERLEAVED_BW(fab_pdata, add_bw, info->node_info->num_mports);
+ ports = INTERLEAVED_VAL(fab_pdata, info->node_info->num_mports);
+ tiers = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_tiers);
+ for (i = 0; i < tiers; i++) {
+ for (j = 0; j < ports; j++) {
uint16_t hop_tier;
/*
* For interleaved gateway ports and slave ports,
@@ -668,8 +717,9 @@
&& hop->node_info->num_sports > 1)
tieredbw += add_bw;
else
- tieredbw += add_bw/
- hop->node_info->num_sports;
+ tieredbw += INTERLEAVED_BW(fab_pdata,
+ add_bw, hop->node_info->
+ num_sports);
/* Update Arb for fab,get HW Mport from enum */
sel_cd->arb[tier][index] =
@@ -683,7 +733,9 @@
}
/* Update bwsum for slaves on fabric */
- for (i = 0; i < hop->node_info->num_sports; i++) {
+
+ ports = INTERLEAVED_VAL(fab_pdata, hop->node_info->num_sports);
+ for (i = 0; i < ports; i++) {
sel_cd->bwsum[hop->node_info->slavep[i]]
= msm_bus_pack_bwsum_bytes((*hop->link_info.
sel_bw/hop->node_info->num_sports));
diff --git a/arch/arm/mach-msm/msm_rq_stats.c b/arch/arm/mach-msm/msm_rq_stats.c
index 81c8ad5..a39703a 100644
--- a/arch/arm/mach-msm/msm_rq_stats.c
+++ b/arch/arm/mach-msm/msm_rq_stats.c
@@ -13,7 +13,6 @@
/*
* Qualcomm MSM Runqueue Stats Interface for Userspace
*/
-
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -26,60 +25,11 @@
#include <linux/workqueue.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
+#include <linux/rq_stats.h>
-struct rq_data {
- unsigned int rq_avg;
- unsigned int rq_poll_ms;
- unsigned int def_timer_ms;
- unsigned int def_interval;
- int64_t last_time;
- int64_t total_time;
- int64_t def_start_time;
- struct delayed_work rq_work;
- struct attribute_group *attr_group;
- struct kobject *kobj;
- struct delayed_work def_timer_work;
-};
-
-static struct rq_data rq_info;
-static DEFINE_SPINLOCK(rq_lock);
-static struct workqueue_struct *rq_wq;
-
-static void rq_work_fn(struct work_struct *work)
-{
- int64_t time_diff = 0;
- int64_t rq_avg = 0;
- unsigned long flags = 0;
-
- spin_lock_irqsave(&rq_lock, flags);
-
- if (!rq_info.last_time)
- rq_info.last_time = ktime_to_ns(ktime_get());
- if (!rq_info.rq_avg)
- rq_info.total_time = 0;
-
- rq_avg = nr_running() * 10;
- time_diff = ktime_to_ns(ktime_get()) - rq_info.last_time;
- do_div(time_diff, (1000 * 1000));
-
- if (time_diff && rq_info.total_time) {
- rq_avg = (rq_avg * time_diff) +
- (rq_info.rq_avg * rq_info.total_time);
- do_div(rq_avg, rq_info.total_time + time_diff);
- }
-
- rq_info.rq_avg = (unsigned int)rq_avg;
-
- /* Set the next poll */
- if (rq_info.rq_poll_ms)
- queue_delayed_work(rq_wq, &rq_info.rq_work,
- msecs_to_jiffies(rq_info.rq_poll_ms));
-
- rq_info.total_time += time_diff;
- rq_info.last_time = ktime_to_ns(ktime_get());
-
- spin_unlock_irqrestore(&rq_lock, flags);
-}
+#define MAX_LONG_SIZE 16
+#define DEFAULT_RQ_POLL_JIFFIES 1
+#define DEFAULT_DEF_TIMER_JIFFIES 5
static void def_work_fn(struct work_struct *work)
{
@@ -109,22 +59,24 @@
}
static ssize_t show_run_queue_poll_ms(struct kobject *kobj,
- struct kobj_attribute *attr, char *buf)
+ struct kobj_attribute *attr, char *buf)
{
int ret = 0;
unsigned long flags = 0;
spin_lock_irqsave(&rq_lock, flags);
- ret = sprintf(buf, "%u\n", rq_info.rq_poll_ms);
+ ret = snprintf(buf, MAX_LONG_SIZE, "%u\n",
+ jiffies_to_msecs(rq_info.rq_poll_jiffies));
spin_unlock_irqrestore(&rq_lock, flags);
return ret;
}
static ssize_t store_run_queue_poll_ms(struct kobject *kobj,
- struct kobj_attribute *attr, const char *buf, size_t count)
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
{
- int val = 0;
+ unsigned int val = 0;
unsigned long flags = 0;
static DEFINE_MUTEX(lock_poll_ms);
@@ -132,15 +84,9 @@
spin_lock_irqsave(&rq_lock, flags);
sscanf(buf, "%u", &val);
- rq_info.rq_poll_ms = val;
+ rq_info.rq_poll_jiffies = msecs_to_jiffies(val);
spin_unlock_irqrestore(&rq_lock, flags);
- if (val <= 0)
- cancel_delayed_work(&rq_info.rq_work);
- else
- queue_delayed_work(rq_wq, &rq_info.rq_work,
- msecs_to_jiffies(val));
-
mutex_unlock(&lock_poll_ms);
return count;
@@ -149,7 +95,8 @@
static ssize_t show_def_timer_ms(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
- return sprintf(buf, "%u\n", rq_info.def_interval);
+ return snprintf(buf, MAX_LONG_SIZE, "%lu\n",
+ rq_info.def_timer_jiffies);
}
static ssize_t store_def_timer_ms(struct kobject *kobj,
@@ -158,16 +105,9 @@
unsigned int val = 0;
sscanf(buf, "%u", &val);
- rq_info.def_timer_ms = val;
+ rq_info.def_timer_jiffies = msecs_to_jiffies(val);
- if (val <= 0)
- cancel_delayed_work(&rq_info.def_timer_work);
- else {
- rq_info.def_start_time = ktime_to_ns(ktime_get());
- queue_delayed_work(rq_wq, &rq_info.def_timer_work,
- msecs_to_jiffies(val));
- }
-
+ rq_info.def_start_time = ktime_to_ns(ktime_get());
return count;
}
@@ -210,7 +150,6 @@
goto rel;
rq_info.rq_avg = 0;
- rq_info.rq_poll_ms = 0;
attribs[0] = MSM_RQ_STATS_RW_ATTRIB(def_timer_ms);
attribs[1] = MSM_RQ_STATS_RO_ATTRIB(run_queue_avg);
@@ -257,8 +196,13 @@
{
rq_wq = create_singlethread_workqueue("rq_stats");
BUG_ON(!rq_wq);
- INIT_DELAYED_WORK_DEFERRABLE(&rq_info.rq_work, rq_work_fn);
- INIT_DELAYED_WORK_DEFERRABLE(&rq_info.def_timer_work, def_work_fn);
+ INIT_WORK(&rq_info.def_timer_work, def_work_fn);
+ spin_lock_init(&rq_lock);
+ rq_info.rq_poll_jiffies = DEFAULT_RQ_POLL_JIFFIES;
+ rq_info.def_timer_jiffies = DEFAULT_DEF_TIMER_JIFFIES;
+ rq_info.rq_poll_last_jiffy = 0;
+ rq_info.def_timer_last_jiffy = 0;
+ rq_info.init = 1;
return init_rq_attribs();
}
late_initcall(msm_rq_stats_init);
diff --git a/arch/arm/mach-msm/msm_watchdog.c b/arch/arm/mach-msm/msm_watchdog.c
index c517178..8a9ac36 100644
--- a/arch/arm/mach-msm/msm_watchdog.c
+++ b/arch/arm/mach-msm/msm_watchdog.c
@@ -39,7 +39,7 @@
static void __iomem *msm_tmr0_base;
/* Watchdog pet interval in ms */
-#define PET_DELAY 3000
+#define PET_DELAY 10000
static unsigned long delay_time;
static unsigned long long last_pet;
@@ -317,11 +317,11 @@
/* 32768 ticks = 1 second */
if (machine_is_msm8960_sim()) {
- __raw_writel(32768*8, msm_tmr0_base + WDT0_BARK_TIME);
- __raw_writel(32768*10, msm_tmr0_base + WDT0_BITE_TIME);
+ __raw_writel(32768*15, msm_tmr0_base + WDT0_BARK_TIME);
+ __raw_writel(32768*17, msm_tmr0_base + WDT0_BITE_TIME);
} else {
- __raw_writel(32768*4, msm_tmr0_base + WDT0_BARK_TIME);
- __raw_writel(32768*5, msm_tmr0_base + WDT0_BITE_TIME);
+ __raw_writel(32768*11, msm_tmr0_base + WDT0_BARK_TIME);
+ __raw_writel(32768*12, msm_tmr0_base + WDT0_BITE_TIME);
}
ret = register_pm_notifier(&msm_watchdog_power_notifier);
diff --git a/arch/arm/mach-msm/peripheral-loader.c b/arch/arm/mach-msm/peripheral-loader.c
index c8f0798..dc3b26f 100644
--- a/arch/arm/mach-msm/peripheral-loader.c
+++ b/arch/arm/mach-msm/peripheral-loader.c
@@ -20,6 +20,8 @@
#include <linux/mutex.h>
#include <linux/memblock.h>
+#include <mach/socinfo.h>
+
#include <asm/uaccess.h>
#include <asm/setup.h>
@@ -232,6 +234,10 @@
struct pil_device *pil_d;
void *retval;
+ /* PIL is not yet supported on 8064. */
+ if (cpu_is_apq8064())
+ return NULL;
+
pil = retval = find_peripheral(name);
if (!pil)
return ERR_PTR(-ENODEV);
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index a929659..c831d4b 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -279,6 +279,12 @@
ret = 0;
mode_sysfs_add_cpu_exit:
+ if (!ret) {
+ if (mode && mode->kobj)
+ kobject_del(mode->kobj);
+ kfree(mode);
+ }
+
return ret;
}
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c b/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
index 519d785..6166de2 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_a2dp_in.c
@@ -42,6 +42,7 @@
#include <mach/msm_adsp.h>
#include <mach/msm_memtypes.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -114,6 +115,7 @@
int running;
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
+ char *build_id;
};
static struct audio_a2dp_in the_audio_a2dp_in;
@@ -368,7 +370,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -941,6 +949,8 @@
MM_ERR("failed to register device event listener\n");
goto evt_error;
}
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
file->private_data = audio;
audio->opened = 1;
rc = 0;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c b/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
index f378297..da77140 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_aac_in.c
@@ -39,6 +39,7 @@
#include <mach/qdsp5v2/audpreproc.h>
#include <mach/qdsp5v2/audio_dev_ctl.h>
#include <mach/debug_mm.h>
+#include <mach/socinfo.h>
/* FRAME_NUM must be a power of two */
#define FRAME_NUM (8)
@@ -141,6 +142,7 @@
int running;
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
+ char *build_id;
};
struct audio_frame {
@@ -573,7 +575,14 @@
{
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("build_id[17] = %c", audio->build_id[17]);
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1403,6 +1412,9 @@
MM_DBG("write buf: phy addr 0x%08x kernel addr 0x%08x\n",
audio->out_phys, (int)audio->out_data);
}
+ MM_ERR("trying to get the build id\n");
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
/* Initialize buffer */
audio->out[0].data = audio->out_data + 0;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_acdb.c b/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
index 36ace7f..ec275b4 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_acdb.c
@@ -31,6 +31,7 @@
#include <mach/msm_subsystem_map.h>
#include <mach/qdsp5v2/audio_dev_ctl.h>
#include <mach/qdsp5v2/audpp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/audpreproc.h>
#include <mach/qdsp5v2/qdsp5audppcmdi.h>
#include <mach/qdsp5v2/qdsp5audpreproccmdi.h>
@@ -130,6 +131,7 @@
unsigned long get_blk_paddr;
u8 *get_blk_kvaddr;
struct msm_mapped_buffer *map_v_get_blk;
+ char *build_id;
};
static struct acdb_data acdb_data;
@@ -1109,23 +1111,26 @@
rtc_acdb.set_iid = 0;
rtc_acdb.valid_abid = false;
rtc_acdb.tx_rx_ctl = 0;
- snprintf(name, sizeof name, "get_set_abid");
- get_set_abid_dentry = debugfs_create_file(name,
+ if (acdb_data.build_id[17] == '1') {
+ snprintf(name, sizeof name, "get_set_abid");
+ get_set_abid_dentry = debugfs_create_file(name,
S_IFREG | S_IRUGO | S_IWUGO,
NULL, NULL, &rtc_acdb_debug_fops);
- if (IS_ERR(get_set_abid_dentry)) {
- MM_ERR("SET GET ABID debugfs_create_file failed\n");
- return false;
- }
+ if (IS_ERR(get_set_abid_dentry)) {
+ MM_ERR("SET GET ABID debugfs_create_file failed\n");
+ return false;
+ }
- snprintf(name1, sizeof name1, "get_set_abid_data");
- get_set_abid_data_dentry = debugfs_create_file(name1,
- S_IFREG | S_IRUGO | S_IWUGO,
- NULL, NULL,
- &rtc_acdb_data_debug_fops);
- if (IS_ERR(get_set_abid_data_dentry)) {
- MM_ERR("SET GET ABID DATA debugfs_create_file failed\n");
- return false;
+ snprintf(name1, sizeof name1, "get_set_abid_data");
+ get_set_abid_data_dentry = debugfs_create_file(name1,
+ S_IFREG | S_IRUGO | S_IWUGO,
+ NULL, NULL,
+ &rtc_acdb_data_debug_fops);
+ if (IS_ERR(get_set_abid_data_dentry)) {
+ MM_ERR("SET GET ABID DATA"
+ " debugfs_create_file failed\n");
+ return false;
+ }
}
rtc_read->phys = allocate_contiguous_ebi_nomap(PMEM_RTC_ACDB_QUERY_MEM,
@@ -2332,18 +2337,20 @@
MM_DBG("AUDPREPROC is calibrated"
" with calib_gain_tx\n");
}
- acdb_rmc = get_rmc_blk();
- if (acdb_rmc != NULL) {
- result = afe_config_rmc_block(acdb_rmc);
- if (result) {
- MM_ERR("ACDB=> Failed to send rmc"
- " data to afe\n");
- result = -EINVAL;
- goto done;
+ if (acdb_data.build_id[17] != '0') {
+ acdb_rmc = get_rmc_blk();
+ if (acdb_rmc != NULL) {
+ result = afe_config_rmc_block(acdb_rmc);
+ if (result) {
+ MM_ERR("ACDB=> Failed to send rmc"
+ " data to afe\n");
+ result = -EINVAL;
+ goto done;
+ } else
+ MM_DBG("AFE is calibrated with rmc params\n");
} else
- MM_DBG("AFE is calibrated with rmc params\n");
- } else
- MM_DBG("RMC block was not found\n");
+ MM_DBG("RMC block was not found\n");
+ }
if (!acdb_data.fleuce_feature_status[acdb_data.preproc_stream_id]) {
result = acdb_fill_audpreproc_fluence();
if (!(IS_ERR_VALUE(result))) {
@@ -3050,9 +3057,11 @@
MM_INFO("audpreproc is routed to pseudo device\n");
return result;
}
- if (session_info[stream_id].sampling_freq)
- acdb_data.device_info->sample_rate =
+ if (acdb_data.build_id[17] == '1') {
+ if (session_info[stream_id].sampling_freq)
+ acdb_data.device_info->sample_rate =
session_info[stream_id].sampling_freq;
+ }
if (!(acdb_data.acdb_state & CAL_DATA_READY)) {
result = check_tx_acdb_values_cached();
if (result) {
@@ -3110,17 +3119,19 @@
callback at this scenario we should not access
device information
*/
- if (acdb_data.device_info &&
- session_info[stream_id].sampling_freq) {
- acdb_data.device_info->sample_rate =
+ if (acdb_data.build_id[17] != '0') {
+ if (acdb_data.device_info &&
+ session_info[stream_id].sampling_freq) {
+ acdb_data.device_info->sample_rate =
session_info[stream_id].sampling_freq;
- result = check_tx_acdb_values_cached();
- if (!result) {
- MM_INFO("acdb values for the stream is" \
- " querried from modem");
- acdb_data.acdb_state |= CAL_DATA_READY;
- } else {
- acdb_data.acdb_state &= ~CAL_DATA_READY;
+ result = check_tx_acdb_values_cached();
+ if (!result) {
+ MM_INFO("acdb values for the stream is" \
+ " querried from modem");
+ acdb_data.acdb_state |= CAL_DATA_READY;
+ } else {
+ acdb_data.acdb_state &= ~CAL_DATA_READY;
+ }
}
}
if (acdb_data.preproc_stream_id == 0)
@@ -3195,6 +3206,7 @@
if (result)
goto err4;
+
return result;
err4:
@@ -3276,10 +3288,12 @@
result = acdb_initialize_data();
if (result)
goto done;
-
- result = initialize_modem_acdb();
- if (result < 0)
- MM_ERR("failed to initialize modem ACDB\n");
+ MM_ERR("acdb_data.build_id[17] = %c\n", acdb_data.build_id[17]);
+ if (acdb_data.build_id[17] != '0') {
+ result = initialize_modem_acdb();
+ if (result < 0)
+ MM_ERR("failed to initialize modem ACDB\n");
+ }
while (!kthread_should_stop()) {
MM_DBG("Waiting for call back events\n");
@@ -3375,6 +3389,10 @@
result = -ENODEV;
goto err;
}
+
+ acdb_data.build_id = socinfo_get_build_id();
+ MM_INFO("build id used is = %s\n", acdb_data.build_id);
+
#ifdef CONFIG_DEBUG_FS
/*This is RTC specific INIT used only with debugfs*/
if (!rtc_acdb_init())
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c b/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
index db56a0b..e1af44f 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_amrnb_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
#include <mach/msm_adsp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -104,6 +105,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -337,7 +339,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -854,6 +862,9 @@
MM_ERR("failed to register device event listener\n");
goto evt_error;
}
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
+
file->private_data = audio;
audio->opened = 1;
done:
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c b/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
index ec31b65..c086153 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_evrc_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -136,6 +137,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -558,7 +560,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1461,6 +1469,9 @@
file->private_data = audio;
audio->opened = 1;
audio->out_frame_cnt++;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
+
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c b/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
index 6422dca..7f68c03 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_pcm_in.c
@@ -36,6 +36,7 @@
#include <mach/msm_subsystem_map.h>
#include <mach/msm_adsp.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -120,6 +121,7 @@
int stopped; /* set when stopped, cleared on flush */
int abort; /* set when error, like sample rate mismatch */
int dual_mic_config;
+ char *build_id;
};
static struct audio_in the_audio_in;
@@ -370,7 +372,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -910,6 +918,8 @@
file->private_data = audio;
audio->opened = 1;
rc = 0;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c b/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
index 36fc3dcf..11599f8 100644
--- a/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
+++ b/arch/arm/mach-msm/qdsp5v2/audio_qcelp_in.c
@@ -34,6 +34,7 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/msm_subsystem_map.h>
+#include <mach/socinfo.h>
#include <mach/qdsp5v2/qdsp5audreccmdi.h>
#include <mach/qdsp5v2/qdsp5audrecmsg.h>
#include <mach/qdsp5v2/audpreproc.h>
@@ -139,6 +140,7 @@
int enabled;
int running;
int stopped; /* set when stopped, cleared on flush */
+ char *build_id;
};
struct audio_frame {
@@ -562,7 +564,13 @@
struct audpreproc_audrec_cmd_enc_cfg cmd;
memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ if (audio->build_id[17] == '1') {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG_2;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG_2 command");
+ } else {
+ cmd.cmd_id = AUDPREPROC_AUDREC_CMD_ENC_CFG;
+ MM_ERR("sending AUDPREPROC_AUDREC_CMD_ENC_CFG command");
+ }
cmd.stream_id = audio->enc_id;
if (enable)
@@ -1466,6 +1474,8 @@
file->private_data = audio;
audio->opened = 1;
audio->out_frame_cnt++;
+ audio->build_id = socinfo_get_build_id();
+ MM_ERR("build id used is = %s\n", audio->build_id);
done:
mutex_unlock(&audio->lock);
return rc;
diff --git a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c b/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
index 11fff28..cd1fe4c 100644
--- a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
+++ b/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
@@ -28,17 +28,6 @@
#include <sound/dai.h>
#include "q6core.h"
-#define NUM_FRA_IN_BLOCK 192
-#define NUM_SAMP_PER_CH_PER_AC3_FRAME 1536
-#define AC3_REP_PER 1536 /* num of 60958 Frames */
-#define FRAME_60958_SZ 8 /* bytes */
-#define PREABLE_61937_SZ_16_BIT 4 /* in 16 bit words */
-
-
-#define MAX_AC3_FRA_SZ_16_BIT 1920 /* in 16 bit words */
-#define DMA_PERIOD_SZ (AC3_REP_PER * FRAME_60958_SZ)
-#define DMA_BUF_SZ (DMA_PERIOD_SZ * 2)
-#define USER_BUF_SZ DMA_PERIOD_SZ
#define DMA_ALLOC_BUF_SZ (SZ_4K * 6)
#define HDMI_AUDIO_FIFO_WATER_MARK 4
@@ -62,6 +51,7 @@
u32 dma_ch;
wait_queue_head_t wait;
u32 config;
+ u32 dma_period_sz;
};
static struct lpa_if *lpa_if_ptr;
@@ -127,12 +117,11 @@
dma_params.src_start = lpa_if->buffer_phys;
dma_params.buffer = lpa_if->buffer;
- dma_params.buffer_size = DMA_BUF_SZ;
- dma_params.period_size = DMA_PERIOD_SZ;
+ dma_params.buffer_size = lpa_if->dma_period_sz * 2;
+ dma_params.period_size = lpa_if->dma_period_sz;
dma_params.channels = 2;
lpa_if->dma_ch = 0;
-
dai_set_params(lpa_if->dma_ch, &dma_params);
register_dma_irq_handler(lpa_if->dma_ch, lpa_if_irq, (void *)lpa_if);
@@ -195,7 +184,33 @@
rc = -EFAULT;
}
break;
+ case AUDIO_SET_CONFIG:
+ pr_debug("AUDIO_SET_CONFIG\n");
+ if (copy_from_user(&lpa_if->dma_period_sz, (void *) arg,
+ sizeof(unsigned int))) {
+ pr_debug("%s:failed to copy from user\n", __func__);
+ rc = -EFAULT;
+ }
+ if (lpa_if->dma_period_sz > DMA_ALLOC_BUF_SZ) {
+ pr_err("Dma buffer size greater than allocated size\n");
+ return -EINVAL;
+ }
+ pr_debug("Dma_period_sz %d\n", lpa_if->dma_period_sz);
+ lpa_if->cfg.buffer_count = 2;
+ lpa_if->cfg.buffer_size = lpa_if->dma_period_sz * 2;
+ lpa_if->audio_buf[0].phys = lpa_if->buffer_phys;
+ lpa_if->audio_buf[0].data = lpa_if->buffer;
+ lpa_if->audio_buf[0].size = lpa_if->dma_period_sz;
+ lpa_if->audio_buf[0].used = 0;
+
+ lpa_if->audio_buf[1].phys =
+ lpa_if->buffer_phys + lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].data =
+ lpa_if->buffer + lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].size = lpa_if->dma_period_sz;
+ lpa_if->audio_buf[1].used = 0;
+ break;
default:
pr_err("UnKnown Ioctl\n");
rc = -EINVAL;
@@ -209,26 +224,9 @@
static int lpa_if_open(struct inode *inode, struct file *file)
{
- struct lpa_if *lpa_if;
-
pr_debug("\n");
file->private_data = lpa_if_ptr;
- lpa_if = lpa_if_ptr;
-
- lpa_if->cfg.buffer_count = 2;
- lpa_if->cfg.buffer_size = USER_BUF_SZ;
-
- lpa_if->audio_buf[0].phys = lpa_if->buffer_phys;
- lpa_if->audio_buf[0].data = lpa_if->buffer;
- lpa_if->audio_buf[0].size = DMA_PERIOD_SZ;
- lpa_if->audio_buf[0].used = 0;
-
- lpa_if->audio_buf[1].phys = lpa_if->buffer_phys + DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].data = lpa_if->buffer + DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].size = DMA_PERIOD_SZ;
- lpa_if->audio_buf[1].used = 0;
-
dma_buf_index = 0;
core_req_bus_bandwith(AUDIO_IF_BUS_ID, 100000, 0);
@@ -287,8 +285,8 @@
xfer = count;
- if (xfer > USER_BUF_SZ)
- xfer = USER_BUF_SZ;
+ if (xfer > lpa_if->dma_period_sz)
+ xfer = lpa_if->dma_period_sz;
if (copy_from_user(ab->data, buf, xfer)) {
pr_err("copy from user failed\n");
diff --git a/arch/arm/mach-msm/restart.c b/arch/arm/mach-msm/restart.c
index 7ddcde7..00be696 100644
--- a/arch/arm/mach-msm/restart.c
+++ b/arch/arm/mach-msm/restart.c
@@ -33,11 +33,12 @@
#include <mach/irqs.h>
#include <mach/scm.h>
#include "msm_watchdog.h"
+#include "timer.h"
-#define WDT0_RST (MSM_TMR0_BASE + 0x38)
-#define WDT0_EN (MSM_TMR0_BASE + 0x40)
-#define WDT0_BARK_TIME (MSM_TMR0_BASE + 0x4C)
-#define WDT0_BITE_TIME (MSM_TMR0_BASE + 0x5C)
+#define WDT0_RST 0x38
+#define WDT0_EN 0x40
+#define WDT0_BARK_TIME 0x4C
+#define WDT0_BITE_TIME 0x5C
#define PSHOLD_CTL_SU (MSM_TLMM_BASE + 0x820)
@@ -50,6 +51,7 @@
void *restart_reason;
int pmic_reset_irq;
+static void __iomem *msm_tmr0_base;
#ifdef CONFIG_MSM_DLOAD_MODE
static int in_panic;
@@ -218,7 +220,7 @@
}
}
- __raw_writel(0, WDT0_EN);
+ __raw_writel(0, msm_tmr0_base + WDT0_EN);
if (!(machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())) {
mb();
__raw_writel(0, PSHOLD_CTL_SU); /* Actually reset the chip */
@@ -226,10 +228,10 @@
pr_notice("PS_HOLD didn't work, falling back to watchdog\n");
}
- __raw_writel(1, WDT0_RST);
- __raw_writel(5*0x31F3, WDT0_BARK_TIME);
- __raw_writel(0x31F3, WDT0_BITE_TIME);
- __raw_writel(1, WDT0_EN);
+ __raw_writel(1, msm_tmr0_base + WDT0_RST);
+ __raw_writel(5*0x31F3, msm_tmr0_base + WDT0_BARK_TIME);
+ __raw_writel(0x31F3, msm_tmr0_base + WDT0_BITE_TIME);
+ __raw_writel(1, msm_tmr0_base + WDT0_EN);
mdelay(10000);
printk(KERN_ERR "Restarting has failed\n");
@@ -246,6 +248,7 @@
/* Reset detection is switched on below.*/
set_dload_mode(1);
#endif
+ msm_tmr0_base = msm_timer_get_timer0_base();
restart_reason = MSM_IMEM_BASE + RESTART_REASON_ADDR;
pm_power_off = msm_power_off;
diff --git a/arch/arm/mach-msm/rpm-regulator-8660.c b/arch/arm/mach-msm/rpm-regulator-8660.c
new file mode 100644
index 0000000..6c4a9ad
--- /dev/null
+++ b/arch/arm/mach-msm/rpm-regulator-8660.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include "rpm-regulator-private.h"
+
+/* RPM regulator request formats */
+static struct rpm_vreg_parts ldo_parts = {
+ .request_len = 2,
+ .mV = REQUEST_MEMBER(0, 0x00000FFF, 0),
+ .ip = REQUEST_MEMBER(0, 0x00FFF000, 12),
+ .fm = REQUEST_MEMBER(0, 0x03000000, 24),
+ .pc = REQUEST_MEMBER(0, 0x3C000000, 26),
+ .pf = REQUEST_MEMBER(0, 0xC0000000, 30),
+ .pd = REQUEST_MEMBER(1, 0x00000001, 0),
+ .ia = REQUEST_MEMBER(1, 0x00001FFE, 1),
+};
+
+static struct rpm_vreg_parts smps_parts = {
+ .request_len = 2,
+ .mV = REQUEST_MEMBER(0, 0x00000FFF, 0),
+ .ip = REQUEST_MEMBER(0, 0x00FFF000, 12),
+ .fm = REQUEST_MEMBER(0, 0x03000000, 24),
+ .pc = REQUEST_MEMBER(0, 0x3C000000, 26),
+ .pf = REQUEST_MEMBER(0, 0xC0000000, 30),
+ .pd = REQUEST_MEMBER(1, 0x00000001, 0),
+ .ia = REQUEST_MEMBER(1, 0x00001FFE, 1),
+ .freq = REQUEST_MEMBER(1, 0x001FE000, 13),
+ .freq_clk_src = REQUEST_MEMBER(1, 0x00600000, 21),
+};
+
+static struct rpm_vreg_parts switch_parts = {
+ .request_len = 1,
+ .enable_state = REQUEST_MEMBER(0, 0x00000001, 0),
+ .pd = REQUEST_MEMBER(0, 0x00000002, 1),
+ .pc = REQUEST_MEMBER(0, 0x0000003C, 2),
+ .pf = REQUEST_MEMBER(0, 0x000000C0, 6),
+ .hpm = REQUEST_MEMBER(0, 0x00000300, 8),
+};
+
+static struct rpm_vreg_parts ncp_parts = {
+ .request_len = 1,
+ .mV = REQUEST_MEMBER(0, 0x00000FFF, 0),
+ .enable_state = REQUEST_MEMBER(0, 0x00001000, 12),
+ .comp_mode = REQUEST_MEMBER(0, 0x00002000, 13),
+ .freq = REQUEST_MEMBER(0, 0x003FC000, 14),
+};
+
+/* Physically available PMIC regulator voltage setpoint ranges */
+static struct vreg_range pldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+ VOLTAGE_RANGE(3100000, 4900000, 50000),
+};
+
+static struct vreg_range nldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range smps_ranges[] = {
+ VOLTAGE_RANGE( 375000, 737500, 12500),
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+};
+
+static struct vreg_range ftsmps_ranges[] = {
+ VOLTAGE_RANGE( 350000, 650000, 50000),
+ VOLTAGE_RANGE( 700000, 1400000, 12500),
+ VOLTAGE_RANGE(1500000, 3300000, 50000),
+};
+
+static struct vreg_range ncp_ranges[] = {
+ VOLTAGE_RANGE(1500000, 3050000, 50000),
+};
+
+static struct vreg_set_points pldo_set_points = SET_POINTS(pldo_ranges);
+static struct vreg_set_points nldo_set_points = SET_POINTS(nldo_ranges);
+static struct vreg_set_points smps_set_points = SET_POINTS(smps_ranges);
+static struct vreg_set_points ftsmps_set_points = SET_POINTS(ftsmps_ranges);
+static struct vreg_set_points ncp_set_points = SET_POINTS(ncp_ranges);
+
+static struct vreg_set_points *all_set_points[] = {
+ &pldo_set_points,
+ &nldo_set_points,
+ &smps_set_points,
+ &ftsmps_set_points,
+ &ncp_set_points,
+};
+
+#define LDO(_vreg_id, _rpm_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_##_vreg_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_##_rpm_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_##_rpm_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8660_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_LDO, \
+ .set_points = &_ranges##_set_points, \
+ .part = &ldo_parts, \
+ .id = RPM_VREG_ID_##_vreg_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define SMPS(_vreg_id, _rpm_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_##_vreg_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_##_rpm_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_##_rpm_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8660_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_SMPS, \
+ .set_points = &_ranges##_set_points, \
+ .part = &smps_parts, \
+ .id = RPM_VREG_ID_##_vreg_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define LVS(_vreg_id, _rpm_id, _name, _name_pc) \
+ [RPM_VREG_ID_##_vreg_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_##_rpm_id, }, \
+ [1] = { .id = -1, }, \
+ }, \
+ .type = RPM_REGULATOR_TYPE_VS, \
+ .part = &switch_parts, \
+ .id = RPM_VREG_ID_##_vreg_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define MVS(_vreg_id, _rpm_id, _name, _name_pc) \
+ LVS(_vreg_id, _rpm_id, _name, _name_pc)
+
+#define NCP(_vreg_id, _rpm_id, _name, _name_pc) \
+ [RPM_VREG_ID_##_vreg_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_##_rpm_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_##_rpm_id##_1, }, \
+ }, \
+ .type = RPM_REGULATOR_TYPE_NCP, \
+ .set_points = &ncp_set_points, \
+ .part = &ncp_parts, \
+ .id = RPM_VREG_ID_##_vreg_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+static struct vreg vregs[] = {
+ LDO(PM8058_L0, LDO0, "8058_l0", "8058_l0_pc", nldo, LDO_150),
+ LDO(PM8058_L1, LDO1, "8058_l1", "8058_l1_pc", nldo, LDO_300),
+ LDO(PM8058_L2, LDO2, "8058_l2", "8058_l2_pc", pldo, LDO_300),
+ LDO(PM8058_L3, LDO3, "8058_l3", "8058_l3_pc", pldo, LDO_150),
+ LDO(PM8058_L4, LDO4, "8058_l4", "8058_l4_pc", pldo, LDO_50),
+ LDO(PM8058_L5, LDO5, "8058_l5", "8058_l5_pc", pldo, LDO_300),
+ LDO(PM8058_L6, LDO6, "8058_l6", "8058_l6_pc", pldo, LDO_50),
+ LDO(PM8058_L7, LDO7, "8058_l7", "8058_l7_pc", pldo, LDO_50),
+ LDO(PM8058_L8, LDO8, "8058_l8", "8058_l8_pc", pldo, LDO_300),
+ LDO(PM8058_L9, LDO9, "8058_l9", "8058_l9_pc", pldo, LDO_300),
+ LDO(PM8058_L10, LDO10, "8058_l10", "8058_l10_pc", pldo, LDO_300),
+ LDO(PM8058_L11, LDO11, "8058_l11", "8058_l11_pc", pldo, LDO_150),
+ LDO(PM8058_L12, LDO12, "8058_l12", "8058_l12_pc", pldo, LDO_150),
+ LDO(PM8058_L13, LDO13, "8058_l13", "8058_l13_pc", pldo, LDO_300),
+ LDO(PM8058_L14, LDO14, "8058_l14", "8058_l14_pc", pldo, LDO_300),
+ LDO(PM8058_L15, LDO15, "8058_l15", "8058_l15_pc", pldo, LDO_300),
+ LDO(PM8058_L16, LDO16, "8058_l16", "8058_l16_pc", pldo, LDO_300),
+ LDO(PM8058_L17, LDO17, "8058_l17", "8058_l17_pc", pldo, LDO_150),
+ LDO(PM8058_L18, LDO18, "8058_l18", "8058_l18_pc", pldo, LDO_150),
+ LDO(PM8058_L19, LDO19, "8058_l19", "8058_l19_pc", pldo, LDO_150),
+ LDO(PM8058_L20, LDO20, "8058_l20", "8058_l20_pc", pldo, LDO_150),
+ LDO(PM8058_L21, LDO21, "8058_l21", "8058_l21_pc", nldo, LDO_150),
+ LDO(PM8058_L22, LDO22, "8058_l22", "8058_l22_pc", nldo, LDO_300),
+ LDO(PM8058_L23, LDO23, "8058_l23", "8058_l23_pc", nldo, LDO_300),
+ LDO(PM8058_L24, LDO24, "8058_l24", "8058_l24_pc", nldo, LDO_150),
+ LDO(PM8058_L25, LDO25, "8058_l25", "8058_l25_pc", nldo, LDO_150),
+
+ SMPS(PM8058_S0, SMPS0, "8058_s0", "8058_s0_pc", smps, SMPS),
+ SMPS(PM8058_S1, SMPS1, "8058_s1", "8058_s1_pc", smps, SMPS),
+ SMPS(PM8058_S2, SMPS2, "8058_s2", "8058_s2_pc", smps, SMPS),
+ SMPS(PM8058_S3, SMPS3, "8058_s3", "8058_s3_pc", smps, SMPS),
+ SMPS(PM8058_S4, SMPS4, "8058_s4", "8058_s4_pc", smps, SMPS),
+
+ LVS(PM8058_LVS0, LVS0, "8058_lvs0", "8058_lvs0_pc"),
+ LVS(PM8058_LVS1, LVS1, "8058_lvs1", "8058_lvs1_pc"),
+
+ NCP(PM8058_NCP, NCP, "8058_ncp", NULL),
+
+ LDO(PM8901_L0, LDO0B, "8901_l0", "8901_l0_pc", nldo, LDO_300),
+ LDO(PM8901_L1, LDO1B, "8901_l1", "8901_l1_pc", pldo, LDO_300),
+ LDO(PM8901_L2, LDO2B, "8901_l2", "8901_l2_pc", pldo, LDO_300),
+ LDO(PM8901_L3, LDO3B, "8901_l3", "8901_l3_pc", pldo, LDO_300),
+ LDO(PM8901_L4, LDO4B, "8901_l4", "8901_l4_pc", pldo, LDO_300),
+ LDO(PM8901_L5, LDO5B, "8901_l5", "8901_l5_pc", pldo, LDO_300),
+ LDO(PM8901_L6, LDO6B, "8901_l6", "8901_l6_pc", pldo, LDO_300),
+
+ SMPS(PM8901_S0, SMPS0B, "8901_s0", "8901_s0_pc", ftsmps, FTSMPS),
+ SMPS(PM8901_S1, SMPS1B, "8901_s1", "8901_s1_pc", ftsmps, FTSMPS),
+ SMPS(PM8901_S2, SMPS2B, "8901_s2", "8901_s2_pc", ftsmps, FTSMPS),
+ SMPS(PM8901_S3, SMPS3B, "8901_s3", "8901_s3_pc", ftsmps, FTSMPS),
+ SMPS(PM8901_S4, SMPS4B, "8901_s4", "8901_s4_pc", ftsmps, FTSMPS),
+
+ LVS(PM8901_LVS0, LVS0B, "8901_lvs0", "8901_lvs0_pc"),
+ LVS(PM8901_LVS1, LVS1B, "8901_lvs1", "8901_lvs1_pc"),
+ LVS(PM8901_LVS2, LVS2B, "8901_lvs2", "8901_lvs2_pc"),
+ LVS(PM8901_LVS3, LVS3B, "8901_lvs3", "8901_lvs3_pc"),
+
+ MVS(PM8901_MVS0, MVS, "8901_mvs0", "8901_mvs0_pc"),
+};
+
+static const char *pin_func_label[] = {
+ [RPM_VREG_PIN_FN_8660_ENABLE] = "on/off",
+ [RPM_VREG_PIN_FN_8660_MODE] = "HPM/LPM",
+ [RPM_VREG_PIN_FN_8660_SLEEP_B] = "sleep_b",
+ [RPM_VREG_PIN_FN_8660_NONE] = "none",
+};
+
+static const char *force_mode_label[] = {
+ [RPM_VREG_FORCE_MODE_8660_NONE] = "none",
+ [RPM_VREG_FORCE_MODE_8660_LPM] = "LPM",
+ [RPM_VREG_FORCE_MODE_8660_HPM] = "HPM",
+};
+
+static const char *pin_control_label[] = {
+ " A0",
+ " A1",
+ " D0",
+ " D1",
+};
+
+static int is_real_id(int id)
+{
+ return (id >= 0) && (id <= RPM_VREG_ID_8660_MAX_REAL);
+}
+
+static int pc_id_to_real_id(int id)
+{
+ int real_id;
+
+ if (id >= RPM_VREG_ID_PM8058_L0_PC && id <= RPM_VREG_ID_PM8058_LVS1_PC)
+ real_id = id - RPM_VREG_ID_PM8058_L0_PC + RPM_VREG_ID_PM8058_L0;
+ else
+ real_id = id - RPM_VREG_ID_PM8901_L0_PC + RPM_VREG_ID_PM8901_L0;
+
+ return real_id;
+}
+
+static struct vreg_config config = {
+ .vregs = vregs,
+ .vregs_len = ARRAY_SIZE(vregs),
+
+ .vreg_id_min = RPM_VREG_ID_PM8058_L0,
+ .vreg_id_max = RPM_VREG_ID_8660_MAX,
+
+ .pin_func_none = RPM_VREG_PIN_FN_8660_NONE,
+ .pin_func_sleep_b = RPM_VREG_PIN_FN_8660_SLEEP_B,
+
+ .mode_lpm = REGULATOR_MODE_IDLE,
+ .mode_hpm = REGULATOR_MODE_NORMAL,
+
+ .set_points = all_set_points,
+ .set_points_len = ARRAY_SIZE(all_set_points),
+
+ .label_pin_ctrl = pin_control_label,
+ .label_pin_ctrl_len = ARRAY_SIZE(pin_control_label),
+ .label_pin_func = pin_func_label,
+ .label_pin_func_len = ARRAY_SIZE(pin_func_label),
+ .label_force_mode = force_mode_label,
+ .label_force_mode_len = ARRAY_SIZE(force_mode_label),
+
+ .is_real_id = is_real_id,
+ .pc_id_to_real_id = pc_id_to_real_id,
+
+ .use_legacy_optimum_mode = 1,
+ .ia_follows_ip = 1,
+};
+
+struct vreg_config *get_config_8660(void)
+{
+ return &config;
+}
diff --git a/arch/arm/mach-msm/rpm-regulator-8960.c b/arch/arm/mach-msm/rpm-regulator-8960.c
index 52cc77d..8726ed4 100644
--- a/arch/arm/mach-msm/rpm-regulator-8960.c
+++ b/arch/arm/mach-msm/rpm-regulator-8960.c
@@ -13,84 +13,10 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/driver.h>
-#include <mach/rpm.h>
-#include <mach/rpm-regulator.h>
-#include <mach/socinfo.h>
+#include "rpm-regulator-private.h"
-#include "rpm_resources.h"
-
-/* Debug Definitions */
-
-enum {
- MSM_RPM_VREG_DEBUG_REQUEST = BIT(0),
- MSM_RPM_VREG_DEBUG_VOTE = BIT(1),
- MSM_RPM_VREG_DEBUG_DUPLICATE = BIT(2),
- MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG = BIT(3),
-};
-
-static int msm_rpm_vreg_debug_mask;
-module_param_named(
- debug_mask, msm_rpm_vreg_debug_mask, int, S_IRUSR | S_IWUSR
-);
-
-#define REGULATOR_TYPE_LDO 0
-#define REGULATOR_TYPE_SMPS 1
-#define REGULATOR_TYPE_VS 2
-#define REGULATOR_TYPE_NCP 3
-
-#define MICRO_TO_MILLI(uV) ((uV) / 1000)
-#define MILLI_TO_MICRO(mV) ((mV) * 1000)
-
-#define SET_PART(_vreg, _part, _val) \
- _vreg->req[_vreg->part->_part.word].value \
- = (_vreg->req[_vreg->part->_part.word].value \
- & ~vreg->part->_part.mask) \
- | (((_val) << vreg->part->_part.shift) & vreg->part->_part.mask)
-
-#define GET_PART(_vreg, _part) \
- ((_vreg->req[_vreg->part->_part.word].value & vreg->part->_part.mask) \
- >> vreg->part->_part.shift)
-
-struct request_member {
- int word;
- unsigned int mask;
- int shift;
-};
-
-struct rpm_vreg_parts {
- struct request_member mV; /* voltage: used if voltage is in mV */
- struct request_member uV; /* voltage: used if voltage is in uV */
- struct request_member ip; /* peak current in mA */
- struct request_member pd; /* pull down enable */
- struct request_member ia; /* average current in mA */
- struct request_member fm; /* force mode */
- struct request_member pm; /* power mode */
- struct request_member pc; /* pin control */
- struct request_member pf; /* pin function */
- struct request_member enable_state; /* NCP and switch */
- struct request_member comp_mode; /* NCP */
- struct request_member freq; /* frequency: NCP and SMPS */
- struct request_member freq_clk_src; /* clock source: SMPS */
- struct request_member hpm; /* switch: control OCP ans SS */
- int request_len;
-};
-
-#define REQUEST_MEMBER(_word, _mask, _shift) \
- { \
- .word = _word, \
- .mask = _mask, \
- .shift = _shift, \
- }
-
-struct rpm_vreg_parts ldo_parts = {
+/* RPM regulator request formats */
+static struct rpm_vreg_parts ldo_parts = {
.request_len = 2,
.uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
.pd = REQUEST_MEMBER(0, 0x00800000, 23),
@@ -101,7 +27,7 @@
.fm = REQUEST_MEMBER(1, 0x00700000, 20),
};
-struct rpm_vreg_parts smps_parts = {
+static struct rpm_vreg_parts smps_parts = {
.request_len = 2,
.uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
.pd = REQUEST_MEMBER(0, 0x00800000, 23),
@@ -115,7 +41,7 @@
.freq_clk_src = REQUEST_MEMBER(1, 0x60000000, 29),
};
-struct rpm_vreg_parts switch_parts = {
+static struct rpm_vreg_parts switch_parts = {
.request_len = 1,
.enable_state = REQUEST_MEMBER(0, 0x00000001, 0),
.pd = REQUEST_MEMBER(0, 0x00000002, 1),
@@ -124,7 +50,7 @@
.hpm = REQUEST_MEMBER(0, 0x00000C00, 10),
};
-struct rpm_vreg_parts ncp_parts = {
+static struct rpm_vreg_parts ncp_parts = {
.request_len = 1,
.uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
.enable_state = REQUEST_MEMBER(0, 0x00800000, 23),
@@ -132,26 +58,7 @@
.freq = REQUEST_MEMBER(0, 0x3E000000, 25),
};
-struct vreg_range {
- int min_uV;
- int max_uV;
- int step_uV;
- unsigned n_voltages;
-};
-
-struct vreg_set_points {
- struct vreg_range *range;
- int count;
- unsigned n_voltages;
-};
-
-#define VOLTAGE_RANGE(_min_uV, _max_uV, _step_uV) \
- { \
- .min_uV = _min_uV, \
- .max_uV = _max_uV, \
- .step_uV = _step_uV, \
- }
-
+/* Physically available PMIC regulator voltage setpoint ranges */
static struct vreg_range pldo_ranges[] = {
VOLTAGE_RANGE( 750000, 1487500, 12500),
VOLTAGE_RANGE(1500000, 3075000, 25000),
@@ -183,12 +90,6 @@
VOLTAGE_RANGE(1500000, 3050000, 50000),
};
-#define SET_POINTS(_ranges) \
-{ \
- .range = _ranges, \
- .count = ARRAY_SIZE(_ranges), \
-};
-
static struct vreg_set_points pldo_set_points = SET_POINTS(pldo_ranges);
static struct vreg_set_points nldo_set_points = SET_POINTS(nldo_ranges);
static struct vreg_set_points nldo1200_set_points = SET_POINTS(nldo1200_ranges);
@@ -196,1217 +97,164 @@
static struct vreg_set_points ftsmps_set_points = SET_POINTS(ftsmps_ranges);
static struct vreg_set_points ncp_set_points = SET_POINTS(ncp_ranges);
-/*
- * This is used when voting for LPM or HPM by subtracting or adding to the
- * hpm_min_load of a regulator. It has units of uA.
- */
-#define LOAD_THRESHOLD_STEP 1000
-
-/* This is the maximum uA load that can be passed to the RPM. */
-#define MAX_POSSIBLE_LOAD (MILLI_TO_MICRO(0xFFF))
-
-struct vreg {
- struct msm_rpm_iv_pair req[2];
- struct msm_rpm_iv_pair prev_active_req[2];
- struct msm_rpm_iv_pair prev_sleep_req[2];
- struct rpm_regulator_init_data pdata;
- struct regulator_dev *rdev;
- struct regulator_dev *rdev_pc;
- const char *name;
- struct vreg_set_points *set_points;
- struct rpm_vreg_parts *part;
- int type;
- enum rpm_vreg_id id;
- struct mutex pc_lock;
- int save_uV;
- int mode;
- bool is_enabled;
- bool is_enabled_pc;
- const int hpm_min_load;
- int active_min_uV_vote[RPM_VREG_VOTER_COUNT];
- int sleep_min_uV_vote[RPM_VREG_VOTER_COUNT];
-
+static struct vreg_set_points *all_set_points[] = {
+ &pldo_set_points,
+ &nldo_set_points,
+ &nldo1200_set_points,
+ &smps_set_points,
+ &ftsmps_set_points,
+ &ncp_set_points,
};
-#define LDO(_id, _ranges, _hpm_min_load) \
+#define LDO(_id, _name, _name_pc, _ranges, _hpm_min_load) \
[RPM_VREG_ID_PM8921_##_id] = { \
.req = { \
[0] = { .id = MSM_RPM_ID_PM8921_##_id##_0, }, \
[1] = { .id = MSM_RPM_ID_PM8921_##_id##_1, }, \
}, \
- .hpm_min_load = RPM_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
- .type = REGULATOR_TYPE_LDO, \
+ .hpm_min_load = RPM_VREG_8960_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_LDO, \
.set_points = &_ranges##_set_points, \
.part = &ldo_parts, \
.id = RPM_VREG_ID_PM8921_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
}
-#define SMPS(_id, _ranges, _hpm_min_load) \
+#define SMPS(_id, _name, _name_pc, _ranges, _hpm_min_load) \
[RPM_VREG_ID_PM8921_##_id] = { \
.req = { \
[0] = { .id = MSM_RPM_ID_PM8921_##_id##_0, }, \
[1] = { .id = MSM_RPM_ID_PM8921_##_id##_1, }, \
}, \
- .hpm_min_load = RPM_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
- .type = REGULATOR_TYPE_SMPS, \
+ .hpm_min_load = RPM_VREG_8960_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_SMPS, \
.set_points = &_ranges##_set_points, \
.part = &smps_parts, \
.id = RPM_VREG_ID_PM8921_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
}
-#define LVS(_id) \
+#define LVS(_id, _name, _name_pc) \
[RPM_VREG_ID_PM8921_##_id] = { \
.req = { \
[0] = { .id = MSM_RPM_ID_PM8921_##_id, }, \
[1] = { .id = -1, }, \
}, \
- .type = REGULATOR_TYPE_VS, \
+ .type = RPM_REGULATOR_TYPE_VS, \
.part = &switch_parts, \
.id = RPM_VREG_ID_PM8921_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
}
-#define MVS(_vreg_id, _rpm_id) \
+#define MVS(_vreg_id, _name, _name_pc, _rpm_id) \
[RPM_VREG_ID_PM8921_##_vreg_id] = { \
.req = { \
[0] = { .id = MSM_RPM_ID_##_rpm_id, }, \
[1] = { .id = -1, }, \
}, \
- .type = REGULATOR_TYPE_VS, \
+ .type = RPM_REGULATOR_TYPE_VS, \
.part = &switch_parts, \
.id = RPM_VREG_ID_PM8921_##_vreg_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
}
-#define NCP(_id) \
+#define NCP(_id, _name, _name_pc) \
[RPM_VREG_ID_PM8921_##_id] = { \
.req = { \
[0] = { .id = MSM_RPM_ID_##_id##_0, }, \
[1] = { .id = MSM_RPM_ID_##_id##_1, }, \
}, \
- .type = REGULATOR_TYPE_NCP, \
+ .type = RPM_REGULATOR_TYPE_NCP, \
.set_points = &ncp_set_points, \
.part = &ncp_parts, \
.id = RPM_VREG_ID_PM8921_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
}
static struct vreg vregs[] = {
- LDO(L1, nldo, LDO_150),
- LDO(L2, nldo, LDO_150),
- LDO(L3 , pldo, LDO_150),
- LDO(L4, pldo, LDO_50),
- LDO(L5, pldo, LDO_300),
- LDO(L6, pldo, LDO_600),
- LDO(L7, pldo, LDO_150),
- LDO(L8, pldo, LDO_300),
- LDO(L9, pldo, LDO_300),
- LDO(L10, pldo, LDO_600),
- LDO(L11, pldo, LDO_150),
- LDO(L12, nldo, LDO_150),
- LDO(L14, pldo, LDO_50),
- LDO(L15, pldo, LDO_150),
- LDO(L16, pldo, LDO_300),
- LDO(L17, pldo, LDO_150),
- LDO(L18, nldo, LDO_150),
- LDO(L21, pldo, LDO_150),
- LDO(L22, pldo, LDO_150),
- LDO(L23, pldo, LDO_150),
- LDO(L24, nldo1200, LDO_1200),
- LDO(L25, nldo1200, LDO_1200),
- LDO(L26, nldo1200, LDO_1200),
- LDO(L27, nldo1200, LDO_1200),
- LDO(L28, nldo1200, LDO_1200),
- LDO(L29, pldo, LDO_150),
+ LDO(L1, "8921_l1", "8921_l1_pc", nldo, LDO_150),
+ LDO(L2, "8921_l2", "8921_l2_pc", nldo, LDO_150),
+ LDO(L3, "8921_l3", "8921_l3_pc", pldo, LDO_150),
+ LDO(L4, "8921_l4", "8921_l4_pc", pldo, LDO_50),
+ LDO(L5, "8921_l5", "8921_l5_pc", pldo, LDO_300),
+ LDO(L6, "8921_l6", "8921_l6_pc", pldo, LDO_600),
+ LDO(L7, "8921_l7", "8921_l7_pc", pldo, LDO_150),
+ LDO(L8, "8921_l8", "8921_l8_pc", pldo, LDO_300),
+ LDO(L9, "8921_l9", "8921_l9_pc", pldo, LDO_300),
+ LDO(L10, "8921_l10", "8921_l10_pc", pldo, LDO_600),
+ LDO(L11, "8921_l11", "8921_l11_pc", pldo, LDO_150),
+ LDO(L12, "8921_l12", "8921_l12_pc", nldo, LDO_150),
+ LDO(L14, "8921_l14", "8921_l14_pc", pldo, LDO_50),
+ LDO(L15, "8921_l15", "8921_l15_pc", pldo, LDO_150),
+ LDO(L16, "8921_l16", "8921_l16_pc", pldo, LDO_300),
+ LDO(L17, "8921_l17", "8921_l17_pc", pldo, LDO_150),
+ LDO(L18, "8921_l18", "8921_l18_pc", nldo, LDO_150),
+ LDO(L21, "8921_l21", "8921_l21_pc", pldo, LDO_150),
+ LDO(L22, "8921_l22", "8921_l22_pc", pldo, LDO_150),
+ LDO(L23, "8921_l23", "8921_l23_pc", pldo, LDO_150),
+ LDO(L24, "8921_l24", NULL, nldo1200, LDO_1200),
+ LDO(L25, "8921_l25", NULL, nldo1200, LDO_1200),
+ LDO(L26, "8921_l26", NULL, nldo1200, LDO_1200),
+ LDO(L27, "8921_l27", NULL, nldo1200, LDO_1200),
+ LDO(L28, "8921_l28", NULL, nldo1200, LDO_1200),
+ LDO(L29, "8921_l29", "8921_l29_pc", pldo, LDO_150),
- SMPS(S1, smps, SMPS_1500),
- SMPS(S2, smps, SMPS_1500),
- SMPS(S3, smps, SMPS_1500),
- SMPS(S4, smps, SMPS_1500),
- SMPS(S5, ftsmps, SMPS_2000),
- SMPS(S6, ftsmps, SMPS_2000),
- SMPS(S7, smps, SMPS_1500),
- SMPS(S8, smps, SMPS_1500),
+ SMPS(S1, "8921_s1", "8921_s1_pc", smps, SMPS_1500),
+ SMPS(S2, "8921_s2", "8921_s2_pc", smps, SMPS_1500),
+ SMPS(S3, "8921_s3", "8921_s3_pc", smps, SMPS_1500),
+ SMPS(S4, "8921_s4", "8921_s4_pc", smps, SMPS_1500),
+ SMPS(S5, "8921_s5", NULL, ftsmps, SMPS_2000),
+ SMPS(S6, "8921_s6", NULL, ftsmps, SMPS_2000),
+ SMPS(S7, "8921_s7", "8921_s7_pc", smps, SMPS_1500),
+ SMPS(S8, "8921_s8", "8921_s8_pc", smps, SMPS_1500),
- LVS(LVS1),
- LVS(LVS2),
- LVS(LVS3),
- LVS(LVS4),
- LVS(LVS5),
- LVS(LVS6),
- LVS(LVS7),
- MVS(USB_OTG, USB_OTG_SWITCH),
- MVS(HDMI_MVS, HDMI_SWITCH),
+ LVS(LVS1, "8921_lvs1", "8921_lvs1_pc"),
+ LVS(LVS2, "8921_lvs2", NULL),
+ LVS(LVS3, "8921_lvs3", "8921_lvs3_pc"),
+ LVS(LVS4, "8921_lvs4", "8921_lvs4_pc"),
+ LVS(LVS5, "8921_lvs5", "8921_lvs5_pc"),
+ LVS(LVS6, "8921_lvs6", "8921_lvs6_pc"),
+ LVS(LVS7, "8921_lvs7", "8921_lvs7_pc"),
+ MVS(USB_OTG, "8921_usb_otg", NULL, USB_OTG_SWITCH),
+ MVS(HDMI_MVS, "8921_hdmi_mvs", NULL, HDMI_SWITCH),
- NCP(NCP),
+ NCP(NCP, "8921_ncp", NULL),
};
-#define vreg_err(vreg, fmt, ...) \
- pr_err("%s: " fmt, vreg->name, ##__VA_ARGS__)
-
-#define VREG_ID_IS_VDD_MEM_OR_DIG(id) \
- ((id == RPM_VREG_ID_PM8921_L24) || (id == RPM_VREG_ID_PM8921_S3))
-
-const char *pin_func_label[] = {
- [RPM_VREG_PIN_FN_DONT_CARE] = "don't care",
- [RPM_VREG_PIN_FN_ENABLE] = "on/off",
- [RPM_VREG_PIN_FN_MODE] = "HPM/LPM",
- [RPM_VREG_PIN_FN_SLEEP_B] = "sleep_b",
- [RPM_VREG_PIN_FN_NONE] = "none",
+static const char *pin_func_label[] = {
+ [RPM_VREG_PIN_FN_8960_DONT_CARE] = "don't care",
+ [RPM_VREG_PIN_FN_8960_ENABLE] = "on/off",
+ [RPM_VREG_PIN_FN_8960_MODE] = "HPM/LPM",
+ [RPM_VREG_PIN_FN_8960_SLEEP_B] = "sleep_b",
+ [RPM_VREG_PIN_FN_8960_NONE] = "none",
};
-const char *force_mode_label[] = {
- [RPM_VREG_FORCE_MODE_NONE] = "none",
- [RPM_VREG_FORCE_MODE_LPM] = "LPM",
- [RPM_VREG_FORCE_MODE_AUTO] = "auto",
- [RPM_VREG_FORCE_MODE_HPM] = "HPM",
- [RPM_VREG_FORCE_MODE_BYPASS] = "BYP",
+static const char *force_mode_label[] = {
+ [RPM_VREG_FORCE_MODE_8960_NONE] = "none",
+ [RPM_VREG_FORCE_MODE_8960_LPM] = "LPM",
+ [RPM_VREG_FORCE_MODE_8960_AUTO] = "auto",
+ [RPM_VREG_FORCE_MODE_8960_HPM] = "HPM",
+ [RPM_VREG_FORCE_MODE_8960_BYPASS] = "BYP",
};
-const char *power_mode_label[] = {
- [RPM_VREG_POWER_MODE_HYSTERETIC] = "HYS",
- [RPM_VREG_POWER_MODE_PWM] = "PWM",
+static const char *power_mode_label[] = {
+ [RPM_VREG_POWER_MODE_8960_HYSTERETIC] = "HYS",
+ [RPM_VREG_POWER_MODE_8960_PWM] = "PWM",
};
-static void rpm_regulator_req(struct vreg *vreg, int set)
-{
- int uV, ip, fm, pm, pc, pf, pd, ia, freq, clk, state, hpm, comp_mode;
- const char *pf_label = "", *fm_label = "", *pc_total = "";
- const char *pc_en0 = "", *pc_en1 = "", *pc_en2 = "", *pc_en3 = "";
- const char *pm_label = "";
-
- /* Suppress VDD_MEM and VDD_DIG printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
- && VREG_ID_IS_VDD_MEM_OR_DIG(vreg->id))
- return;
-
- if (vreg->part->uV.mask)
- uV = GET_PART(vreg, uV);
- else
- uV = MILLI_TO_MICRO(GET_PART(vreg, mV));
-
- ip = GET_PART(vreg, ip);
- fm = GET_PART(vreg, fm);
- pm = GET_PART(vreg, pm);
- pc = GET_PART(vreg, pc);
- pf = GET_PART(vreg, pf);
- pd = GET_PART(vreg, pd);
- ia = GET_PART(vreg, ia);
- freq = GET_PART(vreg, freq);
- clk = GET_PART(vreg, freq_clk_src);
- state = GET_PART(vreg, enable_state);
- hpm = GET_PART(vreg, hpm);
- comp_mode = GET_PART(vreg, comp_mode);
-
- if (pf >= 0 && pf < ARRAY_SIZE(pin_func_label))
- pf_label = pin_func_label[pf];
-
- if (fm >= 0 && fm < ARRAY_SIZE(force_mode_label))
- fm_label = force_mode_label[fm];
-
- if (pm >= 0 && pm < ARRAY_SIZE(power_mode_label))
- pm_label = power_mode_label[pm];
-
- if (pc & RPM_VREG_PIN_CTRL_EN0)
- pc_en0 = " D1";
- if (pc & RPM_VREG_PIN_CTRL_EN1)
- pc_en1 = " A0";
- if (pc & RPM_VREG_PIN_CTRL_EN2)
- pc_en2 = " A1";
- if (pc & RPM_VREG_PIN_CTRL_EN3)
- pc_en3 = " A2";
- if (pc == RPM_VREG_PIN_CTRL_NONE)
- pc_total = " none";
-
- switch (vreg->type) {
- case REGULATOR_TYPE_LDO:
- pr_info("%s %-9s: s=%c, v=%7d uV, ip=%4d mA, fm=%s (%d), "
- "pc=%s%s%s%s%s (%d), pf=%s (%d), pd=%s (%d), "
- "ia=%4d mA; req[0]={%d, 0x%08X}, req[1]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg->name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'), uV, ip,
- fm_label, fm, pc_en0, pc_en1, pc_en2, pc_en3, pc_total,
- pc, pf_label, pf, (pd == 1 ? "Y" : "N"), pd, ia,
- vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
- break;
- case REGULATOR_TYPE_SMPS:
- pr_info("%s %-9s: s=%c, v=%7d uV, ip=%4d mA, fm=%s (%d), "
- "pc=%s%s%s%s%s (%d), pf=%s (%d), pd=%s (%d), "
- "ia=%4d mA, freq=%2d, pm=%s (%d), clk_src=%d; "
- "req[0]={%d, 0x%08X}, req[1]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg->name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'), uV, ip,
- fm_label, fm, pc_en0, pc_en1, pc_en2, pc_en3, pc_total,
- pc, pf_label, pf, (pd == 1 ? "Y" : "N"), pd, ia, freq,
- pm_label, pm, clk, vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
- break;
- case REGULATOR_TYPE_VS:
- pr_info("%s %-9s: s=%c, state=%s (%d), pd=%s (%d), "
- "pc =%s%s%s%s%s (%d), pf=%s (%d), hpm=%d; "
- "req[0]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg->name, (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'),
- (state == 1 ? "on" : "off"), state,
- (pd == 1 ? "Y" : "N"), pd, pc_en0, pc_en1, pc_en2,
- pc_en3, pc_total, pc, pf_label, pf, hpm,
- vreg->req[0].id, vreg->req[0].value);
- break;
- case REGULATOR_TYPE_NCP:
- pr_info("%s %-9s: s=%c, v=-%7d uV, state=%s (%d), freq=%2d, "
- "comp=%d; req[0]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg->name, (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'),
- uV, (state == 1 ? "on" : "off"), state, freq, comp_mode,
- vreg->req[0].id, vreg->req[0].value);
- break;
- }
-}
-
-static void rpm_regulator_vote(struct vreg *vreg, enum rpm_vreg_voter voter,
- int set, int voter_uV, int aggregate_uV)
-{
- /* Suppress VDD_MEM and VDD_DIG printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
- && VREG_ID_IS_VDD_MEM_OR_DIG(vreg->id))
- return;
-
- pr_info("vote received %-9s: voter=%d, set=%c, v_voter=%7d uV, "
- "v_aggregate=%7d uV\n", vreg->name, voter,
- (set == 0 ? 'A' : 'S'), voter_uV, aggregate_uV);
-}
-
-static void rpm_regulator_duplicate(struct vreg *vreg, int set, int cnt)
-{
- /* Suppress VDD_MEM and VDD_DIG printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
- && VREG_ID_IS_VDD_MEM_OR_DIG(vreg->id))
- return;
-
- if (cnt == 2)
- pr_info("ignored request %-9s: set=%c; req[0]={%d, 0x%08X}, "
- "req[1]={%d, 0x%08X}\n", vreg->name,
- (set == 0 ? 'A' : 'S'),
- vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
- else if (cnt == 1)
- pr_info("ignored request %-9s: set=%c; req[0]={%d, 0x%08X}\n",
- vreg->name, (set == 0 ? 'A' : 'S'),
- vreg->req[0].id, vreg->req[0].value);
-}
-
-/* Spin lock needed for sleep-selectable regulators. */
-static DEFINE_SPINLOCK(pm8921_noirq_lock);
-
-static int voltage_from_req(struct vreg *vreg)
-{
- int uV = 0;
-
- if (vreg->part->uV.mask)
- uV = GET_PART(vreg, uV);
- else
- uV = MILLI_TO_MICRO(GET_PART(vreg, mV));
-
- return uV;
-}
-
-static void voltage_to_req(int uV, struct vreg *vreg)
-{
- if (vreg->part->uV.mask)
- SET_PART(vreg, uV, uV);
- else
- SET_PART(vreg, mV, MICRO_TO_MILLI(uV));
-}
-
-static int vreg_send_request(struct vreg *vreg, enum rpm_vreg_voter voter,
- int set, unsigned mask0, unsigned val0,
- unsigned mask1, unsigned val1, unsigned cnt,
- int update_voltage)
-{
- struct msm_rpm_iv_pair *prev_req;
- int rc = 0, max_uV_vote = 0;
- unsigned prev0, prev1;
- int *min_uV_vote;
- int i;
-
- if (set == MSM_RPM_CTX_SET_0) {
- min_uV_vote = vreg->active_min_uV_vote;
- prev_req = vreg->prev_active_req;
- } else {
- min_uV_vote = vreg->sleep_min_uV_vote;
- prev_req = vreg->prev_sleep_req;
- }
-
- prev0 = vreg->req[0].value;
- vreg->req[0].value &= ~mask0;
- vreg->req[0].value |= val0 & mask0;
-
- prev1 = vreg->req[1].value;
- vreg->req[1].value &= ~mask1;
- vreg->req[1].value |= val1 & mask1;
-
- if (update_voltage)
- min_uV_vote[voter] = voltage_from_req(vreg);
-
- /* Find the highest voltage voted for and use it. */
- for (i = 0; i < RPM_VREG_VOTER_COUNT; i++)
- max_uV_vote = max(max_uV_vote, min_uV_vote[i]);
- voltage_to_req(max_uV_vote, vreg);
-
- if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_VOTE)
- rpm_regulator_vote(vreg, voter, set, min_uV_vote[voter],
- max_uV_vote);
-
- /* Ignore duplicate requests */
- if (vreg->req[0].value != prev_req[0].value ||
- vreg->req[1].value != prev_req[1].value) {
- rc = msm_rpmrs_set_noirq(set, vreg->req, cnt);
- if (rc) {
- vreg->req[0].value = prev0;
- vreg->req[1].value = prev1;
-
- vreg_err(vreg, "msm_rpmrs_set_noirq failed - "
- "set=%s, id=%d, rc=%d\n",
- (set == MSM_RPM_CTX_SET_0 ? "active" : "sleep"),
- vreg->req[0].id, rc);
- } else {
- /* Only save if nonzero and active set. */
- if (max_uV_vote && (set == MSM_RPM_CTX_SET_0))
- vreg->save_uV = max_uV_vote;
- if (msm_rpm_vreg_debug_mask
- & MSM_RPM_VREG_DEBUG_REQUEST)
- rpm_regulator_req(vreg, set);
- prev_req[0].value = vreg->req[0].value;
- prev_req[1].value = vreg->req[1].value;
- }
- } else if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_DUPLICATE) {
- rpm_regulator_duplicate(vreg, set, cnt);
- }
-
- return rc;
-}
-
-static int vreg_set_noirq(struct vreg *vreg, enum rpm_vreg_voter voter,
- int sleep, unsigned mask0, unsigned val0,
- unsigned mask1, unsigned val1, unsigned cnt,
- int update_voltage)
-{
- unsigned int s_mask[2] = {mask0, mask1}, s_val[2] = {val0, val1};
- unsigned long flags;
- int rc;
-
- if (voter < 0 || voter >= RPM_VREG_VOTER_COUNT)
- return -EINVAL;
-
- spin_lock_irqsave(&pm8921_noirq_lock, flags);
-
- /*
- * Send sleep set request first so that subsequent set_mode, etc calls
- * use the voltage from the active set.
- */
- if (sleep)
- rc = vreg_send_request(vreg, voter, MSM_RPM_CTX_SET_SLEEP,
- mask0, val0, mask1, val1, cnt, update_voltage);
- else {
- /*
- * Vote for 0 V in the sleep set when active set-only is
- * specified. This ensures that a disable vote will be issued
- * at some point for the sleep set of the regulator.
- */
- if (vreg->part->uV.mask) {
- s_val[vreg->part->uV.word] = 0 << vreg->part->uV.shift;
- s_mask[vreg->part->uV.word] = vreg->part->uV.mask;
- } else {
- s_val[vreg->part->mV.word] = 0 << vreg->part->mV.shift;
- s_mask[vreg->part->mV.word] = vreg->part->mV.mask;
- }
-
- rc = vreg_send_request(vreg, voter, MSM_RPM_CTX_SET_SLEEP,
- s_mask[0], s_val[0], s_mask[1], s_val[1],
- cnt, update_voltage);
- }
-
- rc = vreg_send_request(vreg, voter, MSM_RPM_CTX_SET_0, mask0, val0,
- mask1, val1, cnt, update_voltage);
-
- spin_unlock_irqrestore(&pm8921_noirq_lock, flags);
-
- return rc;
-}
-
-/**
- * rpm_vreg_set_voltage - vote for a min_uV value of specified regualtor
- * @vreg: ID for regulator
- * @voter: ID for the voter
- * @min_uV: minimum acceptable voltage (in uV) that is voted for
- * @max_uV: maximum acceptable voltage (in uV) that is voted for
- * @sleep_also: 0 for active set only, non-0 for active set and sleep set
- *
- * Returns 0 on success or errno.
- *
- * This function is used to vote for the voltage of a regulator without
- * using the regulator framework. It is needed by consumers which hold spin
- * locks or have interrupts disabled because the regulator framework can sleep.
- * It is also needed by consumers which wish to only vote for active set
- * regulator voltage.
- *
- * If sleep_also == 0, then a sleep-set value of 0V will be voted for.
- *
- * This function may only be called for regulators which have the sleep flag
- * specified in their private data.
- */
-int rpm_vreg_set_voltage(enum rpm_vreg_id vreg_id, enum rpm_vreg_voter voter,
- int min_uV, int max_uV, int sleep_also)
-{
- unsigned int mask[2] = {0}, val[2] = {0};
- struct vreg_range *range;
- struct vreg *vreg;
- int uV = min_uV;
- int lim_min_uV, lim_max_uV, i, rc;
-
- if (vreg_id < 0 || vreg_id > RPM_VREG_ID_PM8921_MAX_REAL) {
- pr_err("invalid regulator id=%d\n", vreg_id);
- return -EINVAL;
- }
-
- /*
- * TODO: make this function a no-op for 8064 so that it can be called by
- * consumers on 8064 before RPM capabilities are present. (needed for
- * acpuclock driver)
- */
- if (cpu_is_apq8064())
- return 0;
-
- vreg = &vregs[vreg_id];
- range = &vreg->set_points->range[0];
-
- if (!vreg->pdata.sleep_selectable) {
- vreg_err(vreg, "regulator is not marked sleep selectable\n");
- return -EINVAL;
- }
-
- /*
- * Check if request voltage is outside of allowed range. The regulator
- * core has already checked that constraint range is inside of the
- * physically allowed range.
- */
- lim_min_uV = vreg->pdata.init_data.constraints.min_uV;
- lim_max_uV = vreg->pdata.init_data.constraints.max_uV;
-
- if (uV < lim_min_uV && max_uV >= lim_min_uV)
- uV = lim_min_uV;
-
- if (uV < lim_min_uV || uV > lim_max_uV) {
- vreg_err(vreg,
- "request v=[%d, %d] is outside allowed v=[%d, %d]\n",
- min_uV, max_uV, lim_min_uV, lim_max_uV);
- return -EINVAL;
- }
-
- /* Find the range which uV is inside of. */
- for (i = vreg->set_points->count - 1; i > 0; i--) {
- if (uV > vreg->set_points->range[i - 1].max_uV) {
- range = &vreg->set_points->range[i];
- break;
- }
- }
-
- /*
- * Force uV to be an allowed set point and apply a ceiling function
- * to non-set point values.
- */
- uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
- uV = uV * range->step_uV + range->min_uV;
-
- if (vreg->part->uV.mask) {
- val[vreg->part->uV.word] = uV << vreg->part->uV.shift;
- mask[vreg->part->uV.word] = vreg->part->uV.mask;
- } else {
- val[vreg->part->mV.word]
- = MICRO_TO_MILLI(uV) << vreg->part->mV.shift;
- mask[vreg->part->mV.word] = vreg->part->mV.mask;
- }
-
- rc = vreg_set_noirq(vreg, voter, sleep_also, mask[0], val[0], mask[1],
- val[1], vreg->part->request_len, 1);
- if (rc)
- vreg_err(vreg, "vreg_set_noirq failed, rc=%d\n", rc);
-
- return rc;
-}
-EXPORT_SYMBOL_GPL(rpm_vreg_set_voltage);
-
-/**
- * rpm_vreg_set_frequency - sets the frequency of a switching regulator
- * @vreg: ID for regulator
- * @freq: enum corresponding to desired frequency
- *
- * Returns 0 on success or errno.
- */
-int rpm_vreg_set_frequency(enum rpm_vreg_id vreg_id, enum rpm_vreg_freq freq)
-{
- unsigned int mask[2] = {0}, val[2] = {0};
- struct vreg *vreg;
- int rc;
-
- if (vreg_id < 0 || vreg_id > RPM_VREG_ID_PM8921_MAX_REAL) {
- pr_err("invalid regulator id=%d\n", vreg_id);
- return -EINVAL;
- }
-
- /*
- * TODO: make this function a no-op for 8064 so that it can be called by
- * consumers on 8064 before RPM capabilities are present.
- */
- if (cpu_is_apq8064())
- return 0;
-
- vreg = &vregs[vreg_id];
-
- if (freq < 0 || freq > RPM_VREG_FREQ_1p20) {
- vreg_err(vreg, "invalid frequency=%d\n", freq);
- return -EINVAL;
- }
- if (!vreg->pdata.sleep_selectable) {
- vreg_err(vreg, "regulator is not marked sleep selectable\n");
- return -EINVAL;
- }
- if (!vreg->part->freq.mask) {
- vreg_err(vreg, "frequency not supported\n");
- return -EINVAL;
- }
-
- val[vreg->part->freq.word] = freq << vreg->part->freq.shift;
- mask[vreg->part->freq.word] = vreg->part->freq.mask;
-
- rc = vreg_set_noirq(vreg, RPM_VREG_VOTER_REG_FRAMEWORK, 1, mask[0],
- val[0], mask[1], val[1], vreg->part->request_len, 0);
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-
- return rc;
-}
-EXPORT_SYMBOL_GPL(rpm_vreg_set_frequency);
-
-static inline int vreg_hpm_min_uA(struct vreg *vreg)
-{
- return vreg->hpm_min_load;
-}
-
-static inline int vreg_lpm_max_uA(struct vreg *vreg)
-{
- return vreg->hpm_min_load - LOAD_THRESHOLD_STEP;
-}
-
-static inline unsigned saturate_peak_load(struct vreg *vreg, unsigned load_uA)
-{
- unsigned load_max
- = MILLI_TO_MICRO(vreg->part->ip.mask >> vreg->part->ip.shift);
-
- return (load_uA > load_max ? load_max : load_uA);
-}
-
-static inline unsigned saturate_avg_load(struct vreg *vreg, unsigned load_uA)
-{
- unsigned load_max
- = MILLI_TO_MICRO(vreg->part->ia.mask >> vreg->part->ia.shift);
- return (load_uA > load_max ? load_max : load_uA);
-}
-
-/* Change vreg->req, but do not send it to the RPM. */
-static int vreg_store(struct vreg *vreg, unsigned mask0, unsigned val0,
- unsigned mask1, unsigned val1)
-{
- unsigned long flags = 0;
-
- if (vreg->pdata.sleep_selectable)
- spin_lock_irqsave(&pm8921_noirq_lock, flags);
-
- vreg->req[0].value &= ~mask0;
- vreg->req[0].value |= val0 & mask0;
-
- vreg->req[1].value &= ~mask1;
- vreg->req[1].value |= val1 & mask1;
-
- if (vreg->pdata.sleep_selectable)
- spin_unlock_irqrestore(&pm8921_noirq_lock, flags);
-
- return 0;
-}
-
-static int vreg_set(struct vreg *vreg, unsigned mask0, unsigned val0,
- unsigned mask1, unsigned val1, unsigned cnt)
-{
- unsigned prev0 = 0, prev1 = 0;
- int rc;
-
- /*
- * Bypass the normal route for regulators that can be called to change
- * just the active set values.
- */
- if (vreg->pdata.sleep_selectable)
- return vreg_set_noirq(vreg, RPM_VREG_VOTER_REG_FRAMEWORK, 1,
- mask0, val0, mask1, val1, cnt, 1);
-
- prev0 = vreg->req[0].value;
- vreg->req[0].value &= ~mask0;
- vreg->req[0].value |= val0 & mask0;
-
- prev1 = vreg->req[1].value;
- vreg->req[1].value &= ~mask1;
- vreg->req[1].value |= val1 & mask1;
-
- /* Ignore duplicate requests */
- if (vreg->req[0].value == vreg->prev_active_req[0].value &&
- vreg->req[1].value == vreg->prev_active_req[1].value) {
- if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_DUPLICATE)
- rpm_regulator_duplicate(vreg, MSM_RPM_CTX_SET_0, cnt);
- return 0;
- }
-
- rc = msm_rpm_set(MSM_RPM_CTX_SET_0, vreg->req, cnt);
- if (rc) {
- vreg->req[0].value = prev0;
- vreg->req[1].value = prev1;
-
- vreg_err(vreg, "msm_rpm_set failed, set=active, id=%d, rc=%d\n",
- vreg->req[0].id, rc);
- } else {
- if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_REQUEST)
- rpm_regulator_req(vreg, MSM_RPM_CTX_SET_0);
- vreg->prev_active_req[0].value = vreg->req[0].value;
- vreg->prev_active_req[1].value = vreg->req[1].value;
- }
-
- return rc;
-}
-
-static int vreg_is_enabled(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- int enabled;
-
- mutex_lock(&vreg->pc_lock);
- enabled = vreg->is_enabled;
- mutex_unlock(&vreg->pc_lock);
-
- return enabled;
-}
-
-static void set_enable(struct vreg *vreg, unsigned int *mask, unsigned int *val)
-{
- switch (vreg->type) {
- case REGULATOR_TYPE_LDO:
- case REGULATOR_TYPE_SMPS:
- /* Enable by setting a voltage. */
- if (vreg->part->uV.mask) {
- val[vreg->part->uV.word]
- |= vreg->save_uV << vreg->part->uV.shift;
- mask[vreg->part->uV.word] |= vreg->part->uV.mask;
- } else {
- val[vreg->part->mV.word]
- |= MICRO_TO_MILLI(vreg->save_uV)
- << vreg->part->mV.shift;
- mask[vreg->part->mV.word] |= vreg->part->mV.mask;
- }
- break;
- case REGULATOR_TYPE_VS:
- case REGULATOR_TYPE_NCP:
- /* Enable by setting enable_state. */
- val[vreg->part->enable_state.word]
- |= RPM_VREG_STATE_ON << vreg->part->enable_state.shift;
- mask[vreg->part->enable_state.word]
- |= vreg->part->enable_state.mask;
- }
-}
-
-static int vreg_enable(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mask[2] = {0}, val[2] = {0};
- int rc = 0;
-
- set_enable(vreg, mask, val);
-
- mutex_lock(&vreg->pc_lock);
-
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
- if (!rc)
- vreg->is_enabled = true;
-
- mutex_unlock(&vreg->pc_lock);
-
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-
- return rc;
-}
-
-static void set_disable(struct vreg *vreg, unsigned int *mask,
- unsigned int *val)
-{
- switch (vreg->type) {
- case REGULATOR_TYPE_LDO:
- case REGULATOR_TYPE_SMPS:
- /* Disable by setting a voltage of 0 uV. */
- if (vreg->part->uV.mask) {
- val[vreg->part->uV.word] |= 0 << vreg->part->uV.shift;
- mask[vreg->part->uV.word] |= vreg->part->uV.mask;
- } else {
- val[vreg->part->mV.word] |= 0 << vreg->part->mV.shift;
- mask[vreg->part->mV.word] |= vreg->part->mV.mask;
- }
- break;
- case REGULATOR_TYPE_VS:
- case REGULATOR_TYPE_NCP:
- /* Disable by setting enable_state. */
- val[vreg->part->enable_state.word]
- |= RPM_VREG_STATE_OFF << vreg->part->enable_state.shift;
- mask[vreg->part->enable_state.word]
- |= vreg->part->enable_state.mask;
- }
-}
-
-static int vreg_disable(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mask[2] = {0}, val[2] = {0};
- int rc = 0;
-
- set_disable(vreg, mask, val);
-
- mutex_lock(&vreg->pc_lock);
-
- /* Only disable if pin control is not in use. */
- if (!vreg->is_enabled_pc)
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
-
- if (!rc)
- vreg->is_enabled = false;
-
- mutex_unlock(&vreg->pc_lock);
-
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-
- return rc;
-}
-
-static int vreg_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
- unsigned *selector)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- struct vreg_range *range = &vreg->set_points->range[0];
- unsigned int mask[2] = {0}, val[2] = {0};
- int rc = 0, uV = min_uV;
- int lim_min_uV, lim_max_uV, i;
-
- /* Check if request voltage is outside of physically settable range. */
- lim_min_uV = vreg->set_points->range[0].min_uV;
- lim_max_uV =
- vreg->set_points->range[vreg->set_points->count - 1].max_uV;
-
- if (uV < lim_min_uV && max_uV >= lim_min_uV)
- uV = lim_min_uV;
-
- if (uV < lim_min_uV || uV > lim_max_uV) {
- vreg_err(vreg,
- "request v=[%d, %d] is outside possible v=[%d, %d]\n",
- min_uV, max_uV, lim_min_uV, lim_max_uV);
- return -EINVAL;
- }
-
- /* Find the range which uV is inside of. */
- for (i = vreg->set_points->count - 1; i > 0; i--) {
- if (uV > vreg->set_points->range[i - 1].max_uV) {
- range = &vreg->set_points->range[i];
- break;
- }
- }
-
- /*
- * Force uV to be an allowed set point and apply a ceiling function
- * to non-set point values.
- */
- uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
- uV = uV * range->step_uV + range->min_uV;
-
- if (vreg->part->uV.mask) {
- val[vreg->part->uV.word] = uV << vreg->part->uV.shift;
- mask[vreg->part->uV.word] = vreg->part->uV.mask;
- } else {
- val[vreg->part->mV.word]
- = MICRO_TO_MILLI(uV) << vreg->part->mV.shift;
- mask[vreg->part->mV.word] = vreg->part->mV.mask;
- }
-
- mutex_lock(&vreg->pc_lock);
-
- /*
- * Only send a request for a new voltage if the regulator is currently
- * enabled. This will ensure that LDO and SMPS regulators are not
- * inadvertently turned on because voltage > 0 is equivalent to
- * enabling. For NCP, this just removes unnecessary RPM requests.
- */
- if (vreg->is_enabled) {
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
- } else if (vreg->type == REGULATOR_TYPE_NCP) {
- /* Regulator is disabled; store but don't send new request. */
- rc = vreg_store(vreg, mask[0], val[0], mask[1], val[1]);
- }
-
- if (!rc && (!vreg->pdata.sleep_selectable || !vreg->is_enabled))
- vreg->save_uV = uV;
-
- mutex_unlock(&vreg->pc_lock);
-
- return rc;
-}
-
-static int vreg_get_voltage(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
-
- return vreg->save_uV;
-}
-
-static int vreg_list_voltage(struct regulator_dev *rdev, unsigned selector)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- int uV = 0;
- int i;
-
- if (!vreg->set_points) {
- vreg_err(vreg, "no voltages available\n");
- return -EINVAL;
- }
-
- if (selector >= vreg->set_points->n_voltages)
- return 0;
-
- for (i = 0; i < vreg->set_points->count; i++) {
- if (selector < vreg->set_points->range[i].n_voltages) {
- uV = selector * vreg->set_points->range[i].step_uV
- + vreg->set_points->range[i].min_uV;
- break;
- } else {
- selector -= vreg->set_points->range[i].n_voltages;
- }
- }
-
- return uV;
-}
-
-static int vreg_set_mode(struct regulator_dev *rdev, unsigned int mode)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mask[2] = {0}, val[2] = {0};
- int rc = 0;
- int peak_uA;
-
- mutex_lock(&vreg->pc_lock);
-
- peak_uA = MILLI_TO_MICRO((vreg->req[vreg->part->ip.word].value
- & vreg->part->ip.mask) >> vreg->part->ip.shift);
-
- switch (mode) {
- case REGULATOR_MODE_NORMAL:
- /* Make sure that request currents are in HPM range. */
- if (peak_uA < vreg_hpm_min_uA(vreg)) {
- val[vreg->part->ip.word]
- = MICRO_TO_MILLI(vreg_hpm_min_uA(vreg))
- << vreg->part->ip.shift;
- mask[vreg->part->ip.word] = vreg->part->ip.mask;
- }
- break;
- case REGULATOR_MODE_IDLE:
- /* Make sure that request currents are in LPM range. */
- if (peak_uA > vreg_lpm_max_uA(vreg)) {
- val[vreg->part->ip.word]
- = MICRO_TO_MILLI(vreg_lpm_max_uA(vreg))
- << vreg->part->ip.shift;
- mask[vreg->part->ip.word] = vreg->part->ip.mask;
- }
- break;
- default:
- vreg_err(vreg, "invalid mode: %u\n", mode);
- mutex_unlock(&vreg->pc_lock);
- return -EINVAL;
- }
-
- if (vreg->is_enabled) {
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
- } else {
- /* Regulator is disabled; store but don't send new request. */
- rc = vreg_store(vreg, mask[0], val[0], mask[1], val[1]);
- }
-
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
- else
- vreg->mode = mode;
-
- mutex_unlock(&vreg->pc_lock);
-
- return rc;
-}
-
-static unsigned int vreg_get_mode(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
-
- return vreg->mode;
-}
-
-static unsigned int vreg_get_optimum_mode(struct regulator_dev *rdev,
- int input_uV, int output_uV, int load_uA)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mode;
-
- load_uA += vreg->pdata.system_uA;
-
- mutex_lock(&vreg->pc_lock);
- SET_PART(vreg, ip, MICRO_TO_MILLI(saturate_peak_load(vreg, load_uA)));
- mutex_unlock(&vreg->pc_lock);
-
- if (load_uA >= vreg->hpm_min_load)
- mode = REGULATOR_MODE_NORMAL;
- else
- mode = REGULATOR_MODE_IDLE;
-
- return mode;
-}
-
-/*
- * Returns the logical pin control enable state because the pin control options
- * present in the hardware out of restart could be different from those desired
- * by the consumer.
- */
-static int vreg_pin_control_is_enabled(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
-
- return vreg->is_enabled_pc;
-}
-
-static int vreg_pin_control_enable(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mask[2] = {0}, val[2] = {0};
- int rc;
-
- mutex_lock(&vreg->pc_lock);
-
- val[vreg->part->pc.word]
- |= vreg->pdata.pin_ctrl << vreg->part->pc.shift;
- mask[vreg->part->pc.word] |= vreg->part->pc.mask;
-
- val[vreg->part->pf.word] |= vreg->pdata.pin_fn << vreg->part->pf.shift;
- mask[vreg->part->pf.word] |= vreg->part->pf.mask;
-
- if (!vreg->is_enabled)
- set_enable(vreg, mask, val);
-
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
-
- if (!rc)
- vreg->is_enabled_pc = true;
-
- mutex_unlock(&vreg->pc_lock);
-
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-
- return rc;
-}
-
-static int vreg_pin_control_disable(struct regulator_dev *rdev)
-{
- struct vreg *vreg = rdev_get_drvdata(rdev);
- unsigned int mask[2] = {0}, val[2] = {0};
- enum rpm_vreg_pin_fn pin_fn;
- int rc;
-
- mutex_lock(&vreg->pc_lock);
-
- val[vreg->part->pc.word]
- |= RPM_VREG_PIN_CTRL_NONE << vreg->part->pc.shift;
- mask[vreg->part->pc.word] |= vreg->part->pc.mask;
-
- pin_fn = RPM_VREG_PIN_FN_NONE;
- if (vreg->pdata.pin_fn == RPM_VREG_PIN_FN_SLEEP_B)
- pin_fn = RPM_VREG_PIN_FN_SLEEP_B;
- val[vreg->part->pf.word] |= pin_fn << vreg->part->pf.shift;
- mask[vreg->part->pf.word] |= vreg->part->pf.mask;
-
- if (!vreg->is_enabled)
- set_disable(vreg, mask, val);
-
- rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
- vreg->part->request_len);
-
- if (!rc)
- vreg->is_enabled_pc = false;
-
- mutex_unlock(&vreg->pc_lock);
-
- if (rc)
- vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-
- return rc;
-}
-
-/* Real regulator operations. */
-static struct regulator_ops ldo_ops = {
- .enable = vreg_enable,
- .disable = vreg_disable,
- .is_enabled = vreg_is_enabled,
- .set_voltage = vreg_set_voltage,
- .get_voltage = vreg_get_voltage,
- .list_voltage = vreg_list_voltage,
- .set_mode = vreg_set_mode,
- .get_mode = vreg_get_mode,
- .get_optimum_mode = vreg_get_optimum_mode,
+static const char *pin_control_label[] = {
+ " D1",
+ " A0",
+ " A1",
+ " A2",
};
-static struct regulator_ops smps_ops = {
- .enable = vreg_enable,
- .disable = vreg_disable,
- .is_enabled = vreg_is_enabled,
- .set_voltage = vreg_set_voltage,
- .get_voltage = vreg_get_voltage,
- .list_voltage = vreg_list_voltage,
- .set_mode = vreg_set_mode,
- .get_mode = vreg_get_mode,
- .get_optimum_mode = vreg_get_optimum_mode,
-};
-
-static struct regulator_ops switch_ops = {
- .enable = vreg_enable,
- .disable = vreg_disable,
- .is_enabled = vreg_is_enabled,
-};
-
-static struct regulator_ops ncp_ops = {
- .enable = vreg_enable,
- .disable = vreg_disable,
- .is_enabled = vreg_is_enabled,
- .set_voltage = vreg_set_voltage,
- .get_voltage = vreg_get_voltage,
- .list_voltage = vreg_list_voltage,
-};
-
-/* Pin control regulator operations. */
-static struct regulator_ops pin_control_ops = {
- .enable = vreg_pin_control_enable,
- .disable = vreg_pin_control_disable,
- .is_enabled = vreg_pin_control_is_enabled,
-};
-
-#define VREG_DESC(_id, _name, _ops) \
- [RPM_VREG_ID_PM8921_##_id] = { \
- .id = RPM_VREG_ID_PM8921_##_id, \
- .name = _name, \
- .ops = _ops, \
- .type = REGULATOR_VOLTAGE, \
- .owner = THIS_MODULE, \
- }
-
-static struct regulator_desc vreg_description[] = {
- VREG_DESC(L1, "8921_l1", &ldo_ops),
- VREG_DESC(L2, "8921_l2", &ldo_ops),
- VREG_DESC(L3, "8921_l3", &ldo_ops),
- VREG_DESC(L4, "8921_l4", &ldo_ops),
- VREG_DESC(L5, "8921_l5", &ldo_ops),
- VREG_DESC(L6, "8921_l6", &ldo_ops),
- VREG_DESC(L7, "8921_l7", &ldo_ops),
- VREG_DESC(L8, "8921_l8", &ldo_ops),
- VREG_DESC(L9, "8921_l9", &ldo_ops),
- VREG_DESC(L10, "8921_l10", &ldo_ops),
- VREG_DESC(L11, "8921_l11", &ldo_ops),
- VREG_DESC(L12, "8921_l12", &ldo_ops),
- VREG_DESC(L14, "8921_l14", &ldo_ops),
- VREG_DESC(L15, "8921_l15", &ldo_ops),
- VREG_DESC(L16, "8921_l16", &ldo_ops),
- VREG_DESC(L17, "8921_l17", &ldo_ops),
- VREG_DESC(L18, "8921_l18", &ldo_ops),
- VREG_DESC(L21, "8921_l21", &ldo_ops),
- VREG_DESC(L22, "8921_l22", &ldo_ops),
- VREG_DESC(L23, "8921_l23", &ldo_ops),
- VREG_DESC(L24, "8921_l24", &ldo_ops),
- VREG_DESC(L25, "8921_l25", &ldo_ops),
- VREG_DESC(L26, "8921_l26", &ldo_ops),
- VREG_DESC(L27, "8921_l27", &ldo_ops),
- VREG_DESC(L28, "8921_l28", &ldo_ops),
- VREG_DESC(L29, "8921_l29", &ldo_ops),
-
- VREG_DESC(S1, "8921_s1", &smps_ops),
- VREG_DESC(S2, "8921_s2", &smps_ops),
- VREG_DESC(S3, "8921_s3", &smps_ops),
- VREG_DESC(S4, "8921_s4", &smps_ops),
- VREG_DESC(S5, "8921_s5", &smps_ops),
- VREG_DESC(S6, "8921_s6", &smps_ops),
- VREG_DESC(S7, "8921_s7", &smps_ops),
- VREG_DESC(S8, "8921_s8", &smps_ops),
-
- VREG_DESC(LVS1, "8921_lvs1", &switch_ops),
- VREG_DESC(LVS2, "8921_lvs2", &switch_ops),
- VREG_DESC(LVS3, "8921_lvs3", &switch_ops),
- VREG_DESC(LVS4, "8921_lvs4", &switch_ops),
- VREG_DESC(LVS5, "8921_lvs5", &switch_ops),
- VREG_DESC(LVS6, "8921_lvs6", &switch_ops),
- VREG_DESC(LVS7, "8921_lvs7", &switch_ops),
-
- VREG_DESC(USB_OTG, "8921_usb_otg", &switch_ops),
- VREG_DESC(HDMI_MVS, "8921_hdmi_mvs", &switch_ops),
- VREG_DESC(NCP, "8921_ncp", &ncp_ops),
-
- VREG_DESC(L1_PC, "8921_l1_pc", &pin_control_ops),
- VREG_DESC(L2_PC, "8921_l2_pc", &pin_control_ops),
- VREG_DESC(L3_PC, "8921_l3_pc", &pin_control_ops),
- VREG_DESC(L4_PC, "8921_l4_pc", &pin_control_ops),
- VREG_DESC(L5_PC, "8921_l5_pc", &pin_control_ops),
- VREG_DESC(L6_PC, "8921_l6_pc", &pin_control_ops),
- VREG_DESC(L7_PC, "8921_l7_pc", &pin_control_ops),
- VREG_DESC(L8_PC, "8921_l8_pc", &pin_control_ops),
- VREG_DESC(L9_PC, "8921_l9_pc", &pin_control_ops),
- VREG_DESC(L10_PC, "8921_l10_pc", &pin_control_ops),
- VREG_DESC(L11_PC, "8921_l11_pc", &pin_control_ops),
- VREG_DESC(L12_PC, "8921_l12_pc", &pin_control_ops),
- VREG_DESC(L14_PC, "8921_l14_pc", &pin_control_ops),
- VREG_DESC(L15_PC, "8921_l15_pc", &pin_control_ops),
- VREG_DESC(L16_PC, "8921_l16_pc", &pin_control_ops),
- VREG_DESC(L17_PC, "8921_l17_pc", &pin_control_ops),
- VREG_DESC(L18_PC, "8921_l18_pc", &pin_control_ops),
- VREG_DESC(L21_PC, "8921_l21_pc", &pin_control_ops),
- VREG_DESC(L22_PC, "8921_l22_pc", &pin_control_ops),
- VREG_DESC(L23_PC, "8921_l23_pc", &pin_control_ops),
- VREG_DESC(L29_PC, "8921_l29_pc", &pin_control_ops),
-
- VREG_DESC(S1_PC, "8921_s1_pc", &pin_control_ops),
- VREG_DESC(S2_PC, "8921_s2_pc", &pin_control_ops),
- VREG_DESC(S3_PC, "8921_s3_pc", &pin_control_ops),
- VREG_DESC(S4_PC, "8921_s4_pc", &pin_control_ops),
- VREG_DESC(S7_PC, "8921_s7_pc", &pin_control_ops),
- VREG_DESC(S8_PC, "8921_s8_pc", &pin_control_ops),
-
- VREG_DESC(LVS1_PC, "8921_lvs1_pc", &pin_control_ops),
- VREG_DESC(LVS3_PC, "8921_lvs3_pc", &pin_control_ops),
- VREG_DESC(LVS4_PC, "8921_lvs4_pc", &pin_control_ops),
- VREG_DESC(LVS5_PC, "8921_lvs5_pc", &pin_control_ops),
- VREG_DESC(LVS6_PC, "8921_lvs6_pc", &pin_control_ops),
- VREG_DESC(LVS7_PC, "8921_lvs7_pc", &pin_control_ops),
-};
-
-static inline int is_real_regulator(int id)
+static int is_real_id(int id)
{
return (id >= 0) && (id <= RPM_VREG_ID_PM8921_MAX_REAL);
}
@@ -1431,237 +279,36 @@
return real_id;
}
-static int __devinit
-rpm_vreg_init_regulator(const struct rpm_regulator_init_data *pdata,
- struct device *dev)
-{
- enum rpm_vreg_pin_fn pin_fn;
- struct regulator_desc *rdesc;
- struct regulator_dev *rdev;
- struct vreg *vreg;
- const char *reg_name = "";
- unsigned pin_ctrl;
- int rc = 0, id = pdata->id;
+static struct vreg_config config = {
+ .vregs = vregs,
+ .vregs_len = ARRAY_SIZE(vregs),
- if (id < 0 || id > RPM_VREG_ID_PM8921_MAX) {
- pr_err("invalid regulator id: %d\n", id);
- return -ENODEV;
- }
+ .vreg_id_min = RPM_VREG_ID_PM8921_L1,
+ .vreg_id_max = RPM_VREG_ID_PM8921_MAX,
- rdesc = &vreg_description[pdata->id];
- if (!is_real_regulator(pdata->id))
- id = pc_id_to_real_id(pdata->id);
- vreg = &vregs[id];
- reg_name = vreg_description[pdata->id].name;
- if (!pdata) {
- pr_err("%s: requires platform data\n", reg_name);
- return -EINVAL;
- }
- if (vreg->set_points)
- rdesc->n_voltages = vreg->set_points->n_voltages;
- else
- rdesc->n_voltages = 0;
+ .pin_func_none = RPM_VREG_PIN_FN_8960_NONE,
+ .pin_func_sleep_b = RPM_VREG_PIN_FN_8960_SLEEP_B,
- mutex_lock(&vreg->pc_lock);
+ .mode_lpm = REGULATOR_MODE_IDLE,
+ .mode_hpm = REGULATOR_MODE_NORMAL,
- if (is_real_regulator(pdata->id)) {
- /* Do not modify pin control and pin function values. */
- pin_ctrl = vreg->pdata.pin_ctrl;
- pin_fn = vreg->pdata.pin_fn;
- memcpy(&(vreg->pdata), pdata,
- sizeof(struct rpm_regulator_init_data));
- vreg->pdata.pin_ctrl = pin_ctrl;
- vreg->pdata.pin_fn = pin_fn;
- vreg->name = reg_name;
+ .set_points = all_set_points,
+ .set_points_len = ARRAY_SIZE(all_set_points),
- vreg->save_uV = vreg->pdata.default_uV;
- if (vreg->pdata.peak_uA >= vreg->hpm_min_load)
- vreg->mode = REGULATOR_MODE_NORMAL;
- else
- vreg->mode = REGULATOR_MODE_IDLE;
+ .label_pin_ctrl = pin_control_label,
+ .label_pin_ctrl_len = ARRAY_SIZE(pin_control_label),
+ .label_pin_func = pin_func_label,
+ .label_pin_func_len = ARRAY_SIZE(pin_func_label),
+ .label_force_mode = force_mode_label,
+ .label_force_mode_len = ARRAY_SIZE(force_mode_label),
+ .label_power_mode = power_mode_label,
+ .label_power_mode_len = ARRAY_SIZE(power_mode_label),
- /* Initialize the RPM request. */
- SET_PART(vreg, ip,
- MICRO_TO_MILLI(saturate_peak_load(vreg, vreg->pdata.peak_uA)));
- SET_PART(vreg, fm, vreg->pdata.force_mode);
- SET_PART(vreg, pm, vreg->pdata.power_mode);
- SET_PART(vreg, pd, vreg->pdata.pull_down_enable);
- SET_PART(vreg, ia,
- MICRO_TO_MILLI(saturate_avg_load(vreg, vreg->pdata.avg_uA)));
- SET_PART(vreg, freq, vreg->pdata.freq);
- SET_PART(vreg, freq_clk_src, 0);
- SET_PART(vreg, comp_mode, 0);
- SET_PART(vreg, hpm, 0);
- if (!vreg->is_enabled_pc) {
- SET_PART(vreg, pf, RPM_VREG_PIN_FN_NONE);
- SET_PART(vreg, pc, RPM_VREG_PIN_CTRL_NONE);
- }
- } else {
- /* Pin control regulator */
- if ((pdata->pin_ctrl & RPM_VREG_PIN_CTRL_ALL)
- == RPM_VREG_PIN_CTRL_NONE
- && pdata->pin_fn != RPM_VREG_PIN_FN_SLEEP_B) {
- pr_err("%s: no pin control input specified\n",
- reg_name);
- mutex_unlock(&vreg->pc_lock);
- return -EINVAL;
- }
- vreg->pdata.pin_ctrl = pdata->pin_ctrl;
- vreg->pdata.pin_fn = pdata->pin_fn;
- if (!vreg->name)
- vreg->name = reg_name;
-
- /* Initialize the RPM request. */
- pin_fn = RPM_VREG_PIN_FN_NONE;
- /* Allow pf=sleep_b to be specified by platform data. */
- if (vreg->pdata.pin_fn == RPM_VREG_PIN_FN_SLEEP_B)
- pin_fn = RPM_VREG_PIN_FN_SLEEP_B;
- SET_PART(vreg, pf, pin_fn);
- SET_PART(vreg, pc, RPM_VREG_PIN_CTRL_NONE);
- }
-
- mutex_unlock(&vreg->pc_lock);
-
- if (rc)
- goto bail;
-
- rdev = regulator_register(rdesc, dev, &(pdata->init_data), vreg);
- if (IS_ERR(rdev)) {
- rc = PTR_ERR(rdev);
- pr_err("regulator_register failed: %s, rc=%d\n", reg_name, rc);
- return rc;
- } else {
- if (is_real_regulator(pdata->id))
- vreg->rdev = rdev;
- else
- vreg->rdev_pc = rdev;
- }
-
-bail:
- if (rc)
- pr_err("error for %s, rc=%d\n", reg_name, rc);
-
- return rc;
-}
-
-static int __devinit rpm_vreg_probe(struct platform_device *pdev)
-{
- struct rpm_regulator_platform_data *platform_data;
- int rc = 0;
- int i;
-
- platform_data = pdev->dev.platform_data;
- if (!platform_data) {
- pr_err("rpm-regulator requires platform data\n");
- return -EINVAL;
- }
-
- /* Initialize all of the regulators listed in the platform data. */
- for (i = 0; i < platform_data->num_regulators; i++) {
- rc = rpm_vreg_init_regulator(&platform_data->init_data[i],
- &pdev->dev);
- if (rc) {
- pr_err("rpm_vreg_init_regulator failed, rc=%d\n", rc);
- goto remove_regulators;
- }
- }
-
- platform_set_drvdata(pdev, platform_data);
-
- return rc;
-
-remove_regulators:
- /* Unregister all regulators added before the erroring one. */
- for (; i >= 0; i--) {
- if (is_real_regulator(platform_data->init_data[i].id))
- regulator_unregister(vregs[i].rdev);
- else
- regulator_unregister(
- vregs[pc_id_to_real_id(i)].rdev_pc);
- }
-
- return rc;
-}
-
-static int __devexit rpm_vreg_remove(struct platform_device *pdev)
-{
- struct rpm_regulator_platform_data *platform_data;
- int i, id;
-
- platform_data = platform_get_drvdata(pdev);
- platform_set_drvdata(pdev, NULL);
-
- if (platform_data) {
- for (i = 0; i < platform_data->num_regulators; i++) {
- id = platform_data->init_data[i].id;
- if (is_real_regulator(id)) {
- regulator_unregister(vregs[id].rdev);
- vregs[id].rdev = NULL;
- } else {
- regulator_unregister(
- vregs[pc_id_to_real_id(id)].rdev_pc);
- vregs[id].rdev_pc = NULL;
- }
- }
- }
-
- return 0;
-}
-
-static struct platform_driver rpm_vreg_driver = {
- .probe = rpm_vreg_probe,
- .remove = __devexit_p(rpm_vreg_remove),
- .driver = {
- .name = RPM_REGULATOR_DEV_NAME,
- .owner = THIS_MODULE,
- },
+ .is_real_id = is_real_id,
+ .pc_id_to_real_id = pc_id_to_real_id,
};
-static int __init rpm_vreg_init(void)
+struct vreg_config *get_config_8960(void)
{
- struct vreg_set_points *set_points[] = {
- &pldo_set_points,
- &nldo_set_points,
- &nldo1200_set_points,
- &smps_set_points,
- &ftsmps_set_points,
- &ncp_set_points,
- };
- int i, j;
-
- /* Calculate the number of set points available for each regualtor. */
- for (i = 0; i < ARRAY_SIZE(set_points); i++) {
- for (j = 0; j < set_points[i]->count; j++) {
- set_points[i]->range[j].n_voltages
- = (set_points[i]->range[j].max_uV
- - set_points[i]->range[j].min_uV)
- / set_points[i]->range[j].step_uV + 1;
- set_points[i]->n_voltages
- += set_points[i]->range[j].n_voltages;
- }
- }
-
- /* Initialize pin control mutexes */
- for (i = 0; i < ARRAY_SIZE(vregs); i++)
- mutex_init(&vregs[i].pc_lock);
-
- return platform_driver_register(&rpm_vreg_driver);
+ return &config;
}
-
-static void __exit rpm_vreg_exit(void)
-{
- int i;
-
- platform_driver_unregister(&rpm_vreg_driver);
-
- for (i = 0; i < ARRAY_SIZE(vregs); i++)
- mutex_destroy(&vregs[i].pc_lock);
-}
-
-postcore_initcall(rpm_vreg_init);
-module_exit(rpm_vreg_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("MSM8960 rpm regulator driver");
-MODULE_VERSION("1.0");
-MODULE_ALIAS("platform:" RPM_REGULATOR_DEV_NAME);
diff --git a/arch/arm/mach-msm/rpm-regulator-9615.c b/arch/arm/mach-msm/rpm-regulator-9615.c
new file mode 100644
index 0000000..23c0ee3
--- /dev/null
+++ b/arch/arm/mach-msm/rpm-regulator-9615.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include "rpm-regulator-private.h"
+
+/* RPM regulator request formats */
+static struct rpm_vreg_parts ldo_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+};
+
+static struct rpm_vreg_parts smps_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+ .pm = REQUEST_MEMBER(1, 0x00800000, 23),
+ .freq = REQUEST_MEMBER(1, 0x1F000000, 24),
+ .freq_clk_src = REQUEST_MEMBER(1, 0x60000000, 29),
+};
+
+static struct rpm_vreg_parts switch_parts = {
+ .request_len = 1,
+ .enable_state = REQUEST_MEMBER(0, 0x00000001, 0),
+ .pd = REQUEST_MEMBER(0, 0x00000002, 1),
+ .pc = REQUEST_MEMBER(0, 0x0000003C, 2),
+ .pf = REQUEST_MEMBER(0, 0x000003C0, 6),
+ .hpm = REQUEST_MEMBER(0, 0x00000C00, 10),
+};
+
+/* Physically available PMIC regulator voltage setpoint ranges */
+static struct vreg_range pldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+ VOLTAGE_RANGE(3100000, 4900000, 50000),
+};
+
+static struct vreg_range nldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range nldo1200_ranges[] = {
+ VOLTAGE_RANGE( 375000, 743750, 6250),
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range smps_ranges[] = {
+ VOLTAGE_RANGE( 375000, 737500, 12500),
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+};
+
+static struct vreg_set_points pldo_set_points = SET_POINTS(pldo_ranges);
+static struct vreg_set_points nldo_set_points = SET_POINTS(nldo_ranges);
+static struct vreg_set_points nldo1200_set_points = SET_POINTS(nldo1200_ranges);
+static struct vreg_set_points smps_set_points = SET_POINTS(smps_ranges);
+
+static struct vreg_set_points *all_set_points[] = {
+ &pldo_set_points,
+ &nldo_set_points,
+ &nldo1200_set_points,
+ &smps_set_points,
+};
+
+#define LDO(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8018_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8018_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8018_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_9615_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_LDO, \
+ .set_points = &_ranges##_set_points, \
+ .part = &ldo_parts, \
+ .id = RPM_VREG_ID_PM8018_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define SMPS(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8018_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8018_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8018_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_9615_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_SMPS, \
+ .set_points = &_ranges##_set_points, \
+ .part = &smps_parts, \
+ .id = RPM_VREG_ID_PM8018_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define LVS(_id, _name, _name_pc) \
+ [RPM_VREG_ID_PM8018_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8018_##_id, }, \
+ [1] = { .id = -1, }, \
+ }, \
+ .type = RPM_REGULATOR_TYPE_VS, \
+ .part = &switch_parts, \
+ .id = RPM_VREG_ID_PM8018_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+static struct vreg vregs[] = {
+ LDO(L2, "8018_l2", "8018_l2_pc", pldo, LDO_50),
+ LDO(L3, "8018_l3", "8018_l3_pc", pldo, LDO_50),
+ LDO(L4, "8018_l4", "8018_l4_pc", pldo, LDO_300),
+ LDO(L5, "8018_l5", "8018_l5_pc", pldo, LDO_150),
+ LDO(L6, "8018_l6", "8018_l6_pc", pldo, LDO_150),
+ LDO(L7, "8018_l7", "8018_l7_pc", pldo, LDO_300),
+ LDO(L8, "8018_l8", "8018_l8_pc", nldo, LDO_150),
+ LDO(L9, "8018_l9", NULL, nldo1200, LDO_1200),
+ LDO(L10, "8018_l10", NULL, nldo1200, LDO_1200),
+ LDO(L11, "8018_l11", NULL, nldo1200, LDO_1200),
+ LDO(L12, "8018_l12", NULL, nldo1200, LDO_1200),
+ LDO(L13, "8018_l13", "8018_l13_pc", pldo, LDO_50),
+ LDO(L14, "8018_l14", "8018_l14_pc", pldo, LDO_50),
+
+ SMPS(S1, "8018_s1", "8018_s1_pc", smps, SMPS_1500),
+ SMPS(S2, "8018_s2", "8018_s2_pc", smps, SMPS_1500),
+ SMPS(S3, "8018_s3", "8018_s3_pc", smps, SMPS_1500),
+ SMPS(S4, "8018_s4", "8018_s4_pc", smps, SMPS_1500),
+ SMPS(S5, "8018_s5", "8018_s5_pc", smps, SMPS_1500),
+
+ LVS(LVS1, "8018_lvs1", "8018_lvs1_pc"),
+};
+
+static const char *pin_control_label[] = {
+ " D1",
+ " A0",
+ " A1",
+ " A2",
+};
+
+static const char *pin_func_label[] = {
+ [RPM_VREG_PIN_FN_9615_DONT_CARE] = "don't care",
+ [RPM_VREG_PIN_FN_9615_ENABLE] = "on/off",
+ [RPM_VREG_PIN_FN_9615_MODE] = "HPM/LPM",
+ [RPM_VREG_PIN_FN_9615_SLEEP_B] = "sleep_b",
+ [RPM_VREG_PIN_FN_9615_NONE] = "none",
+};
+
+static const char *force_mode_label[] = {
+ [RPM_VREG_FORCE_MODE_9615_NONE] = "none",
+ [RPM_VREG_FORCE_MODE_9615_LPM] = "LPM",
+ [RPM_VREG_FORCE_MODE_9615_AUTO] = "auto",
+ [RPM_VREG_FORCE_MODE_9615_HPM] = "HPM",
+ [RPM_VREG_FORCE_MODE_9615_BYPASS] = "BYP",
+};
+
+static const char *power_mode_label[] = {
+ [RPM_VREG_POWER_MODE_9615_HYSTERETIC] = "HYS",
+ [RPM_VREG_POWER_MODE_9615_PWM] = "PWM",
+};
+
+static int is_real_id(int id)
+{
+ return (id >= 0) && (id <= RPM_VREG_ID_PM8018_MAX_REAL);
+}
+
+static int pc_id_to_real_id(int id)
+{
+ int real_id;
+
+ if (id >= RPM_VREG_ID_PM8018_L2_PC && id <= RPM_VREG_ID_PM8018_L8_PC)
+ real_id = id - RPM_VREG_ID_PM8018_L2_PC + RPM_VREG_ID_PM8018_L2;
+ else
+ real_id = id - RPM_VREG_ID_PM8018_L13_PC
+ + RPM_VREG_ID_PM8018_L13;
+
+ return real_id;
+}
+
+static struct vreg_config config = {
+ .vregs = vregs,
+ .vregs_len = ARRAY_SIZE(vregs),
+
+ .vreg_id_min = RPM_VREG_ID_PM8018_L2,
+ .vreg_id_max = RPM_VREG_ID_PM8018_MAX,
+
+ .pin_func_none = RPM_VREG_PIN_FN_9615_NONE,
+ .pin_func_sleep_b = RPM_VREG_PIN_FN_9615_SLEEP_B,
+
+ .mode_lpm = REGULATOR_MODE_IDLE,
+ .mode_hpm = REGULATOR_MODE_NORMAL,
+
+ .set_points = all_set_points,
+ .set_points_len = ARRAY_SIZE(all_set_points),
+
+ .label_pin_ctrl = pin_control_label,
+ .label_pin_ctrl_len = ARRAY_SIZE(pin_control_label),
+ .label_pin_func = pin_func_label,
+ .label_pin_func_len = ARRAY_SIZE(pin_func_label),
+ .label_force_mode = force_mode_label,
+ .label_force_mode_len = ARRAY_SIZE(force_mode_label),
+ .label_power_mode = power_mode_label,
+ .label_power_mode_len = ARRAY_SIZE(power_mode_label),
+
+ .is_real_id = is_real_id,
+ .pc_id_to_real_id = pc_id_to_real_id,
+};
+
+struct vreg_config *get_config_9615(void)
+{
+ return &config;
+}
diff --git a/arch/arm/mach-msm/rpm-regulator-private.h b/arch/arm/mach-msm/rpm-regulator-private.h
new file mode 100644
index 0000000..ff127d9
--- /dev/null
+++ b/arch/arm/mach-msm/rpm-regulator-private.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_RPM_REGULATOR_INT_H
+#define __ARCH_ARM_MACH_MSM_RPM_REGULATOR_INT_H
+
+#include <linux/regulator/driver.h>
+#include <mach/rpm.h>
+#include <mach/rpm-regulator.h>
+
+/* Possible RPM regulator request types */
+enum rpm_regulator_type {
+ RPM_REGULATOR_TYPE_LDO,
+ RPM_REGULATOR_TYPE_SMPS,
+ RPM_REGULATOR_TYPE_VS,
+ RPM_REGULATOR_TYPE_NCP,
+ RPM_REGULATOR_TYPE_MAX = RPM_REGULATOR_TYPE_NCP,
+};
+
+struct request_member {
+ int word;
+ unsigned int mask;
+ int shift;
+};
+
+/* Possible RPM regulator request members */
+struct rpm_vreg_parts {
+ struct request_member mV; /* voltage: used if voltage is in mV */
+ struct request_member uV; /* voltage: used if voltage is in uV */
+ struct request_member ip; /* peak current in mA */
+ struct request_member pd; /* pull down enable */
+ struct request_member ia; /* average current in mA */
+ struct request_member fm; /* force mode */
+ struct request_member pm; /* power mode */
+ struct request_member pc; /* pin control */
+ struct request_member pf; /* pin function */
+ struct request_member enable_state; /* NCP and switch */
+ struct request_member comp_mode; /* NCP */
+ struct request_member freq; /* frequency: NCP and SMPS */
+ struct request_member freq_clk_src; /* clock source: SMPS */
+ struct request_member hpm; /* switch: control OCP and SS */
+ int request_len;
+};
+
+struct vreg_range {
+ int min_uV;
+ int max_uV;
+ int step_uV;
+ unsigned n_voltages;
+};
+
+struct vreg_set_points {
+ struct vreg_range *range;
+ int count;
+ unsigned n_voltages;
+};
+
+struct vreg {
+ struct msm_rpm_iv_pair req[2];
+ struct msm_rpm_iv_pair prev_active_req[2];
+ struct msm_rpm_iv_pair prev_sleep_req[2];
+ struct rpm_regulator_init_data pdata;
+ struct regulator_desc rdesc;
+ struct regulator_desc rdesc_pc;
+ struct regulator_dev *rdev;
+ struct regulator_dev *rdev_pc;
+ struct vreg_set_points *set_points;
+ struct rpm_vreg_parts *part;
+ int type;
+ int id;
+ struct mutex pc_lock;
+ int save_uV;
+ int mode;
+ bool is_enabled;
+ bool is_enabled_pc;
+ const int hpm_min_load;
+ int active_min_uV_vote[RPM_VREG_VOTER_COUNT];
+ int sleep_min_uV_vote[RPM_VREG_VOTER_COUNT];
+};
+
+struct vreg_config {
+ struct vreg *vregs;
+ int vregs_len;
+
+ int vreg_id_min;
+ int vreg_id_max;
+
+ int pin_func_none;
+ int pin_func_sleep_b;
+
+ unsigned int mode_lpm;
+ unsigned int mode_hpm;
+
+ struct vreg_set_points **set_points;
+ int set_points_len;
+
+ const char **label_pin_ctrl;
+ int label_pin_ctrl_len;
+ const char **label_pin_func;
+ int label_pin_func_len;
+ const char **label_force_mode;
+ int label_force_mode_len;
+ const char **label_power_mode;
+ int label_power_mode_len;
+
+ int (*is_real_id) (int vreg_id);
+ int (*pc_id_to_real_id) (int vreg_id);
+
+ /* Legacy options to be used with MSM8660 */
+ int use_legacy_optimum_mode;
+ int ia_follows_ip;
+};
+
+#define REQUEST_MEMBER(_word, _mask, _shift) \
+ { \
+ .word = _word, \
+ .mask = _mask, \
+ .shift = _shift, \
+ }
+
+#define VOLTAGE_RANGE(_min_uV, _max_uV, _step_uV) \
+ { \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .step_uV = _step_uV, \
+ }
+
+#define SET_POINTS(_ranges) \
+{ \
+ .range = _ranges, \
+ .count = ARRAY_SIZE(_ranges), \
+};
+
+#define MICRO_TO_MILLI(uV) ((uV) / 1000)
+#define MILLI_TO_MICRO(mV) ((mV) * 1000)
+
+#if defined(CONFIG_ARCH_MSM8X60)
+struct vreg_config *get_config_8660(void);
+#else
+static inline struct vreg_config *get_config_8660(void)
+{
+ return NULL;
+}
+#endif
+
+#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064)
+struct vreg_config *get_config_8960(void);
+#else
+static inline struct vreg_config *get_config_8960(void)
+{
+ return NULL;
+}
+#endif
+
+#if defined(CONFIG_ARCH_MSM9615)
+struct vreg_config *get_config_9615(void);
+#else
+static inline struct vreg_config *get_config_9615(void)
+{
+ return NULL;
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-msm/rpm-regulator.c b/arch/arm/mach-msm/rpm-regulator.c
index b9e577a..2494969 100644
--- a/arch/arm/mach-msm/rpm-regulator.c
+++ b/arch/arm/mach-msm/rpm-regulator.c
@@ -1,4 +1,5 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/*
+ * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,18 +11,22 @@
* GNU General Public License for more details.
*/
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
#include <linux/module.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
-#include <linux/mfd/pmic8901.h>
#include <mach/rpm.h>
#include <mach/rpm-regulator.h>
+#include <mach/socinfo.h>
#include "rpm_resources.h"
+#include "rpm-regulator-private.h"
/* Debug Definitions */
@@ -29,7 +34,7 @@
MSM_RPM_VREG_DEBUG_REQUEST = BIT(0),
MSM_RPM_VREG_DEBUG_VOTE = BIT(1),
MSM_RPM_VREG_DEBUG_DUPLICATE = BIT(2),
- MSM_RPM_VREG_DEBUG_IGNORE_8058_S0_S1 = BIT(3),
+ MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG = BIT(3),
};
static int msm_rpm_vreg_debug_mask;
@@ -37,241 +42,242 @@
debug_mask, msm_rpm_vreg_debug_mask, int, S_IRUSR | S_IWUSR
);
-#define MICRO_TO_MILLI(uV) ((uV) / 1000)
-#define MILLI_TO_MICRO(mV) ((mV) * 1000)
+struct vreg_config *(*get_config[])(void) = {
+ [RPM_VREG_VERSION_8660] = get_config_8660,
+ [RPM_VREG_VERSION_8960] = get_config_8960,
+ [RPM_VREG_VERSION_9615] = get_config_9615,
+};
-/* LDO register word 1 */
-#define LDO_VOLTAGE 0x00000FFF
-#define LDO_VOLTAGE_SHIFT 0
-#define LDO_PEAK_CURRENT 0x00FFF000
-#define LDO_PEAK_CURRENT_SHIFT 12
-#define LDO_MODE 0x03000000
-#define LDO_MODE_SHIFT 24
-#define LDO_PIN_CTRL 0x3C000000
-#define LDO_PIN_CTRL_SHIFT 26
-#define LDO_PIN_FN 0xC0000000
-#define LDO_PIN_FN_SHIFT 30
+#define SET_PART(_vreg, _part, _val) \
+ _vreg->req[_vreg->part->_part.word].value \
+ = (_vreg->req[_vreg->part->_part.word].value \
+ & ~vreg->part->_part.mask) \
+ | (((_val) << vreg->part->_part.shift) & vreg->part->_part.mask)
-/* LDO register word 2 */
-#define LDO_PULL_DOWN_ENABLE 0x00000001
-#define LDO_PULL_DOWN_ENABLE_SHIFT 0
-#define LDO_AVG_CURRENT 0x00001FFE
-#define LDO_AVG_CURRENT_SHIFT 1
+#define GET_PART(_vreg, _part) \
+ ((_vreg->req[_vreg->part->_part.word].value & vreg->part->_part.mask) \
+ >> vreg->part->_part.shift)
-/* SMPS register word 1 */
-#define SMPS_VOLTAGE 0x00000FFF
-#define SMPS_VOLTAGE_SHIFT 0
-#define SMPS_PEAK_CURRENT 0x00FFF000
-#define SMPS_PEAK_CURRENT_SHIFT 12
-#define SMPS_MODE 0x03000000
-#define SMPS_MODE_SHIFT 24
-#define SMPS_PIN_CTRL 0x3C000000
-#define SMPS_PIN_CTRL_SHIFT 26
-#define SMPS_PIN_FN 0xC0000000
-#define SMPS_PIN_FN_SHIFT 30
+#define USES_PART(_vreg, _part) (vreg->part->_part.mask)
-/* SMPS register word 2 */
-#define SMPS_PULL_DOWN_ENABLE 0x00000001
-#define SMPS_PULL_DOWN_ENABLE_SHIFT 0
-#define SMPS_AVG_CURRENT 0x00001FFE
-#define SMPS_AVG_CURRENT_SHIFT 1
-#define SMPS_FREQ 0x001FE000
-#define SMPS_FREQ_SHIFT 13
-#define SMPS_CLK_SRC 0x00600000
-#define SMPS_CLK_SRC_SHIFT 21
+#define vreg_err(vreg, fmt, ...) \
+ pr_err("%s: " fmt, vreg->rdesc.name, ##__VA_ARGS__)
-/* SWITCH register word 1 */
-#define SWITCH_STATE 0x0001
-#define SWITCH_STATE_SHIFT 0
-#define SWITCH_PULL_DOWN_ENABLE 0x0002
-#define SWITCH_PULL_DOWN_ENABLE_SHIFT 1
-#define SWITCH_PIN_CTRL 0x003C
-#define SWITCH_PIN_CTRL_SHIFT 2
-#define SWITCH_PIN_FN 0x00C0
-#define SWITCH_PIN_FN_SHIFT 6
+#define RPM_VREG_PIN_CTRL_EN0 0x01
+#define RPM_VREG_PIN_CTRL_EN1 0x02
+#define RPM_VREG_PIN_CTRL_EN2 0x04
+#define RPM_VREG_PIN_CTRL_EN3 0x08
+#define RPM_VREG_PIN_CTRL_ALL 0x0F
-/* NCP register word 1 */
-#define NCP_VOLTAGE 0x0FFF
-#define NCP_VOLTAGE_SHIFT 0
-#define NCP_STATE 0x1000
-#define NCP_STATE_SHIFT 12
-
+static const char *label_freq[] = {
+ [RPM_VREG_FREQ_NONE] = " N/A",
+ [RPM_VREG_FREQ_19p20] = "19.2",
+ [RPM_VREG_FREQ_9p60] = "9.60",
+ [RPM_VREG_FREQ_6p40] = "6.40",
+ [RPM_VREG_FREQ_4p80] = "4.80",
+ [RPM_VREG_FREQ_3p84] = "3.84",
+ [RPM_VREG_FREQ_3p20] = "3.20",
+ [RPM_VREG_FREQ_2p74] = "2.74",
+ [RPM_VREG_FREQ_2p40] = "2.40",
+ [RPM_VREG_FREQ_2p13] = "2.13",
+ [RPM_VREG_FREQ_1p92] = "1.92",
+ [RPM_VREG_FREQ_1p75] = "1.75",
+ [RPM_VREG_FREQ_1p60] = "1.60",
+ [RPM_VREG_FREQ_1p48] = "1.48",
+ [RPM_VREG_FREQ_1p37] = "1.37",
+ [RPM_VREG_FREQ_1p28] = "1.28",
+ [RPM_VREG_FREQ_1p20] = "1.20",
+};
/*
* This is used when voting for LPM or HPM by subtracting or adding to the
* hpm_min_load of a regulator. It has units of uA.
*/
-#define LOAD_THRESHOLD_STEP 1000
+#define LOAD_THRESHOLD_STEP 1000
-/* This is the maximum uA load that can be passed to the RPM. */
-#define MAX_POSSIBLE_LOAD (MILLI_TO_MICRO(0xFFF))
+/* rpm_version keeps track of the version for the currently running driver. */
+enum rpm_vreg_version rpm_version = -1;
-/* Voltage regulator types */
-#define IS_LDO(id) ((id >= RPM_VREG_ID_PM8058_L0 && \
- id <= RPM_VREG_ID_PM8058_L25) || \
- (id >= RPM_VREG_ID_PM8901_L0 && \
- id <= RPM_VREG_ID_PM8901_L6))
-#define IS_SMPS(id) ((id >= RPM_VREG_ID_PM8058_S0 && \
- id <= RPM_VREG_ID_PM8058_S4) || \
- (id >= RPM_VREG_ID_PM8901_S0 && \
- id <= RPM_VREG_ID_PM8901_S4))
-#define IS_SWITCH(id) ((id >= RPM_VREG_ID_PM8058_LVS0 && \
- id <= RPM_VREG_ID_PM8058_LVS1) || \
- (id >= RPM_VREG_ID_PM8901_LVS0 && \
- id <= RPM_VREG_ID_PM8901_LVS3) || \
- (id == RPM_VREG_ID_PM8901_MVS0))
-#define IS_NCP(id) (id == RPM_VREG_ID_PM8058_NCP)
+/* config holds all configuration data of the currently running driver. */
+static struct vreg_config *config;
-#define IS_8901_SMPS(id) ((id >= RPM_VREG_ID_PM8901_S0 && \
- id <= RPM_VREG_ID_PM8901_S4))
+/* These regulator ID values are specified in the board file. */
+static int vreg_id_vdd_mem, vreg_id_vdd_dig;
-struct vreg {
- struct msm_rpm_iv_pair req[2];
- struct msm_rpm_iv_pair prev_active_req[2];
- struct msm_rpm_iv_pair prev_sleep_req[2];
- struct rpm_vreg_pdata *pdata;
- int save_uV;
- const int hpm_min_load;
- unsigned pc_vote;
- unsigned optimum;
- unsigned mode_initialized;
- int active_min_mV_vote[RPM_VREG_VOTER_COUNT];
- int sleep_min_mV_vote[RPM_VREG_VOTER_COUNT];
- enum rpm_vreg_id id;
-};
+static inline int vreg_id_is_vdd_mem_or_dig(int id)
+{
+ return id == vreg_id_vdd_mem || id == vreg_id_vdd_dig;
+}
-#define RPM_VREG_NCP_HPM_MIN_LOAD 0
+#define DEBUG_PRINT_BUFFER_SIZE 512
-#define VREG_2(_vreg_id, _rpm_id, _hpm_min_load) \
- [RPM_VREG_ID_##_vreg_id] = { \
- .req = { \
- [0] = { .id = MSM_RPM_ID_##_rpm_id##_0, }, \
- [1] = { .id = MSM_RPM_ID_##_rpm_id##_1, }, \
- }, \
- .hpm_min_load = RPM_VREG_##_hpm_min_load, \
+static void rpm_regulator_req(struct vreg *vreg, int set)
+{
+ int uV, mV, fm, pm, pc, pf, pd, freq, state, i;
+ const char *pf_label = "", *fm_label = "", *pc_total = "";
+ const char *pc_en[4] = {"", "", "", ""};
+ const char *pm_label = "", *freq_label = "";
+ char buf[DEBUG_PRINT_BUFFER_SIZE];
+ size_t buflen = DEBUG_PRINT_BUFFER_SIZE;
+ int pos = 0;
+
+ /* Suppress VDD_MEM and VDD_DIG printing. */
+ if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
+ && vreg_id_is_vdd_mem_or_dig(vreg->id))
+ return;
+
+ uV = GET_PART(vreg, uV);
+ mV = GET_PART(vreg, mV);
+ if (vreg->type == RPM_REGULATOR_TYPE_NCP) {
+ uV = -uV;
+ mV = -mV;
}
-#define VREG_1(_vreg_id, _rpm_id) \
- [RPM_VREG_ID_##_vreg_id] = { \
- .req = { \
- [0] = { .id = MSM_RPM_ID_##_rpm_id, }, \
- [1] = { .id = -1, }, \
- }, \
+ fm = GET_PART(vreg, fm);
+ pm = GET_PART(vreg, pm);
+ pc = GET_PART(vreg, pc);
+ pf = GET_PART(vreg, pf);
+ pd = GET_PART(vreg, pd);
+ freq = GET_PART(vreg, freq);
+ state = GET_PART(vreg, enable_state);
+
+ if (pf >= 0 && pf < config->label_pin_func_len)
+ pf_label = config->label_pin_func[pf];
+
+ if (fm >= 0 && fm < config->label_force_mode_len)
+ fm_label = config->label_force_mode[fm];
+
+ if (pm >= 0 && pm < config->label_power_mode_len)
+ pm_label = config->label_power_mode[pm];
+
+ if (freq >= 0 && freq < ARRAY_SIZE(label_freq))
+ freq_label = label_freq[freq];
+
+ for (i = 0; i < config->label_pin_ctrl_len; i++)
+ if (pc & (1 << i))
+ pc_en[i] = config->label_pin_ctrl[i];
+
+ if (pc == RPM_VREG_PIN_CTRL_NONE)
+ pc_total = " none";
+
+ pos += scnprintf(buf + pos, buflen - pos, "%s%s: ",
+ KERN_INFO, __func__);
+
+ pos += scnprintf(buf + pos, buflen - pos, "%s %-9s: s=%c",
+ (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
+ vreg->rdesc.name,
+ (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'));
+
+ if (USES_PART(vreg, uV))
+ pos += scnprintf(buf + pos, buflen - pos, ", v=%7d uV", uV);
+ if (USES_PART(vreg, mV))
+ pos += scnprintf(buf + pos, buflen - pos, ", v=%4d mV", mV);
+ if (USES_PART(vreg, enable_state))
+ pos += scnprintf(buf + pos, buflen - pos, ", state=%s (%d)",
+ (state == 1 ? "on" : "off"), state);
+ if (USES_PART(vreg, ip))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", ip=%4d mA", GET_PART(vreg, ip));
+ if (USES_PART(vreg, fm))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", fm=%s (%d)", fm_label, fm);
+ if (USES_PART(vreg, pc))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", pc=%s%s%s%s%s (%X)", pc_en[0], pc_en[1],
+ pc_en[2], pc_en[3], pc_total, pc);
+ if (USES_PART(vreg, pf))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", pf=%s (%d)", pf_label, pf);
+ if (USES_PART(vreg, pd))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", pd=%s (%d)", (pd == 1 ? "Y" : "N"), pd);
+ if (USES_PART(vreg, ia))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", ia=%4d mA", GET_PART(vreg, ia));
+ if (USES_PART(vreg, freq)) {
+ if (vreg->type == RPM_REGULATOR_TYPE_NCP)
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", freq=%2d", freq);
+ else
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", freq=%s MHz (%2d)", freq_label, freq);
}
+ if (USES_PART(vreg, pm))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", pm=%s (%d)", pm_label, pm);
+ if (USES_PART(vreg, freq_clk_src))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", clk_src=%d", GET_PART(vreg, freq_clk_src));
+ if (USES_PART(vreg, comp_mode))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", comp=%d", GET_PART(vreg, comp_mode));
+ if (USES_PART(vreg, hpm))
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", hpm=%d", GET_PART(vreg, hpm));
-static struct vreg vregs[RPM_VREG_ID_MAX] = {
- VREG_2(PM8058_L0, LDO0, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L1, LDO1, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L2, LDO2, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L3, LDO3, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L4, LDO4, LDO_50_HPM_MIN_LOAD),
- VREG_2(PM8058_L5, LDO5, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L6, LDO6, LDO_50_HPM_MIN_LOAD),
- VREG_2(PM8058_L7, LDO7, LDO_50_HPM_MIN_LOAD),
- VREG_2(PM8058_L8, LDO8, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L9, LDO9, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L10, LDO10, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L11, LDO11, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L12, LDO12, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L13, LDO13, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L14, LDO14, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L15, LDO15, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L16, LDO16, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L17, LDO17, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L18, LDO18, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L19, LDO19, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L20, LDO20, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L21, LDO21, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L22, LDO22, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L23, LDO23, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8058_L24, LDO24, LDO_150_HPM_MIN_LOAD),
- VREG_2(PM8058_L25, LDO25, LDO_150_HPM_MIN_LOAD),
+ pos += scnprintf(buf + pos, buflen - pos, "; req[0]={%d, 0x%08X}",
+ vreg->req[0].id, vreg->req[0].value);
+ if (vreg->part->request_len > 1)
+ pos += scnprintf(buf + pos, buflen - pos,
+ ", req[1]={%d, 0x%08X}", vreg->req[1].id,
+ vreg->req[1].value);
- VREG_2(PM8058_S0, SMPS0, SMPS_HPM_MIN_LOAD),
- VREG_2(PM8058_S1, SMPS1, SMPS_HPM_MIN_LOAD),
- VREG_2(PM8058_S2, SMPS2, SMPS_HPM_MIN_LOAD),
- VREG_2(PM8058_S3, SMPS3, SMPS_HPM_MIN_LOAD),
- VREG_2(PM8058_S4, SMPS4, SMPS_HPM_MIN_LOAD),
+ pos += scnprintf(buf + pos, buflen - pos, "\n");
+ printk(buf);
+}
- VREG_1(PM8058_LVS0, LVS0),
- VREG_1(PM8058_LVS1, LVS1),
+static void rpm_regulator_vote(struct vreg *vreg, enum rpm_vreg_voter voter,
+ int set, int voter_uV, int aggregate_uV)
+{
+ /* Suppress VDD_MEM and VDD_DIG printing. */
+ if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
+ && vreg_id_is_vdd_mem_or_dig(vreg->id))
+ return;
- VREG_2(PM8058_NCP, NCP, NCP_HPM_MIN_LOAD),
+ pr_info("vote received %-9s: voter=%d, set=%c, v_voter=%7d uV, "
+ "v_aggregate=%7d uV\n", vreg->rdesc.name, voter,
+ (set == 0 ? 'A' : 'S'), voter_uV, aggregate_uV);
+}
- VREG_2(PM8901_L0, LDO0B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L1, LDO1B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L2, LDO2B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L3, LDO3B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L4, LDO4B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L5, LDO5B, LDO_300_HPM_MIN_LOAD),
- VREG_2(PM8901_L6, LDO6B, LDO_300_HPM_MIN_LOAD),
+static void rpm_regulator_duplicate(struct vreg *vreg, int set, int cnt)
+{
+ /* Suppress VDD_MEM and VDD_DIG printing. */
+ if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_VDD_MEM_DIG)
+ && vreg_id_is_vdd_mem_or_dig(vreg->id))
+ return;
- VREG_2(PM8901_S0, SMPS0B, FTSMPS_HPM_MIN_LOAD),
- VREG_2(PM8901_S1, SMPS1B, FTSMPS_HPM_MIN_LOAD),
- VREG_2(PM8901_S2, SMPS2B, FTSMPS_HPM_MIN_LOAD),
- VREG_2(PM8901_S3, SMPS3B, FTSMPS_HPM_MIN_LOAD),
- VREG_2(PM8901_S4, SMPS4B, FTSMPS_HPM_MIN_LOAD),
-
- VREG_1(PM8901_LVS0, LVS0B),
- VREG_1(PM8901_LVS1, LVS1B),
- VREG_1(PM8901_LVS2, LVS2B),
- VREG_1(PM8901_LVS3, LVS3B),
-
- VREG_1(PM8901_MVS0, MVS),
-};
-
-static void print_rpm_request(struct vreg *vreg, int set);
-static void print_rpm_vote(struct vreg *vreg, enum rpm_vreg_voter voter,
- int set, int voter_mV, int aggregate_mV);
-static void print_rpm_duplicate(struct vreg *vreg, int set, int cnt);
-
-static unsigned int smps_get_mode(struct regulator_dev *dev);
-static unsigned int ldo_get_mode(struct regulator_dev *dev);
-static unsigned int switch_get_mode(struct regulator_dev *dev);
+ if (cnt == 2)
+ pr_info("ignored request %-9s: set=%c; req[0]={%d, 0x%08X}, "
+ "req[1]={%d, 0x%08X}\n", vreg->rdesc.name,
+ (set == 0 ? 'A' : 'S'),
+ vreg->req[0].id, vreg->req[0].value,
+ vreg->req[1].id, vreg->req[1].value);
+ else if (cnt == 1)
+ pr_info("ignored request %-9s: set=%c; req[0]={%d, 0x%08X}\n",
+ vreg->rdesc.name, (set == 0 ? 'A' : 'S'),
+ vreg->req[0].id, vreg->req[0].value);
+}
/* Spin lock needed for sleep-selectable regulators. */
-static DEFINE_SPINLOCK(pm8058_noirq_lock);
+static DEFINE_SPINLOCK(rpm_noirq_lock);
static int voltage_from_req(struct vreg *vreg)
{
- int shift = 0;
- uint32_t value = 0, mask = 0;
+ int uV = 0;
- value = vreg->req[0].value;
+ if (vreg->part->uV.mask)
+ uV = GET_PART(vreg, uV);
+ else
+ uV = MILLI_TO_MICRO(GET_PART(vreg, mV));
- if (IS_SMPS(vreg->id)) {
- mask = SMPS_VOLTAGE;
- shift = SMPS_VOLTAGE_SHIFT;
- } else if (IS_LDO(vreg->id)) {
- mask = LDO_VOLTAGE;
- shift = LDO_VOLTAGE_SHIFT;
- } else if (IS_NCP(vreg->id)) {
- mask = NCP_VOLTAGE;
- shift = NCP_VOLTAGE_SHIFT;
- }
-
- return (value & mask) >> shift;
+ return uV;
}
-static void voltage_to_req(int voltage, struct vreg *vreg)
+static void voltage_to_req(int uV, struct vreg *vreg)
{
- int shift = 0;
- uint32_t *value = NULL, mask = 0;
-
- value = &(vreg->req[0].value);
-
- if (IS_SMPS(vreg->id)) {
- mask = SMPS_VOLTAGE;
- shift = SMPS_VOLTAGE_SHIFT;
- } else if (IS_LDO(vreg->id)) {
- mask = LDO_VOLTAGE;
- shift = LDO_VOLTAGE_SHIFT;
- } else if (IS_NCP(vreg->id)) {
- mask = NCP_VOLTAGE;
- shift = NCP_VOLTAGE_SHIFT;
- }
-
- *value &= ~mask;
- *value |= (voltage << shift) & mask;
+ if (vreg->part->uV.mask)
+ SET_PART(vreg, uV, uV);
+ else
+ SET_PART(vreg, mV, MICRO_TO_MILLI(uV));
}
static int vreg_send_request(struct vreg *vreg, enum rpm_vreg_voter voter,
@@ -280,15 +286,16 @@
int update_voltage)
{
struct msm_rpm_iv_pair *prev_req;
- int rc = 0, max_mV_vote = 0, i;
+ int rc = 0, max_uV_vote = 0;
unsigned prev0, prev1;
- int *min_mV_vote;
+ int *min_uV_vote;
+ int i;
if (set == MSM_RPM_CTX_SET_0) {
- min_mV_vote = vreg->active_min_mV_vote;
+ min_uV_vote = vreg->active_min_uV_vote;
prev_req = vreg->prev_active_req;
} else {
- min_mV_vote = vreg->sleep_min_mV_vote;
+ min_uV_vote = vreg->sleep_min_uV_vote;
prev_req = vreg->prev_sleep_req;
}
@@ -301,42 +308,41 @@
vreg->req[1].value |= val1 & mask1;
if (update_voltage)
- min_mV_vote[voter] = voltage_from_req(vreg);
+ min_uV_vote[voter] = voltage_from_req(vreg);
/* Find the highest voltage voted for and use it. */
for (i = 0; i < RPM_VREG_VOTER_COUNT; i++)
- max_mV_vote = max(max_mV_vote, min_mV_vote[i]);
- voltage_to_req(max_mV_vote, vreg);
+ max_uV_vote = max(max_uV_vote, min_uV_vote[i]);
+ voltage_to_req(max_uV_vote, vreg);
if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_VOTE)
- print_rpm_vote(vreg, voter, set, min_mV_vote[voter],
- max_mV_vote);
+ rpm_regulator_vote(vreg, voter, set, min_uV_vote[voter],
+ max_uV_vote);
/* Ignore duplicate requests */
if (vreg->req[0].value != prev_req[0].value ||
vreg->req[1].value != prev_req[1].value) {
-
rc = msm_rpmrs_set_noirq(set, vreg->req, cnt);
if (rc) {
vreg->req[0].value = prev0;
vreg->req[1].value = prev1;
- pr_err("%s: msm_rpmrs_set_noirq failed - "
- "set=%s, id=%d, rc=%d\n", __func__,
+ vreg_err(vreg, "msm_rpmrs_set_noirq failed - "
+ "set=%s, id=%d, rc=%d\n",
(set == MSM_RPM_CTX_SET_0 ? "active" : "sleep"),
vreg->req[0].id, rc);
} else {
/* Only save if nonzero and active set. */
- if (max_mV_vote && (set == MSM_RPM_CTX_SET_0))
- vreg->save_uV = MILLI_TO_MICRO(max_mV_vote);
+ if (max_uV_vote && (set == MSM_RPM_CTX_SET_0))
+ vreg->save_uV = max_uV_vote;
if (msm_rpm_vreg_debug_mask
& MSM_RPM_VREG_DEBUG_REQUEST)
- print_rpm_request(vreg, set);
+ rpm_regulator_req(vreg, set);
prev_req[0].value = vreg->req[0].value;
prev_req[1].value = vreg->req[1].value;
}
} else if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_DUPLICATE) {
- print_rpm_duplicate(vreg, set, cnt);
+ rpm_regulator_duplicate(vreg, set, cnt);
}
return rc;
@@ -347,14 +353,14 @@
unsigned mask1, unsigned val1, unsigned cnt,
int update_voltage)
{
+ unsigned int s_mask[2] = {mask0, mask1}, s_val[2] = {val0, val1};
unsigned long flags;
int rc;
- unsigned val0_sleep, mask0_sleep;
if (voter < 0 || voter >= RPM_VREG_VOTER_COUNT)
return -EINVAL;
- spin_lock_irqsave(&pm8058_noirq_lock, flags);
+ spin_lock_irqsave(&rpm_noirq_lock, flags);
/*
* Send sleep set request first so that subsequent set_mode, etc calls
@@ -369,28 +375,23 @@
* specified. This ensures that a disable vote will be issued
* at some point for the sleep set of the regulator.
*/
- val0_sleep = val0;
- mask0_sleep = mask0;
- if (IS_SMPS(vreg->id)) {
- val0_sleep &= ~SMPS_VOLTAGE;
- mask0_sleep |= SMPS_VOLTAGE;
- } else if (IS_LDO(vreg->id)) {
- val0_sleep &= ~LDO_VOLTAGE;
- mask0_sleep |= LDO_VOLTAGE;
- } else if (IS_NCP(vreg->id)) {
- val0_sleep &= ~NCP_VOLTAGE;
- mask0_sleep |= NCP_VOLTAGE;
+ if (vreg->part->uV.mask) {
+ s_val[vreg->part->uV.word] = 0 << vreg->part->uV.shift;
+ s_mask[vreg->part->uV.word] = vreg->part->uV.mask;
+ } else {
+ s_val[vreg->part->mV.word] = 0 << vreg->part->mV.shift;
+ s_mask[vreg->part->mV.word] = vreg->part->mV.mask;
}
rc = vreg_send_request(vreg, voter, MSM_RPM_CTX_SET_SLEEP,
- mask0_sleep, val0_sleep,
- mask1, val1, cnt, update_voltage);
+ s_mask[0], s_val[0], s_mask[1], s_val[1],
+ cnt, update_voltage);
}
rc = vreg_send_request(vreg, voter, MSM_RPM_CTX_SET_0, mask0, val0,
mask1, val1, cnt, update_voltage);
- spin_unlock_irqrestore(&pm8058_noirq_lock, flags);
+ spin_unlock_irqrestore(&rpm_noirq_lock, flags);
return rc;
}
@@ -416,38 +417,87 @@
* This function may only be called for regulators which have the sleep flag
* specified in their private data.
*/
-int rpm_vreg_set_voltage(enum rpm_vreg_id vreg_id, enum rpm_vreg_voter voter,
- int min_uV, int max_uV, int sleep_also)
+int rpm_vreg_set_voltage(int vreg_id, enum rpm_vreg_voter voter, int min_uV,
+ int max_uV, int sleep_also)
{
- int rc;
- unsigned val0 = 0, val1 = 0, mask0 = 0, mask1 = 0, cnt = 2;
+ unsigned int mask[2] = {0}, val[2] = {0};
+ struct vreg_range *range;
+ struct vreg *vreg;
+ int uV = min_uV;
+ int lim_min_uV, lim_max_uV, i, rc;
- if (vreg_id < 0 || vreg_id >= RPM_VREG_ID_MAX)
- return -EINVAL;
+ /*
+ * HACK: make this function a no-op for 8064 so that it can be called by
+ * consumers on 8064 before RPM capabilities are present. (needed for
+ * acpuclock driver)
+ */
+ if (cpu_is_apq8064())
+ return 0;
- if (!vregs[vreg_id].pdata->sleep_selectable)
- return -EINVAL;
-
- if (min_uV < vregs[vreg_id].pdata->init_data.constraints.min_uV ||
- min_uV > vregs[vreg_id].pdata->init_data.constraints.max_uV)
- return -EINVAL;
-
- if (IS_SMPS(vreg_id)) {
- mask0 = SMPS_VOLTAGE;
- val0 = MICRO_TO_MILLI(min_uV) << SMPS_VOLTAGE_SHIFT;
- } else if (IS_LDO(vreg_id)) {
- mask0 = LDO_VOLTAGE;
- val0 = MICRO_TO_MILLI(min_uV) << LDO_VOLTAGE_SHIFT;
- } else if (IS_NCP(vreg_id)) {
- mask0 = NCP_VOLTAGE;
- val0 = MICRO_TO_MILLI(min_uV) << NCP_VOLTAGE_SHIFT;
- cnt = 1;
- } else {
- cnt = 1;
+ if (!config) {
+ pr_err("rpm-regulator driver has not probed yet.\n");
+ return -ENODEV;
}
- rc = vreg_set_noirq(&vregs[vreg_id], voter, sleep_also, mask0, val0,
- mask1, val1, cnt, 1);
+ if (vreg_id < config->vreg_id_min || vreg_id > config->vreg_id_max) {
+ pr_err("invalid regulator id=%d\n", vreg_id);
+ return -EINVAL;
+ }
+
+ vreg = &config->vregs[vreg_id];
+ range = &vreg->set_points->range[0];
+
+ if (!vreg->pdata.sleep_selectable) {
+ vreg_err(vreg, "regulator is not marked sleep selectable\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Check if request voltage is outside of allowed range. The regulator
+ * core has already checked that constraint range is inside of the
+ * physically allowed range.
+ */
+ lim_min_uV = vreg->pdata.init_data.constraints.min_uV;
+ lim_max_uV = vreg->pdata.init_data.constraints.max_uV;
+
+ if (uV < lim_min_uV && max_uV >= lim_min_uV)
+ uV = lim_min_uV;
+
+ if (uV < lim_min_uV || uV > lim_max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside allowed v=[%d, %d]\n",
+ min_uV, max_uV, lim_min_uV, lim_max_uV);
+ return -EINVAL;
+ }
+
+ /* Find the range which uV is inside of. */
+ for (i = vreg->set_points->count - 1; i > 0; i--) {
+ if (uV > vreg->set_points->range[i - 1].max_uV) {
+ range = &vreg->set_points->range[i];
+ break;
+ }
+ }
+
+ /*
+ * Force uV to be an allowed set point and apply a ceiling function
+ * to non-set point values.
+ */
+ uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
+ uV = uV * range->step_uV + range->min_uV;
+
+ if (vreg->part->uV.mask) {
+ val[vreg->part->uV.word] = uV << vreg->part->uV.shift;
+ mask[vreg->part->uV.word] = vreg->part->uV.mask;
+ } else {
+ val[vreg->part->mV.word]
+ = MICRO_TO_MILLI(uV) << vreg->part->mV.shift;
+ mask[vreg->part->mV.word] = vreg->part->mV.mask;
+ }
+
+ rc = vreg_set_noirq(vreg, voter, sleep_also, mask[0], val[0], mask[1],
+ val[1], vreg->part->request_len, 1);
+ if (rc)
+ vreg_err(vreg, "vreg_set_noirq failed, rc=%d\n", rc);
return rc;
}
@@ -456,52 +506,60 @@
/**
* rpm_vreg_set_frequency - sets the frequency of a switching regulator
* @vreg: ID for regulator
- * @min_uV: minimum acceptable frequency of operation
+ * @freq: enum corresponding to desired frequency
*
* Returns 0 on success or errno.
*/
-int rpm_vreg_set_frequency(enum rpm_vreg_id vreg_id, enum rpm_vreg_freq freq)
+int rpm_vreg_set_frequency(int vreg_id, enum rpm_vreg_freq freq)
{
- unsigned val0 = 0, val1 = 0, mask0 = 0, mask1 = 0, cnt = 2;
+ unsigned int mask[2] = {0}, val[2] = {0};
+ struct vreg *vreg;
int rc;
- if (vreg_id < 0 || vreg_id >= RPM_VREG_ID_MAX) {
- pr_err("%s: invalid regulator id=%d\n", __func__, vreg_id);
+ /*
+ * HACK: make this function a no-op for 8064 so that it can be called by
+ * consumers on 8064 before RPM capabilities are present.
+ */
+ if (cpu_is_apq8064())
+ return 0;
+
+ if (!config) {
+ pr_err("rpm-regulator driver has not probed yet.\n");
+ return -ENODEV;
+ }
+
+ if (vreg_id < config->vreg_id_min || vreg_id > config->vreg_id_max) {
+ pr_err("invalid regulator id=%d\n", vreg_id);
return -EINVAL;
}
+ vreg = &config->vregs[vreg_id];
+
if (freq < 0 || freq > RPM_VREG_FREQ_1p20) {
- pr_err("%s: invalid frequency=%d\n", __func__, freq);
+ vreg_err(vreg, "invalid frequency=%d\n", freq);
+ return -EINVAL;
+ }
+ if (!vreg->pdata.sleep_selectable) {
+ vreg_err(vreg, "regulator is not marked sleep selectable\n");
+ return -EINVAL;
+ }
+ if (!vreg->part->freq.mask) {
+ vreg_err(vreg, "frequency not supported\n");
return -EINVAL;
}
- if (!IS_SMPS(vreg_id)) {
- pr_err("%s: regulator id=%d does not support frequency\n",
- __func__, vreg_id);
- return -EINVAL;
- }
+ val[vreg->part->freq.word] = freq << vreg->part->freq.shift;
+ mask[vreg->part->freq.word] = vreg->part->freq.mask;
- if (!vregs[vreg_id].pdata->sleep_selectable) {
- pr_err("%s: regulator id=%d is not marked sleep selectable\n",
- __func__, vreg_id);
- return -EINVAL;
- }
-
- mask1 = SMPS_FREQ;
- val1 = freq << SMPS_FREQ_SHIFT;
-
- rc = vreg_set_noirq(&vregs[vreg_id], RPM_VREG_VOTER_REG_FRAMEWORK,
- 1, mask0, val0, mask1, val1, cnt, 0);
+ rc = vreg_set_noirq(vreg, RPM_VREG_VOTER_REG_FRAMEWORK, 1, mask[0],
+ val[0], mask[1], val[1], vreg->part->request_len, 0);
+ if (rc)
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
return rc;
}
EXPORT_SYMBOL_GPL(rpm_vreg_set_frequency);
-#define IS_PMIC_8901_V1(rev) ((rev) == PM_8901_REV_1p0 || \
- (rev) == PM_8901_REV_1p1)
-
-#define PMIC_8901_V1_SCALE(uV) ((((uV) - 62100) * 23) / 25)
-
static inline int vreg_hpm_min_uA(struct vreg *vreg)
{
return vreg->hpm_min_load;
@@ -512,9 +570,19 @@
return vreg->hpm_min_load - LOAD_THRESHOLD_STEP;
}
-static inline unsigned saturate_load(unsigned load_uA)
+static inline unsigned saturate_peak_load(struct vreg *vreg, unsigned load_uA)
{
- return (load_uA > MAX_POSSIBLE_LOAD ? MAX_POSSIBLE_LOAD : load_uA);
+ unsigned load_max
+ = MILLI_TO_MICRO(vreg->part->ip.mask >> vreg->part->ip.shift);
+
+ return (load_uA > load_max ? load_max : load_uA);
+}
+
+static inline unsigned saturate_avg_load(struct vreg *vreg, unsigned load_uA)
+{
+ unsigned load_max
+ = MILLI_TO_MICRO(vreg->part->ia.mask >> vreg->part->ia.shift);
+ return (load_uA > load_max ? load_max : load_uA);
}
/* Change vreg->req, but do not send it to the RPM. */
@@ -523,8 +591,8 @@
{
unsigned long flags = 0;
- if (vreg->pdata->sleep_selectable)
- spin_lock_irqsave(&pm8058_noirq_lock, flags);
+ if (vreg->pdata.sleep_selectable)
+ spin_lock_irqsave(&rpm_noirq_lock, flags);
vreg->req[0].value &= ~mask0;
vreg->req[0].value |= val0 & mask0;
@@ -532,8 +600,8 @@
vreg->req[1].value &= ~mask1;
vreg->req[1].value |= val1 & mask1;
- if (vreg->pdata->sleep_selectable)
- spin_unlock_irqrestore(&pm8058_noirq_lock, flags);
+ if (vreg->pdata.sleep_selectable)
+ spin_unlock_irqrestore(&rpm_noirq_lock, flags);
return 0;
}
@@ -548,7 +616,7 @@
* Bypass the normal route for regulators that can be called to change
* just the active set values.
*/
- if (vreg->pdata->sleep_selectable)
+ if (vreg->pdata.sleep_selectable)
return vreg_set_noirq(vreg, RPM_VREG_VOTER_REG_FRAMEWORK, 1,
mask0, val0, mask1, val1, cnt, 1);
@@ -564,7 +632,7 @@
if (vreg->req[0].value == vreg->prev_active_req[0].value &&
vreg->req[1].value == vreg->prev_active_req[1].value) {
if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_DUPLICATE)
- print_rpm_duplicate(vreg, MSM_RPM_CTX_SET_0, cnt);
+ rpm_regulator_duplicate(vreg, MSM_RPM_CTX_SET_0, cnt);
return 0;
}
@@ -573,11 +641,11 @@
vreg->req[0].value = prev0;
vreg->req[1].value = prev1;
- pr_err("%s: msm_rpm_set fail id=%d, rc=%d\n",
- __func__, vreg->req[0].id, rc);
+ vreg_err(vreg, "msm_rpm_set failed, set=active, id=%d, rc=%d\n",
+ vreg->req[0].id, rc);
} else {
if (msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_REQUEST)
- print_rpm_request(vreg, MSM_RPM_CTX_SET_0);
+ rpm_regulator_req(vreg, MSM_RPM_CTX_SET_0);
vreg->prev_active_req[0].value = vreg->req[0].value;
vreg->prev_active_req[1].value = vreg->req[1].value;
}
@@ -585,880 +653,736 @@
return rc;
}
-static int smps_is_enabled(struct regulator_dev *dev)
+static int vreg_is_enabled(struct regulator_dev *rdev)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- return ((vreg->req[0].value & SMPS_VOLTAGE) >> SMPS_VOLTAGE_SHIFT) != 0;
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ int enabled;
+
+ mutex_lock(&vreg->pc_lock);
+ enabled = vreg->is_enabled;
+ mutex_unlock(&vreg->pc_lock);
+
+ return enabled;
}
-static int _smps_set_voltage(struct regulator_dev *dev, int min_uV)
+static void set_enable(struct vreg *vreg, unsigned int *mask, unsigned int *val)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- int scaled_min_uV = min_uV;
- static int pmic8901_rev;
-
- /* Scale input request voltage down if using v1 PMIC 8901. */
- if (IS_8901_SMPS(vreg->id) && min_uV) {
- if (pmic8901_rev <= 0)
- pmic8901_rev = pm8901_rev(NULL);
-
- if (pmic8901_rev < 0)
- pr_err("%s: setting %s to %d uV; PMIC 8901 revision "
- "unavailable, no scaling can be performed.\n",
- __func__, dev->desc->name, min_uV);
- else if (IS_PMIC_8901_V1(pmic8901_rev))
- scaled_min_uV = PMIC_8901_V1_SCALE(min_uV);
+ switch (vreg->type) {
+ case RPM_REGULATOR_TYPE_LDO:
+ case RPM_REGULATOR_TYPE_SMPS:
+ /* Enable by setting a voltage. */
+ if (vreg->part->uV.mask) {
+ val[vreg->part->uV.word]
+ |= vreg->save_uV << vreg->part->uV.shift;
+ mask[vreg->part->uV.word] |= vreg->part->uV.mask;
+ } else {
+ val[vreg->part->mV.word]
+ |= MICRO_TO_MILLI(vreg->save_uV)
+ << vreg->part->mV.shift;
+ mask[vreg->part->mV.word] |= vreg->part->mV.mask;
+ }
+ break;
+ case RPM_REGULATOR_TYPE_VS:
+ case RPM_REGULATOR_TYPE_NCP:
+ /* Enable by setting enable_state. */
+ val[vreg->part->enable_state.word]
+ |= RPM_VREG_STATE_ON << vreg->part->enable_state.shift;
+ mask[vreg->part->enable_state.word]
+ |= vreg->part->enable_state.mask;
}
-
- return vreg_set(vreg, SMPS_VOLTAGE,
- MICRO_TO_MILLI(scaled_min_uV) << SMPS_VOLTAGE_SHIFT,
- 0, 0, 2);
}
-static int smps_set_voltage(struct regulator_dev *dev, int min_uV, int max_uV,
+static int vreg_enable(struct regulator_dev *rdev)
+{
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mask[2] = {0}, val[2] = {0};
+ int rc = 0;
+
+ set_enable(vreg, mask, val);
+
+ mutex_lock(&vreg->pc_lock);
+
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
+ if (!rc)
+ vreg->is_enabled = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static void set_disable(struct vreg *vreg, unsigned int *mask,
+ unsigned int *val)
+{
+ switch (vreg->type) {
+ case RPM_REGULATOR_TYPE_LDO:
+ case RPM_REGULATOR_TYPE_SMPS:
+ /* Disable by setting a voltage of 0 uV. */
+ if (vreg->part->uV.mask) {
+ val[vreg->part->uV.word] |= 0 << vreg->part->uV.shift;
+ mask[vreg->part->uV.word] |= vreg->part->uV.mask;
+ } else {
+ val[vreg->part->mV.word] |= 0 << vreg->part->mV.shift;
+ mask[vreg->part->mV.word] |= vreg->part->mV.mask;
+ }
+ break;
+ case RPM_REGULATOR_TYPE_VS:
+ case RPM_REGULATOR_TYPE_NCP:
+ /* Disable by setting enable_state. */
+ val[vreg->part->enable_state.word]
+ |= RPM_VREG_STATE_OFF << vreg->part->enable_state.shift;
+ mask[vreg->part->enable_state.word]
+ |= vreg->part->enable_state.mask;
+ }
+}
+
+static int vreg_disable(struct regulator_dev *rdev)
+{
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mask[2] = {0}, val[2] = {0};
+ int rc = 0;
+
+ set_disable(vreg, mask, val);
+
+ mutex_lock(&vreg->pc_lock);
+
+ /* Only disable if pin control is not in use. */
+ if (!vreg->is_enabled_pc)
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
+
+ if (!rc)
+ vreg->is_enabled = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
+
+ return rc;
+}
+
+static int vreg_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
unsigned *selector)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- int rc = 0;
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ struct vreg_range *range = &vreg->set_points->range[0];
+ unsigned int mask[2] = {0}, val[2] = {0};
+ int rc = 0, uV = min_uV;
+ int lim_min_uV, lim_max_uV, i;
- if (smps_is_enabled(dev))
- rc = _smps_set_voltage(dev, min_uV);
- if (rc)
- return rc;
+ /* Check if request voltage is outside of physically settable range. */
+ lim_min_uV = vreg->set_points->range[0].min_uV;
+ lim_max_uV =
+ vreg->set_points->range[vreg->set_points->count - 1].max_uV;
- /* only save if nonzero (or not disabling) */
- if (min_uV && (!vreg->pdata->sleep_selectable || !smps_is_enabled(dev)))
- vreg->save_uV = min_uV;
+ if (uV < lim_min_uV && max_uV >= lim_min_uV)
+ uV = lim_min_uV;
- return rc;
-}
-
-static int smps_get_voltage(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- return vreg->save_uV;
-}
-
-static int smps_enable(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- int rc = 0;
- unsigned mask, val;
-
- /* enable by setting voltage */
- if (MICRO_TO_MILLI(vreg->save_uV) > 0) {
- /* reenable pin control if it is in use */
- if (smps_get_mode(dev) == REGULATOR_MODE_IDLE) {
- mask = SMPS_PIN_CTRL | SMPS_PIN_FN;
- val = vreg->pdata->pin_ctrl << SMPS_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << SMPS_PIN_FN_SHIFT;
- vreg_store(vreg, mask, val, 0, 0);
- }
-
- rc = _smps_set_voltage(dev, vreg->save_uV);
- }
- return rc;
-}
-
-static int smps_disable(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned mask, val;
-
- /* turn off pin control */
- mask = SMPS_PIN_CTRL | SMPS_PIN_FN;
- val = RPM_VREG_PIN_CTRL_NONE << SMPS_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << SMPS_PIN_FN_SHIFT;
- vreg_store(vreg, mask, val, 0, 0);
-
- /* disable by setting voltage to zero */
- return _smps_set_voltage(dev, 0);
-}
-
-/*
- * Optimum mode programming:
- * REGULATOR_MODE_FAST: Go to HPM (highest priority)
- * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl
- * votes, else go to LPM
- *
- * Pin ctrl mode voting via regulator set_mode:
- * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
- * go to HPM
- * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
- *
- * Pin ctrl mode takes priority on the RPM when force mode is not set;
- * therefore, pin ctrl bits must be cleared if LPM or HPM is being voted for.
- */
-static int smps_set_mode(struct regulator_dev *dev, unsigned int mode)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned optimum = vreg->optimum;
- unsigned pc_vote = vreg->pc_vote;
- unsigned mode_initialized = vreg->mode_initialized;
- unsigned mask0 = 0, val0 = 0, mask1 = 0, val1 = 0;
- int set_hpm = -1, set_pin_control = -1;
- int peak_uA;
- int rc = 0;
-
- peak_uA = MILLI_TO_MICRO((vreg->req[0].value & SMPS_PEAK_CURRENT) >>
- SMPS_PEAK_CURRENT_SHIFT);
-
- switch (mode) {
- case REGULATOR_MODE_FAST:
- set_hpm = 1;
- set_pin_control = 0;
- optimum = REGULATOR_MODE_FAST;
- mode_initialized = 1;
- break;
-
- case REGULATOR_MODE_STANDBY:
- set_hpm = 0;
- if (pc_vote)
- set_pin_control = 1;
- else
- set_pin_control = 0;
- optimum = REGULATOR_MODE_STANDBY;
- mode_initialized = 1;
- break;
-
- case REGULATOR_MODE_IDLE:
- if (pc_vote++)
- goto done; /* already taken care of */
-
- if (mode_initialized && optimum == REGULATOR_MODE_FAST) {
- set_hpm = 1;
- set_pin_control = 0;
- } else {
- set_pin_control = 1;
- }
- break;
-
- case REGULATOR_MODE_NORMAL:
- if (pc_vote && --pc_vote)
- goto done; /* already taken care of */
-
- if (optimum == REGULATOR_MODE_STANDBY)
- set_hpm = 0;
- else
- set_hpm = 1;
- set_pin_control = 0;
- break;
-
- default:
+ if (uV < lim_min_uV || uV > lim_max_uV) {
+ vreg_err(vreg,
+ "request v=[%d, %d] is outside possible v=[%d, %d]\n",
+ min_uV, max_uV, lim_min_uV, lim_max_uV);
return -EINVAL;
}
- if (set_hpm == 1) {
- /* Make sure that request currents are at HPM level. */
- if (peak_uA < vreg_hpm_min_uA(vreg)) {
- mask0 = SMPS_PEAK_CURRENT;
- mask1 = SMPS_AVG_CURRENT;
- val0 = (MICRO_TO_MILLI(vreg_hpm_min_uA(vreg)) <<
- SMPS_PEAK_CURRENT_SHIFT) & SMPS_PEAK_CURRENT;
- val1 = (MICRO_TO_MILLI(vreg_hpm_min_uA(vreg)) <<
- SMPS_AVG_CURRENT_SHIFT) & SMPS_AVG_CURRENT;
- }
- } else if (set_hpm == 0) {
- /* Make sure that request currents are at LPM level. */
- if (peak_uA > vreg_lpm_max_uA(vreg)) {
- mask0 = SMPS_PEAK_CURRENT;
- mask1 = SMPS_AVG_CURRENT;
- val0 = (MICRO_TO_MILLI(vreg_lpm_max_uA(vreg)) <<
- SMPS_PEAK_CURRENT_SHIFT) & SMPS_PEAK_CURRENT;
- val1 = (MICRO_TO_MILLI(vreg_lpm_max_uA(vreg)) <<
- SMPS_AVG_CURRENT_SHIFT) & SMPS_AVG_CURRENT;
+ /* Find the range which uV is inside of. */
+ for (i = vreg->set_points->count - 1; i > 0; i--) {
+ if (uV > vreg->set_points->range[i - 1].max_uV) {
+ range = &vreg->set_points->range[i];
+ break;
}
}
- if (set_pin_control == 1) {
- /* Enable pin control and pin function. */
- mask0 |= SMPS_PIN_CTRL | SMPS_PIN_FN;
- val0 |= vreg->pdata->pin_ctrl << SMPS_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << SMPS_PIN_FN_SHIFT;
- } else if (set_pin_control == 0) {
- /* Clear pin control and pin function*/
- mask0 |= SMPS_PIN_CTRL | SMPS_PIN_FN;
- val0 |= RPM_VREG_PIN_CTRL_NONE << SMPS_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << SMPS_PIN_FN_SHIFT;
- }
+ /*
+ * Force uV to be an allowed set point and apply a ceiling function
+ * to non-set point values.
+ */
+ uV = (uV - range->min_uV + range->step_uV - 1) / range->step_uV;
+ uV = uV * range->step_uV + range->min_uV;
- if (smps_is_enabled(dev)) {
- rc = vreg_set(vreg, mask0, val0, mask1, val1, 2);
+ if (vreg->part->uV.mask) {
+ val[vreg->part->uV.word] = uV << vreg->part->uV.shift;
+ mask[vreg->part->uV.word] = vreg->part->uV.mask;
} else {
+ val[vreg->part->mV.word]
+ = MICRO_TO_MILLI(uV) << vreg->part->mV.shift;
+ mask[vreg->part->mV.word] = vreg->part->mV.mask;
+ }
+
+ mutex_lock(&vreg->pc_lock);
+
+ /*
+ * Only send a request for a new voltage if the regulator is currently
+ * enabled. This will ensure that LDO and SMPS regulators are not
+ * inadvertently turned on because voltage > 0 is equivalent to
+ * enabling. For NCP, this just removes unnecessary RPM requests.
+ */
+ if (vreg->is_enabled) {
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
+ if (rc)
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
+ } else if (vreg->type == RPM_REGULATOR_TYPE_NCP) {
/* Regulator is disabled; store but don't send new request. */
- rc = vreg_store(vreg, mask0, val0, mask1, val1);
- }
- if (rc)
- return rc;
-
-done:
- vreg->mode_initialized = mode_initialized;
- vreg->optimum = optimum;
- vreg->pc_vote = pc_vote;
-
- return 0;
-}
-
-static unsigned int smps_get_mode(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
-
- if ((vreg->optimum == REGULATOR_MODE_FAST) && vreg->mode_initialized)
- return REGULATOR_MODE_FAST;
- else if (vreg->pc_vote)
- return REGULATOR_MODE_IDLE;
- else if (vreg->optimum == REGULATOR_MODE_STANDBY)
- return REGULATOR_MODE_STANDBY;
- return REGULATOR_MODE_FAST;
-}
-
-unsigned int smps_get_optimum_mode(struct regulator_dev *dev, int input_uV,
- int output_uV, int load_uA)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
-
- if (MICRO_TO_MILLI(load_uA) > 0) {
- vreg->req[0].value &= ~SMPS_PEAK_CURRENT;
- vreg->req[0].value |= (MICRO_TO_MILLI(saturate_load(load_uA)) <<
- SMPS_PEAK_CURRENT_SHIFT) & SMPS_PEAK_CURRENT;
- vreg->req[1].value &= ~SMPS_AVG_CURRENT;
- vreg->req[1].value |= (MICRO_TO_MILLI(saturate_load(load_uA)) <<
- SMPS_AVG_CURRENT_SHIFT) & SMPS_AVG_CURRENT;
- } else {
- /*
- * smps_get_optimum_mode is being called before consumers have
- * specified their load currents via regulator_set_optimum_mode.
- * Return whatever the existing mode is.
- */
- return smps_get_mode(dev);
+ rc = vreg_store(vreg, mask[0], val[0], mask[1], val[1]);
}
- if (load_uA >= vreg->hpm_min_load)
- return REGULATOR_MODE_FAST;
- return REGULATOR_MODE_STANDBY;
-}
+ if (!rc && (!vreg->pdata.sleep_selectable || !vreg->is_enabled))
+ vreg->save_uV = uV;
-static int ldo_is_enabled(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- return ((vreg->req[0].value & LDO_VOLTAGE) >> LDO_VOLTAGE_SHIFT) != 0;
-}
-
-static int _ldo_set_voltage(struct regulator_dev *dev, int min_uV)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
-
- return vreg_set(vreg, LDO_VOLTAGE,
- MICRO_TO_MILLI(min_uV) << LDO_VOLTAGE_SHIFT,
- 0, 0, 2);
-}
-
-static int ldo_set_voltage(struct regulator_dev *dev, int min_uV, int max_uV,
- unsigned *selector)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- int rc = 0;
-
- if (ldo_is_enabled(dev))
- rc = _ldo_set_voltage(dev, min_uV);
- if (rc)
- return rc;
-
- /* only save if nonzero (or not disabling) */
- if (min_uV && (!vreg->pdata->sleep_selectable || !ldo_is_enabled(dev)))
- vreg->save_uV = min_uV;
+ mutex_unlock(&vreg->pc_lock);
return rc;
}
-static int ldo_get_voltage(struct regulator_dev *dev)
+static int vreg_get_voltage(struct regulator_dev *rdev)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+
return vreg->save_uV;
}
-static int ldo_enable(struct regulator_dev *dev)
+static int vreg_list_voltage(struct regulator_dev *rdev, unsigned selector)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- int rc = 0;
- unsigned mask, val;
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ int uV = 0;
+ int i;
- /* enable by setting voltage */
- if (MICRO_TO_MILLI(vreg->save_uV) > 0) {
- /* reenable pin control if it is in use */
- if (ldo_get_mode(dev) == REGULATOR_MODE_IDLE) {
- mask = LDO_PIN_CTRL | LDO_PIN_FN;
- val = vreg->pdata->pin_ctrl << LDO_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << LDO_PIN_FN_SHIFT;
- vreg_store(vreg, mask, val, 0, 0);
- }
-
- rc = _ldo_set_voltage(dev, vreg->save_uV);
- }
- return rc;
-}
-
-static int ldo_disable(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned mask, val;
-
- /* turn off pin control */
- mask = LDO_PIN_CTRL | LDO_PIN_FN;
- val = RPM_VREG_PIN_CTRL_NONE << LDO_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << LDO_PIN_FN_SHIFT;
- vreg_store(vreg, mask, val, 0, 0);
-
- /* disable by setting voltage to zero */
- return _ldo_set_voltage(dev, 0);
-}
-
-/*
- * Optimum mode programming:
- * REGULATOR_MODE_FAST: Go to HPM (highest priority)
- * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl
- * votes, else go to LPM
- *
- * Pin ctrl mode voting via regulator set_mode:
- * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
- * go to HPM
- * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
- *
- * Pin ctrl mode takes priority on the RPM when force mode is not set;
- * therefore, pin ctrl bits must be cleared if LPM or HPM is being voted for.
- */
-static int ldo_set_mode(struct regulator_dev *dev, unsigned int mode)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned optimum = vreg->optimum;
- unsigned pc_vote = vreg->pc_vote;
- unsigned mode_initialized = vreg->mode_initialized;
- unsigned mask0 = 0, val0 = 0, mask1 = 0, val1 = 0;
- int set_hpm = -1, set_pin_control = -1;
- int peak_uA;
- int rc = 0;
-
- peak_uA = MILLI_TO_MICRO((vreg->req[0].value & LDO_PEAK_CURRENT) >>
- LDO_PEAK_CURRENT_SHIFT);
-
- switch (mode) {
- case REGULATOR_MODE_FAST:
- set_hpm = 1;
- set_pin_control = 0;
- optimum = REGULATOR_MODE_FAST;
- mode_initialized = 1;
- break;
-
- case REGULATOR_MODE_STANDBY:
- set_hpm = 0;
- if (pc_vote)
- set_pin_control = 1;
- else
- set_pin_control = 0;
- optimum = REGULATOR_MODE_STANDBY;
- mode_initialized = 1;
- break;
-
- case REGULATOR_MODE_IDLE:
- if (pc_vote++)
- goto done; /* already taken care of */
-
- if (mode_initialized && optimum == REGULATOR_MODE_FAST) {
- set_hpm = 1;
- set_pin_control = 0;
- } else {
- set_pin_control = 1;
- }
- break;
-
- case REGULATOR_MODE_NORMAL:
- if (pc_vote && --pc_vote)
- goto done; /* already taken care of */
-
- if (optimum == REGULATOR_MODE_STANDBY)
- set_hpm = 0;
- else
- set_hpm = 1;
- set_pin_control = 0;
- break;
-
- default:
+ if (!vreg->set_points) {
+ vreg_err(vreg, "no voltages available\n");
return -EINVAL;
}
- if (set_hpm == 1) {
- /* Make sure that request currents are at HPM level. */
+ if (selector >= vreg->set_points->n_voltages)
+ return 0;
+
+ for (i = 0; i < vreg->set_points->count; i++) {
+ if (selector < vreg->set_points->range[i].n_voltages) {
+ uV = selector * vreg->set_points->range[i].step_uV
+ + vreg->set_points->range[i].min_uV;
+ break;
+ } else {
+ selector -= vreg->set_points->range[i].n_voltages;
+ }
+ }
+
+ return uV;
+}
+
+static int vreg_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mask[2] = {0}, val[2] = {0};
+ int rc = 0;
+ int peak_uA;
+
+ mutex_lock(&vreg->pc_lock);
+
+ peak_uA = MILLI_TO_MICRO((vreg->req[vreg->part->ip.word].value
+ & vreg->part->ip.mask) >> vreg->part->ip.shift);
+
+ if (mode == config->mode_hpm) {
+ /* Make sure that request currents are in HPM range. */
if (peak_uA < vreg_hpm_min_uA(vreg)) {
- mask0 = LDO_PEAK_CURRENT;
- mask1 = LDO_AVG_CURRENT;
- val0 = (MICRO_TO_MILLI(vreg_hpm_min_uA(vreg)) <<
- LDO_PEAK_CURRENT_SHIFT) & LDO_PEAK_CURRENT;
- val1 = (MICRO_TO_MILLI(vreg_hpm_min_uA(vreg)) <<
- LDO_AVG_CURRENT_SHIFT) & LDO_AVG_CURRENT;
+ val[vreg->part->ip.word]
+ = MICRO_TO_MILLI(vreg_hpm_min_uA(vreg))
+ << vreg->part->ip.shift;
+ mask[vreg->part->ip.word] = vreg->part->ip.mask;
+
+ if (config->ia_follows_ip) {
+ val[vreg->part->ia.word]
+ |= MICRO_TO_MILLI(vreg_hpm_min_uA(vreg))
+ << vreg->part->ia.shift;
+ mask[vreg->part->ia.word]
+ |= vreg->part->ia.mask;
+ }
}
- } else if (set_hpm == 0) {
- /* Make sure that request currents are at LPM level. */
+ } else if (mode == config->mode_lpm) {
+ /* Make sure that request currents are in LPM range. */
if (peak_uA > vreg_lpm_max_uA(vreg)) {
- mask0 = LDO_PEAK_CURRENT;
- mask1 = LDO_AVG_CURRENT;
- val0 = (MICRO_TO_MILLI(vreg_lpm_max_uA(vreg)) <<
- LDO_PEAK_CURRENT_SHIFT) & LDO_PEAK_CURRENT;
- val1 = (MICRO_TO_MILLI(vreg_lpm_max_uA(vreg)) <<
- LDO_AVG_CURRENT_SHIFT) & LDO_AVG_CURRENT;
+ val[vreg->part->ip.word]
+ = MICRO_TO_MILLI(vreg_lpm_max_uA(vreg))
+ << vreg->part->ip.shift;
+ mask[vreg->part->ip.word] = vreg->part->ip.mask;
+
+ if (config->ia_follows_ip) {
+ val[vreg->part->ia.word]
+ |= MICRO_TO_MILLI(vreg_lpm_max_uA(vreg))
+ << vreg->part->ia.shift;
+ mask[vreg->part->ia.word]
+ |= vreg->part->ia.mask;
+ }
}
+ } else {
+ vreg_err(vreg, "invalid mode: %u\n", mode);
+ mutex_unlock(&vreg->pc_lock);
+ return -EINVAL;
}
- if (set_pin_control == 1) {
- /* Enable pin control and pin function. */
- mask0 |= LDO_PIN_CTRL | LDO_PIN_FN;
- val0 |= vreg->pdata->pin_ctrl << LDO_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << LDO_PIN_FN_SHIFT;
- } else if (set_pin_control == 0) {
- /* Clear pin control and pin function*/
- mask0 |= LDO_PIN_CTRL | LDO_PIN_FN;
- val0 |= RPM_VREG_PIN_CTRL_NONE << LDO_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << LDO_PIN_FN_SHIFT;
- }
-
- if (ldo_is_enabled(dev)) {
- rc = vreg_set(vreg, mask0, val0, mask1, val1, 2);
+ if (vreg->is_enabled) {
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
} else {
/* Regulator is disabled; store but don't send new request. */
- rc = vreg_store(vreg, mask0, val0, mask1, val1);
+ rc = vreg_store(vreg, mask[0], val[0], mask[1], val[1]);
}
+
if (rc)
- return rc;
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
+ else
+ vreg->mode = mode;
-done:
- vreg->mode_initialized = mode_initialized;
- vreg->optimum = optimum;
- vreg->pc_vote = pc_vote;
+ mutex_unlock(&vreg->pc_lock);
- return 0;
+ return rc;
}
-static unsigned int ldo_get_mode(struct regulator_dev *dev)
+static unsigned int vreg_get_mode(struct regulator_dev *rdev)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
+ struct vreg *vreg = rdev_get_drvdata(rdev);
- if ((vreg->optimum == REGULATOR_MODE_FAST) && vreg->mode_initialized)
- return REGULATOR_MODE_FAST;
- else if (vreg->pc_vote)
- return REGULATOR_MODE_IDLE;
- else if (vreg->optimum == REGULATOR_MODE_STANDBY)
- return REGULATOR_MODE_STANDBY;
- return REGULATOR_MODE_FAST;
+ return vreg->mode;
}
-unsigned int ldo_get_optimum_mode(struct regulator_dev *dev, int input_uV,
- int output_uV, int load_uA)
+static unsigned int vreg_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mode;
- if (MICRO_TO_MILLI(load_uA) > 0) {
- vreg->req[0].value &= ~LDO_PEAK_CURRENT;
- vreg->req[0].value |= (MICRO_TO_MILLI(saturate_load(load_uA)) <<
- LDO_PEAK_CURRENT_SHIFT) & LDO_PEAK_CURRENT;
- vreg->req[1].value &= ~LDO_AVG_CURRENT;
- vreg->req[1].value |= (MICRO_TO_MILLI(saturate_load(load_uA)) <<
- LDO_AVG_CURRENT_SHIFT) & LDO_AVG_CURRENT;
- } else {
- /*
- * ldo_get_optimum_mode is being called before consumers have
- * specified their load currents via regulator_set_optimum_mode.
- * Return whatever the existing mode is.
- */
- return ldo_get_mode(dev);
- }
+ load_uA += vreg->pdata.system_uA;
+
+ mutex_lock(&vreg->pc_lock);
+ SET_PART(vreg, ip, MICRO_TO_MILLI(saturate_peak_load(vreg, load_uA)));
+ if (config->ia_follows_ip)
+ SET_PART(vreg, ia,
+ MICRO_TO_MILLI(saturate_avg_load(vreg, load_uA)));
+ mutex_unlock(&vreg->pc_lock);
if (load_uA >= vreg->hpm_min_load)
- return REGULATOR_MODE_FAST;
- return REGULATOR_MODE_STANDBY;
+ mode = config->mode_hpm;
+ else
+ mode = config->mode_lpm;
+
+ return mode;
}
-static int switch_enable(struct regulator_dev *dev)
+static unsigned int vreg_legacy_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned mask = 0, val = 0;
+ struct vreg *vreg = rdev_get_drvdata(rdev);
- /* reenable pin control if it is in use */
- if (switch_get_mode(dev) == REGULATOR_MODE_IDLE) {
- mask = SWITCH_PIN_CTRL | SWITCH_PIN_FN;
- val = vreg->pdata->pin_ctrl << SWITCH_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << SWITCH_PIN_FN_SHIFT;
+ if (MICRO_TO_MILLI(load_uA) <= 0) {
+ /*
+ * vreg_legacy_get_optimum_mode is being called before consumers
+ * have specified their load currents via
+ * regulator_set_optimum_mode. Return whatever the existing mode
+ * is.
+ */
+ return vreg->mode;
}
- return vreg_set(rdev_get_drvdata(dev), SWITCH_STATE | mask,
- (RPM_VREG_STATE_ON << SWITCH_STATE_SHIFT) | val, 0, 0, 1);
-}
-
-static int switch_disable(struct regulator_dev *dev)
-{
- unsigned mask, val;
-
- /* turn off pin control */
- mask = SWITCH_PIN_CTRL | SWITCH_PIN_FN;
- val = RPM_VREG_PIN_CTRL_NONE << SWITCH_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << SWITCH_PIN_FN_SHIFT;
-
- return vreg_set(rdev_get_drvdata(dev), SWITCH_STATE | mask,
- (RPM_VREG_STATE_OFF << SWITCH_STATE_SHIFT) | val, 0, 0, 1);
-}
-
-static int switch_is_enabled(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- enum rpm_vreg_state state;
-
- state = (vreg->req[0].value & SWITCH_STATE) >> SWITCH_STATE_SHIFT;
-
- return state == RPM_VREG_STATE_ON;
+ return vreg_get_optimum_mode(rdev, input_uV, output_uV, load_uA);
}
/*
- * Pin ctrl mode voting via regulator set_mode:
- * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
- * go to HPM
- * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
+ * Returns the logical pin control enable state because the pin control options
+ * present in the hardware out of restart could be different from those desired
+ * by the consumer.
*/
-static int switch_set_mode(struct regulator_dev *dev, unsigned int mode)
+static int vreg_pin_control_is_enabled(struct regulator_dev *rdev)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
- unsigned pc_vote = vreg->pc_vote;
- unsigned mask, val;
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+
+ return vreg->is_enabled_pc;
+}
+
+static int vreg_pin_control_enable(struct regulator_dev *rdev)
+{
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mask[2] = {0}, val[2] = {0};
int rc;
- switch (mode) {
- case REGULATOR_MODE_IDLE:
- if (pc_vote++)
- goto done; /* already taken care of */
+ mutex_lock(&vreg->pc_lock);
- mask = SWITCH_PIN_CTRL | SWITCH_PIN_FN;
- val = vreg->pdata->pin_ctrl << SWITCH_PIN_CTRL_SHIFT
- | vreg->pdata->pin_fn << SWITCH_PIN_FN_SHIFT;
- break;
+ val[vreg->part->pc.word]
+ |= vreg->pdata.pin_ctrl << vreg->part->pc.shift;
+ mask[vreg->part->pc.word] |= vreg->part->pc.mask;
- case REGULATOR_MODE_NORMAL:
- if (--pc_vote)
- goto done; /* already taken care of */
+ val[vreg->part->pf.word] |= vreg->pdata.pin_fn << vreg->part->pf.shift;
+ mask[vreg->part->pf.word] |= vreg->part->pf.mask;
- mask = SWITCH_PIN_CTRL | SWITCH_PIN_FN;
- val = RPM_VREG_PIN_CTRL_NONE << SWITCH_PIN_CTRL_SHIFT
- | RPM_VREG_PIN_FN_NONE << SWITCH_PIN_FN_SHIFT;
- break;
+ if (!vreg->is_enabled)
+ set_enable(vreg, mask, val);
- default:
- return -EINVAL;
- }
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
- if (switch_is_enabled(dev)) {
- rc = vreg_set(vreg, mask, val, 0, 0, 2);
- } else {
- /* Regulator is disabled; store but don't send new request. */
- rc = vreg_store(vreg, mask, val, 0, 0);
- }
+ if (!rc)
+ vreg->is_enabled_pc = true;
+
+ mutex_unlock(&vreg->pc_lock);
+
if (rc)
- return rc;
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
-done:
- vreg->pc_vote = pc_vote;
- return 0;
+ return rc;
}
-static unsigned int switch_get_mode(struct regulator_dev *dev)
+static int vreg_pin_control_disable(struct regulator_dev *rdev)
{
- struct vreg *vreg = rdev_get_drvdata(dev);
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+ unsigned int mask[2] = {0}, val[2] = {0};
+ int pin_fn, rc;
- if (vreg->pc_vote)
- return REGULATOR_MODE_IDLE;
- return REGULATOR_MODE_NORMAL;
+ mutex_lock(&vreg->pc_lock);
+
+ val[vreg->part->pc.word]
+ |= RPM_VREG_PIN_CTRL_NONE << vreg->part->pc.shift;
+ mask[vreg->part->pc.word] |= vreg->part->pc.mask;
+
+ pin_fn = config->pin_func_none;
+ if (vreg->pdata.pin_fn == config->pin_func_sleep_b)
+ pin_fn = config->pin_func_sleep_b;
+ val[vreg->part->pf.word] |= pin_fn << vreg->part->pf.shift;
+ mask[vreg->part->pf.word] |= vreg->part->pf.mask;
+
+ if (!vreg->is_enabled)
+ set_disable(vreg, mask, val);
+
+ rc = vreg_set(vreg, mask[0], val[0], mask[1], val[1],
+ vreg->part->request_len);
+
+ if (!rc)
+ vreg->is_enabled_pc = false;
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ vreg_err(vreg, "vreg_set failed, rc=%d\n", rc);
+
+ return rc;
}
-static int ncp_enable(struct regulator_dev *dev)
+static int vreg_enable_time(struct regulator_dev *rdev)
{
- return vreg_set(rdev_get_drvdata(dev), NCP_STATE,
- RPM_VREG_STATE_ON << NCP_STATE_SHIFT, 0, 0, 2);
+ struct vreg *vreg = rdev_get_drvdata(rdev);
+
+ return vreg->pdata.enable_time;
}
-static int ncp_disable(struct regulator_dev *dev)
-{
- return vreg_set(rdev_get_drvdata(dev), NCP_STATE,
- RPM_VREG_STATE_OFF << NCP_STATE_SHIFT, 0, 0, 2);
-}
-
-static int ncp_is_enabled(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
- enum rpm_vreg_state state;
-
- state = (vreg->req[0].value & NCP_STATE) >> NCP_STATE_SHIFT;
-
- return state == RPM_VREG_STATE_ON;
-}
-
-static int ncp_set_voltage(struct regulator_dev *dev, int min_uV, int max_uV,
- unsigned *selector)
-{
- return vreg_set(rdev_get_drvdata(dev), NCP_VOLTAGE,
- MICRO_TO_MILLI(min_uV) << NCP_VOLTAGE_SHIFT, 0, 0, 2);
-}
-
-static int ncp_get_voltage(struct regulator_dev *dev)
-{
- struct vreg *vreg = rdev_get_drvdata(dev);
-
- return MILLI_TO_MICRO((vreg->req[0].value & NCP_VOLTAGE) >>
- NCP_VOLTAGE_SHIFT);
-}
-
+/* Real regulator operations. */
static struct regulator_ops ldo_ops = {
- .enable = ldo_enable,
- .disable = ldo_disable,
- .is_enabled = ldo_is_enabled,
- .set_voltage = ldo_set_voltage,
- .get_voltage = ldo_get_voltage,
- .set_mode = ldo_set_mode,
- .get_optimum_mode = ldo_get_optimum_mode,
- .get_mode = ldo_get_mode,
+ .enable = vreg_enable,
+ .disable = vreg_disable,
+ .is_enabled = vreg_is_enabled,
+ .set_voltage = vreg_set_voltage,
+ .get_voltage = vreg_get_voltage,
+ .list_voltage = vreg_list_voltage,
+ .set_mode = vreg_set_mode,
+ .get_mode = vreg_get_mode,
+ .get_optimum_mode = vreg_get_optimum_mode,
+ .enable_time = vreg_enable_time,
};
static struct regulator_ops smps_ops = {
- .enable = smps_enable,
- .disable = smps_disable,
- .is_enabled = smps_is_enabled,
- .set_voltage = smps_set_voltage,
- .get_voltage = smps_get_voltage,
- .set_mode = smps_set_mode,
- .get_optimum_mode = smps_get_optimum_mode,
- .get_mode = smps_get_mode,
+ .enable = vreg_enable,
+ .disable = vreg_disable,
+ .is_enabled = vreg_is_enabled,
+ .set_voltage = vreg_set_voltage,
+ .get_voltage = vreg_get_voltage,
+ .list_voltage = vreg_list_voltage,
+ .set_mode = vreg_set_mode,
+ .get_mode = vreg_get_mode,
+ .get_optimum_mode = vreg_get_optimum_mode,
+ .enable_time = vreg_enable_time,
};
static struct regulator_ops switch_ops = {
- .enable = switch_enable,
- .disable = switch_disable,
- .is_enabled = switch_is_enabled,
- .set_mode = switch_set_mode,
- .get_mode = switch_get_mode,
+ .enable = vreg_enable,
+ .disable = vreg_disable,
+ .is_enabled = vreg_is_enabled,
+ .enable_time = vreg_enable_time,
};
static struct regulator_ops ncp_ops = {
- .enable = ncp_enable,
- .disable = ncp_disable,
- .is_enabled = ncp_is_enabled,
- .set_voltage = ncp_set_voltage,
- .get_voltage = ncp_get_voltage,
+ .enable = vreg_enable,
+ .disable = vreg_disable,
+ .is_enabled = vreg_is_enabled,
+ .set_voltage = vreg_set_voltage,
+ .get_voltage = vreg_get_voltage,
+ .list_voltage = vreg_list_voltage,
+ .enable_time = vreg_enable_time,
};
-#define DESC(_id, _name, _ops) \
- [_id] = { \
- .id = _id, \
- .name = _name, \
- .ops = _ops, \
- .type = REGULATOR_VOLTAGE, \
- .owner = THIS_MODULE, \
+/* Pin control regulator operations. */
+static struct regulator_ops pin_control_ops = {
+ .enable = vreg_pin_control_enable,
+ .disable = vreg_pin_control_disable,
+ .is_enabled = vreg_pin_control_is_enabled,
+};
+
+struct regulator_ops *vreg_ops[] = {
+ [RPM_REGULATOR_TYPE_LDO] = &ldo_ops,
+ [RPM_REGULATOR_TYPE_SMPS] = &smps_ops,
+ [RPM_REGULATOR_TYPE_VS] = &switch_ops,
+ [RPM_REGULATOR_TYPE_NCP] = &ncp_ops,
+};
+
+static int __devinit
+rpm_vreg_init_regulator(const struct rpm_regulator_init_data *pdata,
+ struct device *dev)
+{
+ struct regulator_desc *rdesc = NULL;
+ struct regulator_dev *rdev;
+ struct vreg *vreg;
+ unsigned pin_ctrl;
+ int id, pin_fn;
+ int rc = 0;
+
+ if (!pdata) {
+ pr_err("platform data missing\n");
+ return -EINVAL;
}
-static struct regulator_desc vreg_descrip[RPM_VREG_ID_MAX] = {
- DESC(RPM_VREG_ID_PM8058_L0, "8058_l0", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L1, "8058_l1", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L2, "8058_l2", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L3, "8058_l3", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L4, "8058_l4", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L5, "8058_l5", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L6, "8058_l6", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L7, "8058_l7", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L8, "8058_l8", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L9, "8058_l9", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L10, "8058_l10", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L11, "8058_l11", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L12, "8058_l12", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L13, "8058_l13", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L14, "8058_l14", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L15, "8058_l15", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L16, "8058_l16", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L17, "8058_l17", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L18, "8058_l18", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L19, "8058_l19", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L20, "8058_l20", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L21, "8058_l21", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L22, "8058_l22", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L23, "8058_l23", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L24, "8058_l24", &ldo_ops),
- DESC(RPM_VREG_ID_PM8058_L25, "8058_l25", &ldo_ops),
+ id = pdata->id;
- DESC(RPM_VREG_ID_PM8058_S0, "8058_s0", &smps_ops),
- DESC(RPM_VREG_ID_PM8058_S1, "8058_s1", &smps_ops),
- DESC(RPM_VREG_ID_PM8058_S2, "8058_s2", &smps_ops),
- DESC(RPM_VREG_ID_PM8058_S3, "8058_s3", &smps_ops),
- DESC(RPM_VREG_ID_PM8058_S4, "8058_s4", &smps_ops),
+ if (id < config->vreg_id_min || id > config->vreg_id_max) {
+ pr_err("invalid regulator id: %d\n", id);
+ return -ENODEV;
+ }
- DESC(RPM_VREG_ID_PM8058_LVS0, "8058_lvs0", &switch_ops),
- DESC(RPM_VREG_ID_PM8058_LVS1, "8058_lvs1", &switch_ops),
+ if (!config->is_real_id(pdata->id))
+ id = config->pc_id_to_real_id(pdata->id);
+ vreg = &config->vregs[id];
- DESC(RPM_VREG_ID_PM8058_NCP, "8058_ncp", &ncp_ops),
-
- DESC(RPM_VREG_ID_PM8901_L0, "8901_l0", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L1, "8901_l1", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L2, "8901_l2", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L3, "8901_l3", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L4, "8901_l4", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L5, "8901_l5", &ldo_ops),
- DESC(RPM_VREG_ID_PM8901_L6, "8901_l6", &ldo_ops),
-
- DESC(RPM_VREG_ID_PM8901_S0, "8901_s0", &smps_ops),
- DESC(RPM_VREG_ID_PM8901_S1, "8901_s1", &smps_ops),
- DESC(RPM_VREG_ID_PM8901_S2, "8901_s2", &smps_ops),
- DESC(RPM_VREG_ID_PM8901_S3, "8901_s3", &smps_ops),
- DESC(RPM_VREG_ID_PM8901_S4, "8901_s4", &smps_ops),
-
- DESC(RPM_VREG_ID_PM8901_LVS0, "8901_lvs0", &switch_ops),
- DESC(RPM_VREG_ID_PM8901_LVS1, "8901_lvs1", &switch_ops),
- DESC(RPM_VREG_ID_PM8901_LVS2, "8901_lvs2", &switch_ops),
- DESC(RPM_VREG_ID_PM8901_LVS3, "8901_lvs3", &switch_ops),
-
- DESC(RPM_VREG_ID_PM8901_MVS0, "8901_mvs0", &switch_ops),
-};
-
-static void ldo_init(struct vreg *vreg)
-{
- enum rpm_vreg_pin_fn pf = RPM_VREG_PIN_FN_NONE;
-
- /* Allow pf=sleep_b to be specified by platform data. */
- if (vreg->pdata->pin_fn == RPM_VREG_PIN_FN_SLEEP_B)
- pf = RPM_VREG_PIN_FN_SLEEP_B;
-
- vreg->req[0].value =
- MICRO_TO_MILLI(saturate_load(vreg->pdata->peak_uA)) <<
- LDO_PEAK_CURRENT_SHIFT |
- vreg->pdata->mode << LDO_MODE_SHIFT | pf << LDO_PIN_FN_SHIFT |
- RPM_VREG_PIN_CTRL_NONE << LDO_PIN_CTRL_SHIFT;
-
- vreg->req[1].value =
- vreg->pdata->pull_down_enable << LDO_PULL_DOWN_ENABLE_SHIFT |
- MICRO_TO_MILLI(saturate_load(vreg->pdata->avg_uA)) <<
- LDO_AVG_CURRENT_SHIFT;
-}
-
-static void smps_init(struct vreg *vreg)
-{
- enum rpm_vreg_pin_fn pf = RPM_VREG_PIN_FN_NONE;
-
- /* Allow pf=sleep_b to be specified by platform data. */
- if (vreg->pdata->pin_fn == RPM_VREG_PIN_FN_SLEEP_B)
- pf = RPM_VREG_PIN_FN_SLEEP_B;
-
- vreg->req[0].value =
- MICRO_TO_MILLI(saturate_load(vreg->pdata->peak_uA)) <<
- SMPS_PEAK_CURRENT_SHIFT |
- vreg->pdata->mode << SMPS_MODE_SHIFT | pf << SMPS_PIN_FN_SHIFT |
- RPM_VREG_PIN_CTRL_NONE << SMPS_PIN_CTRL_SHIFT;
-
-
- vreg->req[1].value =
- vreg->pdata->pull_down_enable << SMPS_PULL_DOWN_ENABLE_SHIFT |
- MICRO_TO_MILLI(saturate_load(vreg->pdata->avg_uA)) <<
- SMPS_AVG_CURRENT_SHIFT |
- vreg->pdata->freq << SMPS_FREQ_SHIFT |
- 0 << SMPS_CLK_SRC_SHIFT;
-}
-
-static void ncp_init(struct vreg *vreg)
-{
- vreg->req[0].value = vreg->pdata->state << NCP_STATE_SHIFT;
-}
-
-static void switch_init(struct vreg *vreg)
-{
- enum rpm_vreg_pin_fn pf = RPM_VREG_PIN_FN_NONE;
-
- /* Allow pf=sleep_b to be specified by platform data. */
- if (vreg->pdata->pin_fn == RPM_VREG_PIN_FN_SLEEP_B)
- pf = RPM_VREG_PIN_FN_SLEEP_B;
-
- vreg->req[0].value =
- vreg->pdata->state << SWITCH_STATE_SHIFT |
- vreg->pdata->pull_down_enable <<
- SWITCH_PULL_DOWN_ENABLE_SHIFT |
- pf << SWITCH_PIN_FN_SHIFT |
- RPM_VREG_PIN_CTRL_NONE << SWITCH_PIN_CTRL_SHIFT;
-}
-
-static int vreg_init(enum rpm_vreg_id id, struct vreg *vreg)
-{
- vreg->save_uV = vreg->pdata->default_uV;
-
- if (vreg->pdata->peak_uA >= vreg->hpm_min_load)
- vreg->optimum = REGULATOR_MODE_FAST;
+ if (config->is_real_id(pdata->id))
+ rdesc = &vreg->rdesc;
else
- vreg->optimum = REGULATOR_MODE_STANDBY;
+ rdesc = &vreg->rdesc_pc;
- vreg->mode_initialized = 0;
-
- if (IS_LDO(id))
- ldo_init(vreg);
- else if (IS_SMPS(id))
- smps_init(vreg);
- else if (IS_NCP(id))
- ncp_init(vreg);
- else if (IS_SWITCH(id))
- switch_init(vreg);
- else
+ if (vreg->type < 0 || vreg->type > RPM_REGULATOR_TYPE_MAX) {
+ pr_err("%s: invalid regulator type: %d\n",
+ vreg->rdesc.name, vreg->type);
return -EINVAL;
+ }
- return 0;
+ mutex_lock(&vreg->pc_lock);
+
+ if (vreg->set_points)
+ rdesc->n_voltages = vreg->set_points->n_voltages;
+ else
+ rdesc->n_voltages = 0;
+
+ rdesc->id = pdata->id;
+ rdesc->owner = THIS_MODULE;
+ rdesc->type = REGULATOR_VOLTAGE;
+
+ if (config->is_real_id(pdata->id)) {
+ /*
+ * Real regulator; do not modify pin control and pin function
+ * values.
+ */
+ rdesc->ops = vreg_ops[vreg->type];
+ pin_ctrl = vreg->pdata.pin_ctrl;
+ pin_fn = vreg->pdata.pin_fn;
+ memcpy(&(vreg->pdata), pdata,
+ sizeof(struct rpm_regulator_init_data));
+ vreg->pdata.pin_ctrl = pin_ctrl;
+ vreg->pdata.pin_fn = pin_fn;
+
+ vreg->save_uV = vreg->pdata.default_uV;
+ if (vreg->pdata.peak_uA >= vreg->hpm_min_load)
+ vreg->mode = config->mode_hpm;
+ else
+ vreg->mode = config->mode_lpm;
+
+ /* Initialize the RPM request. */
+ SET_PART(vreg, ip,
+ MICRO_TO_MILLI(saturate_peak_load(vreg, vreg->pdata.peak_uA)));
+ SET_PART(vreg, fm, vreg->pdata.force_mode);
+ SET_PART(vreg, pm, vreg->pdata.power_mode);
+ SET_PART(vreg, pd, vreg->pdata.pull_down_enable);
+ SET_PART(vreg, ia,
+ MICRO_TO_MILLI(saturate_avg_load(vreg, vreg->pdata.avg_uA)));
+ SET_PART(vreg, freq, vreg->pdata.freq);
+ SET_PART(vreg, freq_clk_src, 0);
+ SET_PART(vreg, comp_mode, 0);
+ SET_PART(vreg, hpm, 0);
+ if (!vreg->is_enabled_pc) {
+ SET_PART(vreg, pf, config->pin_func_none);
+ SET_PART(vreg, pc, RPM_VREG_PIN_CTRL_NONE);
+ }
+ } else {
+ if ((pdata->pin_ctrl & RPM_VREG_PIN_CTRL_ALL)
+ == RPM_VREG_PIN_CTRL_NONE
+ && pdata->pin_fn != config->pin_func_sleep_b) {
+ pr_err("%s: no pin control input specified\n",
+ vreg->rdesc.name);
+ mutex_unlock(&vreg->pc_lock);
+ return -EINVAL;
+ }
+ rdesc->ops = &pin_control_ops;
+ vreg->pdata.pin_ctrl = pdata->pin_ctrl;
+ vreg->pdata.pin_fn = pdata->pin_fn;
+
+ /* Initialize the RPM request. */
+ pin_fn = config->pin_func_none;
+ /* Allow pf=sleep_b to be specified by platform data. */
+ if (vreg->pdata.pin_fn == config->pin_func_sleep_b)
+ pin_fn = config->pin_func_sleep_b;
+ SET_PART(vreg, pf, pin_fn);
+ SET_PART(vreg, pc, RPM_VREG_PIN_CTRL_NONE);
+ }
+
+ mutex_unlock(&vreg->pc_lock);
+
+ if (rc)
+ goto bail;
+
+ rdev = regulator_register(rdesc, dev, &(pdata->init_data), vreg);
+ if (IS_ERR(rdev)) {
+ rc = PTR_ERR(rdev);
+ pr_err("regulator_register failed: %s, rc=%d\n",
+ vreg->rdesc.name, rc);
+ return rc;
+ } else {
+ if (config->is_real_id(pdata->id))
+ vreg->rdev = rdev;
+ else
+ vreg->rdev_pc = rdev;
+ }
+
+bail:
+ if (rc)
+ pr_err("error for %s, rc=%d\n", vreg->rdesc.name, rc);
+
+ return rc;
+}
+
+static void rpm_vreg_set_point_init(void)
+{
+ struct vreg_set_points **set_points;
+ int i, j, temp;
+
+ set_points = config->set_points;
+
+ /* Calculate the number of set points available for each regulator. */
+ for (i = 0; i < config->set_points_len; i++) {
+ temp = 0;
+ for (j = 0; j < set_points[i]->count; j++) {
+ set_points[i]->range[j].n_voltages
+ = (set_points[i]->range[j].max_uV
+ - set_points[i]->range[j].min_uV)
+ / set_points[i]->range[j].step_uV + 1;
+ temp += set_points[i]->range[j].n_voltages;
+ }
+ set_points[i]->n_voltages = temp;
+ }
}
static int __devinit rpm_vreg_probe(struct platform_device *pdev)
{
- struct regulator_desc *rdesc;
- struct regulator_dev *rdev;
- struct vreg *vreg;
- int rc;
+ struct rpm_regulator_platform_data *platform_data;
+ int rc = 0;
+ int i, id;
- if (pdev == NULL)
+ platform_data = pdev->dev.platform_data;
+ if (!platform_data) {
+ pr_err("rpm-regulator requires platform data\n");
return -EINVAL;
-
- if (pdev->id < 0 || pdev->id >= RPM_VREG_ID_MAX)
- return -ENODEV;
-
- vreg = &vregs[pdev->id];
- vreg->pdata = pdev->dev.platform_data;
- vreg->id = pdev->id;
- rdesc = &vreg_descrip[pdev->id];
-
- rc = vreg_init(pdev->id, vreg);
- if (rc) {
- pr_err("%s: vreg_init failed, rc=%d\n", __func__, rc);
- return rc;
}
- /* Disallow idle and normal modes if pin control isn't set. */
- if ((vreg->pdata->pin_ctrl == RPM_VREG_PIN_CTRL_NONE)
- && ((vreg->pdata->pin_fn == RPM_VREG_PIN_FN_ENABLE)
- || (vreg->pdata->pin_fn == RPM_VREG_PIN_FN_MODE)))
- vreg->pdata->init_data.constraints.valid_modes_mask
- &= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE);
-
- rdev = regulator_register(rdesc, &pdev->dev,
- &vreg->pdata->init_data, vreg);
- if (IS_ERR(rdev)) {
- rc = PTR_ERR(rdev);
- pr_err("%s: id=%d, rc=%d\n", __func__,
- pdev->id, rc);
- return rc;
+ if (rpm_version >= 0 && rpm_version <= RPM_VREG_VERSION_MAX
+ && platform_data->version != rpm_version) {
+ pr_err("rpm version %d does not match previous version %d\n",
+ platform_data->version, rpm_version);
+ return -EINVAL;
}
- platform_set_drvdata(pdev, rdev);
+ if (platform_data->version < 0
+ || platform_data->version > RPM_VREG_VERSION_MAX) {
+ pr_err("rpm version %d is invalid\n", platform_data->version);
+ return -EINVAL;
+ }
+
+ if (rpm_version < 0 || rpm_version > RPM_VREG_VERSION_MAX) {
+ rpm_version = platform_data->version;
+ config = get_config[platform_data->version]();
+ vreg_id_vdd_mem = platform_data->vreg_id_vdd_mem;
+ vreg_id_vdd_dig = platform_data->vreg_id_vdd_dig;
+ if (!config) {
+ pr_err("rpm version %d is not available\n",
+ platform_data->version);
+ return -ENODEV;
+ }
+ if (config->use_legacy_optimum_mode)
+ for (i = 0; i < ARRAY_SIZE(vreg_ops); i++)
+ vreg_ops[i]->get_optimum_mode
+ = vreg_legacy_get_optimum_mode;
+ rpm_vreg_set_point_init();
+ /* First time probed; initialize pin control mutexes. */
+ for (i = 0; i < config->vregs_len; i++)
+ mutex_init(&config->vregs[i].pc_lock);
+ }
+
+ /* Initialize all of the regulators listed in the platform data. */
+ for (i = 0; i < platform_data->num_regulators; i++) {
+ rc = rpm_vreg_init_regulator(&platform_data->init_data[i],
+ &pdev->dev);
+ if (rc) {
+ pr_err("rpm_vreg_init_regulator failed, rc=%d\n", rc);
+ goto remove_regulators;
+ }
+ }
+
+ platform_set_drvdata(pdev, platform_data);
+
+ return rc;
+
+remove_regulators:
+ /* Unregister all regulators added before the erroring one. */
+ for (; i >= 0; i--) {
+ id = platform_data->init_data[i].id;
+ if (config->is_real_id(id)) {
+ regulator_unregister(config->vregs[id].rdev);
+ config->vregs[id].rdev = NULL;
+ } else {
+ regulator_unregister(config->vregs[
+ config->pc_id_to_real_id(id)].rdev_pc);
+ config->vregs[id].rdev_pc = NULL;
+ }
+ }
return rc;
}
static int __devexit rpm_vreg_remove(struct platform_device *pdev)
{
- struct regulator_dev *rdev = platform_get_drvdata(pdev);
+ struct rpm_regulator_platform_data *platform_data;
+ int i, id;
+ platform_data = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, NULL);
- regulator_unregister(rdev);
+
+ if (platform_data) {
+ for (i = 0; i < platform_data->num_regulators; i++) {
+ id = platform_data->init_data[i].id;
+ if (config->is_real_id(id)) {
+ regulator_unregister(config->vregs[id].rdev);
+ config->vregs[id].rdev = NULL;
+ } else {
+ regulator_unregister(config->vregs[
+ config->pc_id_to_real_id(id)].rdev_pc);
+ config->vregs[id].rdev_pc = NULL;
+ }
+ }
+ }
return 0;
}
@@ -1467,7 +1391,7 @@
.probe = rpm_vreg_probe,
.remove = __devexit_p(rpm_vreg_remove),
.driver = {
- .name = "rpm-regulator",
+ .name = RPM_REGULATOR_DEV_NAME,
.owner = THIS_MODULE,
},
};
@@ -1479,189 +1403,18 @@
static void __exit rpm_vreg_exit(void)
{
+ int i;
+
platform_driver_unregister(&rpm_vreg_driver);
+
+ for (i = 0; i < config->vregs_len; i++)
+ mutex_destroy(&config->vregs[i].pc_lock);
}
postcore_initcall(rpm_vreg_init);
module_exit(rpm_vreg_exit);
-#define VREG_ID_IS_8058_S0_OR_S1(id) \
- ((id == RPM_VREG_ID_PM8058_S0) || (id == RPM_VREG_ID_PM8058_S1))
-
-static void print_rpm_request(struct vreg *vreg, int set)
-{
- int v, ip, fm, pc, pf, pd, ia, freq, clk, state;
-
- /* Suppress 8058_s0 and 8058_s1 printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_8058_S0_S1)
- && VREG_ID_IS_8058_S0_OR_S1(vreg->id))
- return;
-
- if (IS_LDO(vreg->id)) {
- v = (vreg->req[0].value & LDO_VOLTAGE) >> LDO_VOLTAGE_SHIFT;
- ip = (vreg->req[0].value & LDO_PEAK_CURRENT)
- >> LDO_PEAK_CURRENT_SHIFT;
- fm = (vreg->req[0].value & LDO_MODE) >> LDO_MODE_SHIFT;
- pc = (vreg->req[0].value & LDO_PIN_CTRL) >> LDO_PIN_CTRL_SHIFT;
- pf = (vreg->req[0].value & LDO_PIN_FN) >> LDO_PIN_FN_SHIFT;
- pd = (vreg->req[1].value & LDO_PULL_DOWN_ENABLE)
- >> LDO_PULL_DOWN_ENABLE_SHIFT;
- ia = (vreg->req[1].value & LDO_AVG_CURRENT)
- >> LDO_AVG_CURRENT_SHIFT;
-
- pr_info("rpm-regulator: %s %-9s: s=%c, v=%4d mV, ip=%4d "
- "mA, fm=%s (%d), pc=%s%s%s%s%s (%d), pf=%s (%d), pd=%s "
- "(%d), ia=%4d mA; req[0]={%d, 0x%08X}, "
- "req[1]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg_descrip[vreg->id].name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'), v, ip,
- (fm == RPM_VREG_MODE_NONE ? "none" :
- (fm == RPM_VREG_MODE_LPM ? "LPM" :
- (fm == RPM_VREG_MODE_HPM ? "HPM" : ""))),
- fm,
- (pc & RPM_VREG_PIN_CTRL_A0 ? " A0" : ""),
- (pc & RPM_VREG_PIN_CTRL_A1 ? " A1" : ""),
- (pc & RPM_VREG_PIN_CTRL_D0 ? " D0" : ""),
- (pc & RPM_VREG_PIN_CTRL_D1 ? " D1" : ""),
- (pc == RPM_VREG_PIN_CTRL_NONE ? " none" : ""), pc,
- (pf == RPM_VREG_PIN_FN_NONE ?
- "none" :
- (pf == RPM_VREG_PIN_FN_ENABLE ?
- "on/off" :
- (pf == RPM_VREG_PIN_FN_MODE ?
- "HPM/LPM" :
- (pf == RPM_VREG_PIN_FN_SLEEP_B ?
- "sleep_b" : "")))),
- pf, (pd == 1 ? "Y" : "N"), pd, ia,
- vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
-
- } else if (IS_SMPS(vreg->id)) {
- v = (vreg->req[0].value & SMPS_VOLTAGE) >> SMPS_VOLTAGE_SHIFT;
- ip = (vreg->req[0].value & SMPS_PEAK_CURRENT)
- >> SMPS_PEAK_CURRENT_SHIFT;
- fm = (vreg->req[0].value & SMPS_MODE) >> SMPS_MODE_SHIFT;
- pc = (vreg->req[0].value & SMPS_PIN_CTRL)
- >> SMPS_PIN_CTRL_SHIFT;
- pf = (vreg->req[0].value & SMPS_PIN_FN) >> SMPS_PIN_FN_SHIFT;
- pd = (vreg->req[1].value & SMPS_PULL_DOWN_ENABLE)
- >> SMPS_PULL_DOWN_ENABLE_SHIFT;
- ia = (vreg->req[1].value & SMPS_AVG_CURRENT)
- >> SMPS_AVG_CURRENT_SHIFT;
- freq = (vreg->req[1].value & SMPS_FREQ) >> SMPS_FREQ_SHIFT;
- clk = (vreg->req[1].value & SMPS_CLK_SRC) >> SMPS_CLK_SRC_SHIFT;
-
- pr_info("rpm-regulator: %s %-9s: s=%c, v=%4d mV, ip=%4d "
- "mA, fm=%s (%d), pc=%s%s%s%s%s (%d), pf=%s (%d), pd=%s "
- "(%d), ia=%4d mA, freq=%2d, clk=%d; "
- "req[0]={%d, 0x%08X}, req[1]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg_descrip[vreg->id].name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'), v, ip,
- (fm == RPM_VREG_MODE_NONE ? "none" :
- (fm == RPM_VREG_MODE_LPM ? "LPM" :
- (fm == RPM_VREG_MODE_HPM ? "HPM" : ""))),
- fm,
- (pc & RPM_VREG_PIN_CTRL_A0 ? " A0" : ""),
- (pc & RPM_VREG_PIN_CTRL_A1 ? " A1" : ""),
- (pc & RPM_VREG_PIN_CTRL_D0 ? " D0" : ""),
- (pc & RPM_VREG_PIN_CTRL_D1 ? " D1" : ""),
- (pc == RPM_VREG_PIN_CTRL_NONE ? " none" : ""), pc,
- (pf == RPM_VREG_PIN_FN_NONE ?
- "none" :
- (pf == RPM_VREG_PIN_FN_ENABLE ?
- "on/off" :
- (pf == RPM_VREG_PIN_FN_MODE ?
- "HPM/LPM" :
- (pf == RPM_VREG_PIN_FN_SLEEP_B ?
- "sleep_b" : "")))),
- pf, (pd == 1 ? "Y" : "N"), pd, ia, freq, clk,
- vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
-
- } else if (IS_SWITCH(vreg->id)) {
- state = (vreg->req[0].value & SWITCH_STATE)
- >> SWITCH_STATE_SHIFT;
- pd = (vreg->req[0].value & SWITCH_PULL_DOWN_ENABLE)
- >> SWITCH_PULL_DOWN_ENABLE_SHIFT;
- pc = (vreg->req[0].value & SWITCH_PIN_CTRL)
- >> SWITCH_PIN_CTRL_SHIFT;
- pf = (vreg->req[0].value & SWITCH_PIN_FN)
- >> SWITCH_PIN_FN_SHIFT;
-
- pr_info("rpm-regulator: %s %-9s: s=%c, state=%s (%d), "
- "pd=%s (%d), pc =%s%s%s%s%s (%d), pf=%s (%d); "
- "req[0]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg_descrip[vreg->id].name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'),
- (state == 1 ? "on" : "off"), state,
- (pd == 1 ? "Y" : "N"), pd,
- (pc & RPM_VREG_PIN_CTRL_A0 ? " A0" : ""),
- (pc & RPM_VREG_PIN_CTRL_A1 ? " A1" : ""),
- (pc & RPM_VREG_PIN_CTRL_D0 ? " D0" : ""),
- (pc & RPM_VREG_PIN_CTRL_D1 ? " D1" : ""),
- (pc == RPM_VREG_PIN_CTRL_NONE ? " none" : ""), pc,
- (pf == RPM_VREG_PIN_FN_NONE ?
- "none" :
- (pf == RPM_VREG_PIN_FN_ENABLE ?
- "on/off" :
- (pf == RPM_VREG_PIN_FN_MODE ?
- "HPM/LPM" :
- (pf == RPM_VREG_PIN_FN_SLEEP_B ?
- "sleep_b" : "")))),
- pf, vreg->req[0].id, vreg->req[0].value);
-
- } else if (IS_NCP(vreg->id)) {
- v = (vreg->req[0].value & NCP_VOLTAGE) >> NCP_VOLTAGE_SHIFT;
- state = (vreg->req[0].value & NCP_STATE) >> NCP_STATE_SHIFT;
-
- pr_info("rpm-regulator: %s %-9s: s=%c, v=-%4d mV, "
- "state=%s (%d); req[0]={%d, 0x%08X}\n",
- (set == MSM_RPM_CTX_SET_0 ? "sending " : "buffered"),
- vreg_descrip[vreg->id].name,
- (set == MSM_RPM_CTX_SET_0 ? 'A' : 'S'),
- v, (state == 1 ? "on" : "off"), state,
- vreg->req[0].id, vreg->req[0].value);
- }
-}
-
-static void print_rpm_vote(struct vreg *vreg, enum rpm_vreg_voter voter,
- int set, int voter_mV, int aggregate_mV)
-{
- /* Suppress 8058_s0 and 8058_s1 printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_8058_S0_S1)
- && VREG_ID_IS_8058_S0_OR_S1(vreg->id))
- return;
-
- pr_info("rpm-regulator: vote received %-9s: voter=%d, set=%c, "
- "v_voter=%4d mV, v_aggregate=%4d mV\n",
- vreg_descrip[vreg->id].name, voter, (set == 0 ? 'A' : 'S'),
- voter_mV, aggregate_mV);
-}
-
-static void print_rpm_duplicate(struct vreg *vreg, int set, int cnt)
-{
- /* Suppress 8058_s0 and 8058_s1 printing. */
- if ((msm_rpm_vreg_debug_mask & MSM_RPM_VREG_DEBUG_IGNORE_8058_S0_S1)
- && VREG_ID_IS_8058_S0_OR_S1(vreg->id))
- return;
-
- if (cnt == 2)
- pr_info("rpm-regulator: ignored duplicate request %-9s: set=%c;"
- " req[0]={%d, 0x%08X}, req[1]={%d, 0x%08X}\n",
- vreg_descrip[vreg->id].name, (set == 0 ? 'A' : 'S'),
- vreg->req[0].id, vreg->req[0].value,
- vreg->req[1].id, vreg->req[1].value);
- else if (cnt == 1)
- pr_info("rpm-regulator: ignored duplicate request %-9s: set=%c;"
- " req[0]={%d, 0x%08X}\n",
- vreg_descrip[vreg->id].name, (set == 0 ? 'A' : 'S'),
- vreg->req[0].id, vreg->req[0].value);
-}
-
MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("rpm regulator driver");
+MODULE_DESCRIPTION("MSM RPM regulator driver");
MODULE_VERSION("1.0");
-MODULE_ALIAS("platform:rpm-regulator");
+MODULE_ALIAS("platform:" RPM_REGULATOR_DEV_NAME);
diff --git a/arch/arm/mach-msm/sdio_al.c b/arch/arm/mach-msm/sdio_al.c
index 3acd4a4..ace437b 100644
--- a/arch/arm/mach-msm/sdio_al.c
+++ b/arch/arm/mach-msm/sdio_al.c
@@ -108,6 +108,7 @@
* packet) rx data.
*/
#define DEFAULT_READ_THRESHOLD (1024)
+#define LOW_LATENCY_THRESHOLD (1)
/* Extra bytes to ensure getting the rx threshold interrupt on stream channels
when restoring the threshold after sleep */
@@ -119,7 +120,6 @@
#define THRESHOLD_DISABLE_VAL (0xFFFFFFFF)
-
/** Mailbox polling time for packet channels */
#define DEFAULT_POLL_DELAY_MSEC 10
/** Mailbox polling time for streaming channels */
@@ -351,6 +351,7 @@
struct sdio_al_device *bootloader_dev;
void *subsys_notif_handle;
int sdioc_major;
+ int skip_print_info;
};
struct sdio_al_work {
@@ -985,7 +986,7 @@
continue;
}
if (ch->is_packet_mode == false) {
- ch->read_threshold = 1;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
set_pipe_threshold(sdio_al_dev,
ch->rx_pipe_index,
ch->read_threshold);
@@ -993,7 +994,7 @@
}
/* Prevent modem to go to sleep until we get the PROG_DONE on
the dummy CMD52 */
- msmsdcc_set_pwrsave(sdio_al_dev->card->host, 0);
+ msmsdcc_set_pwrsave(sdio_al_dev->host, 0);
/* Mark HOST_OK_TOSLEEP */
sdio_al_dev->is_ok_to_sleep = 1;
write_lpm_info(sdio_al_dev);
@@ -1155,13 +1156,22 @@
sdio_al_dev->host->index);
}
ch->read_avail = read_avail;
- /* Restore default thresh for non packet channels */
+
+ /*
+ * Restore default thresh for non packet channels.
+ * in case it IS low latency channel then read_threshold
+ * and def_read_threshold are both
+ * LOW_LATENCY_THRESHOLD
+ */
if ((ch->read_threshold != ch->def_read_threshold) &&
(read_avail >= ch->threshold_change_cnt)) {
- ch->read_threshold = ch->def_read_threshold;
- set_pipe_threshold(sdio_al_dev,
- ch->rx_pipe_index,
- ch->read_threshold);
+ if (!ch->is_low_latency_ch) {
+ ch->read_threshold =
+ ch->def_read_threshold;
+ set_pipe_threshold(sdio_al_dev,
+ ch->rx_pipe_index,
+ ch->read_threshold);
+ }
}
}
@@ -1967,14 +1977,18 @@
goto exit_err;
}
- /* Aggregation up to 90% of the maximum size */
- ch->read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+ ch->read_threshold = LOW_LATENCY_THRESHOLD;
+ ch->is_low_latency_ch = ch_config->is_low_latency_ch;
/* Threshold on 50% of the maximum size , sdioc uses double-buffer */
ch->write_threshold = (ch_config->max_tx_threshold * 5) / 10;
ch->threshold_change_cnt = ch->ch_config.max_rx_threshold -
ch->read_threshold + THRESHOLD_CHANGE_EXTRA_BYTES;
- ch->def_read_threshold = ch->read_threshold;
+ if (ch->is_low_latency_ch)
+ ch->def_read_threshold = LOW_LATENCY_THRESHOLD;
+ else /* Aggregation up to 90% of the maximum size */
+ ch->def_read_threshold = (ch_config->max_rx_threshold * 9) / 10;
+
ch->is_packet_mode = ch_config->is_packet_mode;
if (!ch->is_packet_mode) {
ch->poll_delay_msec = DEFAULT_POLL_DELAY_NOPACKET_MSEC;
@@ -2359,10 +2373,9 @@
u32 not_from_int, struct sdio_channel *ch)
{
int ret = 0;
- struct sdio_func *wk_func =
- sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1];
+ struct sdio_func *wk_func = NULL;
unsigned long time_to_wait;
- struct mmc_host *host = wk_func->card->host;
+ struct mmc_host *host = sdio_al_dev->host;
if (sdio_al_dev->is_err) {
SDIO_AL_ERR(__func__);
@@ -2398,7 +2411,7 @@
sdio_al_vote_for_sleep(sdio_al_dev, 0);
msmsdcc_lpm_disable(host);
- msmsdcc_set_pwrsave(sdio_al_dev->card->host, 0);
+ msmsdcc_set_pwrsave(host, 0);
/* Poll the GPIO */
time_to_wait = jiffies + msecs_to_jiffies(1000);
while (time_before(jiffies, time_to_wait)) {
@@ -2416,6 +2429,13 @@
"get_mdm2ap_status() is 0\n");
/* Enable Wake up Function */
+ if (!sdio_al_dev->card ||
+ !sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1]) {
+ sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME
+ ": NULL card or wk_func\n");
+ return -ENODEV;
+ }
+ wk_func = sdio_al_dev->card->sdio_func[SDIO_AL_WAKEUP_FUNC-1];
ret = sdio_al_enable_func_retry(wk_func, "wakeup func");
if (ret) {
sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME ": "
@@ -2442,13 +2462,13 @@
LPM_DEBUG(sdio_al_dev->dev_log, MODULE_NAME "Finished Wake up sequence"
" for card %d", sdio_al_dev->host->index);
- msmsdcc_set_pwrsave(sdio_al_dev->card->host, 1);
+ msmsdcc_set_pwrsave(host, 1);
pr_debug(MODULE_NAME ":Turn clock off\n");
return ret;
error_exit:
sdio_al_vote_for_sleep(sdio_al_dev, 1);
- msmsdcc_set_pwrsave(sdio_al_dev->card->host, 1);
+ msmsdcc_set_pwrsave(host, 1);
WARN_ON(ret);
sdio_al_get_into_err_state(sdio_al_dev);
return ret;
@@ -2476,8 +2496,7 @@
pr_debug(MODULE_NAME ":start %s.\n", __func__);
if (sdio_al_dev == NULL) {
- sdio_al_loge(&sdio_al->gen_log, MODULE_NAME ": NULL sdio_al_dev"
- " for card %d\n", func->card->host->index);
+ sdio_al_loge(&sdio_al->gen_log, MODULE_NAME ": NULL device");
return;
}
@@ -2527,18 +2546,13 @@
int i = 0;
int fn = 0;
- if (card == NULL) {
- sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME ": "
- "sdio_al_setup: No Card detected\n");
+ if (sdio_al_verify_func1(sdio_al_dev, __func__))
return -ENODEV;
- }
-
+ func1 = card->sdio_func[0];
sdio_al_logi(sdio_al_dev->dev_log, MODULE_NAME ":sdio_al_setup for "
"card %d\n", sdio_al_dev->host->index);
- func1 = card->sdio_func[0];
-
ret = sdio_al->pdata->config_mdm2ap_status(1);
if (ret) {
sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME "Could not "
@@ -2560,13 +2574,13 @@
sdio_set_drvdata(func1, sdio_al_dev);
sdio_al_logi(sdio_al_dev->dev_log, MODULE_NAME ":claim IRQ for card "
- "%d\n", card->host->index);
+ "%d\n", sdio_al_dev->host->index);
ret = sdio_claim_irq(func1, sdio_func_irq);
if (ret) {
sdio_al_loge(sdio_al_dev->dev_log, MODULE_NAME ":Fail to claim"
" IRQ for card %d\n",
- card->host->index);
+ sdio_al_dev->host->index);
return ret;
}
@@ -3797,6 +3811,7 @@
}
dev_info(&card->dev, "SDIO Card claimed.\n");
+ sdio_al->skip_print_info = 0;
sdio_al_dev->state = CARD_INSERTED;
@@ -4018,13 +4033,12 @@
struct sdio_func *lpm_func = NULL;
int offset = 0;
int is_ok_to_sleep = 0;
- static atomic_t first_time;
char buf[50];
- if (atomic_read(&first_time) == 1)
+ if (sdio_al->skip_print_info == 1)
return;
- atomic_set(&first_time, 1);
+ sdio_al->skip_print_info = 1;
sdio_al_loge(&sdio_al->gen_log, MODULE_NAME ": %s - SDIO DEBUG INFO\n",
__func__);
diff --git a/arch/arm/mach-msm/sdio_al_private.h b/arch/arm/mach-msm/sdio_al_private.h
index f352499..36d9ec1 100644
--- a/arch/arm/mach-msm/sdio_al_private.h
+++ b/arch/arm/mach-msm/sdio_al_private.h
@@ -66,7 +66,8 @@
u32 is_host_ok_to_sleep;
u32 is_packet_mode;
u32 peer_operation;
- u32 reserved[24];
+ u32 is_low_latency_ch;
+ u32 reserved[23];
};
@@ -173,6 +174,7 @@
int min_write_avail;
int poll_delay_msec;
int is_packet_mode;
+ int is_low_latency_ch;
struct peer_sdioc_channel_config ch_config;
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 7dec32a..94dd8b8 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -43,15 +43,17 @@
#if defined(CONFIG_ARCH_QSD8X50) || defined(CONFIG_ARCH_MSM8X60) \
|| defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_FSM9XXX) \
- || defined(CONFIG_ARCH_MSM9615)
+ || defined(CONFIG_ARCH_MSM9615) || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_QDSP6 1
#endif
-#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
+#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) \
+ || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_DSPS 1
#endif
-#if defined(CONFIG_ARCH_MSM8960)
+#if defined(CONFIG_ARCH_MSM8960) \
+ || defined(CONFIG_ARCH_APQ8064)
#define CONFIG_WCNSS 1
#define CONFIG_DSPS_SMSM 1
#endif
@@ -200,6 +202,23 @@
#define MSM_TRIG_A2DSPS_SMSM_INT
#define MSM_TRIG_A2WCNSS_SMD_INT
#define MSM_TRIG_A2WCNSS_SMSM_INT
+#elif defined(CONFIG_ARCH_APQ8064)
+#define MSM_TRIG_A2M_SMD_INT \
+ (smd_write_intr(1 << 3, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2Q6_SMD_INT \
+ (smd_write_intr(1 << 15, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2M_SMSM_INT \
+ (smd_write_intr(1 << 4, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2Q6_SMSM_INT \
+ (smd_write_intr(1 << 14, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2DSPS_SMD_INT \
+ (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4080))
+#define MSM_TRIG_A2DSPS_SMSM_INT \
+ (smd_write_intr(1, MSM_SIC_NON_SECURE_BASE + 0x4094))
+#define MSM_TRIG_A2WCNSS_SMD_INT \
+ (smd_write_intr(1 << 25, MSM_APCS_GCC_BASE + 0x8))
+#define MSM_TRIG_A2WCNSS_SMSM_INT \
+ (smd_write_intr(1 << 23, MSM_APCS_GCC_BASE + 0x8))
#elif defined(CONFIG_ARCH_FSM9XXX)
#define MSM_TRIG_A2Q6_SMD_INT \
(smd_write_intr(1 << 10, MSM_GCC_BASE + 0x8))
diff --git a/arch/arm/mach-msm/subsystem_restart.c b/arch/arm/mach-msm/subsystem_restart.c
index 4d6f4b1..b862ad4 100644
--- a/arch/arm/mach-msm/subsystem_restart.c
+++ b/arch/arm/mach-msm/subsystem_restart.c
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
+#define pr_fmt(fmt) "subsys-restart: %s(): " fmt, __func__
+
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/uaccess.h>
@@ -32,12 +34,6 @@
#include "smd_private.h"
-#if defined(SUBSYS_RESTART_DEBUG)
-#define dprintk(msg...) printk(msg)
-#else
-#define dprintk(msg...)
-#endif
-
struct subsys_soc_restart_order {
const char * const *subsystem_list;
int count;
@@ -152,12 +148,11 @@
case RESET_SOC:
case RESET_SUBSYS_COUPLED:
case RESET_SUBSYS_INDEPENDENT:
- pr_info("Subsystem Restart: Phase %d behavior activated.\n",
- restart_level);
+ pr_info("Phase %d behavior activated.\n", restart_level);
break;
case RESET_SUBSYS_MIXED:
- pr_info("Subsystem Restart: Phase 2+ behavior activated.\n");
+ pr_info("Phase 2+ behavior activated.\n");
break;
default:
@@ -277,10 +272,10 @@
}
if (!n) {
time_first = &r_log->time;
- pr_debug("time_first: %ld", time_first->tv_sec);
+ pr_debug("Time_first: %ld\n", time_first->tv_sec);
}
n++;
- pr_debug("restart_time: %ld\n", r_log->time.tv_sec);
+ pr_debug("Restart_time: %ld\n", r_log->time.tv_sec);
}
if (time_first && n >= max_restarts_check) {
@@ -327,8 +322,7 @@
shutdown_lock = &soc_restart_order->shutdown_lock;
}
- dprintk("%s[%p]: Attempting to get shutdown lock!\n", __func__,
- current);
+ pr_debug("[%p]: Attempting to get shutdown lock!\n", current);
/* Try to acquire shutdown_lock. If this fails, these subsystems are
* already being restarted - return.
@@ -338,8 +332,7 @@
do_exit(0);
}
- dprintk("%s[%p]: Attempting to get powerup lock!\n", __func__,
- current);
+ pr_debug("[%p]: Attempting to get powerup lock!\n", current);
/* Now that we've acquired the shutdown lock, either we're the first to
* restart these subsystems or some other thread is doing the powerup
@@ -347,7 +340,8 @@
* out, since a subsystem died in its powerup sequence.
*/
if (!mutex_trylock(powerup_lock))
- panic("%s: Subsystem died during powerup!", __func__);
+ panic("%s[%p]: Subsystem died during powerup!",
+ __func__, current);
do_epoch_check(subsys);
@@ -357,8 +351,8 @@
*/
mutex_lock(&soc_order_reg_lock);
- dprintk("%s: Starting restart sequence for %s\n", __func__,
- r_work->subsys->name);
+ pr_debug("[%p]: Starting restart sequence for %s\n", current,
+ r_work->subsys->name);
_send_notification_to_order(restart_list,
restart_list_count,
@@ -369,12 +363,12 @@
if (!restart_list[i])
continue;
- pr_info("subsys-restart: Shutting down %s\n",
+ pr_info("[%p]: Shutting down %s\n", current,
restart_list[i]->name);
if (restart_list[i]->shutdown(subsys) < 0)
- panic("%s: Failed to shutdown %s!\n", __func__,
- restart_list[i]->name);
+ panic("subsys-restart: %s[%p]: Failed to shutdown %s!",
+ __func__, current, restart_list[i]->name);
}
_send_notification_to_order(restart_list, restart_list_count,
@@ -395,8 +389,8 @@
if (restart_list[i]->ramdump)
if (restart_list[i]->ramdump(enable_ramdumps,
subsys) < 0)
- pr_warn("%s(%s): Ramdump failed.", __func__,
- restart_list[i]->name);
+ pr_warn("%s[%p]: Ramdump failed.\n",
+ restart_list[i]->name, current);
}
_send_notification_to_order(restart_list,
@@ -408,26 +402,26 @@
if (!restart_list[i])
continue;
- pr_info("subsys-restart: Powering up %s\n",
- restart_list[i]->name);
+ pr_info("[%p]: Powering up %s\n", current,
+ restart_list[i]->name);
if (restart_list[i]->powerup(subsys) < 0)
- panic("%s: Failed to powerup %s!", __func__,
- restart_list[i]->name);
+ panic("%s[%p]: Failed to powerup %s!", __func__,
+ current, restart_list[i]->name);
}
_send_notification_to_order(restart_list,
restart_list_count,
SUBSYS_AFTER_POWERUP);
- pr_info("%s: Restart sequence for %s completed.", __func__,
- r_work->subsys->name);
+ pr_info("[%p]: Restart sequence for %s completed.\n",
+ current, r_work->subsys->name);
mutex_unlock(powerup_lock);
mutex_unlock(&soc_order_reg_lock);
- dprintk("%s: Released powerup lock!\n", __func__);
+ pr_debug("[%p]: Released powerup lock!\n", current);
kfree(data);
do_exit(0);
@@ -440,11 +434,11 @@
struct restart_thread_data *data = NULL;
if (!subsys_name) {
- pr_err("%s: Invalid subsystem name.", __func__);
+ pr_err("Invalid subsystem name.\n");
return -EINVAL;
}
- pr_info("Subsystem Restart: Restart sequence requested for %s\n",
+ pr_info("Restart sequence requested for %s\n",
subsys_name);
/* List of subsystems is protected by a lock. New subsystems can
@@ -453,8 +447,7 @@
subsys = _find_subsystem(subsys_name);
if (!subsys) {
- pr_warn("%s: Unregistered subsystem %s!", __func__,
- subsys_name);
+ pr_warn("Unregistered subsystem %s!\n", subsys_name);
return -EINVAL;
}
@@ -462,8 +455,7 @@
data = kzalloc(sizeof(struct restart_thread_data), GFP_KERNEL);
if (!data) {
restart_level = RESET_SOC;
- pr_warn("%s: Failed to alloc restart data. Resetting.",
- __func__);
+ pr_warn("Failed to alloc restart data. Resetting.\n");
} else {
if (restart_level == RESET_SUBSYS_COUPLED ||
restart_level == RESET_SUBSYS_MIXED)
@@ -480,8 +472,8 @@
case RESET_SUBSYS_COUPLED:
case RESET_SUBSYS_MIXED:
case RESET_SUBSYS_INDEPENDENT:
- dprintk("%s: Restarting %s [level=%d]!\n", __func__,
- subsys_name, restart_level);
+ pr_debug("Restarting %s [level=%d]!\n", subsys_name,
+ restart_level);
/* Let the kthread handle the actual restarting. Using a
* workqueue will not work since all restart requests are
@@ -490,7 +482,7 @@
* sequence.
*/
tsk = kthread_run(subsystem_restart_thread, data,
- "subsystem_subsystem_restart_thread");
+ "subsystem_restart_thread");
if (IS_ERR(tsk))
panic("%s: Unable to create thread to restart %s",
__func__, subsys->name);
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 2719891..66bab6b 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -42,6 +42,8 @@
struct wake_lock wake_lock_tx;
struct wake_lock wake_lock_rx;
struct timer_list rx_q_timer;
+ struct tasklet_struct hci_event_task;
+ struct tasklet_struct hci_data_task;
};
struct hci_smd_data hs;
@@ -160,6 +162,11 @@
rc = hci_recv_frame(skb);
if (rc < 0) {
BT_ERR("Error in passing the packet to HCI Layer");
+ /*
+ * skb is getting freed in hci_recv_frame, making it
+ * to null to avoid multiple access
+ */
+ skb = NULL;
goto out_data;
}
@@ -228,6 +235,11 @@
rc = hci_recv_frame(skb);
if (rc < 0) {
BT_ERR("Error in passing the packet to HCI Layer");
+ /*
+ * skb is getting freed in hci_recv_frame, making it
+ * to null to avoid multiple access
+ */
+ skb = NULL;
goto out_event;
}
@@ -290,6 +302,7 @@
break;
}
+ kfree_skb(skb);
wake_unlock(&hs.wake_lock_tx);
return ret;
}
@@ -306,7 +319,7 @@
switch (event) {
case SMD_EVENT_DATA:
- hci_smd_recv_event(event);
+ tasklet_hi_schedule(&hs.hci_event_task);
break;
case SMD_EVENT_OPEN:
hci_smd_open(hdev);
@@ -329,7 +342,7 @@
switch (event) {
case SMD_EVENT_DATA:
- hci_smd_recv_data(event);
+ tasklet_hi_schedule(&hs.hci_data_task);
break;
case SMD_EVENT_OPEN:
hci_smd_open(hdev);
@@ -364,6 +377,11 @@
hdev->destruct = hci_smd_destruct;
hdev->owner = THIS_MODULE;
+ tasklet_init(&hsmd->hci_event_task,
+ hci_smd_recv_event, (unsigned long) hsmd);
+ tasklet_init(&hsmd->hci_data_task,
+ hci_smd_recv_data, (unsigned long) hsmd);
+
wake_lock_init(&hs.wake_lock_rx, WAKE_LOCK_SUSPEND, "msm_smd_Rx");
wake_lock_init(&hs.wake_lock_tx, WAKE_LOCK_SUSPEND, "msm_smd_Tx");
/*
@@ -414,6 +432,8 @@
/*Destroy the timer used to monitor the Rx queue for emptiness */
del_timer_sync(&hs.rx_q_timer);
+ tasklet_kill(&hs.hci_event_task);
+ tasklet_kill(&hs.hci_data_task);
}
static int hci_smd_init(void)
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 6fa043c..eabdb4f 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -253,7 +253,18 @@
return -ENOMEM;
}
-void diag_fill_reg_table(int j, struct bindpkt_params *params,
+void diag_clear_reg(int proc_num)
+{
+ int i;
+
+ for (i = 0; i < diag_max_registration; i++) {
+ if (driver->table[i].client_id == proc_num) {
+ driver->table[i].process_id = 0;
+ }
+ }
+}
+
+void diag_add_reg(int j, struct bindpkt_params *params,
int *success, int *count_entries)
{
*success = 1;
@@ -284,7 +295,7 @@
mutex_lock(&driver->diagchar_mutex);
for (i = 0; i < diag_max_registration; i++) {
if (driver->table[i].process_id == 0) {
- diag_fill_reg_table(i, pkt_params->params,
+ diag_add_reg(i, pkt_params->params,
&success, &count_entries);
if (pkt_params->count > count_entries) {
pkt_params->params++;
@@ -315,7 +326,7 @@
driver->table = temp_buf;
}
for (j = i; j < diag_max_registration; j++) {
- diag_fill_reg_table(j, pkt_params->params,
+ diag_add_reg(j, pkt_params->params,
&success, &count_entries);
if (pkt_params->count > count_entries) {
pkt_params->params++;
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index e49d57c..caf3901 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -70,7 +70,7 @@
#define CHK_OVERFLOW(bufStart, start, end, length) \
((bufStart <= start) && (end - start >= length)) ? 1 : 0
-int chk_config_get_id()
+int chk_config_get_id(void)
{
switch (socinfo_get_id()) {
case APQ8060_MACHINE_ID:
@@ -78,6 +78,23 @@
return APQ8060_TOOLS_ID;
case AO8960_MACHINE_ID:
return AO8960_TOOLS_ID;
+ case APQ8064_MACHINE_ID:
+ return APQ8064_TOOLS_ID;
+ default:
+ return 0;
+ }
+}
+
+/*
+ * This will return TRUE for targets which support apps only mode.
+ * This applies to 8960 and newer targets.
+ */
+int chk_apps_only(void)
+{
+ switch (socinfo_get_id()) {
+ case AO8960_MACHINE_ID:
+ case APQ8064_MACHINE_ID:
+ return 1;
default:
return 0;
}
@@ -576,8 +593,8 @@
diag_update_event_mask(buf+1, 0, 0);
diag_update_userspace_clients(EVENT_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 */
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ /* Check for Apps Only */
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for apps only DIAG */
driver->apps_rsp_buf[0] = 0x60;
driver->apps_rsp_buf[1] = 0x0;
@@ -594,8 +611,8 @@
diag_update_log_mask(*(int *)buf, buf+8, *(int *)(buf+4));
diag_update_userspace_clients(LOG_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 */
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ /* Check for Apps Only */
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for Apps only DIAG */
driver->apps_rsp_buf[0] = 0x73;
*(int *)(driver->apps_rsp_buf + 4) = 0x3; /* op. ID */
@@ -617,7 +634,7 @@
diag_update_msg_mask(ssid_first, ssid_last , buf + 8);
diag_update_userspace_clients(MSG_MASKS_TYPE);
#if defined(CONFIG_DIAG_OVER_USB)
- if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)) {
+ if (!(driver->ch) && chk_apps_only()) {
/* echo response back for apps only DIAG */
for (i = 0; i < 8 + ssid_range; i++)
*(driver->apps_rsp_buf + i) = *(buf+i);
@@ -627,9 +644,8 @@
#endif
}
#if defined(CONFIG_DIAG_OVER_USB)
- /* Check for Apps Only 8960 & get event mask request */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
- && *buf == 0x81) {
+ /* Check for Apps Only & get event mask request */
+ else if (!(driver->ch) && chk_apps_only() && *buf == 0x81) {
driver->apps_rsp_buf[0] = 0x81;
driver->apps_rsp_buf[1] = 0x0;
*(uint16_t *)(driver->apps_rsp_buf + 2) = 0x0;
@@ -639,8 +655,8 @@
ENCODE_RSP_AND_SEND(6 + EVENT_LAST_ID/8);
return 0;
}
- /* Get log ID range & Check for Apps Only 8960 */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ /* Get log ID range & Check for Apps Only */
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x73) && *(int *)(buf+4) == 1) {
driver->apps_rsp_buf[0] = 0x73;
*(int *)(driver->apps_rsp_buf + 4) = 0x1; /* operation ID */
@@ -665,7 +681,7 @@
return 0;
}
/* Respond to Get SSID Range request message */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x7d) && (*(buf+1) == 0x1)) {
driver->apps_rsp_buf[0] = 0x7d;
driver->apps_rsp_buf[1] = 0x1;
@@ -713,8 +729,8 @@
ENCODE_RSP_AND_SEND(83);
return 0;
}
- /* Check for AO8960 Respond to Get Subsys Build mask */
- else if (!(driver->ch) && (chk_config_get_id() == AO8960_TOOLS_ID)
+ /* Check for Apps Only Respond to Get Subsys Build mask */
+ else if (!(driver->ch) && chk_apps_only()
&& (*buf == 0x7d) && (*(buf+1) == 0x2)) {
ssid_first = *(uint16_t *)(buf + 2);
ssid_last = *(uint16_t *)(buf + 4);
@@ -901,13 +917,13 @@
driver->debug_flag = 0;
}
/* send error responses from APPS for Central Routing */
- if (type == 1 && chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (type == 1 && chk_apps_only()) {
diag_send_error_rsp(hdlc.dest_idx);
type = 0;
}
/* implies this packet is NOT meant for apps */
if (!(driver->ch) && type == 1) {
- if (chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (chk_apps_only()) {
diag_send_error_rsp(hdlc.dest_idx);
} else { /* APQ 8060, Let Q6 respond */
if (driver->chqdsp)
@@ -1129,7 +1145,11 @@
static void diag_smd_notify(void *ctxt, unsigned event)
{
- queue_work(driver->diag_wq, &(driver->diag_read_smd_work));
+ if (event == SMD_EVENT_CLOSE) {
+ pr_info("diag: clean modem registration\n");
+ diag_clear_reg(MODEM_PROC);
+ } else
+ queue_work(driver->diag_wq, &(driver->diag_read_smd_work));
}
#if defined(CONFIG_MSM_N_WAY_SMD)
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index cc24cbc..6dacab7 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -26,7 +26,8 @@
long diagchar_ioctl(struct file *, unsigned int, unsigned long);
int diag_device_write(void *, int, struct diag_request *);
int mask_request_validate(unsigned char mask_buf[]);
-int chk_config_get_id(void);
+void diag_clear_reg(int);
+int chk_apps_only(void);
/* State for diag forwarding */
#ifdef CONFIG_DIAG_OVER_USB
int diagfwd_connect(void);
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 2b88a9f..534c016 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -138,7 +138,7 @@
int r = 0;
/* open control ports only on 8960 */
- if (chk_config_get_id() == AO8960_TOOLS_ID) {
+ if (chk_apps_only()) {
if (pdev->id == SMD_APPS_MODEM)
r = smd_open("DIAG_CNTL", &driver->ch_cntl, driver,
diag_smd_cntl_notify);
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 3a2cd9a..5937c78 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/types.h>
+#include <mach/socinfo.h>
#define DRIVER_NAME "msm_rng"
@@ -78,11 +79,11 @@
/* read random data from h/w */
do {
/* check status bit if data is available */
- if (!(readl(base + PRNG_STATUS_OFFSET) & 0x00000001))
+ if (!(readl_relaxed(base + PRNG_STATUS_OFFSET) & 0x00000001))
break; /* no data to read so just bail */
/* read FIFO */
- val = readl(base + PRNG_DATA_OUT_OFFSET);
+ val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET);
if (!val)
break; /* no data to read so just bail */
@@ -106,6 +107,45 @@
.read = msm_rng_read,
};
+static int __devinit msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev)
+{
+ unsigned long val = 0;
+ int ret = 0;
+ int error = 0;
+
+ ret = clk_enable(msm_rng_dev->prng_clk);
+ if (ret) {
+ dev_err(&(msm_rng_dev->pdev)->dev,
+ "failed to enable clock in probe\n");
+ error = -EPERM;
+ return error;
+ }
+
+ /* enable PRNG h/w*/
+ val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET) &
+ PRNG_LFSR_CFG_MASK;
+ val |= PRNG_LFSR_CFG_MASK;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET);
+
+ /* The PRNG CONFIG register should be read after writing to the
+ * PRNG_LFSR_CFG register.
+ */
+ mb();
+ val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) &
+ PRNG_CONFIG_MASK;
+ val |= PRNG_CONFIG_ENABLE;
+ writel_relaxed(val, msm_rng_dev->base + PRNG_CONFIG_OFFSET);
+
+ /* The PRNG clk should be disabled only after we have enabled the
+ * PRNG H/W by writting to the PRNG_CONFIG register.
+ */
+ mb();
+
+ clk_disable(msm_rng_dev->prng_clk);
+
+ return error;
+}
+
static int __devinit msm_rng_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -147,18 +187,25 @@
msm_rng_dev->pdev = pdev;
platform_set_drvdata(pdev, msm_rng_dev);
+ /* Enable rng h/w */
+ if (cpu_is_msm9615())
+ error = msm_rng_enable_hw(msm_rng_dev);
+
+ if (error)
+ goto rollback_clk;
+
/* register with hwrng framework */
msm_rng.priv = (unsigned long) msm_rng_dev;
error = hwrng_register(&msm_rng);
if (error) {
dev_err(&pdev->dev, "failed to register hwrng\n");
error = -EPERM;
- goto err_hw_register;
+ goto rollback_clk;
}
return 0;
-err_hw_register:
+rollback_clk:
clk_put(msm_rng_dev->prng_clk);
err_clk_get:
iounmap(msm_rng_dev->base);
diff --git a/drivers/char/msm_rotator.c b/drivers/char/msm_rotator.c
index 01a0504..555e4fa 100644
--- a/drivers/char/msm_rotator.c
+++ b/drivers/char/msm_rotator.c
@@ -61,6 +61,10 @@
#define MSM_ROTATOR_MAX_H 0x1fff
#define MSM_ROTATOR_MAX_W 0x1fff
+#define IS_NONPLANAR 0x0
+#define IS_PLANAR 0x1
+#define IS_PLANAR_16ALIGNED 0x2
+
/* from lsb to msb */
#define GET_PACK_PATTERN(a, x, y, z, bit) \
(((a)<<((bit)*3))|((x)<<((bit)*2))|((y)<<(bit))|(z))
@@ -260,6 +264,7 @@
case MDP_Y_CRCB_H2V2:
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CRCB_H2V2_TILE:
case MDP_Y_CBCR_H2V2_TILE:
return 1;
@@ -375,7 +380,7 @@
int new_session,
unsigned int in_chroma_paddr,
unsigned int out_chroma_paddr,
- int is_planar)
+ int planar_mode)
{
int bpp;
unsigned int in_chr_addr, out_chr_addr;
@@ -385,7 +390,13 @@
return -ENOTTY;
if (!in_chroma_paddr) {
- in_chr_addr = chroma_addr(in_paddr, info->src.width,
+ if (planar_mode & IS_PLANAR_16ALIGNED)
+ in_chr_addr = chroma_addr(in_paddr,
+ ALIGN(info->src.width, 16),
+ info->src.height,
+ bpp);
+ else
+ in_chr_addr = chroma_addr(in_paddr, info->src.width,
info->src.height,
bpp);
} else
@@ -408,19 +419,33 @@
((info->dst_y * info->dst.width)/2 + info->dst_x),
MSM_ROTATOR_OUTP1_ADDR);
- if (is_planar) {
- iowrite32(in_chr_addr +
+ if (planar_mode & IS_PLANAR) {
+ if (planar_mode & IS_PLANAR_16ALIGNED)
+ iowrite32(in_chr_addr +
+ ALIGN((info->src.width / 2), 16) *
+ (info->src.height / 2),
+ MSM_ROTATOR_SRCP2_ADDR);
+ else
+ iowrite32(in_chr_addr +
(info->src.width / 2) * (info->src.height / 2),
MSM_ROTATOR_SRCP2_ADDR);
}
if (new_session) {
- if (is_planar) {
- iowrite32(info->src.width |
+ if (planar_mode & IS_PLANAR) {
+ if (planar_mode & IS_PLANAR_16ALIGNED) {
+ iowrite32(ALIGN(info->src.width, 16) |
+ ALIGN((info->src.width / 2), 16) << 16,
+ MSM_ROTATOR_SRC_YSTRIDE1);
+ iowrite32(ALIGN((info->src.width / 2), 16),
+ MSM_ROTATOR_SRC_YSTRIDE2);
+ } else {
+ iowrite32(info->src.width |
(info->src.width / 2) << 16,
MSM_ROTATOR_SRC_YSTRIDE1);
- iowrite32((info->src.width / 2),
+ iowrite32((info->src.width / 2),
MSM_ROTATOR_SRC_YSTRIDE2);
+ }
} else {
iowrite32(info->src.width |
info->src.width << 16,
@@ -448,7 +473,8 @@
MSM_ROTATOR_SUB_BLOCK_CFG);
iowrite32(0 << 29 | /* frame format 0 = linear */
(use_imem ? 0 : 1) << 22 | /* tile size */
- (is_planar ? 1 : 2) << 19 | /* fetch planes */
+ ((planar_mode & IS_PLANAR) ?
+ 1 : 2) << 19 | /* fetch planes */
0 << 18 | /* unpack align */
1 << 17 | /* unpack tight */
1 << 13 | /* unpack count 0=1 component */
@@ -911,7 +937,7 @@
!= s,
in_chroma_paddr,
out_chroma_paddr,
- 0);
+ IS_NONPLANAR);
break;
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CR_CB_H2V2:
@@ -921,7 +947,16 @@
!= s,
in_chroma_paddr,
out_chroma_paddr,
- 1);
+ IS_PLANAR);
+ break;
+ case MDP_Y_CR_CB_GH2V2:
+ rc = msm_rotator_ycxcx_h2v2(msm_rotator_dev->img_info[s],
+ in_paddr, out_paddr, use_imem,
+ msm_rotator_dev->last_session_idx
+ != s,
+ in_chroma_paddr,
+ out_chroma_paddr,
+ IS_PLANAR | IS_PLANAR_16ALIGNED);
break;
case MDP_Y_CRCB_H2V2_TILE:
case MDP_Y_CBCR_H2V2_TILE:
@@ -1033,6 +1068,7 @@
case MDP_Y_CRCB_H2V2:
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CBCR_H2V1:
case MDP_Y_CRCB_H2V1:
case MDP_YCRYCB_H2V1:
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 8850516..8088e44 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -309,20 +309,21 @@
config CRYPTO_DEV_QCE
tristate "Qualcomm Crypto Engine (QCE) module"
- select CRYPTO_DEV_QCE40 if ARCH_MSM8960
+ select CRYPTO_DEV_QCE40 if ARCH_MSM8960 || ARCH_MSM9615
default n
help
- This driver supports Qualcomm Crypto Engine in MSM7x30 MSM8660
- MSM8x55 and MSM8960
+ This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
+ MSM8x55, MSM8960 and MSM9615
To compile this driver as a module, choose M here: the
For MSM7x30 MSM8660 and MSM8x55 the module is called qce
- For MSM8960 the module is called qce40
+ For MSM8960 and MSM9615 the module is called qce40
config CRYPTO_DEV_QCEDEV
tristate "QCEDEV Interface to CE module"
default n
help
- This driver supports Qualcomm QCEDEV Crypto in MSM7x30 MSM8660, MSM8960.
+ This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
+ MSM8960 and MSM9615.
This exposes the interface to the QCE hardware accelerator via IOCTLs
To compile this driver as a module, choose M here: the
module will be called qcedev.
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 90a7889..4ef2e08 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -29,6 +29,7 @@
#include <crypto/sha.h>
#include <mach/dma.h>
#include <mach/clk.h>
+#include <mach/socinfo.h>
#include "qce.h"
#include "qce40.h"
@@ -149,6 +150,12 @@
pce_dev->ce_dm.ce_block_size = 16;
}
}
+ /*
+ * This is a temporary change - until Data Mover changes its
+ * configuration from 16 byte crci to 64 byte crci.
+ */
+ if (cpu_is_msm9615())
+ pce_dev->ce_dm.ce_block_size = 16;
dev_info(pce_dev->pdev,
"IO base 0x%x\n, ce_in channel %d , "
@@ -161,6 +168,23 @@
return 0;
};
+#ifdef CONFIG_ARCH_MSM9615
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+ unsigned int val = 0;
+
+ val = (1 << CRYPTO_MASK_DOUT_INTR) | (1 << CRYPTO_MASK_DIN_INTR) |
+ (1 << CRYPTO_MASK_OP_DONE_INTR) |
+ (1 << CRYPTO_MASK_ERR_INTR);
+
+ writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG);
+}
+#else
+static void config_ce_engine(struct qce_device *pce_dev)
+{
+
+}
+#endif
static void _check_probe_done_call_back(struct msm_dmov_cmd *cmd_ptr,
unsigned int result, struct msm_dmov_errdata *err)
@@ -185,6 +209,22 @@
clk_reset(pce_dev->ce_core_clk, CLK_RESET_ASSERT);
clk_reset(pce_dev->ce_core_clk, CLK_RESET_DEASSERT);
+ /*
+ * Ensure previous instruction (any writes to CLK registers)
+ * to toggle the CLK reset lines was completed before configuring
+ * ce engine. The ce engine configuration settings should not be lost
+ * becasue of clk reset.
+ */
+ mb();
+
+ /* Configure the CE Engine */
+ config_ce_engine(pce_dev);
+
+ /*
+ * Ensure ce configuration is completed.
+ */
+ mb();
+
pce_dev->ce_dm.chan_ce_in_cmd->complete_func =
_check_probe_done_call_back;
pce_dev->ce_dm.chan_ce_in_cmd->cmdptr =
@@ -2529,4 +2569,4 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Crypto Engine driver");
-MODULE_VERSION("2.11");
+MODULE_VERSION("2.12");
diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c
index dcc98a0..405d021 100644
--- a/drivers/crypto/msm/qcedev.c
+++ b/drivers/crypto/msm/qcedev.c
@@ -1229,6 +1229,7 @@
return qcedev_hmac_final(areq, handle);
}
+#ifdef CONFIG_ANDROID_PMEM
static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
struct qcedev_handle *handle)
{
@@ -1438,6 +1439,13 @@
return err;
}
+#else
+static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq,
+ struct qcedev_handle *handle)
+{
+ return -EPERM;
+}
+#endif/*CONFIG_ANDROID_PMEM*/
static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
int *di, struct qcedev_handle *handle,
@@ -1837,7 +1845,7 @@
podev))
return -EINVAL;
- if (qcedev_areq.cipher_op_req.use_pmem == QCEDEV_USE_PMEM)
+ if (qcedev_areq.cipher_op_req.use_pmem)
err = qcedev_pmem_ablk_cipher(&qcedev_areq, handle);
else
err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
@@ -2156,7 +2164,7 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Qualcomm DEV Crypto driver");
-MODULE_VERSION("1.23");
+MODULE_VERSION("1.24");
module_init(qcedev_init);
module_exit(qcedev_exit);
diff --git a/drivers/gpu/ion/ion_carveout_heap.c b/drivers/gpu/ion/ion_carveout_heap.c
index 44536c8..86d4c8e 100644
--- a/drivers/gpu/ion/ion_carveout_heap.c
+++ b/drivers/gpu/ion/ion_carveout_heap.c
@@ -39,7 +39,8 @@
{
struct ion_carveout_heap *carveout_heap =
container_of(heap, struct ion_carveout_heap, heap);
- unsigned long offset = gen_pool_alloc(carveout_heap->pool, size);
+ unsigned long offset = gen_pool_alloc_aligned(carveout_heap->pool,
+ size, ilog2(align));
if (!offset)
return ION_CARVEOUT_ALLOCATE_FAIL;
diff --git a/drivers/gpu/msm/adreno_postmortem.c b/drivers/gpu/msm/adreno_postmortem.c
index 7c7f0dc..cc69360 100644
--- a/drivers/gpu/msm/adreno_postmortem.c
+++ b/drivers/gpu/msm/adreno_postmortem.c
@@ -25,6 +25,7 @@
#include "a2xx_reg.h"
#define INVALID_RB_CMD 0xaaaaaaaa
+#define NUM_DWORDS_OF_RINGBUFFER_HISTORY 100
struct pm_id_name {
uint32_t id;
@@ -536,7 +537,12 @@
kgsl_regread(device, REG_CP_RB_RPTR_ADDR, &r3);
KGSL_LOG_DUMP(device,
"CP_RB: BASE = %08X | CNTL = %08X | RPTR_ADDR = %08X"
- "\n", cp_rb_base, r2, r3);
+ " | rb_count = %08X\n", cp_rb_base, r2, r3, rb_count);
+ {
+ struct adreno_ringbuffer *rb = &adreno_dev->ringbuffer;
+ if (rb->sizedwords != rb_count)
+ rb_count = rb->sizedwords;
+ }
kgsl_regread(device, REG_CP_RB_RPTR, &cp_rb_rptr);
kgsl_regread(device, REG_CP_RB_WPTR, &cp_rb_wptr);
@@ -683,13 +689,13 @@
goto error_vfree;
}
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
write_idx = (int)cp_rb_wptr + 16;
if (write_idx > rb_count)
write_idx -= rb_count;
- num_item += 64+16;
+ num_item += NUM_DWORDS_OF_RINGBUFFER_HISTORY+16;
if (num_item > rb_count)
num_item = rb_count;
if (write_idx >= read_idx)
@@ -736,7 +742,7 @@
the process in whose context the GPU hung */
cur_pt_base = pt_base;
- read_idx = (int)cp_rb_rptr - 64;
+ read_idx = (int)cp_rb_rptr - NUM_DWORDS_OF_RINGBUFFER_HISTORY;
if (read_idx < 0)
read_idx += rb_count;
KGSL_LOG_DUMP(device,
@@ -745,13 +751,14 @@
adreno_dump_rb(device, rb_copy, num_item<<2, read_idx, rb_count);
if (adreno_ib_dump_enabled()) {
- for (read_idx = 64; read_idx >= 0; --read_idx) {
+ for (read_idx = NUM_DWORDS_OF_RINGBUFFER_HISTORY;
+ read_idx >= 0; --read_idx) {
uint32_t this_cmd = rb_copy[read_idx];
if (this_cmd == cp_type3_packet(
CP_INDIRECT_BUFFER_PFD, 2)) {
uint32_t ib_addr = rb_copy[read_idx+1];
uint32_t ib_size = rb_copy[read_idx+2];
- if (cp_ib1_bufsz && cp_ib1_base == ib_addr) {
+ if (ib_size && cp_ib1_base == ib_addr) {
KGSL_LOG_DUMP(device,
"IB1: base:%8.8X "
"count:%d\n", ib_addr, ib_size);
@@ -762,9 +769,9 @@
}
}
for (i = 0; i < ib_list.count; ++i) {
- if (cp_ib2_bufsz && cp_ib2_base == ib_list.bases[i]) {
- uint32_t ib_size = ib_list.sizes[i];
- uint32_t ib_offset = ib_list.offsets[i];
+ uint32_t ib_size = ib_list.sizes[i];
+ uint32_t ib_offset = ib_list.offsets[i];
+ if (ib_size && cp_ib2_base == ib_list.bases[i]) {
KGSL_LOG_DUMP(device,
"IB2: base:%8.8X count:%d\n",
cp_ib2_base, ib_size);
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 115f073..84f2b33 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -18,6 +18,11 @@
#include "kgsl_pwrscale.h"
#include "kgsl_device.h"
+#define KGSL_PWRFLAGS_POWER_ON 0
+#define KGSL_PWRFLAGS_CLK_ON 1
+#define KGSL_PWRFLAGS_AXI_ON 2
+#define KGSL_PWRFLAGS_IRQ_ON 3
+
#define GPU_SWFI_LATENCY 3
#define UPDATE_BUSY_VAL 1000000
#define UPDATE_BUSY 50
@@ -577,7 +582,8 @@
idle_check_ws);
mutex_lock(&device->mutex);
- if (device->requested_state != KGSL_STATE_SLEEP)
+ if (device->ftbl->isidle(device) &&
+ (device->requested_state != KGSL_STATE_SLEEP))
kgsl_pwrscale_idle(device);
if (device->state & (KGSL_STATE_ACTIVE | KGSL_STATE_NAP)) {
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 794a895..127a19b 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -16,11 +16,6 @@
/*****************************************************************************
** power flags
*****************************************************************************/
-#define KGSL_PWRFLAGS_POWER_ON 0
-#define KGSL_PWRFLAGS_CLK_ON 1
-#define KGSL_PWRFLAGS_AXI_ON 2
-#define KGSL_PWRFLAGS_IRQ_ON 3
-
#define KGSL_PWRFLAGS_ON 1
#define KGSL_PWRFLAGS_OFF 0
diff --git a/drivers/gpu/msm/kgsl_pwrscale_idlestats.c b/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
index c4dcb22..d5fa84e 100644
--- a/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
+++ b/drivers/gpu/msm/kgsl_pwrscale_idlestats.c
@@ -14,18 +14,52 @@
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/idle_stats_device.h>
+#include <linux/cpufreq.h>
+#include <linux/notifier.h>
+#include <linux/cpumask.h>
+#include <linux/tick.h>
#include "kgsl.h"
#include "kgsl_pwrscale.h"
#include "kgsl_device.h"
+#define MAX_CORES 4
+struct _cpu_info {
+ spinlock_t lock;
+ struct notifier_block cpu_nb;
+ u64 start[MAX_CORES];
+ u64 end[MAX_CORES];
+ int curr_freq[MAX_CORES];
+ int max_freq[MAX_CORES];
+};
+
struct idlestats_priv {
char name[32];
struct msm_idle_stats_device idledev;
struct kgsl_device *device;
struct msm_idle_pulse pulse;
+ struct _cpu_info cpu_info;
};
+static int idlestats_cpufreq_notifier(
+ struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct _cpu_info *cpu = container_of(nb,
+ struct _cpu_info, cpu_nb);
+ struct cpufreq_freqs *freq = data;
+
+ if (val != CPUFREQ_POSTCHANGE)
+ return 0;
+
+ spin_lock(&cpu->lock);
+ if (freq->cpu < num_possible_cpus())
+ cpu->curr_freq[freq->cpu] = freq->new / 1000;
+ spin_unlock(&cpu->lock);
+
+ return 0;
+}
+
static void idlestats_get_sample(struct msm_idle_stats_device *idledev,
struct msm_idle_pulse *pulse)
{
@@ -55,14 +89,37 @@
struct kgsl_pwrscale *pwrscale)
{
struct idlestats_priv *priv = pwrscale->priv;
- if (priv->pulse.busy_start_time != 0)
+ int i, busy, nr_cpu = 1;
+
+ if (priv->pulse.busy_start_time != 0) {
+ priv->pulse.wait_interval = 0;
+ /* Calculate the total CPU busy time for this GPU pulse */
+ for (i = 0; i < num_possible_cpus(); i++) {
+ spin_lock(&priv->cpu_info.lock);
+ if (cpu_online(i)) {
+ priv->cpu_info.end[i] =
+ (u64)ktime_to_us(ktime_get()) -
+ get_cpu_idle_time_us(i, NULL);
+ busy = priv->cpu_info.end[i] -
+ priv->cpu_info.start[i];
+ /* Normalize the busy time by frequency */
+ busy = priv->cpu_info.curr_freq[i] *
+ (busy / priv->cpu_info.max_freq[i]);
+ priv->pulse.wait_interval += busy;
+ nr_cpu++;
+ }
+ spin_unlock(&priv->cpu_info.lock);
+ }
+ priv->pulse.wait_interval /= nr_cpu;
msm_idle_stats_idle_end(&priv->idledev, &priv->pulse);
+ }
priv->pulse.busy_start_time = ktime_to_us(ktime_get());
}
static void idlestats_idle(struct kgsl_device *device,
struct kgsl_pwrscale *pwrscale)
{
+ int i, nr_cpu;
struct kgsl_power_stats stats;
struct idlestats_priv *priv = pwrscale->priv;
@@ -78,15 +135,29 @@
}
priv->pulse.busy_interval = stats.busy_time;
- priv->pulse.wait_interval = 0;
+ nr_cpu = num_possible_cpus();
+ for (i = 0; i < nr_cpu; i++)
+ if (cpu_online(i))
+ priv->cpu_info.start[i] =
+ (u64)ktime_to_us(ktime_get()) -
+ get_cpu_idle_time_us(i, NULL);
+
msm_idle_stats_idle_start(&priv->idledev);
}
+static void idlestats_sleep(struct kgsl_device *device,
+ struct kgsl_pwrscale *pwrscale)
+{
+ struct idlestats_priv *priv = pwrscale->priv;
+ priv->idledev.stats->event |= MSM_IDLE_STATS_EVENT_IDLE_TIMER_EXPIRED;
+}
+
static int idlestats_init(struct kgsl_device *device,
struct kgsl_pwrscale *pwrscale)
{
struct idlestats_priv *priv;
- int ret;
+ struct cpufreq_policy cpu_policy;
+ int ret, i;
priv = pwrscale->priv = kzalloc(sizeof(struct idlestats_priv),
GFP_KERNEL);
@@ -101,8 +172,21 @@
priv->idledev.name = (const char *) priv->name;
priv->idledev.get_sample = idlestats_get_sample;
+ spin_lock_init(&priv->cpu_info.lock);
+ priv->cpu_info.cpu_nb.notifier_call =
+ idlestats_cpufreq_notifier;
+ ret = cpufreq_register_notifier(&priv->cpu_info.cpu_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ if (ret)
+ goto err;
+ for (i = 0; i < num_possible_cpus(); i++) {
+ cpufreq_frequency_table_cpuinfo(&cpu_policy,
+ cpufreq_frequency_get_table(i));
+ priv->cpu_info.max_freq[i] = cpu_policy.max / 1000;
+ priv->cpu_info.curr_freq[i] = cpu_policy.max / 1000;
+ }
ret = msm_idle_stats_register_device(&priv->idledev);
-
+err:
if (ret) {
kfree(pwrscale->priv);
pwrscale->priv = NULL;
@@ -119,6 +203,8 @@
if (pwrscale->priv == NULL)
return;
+ cpufreq_unregister_notifier(&priv->cpu_info.cpu_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
msm_idle_stats_deregister_device(&priv->idledev);
kfree(pwrscale->priv);
@@ -130,5 +216,6 @@
.init = idlestats_init,
.idle = idlestats_idle,
.busy = idlestats_busy,
+ .sleep = idlestats_sleep,
.close = idlestats_close
};
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index 61a3edb..6cd57b3 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -565,7 +565,7 @@
z180_cmdstream_start(device);
mod_timer(&device->idle_timer, jiffies + FIRST_TIMEOUT);
- kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_IRQ_ON);
+ kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_ON);
return 0;
error_clk_off:
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index f9d671e..f3cd0ad 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -797,6 +797,15 @@
The driver supports reading the HKADC, XOADC and support to set and receive
temperature threshold notifications using the Battery temperature module.
+config SENSORS_PM8XXX_ADC
+ tristate "Support for Qualcomm PM8XXX ADC"
+ depends on MFD_PM8018_CORE
+ help
+ This is the ADC arbiter driver for Qualcomm PM8XXX Chip.
+
+ The driver supports reading the HKADC, XOADC and support to set and receive
+ temperature threshold notifications using the Battery temperature module.
+
config SENSORS_PC87360
tristate "National Semiconductor PC87360 family"
select HWMON_VID
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index c25ffcb..10d0699 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -121,6 +121,7 @@
obj-$(CONFIG_SENSORS_WPCE775X) += wpce775x.o
obj-$(CONFIG_SENSORS_MSM_ADC) += msm_adc.o m_adcproc.o
obj-$(CONFIG_SENSORS_PM8921_ADC) += pm8921-adc.o msmproc_adc.o
+obj-$(CONFIG_SENSORS_PM8XXX_ADC) += pm8xxx-adc.o pm8xxx-adc-scale.o
# PMBus drivers
obj-$(CONFIG_PMBUS) += pmbus_core.o
diff --git a/drivers/hwmon/pm8xxx-adc-scale.c b/drivers/hwmon/pm8xxx-adc-scale.c
new file mode 100644
index 0000000..40ade69
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc-scale.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+#define KELVINMIL_DEGMIL 273160
+
+static const struct pm8xxx_adc_map_pt adcmap_batttherm[] = {
+ {41001, -30},
+ {40017, -20},
+ {38721, -10},
+ {37186, 0},
+ {35554, 10},
+ {33980, 20},
+ {33253, 25},
+ {32580, 30},
+ {31412, 40},
+ {30481, 50},
+ {29759, 60},
+ {29209, 70},
+ {28794, 80}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_btm_threshold[] = {
+ {-30, 41001},
+ {-20, 40017},
+ {-10, 38721},
+ {0, 37186},
+ {10, 35554},
+ {11, 35392},
+ {12, 35230},
+ {13, 35070},
+ {14, 34910},
+ {15, 34751},
+ {16, 34594},
+ {17, 34438},
+ {18, 34284},
+ {19, 34131},
+ {20, 33980},
+ {21, 33830},
+ {22, 33683},
+ {23, 33538},
+ {24, 33394},
+ {25, 33253},
+ {26, 33114},
+ {27, 32977},
+ {28, 32842},
+ {29, 32710},
+ {30, 32580},
+ {31, 32452},
+ {32, 32327},
+ {33, 32204},
+ {34, 32084},
+ {35, 31966},
+ {36, 31850},
+ {37, 31737},
+ {38, 31627},
+ {39, 31518},
+ {40, 31412},
+ {41, 31309},
+ {42, 31208},
+ {43, 31109},
+ {44, 31013},
+ {45, 30918},
+ {46, 30827},
+ {47, 30737},
+ {48, 30649},
+ {49, 30564},
+ {50, 30481},
+ {51, 30400},
+ {52, 30321},
+ {53, 30244},
+ {54, 30169},
+ {55, 30096},
+ {56, 30025},
+ {57, 29956},
+ {58, 29889},
+ {59, 29823},
+ {60, 29759},
+ {61, 29697},
+ {62, 29637},
+ {63, 29578},
+ {64, 29521},
+ {65, 29465},
+ {66, 29411},
+ {67, 29359},
+ {68, 29308},
+ {69, 29258},
+ {70, 29209},
+ {71, 29162},
+ {72, 29117},
+ {73, 29072},
+ {74, 29029},
+ {75, 28987},
+ {76, 28946},
+ {77, 28906},
+ {78, 28868},
+ {79, 28830},
+ {80, 28794}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_pa_therm[] = {
+ {41350, -30},
+ {41282, -29},
+ {41211, -28},
+ {41137, -27},
+ {41060, -26},
+ {40980, -25},
+ {40897, -24},
+ {40811, -23},
+ {40721, -22},
+ {40629, -21},
+ {40533, -20},
+ {40434, -19},
+ {40331, -18},
+ {40226, -17},
+ {40116, -16},
+ {40004, -15},
+ {39888, -14},
+ {39769, -13},
+ {39647, -12},
+ {39521, -11},
+ {39392, -10},
+ {39260, -9},
+ {39124, -8},
+ {38986, -7},
+ {38845, -6},
+ {38700, -5},
+ {38553, -4},
+ {38403, -3},
+ {38250, -2},
+ {38094, -1},
+ {37936, 0},
+ {37776, 1},
+ {37613, 2},
+ {37448, 3},
+ {37281, 4},
+ {37112, 5},
+ {36942, 6},
+ {36770, 7},
+ {36596, 8},
+ {36421, 9},
+ {36245, 10},
+ {36068, 11},
+ {35890, 12},
+ {35712, 13},
+ {35532, 14},
+ {35353, 15},
+ {35173, 16},
+ {34993, 17},
+ {34813, 18},
+ {34634, 19},
+ {34455, 20},
+ {34276, 21},
+ {34098, 22},
+ {33921, 23},
+ {33745, 24},
+ {33569, 25},
+ {33395, 26},
+ {33223, 27},
+ {33051, 28},
+ {32881, 29},
+ {32713, 30},
+ {32547, 31},
+ {32382, 32},
+ {32219, 33},
+ {32058, 34},
+ {31899, 35},
+ {31743, 36},
+ {31588, 37},
+ {31436, 38},
+ {31285, 39},
+ {31138, 40},
+ {30992, 41},
+ {30849, 42},
+ {30708, 43},
+ {30570, 44},
+ {30434, 45},
+ {30300, 46},
+ {30169, 47},
+ {30041, 48},
+ {29915, 49},
+ {29791, 50},
+ {29670, 51},
+ {29551, 52},
+ {29435, 53},
+ {29321, 54},
+ {29210, 55},
+ {29101, 56},
+ {28994, 57},
+ {28890, 58},
+ {28788, 59},
+ {28688, 60},
+ {28590, 61},
+ {28495, 62},
+ {28402, 63},
+ {28311, 64},
+ {28222, 65},
+ {28136, 66},
+ {28051, 67},
+ {27968, 68},
+ {27888, 69},
+ {27809, 70},
+ {27732, 71},
+ {27658, 72},
+ {27584, 73},
+ {27513, 74},
+ {27444, 75},
+ {27376, 76},
+ {27310, 77},
+ {27245, 78},
+ {27183, 79},
+ {27121, 80},
+ {27062, 81},
+ {27004, 82},
+ {26947, 83},
+ {26892, 84},
+ {26838, 85},
+ {26785, 86},
+ {26734, 87},
+ {26684, 88},
+ {26636, 89},
+ {26588, 90}
+};
+
+static const struct pm8xxx_adc_map_pt adcmap_ntcg_104ef_104fb[] = {
+ {696483, -40960},
+ {649148, -39936},
+ {605368, -38912},
+ {564809, -37888},
+ {527215, -36864},
+ {492322, -35840},
+ {460007, -34816},
+ {429982, -33792},
+ {402099, -32768},
+ {376192, -31744},
+ {352075, -30720},
+ {329714, -29696},
+ {308876, -28672},
+ {289480, -27648},
+ {271417, -26624},
+ {254574, -25600},
+ {238903, -24576},
+ {224276, -23552},
+ {210631, -22528},
+ {197896, -21504},
+ {186007, -20480},
+ {174899, -19456},
+ {164521, -18432},
+ {154818, -17408},
+ {145744, -16384},
+ {137265, -15360},
+ {129307, -14336},
+ {121866, -13312},
+ {114896, -12288},
+ {108365, -11264},
+ {102252, -10240},
+ {96499, -9216},
+ {91111, -8192},
+ {86055, -7168},
+ {81308, -6144},
+ {76857, -5120},
+ {72660, -4096},
+ {68722, -3072},
+ {65020, -2048},
+ {61538, -1024},
+ {58261, 0},
+ {55177, 1024},
+ {52274, 2048},
+ {49538, 3072},
+ {46962, 4096},
+ {44531, 5120},
+ {42243, 6144},
+ {40083, 7168},
+ {38045, 8192},
+ {36122, 9216},
+ {34308, 10240},
+ {32592, 11264},
+ {30972, 12288},
+ {29442, 13312},
+ {27995, 14336},
+ {26624, 15360},
+ {25333, 16384},
+ {24109, 17408},
+ {22951, 18432},
+ {21854, 19456},
+ {20807, 20480},
+ {19831, 21504},
+ {18899, 22528},
+ {18016, 23552},
+ {17178, 24576},
+ {16384, 25600},
+ {15631, 26624},
+ {14916, 27648},
+ {14237, 28672},
+ {13593, 29696},
+ {12976, 30720},
+ {12400, 31744},
+ {11848, 32768},
+ {11324, 33792},
+ {10825, 34816},
+ {10354, 35840},
+ {9900, 36864},
+ {9471, 37888},
+ {9062, 38912},
+ {8674, 39936},
+ {8306, 40960},
+ {7951, 41984},
+ {7616, 43008},
+ {7296, 44032},
+ {6991, 45056},
+ {6701, 46080},
+ {6424, 47104},
+ {6160, 48128},
+ {5908, 49152},
+ {5667, 50176},
+ {5439, 51200},
+ {5219, 52224},
+ {5010, 53248},
+ {4810, 54272},
+ {4619, 55296},
+ {4440, 56320},
+ {4263, 57344},
+ {4097, 58368},
+ {3938, 59392},
+ {3785, 60416},
+ {3637, 61440},
+ {3501, 62464},
+ {3368, 63488},
+ {3240, 64512},
+ {3118, 65536},
+ {2998, 66560},
+ {2889, 67584},
+ {2782, 68608},
+ {2680, 69632},
+ {2581, 70656},
+ {2490, 71680},
+ {2397, 72704},
+ {2310, 73728},
+ {2227, 74752},
+ {2147, 75776},
+ {2064, 76800},
+ {1998, 77824},
+ {1927, 78848},
+ {1860, 79872},
+ {1795, 80896},
+ {1736, 81920},
+ {1673, 82944},
+ {1615, 83968},
+ {1560, 84992},
+ {1507, 86016},
+ {1456, 87040},
+ {1407, 88064},
+ {1360, 89088},
+ {1314, 90112},
+ {1271, 91136},
+ {1228, 92160},
+ {1189, 93184},
+ {1150, 94208},
+ {1112, 95232},
+ {1076, 96256},
+ {1042, 97280},
+ {1008, 98304},
+ {976, 99328},
+ {945, 100352},
+ {915, 101376},
+ {886, 102400},
+ {859, 103424},
+ {832, 104448},
+ {807, 105472},
+ {782, 106496},
+ {756, 107520},
+ {735, 108544},
+ {712, 109568},
+ {691, 110592},
+ {670, 111616},
+ {650, 112640},
+ {631, 113664},
+ {612, 114688},
+ {594, 115712},
+ {577, 116736},
+ {560, 117760},
+ {544, 118784},
+ {528, 119808},
+ {513, 120832},
+ {498, 121856},
+ {483, 122880},
+ {470, 123904},
+ {457, 124928},
+ {444, 125952},
+ {431, 126976},
+ {419, 128000}
+};
+
+static int32_t pm8xxx_adc_map_linear(const struct pm8xxx_adc_map_pt *pts,
+ uint32_t tablesize, int32_t input, int64_t *output)
+{
+ bool descending = 1;
+ uint32_t i = 0;
+
+ if ((pts == NULL) || (output == NULL))
+ return -EINVAL;
+
+ /* Check if table is descending or ascending */
+ if (tablesize > 1) {
+ if (pts[0].x < pts[1].x)
+ descending = 0;
+ }
+
+ while (i < tablesize) {
+ if ((descending == 1) && (pts[i].x < input)) {
+ /* table entry is less than measured
+ value and table is descending, stop */
+ break;
+ } else if ((descending == 0) &&
+ (pts[i].x > input)) {
+ /* table entry is greater than measured
+ value and table is ascending, stop */
+ break;
+ } else {
+ i++;
+ }
+ }
+
+ if (i == 0)
+ *output = pts[0].y;
+ else if (i == tablesize)
+ *output = pts[tablesize-1].y;
+ else {
+ /* result is between search_index and search_index-1 */
+ /* interpolate linearly */
+ *output = (((int32_t) ((pts[i].y - pts[i-1].y)*
+ (input - pts[i-1].x))/
+ (pts[i].x - pts[i-1].x))+
+ pts[i-1].y);
+ }
+
+ return 0;
+}
+
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ bool negative_rawfromoffset = 0;
+ int32_t rawfromoffset = 0;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ adc_chan_result->adc_code = adc_code;
+ if (rawfromoffset < 0) {
+ if (adc_properties->bipolar) {
+ rawfromoffset = -rawfromoffset;
+ negative_rawfromoffset = 1;
+ } else {
+ rawfromoffset = 0;
+ }
+ }
+
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution) - 1;
+
+ adc_chan_result->measurement = (int64_t)rawfromoffset *
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator;
+
+ /* do_div only perform positive integer division! */
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator);
+
+ if (negative_rawfromoffset)
+ adc_chan_result->measurement = -adc_chan_result->measurement;
+
+ /* Note: adc_chan_result->measurement is in the unit of
+ * adc_properties.adc_reference. For generic channel processing,
+ * channel measurement is a scale/ratio relative to the adc
+ * reference input */
+ adc_chan_result->physical = (int32_t) adc_chan_result->measurement;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_default);
+
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_batttherm,
+ ARRAY_SIZE(adcmap_batttherm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_batt_therm);
+
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->measurement = adc_code;
+ /* convert mV ---> degC using the table */
+ return pm8xxx_adc_map_linear(
+ adcmap_pa_therm,
+ ARRAY_SIZE(adcmap_pa_therm),
+ adc_code,
+ &adc_chan_result->physical);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pa_therm);
+
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rawfromoffset;
+
+ if (!chan_properties || !chan_properties->offset_gain_numerator ||
+ !chan_properties->offset_gain_denominator || !adc_properties
+ || !adc_chan_result)
+ return -EINVAL;
+
+ adc_chan_result->adc_code = adc_code;
+ rawfromoffset = adc_code -
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+ if (rawfromoffset > 0) {
+ if (rawfromoffset >= 1 << adc_properties->bitresolution)
+ rawfromoffset = (1 << adc_properties->bitresolution)
+ - 1;
+ /* 2mV/K */
+ adc_chan_result->measurement = (int64_t)rawfromoffset*
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dx *
+ chan_properties->offset_gain_denominator * 1000;
+
+ do_div(adc_chan_result->measurement,
+ chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].dy *
+ chan_properties->offset_gain_numerator*2);
+ } else {
+ adc_chan_result->measurement = 0;
+ }
+ /* Note: adc_chan_result->measurement is in the unit of
+ adc_properties.adc_reference */
+ adc_chan_result->physical = (int32_t)adc_chan_result->measurement;
+ /* Change to .001 deg C */
+ adc_chan_result->physical -= KELVINMIL_DEGMIL;
+ adc_chan_result->measurement <<= 1;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_scale_pmic_therm);
+
+/* Scales the ADC code to 0.001 degrees C using the map
+ * table for the XO thermistor.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_properties,
+ const struct pm8xxx_adc_chan_properties *chan_properties,
+ struct pm8xxx_adc_chan_result *adc_chan_result)
+{
+ int32_t rt_r25;
+ int32_t offset = chan_properties->adc_graph[ADC_CALIB_ABSOLUTE].offset;
+
+ rt_r25 = adc_code - offset;
+
+ pm8xxx_adc_map_linear(adcmap_ntcg_104ef_104fb,
+ ARRAY_SIZE(adcmap_ntcg_104ef_104fb),
+ rt_r25, &adc_chan_result->physical);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_tdkntcg_therm);
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ int rc;
+
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->low_thr_temp,
+ &btm_param->low_thr_voltage);
+
+ if (!rc) {
+ rc = pm8xxx_adc_map_linear(
+ adcmap_btm_threshold,
+ ARRAY_SIZE(adcmap_btm_threshold),
+ btm_param->high_thr_temp,
+ &btm_param->high_thr_voltage);
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_batt_scaler);
diff --git a/drivers/hwmon/pm8xxx-adc.c b/drivers/hwmon/pm8xxx-adc.c
new file mode 100644
index 0000000..152eb40
--- /dev/null
+++ b/drivers/hwmon/pm8xxx-adc.c
@@ -0,0 +1,1286 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Qualcomm's PM8921/PM8018 ADC Arbiter driver
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/hwmon.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/wakelock.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
+
+/* User Bank register set */
+#define PM8XXX_ADC_ARB_USRP_CNTRL1 0x197
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB BIT(0)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV2 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV3 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV4 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_RSV5 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_USRP_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL 0x198
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_PREMUX1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_ANA_PARAM 0x199
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM 0x19A
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_RSV 0x19B
+#define PM8XXX_ADC_ARB_USRP_RSV_RST BIT(0)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST0 BIT(1)
+#define PM8XXX_ADC_ARB_USRP_RSV_DTEST1 BIT(2)
+#define PM8XXX_ADC_ARB_USRP_RSV_OP BIT(3)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
+#define PM8XXX_ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
+#define PM8XXX_ADC_ARB_USRP_RSV_TRM BIT(7)
+
+#define PM8XXX_ADC_ARB_USRP_DATA0 0x19D
+#define PM8XXX_ADC_ARB_USRP_DATA1 0x19C
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL1 0x17e
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_EOC BIT(6)
+#define PM8XXX_ADC_ARB_BTM_CNTRL1_REQ BIT(7)
+
+#define PM8XXX_ADC_ARB_BTM_CNTRL2 0x18c
+#define PM8XXX_ADC_ARB_BTM_AMUX_CNTRL 0x17f
+#define PM8XXX_ADC_ARB_BTM_ANA_PARAM 0x180
+#define PM8XXX_ADC_ARB_BTM_DIG_PARAM 0x181
+#define PM8XXX_ADC_ARB_BTM_RSV 0x182
+#define PM8XXX_ADC_ARB_BTM_DATA1 0x183
+#define PM8XXX_ADC_ARB_BTM_DATA0 0x184
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1 0x185
+#define PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0 0x186
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1 0x187
+#define PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0 0x188
+
+#define PM8XXX_ADC_ARB_ANA_DIG 0xa0
+#define PM8XXX_ADC_BTM_RSV 0x10
+#define PM8XXX_ADC_AMUX_MPP_SEL 2
+#define PM8XXX_ADC_AMUX_SEL 4
+#define PM8XXX_ADC_RSV_IP_SEL 4
+#define PM8XXX_ADC_BTM_CHANNEL_SEL 4
+#define PM8XXX_MAX_CHANNEL_PROPERTIES 2
+#define PM8XXX_ADC_IRQ_0 0
+#define PM8XXX_ADC_IRQ_1 1
+#define PM8XXX_ADC_IRQ_2 2
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_MASK 0xF
+#define PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT 2
+#define PM8XXX_ADC_BTM_DECIMATION_SEL 5
+#define PM8XXX_ADC_MUL 10
+#define PM8XXX_ADC_CONV_TIME_MIN 2000
+#define PM8XXX_ADC_CONV_TIME_MAX 2100
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MIN 200
+#define PM8XXX_ADC_MPP_SETTLE_TIME_MAX 200
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MIN 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UV_MAX 1800000
+#define PM8XXX_ADC_PA_THERM_VREG_UA_LOAD 100000
+
+struct pm8xxx_adc {
+ struct device *dev;
+ struct pm8xxx_adc_properties *adc_prop;
+ int adc_irq;
+ struct mutex adc_lock;
+ struct mutex mpp_adc_lock;
+ spinlock_t btm_lock;
+ uint32_t adc_num_channel;
+ uint32_t adc_num_board_channel;
+ struct completion adc_rslt_completion;
+ struct pm8xxx_adc_amux *adc_channel;
+ int btm_warm_irq;
+ int btm_cool_irq;
+ struct dentry *dent;
+ struct work_struct warm_work;
+ struct work_struct cool_work;
+ uint32_t mpp_base;
+ struct device *hwmon;
+ struct wake_lock adc_wakelock;
+ int msm_suspend_check;
+ struct pm8xxx_adc_amux_properties *conv;
+ struct pm8xxx_adc_arb_btm_param batt[0];
+ struct sensor_device_attribute sens_attr[0];
+};
+
+struct pm8xxx_adc_amux_properties {
+ uint32_t amux_channel;
+ uint32_t decimation;
+ uint32_t amux_ip_rsv;
+ uint32_t amux_mpp_channel;
+ struct pm8xxx_adc_chan_properties chan_prop[0];
+};
+
+static const struct pm8xxx_adc_scaling_ratio pm8xxx_amux_scaling_ratio[] = {
+ {1, 1},
+ {1, 3},
+ {1, 4},
+ {1, 6}
+};
+
+static struct pm8xxx_adc *pmic_adc;
+
+static struct pm8xxx_adc_scale_fn adc_scale_fn[] = {
+ [ADC_SCALE_DEFAULT] = {pm8xxx_adc_scale_default},
+ [ADC_SCALE_BATT_THERM] = {pm8xxx_adc_scale_batt_therm},
+ [ADC_SCALE_PA_THERM] = {pm8xxx_adc_scale_pa_therm},
+ [ADC_SCALE_PMIC_THERM] = {pm8xxx_adc_scale_pmic_therm},
+ [ADC_SCALE_XOTHERM] = {pm8xxx_adc_tdkntcg_therm},
+};
+
+/* On PM8921 ADC the MPP needs to first be configured
+as an analog input to the AMUX pre-mux channel before
+issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+and is common between remote processor's.
+On PM8018 ADC the MPP is directly connected to the AMUX
+pre-mux. Therefore clients of the PM8018 MPP do not need
+to configure the MPP as an analog input to the pre-mux.
+Clients can directly issue request on the pre-mux AMUX
+channel to read the ADC on the MPP */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_config = {
+ .type = PM8XXX_MPP_TYPE_A_INPUT,
+ /* AMUX6 is dedicated to be used for apps processor */
+ .level = PM8XXX_MPP_AIN_AMUX_CH6,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+/* MPP Configuration for default settings */
+static struct pm8xxx_mpp_config_data pm8xxx_adc_mpp_unconfig = {
+ .type = PM8XXX_MPP_TYPE_SINK,
+ .level = PM8XXX_MPP_AIN_AMUX_CH5,
+ .control = PM8XXX_MPP_AOUT_CTRL_DISABLE,
+};
+
+static bool pm8xxx_adc_calib_first_adc;
+static bool pm8xxx_adc_initialized, pm8xxx_adc_calib_device_init;
+
+static int32_t pm8xxx_adc_arb_cntrl(uint32_t arb_cntrl,
+ uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_cntrl = 0;
+
+ if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("PM8xxx ADC request made after suspend_noirq "
+ "with channel: %d\n", channel);
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB;
+ wake_lock(&adc_pmic->adc_wakelock);
+ }
+
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ if (rc < 0) {
+ pr_err("PM8xxx arb cntrl write failed with %d\n", rc);
+ return rc;
+ }
+ }
+
+ if (arb_cntrl) {
+ data_arb_cntrl |= PM8XXX_ADC_ARB_USRP_CNTRL1_REQ;
+ rc = pm8xxx_writeb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_CNTRL1, data_arb_cntrl);
+ } else
+ wake_unlock(&adc_pmic->adc_wakelock);
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_patherm_power(bool on)
+{
+ static struct regulator *pa_therm;
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+ if (on) {
+ pa_therm = regulator_get(adc_pmic->dev,
+ "pa_therm");
+ if (IS_ERR(pa_therm)) {
+ rc = PTR_ERR(pa_therm);
+ pr_err("failed to request pa_therm vreg "
+ "with error %d\n", rc);
+ return rc;
+ }
+
+ rc = regulator_set_voltage(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MIN,
+ PM8XXX_ADC_PA_THERM_VREG_UV_MAX);
+ if (rc < 0) {
+ pr_err("failed to set the voltage for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ rc = regulator_set_optimum_mode(pa_therm,
+ PM8XXX_ADC_PA_THERM_VREG_UA_LOAD);
+ if (rc < 0) {
+ pr_err("failed to set optimum mode for "
+ "pa_therm with error %d\n", rc);
+ goto fail;
+ }
+
+ if (regulator_enable(pa_therm)) {
+ pr_err("failed to enable pa_therm vreg with "
+ "error %d\n", rc);
+ goto fail;
+ }
+ } else {
+ if (pa_therm != NULL) {
+ regulator_disable(pa_therm);
+ regulator_put(pa_therm);
+ }
+ }
+
+ return rc;
+fail:
+ regulator_put(pa_therm);
+ return rc;
+}
+
+static int32_t pm8xxx_adc_channel_power_enable(uint32_t channel,
+ bool power_cntrl)
+{
+ int rc = 0;
+
+ switch (channel)
+ case ADC_MPP_1_AMUX8:
+ pm8xxx_adc_patherm_power(power_cntrl);
+
+ return rc;
+}
+
+
+static uint32_t pm8xxx_adc_read_reg(uint32_t reg, u8 *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc read reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_write_reg(uint32_t reg, u8 data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc;
+
+ rc = pm8xxx_writeb(adc_pmic->dev->parent, reg, data);
+ if (rc < 0) {
+ pr_err("PM8xxx adc write reg %d failed with %d\n", reg, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int32_t pm8xxx_adc_configure(
+ struct pm8xxx_adc_amux_properties *chan_prop)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_amux_chan = 0, data_arb_rsv = 0, data_dig_param = 0;
+ int rc;
+
+ data_amux_chan |= chan_prop->amux_channel << PM8XXX_ADC_AMUX_SEL;
+
+ if (chan_prop->amux_mpp_channel)
+ data_amux_chan |= chan_prop->amux_mpp_channel <<
+ PM8XXX_ADC_AMUX_MPP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_AMUX_CNTRL,
+ data_amux_chan);
+ if (rc < 0)
+ return rc;
+
+ data_arb_rsv &= (PM8XXX_ADC_ARB_USRP_RSV_RST |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST0 |
+ PM8XXX_ADC_ARB_USRP_RSV_DTEST1 |
+ PM8XXX_ADC_ARB_USRP_RSV_OP |
+ PM8XXX_ADC_ARB_USRP_RSV_TRM);
+ data_arb_rsv |= chan_prop->amux_ip_rsv << PM8XXX_ADC_RSV_IP_SEL;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_RSV, data_arb_rsv);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ &data_dig_param);
+ if (rc < 0)
+ return rc;
+
+ /* Default 2.4Mhz clock rate */
+ /* Client chooses the decimation */
+ switch (chan_prop->decimation) {
+ case ADC_DECIMATION_TYPE1:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ case ADC_DECIMATION_TYPE2:
+ data_dig_param |= (PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0
+ | PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE1);
+ break;
+ default:
+ data_dig_param |= PM8XXX_ADC_ARB_USRP_DIG_PARAM_DEC_RATE0;
+ break;
+ }
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_DIG_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_USRP_ANA_PARAM,
+ PM8XXX_ADC_ARB_ANA_DIG);
+ if (rc < 0)
+ return rc;
+
+ if (!pm8xxx_adc_calib_first_adc)
+ enable_irq(adc_pmic->adc_irq);
+
+ rc = pm8xxx_adc_arb_cntrl(1, data_amux_chan);
+ if (rc < 0) {
+ pr_err("Configuring ADC Arbiter"
+ "enable failed with %d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static uint32_t pm8xxx_adc_read_adc_code(int32_t *data)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ uint8_t rslt_lsb, rslt_msb;
+ int32_t rc, max_ideal_adc_code = 1 << adc_pmic->adc_prop->bitresolution;
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA0, &rslt_lsb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(adc_pmic->dev->parent,
+ PM8XXX_ADC_ARB_USRP_DATA1, &rslt_msb);
+ if (rc < 0) {
+ pr_err("PM8xxx adc result read failed with %d\n", rc);
+ return rc;
+ }
+
+ *data = (rslt_msb << 8) | rslt_lsb;
+
+ /* Use the midpoint to determine underflow or overflow */
+ if (*data > max_ideal_adc_code + (max_ideal_adc_code >> 1))
+ *data |= ((1 << (8 * sizeof(*data) -
+ adc_pmic->adc_prop->bitresolution)) - 1) <<
+ adc_pmic->adc_prop->bitresolution;
+
+ /* Default value for switching off the arbiter after reading
+ the ADC value. Bit 0 set to 0. */
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void pm8xxx_adc_btm_warm_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ warm_work);
+ unsigned long flags = 0;
+ bool warm_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ warm_status = irq_read_line(adc_pmic->btm_warm_irq);
+ if (adc_pmic->batt->btm_warm_fn != NULL)
+ adc_pmic->batt->btm_warm_fn(warm_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static void pm8xxx_adc_btm_cool_scheduler_fn(struct work_struct *work)
+{
+ struct pm8xxx_adc *adc_pmic = container_of(work, struct pm8xxx_adc,
+ cool_work);
+ unsigned long flags = 0;
+ bool cool_status;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ cool_status = irq_read_line(adc_pmic->btm_cool_irq);
+ if (adc_pmic->batt->btm_cool_fn != NULL)
+ adc_pmic->batt->btm_cool_fn(cool_status);
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+}
+
+static irqreturn_t pm8xxx_adc_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *adc_8xxx = dev_id;
+
+ disable_irq_nosync(adc_8xxx->adc_irq);
+
+ if (pm8xxx_adc_calib_first_adc)
+ return IRQ_HANDLED;
+ /* TODO Handle spurius interrupt condition */
+ complete(&adc_8xxx->adc_rslt_completion);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_warm_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->warm_work);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t pm8xxx_btm_cool_isr(int irq, void *dev_id)
+{
+ struct pm8xxx_adc *btm_8xxx = dev_id;
+
+ schedule_work(&btm_8xxx->cool_work);
+
+ return IRQ_HANDLED;
+}
+
+static uint32_t pm8xxx_adc_calib_device(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_amux_properties conv;
+ int rc, offset_adc, slope_adc, calib_read_1, calib_read_2;
+ u8 data_arb_usrp_cntrl1 = 0;
+
+ conv.amux_channel = CHANNEL_125V;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_625MV;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV1;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ PM8XXX_CHANNEL_ADC_625_MV);
+ offset_adc = calib_read_2 -
+ ((slope_adc * PM8XXX_CHANNEL_ADC_625_MV) >>
+ PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_ABSOLUTE].dx
+ = PM8XXX_CHANNEL_ADC_625_MV;
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ return rc;
+ }
+ /* Ratiometric Calibration */
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV5;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_1);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ conv.amux_channel = CHANNEL_MUXOFF;
+ conv.decimation = ADC_DECIMATION_TYPE2;
+ conv.amux_ip_rsv = AMUX_RSV4;
+ conv.amux_mpp_channel = PREMUX_MPP_SCALE_0;
+ pm8xxx_adc_calib_first_adc = true;
+ rc = pm8xxx_adc_configure(&conv);
+ if (rc) {
+ pr_err("pm8xxx_adc configure failed with %d\n", rc);
+ goto calib_fail;
+ }
+
+ while (data_arb_usrp_cntrl1 != (PM8XXX_ADC_ARB_USRP_CNTRL1_EOC |
+ PM8XXX_ADC_ARB_USRP_CNTRL1_EN_ARB)) {
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_USRP_CNTRL1,
+ &data_arb_usrp_cntrl1);
+ if (rc < 0)
+ return rc;
+ usleep_range(PM8XXX_ADC_CONV_TIME_MIN,
+ PM8XXX_ADC_CONV_TIME_MAX);
+ }
+ data_arb_usrp_cntrl1 = 0;
+
+ rc = pm8xxx_adc_read_adc_code(&calib_read_2);
+ if (rc) {
+ pr_err("pm8xxx_adc read adc failed with %d\n", rc);
+ pm8xxx_adc_calib_first_adc = false;
+ goto calib_fail;
+ }
+ pm8xxx_adc_calib_first_adc = false;
+
+ slope_adc = (((calib_read_1 - calib_read_2) << PM8XXX_ADC_MUL)/
+ adc_pmic->adc_prop->adc_vdd_reference);
+ offset_adc = calib_read_2 -
+ ((slope_adc * adc_pmic->adc_prop->adc_vdd_reference)
+ >> PM8XXX_ADC_MUL);
+
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].offset
+ = offset_adc;
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dy =
+ (calib_read_1 - calib_read_2);
+ adc_pmic->conv->chan_prop->adc_graph[ADC_CALIB_RATIOMETRIC].dx =
+ adc_pmic->adc_prop->adc_vdd_reference;
+calib_fail:
+ rc = pm8xxx_adc_arb_cntrl(0, CHANNEL_NONE);
+ if (rc < 0) {
+ pr_err("%s: Configuring ADC Arbiter disable"
+ "failed\n", __func__);
+ }
+
+ return rc;
+}
+
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i = 0, rc = 0, rc_fail, amux_prescaling, scale_type;
+ enum pm8xxx_adc_premux_mpp_scale_type mpp_scale;
+
+ if (!pm8xxx_adc_initialized)
+ return -ENODEV;
+
+ if (!pm8xxx_adc_calib_device_init) {
+ if (pm8xxx_adc_calib_device() == 0)
+ pm8xxx_adc_calib_device_init = true;
+ }
+
+ mutex_lock(&adc_pmic->adc_lock);
+
+ for (i = 0; i < adc_pmic->adc_num_channel; i++) {
+ if (channel == adc_pmic->adc_channel[i].channel_name)
+ break;
+ }
+
+ if (i == adc_pmic->adc_num_channel) {
+ rc = -EBADF;
+ goto fail_unlock;
+ }
+
+ if (channel < PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_0;
+ adc_pmic->conv->amux_channel = channel;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE1_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE1_IDX;
+ } else if (channel >= PM8XXX_CHANNEL_MPP_SCALE3_IDX) {
+ mpp_scale = PREMUX_MPP_SCALE_1_DIV3;
+ adc_pmic->conv->amux_channel = channel %
+ PM8XXX_CHANNEL_MPP_SCALE3_IDX;
+ }
+
+ adc_pmic->conv->amux_mpp_channel = mpp_scale;
+ adc_pmic->conv->amux_ip_rsv = adc_pmic->adc_channel[i].adc_rsv;
+ adc_pmic->conv->decimation = adc_pmic->adc_channel[i].adc_decimation;
+ amux_prescaling = adc_pmic->adc_channel[i].chan_path_prescaling;
+
+ adc_pmic->conv->chan_prop->offset_gain_numerator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].num;
+ adc_pmic->conv->chan_prop->offset_gain_denominator =
+ pm8xxx_amux_scaling_ratio[amux_prescaling].den;
+
+ rc = pm8xxx_adc_channel_power_enable(channel, true);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ rc = pm8xxx_adc_configure(adc_pmic->conv);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ wait_for_completion(&adc_pmic->adc_rslt_completion);
+
+ rc = pm8xxx_adc_read_adc_code(&result->adc_code);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ scale_type = adc_pmic->adc_channel[i].adc_scale_fn;
+ if (scale_type >= ADC_SCALE_NONE) {
+ rc = -EBADF;
+ goto fail;
+ }
+
+ adc_scale_fn[scale_type].chan(result->adc_code,
+ adc_pmic->adc_prop, adc_pmic->conv->chan_prop, result);
+
+ rc = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc) {
+ rc = -EINVAL;
+ goto fail_unlock;
+ }
+
+ mutex_unlock(&adc_pmic->adc_lock);
+
+ return 0;
+fail:
+ rc_fail = pm8xxx_adc_channel_power_enable(channel, false);
+ if (rc_fail)
+ pr_err("pm8xxx adc power disable failed\n");
+fail_unlock:
+ mutex_unlock(&adc_pmic->adc_lock);
+ pr_err("pm8xxx adc error with %d\n", rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_read);
+
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0;
+
+ if (!adc_pmic->mpp_base) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP base invalid with error %d\n", rc);
+ return rc;
+ }
+
+ if (mpp_num == PM8XXX_AMUX_MPP_8) {
+ rc = -EINVAL;
+ pr_info("PM8xxx MPP8 is already configured "
+ "to AMUX8. Use pm8xxx_adc_read() instead.\n");
+ return rc;
+ }
+
+ mutex_lock(&adc_pmic->mpp_adc_lock);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_config);
+ if (rc < 0) {
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+ goto fail;
+ }
+
+ usleep_range(PM8XXX_ADC_MPP_SETTLE_TIME_MIN,
+ PM8XXX_ADC_MPP_SETTLE_TIME_MAX);
+
+ rc = pm8xxx_adc_read(channel, result);
+ if (rc < 0)
+ pr_err("pm8xxx adc read error with %d\n", rc);
+
+ rc = pm8xxx_mpp_config(((mpp_num - 1) + adc_pmic->mpp_base),
+ &pm8xxx_adc_mpp_unconfig);
+ if (rc < 0)
+ pr_err("pm8xxx adc mpp config error with %d\n", rc);
+fail:
+ mutex_unlock(&adc_pmic->mpp_adc_lock);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_mpp_config_read);
+
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *btm_param)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ u8 data_btm_cool_thr0, data_btm_cool_thr1;
+ u8 data_btm_warm_thr0, data_btm_warm_thr1;
+ u8 arb_btm_cntrl1;
+ unsigned long flags = 0;
+ int rc;
+
+ if (adc_pmic == NULL) {
+ pr_err("PMIC ADC not valid\n");
+ return -EINVAL;
+ }
+
+ if ((btm_param->btm_cool_fn == NULL) &&
+ (btm_param->btm_warm_fn == NULL)) {
+ pr_err("No BTM warm/cool notification??\n");
+ return -EINVAL;
+ }
+
+ rc = pm8xxx_adc_batt_scaler(btm_param);
+ if (rc < 0) {
+ pr_err("Failed to lookup the BTM thresholds\n");
+ return rc;
+ }
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ data_btm_cool_thr0 = ((btm_param->low_thr_voltage << 24) >> 24);
+ data_btm_cool_thr1 = ((btm_param->low_thr_voltage << 16) >> 24);
+ data_btm_warm_thr0 = ((btm_param->high_thr_voltage << 24) >> 24);
+ data_btm_warm_thr1 = ((btm_param->high_thr_voltage << 16) >> 24);
+
+ if (btm_param->btm_cool_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR0,
+ data_btm_cool_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_COOL_THR1,
+ data_btm_cool_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_cool_fn = btm_param->btm_cool_fn;
+ }
+
+ if (btm_param->btm_warm_fn != NULL) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR0,
+ data_btm_warm_thr0);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_BAT_WARM_THR1,
+ data_btm_warm_thr1);
+ if (rc < 0)
+ goto write_err;
+
+ adc_pmic->batt->btm_warm_fn = btm_param->btm_warm_fn;
+ }
+
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, &arb_btm_cntrl1);
+ if (rc < 0)
+ goto bail_out;
+
+ btm_param->interval &= PM8XXX_ADC_BTM_INTERVAL_SEL_MASK;
+ arb_btm_cntrl1 |=
+ btm_param->interval << PM8XXX_ADC_BTM_INTERVAL_SEL_SHIFT;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1, arb_btm_cntrl1);
+ if (rc < 0)
+ goto write_err;
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+bail_out:
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ pr_debug("%s: with error code %d\n", __func__, rc);
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_configure);
+
+static uint32_t pm8xxx_adc_btm_read(uint32_t channel)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc, i;
+ u8 arb_btm_dig_param, arb_btm_ana_param, arb_btm_rsv;
+ u8 arb_btm_amux_cntrl, data_arb_btm_cntrl = 0;
+ unsigned long flags;
+
+ arb_btm_amux_cntrl = channel << PM8XXX_ADC_BTM_CHANNEL_SEL;
+ arb_btm_rsv = adc_pmic->adc_channel[channel].adc_rsv;
+ arb_btm_dig_param = arb_btm_ana_param = PM8XXX_ADC_ARB_ANA_DIG;
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_AMUX_CNTRL,
+ arb_btm_amux_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ arb_btm_rsv = PM8XXX_ADC_BTM_RSV;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_RSV, arb_btm_rsv);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_DIG_PARAM,
+ arb_btm_dig_param);
+ if (rc < 0)
+ goto write_err;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_ANA_PARAM,
+ arb_btm_ana_param);
+ if (rc < 0)
+ goto write_err;
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+ }
+
+ data_arb_btm_cntrl |= PM8XXX_ADC_ARB_BTM_CNTRL1_REQ
+ | PM8XXX_ADC_ARB_BTM_CNTRL1_SEL_OP_MODE;
+
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0)
+ goto write_err;
+
+ if (pmic_adc->batt->btm_warm_fn != NULL)
+ enable_irq(adc_pmic->btm_warm_irq);
+
+ if (pmic_adc->batt->btm_cool_fn != NULL)
+ enable_irq(adc_pmic->btm_cool_irq);
+
+write_err:
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+}
+
+uint32_t pm8xxx_adc_btm_start(void)
+{
+ return pm8xxx_adc_btm_read(CHANNEL_BATT_THERM);
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_start);
+
+uint32_t pm8xxx_adc_btm_end(void)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i, rc;
+ u8 data_arb_btm_cntrl;
+ unsigned long flags;
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+
+ spin_lock_irqsave(&adc_pmic->btm_lock, flags);
+ /* Set BTM registers to Disable mode */
+ rc = pm8xxx_adc_read_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ &data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+
+ data_arb_btm_cntrl |= ~PM8XXX_ADC_ARB_BTM_CNTRL1_EN_BTM;
+ /* Write twice to the CNTRL register for the arbiter settings
+ to take into effect */
+ for (i = 0; i < 2; i++) {
+ rc = pm8xxx_adc_write_reg(PM8XXX_ADC_ARB_BTM_CNTRL1,
+ data_arb_btm_cntrl);
+ if (rc < 0) {
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+ return rc;
+ }
+ }
+
+ spin_unlock_irqrestore(&adc_pmic->btm_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pm8xxx_adc_btm_end);
+
+static ssize_t pm8xxx_adc_show(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ struct pm8xxx_adc_chan_result result;
+ int rc = -1;
+
+ if (attr->index < adc_pmic->adc_num_channel)
+ rc = pm8xxx_adc_read(attr->index, &result);
+
+ if (rc)
+ return 0;
+
+ return snprintf(buf, sizeof(struct pm8xxx_adc_chan_result),
+ "Result:%lld Raw:%d\n",
+ result.physical, result.adc_code);
+}
+
+static int get_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_read(i, &result);
+ if (!rc)
+ pr_info("ADC value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_fops, get_adc, NULL, "%llu\n");
+
+static int get_mpp_adc(void *data, u64 *val)
+{
+ struct pm8xxx_adc_chan_result result;
+ int i = (int)data;
+ int rc;
+
+ rc = pm8xxx_adc_mpp_config_read(i,
+ ADC_MPP_1_AMUX6, &result);
+ if (!rc)
+ pr_info("ADC MPP value raw:%x physical:%lld\n",
+ result.adc_code, result.physical);
+ *val = result.physical;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reg_mpp_fops, get_mpp_adc, NULL, "%llu\n");
+
+#ifdef CONFIG_DEBUG_FS
+static void create_debugfs_entries(void)
+{
+ int i = 0;
+ pmic_adc->dent = debugfs_create_dir("pm8xxx_adc", NULL);
+
+ if (IS_ERR(pmic_adc->dent)) {
+ pr_err("pmic adc debugfs dir not created\n");
+ return;
+ }
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++)
+ debugfs_create_file(pmic_adc->adc_channel[i].name,
+ 0644, pmic_adc->dent,
+ (void *)pmic_adc->adc_channel[i].channel_name,
+ ®_fops);
+}
+#else
+static inline void create_debugfs_entries(void)
+{
+}
+#endif
+static struct sensor_device_attribute pm8xxx_adc_attr =
+ SENSOR_ATTR(NULL, S_IRUGO, pm8xxx_adc_show, NULL, 0);
+
+static int32_t pm8xxx_adc_init_hwmon(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int rc = 0, i;
+
+ for (i = 0; i < pmic_adc->adc_num_board_channel; i++) {
+ pm8xxx_adc_attr.index = adc_pmic->adc_channel[i].channel_name;
+ pm8xxx_adc_attr.dev_attr.attr.name =
+ adc_pmic->adc_channel[i].name;
+ memcpy(&adc_pmic->sens_attr[i], &pm8xxx_adc_attr,
+ sizeof(pm8xxx_adc_attr));
+ rc = device_create_file(&pdev->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ if (rc) {
+ dev_err(&pdev->dev, "device_create_file failed for "
+ "dev %s\n",
+ adc_pmic->adc_channel[i].name);
+ goto hwmon_err_sens;
+ }
+ }
+
+ return 0;
+hwmon_err_sens:
+ pr_info("Init HWMON failed for pm8xxx_adc with %d\n", rc);
+ return rc;
+}
+
+#ifdef CONFIG_PM
+static int pm8xxx_adc_suspend_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8xxx_adc_resume_noirq(struct device *dev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8xxx_adc_dev_pm_ops = {
+ .suspend_noirq = pm8xxx_adc_suspend_noirq,
+ .resume_noirq = pm8xxx_adc_resume_noirq,
+};
+
+#define PM8XXX_ADC_DEV_PM_OPS (&pm8xxx_adc_dev_pm_ops)
+#else
+#define PM8XXX_ADC_DEV_PM_OPS NULL
+#endif
+
+static int __devexit pm8xxx_adc_teardown(struct platform_device *pdev)
+{
+ struct pm8xxx_adc *adc_pmic = pmic_adc;
+ int i;
+
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
+ platform_set_drvdata(pdev, NULL);
+ pmic_adc = NULL;
+ for (i = 0; i < adc_pmic->adc_num_board_channel; i++)
+ device_remove_file(adc_pmic->dev,
+ &adc_pmic->sens_attr[i].dev_attr);
+ pm8xxx_adc_initialized = false;
+
+ return 0;
+}
+
+static int __devinit pm8xxx_adc_probe(struct platform_device *pdev)
+{
+ const struct pm8xxx_adc_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_adc *adc_pmic;
+ struct pm8xxx_adc_amux_properties *adc_amux_prop;
+ int rc = 0;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data?\n");
+ return -EINVAL;
+ }
+
+ adc_pmic = devm_kzalloc(&pdev->dev, sizeof(struct pm8xxx_adc) +
+ sizeof(struct pm8xxx_adc_arb_btm_param) +
+ (sizeof(struct sensor_device_attribute) *
+ pdata->adc_num_board_channel), GFP_KERNEL);
+ if (!adc_pmic) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_amux_prop = devm_kzalloc(&pdev->dev,
+ sizeof(struct pm8xxx_adc_amux_properties) +
+ sizeof(struct pm8xxx_adc_chan_properties)
+ , GFP_KERNEL);
+ if (!adc_amux_prop) {
+ dev_err(&pdev->dev, "Unable to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ adc_pmic->dev = &pdev->dev;
+ adc_pmic->adc_prop = pdata->adc_prop;
+ adc_pmic->conv = adc_amux_prop;
+ init_completion(&adc_pmic->adc_rslt_completion);
+ adc_pmic->adc_channel = pdata->adc_channel;
+ adc_pmic->adc_num_board_channel = pdata->adc_num_board_channel;
+ adc_pmic->adc_num_channel = ADC_MPP_2_CHANNEL_NONE;
+ adc_pmic->mpp_base = pdata->adc_mpp_base;
+
+ mutex_init(&adc_pmic->adc_lock);
+ mutex_init(&adc_pmic->mpp_adc_lock);
+ spin_lock_init(&adc_pmic->btm_lock);
+
+ adc_pmic->adc_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_0);
+ if (adc_pmic->adc_irq < 0)
+ return adc_pmic->adc_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->adc_irq,
+ pm8xxx_adc_isr,
+ IRQF_TRIGGER_RISING, "pm8xxx_adc_interrupt", adc_pmic);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to request adc irq "
+ "with error %d\n", rc);
+ }
+
+ disable_irq_nosync(adc_pmic->adc_irq);
+
+ adc_pmic->btm_warm_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_1);
+ if (adc_pmic->btm_warm_irq < 0)
+ return adc_pmic->btm_warm_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_warm_irq,
+ pm8xxx_btm_warm_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_warm_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm warm irq failed %d with interrupt number %d\n",
+ rc, adc_pmic->btm_warm_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_warm_irq);
+
+ adc_pmic->btm_cool_irq = platform_get_irq(pdev, PM8XXX_ADC_IRQ_2);
+ if (adc_pmic->btm_cool_irq < 0)
+ return adc_pmic->btm_cool_irq;
+
+ rc = devm_request_irq(&pdev->dev, adc_pmic->btm_cool_irq,
+ pm8xxx_btm_cool_isr,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "pm8xxx_btm_cool_interrupt", adc_pmic);
+ if (rc) {
+ pr_err("btm cool irq failed with return %d and number %d\n",
+ rc, adc_pmic->btm_cool_irq);
+ dev_err(&pdev->dev, "failed to request btm irq\n");
+ }
+
+ disable_irq_nosync(adc_pmic->btm_cool_irq);
+ platform_set_drvdata(pdev, adc_pmic);
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pm8xxx_adc_wakelock");
+ adc_pmic->msm_suspend_check = 0;
+ pmic_adc = adc_pmic;
+
+ INIT_WORK(&adc_pmic->warm_work, pm8xxx_adc_btm_warm_scheduler_fn);
+ INIT_WORK(&adc_pmic->cool_work, pm8xxx_adc_btm_cool_scheduler_fn);
+ create_debugfs_entries();
+ pm8xxx_adc_calib_first_adc = false;
+ pm8xxx_adc_calib_device_init = false;
+ pm8xxx_adc_initialized = true;
+
+ rc = pm8xxx_adc_init_hwmon(pdev);
+ if (rc) {
+ pr_err("pm8xxx adc init hwmon failed with %d\n", rc);
+ dev_err(&pdev->dev, "failed to initialize pm8xxx hwmon adc\n");
+ }
+ adc_pmic->hwmon = hwmon_device_register(adc_pmic->dev);
+ return 0;
+}
+
+static struct platform_driver pm8xxx_adc_driver = {
+ .probe = pm8xxx_adc_probe,
+ .remove = __devexit_p(pm8xxx_adc_teardown),
+ .driver = {
+ .name = PM8XXX_ADC_DEV_NAME,
+ .owner = THIS_MODULE,
+ .pm = PM8XXX_ADC_DEV_PM_OPS,
+ },
+};
+
+static int __init pm8xxx_adc_init(void)
+{
+ return platform_driver_register(&pm8xxx_adc_driver);
+}
+module_init(pm8xxx_adc_init);
+
+static void __exit pm8xxx_adc_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_adc_driver);
+}
+module_exit(pm8xxx_adc_exit);
+
+MODULE_ALIAS("platform:" PM8XXX_ADC_DEV_NAME);
+MODULE_DESCRIPTION("PMIC8921/8018 ADC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/input/touchscreen/atmel_maxtouch.c b/drivers/input/touchscreen/atmel_maxtouch.c
index c454f72..d2bd4df 100644
--- a/drivers/input/touchscreen/atmel_maxtouch.c
+++ b/drivers/input/touchscreen/atmel_maxtouch.c
@@ -1373,12 +1373,11 @@
kfree(message);
fail_worker:
- enable_irq(mxt->irq);
/* Make sure we just didn't miss a interrupt. */
if (mxt->read_chg() == 0){
- disable_irq(mxt->irq);
schedule_delayed_work(&mxt->dwork, 0);
- }
+ } else
+ enable_irq(mxt->irq);
}
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index fc9d579..c9a5ba2 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -17,7 +17,7 @@
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/input/mt.h>
+#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
@@ -539,21 +539,19 @@
if (!finger[id].status)
continue;
- input_mt_slot(input_dev, id);
- input_mt_report_slot_state(input_dev, MT_TOOL_FINGER,
- finger[id].status != MXT_RELEASE);
+ input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
+ finger[id].status != MXT_RELEASE ?
+ finger[id].area : 0);
+ input_report_abs(input_dev, ABS_MT_POSITION_X,
+ finger[id].x);
+ input_report_abs(input_dev, ABS_MT_POSITION_Y,
+ finger[id].y);
+ input_mt_sync(input_dev);
- if (finger[id].status != MXT_RELEASE) {
- finger_num++;
- input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
- finger[id].area);
- input_report_abs(input_dev, ABS_MT_POSITION_X,
- finger[id].x);
- input_report_abs(input_dev, ABS_MT_POSITION_Y,
- finger[id].y);
- } else {
+ if (finger[id].status == MXT_RELEASE)
finger[id].status = 0;
- }
+ else
+ finger_num++;
}
input_report_key(input_dev, BTN_TOUCH, finger_num > 0);
@@ -1217,7 +1215,7 @@
}
}
- msleep(100);
+ msleep(130);
return 0;
@@ -1429,7 +1427,6 @@
0, data->max_y, 0, 0);
/* For multi touch */
- input_mt_init_slots(input_dev, MXT_MAX_FINGER);
input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
0, MXT_MAX_AREA, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_X,
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index 8dbdc01..179f465 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -392,7 +392,16 @@
.minimum = 0,
.maximum = 2,
},
-
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_READ_DEFAULT,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Read default",
+ },
+ {
+ .id = V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Write default",
+ },
};
static void iris_q_event(struct iris_device *radio,
@@ -733,7 +742,7 @@
__u8 sig_threshold = param;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
HCI_OCF_FM_SET_SIGNAL_THRESHOLD);
return radio_hci_send_cmd(hdev, opcode, sizeof(sig_threshold),
&sig_threshold);
@@ -744,7 +753,7 @@
{
__u16 opcode = 0;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
HCI_OCF_FM_GET_SIGNAL_THRESHOLD);
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
@@ -754,7 +763,7 @@
{
__u16 opcode = 0;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
HCI_OCF_FM_GET_PROGRAM_SERVICE_REQ);
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
@@ -764,7 +773,7 @@
{
__u16 opcode = 0;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
HCI_OCF_FM_GET_RADIO_TEXT_REQ);
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
@@ -774,7 +783,7 @@
{
__u16 opcode = 0;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
HCI_OCF_FM_GET_AF_LIST_REQ);
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
@@ -860,7 +869,7 @@
struct hci_fm_def_data_rd_req *def_data_rd =
(struct hci_fm_def_data_rd_req *) param;
- opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
HCI_OCF_FM_DEFAULT_DATA_READ);
return radio_hci_send_cmd(hdev, opcode, sizeof((*def_data_rd)),
def_data_rd);
@@ -873,7 +882,7 @@
struct hci_fm_def_data_wr_req *def_data_wr =
(struct hci_fm_def_data_wr_req *) param;
- opcode = hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
HCI_OCF_FM_DEFAULT_DATA_WRITE);
return radio_hci_send_cmd(hdev, opcode, sizeof((*def_data_wr)),
def_data_wr);
@@ -987,7 +996,7 @@
{
__u16 opcode = 0;
- opcode = hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ,
+ opcode = hci_opcode_pack(HCI_OGF_FM_DIAGNOSTIC_CMD_REQ,
HCI_OCF_FM_STATION_DBG_PARAM);
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
@@ -1212,7 +1221,6 @@
{
int ret = 0;
struct hci_fm_def_data_rd_req *def_data_rd = arg;
-
ret = radio_hci_request(hdev, hci_def_data_read_req, (unsigned
long)def_data_rd, RADIO_HCI_TIMEOUT);
@@ -1224,7 +1232,6 @@
{
int ret = 0;
struct hci_fm_def_data_wr_req *def_data_wr = arg;
-
ret = radio_hci_request(hdev, hci_def_data_write_req, (unsigned
long)def_data_wr, RADIO_HCI_TIMEOUT);
@@ -1596,6 +1603,32 @@
}
+
+static void hci_cc_riva_read_default_rsp(struct radio_hci_dev *hdev,
+ struct sk_buff *skb)
+{
+ struct iris_device *radio = video_get_drvdata(video_get_dev());
+ __u8 status = *((__u8 *) skb->data);
+ __u8 len;
+ char *data;
+
+ if (status)
+ return;
+ len = skb->data[1];
+ data = kmalloc(len+2, GFP_ATOMIC);
+ if (!data) {
+ FMDERR("Memory allocation failed");
+ return;
+ }
+
+ data[0] = status;
+ data[1] = len;
+ memcpy(&data[2], &skb->data[DEFAULT_DATA_OFFSET], len);
+ iris_q_evt_data(radio, data, len+2, IRIS_BUF_RD_DEFAULT);
+ radio_hci_req_complete(hdev, status);
+ kfree(data);
+}
+
static void hci_cc_ssbi_peek_rsp(struct radio_hci_dev *hdev,
struct sk_buff *skb)
{
@@ -1674,6 +1707,8 @@
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_RT_REQ):
case hci_trans_ctrl_cmd_op_pack(HCI_OCF_FM_RDS_PS_REQ):
case hci_common_cmd_op_pack(HCI_OCF_FM_DEFAULT_DATA_WRITE):
+ hci_cc_rsp(hdev, skb);
+ break;
case hci_common_cmd_op_pack(HCI_OCF_FM_RESET):
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_SSBI_POKE_REG):
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_POKE_DATA):
@@ -1705,6 +1740,9 @@
break;
case hci_common_cmd_op_pack(HCI_OCF_FM_DEFAULT_DATA_READ):
+ hci_cc_riva_read_default_rsp(hdev, skb);
+ break;
+
case hci_diagnostic_cmd_op_pack(HCI_OCF_FM_PEEK_DATA):
hci_cc_riva_peek_rsp(hdev, skb);
break;
@@ -2281,6 +2319,30 @@
return retval;
}
+static int iris_vidioc_g_ext_ctrls(struct file *file, void *priv,
+ struct v4l2_ext_controls *ctrl)
+{
+ int retval = 0;
+ char *data = NULL;
+ struct iris_device *radio = video_get_drvdata(video_devdata(file));
+ struct hci_fm_def_data_rd_req default_data_rd;
+
+ switch ((ctrl->controls[0]).id) {
+ case V4L2_CID_PRIVATE_IRIS_READ_DEFAULT:
+ data = (ctrl->controls[0]).string;
+ memset(&default_data_rd, 0, sizeof(default_data_rd));
+ if (copy_from_user(&default_data_rd.mode, data,
+ sizeof(default_data_rd)))
+ return -EFAULT;
+ retval = hci_def_data_read(&default_data_rd, radio->fm_hdev);
+ break;
+ default:
+ retval = -EINVAL;
+ }
+
+ return retval;
+}
+
static int iris_vidioc_s_ext_ctrls(struct file *file, void *priv,
struct v4l2_ext_controls *ctrl)
{
@@ -2288,6 +2350,7 @@
int bytes_to_copy;
struct hci_fm_tx_ps tx_ps;
struct hci_fm_tx_rt tx_rt;
+ struct hci_fm_def_data_wr_req default_data;
struct iris_device *radio = video_get_drvdata(video_devdata(file));
char *data = NULL;
@@ -2333,6 +2396,13 @@
retval = radio_hci_request(radio->fm_hdev, hci_trans_rt_req,
(unsigned long)&tx_rt, RADIO_HCI_TIMEOUT);
break;
+ case V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT:
+ data = (ctrl->controls[0]).string;
+ memset(&default_data, 0, sizeof(default_data));
+ if (copy_from_user(&default_data, data, sizeof(default_data)))
+ return -EFAULT;
+ retval = hci_def_data_write(&default_data, radio->fm_hdev);
+ break;
default:
FMDBG("Shouldn't reach here\n");
retval = -1;
@@ -2850,6 +2920,7 @@
.vidioc_dqbuf = iris_vidioc_dqbuf,
.vidioc_g_fmt_type_private = iris_vidioc_g_fmt_type_private,
.vidioc_s_ext_ctrls = iris_vidioc_s_ext_ctrls,
+ .vidioc_g_ext_ctrls = iris_vidioc_g_ext_ctrls,
};
static const struct v4l2_file_operations iris_fops = {
diff --git a/drivers/media/radio/radio-tavarua.c b/drivers/media/radio/radio-tavarua.c
index 10c5fbf..49bc46c 100644
--- a/drivers/media/radio/radio-tavarua.c
+++ b/drivers/media/radio/radio-tavarua.c
@@ -72,7 +72,7 @@
struct tavarua_device {
struct video_device *videodev;
/* driver management */
- int users;
+ atomic_t users;
/* top level driver data */
struct marimba *marimba;
struct device *dev;
@@ -1690,14 +1690,12 @@
char buffer[] = {0x00, 0x48, 0x8A, 0x8E, 0x97, 0xB7};
int bahama_present = -ENODEV;
- mutex_lock(&radio->lock);
- if (radio->users) {
- mutex_unlock(&radio->lock);
+ if (!atomic_dec_and_test(&radio->users)) {
+ pr_err("%s: Device already in use."
+ "Try again later", __func__);
+ atomic_inc(&radio->users);
return -EBUSY;
- } else {
- radio->users++;
}
- mutex_unlock(&radio->lock);
/* initial gpio pin config & Power up */
retval = radio->pdata->fm_setup(radio->pdata);
@@ -1877,7 +1875,7 @@
radio->pdata->fm_shutdown(radio->pdata);
open_err_setup:
radio->handle_irq = 1;
- radio->users = 0;
+ atomic_inc(&radio->users);
return retval;
}
@@ -1917,8 +1915,11 @@
{ 0x00, 0x80 }
};
- if (!radio)
+ if (!radio) {
+ pr_err("%s: Radio device not available...", __func__);
return -ENODEV;
+ }
+
FMDBG("In %s", __func__);
/* disable radio ctrl */
@@ -2021,7 +2022,7 @@
if (radio->pdata->config_i2s_gpio != NULL)
radio->pdata->config_i2s_gpio(FM_I2S_OFF);
radio->handle_irq = 1;
- radio->users = 0;
+ atomic_inc(&radio->users);
radio->marimba->mod_id = SLAVE_ID_BAHAMA;
return 0;
}
@@ -2785,20 +2786,14 @@
FMDBG("turning on ..\n");
retval = tavarua_start(radio, ctrl->value);
if (retval >= 0) {
- FMDBG("Setting audio path ...\n");
- retval = tavarua_set_audio_path(
- TAVARUA_AUDIO_OUT_DIGITAL_ON,
- TAVARUA_AUDIO_OUT_ANALOG_OFF);
- if (retval < 0) {
- FMDERR("Error in tavarua_set_audio_path"
- " %d\n", retval);
- }
- /* Enabling 'SoftMute' and 'SignalBlending' features */
- value = (radio->registers[IOCTRL] |
+ /* Enabling 'SoftMute' & 'SignalBlending' */
+ value = (radio->registers[IOCTRL] |
IOC_SFT_MUTE | IOC_SIG_BLND);
- retval = tavarua_write_register(radio, IOCTRL, value);
- if (retval < 0)
- FMDBG("SMute and SBlending not enabled\n");
+ retval = tavarua_write_register(radio,
+ IOCTRL, value);
+ if (retval < 0)
+ FMDBG("SMute and SBlending"
+ "not enabled\n");
}
}
/* check if off */
@@ -2821,6 +2816,28 @@
}
}
break;
+ case V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH:
+ FMDBG("Setting audio path ...\n");
+ if (ctrl->value == FM_DIGITAL_PATH) {
+ FMDBG("Digital audio path enabled ...\n");
+ retval = tavarua_set_audio_path(
+ TAVARUA_AUDIO_OUT_DIGITAL_ON,
+ TAVARUA_AUDIO_OUT_ANALOG_OFF);
+ if (retval < 0) {
+ FMDERR("Error in tavarua_set_audio_path"
+ " %d\n", retval);
+ }
+ } else if (ctrl->value == FM_ANALOG_PATH) {
+ FMDBG("Analog audio path enabled ...\n");
+ retval = tavarua_set_audio_path(
+ TAVARUA_AUDIO_OUT_ANALOG_ON,
+ TAVARUA_AUDIO_OUT_DIGITAL_OFF);
+ if (retval < 0) {
+ FMDERR("Error in tavarua_set_audio_path"
+ " %d\n", retval);
+ }
+ }
+ break;
case V4L2_CID_PRIVATE_TAVARUA_REGION:
retval = tavarua_set_region(radio, ctrl->value);
break;
@@ -3535,9 +3552,7 @@
int users = 0;
printk(KERN_INFO DRIVER_NAME "%s: radio suspend\n\n", __func__);
if (radio) {
- mutex_lock(&radio->lock);
- users = radio->users;
- mutex_unlock(&radio->lock);
+ users = atomic_read(&radio->users);
if (users) {
retval = tavarua_disable_interrupts(radio);
if (retval < 0) {
@@ -3568,9 +3583,7 @@
int users = 0;
printk(KERN_INFO DRIVER_NAME "%s: radio resume\n\n", __func__);
if (radio) {
- mutex_lock(&radio->lock);
- users = radio->users;
- mutex_unlock(&radio->lock);
+ users = atomic_read(&radio->users);
if (users) {
retval = tavarua_setup_interrupts(radio,
@@ -3719,8 +3732,8 @@
goto err_bufs;
}
}
- /* init xfr status */
- radio->users = 0;
+ /* initializing the device count */
+ atomic_set(&radio->users, 1);
radio->xfr_in_progress = 0;
radio->xfr_bytes_left = 0;
for (i = 0; i < TAVARUA_XFR_MAX; i++)
diff --git a/drivers/media/video/msm/actuators/imx074_act.c b/drivers/media/video/msm/actuators/imx074_act.c
index 0f9fc1d..2af21d6 100644
--- a/drivers/media/video/msm/actuators/imx074_act.c
+++ b/drivers/media/video/msm/actuators/imx074_act.c
@@ -53,7 +53,7 @@
};
static int32_t imx074_wrapper_i2c_write(struct msm_actuator_ctrl_t *a_ctrl,
- int16_t next_lens_position)
+ int16_t next_lens_position, void *params)
{
msm_camera_i2c_write(&a_ctrl->i2c_client,
0x00,
@@ -86,7 +86,7 @@
__func__,
dac_value);
- rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, dac_value);
+ rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, dac_value, NULL);
return rc;
}
@@ -122,8 +122,8 @@
0x4F,
MSM_CAMERA_I2C_BYTE_DATA);
- rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F);
- rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F);
+ rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F, NULL);
+ rc = a_ctrl->func_tbl.actuator_i2c_write(a_ctrl, 0x7F, NULL);
a_ctrl->curr_step_pos = 0;
return rc;
}
diff --git a/drivers/media/video/msm/actuators/msm_actuator.c b/drivers/media/video/msm/actuators/msm_actuator.c
index b76fb74..7f570e6 100644
--- a/drivers/media/video/msm/actuators/msm_actuator.c
+++ b/drivers/media/video/msm/actuators/msm_actuator.c
@@ -40,14 +40,16 @@
(next_lens_pos +
(sign_direction * damping_code_step))) {
rc = a_ctrl->func_tbl.
- actuator_i2c_write(a_ctrl, next_lens_pos);
+ actuator_i2c_write(a_ctrl, next_lens_pos,
+ damping_params->hw_params);
curr_lens_pos = next_lens_pos;
usleep(wait_time);
}
if (curr_lens_pos != code_boundary) {
rc = a_ctrl->func_tbl.
- actuator_i2c_write(a_ctrl, code_boundary);
+ actuator_i2c_write(a_ctrl, code_boundary,
+ damping_params->hw_params);
usleep(wait_time);
}
return rc;
@@ -107,6 +109,8 @@
}
curr_lens_pos = a_ctrl->step_position_table[a_ctrl->curr_step_pos];
+ CDBG("curr_step_pos =%d dest_step_pos =%d curr_lens_pos=%d\n",
+ a_ctrl->curr_step_pos, dest_step_pos, curr_lens_pos);
while (a_ctrl->curr_step_pos != dest_step_pos) {
step_boundary =
@@ -183,12 +187,10 @@
a_ctrl->step_position_table[step_index] = cur_code;
}
}
-
- LINFO("step position table\n");
for (step_index = 0;
step_index < a_ctrl->set_info.total_steps;
step_index++) {
- LINFO("spt i %d, val %d\n",
+ CDBG("step_position_table[%d]= %d\n",
step_index,
a_ctrl->step_position_table[step_index]);
}
diff --git a/drivers/media/video/msm/actuators/msm_actuator.h b/drivers/media/video/msm/actuators/msm_actuator.h
index c228998..d612dad 100644
--- a/drivers/media/video/msm/actuators/msm_actuator.h
+++ b/drivers/media/video/msm/actuators/msm_actuator.h
@@ -52,7 +52,7 @@
int (*actuator_power_down) (struct msm_actuator_ctrl_t *);
int32_t (*actuator_config)(void __user *);
int32_t (*actuator_i2c_write)(struct msm_actuator_ctrl_t *,
- int16_t);
+ int16_t, void *);
int32_t (*actuator_write_focus)(struct msm_actuator_ctrl_t *,
uint16_t,
struct damping_params_t *,
diff --git a/drivers/media/video/msm/msm.c b/drivers/media/video/msm/msm.c
index 847a1ec..727b751 100644
--- a/drivers/media/video/msm/msm.c
+++ b/drivers/media/video/msm/msm.c
@@ -136,17 +136,20 @@
struct msm_device_queue *queue = &server_dev->ctrl_q;
struct v4l2_event v4l2_evt;
- struct msm_isp_stats_event_ctrl *isp_event;
+ struct msm_isp_event_ctrl *isp_event;
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_KERNEL);
+ if (!isp_event) {
+ pr_err("%s Insufficient memory. return", __func__);
+ return -ENOMEM;
+ }
D("%s\n", __func__);
v4l2_evt.type = V4L2_EVENT_PRIVATE_START + MSM_CAM_RESP_V4L2;
-
/* setup event object to transfer the command; */
- isp_event = (struct msm_isp_stats_event_ctrl *)v4l2_evt.u.data;
+ *((uint32_t *)v4l2_evt.u.data) = (uint32_t)isp_event;
isp_event->resptype = MSM_CAM_RESP_V4L2;
isp_event->isp_data.ctrl = *out;
-
- /* now send command to config thread in usersspace,
+ /* now send command to config thread in userspace,
* and wait for results */
v4l2_event_queue(server_dev->server_command_queue.pvdev,
&v4l2_evt);
@@ -181,6 +184,7 @@
out->value = value;
free_qcmd(rcmd);
+ kfree(isp_event);
D("%s: rc %d\n", __func__, rc);
/* rc is the time elapsed. */
if (rc >= 0) {
@@ -1739,45 +1743,80 @@
break;
case VIDIOC_DQEVENT: {
- void __user *u_ctrl_value = NULL;
- struct msm_isp_stats_event_ctrl *u_isp_event;
- struct msm_isp_stats_event_ctrl *k_isp_event;
+ void __user *u_ctrl_value = NULL, *user_ptr = NULL;
+ struct msm_isp_event_ctrl u_isp_event;
+ struct msm_isp_event_ctrl *k_isp_event;
- /* Make a copy of control value and event data pointer */
+ /* First, copy the event structure from userspace */
D("%s: VIDIOC_DQEVENT\n", __func__);
if (copy_from_user(&ev, (void __user *)arg,
- sizeof(struct v4l2_event)))
+ sizeof(struct v4l2_event))) {
break;
- u_isp_event = (struct msm_isp_stats_event_ctrl *)ev.u.data;
- u_ctrl_value = u_isp_event->isp_data.ctrl.value;
+ }
+ /* Next, get the pointer to event_ctrl structure
+ * embedded inside the v4l2_event.u.data array. */
+ user_ptr = (void __user *)(*((uint32_t *)ev.u.data));
+ /* Next, copy the userspace event ctrl structure */
+ if (copy_from_user((void *)&u_isp_event, user_ptr,
+ sizeof(struct msm_isp_event_ctrl))) {
+ break;
+ }
+
+ /* Save the pointer of the user allocated command buffer*/
+ u_ctrl_value = u_isp_event.isp_data.ctrl.value;
+
+ /* Dequeue the event queued into the v4l2 queue*/
rc = v4l2_event_dequeue(
&g_server_dev.server_command_queue.eventHandle,
- &ev, fp->f_flags & O_NONBLOCK);
+ &ev, fp->f_flags & O_NONBLOCK);
if (rc < 0) {
pr_err("no pending events?");
break;
}
- k_isp_event = (struct msm_isp_stats_event_ctrl *)ev.u.data;
- if (ev.type == V4L2_EVENT_PRIVATE_START+MSM_CAM_RESP_V4L2 &&
- k_isp_event->isp_data.ctrl.length > 0) {
- void *k_ctrl_value = k_isp_event->isp_data.ctrl.value;
- if (copy_to_user(u_ctrl_value, k_ctrl_value,
- u_isp_event->isp_data.ctrl.length)) {
+ /* Use k_isp_event to point to the event_ctrl structure
+ * embedded inside v4l2_event.u.data */
+ k_isp_event = (struct msm_isp_event_ctrl *)
+ (*((uint32_t *)ev.u.data));
+ if (!k_isp_event) {
+ pr_err("%s Invalid event ctrl structure. ", __func__);
+ break;
+ }
+
+ /* Copy the event structure into user struct*/
+ u_isp_event = *k_isp_event;
+
+ /* Restore the saved pointer of the user
+ * allocated command buffer. */
+ u_isp_event.isp_data.ctrl.value = u_ctrl_value;
+ if (ev.type == V4L2_EVENT_PRIVATE_START+MSM_CAM_RESP_V4L2) {
+ /* Copy the ctrl cmd, if present*/
+ if (k_isp_event->isp_data.ctrl.length > 0) {
+ void *k_ctrl_value =
+ k_isp_event->isp_data.ctrl.value;
+ if (copy_to_user(u_ctrl_value, k_ctrl_value,
+ k_isp_event->isp_data.ctrl.length)) {
+ rc = -EINVAL;
+ break;
+ }
+ }
+ /* Copy the event ctrl structure back into
+ * user's structure. */
+ if (copy_to_user(user_ptr, (void *)&u_isp_event,
+ sizeof(struct msm_isp_event_ctrl))) {
rc = -EINVAL;
break;
}
}
- k_isp_event->isp_data.ctrl.value = u_ctrl_value;
+ /* Copy the v4l2_event structure back to the user*/
if (copy_to_user((void __user *)arg, &ev,
sizeof(struct v4l2_event))) {
rc = -EINVAL;
break;
}
}
-
break;
case MSM_CAM_IOCTL_CTRL_CMD_DONE:
@@ -1900,46 +1939,77 @@
break;
case VIDIOC_DQEVENT: {
- void __user *u_msg_value = NULL;
- struct msm_isp_stats_event_ctrl *u_isp_event;
- struct msm_isp_stats_event_ctrl *k_isp_event;
+ void __user *u_msg_value = NULL, *user_ptr = NULL;
+ struct msm_isp_event_ctrl u_isp_event;
+ struct msm_isp_event_ctrl *k_isp_event;
- /* Make a copy of control value and event data pointer */
+ /* First, copy the v4l2 event structure from userspace */
D("%s: VIDIOC_DQEVENT\n", __func__);
if (copy_from_user(&ev, (void __user *)arg,
sizeof(struct v4l2_event)))
break;
- u_isp_event =
- (struct msm_isp_stats_event_ctrl *)ev.u.data;
- u_msg_value = u_isp_event->isp_data.isp_msg.data;
+ /* Next, get the pointer to event_ctrl structure
+ * embedded inside the v4l2_event.u.data array. */
+ user_ptr = (void __user *)(*((uint32_t *)ev.u.data));
+ /* Next, copy the userspace event ctrl structure */
+ if (copy_from_user((void *)&u_isp_event, user_ptr,
+ sizeof(struct msm_isp_event_ctrl))) {
+ break;
+ }
+ /* Save the pointer of the user allocated command buffer*/
+ u_msg_value = u_isp_event.isp_data.isp_msg.data;
+
+ /* Dequeue the event queued into the v4l2 queue*/
rc = v4l2_event_dequeue(
- &config_cam->config_stat_event_queue.eventHandle,
- &ev, fp->f_flags & O_NONBLOCK);
+ &config_cam->config_stat_event_queue.eventHandle,
+ &ev, fp->f_flags & O_NONBLOCK);
if (rc < 0) {
pr_err("no pending events?");
break;
}
+ /* Use k_isp_event to point to the event_ctrl structure
+ * embedded inside v4l2_event.u.data */
+ k_isp_event = (struct msm_isp_event_ctrl *)
+ (*((uint32_t *)ev.u.data));
+ /* Copy the event structure into user struct. */
+ u_isp_event = *k_isp_event;
+
if (ev.type != (V4L2_EVENT_PRIVATE_START +
MSM_CAM_RESP_DIV_FRAME_EVT_MSG) &&
ev.type != (V4L2_EVENT_PRIVATE_START +
MSM_CAM_RESP_MCTL_PP_EVENT)) {
- k_isp_event =
- (struct msm_isp_stats_event_ctrl *)ev.u.data;
+
+ /* Restore the saved pointer of the
+ * user allocated command buffer. */
+ u_isp_event.isp_data.isp_msg.data = u_msg_value;
+
if (ev.type == (V4L2_EVENT_PRIVATE_START +
- MSM_CAM_RESP_STAT_EVT_MSG) &&
- k_isp_event->isp_data.isp_msg.len > 0) {
- void *k_msg_value =
+ MSM_CAM_RESP_STAT_EVT_MSG)) {
+ if (k_isp_event->isp_data.isp_msg.len > 0) {
+ void *k_msg_value =
k_isp_event->isp_data.isp_msg.data;
- if (copy_to_user(u_msg_value, k_msg_value,
- k_isp_event->isp_data.isp_msg.len)) {
- rc = -EINVAL;
- break;
+ if (copy_to_user(u_msg_value,
+ k_msg_value,
+ k_isp_event->isp_data.isp_msg.len)) {
+ rc = -EINVAL;
+ break;
+ }
+ kfree(k_msg_value);
}
- kfree(k_msg_value);
}
- k_isp_event->isp_data.isp_msg.data = u_msg_value;
}
+ /* Copy the event ctrl structure back
+ * into user's structure. */
+ if (copy_to_user(user_ptr,
+ (void *)&u_isp_event, sizeof(
+ struct msm_isp_event_ctrl))) {
+ rc = -EINVAL;
+ break;
+ }
+ kfree(k_isp_event);
+
+ /* Copy the v4l2_event structure back to the user*/
if (copy_to_user((void __user *)arg, &ev,
sizeof(struct v4l2_event))) {
rc = -EINVAL;
diff --git a/drivers/media/video/msm/msm.h b/drivers/media/video/msm/msm.h
index bf75e8b..083fc57 100644
--- a/drivers/media/video/msm/msm.h
+++ b/drivers/media/video/msm/msm.h
@@ -91,6 +91,11 @@
uint32_t vb;
};
+struct isp_msg_event {
+ uint32_t msg_id;
+ uint32_t sof_count;
+};
+
struct isp_msg_output {
uint8_t output_id;
struct msm_free_buf buf;
diff --git a/drivers/media/video/msm/msm_io_8960.c b/drivers/media/video/msm/msm_io_8960.c
index 43f893b..45871bc 100644
--- a/drivers/media/video/msm/msm_io_8960.c
+++ b/drivers/media/video/msm/msm_io_8960.c
@@ -60,6 +60,7 @@
#define MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR 0x01D0
/* MIPI CSID registers */
+#define CSID_HW_VERSION_ADDR 0x0
#define CSID_CORE_CTRL_ADDR 0x4
#define CSID_RST_CMD_ADDR 0x8
#define CSID_CID_LUT_VC_0_ADDR 0xc
@@ -105,6 +106,9 @@
#define CAM_VANA_LOAD_UA 85600
#define CAM_CSI_LOAD_UA 20000
+#define CSID_VERSION_V2 0x2000011
+
+static uint32_t csid_hw_version;
static struct clk *camio_cam_clk;
static struct clk *camio_vfe_clk;
static struct clk *camio_csi_src_clk;
@@ -113,7 +117,10 @@
static struct clk *camio_csi0_clk;
static struct clk *camio_csi0_pclk;
static struct clk *camio_csi_pix_clk;
+static struct clk *camio_csi_pix1_clk;
static struct clk *camio_csi_rdi_clk;
+static struct clk *camio_csi_rdi1_clk;
+static struct clk *camio_csi_rdi2_clk;
static struct clk *camio_csiphy0_timer_clk;
static struct clk *camio_csiphy1_timer_clk;
static struct clk *camio_vfe_pclk;
@@ -497,6 +504,13 @@
msm_camio_clk_rate_set_2(clk, csid_core);
break;
+ case CAMIO_CSI_PIX1_CLK:
+ camio_csi_pix1_clk =
+ clk = clk_get(NULL, "csi_pix1_clk");
+ /* mux to select between csid0 and csid1 */
+ msm_camio_clk_rate_set_2(clk, csid_core);
+ break;
+
case CAMIO_CSI_RDI_CLK:
camio_csi_rdi_clk =
clk = clk_get(NULL, "csi_rdi_clk");
@@ -504,6 +518,20 @@
msm_camio_clk_rate_set_2(clk, csid_core);
break;
+ case CAMIO_CSI_RDI1_CLK:
+ camio_csi_rdi1_clk =
+ clk = clk_get(NULL, "csi_rdi1_clk");
+ /* mux to select between csid0 and csid1 */
+ msm_camio_clk_rate_set_2(clk, csid_core);
+ break;
+
+ case CAMIO_CSI_RDI2_CLK:
+ camio_csi_rdi2_clk =
+ clk = clk_get(NULL, "csi_rdi2_clk");
+ /* mux to select between csid0 and csid1 */
+ msm_camio_clk_rate_set_2(clk, csid_core);
+ break;
+
case CAMIO_CSIPHY0_TIMER_CLK:
camio_csiphy0_timer_clk =
clk = clk_get(NULL, "csi0phy_timer_clk");
@@ -596,10 +624,22 @@
clk = camio_csi0_phy_clk;
break;
+ case CAMIO_CSI_PIX1_CLK:
+ clk = camio_csi_pix1_clk;
+ break;
+
case CAMIO_CSI_PIX_CLK:
clk = camio_csi_pix_clk;
break;
+ case CAMIO_CSI_RDI1_CLK:
+ clk = camio_csi_rdi1_clk;
+ break;
+
+ case CAMIO_CSI_RDI2_CLK:
+ clk = camio_csi_rdi2_clk;
+ break;
+
case CAMIO_CSI_RDI_CLK:
clk = camio_csi_rdi_clk;
break;
@@ -744,6 +784,40 @@
return IRQ_HANDLED;
}
#endif
+
+static int msm_camio_enable_v2_clks(void)
+{
+ int rc = 0;
+ csid_hw_version = msm_io_r(csidbase +
+ CSID_HW_VERSION_ADDR);
+ CDBG("%s csid_hw_version %d\n",
+ __func__,
+ csid_hw_version);
+
+ if (csid_hw_version == CSID_VERSION_V2) {
+ rc = msm_camio_clk_enable(CAMIO_CSI_PIX1_CLK);
+ if (rc < 0)
+ goto csi_pix1_fail;
+
+ rc = msm_camio_clk_enable(CAMIO_CSI_RDI1_CLK);
+ if (rc < 0)
+ goto csi_rdi1_fail;
+
+ rc = msm_camio_clk_enable(CAMIO_CSI_RDI2_CLK);
+ if (rc < 0)
+ goto csi_rdi2_fail;
+ }
+
+ return rc;
+
+csi_rdi2_fail:
+ msm_camio_clk_disable(CAMIO_CSI_RDI1_CLK);
+csi_rdi1_fail:
+ msm_camio_clk_disable(CAMIO_CSI_PIX1_CLK);
+csi_pix1_fail:
+ return rc;
+}
+
static int msm_camio_enable_all_clks(uint8_t csid_core)
{
int rc = 0;
@@ -824,8 +898,18 @@
return rc;
}
+static void msm_camio_disable_v2_clks(void)
+{
+ if (csid_hw_version == CSID_VERSION_V2) {
+ msm_camio_clk_disable(CAMIO_CSI_RDI2_CLK);
+ msm_camio_clk_disable(CAMIO_CSI_RDI1_CLK);
+ msm_camio_clk_disable(CAMIO_CSI_PIX1_CLK);
+ }
+}
+
static void msm_camio_disable_all_clks(uint8_t csid_core)
{
+ msm_camio_disable_v2_clks();
msm_camio_clk_disable(CAMIO_CSI_RDI_CLK);
msm_camio_clk_disable(CAMIO_CSI_PIX_CLK);
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
@@ -1034,6 +1118,7 @@
if (rc < 0)
goto csiphy_irq_fail;
#endif
+ msm_camio_enable_v2_clks();
CDBG("camio enable done\n");
return 0;
#if DBG_CSIPHY
diff --git a/drivers/media/video/msm/msm_io_8x60.c b/drivers/media/video/msm/msm_io_8x60.c
index 5de800f..2262aa4 100644
--- a/drivers/media/video/msm/msm_io_8x60.c
+++ b/drivers/media/video/msm/msm_io_8x60.c
@@ -573,8 +573,6 @@
int rc = 0;
struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- uint32_t val;
-
camio_dev = pdev;
camio_ext = camdev->ioext;
camio_clk = camdev->ioclk;
@@ -606,22 +604,6 @@
if (rc < 0)
goto csi_irq_fail;
- msleep(10);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
- CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
- CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
return 0;
csi_irq_fail:
@@ -642,30 +624,17 @@
return rc;
}
-void msm_camio_disable(struct platform_device *pdev)
+static void msm_camio_csi_disable(void)
{
uint32_t val;
- val = (0x0 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x0 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x0 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
- val = (20 <<
- MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
- (0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
- (0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
+ val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
- val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
- (0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
@@ -681,8 +650,12 @@
csi_free_irq();
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
+}
+void msm_camio_disable(struct platform_device *pdev)
+{
+ CDBG("disable mipi\n");
+ msm_camio_csi_disable();
CDBG("disable clocks\n");
-
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI0_CLK);
msm_camio_clk_disable(CAMIO_CSI1_VFE_CLK);
@@ -755,8 +728,9 @@
{
int rc = 0;
uint32_t val = 0;
+ int i;
- CDBG("msm_camio_csi_config \n");
+ CDBG("msm_camio_csi_config\n");
/* SOT_ECC_EN enable error correction for SYNC (data-lane) */
msm_io_w(0x4, csibase + MIPI_PHY_CONTROL);
@@ -776,15 +750,6 @@
CDBG("%s MIPI_PROTOCOL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PROTOCOL_CONTROL);
- /* SW CAL EN */
- val = (0x1 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
- (0x1 <<
- MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
- (0x1 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
- CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
-
/* settle_cnt is very sensitive to speed!
increase this value to run at higher speeds */
val = (csi_params->settle_cnt <<
@@ -793,11 +758,8 @@
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
- msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
- msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
-
+ for (i = 0; i < csi_params->lane_cnt; i++)
+ msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2 + i * 4);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index 701f2d9..9204269 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -142,7 +142,7 @@
{
int rc = 0;
struct v4l2_event v4l2_evt;
- struct msm_isp_stats_event_ctrl *isp_event;
+ struct msm_isp_event_ctrl *isp_event;
struct msm_sync *sync =
(struct msm_sync *)v4l2_get_subdev_hostdata(sd);
struct msm_cam_media_controller *pmctl = &sync->pcam_sync->mctl;
@@ -157,17 +157,28 @@
if (notification == NOTIFY_VFE_BUF_EVT)
return msm_isp_notify_VFE_BUF_EVT(sd, arg);
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl), GFP_KERNEL);
+ if (!isp_event) {
+ pr_err("%s Insufficient memory. return", __func__);
+ return -ENOMEM;
+ }
+
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
MSM_CAM_RESP_STAT_EVT_MSG;
- isp_event = (struct msm_isp_stats_event_ctrl *)v4l2_evt.u.data;
+ *((uint32_t *)v4l2_evt.u.data) = (uint32_t)isp_event;
+
isp_event->resptype = MSM_CAM_RESP_STAT_EVT_MSG;
isp_event->isp_data.isp_msg.type = MSM_CAMERA_MSG;
isp_event->isp_data.isp_msg.len = 0;
switch (notification) {
- case NOTIFY_ISP_MSG_EVT:
- isp_event->isp_data.isp_msg.msg_id = (uint32_t)arg;
+ case NOTIFY_ISP_MSG_EVT: {
+ struct isp_msg_event *isp_msg = (struct isp_msg_event *)arg;
+
+ isp_event->isp_data.isp_msg.msg_id = isp_msg->msg_id;
+ isp_event->isp_data.isp_msg.frame_id = isp_msg->sof_count;
break;
+ }
case NOTIFY_VFE_MSG_OUT: {
uint8_t msgid;
struct isp_msg_output *isp_output =
@@ -195,6 +206,8 @@
if (!rc) {
isp_event->isp_data.isp_msg.msg_id =
isp_output->output_id;
+ isp_event->isp_data.isp_msg.frame_id =
+ isp_output->frameCounter;
buf = isp_output->buf;
msm_mctl_buf_done(pmctl, msgid,
&buf, isp_output->frameCounter);
@@ -206,6 +219,8 @@
struct isp_msg_stats *isp_stats = (struct isp_msg_stats *)arg;
isp_event->isp_data.isp_msg.msg_id = isp_stats->id;
+ isp_event->isp_data.isp_msg.frame_id =
+ isp_stats->frameCounter;
stats.buffer = msm_pmem_stats_ptov_lookup(&pmctl->sync,
isp_stats->buffer,
&(stats.fd));
diff --git a/drivers/media/video/msm/msm_ispif.c b/drivers/media/video/msm/msm_ispif.c
index c5e38ef..8797d38 100644
--- a/drivers/media/video/msm/msm_ispif.c
+++ b/drivers/media/video/msm/msm_ispif.c
@@ -47,6 +47,7 @@
#define ISPIF_IRQ_MASK_1_ADDR 0X010C
#define ISPIF_IRQ_CLEAR_1_ADDR 0X0110
#define ISPIF_IRQ_STATUS_1_ADDR 0X0114
+#define ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR 0x0124
/*ISPIF RESET BITS*/
@@ -73,9 +74,11 @@
#define ISPIF_IRQ_STATUS_MASK 0xA493000
#define ISPIF_IRQ_1_STATUS_MASK 0xA493000
#define ISPIF_IRQ_STATUS_RDI_SOF_MASK 0x492000
+#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x1
#define MAX_CID 15
+
static struct ispif_device *ispif;
static uint32_t global_intf_cmd_mask = 0xFFFFFFFF;
@@ -207,6 +210,8 @@
ISPIF_IRQ_MASK_ADDR);
msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_CLEAR_ADDR);
+ msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
@@ -410,6 +415,8 @@
}
msm_io_w(out->ispifIrqStatus0,
ispif->base + ISPIF_IRQ_CLEAR_ADDR);
+ msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
+ ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
}
static irqreturn_t msm_io_ispif_irq(int irq_num, void *data)
diff --git a/drivers/media/video/msm/msm_mctl_buf.c b/drivers/media/video/msm/msm_mctl_buf.c
index a83fa00..a8554ee 100644
--- a/drivers/media/video/msm/msm_mctl_buf.c
+++ b/drivers/media/video/msm/msm_mctl_buf.c
@@ -516,8 +516,8 @@
idx = msm_mctl_out_type_to_inst_index(pmctl->sync.pcam_sync,
msg_type);
pcam_inst = pmctl->sync.pcam_sync->dev_inst[idx];
- if (!pcam_inst->streamon) {
- D("%s: stream 0x%p is off\n", __func__, pcam_inst);
+ if (!pcam_inst || !pcam_inst->streamon) {
+ D("%s: stream is turned off\n", __func__);
return rc;
}
spin_lock_irqsave(&pcam_inst->vq_irqlock, flags);
diff --git a/drivers/media/video/msm/msm_mctl_pp.c b/drivers/media/video/msm/msm_mctl_pp.c
index f0c1bfa..7040c29 100644
--- a/drivers/media/video/msm/msm_mctl_pp.c
+++ b/drivers/media/video/msm/msm_mctl_pp.c
@@ -41,14 +41,22 @@
struct msm_cam_evt_divert_frame *div)
{
struct v4l2_event v4l2_evt;
-
+ struct msm_isp_event_ctrl *isp_event;
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl),
+ GFP_KERNEL);
+ if (!isp_event) {
+ pr_err("%s Insufficient memory. return", __func__);
+ return -ENOMEM;
+ }
D("%s: msm_cam_evt_divert_frame=%d",
__func__, sizeof(struct msm_cam_evt_divert_frame));
memset(&v4l2_evt, 0, sizeof(v4l2_evt));
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
MSM_CAM_RESP_DIV_FRAME_EVT_MSG;
- memcpy(&v4l2_evt.u.data[0], div,
- sizeof(struct msm_cam_evt_divert_frame));
+ *((uint32_t *)v4l2_evt.u.data) = (uint32_t)isp_event;
+ /* Copy the divert frame struct into event ctrl struct. */
+ isp_event->isp_data.div_frame = *div;
+
D("%s inst=%p, img_mode=%d, frame_id=%d,phy=0x%x,len=%d\n",
__func__, pcam_inst, pcam_inst->image_mode, div->frame_id,
(uint32_t)div->phy_addr, div->length);
@@ -563,7 +571,7 @@
pp_frame_info->dest_frame.handle;
msm_mctl_buf_done_pp(
p_mctl, msg_type, &done_frame, 0);
- pr_err("%s: vpe done to app, vb=0x%x, path=%d, phy=0x%x",
+ pr_info("%s: vpe done to app, vb=0x%x, path=%d, phy=0x%x",
__func__, done_frame.vb,
pp_frame_cmd->path, done_frame.ch_paddr[0]);
}
@@ -571,21 +579,31 @@
pp_frame_cmd->vpe_output_action)) {
struct v4l2_event v4l2_evt;
struct msm_mctl_pp_event_info *pp_event_info;
+ struct msm_isp_event_ctrl *isp_event;
+ isp_event = kzalloc(sizeof(struct msm_isp_event_ctrl),
+ GFP_KERNEL);
+ if (!isp_event) {
+ pr_err("%s Insufficient memory.", __func__);
+ return -ENOMEM;
+ }
memset(&v4l2_evt, 0, sizeof(v4l2_evt));
- pp_event_info =
- (struct msm_mctl_pp_event_info *)v4l2_evt.
- u.data;
+ *((uint32_t *)v4l2_evt.u.data) = (uint32_t)isp_event;
+
+ /* Get hold of pp event info struct inside event ctrl.*/
+ pp_event_info = &(isp_event->isp_data.pp_event_info);
+
pp_event_info->event = MCTL_PP_EVENT_CMD_ACK;
pp_event_info->ack.cmd = pp_frame_info->user_cmd;
pp_event_info->ack.status = 0;
pp_event_info->ack.cookie = pp_frame_cmd->cookie;
v4l2_evt.type = V4L2_EVENT_PRIVATE_START +
MSM_CAM_RESP_MCTL_PP_EVENT;
+
v4l2_event_queue(
p_mctl->config_device->
config_stat_event_queue.pvdev,
&v4l2_evt);
- pr_err("%s: ack to daemon, cookie=0x%x, event = 0x%x",
+ D("%s: ack to daemon, cookie=0x%x, event = 0x%x",
__func__, pp_frame_info->pp_frame_cmd.cookie,
v4l2_evt.type);
}
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index c801e4a..219e504 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -199,7 +199,7 @@
V32_DEMOSAICV3_DBCC_OFF},
{VFE_CMD_DEMOSAICV3_DBPC_UPDATE},
{VFE_CMD_XBAR_CFG},
- {VFE_CMD_EZTUNE_CFG},
+ {VFE_CMD_MODULE_CFG, V32_MODULE_CFG_LEN, V32_MODULE_CFG_OFF},
{VFE_CMD_ZSL},
/*115*/ {VFE_CMD_LINEARIZATION_UPDATE, V32_LINEARIZATION_LEN1,
V32_LINEARIZATION_OFF1},
@@ -678,7 +678,7 @@
msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
- msm_io_dump(vfe32_ctrl->vfebase, 0x740);
+ msm_io_dump(vfe32_ctrl->vfebase, 0x7B4);
/* Ensure the write order while writing
to the command register using the barrier */
@@ -1121,6 +1121,19 @@
vfe32_program_dmi_cfg(NO_MEM_SELECTED);
}
+static void vfe32_send_isp_msg(
+ struct vfe32_ctrl_type *vctrl,
+ uint32_t isp_msg_id)
+{
+ struct isp_msg_event isp_msg_evt;
+
+ isp_msg_evt.msg_id = isp_msg_id;
+ isp_msg_evt.sof_count = vfe32_ctrl->vfeFrameId;
+ v4l2_subdev_notify(vctrl->subdev,
+ NOTIFY_ISP_MSG_EVT,
+ (void *)&isp_msg_evt);
+}
+
static int vfe32_proc_general(struct msm_isp_cmd *cmd)
{
int i , rc = 0;
@@ -1807,7 +1820,7 @@
vfe32_sync_timer_start(cmdp);
break;
- case VFE_CMD_EZTUNE_CFG: {
+ case VFE_CMD_MODULE_CFG: {
cmdp = kmalloc(cmd->length, GFP_ATOMIC);
if (!cmdp) {
rc = -ENOMEM;
@@ -1885,16 +1898,16 @@
msm_io_memcpy(vfe32_ctrl->vfebase + V33_PCA_ROLL_OFF_CFG_OFF2,
cmdp_local, V33_PCA_ROLL_OFF_CFG_LEN2);
+ cmdp_local += 3;
CDBG("%s: start writing RollOff Ram0 table\n", __func__);
vfe32_program_dmi_cfg(ROLLOFF_RAM0_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- cmdp_local++;
msm_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
- cmdp_local++;
+ cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram0 table\n", __func__);
@@ -1902,10 +1915,9 @@
vfe32_program_dmi_cfg(ROLLOFF_RAM1_BANK0);
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- cmdp_local++;
msm_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
- cmdp_local++;
+ cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram1 table\n", __func__);
@@ -1941,12 +1953,11 @@
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- msm_io_w(*cmdp_local,
+ msm_io_w(*(cmdp_local + 1),
vfe32_ctrl->vfebase + VFE33_DMI_DATA_HI);
- cmdp_local++;
msm_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
- cmdp_local++;
+ cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram0 table\n", __func__);
@@ -1958,10 +1969,9 @@
msm_io_w(temp1, vfe32_ctrl->vfebase + VFE_DMI_ADDR);
for (i = 0 ; i < V33_PCA_ROLL_OFF_TABLE_SIZE ; i++) {
- cmdp_local++;
msm_io_w(*cmdp_local,
vfe32_ctrl->vfebase + VFE33_DMI_DATA_LO);
- cmdp_local++;
+ cmdp_local += 2;
}
CDBG("%s: end writing RollOff Ram1 table\n", __func__);
@@ -2091,8 +2101,7 @@
CDBG("stop video triggered .\n");
}
if (vfe32_ctrl->start_ack_pending == TRUE) {
- v4l2_subdev_notify(vfe32_ctrl->subdev, NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_START_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
} else {
if (vfe32_ctrl->recording_state ==
@@ -2105,9 +2114,7 @@
vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
} else if (vfe32_ctrl->recording_state ==
VFE_REC_STATE_STOPPED) {
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_STOP_REC_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_REC_ACK);
vfe32_ctrl->recording_state = VFE_REC_STATE_IDLE;
}
spin_lock_irqsave(&vfe32_ctrl->update_ack_lock, flags);
@@ -2115,9 +2122,7 @@
vfe32_ctrl->update_ack_pending = FALSE;
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_UPDATE_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_UPDATE_ACK);
} else {
spin_unlock_irqrestore(
&vfe32_ctrl->update_ack_lock, flags);
@@ -2198,9 +2203,7 @@
if (vfe32_ctrl->stop_ack_pending) {
vfe32_ctrl->stop_ack_pending = FALSE;
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_STOP_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_STOP_ACK);
} else {
spin_unlock_irqrestore(&vfe32_ctrl->stop_flag_lock, flags);
/* this is from reset command. */
@@ -2208,9 +2211,7 @@
/* reload all write masters. (frame & line)*/
msm_io_w(0x7FFF, vfe32_ctrl->vfebase + VFE_BUS_CMD);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_RESET_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_RESET_ACK);
}
}
@@ -2220,9 +2221,7 @@
if (vfe32_ctrl->operation_mode ==
VFE_MODE_OF_OPERATION_RAW_SNAPSHOT) {
if (vfe32_ctrl->start_ack_pending) {
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_START_ACK);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_START_ACK);
vfe32_ctrl->start_ack_pending = FALSE;
}
vfe32_ctrl->vfe_capture_count--;
@@ -2234,11 +2233,10 @@
vfe32_ctrl->vfebase + VFE_CAMIF_COMMAND);
}
} /* if raw snapshot mode. */
-
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_SOF_ACK);
vfe32_ctrl->vfeFrameId++;
+ if (vfe32_ctrl->vfeFrameId == 0)
+ vfe32_ctrl->vfeFrameId = 1; /* wrapped back */
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_SOF_ACK);
CDBG("camif_sof_irq, frameId = %d\n", vfe32_ctrl->vfeFrameId);
if (vfe32_ctrl->sync_timer_state) {
@@ -2259,9 +2257,7 @@
temp = (uint32_t *)(vfe32_ctrl->vfebase + VFE_CAMIF_STATUS);
camifStatus = msm_io_r(temp);
pr_err("camifStatus = 0x%x\n", camifStatus);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_CAMIF_ERROR);
+ vfe32_send_isp_msg(vfe32_ctrl, MSG_ID_CAMIF_ERROR);
}
if (errStatus & VFE32_IMASK_BHIST_OVWR)
@@ -2884,9 +2880,8 @@
CAMIF_COMMAND_STOP_IMMEDIATELY,
vfe32_ctrl->vfebase +
VFE_CAMIF_COMMAND);
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT,
- (void *)MSG_ID_SNAPSHOT_DONE);
+ vfe32_send_isp_msg(vfe32_ctrl,
+ MSG_ID_SNAPSHOT_DONE);
}
}
/* then process stats irq. */
@@ -2933,22 +2928,19 @@
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER0) {
CDBG("SYNC_TIMER 0 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER0_DONE);
}
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER1) {
CDBG("SYNC_TIMER 1 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER1_DONE);
}
if (qcmd->vfeInterruptStatus0 &
VFE_IRQ_STATUS0_SYNC_TIMER2) {
CDBG("SYNC_TIMER 2 irq occured.\n");
- v4l2_subdev_notify(vfe32_ctrl->subdev,
- NOTIFY_ISP_MSG_EVT, (void *)
+ vfe32_send_isp_msg(vfe32_ctrl,
MSG_ID_SYNC_TIMER2_DONE);
}
}
diff --git a/drivers/media/video/msm/msm_vfe32.h b/drivers/media/video/msm/msm_vfe32.h
index d3ed0e6..d763c2e 100644
--- a/drivers/media/video/msm/msm_vfe32.h
+++ b/drivers/media/video/msm/msm_vfe32.h
@@ -332,8 +332,8 @@
#define V32_DEMOSAICV3_ABF_OFF 0x000002A4
#define V32_DEMOSAICV3_ABF_LEN 180
-#define V32_EZTUNE_CFG_OFF 0x00000010
-#define V32_EZTUNE_CFG_LEN 4
+#define V32_MODULE_CFG_OFF 0x00000010
+#define V32_MODULE_CFG_LEN 4
#define V32_CLF_CFG_OFF 0x000006B0
#define V32_CLF_CFG_LEN 72
diff --git a/drivers/media/video/msm/sensors/imx074_v4l2.c b/drivers/media/video/msm/sensors/imx074_v4l2.c
index 969595d..99cc2d4 100644
--- a/drivers/media/video/msm/sensors/imx074_v4l2.c
+++ b/drivers/media/video/msm/sensors/imx074_v4l2.c
@@ -153,14 +153,18 @@
.y_output = 0xC30,
.line_length_pclk = 0x1178,
.frame_length_lines = 0xC90,
- .pixel_clk = 182400000,
+ .vt_pixel_clk = 182400000,
+ .op_pixel_clk = 182400000,
+ .binning_factor = 1,
},
{
.x_output = 0x838,
.y_output = 0x618,
.line_length_pclk = 0x1178,
.frame_length_lines = 0x62D,
- .pixel_clk = 216000000,
+ .vt_pixel_clk = 216000000,
+ .op_pixel_clk = 216000000,
+ .binning_factor = 1,
},
};
@@ -319,6 +323,7 @@
.sensor_get_pict_fps = msm_sensor_get_pict_fps,
.sensor_set_fps = msm_sensor_set_fps,
.sensor_write_exp_gain = msm_sensor_write_exp_gain1,
+ .sensor_write_snapshot_exp_gain = msm_sensor_write_exp_gain1,
.sensor_setting = msm_sensor_setting,
.sensor_set_sensor_mode = msm_sensor_set_sensor_mode,
.sensor_mode_init = msm_sensor_mode_init,
diff --git a/drivers/media/video/msm/sensors/msm_sensor.c b/drivers/media/video/msm/sensors/msm_sensor.c
index 806f763..19cf8c7 100644
--- a/drivers/media/video/msm/sensors/msm_sensor.c
+++ b/drivers/media/video/msm/sensors/msm_sensor.c
@@ -155,13 +155,15 @@
int32_t rc = 0;
s_ctrl->fps_divider = fps->fps_div;
- total_lines_per_frame = (uint16_t)
- ((s_ctrl->curr_frame_length_lines) *
- s_ctrl->fps_divider/Q10);
+ if (s_ctrl->curr_res != MSM_SENSOR_INVALID_RES) {
+ total_lines_per_frame = (uint16_t)
+ ((s_ctrl->curr_frame_length_lines) *
+ s_ctrl->fps_divider/Q10);
- rc = msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
+ rc = msm_camera_i2c_write(s_ctrl->sensor_i2c_client,
s_ctrl->sensor_output_reg_addr->frame_length_lines,
total_lines_per_frame, MSM_CAMERA_I2C_WORD_DATA);
+ }
return rc;
}
@@ -249,7 +251,7 @@
v4l2_subdev_notify(s_ctrl->sensor_v4l2_subdev,
NOTIFY_PCLK_CHANGE, &s_ctrl->msm_sensor_reg->
- output_settings[res].pixel_clk);
+ output_settings[res].op_pixel_clk);
v4l2_subdev_notify(s_ctrl->sensor_v4l2_subdev,
NOTIFY_ISPIF_STREAM, (void *)ISPIF_STREAM(
PIX0, ISPIF_ON_FRAME_BOUNDARY));
@@ -477,13 +479,13 @@
case CFG_SET_PICT_EXP_GAIN:
if (s_ctrl->func_tbl->
- sensor_write_exp_gain == NULL) {
+ sensor_write_snapshot_exp_gain == NULL) {
rc = -EFAULT;
break;
}
rc =
s_ctrl->func_tbl->
- sensor_write_exp_gain(
+ sensor_write_snapshot_exp_gain(
s_ctrl,
cdata.cfg.exp_gain.gain,
cdata.cfg.exp_gain.line);
diff --git a/drivers/media/video/msm/sensors/msm_sensor.h b/drivers/media/video/msm/sensors/msm_sensor.h
index fedd485..1121170 100644
--- a/drivers/media/video/msm/sensors/msm_sensor.h
+++ b/drivers/media/video/msm/sensors/msm_sensor.h
@@ -115,6 +115,8 @@
struct fps_cfg *);
int32_t (*sensor_write_exp_gain) (struct msm_sensor_ctrl_t *,
uint16_t, uint32_t);
+ int32_t (*sensor_write_snapshot_exp_gain) (struct msm_sensor_ctrl_t *,
+ uint16_t, uint32_t);
int32_t (*sensor_setting) (struct msm_sensor_ctrl_t *,
int update_type, int rt);
int32_t (*sensor_set_sensor_mode)
diff --git a/drivers/media/video/msm/sensors/ov2720.c b/drivers/media/video/msm/sensors/ov2720.c
index d50ea43..bdad57c 100644
--- a/drivers/media/video/msm/sensors/ov2720.c
+++ b/drivers/media/video/msm/sensors/ov2720.c
@@ -310,21 +310,27 @@
.y_output = 0x444,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
{
.x_output = 0x510,
.y_output = 0x278,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
{
.x_output = 0x298,
.y_output = 0x1F2,
.line_length_pclk = 0x85c,
.frame_length_lines = 0x460,
- .pixel_clk = 72000000,
+ .vt_pixel_clk = 72000000,
+ .op_pixel_clk = 72000000,
+ .binning_factor = 1,
},
};
@@ -479,6 +485,7 @@
.sensor_get_pict_fps = msm_sensor_get_pict_fps,
.sensor_set_fps = msm_sensor_set_fps,
.sensor_write_exp_gain = ov2720_write_exp_gain,
+ .sensor_write_snapshot_exp_gain = ov2720_write_exp_gain,
.sensor_setting = msm_sensor_setting,
.sensor_set_sensor_mode = msm_sensor_set_sensor_mode,
.sensor_mode_init = msm_sensor_mode_init,
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d291baa..a4feb838 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -155,8 +155,7 @@
config PMIC8058
tristate "PMIC8058 Power Management chip"
- depends on I2C_SSBI && (ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX)
- default y if I2C_SSBI && (ARCH_MSM7X30 || ARCH_MSM8X60 || ARCH_FSM9XXX)
+ depends on MSM_SSBI
select MFD_CORE
select MSM_SHOW_RESUME_IRQ
help
diff --git a/drivers/mfd/pm8018-core.c b/drivers/mfd/pm8018-core.c
index 4dfc4cf..1567c5b 100644
--- a/drivers/mfd/pm8018-core.c
+++ b/drivers/mfd/pm8018-core.c
@@ -39,6 +39,9 @@
#define PM8018_VERSION_VALUE 0x08F0
#define PM8018_REVISION_MASK 0x000F
+#define REG_PM8018_PON_CNTRL_3 0x01D
+#define PM8018_RESTART_REASON_MASK 0x07
+
#define SINGLE_IRQ_RESOURCE(_name, _irq) \
{ \
.name = _name, \
@@ -142,6 +145,19 @@
.num_resources = ARRAY_SIZE(gpio_cell_resources),
};
+static const struct resource adc_cell_resources[] __devinitconst = {
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_EOC_USR_IRQ),
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_BATT_TEMP_WARM_IRQ),
+ SINGLE_IRQ_RESOURCE(NULL, PM8018_ADC_BATT_TEMP_COLD_IRQ),
+};
+
+static struct mfd_cell adc_cell __devinitdata = {
+ .name = PM8XXX_ADC_DEV_NAME,
+ .id = -1,
+ .resources = adc_cell_resources,
+ .num_resources = ARRAY_SIZE(adc_cell_resources),
+};
+
static const struct resource mpp_cell_resources[] __devinitconst = {
{
.start = PM8018_IRQ_BLOCK_BIT(PM8018_MPP_BLOCK_START, 0),
@@ -280,6 +296,17 @@
}
}
+ if (pdata->adc_pdata) {
+ adc_cell.platform_data = pdata->adc_pdata;
+ adc_cell.pdata_size = sizeof(struct pm8xxx_adc_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &adc_cell, 1, NULL,
+ irq_base);
+ if (ret) {
+ pr_err("Failed to add adc subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
ret = mfd_add_devices(pmic->dev, 0, &debugfs_cell, 1, NULL, irq_base);
if (ret) {
pr_err("Failed to add debugfs subdevice ret=%d\n", ret);
@@ -325,6 +352,17 @@
return ret;
}
+static const char * const pm8018_restart_reason[] = {
+ [0] = "Unknown",
+ [1] = "Triggered from CBL (external charger)",
+ [2] = "Triggered from KPD (power key press)",
+ [3] = "Triggered from CHG (usb charger insertion)",
+ [4] = "Triggered from SMPL (sudden momentary power loss)",
+ [5] = "Triggered from RTC (real time clock)",
+ [6] = "Triggered by Hard Reset",
+ [7] = "Triggered by General Purpose Trigger",
+};
+
static const char * const pm8018_rev_names[] = {
[PM8XXX_REVISION_8018_TEST] = "test",
[PM8XXX_REVISION_8018_1p0] = "1.0",
@@ -386,6 +424,14 @@
} else {
WARN_ON(version != PM8XXX_VERSION_8018);
}
+ /* Log human readable restart reason */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_PM8018_PON_CNTRL_3, &val, 1);
+ if (rc) {
+ pr_err("Cannot read restart reason rc=%d\n", rc);
+ goto err_read_rev;
+ }
+ val &= PM8018_RESTART_REASON_MASK;
+ pr_info("PMIC Restart Reason: %s\n", pm8018_restart_reason[val]);
rc = pm8018_add_subdevices(pdata, pmic);
if (rc) {
diff --git a/drivers/mfd/pm8821-core.c b/drivers/mfd/pm8821-core.c
index 2da7055..ed29785 100644
--- a/drivers/mfd/pm8821-core.c
+++ b/drivers/mfd/pm8821-core.c
@@ -137,7 +137,7 @@
.name = "pm8xxx-debug",
.id = 1,
.platform_data = "pm8821-dbg",
- .data_size = sizeof("pm8821-dbg"),
+ .pdata_size = sizeof("pm8821-dbg"),
};
@@ -165,7 +165,7 @@
pdata->mpp_pdata->core_data.nmpps = PM8821_NR_MPPS;
pdata->mpp_pdata->core_data.base_addr = REG_MPP_BASE;
mpp_cell.platform_data = pdata->mpp_pdata;
- mpp_cell.data_size = sizeof(struct pm8xxx_mpp_platform_data);
+ mpp_cell.pdata_size = sizeof(struct pm8xxx_mpp_platform_data);
ret = mfd_add_devices(pmic->dev, 0, &mpp_cell, 1, NULL,
irq_base);
if (ret) {
diff --git a/drivers/mfd/pm8xxx-misc.c b/drivers/mfd/pm8xxx-misc.c
index cd5624f..00ac2ab 100644
--- a/drivers/mfd/pm8xxx-misc.c
+++ b/drivers/mfd/pm8xxx-misc.c
@@ -23,6 +23,7 @@
/* PON CTRL 1 register */
#define REG_PM8058_PON_CTRL_1 0x01C
#define REG_PM8921_PON_CTRL_1 0x01C
+#define REG_PM8018_PON_CTRL_1 0x01C
#define PON_CTRL_1_PULL_UP_MASK 0xE0
#define PON_CTRL_1_USB_PWR_EN 0x10
@@ -37,6 +38,7 @@
/* SLEEP CTRL register */
#define REG_PM8058_SLEEP_CTRL 0x02B
#define REG_PM8921_SLEEP_CTRL 0x10A
+#define REG_PM8018_SLEEP_CTRL 0x10A
#define SLEEP_CTRL_SMPL_EN_MASK 0x04
#define SLEEP_CTRL_SMPL_EN_RESET 0x04
@@ -81,6 +83,35 @@
return rc;
}
+static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
+{
+ int rc;
+
+ /* Enable SMPL if resetting is desired. */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL,
+ SLEEP_CTRL_SMPL_EN_MASK,
+ (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF));
+ if (rc) {
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+ return rc;
+ }
+
+ /*
+ * Select action to perform (reset or shutdown) when PS_HOLD goes low.
+ * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that
+ * USB charging is enabled.
+ */
+ rc = pm8xxx_misc_masked_write(chip, REG_PM8018_PON_CTRL_1,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | PON_CTRL_1_WD_EN_MASK,
+ PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN
+ | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF));
+ if (rc)
+ pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc);
+
+ return rc;
+}
+
static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset)
{
int rc;
@@ -201,6 +232,9 @@
/* Loop over all attached PMICs and call specific functions for them. */
list_for_each_entry(chip, &pm8xxx_misc_chips, link) {
switch (chip->version) {
+ case PM8XXX_VERSION_8018:
+ rc = __pm8018_reset_pwr_off(chip, reset);
+ break;
case PM8XXX_VERSION_8058:
rc = __pm8058_reset_pwr_off(chip, reset);
break;
diff --git a/drivers/mfd/pmic8058.c b/drivers/mfd/pmic8058.c
index 7f433db..85c8a9d 100644
--- a/drivers/mfd/pmic8058.c
+++ b/drivers/mfd/pmic8058.c
@@ -20,6 +20,7 @@
#include <linux/slab.h>
#include <linux/ratelimit.h>
#include <linux/kthread.h>
+#include <linux/msm_ssbi.h>
#include <linux/mfd/core.h>
#include <linux/mfd/pmic8058.h>
#include <linux/platform_device.h>
@@ -28,6 +29,7 @@
#include <linux/debugfs.h>
#include <linux/irq.h>
#include <linux/syscore_ops.h>
+#include <linux/gpio.h>
/* PMIC8058 Revision */
#define SSBI_REG_REV 0x002 /* PMIC4 revision */
@@ -143,8 +145,7 @@
struct pm8058_chip {
struct pm8058_platform_data pdata;
-
- struct i2c_client *dev;
+ struct device *dev;
u8 irqs_allowed[MAX_PM_BLOCKS];
u8 blocks_allowed[MAX_PM_MASTERS];
@@ -185,33 +186,15 @@
}
static inline int
-ssbi_write(struct i2c_client *client, u16 addr, const u8 *buf, size_t len)
+ssbi_read(struct device *dev, u16 addr, u8 *buf, size_t len)
{
- int rc;
- struct i2c_msg msg = {
- .addr = addr,
- .flags = 0x0,
- .buf = (u8 *)buf,
- .len = len,
- };
-
- rc = i2c_transfer(client->adapter, &msg, 1);
- return (rc == 1) ? 0 : rc;
+ return msm_ssbi_read(dev->parent, addr, buf, len);
}
static inline int
-ssbi_read(struct i2c_client *client, u16 addr, u8 *buf, size_t len)
+ssbi_write(struct device *dev, u16 addr, u8 *buf, size_t len)
{
- int rc;
- struct i2c_msg msg = {
- .addr = addr,
- .flags = I2C_M_RD,
- .buf = buf,
- .len = len,
- };
-
- rc = i2c_transfer(client->adapter, &msg, 1);
- return (rc == 1) ? 0 : rc;
+ return msm_ssbi_write(dev->parent, addr, buf, len);
}
static int pm8058_masked_write(u16 addr, u8 val, u8 mask)
@@ -1318,7 +1301,7 @@
}
if (!chip->count_wakeable)
- disable_irq(chip->dev->irq);
+ disable_irq(chip->pdata.irq);
return 0;
}
@@ -1368,7 +1351,7 @@
}
if (!chip->count_wakeable)
- enable_irq(chip->dev->irq);
+ enable_irq(chip->pdata.irq);
}
static struct syscore_ops pm8058_pm = {
@@ -1376,14 +1359,13 @@
.resume = pm8058_resume,
};
-static int pm8058_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int __devinit pm8058_probe(struct platform_device *pdev)
{
int i, rc;
- struct pm8058_platform_data *pdata = client->dev.platform_data;
+ struct pm8058_platform_data *pdata = pdev->dev.platform_data;
struct pm8058_chip *chip;
- if (pdata == NULL || !client->irq) {
+ if (pdata == NULL || !gpio_is_valid(pdata->irq)) {
pr_err("%s: No platform_data or IRQ.\n", __func__);
return -ENODEV;
}
@@ -1393,18 +1375,13 @@
return -ENODEV;
}
- if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
- pr_err("%s: i2c_check_functionality failed.\n", __func__);
- return -ENODEV;
- }
-
chip = kzalloc(sizeof *chip, GFP_KERNEL);
if (chip == NULL) {
pr_err("%s: kzalloc() failed.\n", __func__);
return -ENOMEM;
}
- chip->dev = client;
+ chip->dev = &pdev->dev;
/* Read PMIC chip revision */
rc = ssbi_read(chip->dev, SSBI_REG_REV, &chip->revision, 1);
@@ -1417,14 +1394,14 @@
sizeof(chip->pdata));
mutex_init(&chip->pm_lock);
- irq_set_handler_data(chip->dev->irq, (void *)chip);
- irq_set_irq_wake(chip->dev->irq, 1);
+ irq_set_handler_data(pdata->irq, (void *)chip);
+ irq_set_irq_wake(pdata->irq, 1);
chip->pm_max_irq = 0;
chip->pm_max_blocks = 0;
chip->pm_max_masters = 0;
- i2c_set_clientdata(client, chip);
+ platform_set_drvdata(pdev, chip);
pmic_chip = chip;
@@ -1437,12 +1414,12 @@
irq_set_nested_thread(i, 1);
}
- rc = mfd_add_devices(&chip->dev->dev, 0, pdata->sub_devices,
+ rc = mfd_add_devices(chip->dev, 0, pdata->sub_devices,
pdata->num_subdevs, NULL, 0);
/* Add charger sub device with the chip parameter as driver data */
if (pdata->charger_sub_device) {
- rc = mfd_add_devices(&chip->dev->dev, 0,
+ rc = mfd_add_devices(chip->dev, 0,
pdata->charger_sub_device,
1, NULL, 0);
}
@@ -1457,12 +1434,12 @@
}
}
- rc = request_threaded_irq(chip->dev->irq, NULL, pm8058_isr_thread,
+ rc = request_threaded_irq(pdata->irq, NULL, pm8058_isr_thread,
IRQF_ONESHOT | IRQF_DISABLED | pdata->irq_trigger_flags,
"pm8058-irq", chip);
if (rc < 0)
pr_err("%s: could not request irq %d: %d\n", __func__,
- chip->dev->irq, rc);
+ pdata->irq, rc);
rc = pmic8058_dbg_probe(chip);
if (rc < 0)
@@ -1478,15 +1455,15 @@
return 0;
}
-static int __devexit pm8058_remove(struct i2c_client *client)
+static int __devexit pm8058_remove(struct platform_device *pdev)
{
struct pm8058_chip *chip;
- chip = i2c_get_clientdata(client);
+ chip = platform_get_drvdata(pdev);
if (chip) {
if (chip->pm_max_irq) {
- irq_set_irq_wake(chip->dev->irq, 0);
- free_irq(chip->dev->irq, chip);
+ irq_set_irq_wake(chip->pdata.irq, 0);
+ free_irq(chip->pdata.irq, chip);
}
mutex_destroy(&chip->pm_lock);
chip->dev = NULL;
@@ -1499,33 +1476,25 @@
return 0;
}
-static const struct i2c_device_id pm8058_ids[] = {
- { "pm8058-core", 0 },
- { },
-};
-MODULE_DEVICE_TABLE(i2c, pm8058_ids);
-
-static struct i2c_driver pm8058_driver = {
- .driver.name = "pm8058-core",
- .id_table = pm8058_ids,
+static struct platform_driver pm8058_driver = {
.probe = pm8058_probe,
.remove = __devexit_p(pm8058_remove),
+ .driver = {
+ .name = "pm8058-core",
+ .owner = THIS_MODULE,
+ },
};
static int __init pm8058_init(void)
{
- int rc = i2c_add_driver(&pm8058_driver);
- pr_notice("%s: i2c_add_driver: rc = %d\n", __func__, rc);
-
- return rc;
+ return platform_driver_register(&pm8058_driver);
}
+arch_initcall(pm8058_init);
static void __exit pm8058_exit(void)
{
- i2c_del_driver(&pm8058_driver);
+ platform_driver_unregister(&pm8058_driver);
}
-
-arch_initcall(pm8058_init);
module_exit(pm8058_exit);
MODULE_LICENSE("GPL v2");
diff --git a/drivers/misc/eeprom/eeprom_93cx6.c b/drivers/misc/eeprom/eeprom_93cx6.c
index 7b33de9..6ffe9e7 100644
--- a/drivers/misc/eeprom/eeprom_93cx6.c
+++ b/drivers/misc/eeprom/eeprom_93cx6.c
@@ -63,6 +63,7 @@
eeprom->reg_data_out = 0;
eeprom->reg_data_clock = 0;
eeprom->reg_chip_select = 1;
+ eeprom->drive_data = 1;
eeprom->register_write(eeprom);
/*
@@ -101,6 +102,7 @@
*/
eeprom->reg_data_in = 0;
eeprom->reg_data_out = 0;
+ eeprom->drive_data = 1;
/*
* Start writing all bits.
@@ -140,6 +142,7 @@
*/
eeprom->reg_data_in = 0;
eeprom->reg_data_out = 0;
+ eeprom->drive_data = 0;
/*
* Start reading all bits.
@@ -231,3 +234,89 @@
}
EXPORT_SYMBOL_GPL(eeprom_93cx6_multiread);
+
+/**
+ * eeprom_93cx6_wren - set the write enable state
+ * @eeprom: Pointer to eeprom structure
+ * @enable: true to enable writes, otherwise disable writes
+ *
+ * Set the EEPROM write enable state to either allow or deny
+ * writes depending on the @enable value.
+ */
+void eeprom_93cx6_wren(struct eeprom_93cx6 *eeprom, bool enable)
+{
+ u16 command;
+
+ /* start the command */
+ eeprom_93cx6_startup(eeprom);
+
+ /* create command to enable/disable */
+
+ command = enable ? PCI_EEPROM_EWEN_OPCODE : PCI_EEPROM_EWDS_OPCODE;
+ command <<= (eeprom->width - 2);
+
+ eeprom_93cx6_write_bits(eeprom, command,
+ PCI_EEPROM_WIDTH_OPCODE + eeprom->width);
+
+ eeprom_93cx6_cleanup(eeprom);
+}
+EXPORT_SYMBOL_GPL(eeprom_93cx6_wren);
+
+/**
+ * eeprom_93cx6_write - write data to the EEPROM
+ * @eeprom: Pointer to eeprom structure
+ * @addr: Address to write data to.
+ * @data: The data to write to address @addr.
+ *
+ * Write the @data to the specified @addr in the EEPROM and
+ * waiting for the device to finish writing.
+ *
+ * Note, since we do not expect large number of write operations
+ * we delay in between parts of the operation to avoid using excessive
+ * amounts of CPU time busy waiting.
+ */
+void eeprom_93cx6_write(struct eeprom_93cx6 *eeprom, u8 addr, u16 data)
+{
+ int timeout = 100;
+ u16 command;
+
+ /* start the command */
+ eeprom_93cx6_startup(eeprom);
+
+ command = PCI_EEPROM_WRITE_OPCODE << eeprom->width;
+ command |= addr;
+
+ /* send write command */
+ eeprom_93cx6_write_bits(eeprom, command,
+ PCI_EEPROM_WIDTH_OPCODE + eeprom->width);
+
+ /* send data */
+ eeprom_93cx6_write_bits(eeprom, data, 16);
+
+ /* get ready to check for busy */
+ eeprom->drive_data = 0;
+ eeprom->reg_chip_select = 1;
+ eeprom->register_write(eeprom);
+
+ /* wait at-least 250ns to get DO to be the busy signal */
+ usleep_range(1000, 2000);
+
+ /* wait for DO to go high to signify finish */
+
+ while (true) {
+ eeprom->register_read(eeprom);
+
+ if (eeprom->reg_data_out)
+ break;
+
+ usleep_range(1000, 2000);
+
+ if (--timeout <= 0) {
+ printk(KERN_ERR "%s: timeout\n", __func__);
+ break;
+ }
+ }
+
+ eeprom_93cx6_cleanup(eeprom);
+}
+EXPORT_SYMBOL_GPL(eeprom_93cx6_write);
diff --git a/drivers/misc/pmic8058-xoadc.c b/drivers/misc/pmic8058-xoadc.c
index d2d8cba..f21668a 100644
--- a/drivers/misc/pmic8058-xoadc.c
+++ b/drivers/misc/pmic8058-xoadc.c
@@ -23,6 +23,7 @@
#include <linux/slab.h>
#include <linux/ratelimit.h>
#include <linux/delay.h>
+#include <linux/wakelock.h>
#include <mach/mpp.h>
#include <mach/msm_xo.h>
@@ -65,6 +66,9 @@
struct adc_conv_slot conv_queue_elements[MAX_QUEUE_LENGTH];
int xoadc_num;
struct msm_xo_voter *adc_voter;
+ struct wake_lock adc_wakelock;
+ /* flag to warn/bug if wakelocks are taken after suspend_noirq */
+ int msm_suspend_check;
};
static struct pmic8058_adc *pmic_adc[XOADC_PMIC_0 + 1];
@@ -117,7 +121,7 @@
EXPORT_SYMBOL(pm8058_xoadc_slot_request);
static int32_t pm8058_xoadc_arb_cntrl(uint32_t arb_cntrl,
- uint32_t adc_instance)
+ uint32_t adc_instance, uint32_t channel)
{
struct pmic8058_adc *adc_pmic = pmic_adc[adc_instance];
int i, rc;
@@ -128,9 +132,13 @@
ADC_ARB_USRP_CNTRL_RSV4;
if (arb_cntrl) {
+ if (adc_pmic->msm_suspend_check)
+ pr_err("XOADC request being made after suspend irq "
+ "with channel id:%d\n", channel);
data_arb_cntrl |= ADC_ARB_USRP_CNTRL_EN_ARB;
msm_xo_mode_vote(adc_pmic->adc_voter, MSM_XO_MODE_ON);
adc_pmic->pdata->xoadc_mpp_config();
+ wake_lock(&adc_pmic->adc_wakelock);
}
/* Write twice to the CNTRL register for the arbiter settings
@@ -144,8 +152,10 @@
}
}
- if (!arb_cntrl)
+ if (!arb_cntrl) {
msm_xo_mode_vote(adc_pmic->adc_voter, MSM_XO_MODE_OFF);
+ wake_unlock(&adc_pmic->adc_wakelock);
+ }
return 0;
}
@@ -159,7 +169,7 @@
u8 data_dig_param, data_ana_param2;
int rc;
- rc = pm8058_xoadc_arb_cntrl(1, adc_instance);
+ rc = pm8058_xoadc_arb_cntrl(1, adc_instance, slot->chan_path);
if (rc < 0) {
pr_debug("%s: Configuring ADC Arbiter"
"enable failed\n", __func__);
@@ -461,7 +471,7 @@
/* Default value for switching off the arbiter after reading
the ADC value. Bit 0 set to 0. */
if (adc_pmic->xoadc_queue_count == 0) {
- rc = pm8058_xoadc_arb_cntrl(0, adc_instance);
+ rc = pm8058_xoadc_arb_cntrl(0, adc_instance, CHANNEL_MUXOFF);
if (rc < 0) {
pr_debug("%s: Configuring ADC Arbiter disable"
"failed\n", __func__);
@@ -607,6 +617,37 @@
}
EXPORT_SYMBOL(pm8058_xoadc_calibrate);
+#ifdef CONFIG_PM
+static int pm8058_xoadc_suspend_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pmic8058_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 1;
+
+ return 0;
+}
+
+static int pm8058_xoadc_resume_noirq(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct pmic8058_adc *adc_pmic = platform_get_drvdata(pdev);
+
+ adc_pmic->msm_suspend_check = 0;
+
+ return 0;
+}
+
+static const struct dev_pm_ops pm8058_xoadc_dev_pm_ops = {
+ .suspend_noirq = pm8058_xoadc_suspend_noirq,
+ .resume_noirq = pm8058_xoadc_resume_noirq,
+};
+
+#define PM8058_XOADC_DEV_PM_OPS (&pm8058_xoadc_dev_pm_ops)
+#else
+#define PM8058_XOADC_DEV_PM_OPS NULL
+#endif
+
static int __devexit pm8058_xoadc_teardown(struct platform_device *pdev)
{
struct pmic8058_adc *adc_pmic = platform_get_drvdata(pdev);
@@ -614,6 +655,7 @@
if (adc_pmic->pdata->xoadc_vreg_shutdown != NULL)
adc_pmic->pdata->xoadc_vreg_shutdown();
+ wake_lock_destroy(&adc_pmic->adc_wakelock);
msm_xo_put(adc_pmic->adc_voter);
platform_set_drvdata(pdev, adc_pmic->pm_chip);
device_init_wakeup(&pdev->dev, 0);
@@ -728,6 +770,9 @@
}
}
+ wake_lock_init(&adc_pmic->adc_wakelock, WAKE_LOCK_SUSPEND,
+ "pmic8058_xoadc_wakelock");
+
pmic_adc[adc_pmic->xoadc_num] = adc_pmic;
if (pdata->xoadc_vreg_setup != NULL)
@@ -750,6 +795,7 @@
.driver = {
.name = "pm8058-xoadc",
.owner = THIS_MODULE,
+ .pm = PM8058_XOADC_DEV_PM_OPS,
},
};
diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c
index 74b6ac2..e338aed 100644
--- a/drivers/net/ks8851.c
+++ b/drivers/net/ks8851.c
@@ -1723,8 +1723,6 @@
err_id:
err_irq:
- free_netdev(ndev);
-
if (!IS_ERR(ks->vdd_io)) {
regulator_disable(ks->vdd_io);
regulator_put(ks->vdd_io);
@@ -1735,6 +1733,8 @@
regulator_put(ks->vdd_phy);
}
+ free_netdev(ndev);
+
if (pdata && gpio_is_valid(pdata->rst_gpio))
gpio_free(pdata->rst_gpio);
diff --git a/drivers/net/wireless/libra/qcomwlan_pwrif.c b/drivers/net/wireless/libra/qcomwlan_pwrif.c
index 721e9c3..de8b918 100644
--- a/drivers/net/wireless/libra/qcomwlan_pwrif.c
+++ b/drivers/net/wireless/libra/qcomwlan_pwrif.c
@@ -42,6 +42,15 @@
"8058_s2",
"8058_s1",
};
+ static const char *vregs_qwlan_pc_name[] = {
+ "8058_l20_pc",
+ "8058_l8_pc",
+ NULL,
+ NULL,
+ "8901_l0_pc",
+ "8058_s2_pc",
+ NULL,
+ };
static const int vregs_qwlan_val_min[] = {
1800000,
3050000,
@@ -80,6 +89,7 @@
};
bool const *vregs_is_pin_controlled;
static struct regulator *vregs_qwlan[ARRAY_SIZE(vregs_qwlan_name)];
+ static struct regulator *vregs_pc_qwlan[ARRAY_SIZE(vregs_qwlan_name)];
static struct msm_xo_voter *wlan_clock;
int ret, i, rc = 0;
unsigned wlan_gpio_deep_sleep = GPIO_WLAN_DEEP_SLEEP_N;
@@ -157,11 +167,14 @@
}
/* vote for pin control (if needed) */
if (vregs_is_pin_controlled[i]) {
- rc = regulator_set_mode(vregs_qwlan[i],
- REGULATOR_MODE_IDLE);
- if (rc) {
- pr_err("regulator_set_mode(%s) failed\n",
- vregs_qwlan_name[i]);
+ vregs_pc_qwlan[i] = regulator_get(NULL,
+ vregs_qwlan_pc_name[i]);
+ if (IS_ERR(vregs_pc_qwlan[i])) {
+ pr_err("regulator get of %s failed "
+ "(%ld)\n",
+ vregs_qwlan_pc_name[i],
+ PTR_ERR(vregs_pc_qwlan[i]));
+ rc = PTR_ERR(vregs_pc_qwlan[i]);
goto vreg_fail;
}
}
@@ -173,7 +186,23 @@
vregs_qwlan_name[i], rc);
goto vreg_fail;
}
+ if (vregs_is_pin_controlled[i]) {
+ rc = regulator_enable(vregs_pc_qwlan[i]);
+ if (rc < 0) {
+ pr_err("vreg %s enable failed (%d)\n",
+ vregs_qwlan_pc_name[i], rc);
+ goto vreg_fail;
+ }
+ }
} else if (!on && wlan_on) {
+ if (vregs_is_pin_controlled[i]) {
+ rc = regulator_disable(vregs_pc_qwlan[i]);
+ if (rc < 0) {
+ pr_err("vreg %s disable failed (%d)\n",
+ vregs_qwlan_pc_name[i], rc);
+ goto vreg_fail;
+ }
+ }
rc = regulator_disable(vregs_qwlan[i]);
if (rc < 0) {
pr_err("vreg %s disable failed (%d)\n",
@@ -192,6 +221,8 @@
vreg_fail:
regulator_put(vregs_qwlan[i]);
+ if (vregs_is_pin_controlled[i])
+ regulator_put(vregs_pc_qwlan[i]);
vreg_get_fail:
i--;
while (i >= 0) {
@@ -202,7 +233,18 @@
vregs_qwlan_name[i],
!on ? "enable" : "disable", ret);
}
+ if (vregs_is_pin_controlled[i]) {
+ ret = !on ? regulator_enable(vregs_pc_qwlan[i]) :
+ regulator_disable(vregs_pc_qwlan[i]);
+ if (ret < 0) {
+ pr_err("vreg %s %s failed (%d) in err path\n",
+ vregs_qwlan_pc_name[i],
+ !on ? "enable" : "disable", ret);
+ }
+ }
regulator_put(vregs_qwlan[i]);
+ if (vregs_is_pin_controlled[i])
+ regulator_put(vregs_pc_qwlan[i]);
i--;
}
if (!on)
diff --git a/drivers/net/wireless/wcnss/wcnss_wlan.c b/drivers/net/wireless/wcnss/wcnss_wlan.c
index e6945d5..c16632e 100644
--- a/drivers/net/wireless/wcnss/wcnss_wlan.c
+++ b/drivers/net/wireless/wcnss/wcnss_wlan.c
@@ -85,8 +85,10 @@
static int __devinit
wcnss_wlan_ctrl_probe(struct platform_device *pdev)
{
- if (penv)
- penv->smd_channel_ready = 1;
+ if (!penv)
+ return -ENODEV;
+
+ penv->smd_channel_ready = 1;
pr_info("%s: SMD ctrl channel up\n", __func__);
diff --git a/drivers/platform/msm/ssbi.c b/drivers/platform/msm/ssbi.c
index b4fd02e..8a6dbf7 100644
--- a/drivers/platform/msm/ssbi.c
+++ b/drivers/platform/msm/ssbi.c
@@ -62,6 +62,15 @@
#define SSBI_TIMEOUT_US 100
+/* SSBI_FSM Read and Write commands for the FSM9xxx SSBI implementation */
+#define SSBI_FSM_CMD_REG_ADDR_SHFT (0x08)
+
+#define SSBI_FSM_CMD_READ(AD) \
+ (SSBI_CMD_RDWRN | (((AD) & 0xFFFF) << SSBI_FSM_CMD_REG_ADDR_SHFT))
+
+#define SSBI_FSM_CMD_WRITE(AD, DT) \
+ ((((AD) & 0xFFFF) << SSBI_FSM_CMD_REG_ADDR_SHFT) | ((DT) & 0xFF))
+
struct msm_ssbi {
struct device *dev;
struct device *slave;
@@ -113,6 +122,11 @@
ssbi_writel(ssbi, mode2, SSBI2_MODE2);
}
+ if (ssbi->controller_type == FSM_SBI_CTRL_SSBI)
+ cmd = SSBI_FSM_CMD_READ(addr);
+ else
+ cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
+
while (len) {
ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
if (ret)
@@ -146,7 +160,13 @@
if (ret)
goto err;
- ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
+ if (ssbi->controller_type == FSM_SBI_CTRL_SSBI)
+ ssbi_writel(ssbi, SSBI_FSM_CMD_WRITE(addr, *buf),
+ SSBI2_CMD);
+ else
+ ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf,
+ SSBI2_CMD);
+
ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
if (ret)
goto err;
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index da7c6fd..e666bfc 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -87,6 +87,7 @@
unsigned int batt_id_channel;
unsigned int pmic_bms_irq[PM_BMS_MAX_INTS];
DECLARE_BITMAP(enabled_irqs, PM_BMS_MAX_INTS);
+ spinlock_t bms_output_lock;
};
static struct pm8921_bms_chip *the_chip;
@@ -156,6 +157,32 @@
return 0;
}
+#define HOLD_OREG_DATA BIT(1)
+static int pm_bms_lock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA,
+ HOLD_OREG_DATA);
+ if (rc) {
+ pr_err("couldnt lock bms output rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int pm_bms_unlock_output_data(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ rc = pm_bms_masked_write(chip, BMS_CONTROL, HOLD_OREG_DATA, 0);
+ if (rc) {
+ pr_err("fail to unlock BMS_CONTROL rc = %d\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
#define SELECT_OUTPUT_DATA 0x1C
#define SELECT_OUTPUT_TYPE_SHIFT 2
#define OCV_FOR_RBATT 0x0
@@ -182,6 +209,18 @@
pr_err("invalid type %d asked to read\n", type);
return -EINVAL;
}
+
+ /* make sure the bms registers are locked */
+ rc = pm8xxx_readb(chip->dev->parent, BMS_CONTROL, ®);
+ if (rc) {
+ pr_err("fail to read BMS_OUTPUT0 for type %d rc = %d\n",
+ type, rc);
+ return rc;
+ }
+
+ /* Output register data must be held (locked) while reading output */
+ WARN_ON(!(reg && HOLD_OREG_DATA));
+
rc = pm_bms_masked_write(chip, BMS_CONTROL, SELECT_OUTPUT_DATA,
type << SELECT_OUTPUT_TYPE_SHIFT);
if (rc) {
@@ -647,6 +686,49 @@
return result;
}
+static int get_battery_uvolts(struct pm8921_bms_chip *chip, int *uvolts)
+{
+ int rc;
+ struct pm8921_adc_chan_result result;
+
+ rc = pm8921_adc_read(chip->vbat_channel, &result);
+ if (rc) {
+ pr_err("error reading adc channel = %d, rc = %d\n",
+ chip->vbat_channel, rc);
+ return rc;
+ }
+ pr_debug("mvolts phy = %lld meas = 0x%llx", result.physical,
+ result.measurement);
+ *uvolts = (int)result.physical;
+ *uvolts = *uvolts * 1000;
+ return 0;
+}
+
+static int adc_based_ocv(struct pm8921_bms_chip *chip, int *ocv)
+{
+ int vbatt, rbatt, ibatt, rc;
+
+ rc = get_battery_uvolts(chip, &vbatt);
+ if (rc) {
+ pr_err("failed to read vbatt from adc rc = %d\n", rc);
+ last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
+ return rc;
+ }
+
+ rc = pm8921_bms_get_battery_current(&ibatt);
+ if (rc) {
+ pr_err("failed to read batt current rc = %d\n", rc);
+ last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
+ return rc;
+ }
+
+ rbatt = calculate_rbatt(the_chip);
+ if (rbatt < 0)
+ rbatt = DEFAULT_RBATT_MOHMS;
+ *ocv = vbatt + ibatt * rbatt;
+ return 0;
+}
+
static int calculate_pc(struct pm8921_bms_chip *chip, int ocv_uv, int batt_temp,
int chargecycles)
{
@@ -680,24 +762,6 @@
*val = cc_mah;
}
-static int get_battery_uvolts(struct pm8921_bms_chip *chip, int *uvolts)
-{
- int rc;
- struct pm8921_adc_chan_result result;
-
- rc = pm8921_adc_read(chip->vbat_channel, &result);
- if (rc) {
- pr_err("error reading adc channel = %d, rc = %d\n",
- chip->vbat_channel, rc);
- return rc;
- }
- pr_debug("mvolts phy = %lld meas = 0x%llx", result.physical,
- result.measurement);
- *uvolts = (int)result.physical;
- *uvolts = *uvolts * 1000;
- return 0;
-}
-
static int calculate_unusable_charge_mah(struct pm8921_bms_chip *chip,
int fcc, int batt_temp, int chargecycles)
{
@@ -754,11 +818,16 @@
int64_t *cc_mah)
{
int coulumb_counter;
+ unsigned long flags;
*fcc = calculate_fcc(chip, batt_temp, chargecycles);
pr_debug("FCC = %umAh batt_temp = %d, cycles = %d",
*fcc, batt_temp, chargecycles);
+ /* fcc doesnt need to be read from hardware, lock the bms now */
+ spin_lock_irqsave(&chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(chip);
+
*unusable_charge = calculate_unusable_charge_mah(chip, *fcc,
batt_temp, chargecycles);
@@ -771,6 +840,9 @@
/* calculate cc milli_volt_hour */
calculate_cc_mah(chip, cc_mah, &coulumb_counter);
+
+ pm_bms_unlock_output_data(chip);
+ spin_unlock_irqrestore(&chip->bms_output_lock, flags);
pr_debug("cc_mah = %lldmAh cc = %d\n", *cc_mah, coulumb_counter);
}
@@ -798,6 +870,9 @@
* - unusable charge (due to battery resistance)
* SOC% = (remaining usable charge/ fcc - usable_charge);
*/
+#define BMS_BATT_NOMINAL 3700000
+#define MIN_OPERABLE_SOC 10
+#define BATTERY_POWER_SUPPLY_SOC 53
static int calculate_state_of_charge(struct pm8921_bms_chip *chip,
int batt_temp, int chargecycles)
{
@@ -815,25 +890,42 @@
/* calculate remaining usable charge */
remaining_usable_charge = remaining_charge - cc_mah - unusable_charge;
pr_debug("RUC = %dmAh\n", remaining_usable_charge);
- if (remaining_usable_charge < 0) {
+ soc = (remaining_usable_charge * 100) / (fcc - unusable_charge);
+ if (soc > 100)
+ soc = 100;
+ pr_debug("SOC = %u%%\n", soc);
+
+ if (soc < MIN_OPERABLE_SOC) {
+ int ocv = 0, rc;
+
+ rc = adc_based_ocv(chip, &ocv);
+ if (rc == 0 && ocv >= BMS_BATT_NOMINAL) {
+ /*
+ * The ocv doesnt seem to have dropped for
+ * soc to go negative.
+ * The setup must be using a power supply
+ * instead of real batteries.
+ * Fake high enough soc to prevent userspace
+ * shutdown for low battery
+ */
+ soc = BATTERY_POWER_SUPPLY_SOC;
+ pr_debug("Adjusting SOC to %d\n", soc);
+ }
+ }
+
+ if (soc < 0) {
pr_err("bad rem_usb_chg = %d rem_chg %d,"
"cc_mah %lld, unusb_chg %d\n",
remaining_usable_charge, remaining_charge,
cc_mah, unusable_charge);
pr_err("for bad rem_usb_chg last_ocv_uv = %d"
- "chargecycles = %d, batt_temp = %d\n",
- last_ocv_uv, chargecycles, batt_temp);
+ "chargecycles = %d, batt_temp = %d"
+ "fcc = %d soc =%d\n",
+ last_ocv_uv, chargecycles, batt_temp,
+ fcc, soc);
update_userspace = 0;
}
- soc = (remaining_usable_charge * 100) / (fcc - unusable_charge);
- if (soc > 100 || soc < 0) {
- pr_err("bad soc rem_usb_chg %d fcc %d unusb_chg %d\n",
- remaining_usable_charge, fcc, unusable_charge);
- update_userspace = 0;
- }
- pr_debug("SOC = %u%%\n", soc);
-
if (update_userspace) {
last_soc = soc;
}
@@ -901,16 +993,26 @@
int pm8921_bms_get_vsense_avg(int *result)
{
- if (the_chip)
- return read_vsense_avg(the_chip, result);
+ int rc = -EINVAL;
+ unsigned long flags;
+
+ if (the_chip) {
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
+ rc = read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
+ }
pr_err("called before initialization\n");
- return -EINVAL;
+ return rc;
}
EXPORT_SYMBOL(pm8921_bms_get_vsense_avg);
int pm8921_bms_get_battery_current(int *result)
{
+ unsigned long flags;
+
if (!the_chip) {
pr_err("called before initialization\n");
return -EINVAL;
@@ -920,7 +1022,11 @@
return -EINVAL;
}
+ spin_lock_irqsave(&the_chip->bms_output_lock, flags);
+ pm_bms_lock_output_data(the_chip);
read_vsense_avg(the_chip, result);
+ pm_bms_unlock_output_data(the_chip);
+ spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
pr_debug("vsense=%d\n", *result);
/* cast for signed division */
*result = *result / (int)the_chip->r_sense;
@@ -1163,7 +1269,7 @@
static void check_initial_ocv(struct pm8921_bms_chip *chip)
{
- int ocv, vbatt, rbatt, ibatt, rc;
+ int ocv, rc;
/*
* Check if a last_good_ocv is available,
@@ -1171,24 +1277,8 @@
*/
rc = read_last_good_ocv(chip, &ocv);
if (rc || ocv == 0) {
- rc = get_battery_uvolts(chip, &vbatt);
- if (rc) {
- pr_err("failed to read vbatt from adc rc = %d\n", rc);
- last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
- return;
- }
-
- rc = pm8921_bms_get_battery_current(&ibatt);
- if (rc) {
- pr_err("failed to read batt current rc = %d\n", rc);
- last_ocv_uv = DEFAULT_OCV_MICROVOLTS;
- return;
- }
-
- rbatt = calculate_rbatt(the_chip);
- if (rbatt < 0)
- rbatt = DEFAULT_RBATT_MOHMS;
- last_ocv_uv = vbatt + ibatt * rbatt;
+ rc = adc_based_ocv(chip, &last_ocv_uv);
+ pr_err("failed to read ocv from adc and bms rc = %d\n", rc);
}
pr_debug("ocv = %d last_ocv_uv = %d\n", ocv, last_ocv_uv);
}
@@ -1498,7 +1588,7 @@
pr_err("Cannot allocate pm_bms_chip\n");
return -ENOMEM;
}
-
+ spin_lock_init(&chip->bms_output_lock);
chip->dev = &pdev->dev;
chip->r_sense = pdata->r_sense;
chip->i_test = pdata->i_test;
diff --git a/drivers/regulator/pm8058-xo.c b/drivers/regulator/pm8058-xo.c
index ac65395..581e228 100644
--- a/drivers/regulator/pm8058-xo.c
+++ b/drivers/regulator/pm8058-xo.c
@@ -154,7 +154,7 @@
return -EINVAL;
if (pdev->id >= 0 && pdev->id < PM8058_XO_ID_MAX) {
- chip = platform_get_drvdata(pdev);
+ chip = dev_get_drvdata(pdev->dev.parent);
rdesc = &pm8058_xo_buffer_desc[pdev->id];
xo = &pm8058_xo_buffer[pdev->id];
xo->pdata = pdev->dev.platform_data;
@@ -163,6 +163,7 @@
if (rc)
goto bail;
+ platform_set_drvdata(pdev, chip);
xo->rdev = regulator_register(rdesc, &pdev->dev,
&xo->pdata->init_data, xo);
if (IS_ERR(xo->rdev)) {
diff --git a/drivers/regulator/pmic8058-regulator.c b/drivers/regulator/pmic8058-regulator.c
index 98ba163..c11f32b 100644
--- a/drivers/regulator/pmic8058-regulator.c
+++ b/drivers/regulator/pmic8058-regulator.c
@@ -1690,7 +1690,7 @@
return -EINVAL;
if (pdev->id >= 0 && pdev->id < PM8058_VREG_MAX) {
- chip = platform_get_drvdata(pdev);
+ chip = dev_get_drvdata(pdev->dev.parent);
rdesc = &pm8058_vreg_descrip[pdev->id];
vreg = &pm8058_vreg[pdev->id];
vreg->pdata = pdev->dev.platform_data;
@@ -1705,6 +1705,7 @@
vreg->pdata->init_data.constraints.valid_modes_mask
&= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE);
+ platform_set_drvdata(pdev, chip);
vreg->rdev = regulator_register(rdesc, &pdev->dev,
&vreg->pdata->init_data, vreg);
if (IS_ERR(vreg->rdev)) {
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index 0bdb89e..e53374e 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -30,6 +30,8 @@
/* RTC_CTRL register bit fields */
#define PM8xxx_RTC_ENABLE BIT(7)
#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
+#define PM8xxx_RTC_ABORT_ENABLE BIT(0)
+
#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
#define NUM_8_BIT_RTC_REGS 0x4
@@ -461,6 +463,14 @@
}
}
+ /* Enable abort enable feature */
+ ctrl_reg |= PM8xxx_RTC_ABORT_ENABLE;
+ rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "PM8xxx write failed!\n");
+ goto fail_rtc_enable;
+ }
+
rtc_dd->ctrl_reg = ctrl_reg;
if (rtc_write_enable == true)
pm8xxx_rtc_ops.set_time = pm8xxx_rtc_set_time;
@@ -539,9 +549,48 @@
return 0;
}
+static void pm8xxx_rtc_shutdown(struct platform_device *pdev)
+{
+ u8 value[4] = {0, 0, 0, 0};
+ u8 reg;
+ int rc;
+ unsigned long irq_flags;
+ bool rtc_alarm_powerup = false;
+ struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
+ struct pm8xxx_rtc_platform_data *pdata = pdev->dev.platform_data;
+
+ if (pdata != NULL)
+ rtc_alarm_powerup = pdata->rtc_alarm_powerup;
+
+ if (!rtc_alarm_powerup) {
+
+ spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
+ dev_dbg(&pdev->dev, "Disabling alarm interrupts\n");
+
+ /* Disable RTC alarms */
+ reg = rtc_dd->ctrl_reg;
+ reg &= ~PM8xxx_RTC_ALARM_ENABLE;
+ rc = pm8xxx_write_wrapper(rtc_dd, ®, rtc_dd->rtc_base, 1);
+ if (rc < 0) {
+ dev_err(rtc_dd->rtc_dev, "PM8xxx write failed\n");
+ goto fail_alarm_disable;
+ }
+
+ /* Clear Alarm register */
+ rc = pm8xxx_write_wrapper(rtc_dd, value,
+ rtc_dd->alarm_rw_base, NUM_8_BIT_RTC_REGS);
+ if (rc < 0)
+ dev_err(rtc_dd->rtc_dev, "PM8xxx write failed\n");
+
+fail_alarm_disable:
+ spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
+ }
+}
+
static struct platform_driver pm8xxx_rtc_driver = {
.probe = pm8xxx_rtc_probe,
.remove = __devexit_p(pm8xxx_rtc_remove),
+ .shutdown = pm8xxx_rtc_shutdown,
.driver = {
.name = PM8XXX_RTC_DEV_NAME,
.owner = THIS_MODULE,
diff --git a/drivers/thermal/msm8960_tsens.c b/drivers/thermal/msm8960_tsens.c
index be434f6..12b3a42e 100644
--- a/drivers/thermal/msm8960_tsens.c
+++ b/drivers/thermal/msm8960_tsens.c
@@ -41,13 +41,7 @@
#define TSENS_MAIN_SENSOR 0
#define TSENS_8960_QFPROM_ADDR0 (MSM_QFPROM_BASE + 0x00000404)
-#define TSENS_8960_QFPROM_RED_TEMP_SENSOR0_SHIFT 8
-#define TSENS_8960_QFPROM_TEMP_SENSOR0_SHIFT 0
-#define TSENS_8960_QFPROM_TEMP_SENSOR0_MASK \
- (255 << TSENS_QFPROM_TEMP_SENSOR0_SHIFT)
-#define TSENS_8960_QFPROM_RED_TEMP_SENSOR0_MASK \
- (255 << TSENS_8960_QFPROM_RED_TEMP_SENSOR0_SHIFT)
-
+#define TSENS_8960_QFPROM_SPARE_ADDR0 (MSM_QFPROM_BASE + 0x00000414)
#define TSENS_8960_CONFIG 0x9b
#define TSENS_8960_CONFIG_SHIFT 0
#define TSENS_8960_CONFIG_MASK (0xf << TSENS_8960_CONFIG_SHIFT)
@@ -679,30 +673,27 @@
static int tsens_calib_sensors8960(void)
{
- uint32_t *main_sensor_addr, sensor_shift, red_sensor_shift;
- uint32_t sensor_mask, red_sensor_mask, i;
+ uint32_t *main_sensor_addr, sensor_shift, *backup_sensor_addr;
+ uint32_t sensor_mask, i;
for (i = 0; i < tmdev->tsens_num_sensor; i++) {
main_sensor_addr = TSENS_8960_QFPROM_ADDR0 +
- (TSENS_8960_QFPROM_SHIFT * (i >> TSENS_MASK1));
- sensor_shift = (i & TSENS_MASK1) * TSENS_SENSOR_SHIFT;
- red_sensor_shift = sensor_shift + TSENS_RED_SHIFT;
+ (TSENS_8960_QFPROM_SHIFT *
+ (i & TSENS_8960_QFPROM_SHIFT >> TSENS_SENSOR0_SHIFT));
+ sensor_shift = (i % TSENS_8960_QFPROM_SHIFT) * TSENS_RED_SHIFT;
sensor_mask = TSENS_THRESHOLD_MAX_CODE << sensor_shift;
- red_sensor_mask = TSENS_THRESHOLD_MAX_CODE <<
- red_sensor_shift;
+ backup_sensor_addr = TSENS_8960_QFPROM_SPARE_ADDR0 +
+ (TSENS_8960_QFPROM_SHIFT *
+ (i & TSENS_8960_QFPROM_SHIFT >> TSENS_SENSOR0_SHIFT));
tmdev->sensor[i].calib_data = (readl_relaxed(main_sensor_addr)
& sensor_mask) >> sensor_shift;
tmdev->sensor[i].calib_data_backup =
- (readl_relaxed(main_sensor_addr) &
- red_sensor_mask) >> red_sensor_shift;
+ (readl_relaxed(backup_sensor_addr) &
+ sensor_mask) >> sensor_shift;
if (tmdev->sensor[i].calib_data_backup)
tmdev->sensor[i].calib_data =
tmdev->sensor[i].calib_data_backup;
- /* Hardcoded calibration data based on pervious
- * chip. Remove once we obtain the data. */
- tmdev->sensor[i].calib_data = 91;
-
if (!tmdev->sensor[i].calib_data) {
pr_err("%s: No temperature sensor:%d data for"
" calibration in QFPROM!\n", __func__, i);
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index 20b73a1..a86e049 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -346,7 +346,7 @@
char *name;
char buf[32], *b;
int once = 0, err = -1;
- int (*notify)(uint32_t, const char *);
+ int (*notify)(uint32_t, const char *) = NULL;
strncpy(buf, diag_clients, sizeof(buf));
b = strim(buf);
@@ -354,10 +354,8 @@
while (b) {
name = strsep(&b, ",");
/* Allow only first diag channel to update pid and serial no */
- if (!once++)
+ if (_android_dev->pdata && !once++)
notify = _android_dev->pdata->update_pid_and_serial_num;
- else
- notify = NULL;
if (name) {
err = diag_function_add(c, name, notify);
@@ -1105,8 +1103,10 @@
cdev->desc.bDeviceClass = device_desc.bDeviceClass;
cdev->desc.bDeviceSubClass = device_desc.bDeviceSubClass;
cdev->desc.bDeviceProtocol = device_desc.bDeviceProtocol;
- usb_add_config(cdev, &android_config_driver,
- android_bind_config);
+ if (usb_add_config(cdev, &android_config_driver,
+ android_bind_config))
+ return size;
+
usb_gadget_connect(cdev->gadget);
dev->enabled = true;
} else if (!enabled && dev->enabled) {
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 9017706..9d268d1 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1699,6 +1699,9 @@
if (mReq->req.status != -EALREADY)
return -EINVAL;
+ /* clean speculative fetches on req->ptr->token */
+ mb();
+
if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
return -EBUSY;
@@ -2074,7 +2077,6 @@
continue; /* not configured */
if (hw_test_and_clear_complete(i)) {
- udelay(200);
err = isr_tr_complete_low(mEp);
if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
if (err > 0) /* needs status phase */
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 4447b0f..ece6785 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -178,6 +178,17 @@
This driver is not supported on boards like trout which
has an external PHY.
+config USB_EHCI_MSM_HSIC
+ bool "Support for HSIC based MSM on-chip EHCI USB controller"
+ depends on USB_EHCI_HCD && ARCH_MSM
+ ---help---
+ Enables support for the HSIC (High Speed Inter-Chip) based
+ USB Host controller present on the Qualcomm chipsets.
+
+ HSIC is a supplement to USB 2.0 specification and is preferred
+ for chip-to-chip interconnect (having maximum circuit length of
+ 10cm) as it removes the analog transceivers.
+
config USB_EHCI_TEGRA
boolean "NVIDIA Tegra HCD support"
depends on USB_EHCI_HCD && ARCH_TEGRA
@@ -258,7 +269,6 @@
Enables support for the full speed USB controller core present
on the Qualcomm chipsets
-
config USB_ISP116X_HCD
tristate "ISP116X HCD support"
depends on USB
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 0744395..dc11eaf 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1187,31 +1187,6 @@
#define PCI_DRIVER ehci_pci_driver
#endif
-#ifdef CONFIG_USB_EHCI_FSL
-#include "ehci-fsl.c"
-#define PLATFORM_DRIVER ehci_fsl_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_MXC
-#include "ehci-mxc.c"
-#define PLATFORM_DRIVER ehci_mxc_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_SH
-#include "ehci-sh.c"
-#define PLATFORM_DRIVER ehci_hcd_sh_driver
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#include "ehci-au1xxx.c"
-#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
-#endif
-
-#ifdef CONFIG_USB_EHCI_HCD_OMAP
-#include "ehci-omap.c"
-#define PLATFORM_DRIVER ehci_hcd_omap_driver
-#endif
-
#ifdef CONFIG_PPC_PS3
#include "ehci-ps3.c"
#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
@@ -1227,90 +1202,204 @@
#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
#endif
+#ifdef CONFIG_USB_EHCI_FSL
+#include "ehci-fsl.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_MXC
+#include "ehci-mxc.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_SH
+#include "ehci-sh.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#include "ehci-au1xxx.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_OMAP
+#include "ehci-omap.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
#ifdef CONFIG_PLAT_ORION
#include "ehci-orion.c"
-#define PLATFORM_DRIVER ehci_orion_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_IXP4XX
#include "ehci-ixp4xx.c"
-#define PLATFORM_DRIVER ixp4xx_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_W90X900_EHCI
#include "ehci-w90x900.c"
-#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_AT91
#include "ehci-atmel.c"
-#define PLATFORM_DRIVER ehci_atmel_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_OCTEON_EHCI
#include "ehci-octeon.c"
-#define PLATFORM_DRIVER ehci_octeon_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_CNS3XXX_EHCI
#include "ehci-cns3xxx.c"
-#define PLATFORM_DRIVER cns3xxx_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_ARCH_VT8500
#include "ehci-vt8500.c"
-#define PLATFORM_DRIVER vt8500_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_PLAT_SPEAR
#include "ehci-spear.c"
-#define PLATFORM_DRIVER spear_ehci_hcd_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_MSM_72K
#include "ehci-msm72k.c"
-#define PLATFORM_DRIVER ehci_msm_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_MSM
#include "ehci-msm.c"
-#define PLATFORM_DRIVER ehci_msm_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
#include "ehci-pmcmsp.c"
-#define PLATFORM_DRIVER ehci_hcd_msp_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_TEGRA
#include "ehci-tegra.c"
-#define PLATFORM_DRIVER tegra_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_S5P
#include "ehci-s5p.c"
-#define PLATFORM_DRIVER s5p_ehci_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_USB_EHCI_ATH79
#include "ehci-ath79.c"
-#define PLATFORM_DRIVER ehci_ath79_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
#ifdef CONFIG_SPARC_LEON
#include "ehci-grlib.c"
-#define PLATFORM_DRIVER ehci_grlib_driver
+#define PLATFORM_DRIVER_PRESENT
#endif
-#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+#include "ehci-msm-hsic.c"
+#define PLATFORM_DRIVER_PRESENT
+#endif
+
+#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER_PRESENT) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
!defined(XILINX_OF_PLATFORM_DRIVER)
#error "missing bus glue for ehci-hcd"
#endif
+static struct platform_driver *plat_drivers[] = {
+#ifdef CONFIG_USB_EHCI_FSL
+ &ehci_fsl_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_MXC
+ &ehci_mxc_driver,
+#endif
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7786
+ &ehci_hcd_sh_driver,
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+ &ehci_hcd_au1xxx_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_OMAP
+ &ehci_hcd_omap_driver,
+#endif
+
+#ifdef CONFIG_PLAT_ORION
+ &ehci_orion_driver,
+#endif
+
+#ifdef CONFIG_ARCH_IXP4XX
+ &ixp4xx_ehci_driver,
+#endif
+
+#ifdef CONFIG_USB_W90X900_EHCI
+ &ehci_hcd_w90x900_driver,
+#endif
+
+#ifdef CONFIG_ARCH_AT91
+ &ehci_atmel_driver,
+#endif
+
+#ifdef CONFIG_USB_OCTEON_EHCI
+ &ehci_octeon_driver,
+#endif
+
+#ifdef CONFIG_USB_CNS3XXX_EHCI
+ &cns3xxx_ehci_driver,
+#endif
+
+#ifdef CONFIG_ARCH_VT8500
+ &vt8500_ehci_driver,
+#endif
+
+#ifdef CONFIG_PLAT_SPEAR
+ &spear_ehci_hcd_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
+ &ehci_hcd_msp_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+ &tegra_ehci_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_S5P
+ &s5p_ehci_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_ATH79
+ &ehci_ath79_driver
+#endif
+
+#ifdef CONFIG_SPARC_LEON
+ &ehci_grlib_driver
+#endif
+
+#if defined(CONFIG_USB_EHCI_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
+ &ehci_msm_driver,
+#endif
+
+#ifdef CONFIG_USB_EHCI_MSM_HSIC
+ &ehci_msm_hsic_driver
+#endif
+
+};
+
+
static int __init ehci_hcd_init(void)
{
- int retval = 0;
+ int i, retval = 0;
if (usb_disabled())
return -ENODEV;
@@ -1335,11 +1424,14 @@
}
#endif
-#ifdef PLATFORM_DRIVER
- retval = platform_driver_register(&PLATFORM_DRIVER);
- if (retval < 0)
- goto clean0;
-#endif
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++) {
+ retval = platform_driver_register(plat_drivers[i]);
+ if (retval) {
+ while (--i >= 0)
+ platform_driver_unregister(plat_drivers[i]);
+ goto clean0;
+ }
+ }
#ifdef PCI_DRIVER
retval = pci_register_driver(&PCI_DRIVER);
@@ -1382,10 +1474,9 @@
pci_unregister_driver(&PCI_DRIVER);
clean1:
#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++)
+ platform_driver_unregister(plat_drivers[i]);
clean0:
-#endif
#ifdef DEBUG
debugfs_remove(ehci_debug_root);
ehci_debug_root = NULL;
@@ -1398,15 +1489,17 @@
static void __exit ehci_hcd_cleanup(void)
{
+ int i;
#ifdef XILINX_OF_PLATFORM_DRIVER
platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
#endif
#ifdef OF_PLATFORM_DRIVER
platform_driver_unregister(&OF_PLATFORM_DRIVER);
#endif
-#ifdef PLATFORM_DRIVER
- platform_driver_unregister(&PLATFORM_DRIVER);
-#endif
+
+ for (i = 0; i < ARRAY_SIZE(plat_drivers); i++)
+ platform_driver_unregister(plat_drivers[i]);
+
#ifdef PCI_DRIVER
pci_unregister_driver(&PCI_DRIVER);
#endif
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
new file mode 100644
index 0000000..1b8b5d6
--- /dev/null
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -0,0 +1,795 @@
+/* ehci-msm-hsic.c - HSUSB Host Controller Driver Implementation
+ *
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * Partly derived from ehci-fsl.c and ehci-hcd.c
+ * Copyright (c) 2000-2004 by David Brownell
+ * Copyright (c) 2005 MontaVista Software
+ *
+ * All source code in this file is licensed under the following license except
+ * where indicated.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can find it at http://www.fsf.org
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/wakelock.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/usb/msm_hsusb_hw.h>
+#include <linux/usb/msm_hsusb.h>
+#include <linux/gpio.h>
+#include <mach/clk.h>
+#include <mach/msm_iomap.h>
+
+#define MSM_USB_BASE (hcd->regs)
+
+struct msm_hsic_hcd {
+ struct ehci_hcd ehci;
+ struct device *dev;
+ struct clk *ahb_clk;
+ struct clk *sys_clk;
+ struct clk *fs_xcvr_clk;
+ struct clk *hsic_clk;
+ struct clk *cal_clk;
+ struct regulator *hsic_vddcx;
+ bool async_int;
+ atomic_t in_lpm;
+ struct wake_lock wlock;
+};
+
+static inline struct msm_hsic_hcd *hcd_to_hsic(struct usb_hcd *hcd)
+{
+ return (struct msm_hsic_hcd *) (hcd->hcd_priv);
+}
+
+static inline struct usb_hcd *hsic_to_hcd(struct msm_hsic_hcd *mehci)
+{
+ return container_of((void *) mehci, struct usb_hcd, hcd_priv);
+}
+
+#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
+
+#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
+#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
+#define USB_PHY_VDD_DIG_LOAD 49360 /* uA */
+
+static int msm_hsic_init_vddcx(struct msm_hsic_hcd *mehci, int init)
+{
+ int ret = 0;
+
+ if (!init)
+ goto disable_reg;
+
+ mehci->hsic_vddcx = regulator_get(mehci->dev, "HSIC_VDDCX");
+ if (IS_ERR(mehci->hsic_vddcx)) {
+ dev_err(mehci->dev, "unable to get hsic vddcx\n");
+ return PTR_ERR(mehci->hsic_vddcx);
+ }
+
+ ret = regulator_set_voltage(mehci->hsic_vddcx,
+ USB_PHY_VDD_DIG_VOL_MIN,
+ USB_PHY_VDD_DIG_VOL_MAX);
+ if (ret) {
+ dev_err(mehci->dev, "unable to set the voltage"
+ "for hsic vddcx\n");
+ goto reg_set_voltage_err;
+ }
+
+ ret = regulator_set_optimum_mode(mehci->hsic_vddcx,
+ USB_PHY_VDD_DIG_LOAD);
+ if (ret < 0) {
+ pr_err("%s: Unable to set optimum mode of the regulator:"
+ "VDDCX\n", __func__);
+ goto reg_optimum_mode_err;
+ }
+
+ ret = regulator_enable(mehci->hsic_vddcx);
+ if (ret) {
+ dev_err(mehci->dev, "unable to enable hsic vddcx\n");
+ goto reg_enable_err;
+ }
+
+ return 0;
+
+disable_reg:
+ regulator_disable(mehci->hsic_vddcx);
+reg_enable_err:
+ regulator_set_optimum_mode(mehci->hsic_vddcx, 0);
+reg_optimum_mode_err:
+ regulator_set_voltage(mehci->hsic_vddcx, 0,
+ USB_PHY_VDD_DIG_VOL_MIN);
+reg_set_voltage_err:
+ regulator_put(mehci->hsic_vddcx);
+
+ return ret;
+
+}
+
+static int ulpi_write(struct msm_hsic_hcd *mehci, u32 val, u32 reg)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+
+ /* initiate write operation */
+ writel_relaxed(ULPI_RUN | ULPI_WRITE |
+ ULPI_ADDR(reg) | ULPI_DATA(val),
+ USB_ULPI_VIEWPORT);
+
+ /* wait for completion */
+ while (cnt < ULPI_IO_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_RUN))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= ULPI_IO_TIMEOUT_USEC) {
+ dev_err(mehci->dev, "ulpi_write: timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int msm_hsic_config_gpios(struct msm_hsic_hcd *mehci, int gpio_en)
+{
+ int rc = 0;
+ struct msm_hsic_host_platform_data *pdata;
+
+ pdata = mehci->dev->platform_data;
+ /*
+ * In future versions, dedicated lines might be used for HSIC
+ * strobe and data instead of gpios. Hence returning zero value.
+ */
+ if (!pdata->strobe || !pdata->data)
+ return rc;
+
+ if (!gpio_en)
+ goto free_gpio;
+
+ rc = gpio_request(pdata->strobe, "HSIC_STROBE_GPIO");
+ if (rc < 0) {
+ dev_err(mehci->dev, "gpio request failed for HSIC STROBE\n");
+ return rc;
+ }
+
+ rc = gpio_request(pdata->data, "HSIC_DATA_GPIO");
+ if (rc < 0) {
+ dev_err(mehci->dev, "gpio request failed for HSIC DATA\n");
+ goto free_strobe;
+ }
+
+ return 0;
+
+free_gpio:
+ gpio_free(pdata->data);
+free_strobe:
+ gpio_free(pdata->strobe);
+
+ return rc;
+}
+
+static int msm_hsic_phy_clk_reset(struct msm_hsic_hcd *mehci)
+{
+ int ret;
+
+ clk_enable(mehci->fs_xcvr_clk);
+
+ ret = clk_reset(mehci->sys_clk, CLK_RESET_ASSERT);
+ if (ret) {
+ clk_disable(mehci->fs_xcvr_clk);
+ dev_err(mehci->dev, "usb phy clk assert failed\n");
+ return ret;
+ }
+ usleep_range(10000, 12000);
+ clk_disable(mehci->fs_xcvr_clk);
+
+ ret = clk_reset(mehci->sys_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ dev_err(mehci->dev, "usb phy clk deassert failed\n");
+
+ return ret;
+}
+
+static int msm_hsic_phy_reset(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ u32 val;
+ int ret;
+
+ ret = msm_hsic_phy_clk_reset(mehci);
+ if (ret)
+ return ret;
+
+ val = readl_relaxed(USB_PORTSC) & ~PORTSC_PTS_MASK;
+ writel_relaxed(val | PORTSC_PTS_ULPI, USB_PORTSC);
+
+ /* Ensure that RESET operation is completed before turning off clock */
+ mb();
+ dev_dbg(mehci->dev, "phy_reset: success\n");
+
+ return 0;
+}
+
+#define HSIC_GPIO150_PAD_CTL (MSM_TLMM_BASE+0x20C0)
+#define HSIC_GPIO151_PAD_CTL (MSM_TLMM_BASE+0x20C4)
+#define HSIC_CAL_PAD_CTL (MSM_TLMM_BASE+0x20C8)
+#define HSIC_LV_MODE 0x04
+#define HSIC_PAD_CALIBRATION 0xA8
+#define HSIC_GPIO_PAD_VAL 0x0A0AAA10
+#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
+static int msm_hsic_reset(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ int ret;
+
+ ret = msm_hsic_phy_reset(mehci);
+ if (ret) {
+ dev_err(mehci->dev, "phy_reset failed\n");
+ return ret;
+ }
+
+ writel_relaxed(USBCMD_RESET, USB_USBCMD);
+ while (cnt < LINK_RESET_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_USBCMD) & USBCMD_RESET))
+ break;
+ udelay(1);
+ cnt++;
+ }
+ if (cnt >= LINK_RESET_TIMEOUT_USEC)
+ return -ETIMEDOUT;
+
+ /* select ULPI phy */
+ writel_relaxed(0x80000000, USB_PORTSC);
+
+ /* TODO: Need to confirm if HSIC PHY also requires delay after RESET */
+ msleep(100);
+
+ /* HSIC PHY Initialization */
+ /* Enable LV_MODE in HSIC_CAL_PAD_CTL register */
+ writel_relaxed(HSIC_LV_MODE, HSIC_CAL_PAD_CTL);
+
+ /*set periodic calibration interval to ~2.048sec in HSIC_IO_CAL_REG */
+ ulpi_write(mehci, 0xFF, 0x33);
+
+ /* Enable periodic IO calibration in HSIC_CFG register */
+ ulpi_write(mehci, HSIC_PAD_CALIBRATION, 0x30);
+
+ /* Configure GPIO 150/151 pins for HSIC functionality mode */
+ ret = msm_hsic_config_gpios(mehci, 1);
+ if (ret) {
+ dev_err(mehci->dev, " gpio configuarion failed\n");
+ return ret;
+ }
+
+ /* Set LV_MODE=0x1 and DCC=0x2 in HSIC_GPIO150/151_PAD_CTL register */
+ writel_relaxed(HSIC_GPIO_PAD_VAL, HSIC_GPIO150_PAD_CTL);
+ writel_relaxed(HSIC_GPIO_PAD_VAL, HSIC_GPIO151_PAD_CTL);
+
+ /* Enable HSIC mode in HSIC_CFG register */
+ ulpi_write(mehci, 0x01, 0x31);
+
+ return 0;
+}
+
+#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
+#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
+
+#ifdef CONFIG_PM_SLEEP
+static int msm_hsic_suspend(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ u32 val;
+
+ if (atomic_read(&mehci->in_lpm)) {
+ dev_dbg(mehci->dev, "%s called in lpm\n", __func__);
+ return 0;
+ }
+
+ disable_irq(hcd->irq);
+ /*
+ * PHY may take some time or even fail to enter into low power
+ * mode (LPM). Hence poll for 500 msec and reset the PHY and link
+ * in failure case.
+ */
+ val = readl_relaxed(USB_PORTSC) | PORTSC_PHCD;
+ writel_relaxed(val, USB_PORTSC);
+ while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
+ if (readl_relaxed(USB_PORTSC) & PORTSC_PHCD)
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
+ dev_err(mehci->dev, "Unable to suspend PHY\n");
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_reset(mehci);
+ enable_irq(hcd->irq);
+ return -ETIMEDOUT;
+ }
+
+ /*
+ * PHY has capability to generate interrupt asynchronously in low
+ * power mode (LPM). This interrupt is level triggered. So USB IRQ
+ * line must be disabled till async interrupt enable bit is cleared
+ * in USBCMD register. Assert STP (ULPI interface STOP signal) to
+ * block data communication from PHY.
+ */
+ writel_relaxed(readl_relaxed(USB_USBCMD) | ASYNC_INTR_CTRL |
+ ULPI_STP_CTRL, USB_USBCMD);
+
+ /*
+ * Ensure that hardware is put in low power mode before
+ * clocks are turned OFF and VDD is allowed to minimize.
+ */
+ mb();
+
+ clk_disable(mehci->sys_clk);
+ clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->cal_clk);
+ clk_disable(mehci->ahb_clk);
+
+ atomic_set(&mehci->in_lpm, 1);
+ enable_irq(hcd->irq);
+ wake_unlock(&mehci->wlock);
+
+ dev_info(mehci->dev, "HSIC-USB in low power mode\n");
+
+ return 0;
+}
+
+static int msm_hsic_resume(struct msm_hsic_hcd *mehci)
+{
+ struct usb_hcd *hcd = hsic_to_hcd(mehci);
+ int cnt = 0;
+ unsigned temp;
+
+ if (!atomic_read(&mehci->in_lpm)) {
+ dev_dbg(mehci->dev, "%s called in !in_lpm\n", __func__);
+ return 0;
+ }
+
+ wake_lock(&mehci->wlock);
+
+ clk_enable(mehci->sys_clk);
+ clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->cal_clk);
+ clk_enable(mehci->ahb_clk);
+
+ temp = readl_relaxed(USB_USBCMD);
+ temp &= ~ASYNC_INTR_CTRL;
+ temp &= ~ULPI_STP_CTRL;
+ writel_relaxed(temp, USB_USBCMD);
+
+ if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD))
+ goto skip_phy_resume;
+
+ temp = readl_relaxed(USB_PORTSC) & ~PORTSC_PHCD;
+ writel_relaxed(temp, USB_PORTSC);
+ while (cnt < PHY_RESUME_TIMEOUT_USEC) {
+ if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD) &&
+ (readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_SYNC_STATE))
+ break;
+ udelay(1);
+ cnt++;
+ }
+
+ if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
+ /*
+ * This is a fatal error. Reset the link and
+ * PHY to make hsic working.
+ */
+ dev_err(mehci->dev, "Unable to resume USB. Reset the hsic\n");
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_reset(mehci);
+ }
+
+skip_phy_resume:
+
+ atomic_set(&mehci->in_lpm, 0);
+
+ if (mehci->async_int) {
+ mehci->async_int = false;
+ pm_runtime_put_noidle(mehci->dev);
+ enable_irq(hcd->irq);
+ }
+
+ dev_info(mehci->dev, "HSIC-USB exited from low power mode\n");
+
+ return 0;
+}
+#endif
+
+static irqreturn_t msm_hsic_irq(struct usb_hcd *hcd)
+{
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ if (atomic_read(&mehci->in_lpm)) {
+ disable_irq_nosync(hcd->irq);
+ mehci->async_int = true;
+ pm_runtime_get(mehci->dev);
+ return IRQ_HANDLED;
+ }
+
+ return ehci_irq(hcd);
+}
+
+static int ehci_hsic_reset(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int retval;
+
+ ehci->caps = USB_CAPLENGTH;
+ ehci->regs = USB_CAPLENGTH +
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+
+ /* cache the data to minimize the chip reads*/
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+ hcd->has_tt = 1;
+ ehci->sbrn = HCD_USB2;
+
+ retval = ehci_halt(ehci);
+ if (retval)
+ return retval;
+
+ /* data structure init */
+ retval = ehci_init(hcd);
+ if (retval)
+ return retval;
+
+ retval = ehci_reset(ehci);
+ if (retval)
+ return retval;
+
+ /* bursts of unspecified length. */
+ writel_relaxed(0, USB_AHBBURST);
+ /* Use the AHB transactor */
+ writel_relaxed(0, USB_AHBMODE);
+ /* Disable streaming mode and select host mode */
+ writel_relaxed(0x13, USB_USBMODE);
+
+ ehci_port_power(ehci, 1);
+ return 0;
+}
+
+static struct hc_driver msm_hsic_driver = {
+ .description = hcd_name,
+ .product_desc = "Qualcomm EHCI Host Controller using HSIC",
+ .hcd_priv_size = sizeof(struct msm_hsic_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = msm_hsic_irq,
+ .flags = HCD_USB2 | HCD_MEMORY,
+
+ .reset = ehci_hsic_reset,
+ .start = ehci_run,
+
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ehci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ /*
+ * PM support
+ */
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+};
+
+static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)
+{
+ int ret = 0;
+
+ if (!init)
+ goto put_clocks;
+
+ /*sys_clk is required for LINK protocol engine,it should be at 60MHz */
+ mehci->sys_clk = clk_get(mehci->dev, "usb_hsic_system_clk");
+ if (IS_ERR(mehci->sys_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_sys_clk\n");
+ ret = PTR_ERR(mehci->sys_clk);
+ return ret;
+ }
+ clk_set_rate(mehci->sys_clk, 60000000);
+
+ /* 60MHz fs_xcvr_clk is for LINK to be used during PHY RESET */
+ mehci->fs_xcvr_clk = clk_get(mehci->dev, "usb_hsic_xcvr_fs_clk");
+ if (IS_ERR(mehci->fs_xcvr_clk)) {
+ dev_err(mehci->dev, "failed to get fs_xcvr_clk\n");
+ ret = PTR_ERR(mehci->fs_xcvr_clk);
+ goto put_sys_clk;
+ }
+ clk_set_rate(mehci->fs_xcvr_clk, 60000000);
+
+ /* 480MHz hsic_clk is required for HSIC PHY operation */
+ mehci->hsic_clk = clk_get(mehci->dev, "usb_hsic_hsic_clk");
+ if (IS_ERR(mehci->hsic_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_clk\n");
+ ret = PTR_ERR(mehci->hsic_clk);
+ goto put_fs_xcvr_clk;
+ }
+ clk_set_rate(mehci->hsic_clk, 480000000);
+
+ /* 10MHz cal_clk is required for calibration of I/O pads */
+ mehci->cal_clk = clk_get(mehci->dev, "usb_hsic_hsio_cal_clk");
+ if (IS_ERR(mehci->cal_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_cal_clk\n");
+ ret = PTR_ERR(mehci->cal_clk);
+ goto put_hsic_clk;
+ }
+ clk_set_rate(mehci->cal_clk, 10000000);
+
+ /* ahb_clk is required for data transfers */
+ mehci->ahb_clk = clk_get(mehci->dev, "usb_hsic_p_clk");
+ if (IS_ERR(mehci->ahb_clk)) {
+ dev_err(mehci->dev, "failed to get hsic_ahb_clk\n");
+ ret = PTR_ERR(mehci->ahb_clk);
+ goto put_cal_clk;
+ }
+
+ clk_enable(mehci->sys_clk);
+ clk_enable(mehci->hsic_clk);
+ clk_enable(mehci->cal_clk);
+ clk_enable(mehci->ahb_clk);
+
+ return 0;
+
+put_clocks:
+ clk_disable(mehci->sys_clk);
+ clk_disable(mehci->hsic_clk);
+ clk_disable(mehci->cal_clk);
+ clk_disable(mehci->ahb_clk);
+ clk_put(mehci->ahb_clk);
+put_cal_clk:
+ clk_put(mehci->cal_clk);
+put_hsic_clk:
+ clk_put(mehci->hsic_clk);
+put_fs_xcvr_clk:
+ clk_put(mehci->fs_xcvr_clk);
+put_sys_clk:
+ clk_put(mehci->sys_clk);
+
+ return ret;
+}
+static int __devinit ehci_hsic_msm_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct resource *res;
+ struct msm_hsic_hcd *mehci;
+ int ret;
+
+ dev_dbg(&pdev->dev, "ehci_msm-hsic probe\n");
+
+ hcd = usb_create_hcd(&msm_hsic_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd) {
+ dev_err(&pdev->dev, "Unable to create HCD\n");
+ return -ENOMEM;
+ }
+
+ hcd->irq = platform_get_irq(pdev, 0);
+ if (hcd->irq < 0) {
+ dev_err(&pdev->dev, "Unable to get IRQ resource\n");
+ ret = hcd->irq;
+ goto put_hcd;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get memory resource\n");
+ ret = -ENODEV;
+ goto put_hcd;
+ }
+
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto put_hcd;
+ }
+
+ mehci = hcd_to_hsic(hcd);
+ mehci->dev = &pdev->dev;
+
+ ret = msm_hsic_init_clocks(mehci, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize clocks\n");
+ ret = -ENODEV;
+ goto unmap;
+ }
+
+ ret = msm_hsic_init_vddcx(mehci, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize VDDCX\n");
+ ret = -ENODEV;
+ goto deinit_clocks;
+ }
+
+ ret = msm_hsic_reset(mehci);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize PHY\n");
+ goto deinit_vddcx;
+ }
+
+ ret = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to register HCD\n");
+ goto unconfig_gpio;
+ }
+
+ device_init_wakeup(&pdev->dev, 1);
+ wake_lock_init(&mehci->wlock, WAKE_LOCK_SUSPEND, dev_name(&pdev->dev));
+ wake_lock(&mehci->wlock);
+ /*
+ * This pdev->dev is assigned parent of root-hub by USB core,
+ * hence, runtime framework automatically calls this driver's
+ * runtime APIs based on root-hub's state.
+ */
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+unconfig_gpio:
+ msm_hsic_config_gpios(mehci, 0);
+deinit_vddcx:
+ msm_hsic_init_vddcx(mehci, 0);
+deinit_clocks:
+ msm_hsic_init_clocks(mehci, 0);
+unmap:
+ iounmap(hcd->regs);
+put_hcd:
+ usb_put_hcd(hcd);
+
+ return ret;
+}
+
+static int __devexit ehci_hsic_msm_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ device_init_wakeup(&pdev->dev, 0);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+
+ usb_remove_hcd(hcd);
+ msm_hsic_config_gpios(mehci, 0);
+ msm_hsic_init_vddcx(mehci, 0);
+
+ msm_hsic_init_clocks(mehci, 0);
+ wake_lock_destroy(&mehci->wlock);
+ iounmap(hcd->regs);
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int msm_hsic_pm_suspend(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "ehci-msm-hsic PM suspend\n");
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(hcd->irq);
+
+ return msm_hsic_suspend(mehci);
+
+}
+
+static int msm_hsic_pm_resume(struct device *dev)
+{
+ int ret;
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "ehci-msm-hsic PM resume\n");
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(hcd->irq);
+
+ ret = msm_hsic_resume(mehci);
+ if (ret)
+ return ret;
+
+ /* Bring the device to full powered state upon system resume */
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PM_RUNTIME
+static int msm_hsic_runtime_idle(struct device *dev)
+{
+ dev_dbg(dev, "EHCI runtime idle\n");
+
+ return 0;
+}
+
+static int msm_hsic_runtime_suspend(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "EHCI runtime suspend\n");
+ return msm_hsic_suspend(mehci);
+}
+
+static int msm_hsic_runtime_resume(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+
+ dev_dbg(dev, "EHCI runtime resume\n");
+ return msm_hsic_resume(mehci);
+}
+#endif
+
+#ifdef CONFIG_PM
+static const struct dev_pm_ops msm_hsic_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(msm_hsic_pm_suspend, msm_hsic_pm_resume)
+ SET_RUNTIME_PM_OPS(msm_hsic_runtime_suspend, msm_hsic_runtime_resume,
+ msm_hsic_runtime_idle)
+};
+#endif
+
+static struct platform_driver ehci_msm_hsic_driver = {
+ .probe = ehci_hsic_msm_probe,
+ .remove = __devexit_p(ehci_hsic_msm_remove),
+ .driver = {
+ .name = "msm_hsic_host",
+#ifdef CONFIG_PM
+ .pm = &msm_hsic_dev_pm_ops,
+#endif
+ },
+};
diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
index 527dc85..1135806 100644
--- a/drivers/usb/misc/Kconfig
+++ b/drivers/usb/misc/Kconfig
@@ -280,3 +280,28 @@
To compile this driver as a module, choose M here: the
module will be called qcaux. If unsure, choose N.
+
+config USB_QCOM_DUN_BRIDGE
+ tristate "USB Qualcomm modem DUN bridge driver"
+ depends on USB && !USB_SERIAL_QUALCOMM
+ help
+ Say Y here if you have a Qualcomm modem device connected via USB that
+ will be bridged in kernel space. This driver will enable bridging
+ with the gadget serial driver for use in dial-up networking. This is
+ not the same as the qcserial driver that exposes a TTY interface to
+ userspace.
+
+ To compile this driver as a module, choose M here: the module
+ will be called dun_bridge.
+
+config USB_QCOM_DUN_BRIDGE_TEST
+ tristate "USB Qualcomm modem DUN bridge driver test"
+ depends on USB && USB_QCOM_DUN_BRIDGE && !USB_SERIAL_QUALCOMM
+ help
+ Say Y here if you want to enable the test hook for the
+ Qualcomm modem bridge driver. When enabled, this will create
+ a debugfs file entry named "dun_bridge_test" which can be used
+ to read and write directly to the modem.
+
+ To compile this driver as a module, choose M here: the module
+ will be called dun_bridge_test.
diff --git a/drivers/usb/misc/Makefile b/drivers/usb/misc/Makefile
index 20ee62a..03568bc 100644
--- a/drivers/usb/misc/Makefile
+++ b/drivers/usb/misc/Makefile
@@ -31,3 +31,5 @@
obj-$(CONFIG_USB_QCOM_DIAG) += diag_usb.o
obj-$(CONFIG_USB_QCOM_DIAG_TEST) += diag_bridge_test.o
+obj-$(CONFIG_USB_QCOM_DUN_BRIDGE) += dun_bridge.o
+obj-$(CONFIG_USB_QCOM_DUN_BRIDGE_TEST) += dun_bridge_test.o
diff --git a/drivers/usb/misc/dun_bridge.c b/drivers/usb/misc/dun_bridge.c
new file mode 100644
index 0000000..aca7714
--- /dev/null
+++ b/drivers/usb/misc/dun_bridge.c
@@ -0,0 +1,520 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/usb.h>
+#include <linux/usb/cdc.h>
+#include <linux/usb/ch9.h>
+#include <asm/unaligned.h>
+#include <mach/usb_dun_bridge.h>
+
+#define DRIVER_DESC "Qualcomm USB DUN bridge driver"
+#define DRIVER_VERSION "1.0"
+
+struct dun_bridge {
+ struct usb_device *udev;
+ struct usb_interface *intf;
+ struct usb_anchor submitted;
+ u8 int_in_epaddr;
+ unsigned in, out; /* bulk in/out pipes */
+
+ struct urb *inturb;
+ struct usb_ctrlrequest cmd;
+ u8 *ctrl_buf;
+
+ struct kref kref;
+ struct platform_device *pdev;
+
+ struct dun_bridge_ops *ops;
+};
+
+static struct dun_bridge *__dev;
+
+/* This assumes that __dev has already been initialized by probe(). */
+int dun_bridge_open(struct dun_bridge_ops *ops)
+{
+ struct dun_bridge *dev = __dev;
+ int ret = 0;
+
+ if (!dev) {
+ err("%s: dev is null", __func__);
+ return -ENODEV;
+ }
+
+ if (!ops || !ops->read_complete || !ops->write_complete)
+ return -EINVAL;
+
+ dev->ops = ops;
+ if (ops->ctrl_status) {
+ ret = usb_submit_urb(dev->inturb, GFP_KERNEL);
+ if (ret)
+ pr_err("%s: submitting int urb failed: %d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_open);
+
+int dun_bridge_close(void)
+{
+ struct dun_bridge *dev = __dev;
+ if (!dev)
+ return -ENODEV;
+
+ dev_dbg(&dev->udev->dev, "%s:", __func__);
+ usb_unlink_anchored_urbs(&dev->submitted);
+ usb_unlink_urb(dev->inturb);
+ dev->ops = NULL;
+
+ return 0;
+}
+EXPORT_SYMBOL(dun_bridge_close);
+
+static void read_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct dun_bridge_ops *ops;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ kfree(urb->transfer_buffer);
+ return;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: status:%d actual:%d\n", __func__,
+ urb->status, urb->actual_length);
+
+ usb_autopm_put_interface(dev->intf);
+ ops = dev->ops;
+ if (ops)
+ ops->read_complete(ops->ctxt,
+ urb->transfer_buffer,
+ urb->transfer_buffer_length,
+ /* callback must check this value for error */
+ urb->status < 0 ?
+ urb->status : urb->actual_length);
+ else {
+ /* can't call back, free buffer on caller's behalf */
+ dev_err(&dev->udev->dev, "cannot complete read callback\n");
+ kfree(urb->transfer_buffer);
+ }
+}
+
+int dun_bridge_read(void *data, int len)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb;
+ int ret;
+
+ if (!dev || !dev->ops)
+ return -ENODEV;
+
+ if (!dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ dev_err(&dev->udev->dev, "%s: invalid len:%d\n", __func__, len);
+ return -EINVAL;
+ }
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_bulk_urb(urb, dev->udev, dev->in,
+ data, len, read_cb, dev);
+ usb_anchor_urb(urb, &dev->submitted);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_KERNEL);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_unanchor_urb(urb);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_read);
+
+static void write_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct dun_bridge_ops *ops;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ kfree(urb->transfer_buffer);
+ return;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: status:%d actual:%d\n", __func__,
+ urb->status, urb->actual_length);
+
+ usb_autopm_put_interface(dev->intf);
+ ops = dev->ops;
+ if (ops)
+ ops->write_complete(ops->ctxt,
+ urb->transfer_buffer,
+ urb->transfer_buffer_length,
+ /* callback must check this value for error */
+ urb->status < 0 ?
+ urb->status : urb->actual_length);
+ else {
+ /* can't call back, free buffer on caller's behalf */
+ dev_err(&dev->udev->dev, "cannot complete write callback\n");
+ kfree(urb->transfer_buffer);
+ }
+}
+
+int dun_bridge_write(void *data, int len)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb;
+ int ret;
+
+ if (!dev || !dev->ops)
+ return -ENODEV;
+
+ if (!dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!len) {
+ dev_err(&dev->udev->dev, "%s: invalid len:%d\n", __func__, len);
+ return -EINVAL;
+ }
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_bulk_urb(urb, dev->udev, dev->out,
+ data, len, write_cb, dev);
+ usb_anchor_urb(urb, &dev->submitted);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_KERNEL);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_unanchor_urb(urb);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_write);
+
+static void ctrl_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ usb_autopm_put_interface(dev->intf);
+}
+
+int dun_bridge_send_ctrl_bits(unsigned ctrl_bits)
+{
+ struct dun_bridge *dev = __dev;
+ struct urb *urb = NULL;
+ int ret;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return -ENODEV;
+ }
+
+ dev_dbg(&dev->udev->dev, "%s: %#x", __func__, ctrl_bits);
+
+ dev->cmd.bRequestType = USB_TYPE_CLASS | USB_RECIP_INTERFACE;
+ dev->cmd.bRequest = USB_CDC_REQ_SET_CONTROL_LINE_STATE;
+ dev->cmd.wValue = cpu_to_le16(ctrl_bits);
+ dev->cmd.wIndex = cpu_to_le16(dev->int_in_epaddr);
+ dev->cmd.wLength = 0;
+
+ urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!urb) {
+ dev_err(&dev->udev->dev, "%s: Unable to alloc urb\n", __func__);
+ return -ENOMEM;
+ }
+
+ usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
+ (unsigned char *)&dev->cmd, NULL, 0,
+ ctrl_cb, dev);
+
+ usb_autopm_get_interface(dev->intf);
+ ret = usb_submit_urb(urb, GFP_ATOMIC);
+ if (ret) {
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, ret);
+ usb_autopm_put_interface(dev->intf);
+ }
+
+ usb_free_urb(urb);
+ return ret;
+}
+EXPORT_SYMBOL(dun_bridge_send_ctrl_bits);
+
+static void int_cb(struct urb *urb)
+{
+ struct dun_bridge *dev = urb->context;
+ struct usb_cdc_notification *dr = urb->transfer_buffer;
+ unsigned char *data;
+ unsigned int ctrl_bits;
+ int status = urb->status;
+
+ if (!dev || !dev->intf) {
+ pr_err("%s: device is disconnected\n", __func__);
+ return;
+ }
+
+ switch (status) {
+ case 0:
+ /* success */
+ break;
+ case -ECONNRESET:
+ case -ENOENT:
+ case -ESHUTDOWN:
+ /* this urb is terminated, clean up */
+ dev_err(&dev->udev->dev,
+ "%s - urb shutting down with status: %d\n",
+ __func__, status);
+ return;
+ default:
+ dev_err(&dev->udev->dev,
+ "%s - nonzero urb status received: %d\n",
+ __func__, status);
+ goto resubmit_urb;
+ }
+
+ data = (unsigned char *)(dr + 1);
+ switch (dr->bNotificationType) {
+ case USB_CDC_NOTIFY_NETWORK_CONNECTION:
+ dev_dbg(&dev->udev->dev, "%s network\n", dr->wValue ?
+ "connected to" : "disconnected from");
+ break;
+
+ case USB_CDC_NOTIFY_SERIAL_STATE:
+ ctrl_bits = get_unaligned_le16(data);
+ dev_dbg(&dev->udev->dev, "serial state: %d\n", ctrl_bits);
+ if (dev->ops && dev->ops->ctrl_status)
+ dev->ops->ctrl_status(dev->ops->ctxt, ctrl_bits);
+ break;
+
+ default:
+ dev_err(&dev->udev->dev, "unknown notification %d received: "
+ "index %d len %d data0 %d data1 %d\n",
+ dr->bNotificationType, dr->wIndex,
+ dr->wLength, data[0], data[1]);
+ break;
+ }
+resubmit_urb:
+ status = usb_submit_urb(dev->inturb, GFP_ATOMIC);
+ if (status)
+ dev_err(&dev->udev->dev, "%s: submit urb err:%d\n",
+ __func__, status);
+}
+
+static void dun_bridge_delete(struct kref *kref)
+{
+ struct dun_bridge *dev = container_of(kref, struct dun_bridge, kref);
+
+ __dev = NULL;
+ usb_put_dev(dev->udev);
+ usb_free_urb(dev->inturb);
+ kfree(dev->ctrl_buf);
+ kfree(dev);
+}
+
+static int
+dun_bridge_probe(struct usb_interface *intf, const struct usb_device_id *id)
+{
+ struct dun_bridge *dev;
+ struct usb_host_interface *iface_desc;
+ struct usb_endpoint_descriptor *epd;
+ __u8 iface_num;
+ int i;
+ int ctrlsize = 0;
+ int ret = -ENOMEM;
+
+ iface_desc = intf->cur_altsetting;
+ iface_num = iface_desc->desc.bInterfaceNumber;
+
+ /* is this interface supported? */
+ if (iface_num != id->driver_info)
+ return -ENODEV;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev) {
+ pr_err("%s: unable to allocate dev\n", __func__);
+ goto error;
+ }
+
+ dev->pdev = platform_device_alloc("dun_bridge", 0);
+ if (!dev->pdev) {
+ pr_err("%s: unable to allocate platform device\n", __func__);
+ kfree(dev);
+ return -ENOMEM;
+ }
+ __dev = dev;
+
+ kref_init(&dev->kref);
+ dev->udev = usb_get_dev(interface_to_usbdev(intf));
+ dev->intf = intf;
+
+ init_usb_anchor(&dev->submitted);
+ dev->inturb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!dev->inturb) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+ epd = &iface_desc->endpoint[i].desc;
+
+ if (usb_endpoint_is_int_in(epd)) {
+ dev->int_in_epaddr = epd->bEndpointAddress;
+ ctrlsize = le16_to_cpu(epd->wMaxPacketSize);
+
+ dev->ctrl_buf = kzalloc(ctrlsize, GFP_KERNEL);
+ if (!dev->ctrl_buf) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ usb_fill_int_urb(dev->inturb, dev->udev,
+ usb_rcvintpipe(dev->udev,
+ dev->int_in_epaddr),
+ dev->ctrl_buf, ctrlsize,
+ int_cb, dev, epd->bInterval);
+
+ } else if (usb_endpoint_is_bulk_in(epd))
+ dev->in = usb_rcvbulkpipe(dev->udev,
+ epd->bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK);
+
+ else if (usb_endpoint_is_bulk_out(epd))
+ dev->out = usb_sndbulkpipe(dev->udev,
+ epd->bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK);
+ }
+
+ if (!dev->int_in_epaddr && !dev->in && !dev->out) {
+ dev_err(&dev->udev->dev, "%s: could not find all endpoints\n",
+ __func__);
+ ret = -ENODEV;
+ goto error;
+ }
+
+ usb_set_intfdata(intf, dev);
+ platform_device_add(dev->pdev);
+ return 0;
+error:
+ if (dev)
+ kref_put(&dev->kref, dun_bridge_delete);
+ return ret;
+}
+
+static void dun_bridge_disconnect(struct usb_interface *intf)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+
+ platform_device_del(dev->pdev);
+ usb_set_intfdata(intf, NULL);
+ dev->intf = NULL;
+
+ kref_put(&dev->kref, dun_bridge_delete);
+
+ pr_debug("%s: DUN Bridge now disconnected\n", __func__);
+}
+
+static int dun_bridge_suspend(struct usb_interface *intf, pm_message_t message)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+
+ dev_dbg(&dev->udev->dev, "%s:", __func__);
+ usb_unlink_anchored_urbs(&dev->submitted);
+ usb_unlink_urb(dev->inturb);
+
+ return 0;
+}
+
+static int dun_bridge_resume(struct usb_interface *intf)
+{
+ struct dun_bridge *dev = usb_get_intfdata(intf);
+ int ret = 0;
+
+ if (dev->ops && dev->ops->ctrl_status) {
+ ret = usb_submit_urb(dev->inturb, GFP_KERNEL);
+ if (ret)
+ dev_err(&dev->udev->dev, "%s: submit int urb err: %d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
+#define VALID_INTERFACE_NUM 2
+static const struct usb_device_id id_table[] = {
+ { USB_DEVICE(0x05c6, 0x9001), /* Generic QC Modem device */
+ .driver_info = VALID_INTERFACE_NUM },
+ { } /* Terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, id_table);
+
+static struct usb_driver dun_bridge_driver = {
+ .name = "dun_usb_bridge",
+ .probe = dun_bridge_probe,
+ .disconnect = dun_bridge_disconnect,
+ .id_table = id_table,
+ .suspend = dun_bridge_suspend,
+ .resume = dun_bridge_resume,
+ .supports_autosuspend = true,
+};
+
+static int __init dun_bridge_init(void)
+{
+ int ret;
+
+ ret = usb_register(&dun_bridge_driver);
+ if (ret)
+ pr_err("%s: unable to register dun_bridge_driver\n", __func__);
+
+ return ret;
+}
+
+static void __exit dun_bridge_exit(void)
+{
+ usb_deregister(&dun_bridge_driver);
+}
+
+module_init(dun_bridge_init);
+module_exit(dun_bridge_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL V2");
diff --git a/drivers/usb/misc/dun_bridge_test.c b/drivers/usb/misc/dun_bridge_test.c
new file mode 100644
index 0000000..d545e13
--- /dev/null
+++ b/drivers/usb/misc/dun_bridge_test.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/usb/cdc.h>
+#include <linux/uaccess.h>
+#include <mach/usb_dun_bridge.h>
+
+#define RD_BUF_SIZE 2048
+#define DUN_TEST_CONNECTED 0
+
+
+struct dun_bridge_test_dev {
+ char *read_buf;
+ size_t buflen;
+ struct work_struct read_w;
+ unsigned long flags;
+
+ struct dun_bridge_ops ops;
+};
+static struct dun_bridge_test_dev *__dev;
+
+static struct dentry *dfile;
+
+static void
+dun_bridge_test_read_complete(void *d, char *buf, size_t size, size_t actual)
+{
+ if (actual < 0) {
+ pr_err("%s: read complete err\n", __func__);
+ return;
+ }
+
+ __dev->buflen = actual;
+ buf[actual] = 0;
+
+ pr_info("%s: %s\n", __func__, buf);
+
+ if (test_bit(DUN_TEST_CONNECTED, &__dev->flags))
+ schedule_work(&__dev->read_w);
+}
+
+static void dun_bridge_test_read_work(struct work_struct *w)
+{
+ struct dun_bridge_test_dev *dev =
+ container_of(w, struct dun_bridge_test_dev, read_w);
+
+ dun_bridge_read(dev->read_buf, RD_BUF_SIZE);
+}
+
+static void
+dun_bridge_test_write_complete(void *d, char *buf, size_t size, size_t actual)
+{
+ struct dun_bridge_test_dev *dev = d;
+
+ if (actual > 0)
+ schedule_work(&dev->read_w);
+
+ kfree(buf);
+}
+
+#if defined(CONFIG_DEBUG_FS)
+#define DEBUG_BUF_SIZE 1024
+
+#define ACM_CTRL_DTR 0x01
+#define ACM_CTRL_RTS 0x02
+
+static int debug_open(struct inode *inode, struct file *file)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ int ret = 0;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (!test_bit(DUN_TEST_CONNECTED, &dev->flags)) {
+ ret = dun_bridge_open(&dev->ops);
+ if (ret)
+ return ret;
+ set_bit(DUN_TEST_CONNECTED, &dev->flags);
+ dun_bridge_send_ctrl_bits(ACM_CTRL_DTR | ACM_CTRL_RTS);
+ }
+
+ return ret;
+}
+
+static ssize_t debug_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ return simple_read_from_buffer(ubuf, count, ppos,
+ dev->read_buf, dev->buflen);
+}
+
+static ssize_t debug_write(struct file *file, const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+ unsigned char *buf;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ buf = kmalloc(count, GFP_KERNEL);
+ if (!buf) {
+ pr_err("%s: unable to allocate mem for writing\n", __func__);
+ return -ENOMEM;
+ }
+
+ if (!copy_from_user(buf, ubuf, count)) {
+ ret = dun_bridge_write(buf, count);
+ if (ret < 0) {
+ pr_err("%s: error writing to dun_bridge\n", __func__);
+ kfree(buf);
+ return ret;
+ }
+ } else {
+ pr_err("%s: error copying for writing\n", __func__);
+ kfree(buf);
+ }
+
+ return count;
+}
+
+const struct file_operations dun_bridge_test_debug_ops = {
+ .open = debug_open,
+ .read = debug_read,
+ .write = debug_write,
+};
+
+static void dun_bridge_test_debug_init(void)
+{
+ dfile = debugfs_create_file("dun_bridge_test", 0555, NULL,
+ NULL, &dun_bridge_test_debug_ops);
+}
+#else
+static void dun_bridge_test_debug_init(void) { }
+#endif
+
+static int __init dun_bridge_test_init(void)
+{
+ struct dun_bridge_test_dev *dev;
+
+ pr_info("%s\n", __func__);
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ __dev = dev;
+
+ dev->ops.read_complete = dun_bridge_test_read_complete;
+ dev->ops.write_complete = dun_bridge_test_write_complete;
+ dev->read_buf = kmalloc(RD_BUF_SIZE, GFP_KERNEL);
+ if (!dev->read_buf) {
+ pr_err("%s: unable to allocate read buffer\n", __func__);
+ kfree(dev);
+ return -ENOMEM;
+ }
+
+ dev->ops.ctxt = dev;
+ INIT_WORK(&dev->read_w, dun_bridge_test_read_work);
+
+ dun_bridge_test_debug_init();
+
+ return 0;
+}
+
+static void __exit dun_bridge_test_exit(void)
+{
+ struct dun_bridge_test_dev *dev = __dev;
+
+ pr_info("%s:\n", __func__);
+
+ if (test_bit(DUN_TEST_CONNECTED, &dev->flags))
+ dun_bridge_close();
+
+ debugfs_remove(dfile);
+
+ kfree(dev->read_buf);
+ kfree(dev);
+}
+
+module_init(dun_bridge_test_init);
+module_exit(dun_bridge_test_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL V2");
diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig
index d3059d1..34b564f 100644
--- a/drivers/video/msm/Kconfig
+++ b/drivers/video/msm/Kconfig
@@ -156,6 +156,10 @@
select FB_MSM_MIPI_DSI
default n
+config FB_MSM_MIPI_DSI_TRULY
+ bool
+ select FB_MSM_MIPI_DSI
+
config FB_MSM_MIPI_DSI_SIMULATOR
bool
select FB_MSM_MIPI_DSI
@@ -282,6 +286,10 @@
The panel is connected to the host
via Toshiba DSI-to-LVDS bridge.
+config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
+ bool
+ select FB_MSM_MIPI_DSI_TRULY
+
config FB_MSM_MIPI_SIMULATOR_VIDEO
bool
select FB_MSM_MIPI_DSI_SIMULATOR
@@ -390,6 +398,7 @@
select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
+ select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
select FB_MSM_MIPI_SIMULATOR_VIDEO
@@ -489,6 +498,10 @@
bool "MIPI Chimei WXGA PT Panel"
select FB_MSM_MIPI_CHIMEI_WXGA
+config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT_PANEL
+ bool "MIPI Truly Video WVGA PT Panel"
+ select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
+
config FB_MSM_MIPI_SIMULATOR_VIDEO_PANEL
bool "MIPI Simulator Video Panel"
select FB_MSM_MIPI_SIMULATOR_VIDEO
@@ -499,6 +512,11 @@
---help---
Support for EBI2 TMD QVGA (240x320) and Epson QCIF (176x220) panel
+config FB_MSM_HDMI_AS_PRIMARY
+ bool "Use HDMI as primary panel"
+ ---help---
+ Support for using HDMI as primary
+
config FB_MSM_PANEL_NONE
bool "NONE"
---help---
@@ -597,6 +615,14 @@
Support for HDCP mode for MSM HDMI 1080p Panel
Choose to enable HDCP
+config FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ depends on FB_MSM_HDMI_MSM_PANEL
+ bool "Enable CEC"
+ default n
+ ---help---
+ Support for HDMI CEC Feature
+ Choose to enable CEC
+
choice
depends on (FB_MSM_MDP22 || FB_MSM_MDP31 || FB_MSM_MDP40)
prompt "TVOut Region"
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile
index 3e89f0b..d6e8ced 100644
--- a/drivers/video/msm/Makefile
+++ b/drivers/video/msm/Makefile
@@ -71,6 +71,7 @@
obj-$(CONFIG_FB_MSM_MIPI_DSI_TOSHIBA) += mipi_toshiba.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_NOVATEK) += mipi_novatek.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_RENESAS) += mipi_renesas.o
+obj-$(CONFIG_FB_MSM_MIPI_DSI_TRULY) += mipi_truly.o
obj-$(CONFIG_FB_MSM_MIPI_DSI_SIMULATOR) += mipi_simulator.o
# MIPI Bridge
@@ -107,14 +108,23 @@
obj-$(CONFIG_FB_MSM_MDDI_QUICKVX) += mddi_quickvx.o
endif
+ifeq ($(CONFIG_FB_MSM_MIPI_PANEL_DETECT),y)
+obj-y += mipi_toshiba_video_wvga_pt.o mipi_toshiba_video_wsvga_pt.o
+obj-y += mipi_novatek_video_qhd_pt.o mipi_novatek_cmd_qhd_pt.o
+obj-y += mipi_renesas_video_fwvga_pt.o mipi_renesas_cmd_fwvga_pt.o
+obj-y += mipi_chimei_wxga_pt.o
+obj-y += mipi_truly_video_wvga_pt.o
+else
obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT) += mipi_toshiba_video_wvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT) += mipi_toshiba_video_wsvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT) += mipi_novatek_video_qhd_pt.o
obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT) += mipi_novatek_cmd_qhd_pt.o
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT) += mipi_renesas_cmd_fwvga_pt.o
+obj-$(CONFIG_FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT) += mipi_truly_video_wvga_pt.o
obj-$(CONFIG_FB_MSM_MIPI_SIMULATOR_VIDEO) += mipi_simulator_video.o
obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WXGA) += mipi_chimei_wxga_pt.o
+endif
obj-$(CONFIG_FB_MSM_LCDC_PANEL) += lcdc_panel.o
obj-$(CONFIG_FB_MSM_LCDC_PRISM_WVGA) += lcdc_prism.o
diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c
index 4203779..1d87de6 100644
--- a/drivers/video/msm/external_common.c
+++ b/drivers/video/msm/external_common.c
@@ -18,7 +18,9 @@
/* #define DEBUG */
#define DEV_DBG_PREFIX "EXT_COMMON: "
+/* #define CEC_COMPLIANCE_TESTING */
#include "msm_fb.h"
+#include "hdmi_msm.h"
#include "external_common.h"
struct external_common_state_type *external_common_state;
@@ -26,6 +28,7 @@
DEFINE_MUTEX(external_common_state_hpd_mutex);
EXPORT_SYMBOL(external_common_state_hpd_mutex);
+
static int atoi(const char *name)
{
int val = 0;
@@ -280,8 +283,11 @@
struct device_attribute *attr, const char *buf, size_t count)
{
ssize_t ret = strnlen(buf, PAGE_SIZE);
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ int hpd = 1;
+#else
int hpd = atoi(buf);
-
+#endif
if (external_common_state->hpd_feature) {
if (hpd == 0 && external_common_state->hpd_feature_on) {
external_common_state->hpd_feature(0);
@@ -304,6 +310,132 @@
return ret;
}
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+/*
+ * This interface for CEC feature is defined to suit
+ * the current requirements. However, the actual functionality is
+ * added to accommodate different interfaces
+ */
+static ssize_t hdmi_msm_rda_cec(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ /* 0x028C CEC_CTRL */
+ ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
+ (HDMI_INP(0x028C) & BIT(0)));
+ return ret;
+}
+
+static ssize_t hdmi_msm_wta_cec(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ ssize_t ret = strnlen(buf, PAGE_SIZE);
+ int cec = atoi(buf);
+
+ if (cec != 0) {
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_enabled = true;
+ hdmi_msm_state->cec_logical_addr = 4;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ hdmi_msm_cec_init();
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ DEV_DBG("CEC enabled\n");
+ } else {
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_enabled = false;
+ hdmi_msm_state->cec_logical_addr = 15;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, 0);
+ DEV_DBG("CEC disabled\n");
+ }
+ return ret;
+}
+
+static ssize_t hdmi_msm_rda_cec_logical_addr(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ ssize_t ret;
+
+ mutex_lock(&hdmi_msm_state_mutex);
+ ret = snprintf(buf, PAGE_SIZE, "%d\n",
+ hdmi_msm_state->cec_logical_addr);
+ mutex_unlock(&hdmi_msm_state_mutex);
+ return ret;
+}
+
+static ssize_t hdmi_msm_wta_cec_logical_addr(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+
+#ifdef CEC_COMPLIANCE_TESTING
+ /*
+ * Only for testing
+ */
+ hdmi_msm_cec_one_touch_play();
+ return 0;
+#else
+ ssize_t ret = strnlen(buf, PAGE_SIZE);
+ int logical_addr = atoi(buf);
+
+ if (logical_addr < 0 || logical_addr > 15)
+ return -EINVAL;
+
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_logical_addr = logical_addr;
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ hdmi_msm_cec_write_logical_addr(logical_addr);
+
+ return ret;
+#endif
+}
+
+static ssize_t hdmi_msm_rda_cec_frame(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_queue_rd == hdmi_msm_state->cec_queue_wr
+ && !hdmi_msm_state->cec_queue_full) {
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_ERR("CEC message queue is empty\n");
+ return -EBUSY;
+ }
+ memcpy(buf, hdmi_msm_state->cec_queue_rd++,
+ sizeof(struct hdmi_msm_cec_msg));
+ hdmi_msm_state->cec_queue_full = false;
+ if (hdmi_msm_state->cec_queue_rd == CEC_QUEUE_END)
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ return sizeof(struct hdmi_msm_cec_msg);
+}
+
+static ssize_t hdmi_msm_wta_cec_frame(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int retry = ((struct hdmi_msm_cec_msg *) buf)->retransmit;
+
+ if (retry > 15)
+ retry = 15;
+ while (1) {
+ hdmi_msm_cec_msg_send((struct hdmi_msm_cec_msg *) buf);
+ if (hdmi_msm_state->cec_frame_wr_status
+ & CEC_STATUS_WR_ERROR && retry--)
+ msleep(360);
+ else
+ break;
+ }
+
+ if (hdmi_msm_state->cec_frame_wr_status & CEC_STATUS_WR_DONE)
+ return sizeof(struct hdmi_msm_cec_msg);
+ else
+ return -EINVAL;
+}
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
static ssize_t hdmi_common_rda_3d_present(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -361,6 +493,23 @@
}
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+static DEVICE_ATTR(cec, S_IRUGO | S_IWUSR,
+ hdmi_msm_rda_cec,
+ hdmi_msm_wta_cec);
+
+static DEVICE_ATTR(cec_logical_addr, S_IRUGO | S_IWUSR,
+ hdmi_msm_rda_cec_logical_addr,
+ hdmi_msm_wta_cec_logical_addr);
+
+static DEVICE_ATTR(cec_rd_frame, S_IRUGO,
+ hdmi_msm_rda_cec_frame, NULL);
+
+static DEVICE_ATTR(cec_wr_frame, S_IWUSR,
+ NULL, hdmi_msm_wta_cec_frame);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
+
static ssize_t external_common_rda_video_mode(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -453,6 +602,12 @@
#ifdef CONFIG_FB_MSM_HDMI_3D
&dev_attr_format_3d.attr,
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ &dev_attr_cec.attr,
+ &dev_attr_cec_logical_addr.attr,
+ &dev_attr_cec_rd_frame.attr,
+ &dev_attr_cec_wr_frame.attr,
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
NULL,
};
static struct attribute_group external_common_fs_attr_group = {
@@ -1283,7 +1438,11 @@
pinfo->pdest = DISPLAY_2;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ pinfo->fb_num = 2;
+#else
pinfo->fb_num = 1;
+#endif
/* blk */
pinfo->lcdc.border_clr = 0;
diff --git a/drivers/video/msm/external_common.h b/drivers/video/msm/external_common.h
index 30a8f48..f629d0f 100644
--- a/drivers/video/msm/external_common.h
+++ b/drivers/video/msm/external_common.h
@@ -225,6 +225,7 @@
/* The external interface driver needs to initialize the common state. */
extern struct external_common_state_type *external_common_state;
extern struct mutex external_common_state_hpd_mutex;
+extern struct mutex hdmi_msm_state_mutex;
#ifdef CONFIG_FB_MSM_HDMI_COMMON
#define VFRMT_NOT_SUPPORTED(VFRMT) \
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
index fe3c614..63c2147 100644
--- a/drivers/video/msm/hdmi_msm.c
+++ b/drivers/video/msm/hdmi_msm.c
@@ -15,6 +15,9 @@
#define DEV_DBG_PREFIX "HDMI: "
/* #define REG_DUMP */
+#define CEC_MSG_PRINT
+/* #define CEC_COMPLIANCE_TESTING */
+
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/clk.h>
@@ -49,7 +52,8 @@
struct workqueue_struct *hdmi_work_queue;
struct hdmi_msm_state_type *hdmi_msm_state;
-static DEFINE_MUTEX(hdmi_msm_state_mutex);
+DEFINE_MUTEX(hdmi_msm_state_mutex);
+EXPORT_SYMBOL(hdmi_msm_state_mutex);
static DEFINE_MUTEX(hdcp_auth_state_mutex);
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT
@@ -58,6 +62,478 @@
static inline void hdmi_msm_hdcp_enable(void) {}
#endif
+static void hdmi_msm_turn_on(void);
+static int hdmi_msm_audio_off(void);
+static int hdmi_msm_read_edid(void);
+static void hdmi_msm_hpd_off(void);
+
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+
+#define HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE BIT(16)
+#define HDMI_MSM_CEC_REFTIMER_REFTIMER(___t) (((___t)&0xFFFF) << 0)
+
+#define HDMI_MSM_CEC_TIME_SIGNAL_FREE_TIME(___t) (((___t)&0x1FF) << 7)
+#define HDMI_MSM_CEC_TIME_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(___la) (((___la)&0xFF) << 0)
+
+#define HDMI_MSM_CEC_CTRL_LINE_OE BIT(9)
+#define HDMI_MSM_CEC_CTRL_FRAME_SIZE(___sz) (((___sz)&0x1F) << 4)
+#define HDMI_MSM_CEC_CTRL_SOFT_RESET BIT(2)
+#define HDMI_MSM_CEC_CTRL_SEND_TRIG BIT(1)
+#define HDMI_MSM_CEC_CTRL_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK BIT(7)
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK BIT(6)
+#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_INT BIT(6)
+#define HDMI_MSM_CEC_INT_MONITOR_MASK BIT(5)
+#define HDMI_MSM_CEC_INT_MONITOR_ACK BIT(4)
+#define HDMI_MSM_CEC_INT_MONITOR_INT BIT(4)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_MASK BIT(3)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_ACK BIT(2)
+#define HDMI_MSM_CEC_INT_FRAME_ERROR_INT BIT(2)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK BIT(1)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK BIT(0)
+#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT BIT(0)
+
+#define HDMI_MSM_CEC_FRAME_WR_SUCCESS(___st) (((___st)&0xF) ==\
+ (HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT &&\
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK &&\
+ (HDMI_MSM_CEC_INT_FRAME_ERROR_MASK &&\
+ !(HDMI_MSM_CEC_INT_FRAME_ERROR_INT))))
+
+#define HDMI_MSM_CEC_RETRANSMIT_NUM(___num) (((___num)&0xF) << 4)
+#define HDMI_MSM_CEC_RETRANSMIT_ENABLE BIT(0)
+
+#define HDMI_MSM_CEC_WR_DATA_DATA(___d) (((___d)&0xFF) << 8)
+
+
+void hdmi_msm_cec_init(void)
+{
+ /* 0x02A8 CEC_REFTIMER */
+ HDMI_OUTP(0x02A8,
+ HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE
+ | HDMI_MSM_CEC_REFTIMER_REFTIMER(27 * 50)
+ );
+
+ /* 0x02A4 CEC_TIME */
+ HDMI_OUTP(0x02A4,
+ HDMI_MSM_CEC_TIME_SIGNAL_FREE_TIME(350)
+ | HDMI_MSM_CEC_TIME_ENABLE
+ );
+
+ /*
+ * 0x02A0 CEC_ADDR
+ * Starting with a default address of 4
+ */
+ HDMI_OUTP(0x02A0, HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(4));
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+
+ /* 0x029C CEC_INT */
+ /* Enable CEC interrupts */
+ HDMI_OUTP(0x029C, \
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK \
+ | HDMI_MSM_CEC_INT_FRAME_ERROR_MASK \
+ | HDMI_MSM_CEC_INT_MONITOR_MASK \
+ | HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK);
+
+ HDMI_OUTP(0x02B0, 0x7FF << 4 | 1);
+
+ /*
+ * Slight adjustment to logic 1 low periods on read,
+ * CEC Test 8.2-3 was failing, 8 for the
+ * BIT_1_ERR_RANGE_HI = 8 => 750us, the test used 775us,
+ * so increased this to 9 which => 800us.
+ */
+ HDMI_OUTP(0x02E0, 0x889788);
+
+ /*
+ * Slight adjustment to logic 0 low period on write
+ */
+ HDMI_OUTP(0x02DC, 0x8888A888);
+
+ /*
+ * Enable Signal Free Time counter and set to 7 bit periods
+ */
+ HDMI_OUTP(0x02A4, 0x1 | (7 * 0x30) << 7);
+
+}
+
+void hdmi_msm_cec_write_logical_addr(int addr)
+{
+ /* 0x02A0 CEC_ADDR
+ * LOGICAL_ADDR 7:0 NUM
+ */
+ HDMI_OUTP(0x02A0, addr & 0xFF);
+}
+
+void hdmi_msm_dump_cec_msg(struct hdmi_msm_cec_msg *msg)
+{
+#ifdef CEC_MSG_PRINT
+ int i;
+ DEV_DBG("sender_id : %d", msg->sender_id);
+ DEV_DBG("recvr_id : %d", msg->recvr_id);
+ if (msg->frame_size < 2) {
+ DEV_DBG("polling message");
+ return;
+ }
+ DEV_DBG("opcode : %02x", msg->opcode);
+ for (i = 0; i < msg->frame_size - 2; i++)
+ DEV_DBG("operand(%2d) : %02x", i + 1, msg->operand[i]);
+#endif /* CEC_MSG_PRINT */
+}
+
+void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg)
+{
+ int i;
+ uint32 timeout_count = 1;
+ int retry = 10;
+
+ boolean frameType = (msg->recvr_id == 15 ? BIT(0) : 0);
+
+ INIT_COMPLETION(hdmi_msm_state->cec_frame_wr_done);
+ hdmi_msm_state->cec_frame_wr_status = 0;
+
+ /* 0x0294 HDMI_MSM_CEC_RETRANSMIT */
+ HDMI_OUTP(0x0294,
+ HDMI_MSM_CEC_RETRANSMIT_NUM(msg->retransmit)
+ | (msg->retransmit > 0) ? HDMI_MSM_CEC_RETRANSMIT_ENABLE : 0);
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C, 0x1 | msg->frame_size << 4);
+
+ /* 0x0290 CEC_WR_DATA */
+
+ /* header block */
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->sender_id << 4 | msg->recvr_id)
+ | frameType);
+
+ /* data block 0 : opcode */
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->frame_size < 2 ? 0 : msg->opcode)
+ | frameType);
+
+ /* data block 1-14 : operand 0-13 */
+ for (i = 0; i < msg->frame_size - 1; i++)
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(msg->operand[i])
+ | (msg->recvr_id == 15 ? BIT(0) : 0));
+
+ for (; i < 14; i++)
+ HDMI_OUTP(0x0290,
+ HDMI_MSM_CEC_WR_DATA_DATA(0)
+ | (msg->recvr_id == 15 ? BIT(0) : 0));
+
+ while ((HDMI_INP(0x0298) & 1) && retry--) {
+ DEV_DBG("CEC line is busy(%d)\n", retry);
+ schedule();
+ }
+
+ /* 0x028C CEC_CTRL */
+ HDMI_OUTP(0x028C,
+ HDMI_MSM_CEC_CTRL_LINE_OE
+ | HDMI_MSM_CEC_CTRL_FRAME_SIZE(msg->frame_size)
+ | HDMI_MSM_CEC_CTRL_SEND_TRIG
+ | HDMI_MSM_CEC_CTRL_ENABLE);
+
+ timeout_count = wait_for_completion_interruptible_timeout(
+ &hdmi_msm_state->cec_frame_wr_done, HZ);
+
+ if (!timeout_count) {
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_TMOUT;
+ DEV_ERR("%s: timedout", __func__);
+ hdmi_msm_dump_cec_msg(msg);
+ } else {
+ DEV_DBG("CEC write frame done (frame len=%d)",
+ msg->frame_size);
+ hdmi_msm_dump_cec_msg(msg);
+ }
+}
+
+void hdmi_msm_cec_msg_recv(void)
+{
+ uint32 data;
+ int i;
+#ifdef CEC_COMPLIANCE_TESTING
+ struct hdmi_msm_cec_msg temp_msg;
+#endif
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd
+ && hdmi_msm_state->cec_queue_full) {
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_ERR("CEC message queue is overflowing\n");
+#ifdef CEC_COMPLIANCE_TESTING
+ /*
+ * Without CEC daemon:
+ * Compliance tests fail once the queue gets filled up.
+ * so reset the pointers to the start of the queue.
+ */
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_full = false;
+#else
+ return;
+#endif
+ }
+ if (hdmi_msm_state->cec_queue_wr == NULL) {
+ DEV_ERR("%s: wp is NULL\n", __func__);
+ return;
+ }
+ mutex_unlock(&hdmi_msm_state_mutex);
+
+ /* 0x02AC CEC_RD_DATA */
+ data = HDMI_INP(0x02AC);
+
+ hdmi_msm_state->cec_queue_wr->sender_id = (data & 0xF0) >> 4;
+ hdmi_msm_state->cec_queue_wr->recvr_id = (data & 0x0F);
+ hdmi_msm_state->cec_queue_wr->frame_size = (data & 0x1F00) >> 8;
+ DEV_DBG("Recvd init=[%u] dest=[%u] size=[%u]\n",
+ hdmi_msm_state->cec_queue_wr->sender_id,
+ hdmi_msm_state->cec_queue_wr->recvr_id,
+ hdmi_msm_state->cec_queue_wr->frame_size);
+
+ if (hdmi_msm_state->cec_queue_wr->frame_size < 1) {
+ DEV_ERR("%s: invalid message (frame length = %d)",
+ __func__, hdmi_msm_state->cec_queue_wr->frame_size);
+ return;
+ } else if (hdmi_msm_state->cec_queue_wr->frame_size == 1) {
+ DEV_DBG("%s: polling message (dest[%x] <- init[%x])",
+ __func__,
+ hdmi_msm_state->cec_queue_wr->recvr_id,
+ hdmi_msm_state->cec_queue_wr->sender_id);
+ return;
+ }
+
+ /* data block 0 : opcode */
+ data = HDMI_INP(0x02AC);
+ hdmi_msm_state->cec_queue_wr->opcode = data & 0xFF;
+
+ /* data block 1-14 : operand 0-13 */
+ for (i = 0; i < hdmi_msm_state->cec_queue_wr->frame_size - 2; i++) {
+ data = HDMI_INP(0x02AC);
+ hdmi_msm_state->cec_queue_wr->operand[i] = data & 0xFF;
+ }
+
+ for (; i < 14; i++)
+ hdmi_msm_state->cec_queue_wr->operand[i] = 0;
+
+ DEV_DBG("CEC read frame done\n");
+ DEV_DBG("=======================================\n");
+ hdmi_msm_dump_cec_msg(hdmi_msm_state->cec_queue_wr);
+ DEV_DBG("=======================================\n");
+
+#ifdef CEC_COMPLIANCE_TESTING
+ switch (hdmi_msm_state->cec_queue_wr->opcode) {
+ case 0x64:
+ /* Set OSD String */
+ DEV_INFO("Recvd OSD Str=[%x]\n",\
+ hdmi_msm_state->cec_queue_wr->operand[3]);
+ break;
+ case 0x83:
+ /* Give Phy Addr */
+ DEV_INFO("Recvd a Give Phy Addr cmd\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ /* Setup a frame for sending out phy addr */
+ temp_msg.sender_id = 0x4;
+
+ /* Broadcast */
+ temp_msg.recvr_id = 0xf;
+ temp_msg.opcode = 0x84;
+ i = 0;
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.operand[i++] = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0xFF:
+ /* Abort */
+ DEV_INFO("Recvd an abort cmd 0xFF\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /*feature abort */
+ temp_msg.opcode = 0x00;
+ temp_msg.operand[i++] =
+ hdmi_msm_state->cec_queue_wr->opcode;
+
+ /*reason for abort = "Refused" */
+ temp_msg.operand[i++] = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_dump_cec_msg(&temp_msg);
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x046:
+ /* Give OSD name */
+ DEV_INFO("Recvd cmd 0x046\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /* OSD Name */
+ temp_msg.opcode = 0x47;
+
+ /* Display control byte */
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x08F:
+ /* Give Device Power status */
+ DEV_INFO("Recvd a Power status message\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+
+ /* OSD String */
+ temp_msg.opcode = 0x90;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ case 0x080:
+ /* Routing Change cmd */
+ case 0x086:
+ /* Set Stream Path */
+ DEV_INFO("Recvd Set Stream\n");
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+
+ /*Broadcast this message*/
+ temp_msg.recvr_id = 0xf;
+ i = 0;
+ temp_msg.opcode = 0x82; /* Active Source */
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+
+ /*
+ * sending <Image View On> message
+ */
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* opcode for Image View On */
+ temp_msg.opcode = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+ default:
+ DEV_INFO("Recvd an unknown cmd = [%u]\n",
+ hdmi_msm_state->cec_queue_wr->opcode);
+#ifdef __SEND_ABORT__
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* opcode for feature abort */
+ temp_msg.opcode = 0x00;
+ temp_msg.operand[i++] =
+ hdmi_msm_state->cec_queue_wr->opcode;
+ /*reason for abort = "Unrecognized opcode" */
+ temp_msg.operand[i++] = 0x00;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+#else
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* OSD String */
+ temp_msg.opcode = 0x64;
+ temp_msg.operand[i++] = 0x0;
+ temp_msg.operand[i++] = 'H';
+ temp_msg.operand[i++] = 'e';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = ' ';
+ temp_msg.operand[i++] = 'W';
+ temp_msg.operand[i++] = 'o';
+ temp_msg.operand[i++] = 'r';
+ temp_msg.operand[i++] = 'l';
+ temp_msg.operand[i++] = 'd';
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ break;
+#endif /* __SEND_ABORT__ */
+ }
+
+#endif /* CEC_COMPLIANCE_TESTING */
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_queue_wr++;
+ if (hdmi_msm_state->cec_queue_wr == CEC_QUEUE_END)
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd)
+ hdmi_msm_state->cec_queue_full = true;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ DEV_DBG("Exiting %s()\n", __func__);
+}
+
+void hdmi_msm_cec_one_touch_play(void)
+{
+ struct hdmi_msm_cec_msg temp_msg;
+ uint32 i = 0;
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ /*
+ * Broadcast this message
+ */
+ temp_msg.recvr_id = 0xf;
+ i = 0;
+ /* Active Source */
+ temp_msg.opcode = 0x82;
+ temp_msg.operand[i++] = 0x10;
+ temp_msg.operand[i++] = 0x00;
+ /*temp_msg.operand[i++] = 0x04;*/
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+ /*
+ * sending <Image View On> message
+ */
+ memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
+ temp_msg.sender_id = 0x4;
+ temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
+ i = 0;
+ /* Image View On */
+ temp_msg.opcode = 0x04;
+ temp_msg.frame_size = i + 2;
+ hdmi_msm_cec_msg_send(&temp_msg);
+
+}
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
uint32 hdmi_msm_get_io_base(void)
{
return (uint32)MSM_HDMI_BASE;
@@ -276,17 +752,18 @@
} else {
hdmi_msm_state->hpd_cable_chg_detected = FALSE;
mutex_unlock(&hdmi_msm_state_mutex);
+ /* QDSP OFF preceding the HPD event notification */
+ envp[0] = "HDCP_STATE=FAIL";
+ envp[1] = NULL;
+ DEV_INFO("HDMI HPD: QDSP OFF\n");
+ kobject_uevent_env(external_common_state->uevent_kobj,
+ KOBJ_CHANGE, envp);
if (hpd_state) {
hdmi_msm_read_edid();
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT
hdmi_msm_state->reauth = FALSE ;
#endif
/* Build EDID table */
- envp[0] = "HDCP_STATE=FAIL";
- envp[1] = NULL;
- DEV_INFO("HDMI HPD: QDSP OFF\n");
- kobject_uevent_env(external_common_state->uevent_kobj,
- KOBJ_CHANGE, envp);
hdmi_msm_turn_on();
DEV_INFO("HDMI HPD: sense CONNECTED: send ONLINE\n");
kobject_uevent(external_common_state->uevent_kobj,
@@ -396,6 +873,9 @@
{
uint32 hpd_int_status;
uint32 hpd_int_ctrl;
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ uint32 cec_intr_status;
+#endif
uint32 ddc_int_ctrl;
uint32 audio_int_val;
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT
@@ -600,8 +1080,55 @@
}
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ /* Process CEC Interrupt */
+ /* HDMI_MSM_CEC_INT[0x029C] */
+ cec_intr_status = HDMI_INP_ND(0x029C);
+
+ DEV_DBG("cec interrupt status is [%u]\n", cec_intr_status);
+
+ if (HDMI_MSM_CEC_FRAME_WR_SUCCESS(cec_intr_status)) {
+ DEV_DBG("CEC_IRQ_FRAME_WR_DONE\n");
+ HDMI_OUTP(0x029C, cec_intr_status |
+ HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK);
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_DONE;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ complete(&hdmi_msm_state->cec_frame_wr_done);
+ return IRQ_HANDLED;
+ }
+ if ((cec_intr_status & (1 << 2)) && (cec_intr_status & (1 << 3))) {
+ DEV_DBG("CEC_IRQ_FRAME_ERROR\n");
+ /* Toggle CEC hardware FSM */
+ HDMI_OUTP(0x028C, 0x0);
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+ HDMI_OUTP(0x029C, cec_intr_status);
+ mutex_lock(&hdmi_msm_state_mutex);
+ hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_ERROR;
+ mutex_unlock(&hdmi_msm_state_mutex);
+ complete(&hdmi_msm_state->cec_frame_wr_done);
+ return IRQ_HANDLED;
+ }
+
+ if ((cec_intr_status & (1 << 4)) && (cec_intr_status & (1 << 5)))
+ DEV_DBG("CEC_IRQ_MONITOR\n");
+
+ if ((cec_intr_status & (1 << 6)) && (cec_intr_status & (1 << 7))) {
+ DEV_DBG("CEC_IRQ_FRAME_RD_DONE\n");
+ HDMI_OUTP(0x029C, cec_intr_status |
+ HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK);
+ hdmi_msm_cec_msg_recv();
+
+ /* Toggle CEC hardware FSM */
+ HDMI_OUTP(0x028C, 0x0);
+ HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
+
+ return IRQ_HANDLED;
+ }
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>, ddc_int_ctrl=%04x, "
- "aud_int=%04x, cec_int=%04x\n", __func__, hpd_int_ctrl,
+ "aud_int=%04x, cec_intr_status=%04x\n", __func__, hpd_int_ctrl,
hpd_int_status, ddc_int_ctrl, audio_int_val,
HDMI_INP_ND(0x029C));
@@ -3129,6 +3656,17 @@
hdmi_msm_state->reauth = FALSE ;
}
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ /* re-initialize CEC if enabled */
+ mutex_lock(&hdmi_msm_state_mutex);
+ if (hdmi_msm_state->cec_enabled == true) {
+ hdmi_msm_cec_init();
+ hdmi_msm_cec_write_logical_addr(
+ hdmi_msm_state->cec_logical_addr);
+ }
+ mutex_unlock(&hdmi_msm_state_mutex);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
DEV_INFO("HDMI Core: Initialized\n");
}
@@ -3186,6 +3724,7 @@
hdmi_msm_set_mode(FALSE);
HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/
hdmi_msm_state->hpd_initialized = FALSE;
+ hdmi_msm_state->pd->cec_power(0);
hdmi_msm_state->pd->enable_5v(0);
hdmi_msm_state->pd->core_power(0, 1);
hdmi_msm_clk(0);
@@ -3207,6 +3746,7 @@
hdmi_msm_clk(1);
hdmi_msm_state->pd->core_power(1, 1);
hdmi_msm_state->pd->enable_5v(1);
+ hdmi_msm_state->pd->cec_power(1);
hdmi_msm_dump_regs("HDMI-INIT: ");
hdmi_msm_set_mode(FALSE);
@@ -3351,7 +3891,7 @@
hdmi_msm_hpd_off();
hdmi_msm_powerdown_phy();
hdmi_msm_dump_regs("HDMI-OFF: ");
- hdmi_msm_hpd_on(false);
+ hdmi_msm_hpd_on(true);
mutex_lock(&external_common_state_hpd_mutex);
if (!external_common_state->hpd_feature_on)
@@ -3454,6 +3994,12 @@
goto error;
}
+ if (!hdmi_msm_state->pd->cec_power) {
+ DEV_ERR("Init FAILED: cec_power function missing\n");
+ rc = -ENODEV;
+ goto error;
+ }
+
rc = request_threaded_irq(hdmi_msm_state->irq, NULL, &hdmi_msm_isr,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "hdmi_msm_isr", NULL);
if (rc) {
@@ -3685,6 +4231,21 @@
external_common_state->switch_3d = hdmi_msm_switch_3d;
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ hdmi_msm_state->cec_queue_start =
+ kzalloc(sizeof(struct hdmi_msm_cec_msg)*CEC_QUEUE_SIZE,
+ GFP_KERNEL);
+ if (!hdmi_msm_state->cec_queue_start) {
+ pr_err("hdmi_msm_init FAILED: CEC queue out of memory\n");
+ rc = -ENOMEM;
+ goto init_exit;
+ }
+
+ hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
+ hdmi_msm_state->cec_queue_full = false;
+#endif
+
/*
* Create your work queue
* allocs and returns ptr
@@ -3709,6 +4270,10 @@
INIT_WORK(&hdmi_msm_state->hdcp_work, hdmi_msm_hdcp_work);
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ init_completion(&hdmi_msm_state->cec_frame_wr_done);
+#endif
+
rc = platform_device_register(&this_device);
if (rc) {
pr_err("hdmi_msm_init FAILED: platform_device_register rc=%d\n",
diff --git a/drivers/video/msm/hdmi_msm.h b/drivers/video/msm/hdmi_msm.h
index 2f44b6d..6d19d157 100644
--- a/drivers/video/msm/hdmi_msm.h
+++ b/drivers/video/msm/hdmi_msm.h
@@ -33,7 +33,22 @@
#define HDMI_INP(offset) inpdw(MSM_HDMI_BASE+(offset))
#endif
+
+/*
+ * Ref. HDMI 1.4a
+ * Supplement-1 CEC Section 6, 7
+ */
+struct hdmi_msm_cec_msg {
+ uint8 sender_id;
+ uint8 recvr_id;
+ uint8 opcode;
+ uint8 operand[15];
+ uint8 frame_size;
+ uint8 retransmit;
+};
+
#define QFPROM_BASE ((uint32)hdmi_msm_state->qfprom_io)
+#define HDMI_BASE ((uint32)hdmi_msm_state->hdmi_io)
struct hdmi_msm_state_type {
boolean panel_power_on;
@@ -58,6 +73,23 @@
struct timer_list hdcp_timer;
#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_HDCP_SUPPORT */
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+ boolean cec_enabled;
+ int cec_logical_addr;
+ struct completion cec_frame_wr_done;
+#define CEC_STATUS_WR_ERROR 0x0001
+#define CEC_STATUS_WR_DONE 0x0002
+#define CEC_STATUS_WR_TMOUT 0x0004
+ uint32 cec_frame_wr_status;
+
+ struct hdmi_msm_cec_msg *cec_queue_start;
+ struct hdmi_msm_cec_msg *cec_queue_wr;
+ struct hdmi_msm_cec_msg *cec_queue_rd;
+ boolean cec_queue_full;
+#define CEC_QUEUE_SIZE 16
+#define CEC_QUEUE_END (hdmi_msm_state->cec_queue_start + CEC_QUEUE_SIZE)
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
int irq;
struct msm_hdmi_platform_data *pd;
struct clk *hdmi_app_clk;
@@ -84,4 +116,12 @@
void hdmi_msm_phy_status_poll(void);
#endif
+#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
+void hdmi_msm_cec_init(void);
+void hdmi_msm_cec_write_logical_addr(int addr);
+void hdmi_msm_cec_msg_recv(void);
+void hdmi_msm_cec_one_touch_play(void);
+void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg);
+#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
+
#endif /* __HDMI_MSM_H__ */
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 37c9ca8..c522b0f 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -541,7 +541,7 @@
#ifdef CONFIG_FB_MSM_MDP303
#ifdef CONFIG_FB_MSM_MIPI_DSI
- mipi_dsi_cmd_mdp_sw_trigger();
+ mipi_dsi_cmd_mdp_start();
#endif
#endif
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 0740f42..fd2f13e 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -143,7 +143,7 @@
};
/* 2 VG pipes can be shared by RGB and VIDEO */
-#define MDP4_MAX_PIPE (OVERLAY_PIPE_MAX + 2)
+#define MDP4_MAX_PIPE (OVERLAY_PIPE_MAX + 2)
#define OVERLAY_TYPE_RGB 0x01
#define OVERLAY_TYPE_VIDEO 0x02
@@ -343,6 +343,7 @@
ulong err_format;
};
+struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx);
void mdp4_sw_reset(unsigned long bits);
void mdp4_display_intf_sel(int output, unsigned long intf);
void mdp4_overlay_cfg(int layer, int blt_mode, int refresh, int direct_out);
@@ -367,16 +368,9 @@
void mdp4_clear_lcdc(void);
void mdp4_mixer_blend_init(int mixer_num);
void mdp4_vg_qseed_init(int vg_num);
-void mdp4_vg_csc_mv_setup(int vp_num);
-void mdp4_vg_csc_pre_bv_setup(int vp_num);
-void mdp4_vg_csc_post_bv_setup(int vp_num);
-void mdp4_vg_csc_pre_lv_setup(int vp_num);
-void mdp4_vg_csc_post_lv_setup(int vp_num);
-void mdp4_mixer1_csc_mv_setup(void);
-void mdp4_mixer1_csc_pre_bv_setup(void);
-void mdp4_mixer1_csc_post_bv_setup(void);
-void mdp4_mixer1_csc_pre_lv_setup(void);
-void mdp4_mixer1_csc_post_lv_setup(void);
+void mdp4_vg_csc_setup(int vp_num);
+void mdp4_mixer1_csc_setup(void);
+void mdp4_vg_csc_update(struct mdp_csc *p);
irqreturn_t mdp4_isr(int irq, void *ptr);
void mdp4_overlay_format_to_pipe(uint32 format, struct mdp4_overlay_pipe *pipe);
uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe);
diff --git a/drivers/video/msm/mdp4_dtv.c b/drivers/video/msm/mdp4_dtv.c
index f07a8b4..a44f7c0 100644
--- a/drivers/video/msm/mdp4_dtv.c
+++ b/drivers/video/msm/mdp4_dtv.c
@@ -223,8 +223,11 @@
* get/set panel specific fb info
*/
mfd->panel_info = pdata->panel_info;
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
+#else
mfd->fb_imgType = MDP_RGB_565;
-
+#endif
fbi = mfd->fbi;
fbi->var.pixclock = mfd->panel_info.clk_rate;
fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index ecefdc3..1b2dec4 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -453,13 +453,15 @@
*luma_off = 0;
*chroma_off = 0;
- if (pipe->src_x) {
+ if (pipe->src_x && (pipe->frame_format ==
+ MDP4_FRAME_FORMAT_LINEAR)) {
src_xy = (pipe->src_y << 16) | pipe->src_x;
src_xy &= 0xffff0000;
outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
switch (pipe->src_format) {
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
*luma_off = pipe->src_x;
*chroma_off = pipe->src_x/2;
@@ -520,6 +522,11 @@
dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
ptype = mdp4_overlay_format2type(pipe->src_format);
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ frame_size = ((pipe->src_height << 16) |
+ ALIGN(pipe->src_width, 16));
+ src_size = ((pipe->src_h << 16) | ALIGN(pipe->src_w, 16));
+ }
format = mdp4_overlay_format(pipe);
pattern = mdp4_overlay_unpack_pattern(pipe);
@@ -540,7 +547,7 @@
outpdw(vg_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
outpdw(vg_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
- if (pipe->frame_format)
+ if (pipe->frame_format != MDP4_FRAME_FORMAT_LINEAR)
outpdw(vg_base + 0x0048, frame_size); /* TILE frame size */
/*
@@ -617,6 +624,7 @@
case MDP_Y_CBCR_H2V2_TILE:
case MDP_Y_CRCB_H2V2_TILE:
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
case MDP_Y_CRCB_H1V1:
case MDP_Y_CBCR_H1V1:
@@ -865,6 +873,7 @@
pipe->bpp = 2; /* 2 bpp */
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CB_CR_H2V2:
pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
@@ -960,6 +969,7 @@
b_num = 8;
break;
case MDP_Y_CR_CB_H2V2:
+ case MDP_Y_CR_CB_GH2V2:
case MDP_Y_CRCB_H2V2:
case MDP_Y_CRCB_H2V1:
case MDP_Y_CRCB_H1V1:
@@ -2360,18 +2370,35 @@
pipe->srcp2_addr = start + img->offset;
*pp_src_plane2_file = p_src_plane2_file;
} else {
- addr += (pipe->src_width * pipe->src_height);
- pipe->srcp1_addr = addr;
- addr += ((pipe->src_width / 2) *
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ addr += (ALIGN(pipe->src_width, 16) *
+ pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((ALIGN((pipe->src_width / 2), 16)) *
(pipe->src_height / 2));
- pipe->srcp2_addr = addr;
+ pipe->srcp2_addr = addr;
+ } else {
+ addr += (pipe->src_width * pipe->src_height);
+ pipe->srcp1_addr = addr;
+ addr += ((pipe->src_width / 2) *
+ (pipe->src_height / 2));
+ pipe->srcp2_addr = addr;
+ }
}
/* mdp planar format expects Cb in srcp1 and Cr in p2 */
- if (pipe->src_format == MDP_Y_CR_CB_H2V2)
+ if ((pipe->src_format == MDP_Y_CR_CB_H2V2) ||
+ (pipe->src_format == MDP_Y_CR_CB_GH2V2))
swap(pipe->srcp1_addr, pipe->srcp2_addr);
- pipe->srcp0_ystride = pipe->src_width;
- pipe->srcp1_ystride = pipe->src_width / 2;
- pipe->srcp2_ystride = pipe->src_width / 2;
+
+ if (pipe->src_format == MDP_Y_CR_CB_GH2V2) {
+ pipe->srcp0_ystride = ALIGN(pipe->src_width, 16);
+ pipe->srcp1_ystride = ALIGN(pipe->src_width / 2, 16);
+ pipe->srcp2_ystride = ALIGN(pipe->src_width / 2, 16);
+ } else {
+ pipe->srcp0_ystride = pipe->src_width;
+ pipe->srcp1_ystride = pipe->src_width / 2;
+ pipe->srcp2_ystride = pipe->src_width / 2;
+ }
}
if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
diff --git a/drivers/video/msm/mdp4_overlay_dsi_cmd.c b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
index 4cd69ef..0020fd5 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_cmd.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_cmd.c
@@ -171,8 +171,8 @@
* dma_p = 0, dma_s = 1
*/
MDP_OUTP(MDP_BASE + 0x000a0, 0x10);
- /* enable dsi trigger on dma_p */
- MDP_OUTP(MDP_BASE + 0x000a4, 0x01);
+ /* disable dsi trigger */
+ MDP_OUTP(MDP_BASE + 0x000a4, 0x00);
/* whole screen for base layer */
src = (uint8 *) iBuf->buf;
@@ -461,7 +461,7 @@
/* kick off dmap */
outpdw(MDP_BASE + 0x000c, 0x0);
/* trigger dsi cmd engine */
- mipi_dsi_cmd_mdp_sw_trigger();
+ mipi_dsi_cmd_mdp_start();
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
}
@@ -521,7 +521,7 @@
/* kick off dmap */
outpdw(MDP_BASE + 0x000c, 0x0);
/* trigger dsi cmd engine */
- mipi_dsi_cmd_mdp_sw_trigger();
+ mipi_dsi_cmd_mdp_start();
mdp_disable_irq_nosync(MDP_OVERLAY0_TERM);
}
@@ -638,6 +638,11 @@
/* change mdp clk */
mdp4_set_perf_level();
+ mipi_dsi_mdp_busy_wait(mfd);
+
+ if (dsi_pipe->blt_addr == 0)
+ mipi_dsi_cmd_mdp_start();
+
mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);
spin_lock_irqsave(&mdp_spin_lock, flag);
@@ -648,11 +653,6 @@
/* start OVERLAY pipe */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
-
- if (dsi_pipe->blt_addr == 0) {
- /* trigger dsi cmd engine */
- mipi_dsi_cmd_mdp_sw_trigger();
- }
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index e6ba15e..82bce01 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -115,8 +115,13 @@
format = MDP_RGB_565;
else if (bpp == 3)
format = MDP_RGB_888;
- else
+ else {
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ format = MSMFB_DEFAULT_TYPE;
+#else
format = MDP_ARGB_8888;
+#endif
+ }
if (dtv_pipe == NULL) {
ptype = mdp4_overlay_format2type(format);
@@ -143,7 +148,12 @@
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ if (is_mdp4_hw_reset()) {
+ mdp4_hw_init();
+ outpdw(MDP_BASE + 0x0038, mdp4_display_intf);
+ }
+#endif
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index fb0d771..99607e7 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -265,24 +265,9 @@
mdp4_vg_qseed_init(0);
mdp4_vg_qseed_init(1);
- /* yuv2rgb */
- mdp4_vg_csc_mv_setup(0);
- mdp4_vg_csc_mv_setup(1);
- mdp4_vg_csc_pre_bv_setup(0);
- mdp4_vg_csc_pre_bv_setup(1);
- mdp4_vg_csc_post_bv_setup(0);
- mdp4_vg_csc_post_bv_setup(1);
- mdp4_vg_csc_pre_lv_setup(0);
- mdp4_vg_csc_pre_lv_setup(1);
- mdp4_vg_csc_post_lv_setup(0);
- mdp4_vg_csc_post_lv_setup(1);
-
- /* rgb2yuv */
- mdp4_mixer1_csc_mv_setup();
- mdp4_mixer1_csc_pre_bv_setup();
- mdp4_mixer1_csc_post_bv_setup();
- mdp4_mixer1_csc_pre_lv_setup();
- mdp4_mixer1_csc_post_lv_setup();
+ mdp4_vg_csc_setup(0);
+ mdp4_vg_csc_setup(1);
+ mdp4_mixer1_csc_setup();
if (mdp_rev <= MDP_REV_41) {
mdp4_mixer_gc_lut_setup(0);
@@ -556,8 +541,17 @@
outpdw(MDP_DMA_P_HIST_INTR_CLEAR, isr);
mb();
isr &= mask;
- if (isr & INTR_HIST_DONE)
- complete(&mdp_hist_comp);
+ if (isr & INTR_HIST_DONE) {
+ if (waitqueue_active(&(mdp_hist_comp.wait))) {
+ complete(&mdp_hist_comp);
+ } else {
+ if (mdp_is_hist_start == TRUE) {
+ MDP_OUTP(MDP_BASE + 0x95004,
+ mdp_hist_frame_cnt);
+ MDP_OUTP(MDP_BASE + 0x95000, 1);
+ }
+ }
+ }
}
out:
@@ -1212,17 +1206,54 @@
}
-static uint32 csc_matrix_tab[9] = {
- 0x0254, 0x0000, 0x0331,
- 0x0254, 0xff37, 0xfe60,
- 0x0254, 0x0409, 0x0000
+struct mdp4_csc_matrix {
+uint32 csc_mv[9];
+uint32 csc_pre_bv[3];
+uint32 csc_post_bv[3];
+uint32 csc_pre_lv[6];
+uint32 csc_post_lv[6];
+} csc_matrix[2] = {
+ {
+ {
+ 0x0254, 0x0000, 0x0331,
+ 0x0254, 0xff37, 0xfe60,
+ 0x0254, 0x0409, 0x0000,
+ },
+ {
+ 0xfff0, 0xff80, 0xff80,
+ },
+ {
+ 0, 0, 0,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ },
+ {
+ {
+ 0x0254, 0x0000, 0x0331,
+ 0x0254, 0xff37, 0xfe60,
+ 0x0254, 0x0409, 0x0000,
+ },
+ {
+ 0xfff0, 0xff80, 0xff80,
+ },
+ {
+ 0, 0, 0,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ {
+ 0, 0xff, 0, 0xff, 0, 0xff,
+ },
+ },
};
-static uint32 csc_pre_bv_tab[3] = {0xfff0, 0xff80, 0xff80 };
-static uint32 csc_post_bv_tab[3] = {0, 0, 0 };
-static uint32 csc_pre_lv_tab[6] = {0, 0xff, 0, 0xff, 0, 0xff };
-static uint32 csc_post_lv_tab[6] = {0, 0xff, 0, 0xff, 0, 0xff };
#define MDP4_CSC_MV_OFF 0x4400
#define MDP4_CSC_PRE_BV_OFF 0x4500
@@ -1241,7 +1272,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 9; i++) {
- outpdw(off, csc_matrix_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_mv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1258,7 +1289,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 3; i++) {
- outpdw(off, csc_pre_bv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_pre_bv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1275,7 +1306,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 3; i++) {
- outpdw(off, csc_post_bv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_post_bv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1292,7 +1323,7 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 6; i++) {
- outpdw(off, csc_pre_lv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_pre_lv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
@@ -1309,12 +1340,47 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
for (i = 0; i < 6; i++) {
- outpdw(off, csc_post_lv_tab[i]);
+ outpdw(off, csc_matrix[vp_num].csc_post_lv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+void mdp4_vg_csc_setup(int vp_num)
+{
+ /* yuv2rgb */
+ mdp4_vg_csc_mv_setup(vp_num);
+ mdp4_vg_csc_pre_bv_setup(vp_num);
+ mdp4_vg_csc_post_bv_setup(vp_num);
+ mdp4_vg_csc_pre_lv_setup(vp_num);
+ mdp4_vg_csc_post_lv_setup(vp_num);
+}
+void mdp4_vg_csc_update(struct mdp_csc *p)
+{
+ struct mdp4_overlay_pipe *pipe;
+ int vp_num;
+
+ pipe = mdp4_overlay_ndx2pipe(p->id);
+ if (pipe == NULL) {
+ pr_err("%s: p->id = %d Error\n", __func__, p->id);
+ return;
+ }
+
+ vp_num = pipe->pipe_num - OVERLAY_PIPE_VG1;
+
+ if (vp_num == 0 || vp_num == 1) {
+ memcpy(csc_matrix[vp_num].csc_mv, p->csc_mv, sizeof(p->csc_mv));
+ memcpy(csc_matrix[vp_num].csc_pre_bv, p->csc_pre_bv,
+ sizeof(p->csc_pre_bv));
+ memcpy(csc_matrix[vp_num].csc_post_bv, p->csc_post_bv,
+ sizeof(p->csc_post_bv));
+ memcpy(csc_matrix[vp_num].csc_pre_lv, p->csc_pre_lv,
+ sizeof(p->csc_pre_lv));
+ memcpy(csc_matrix[vp_num].csc_post_lv, p->csc_post_lv,
+ sizeof(p->csc_post_lv));
+ mdp4_vg_csc_setup(vp_num);
+ }
+}
static uint32 csc_rgb2yuv_matrix_tab[9] = {
0x0083, 0x0102, 0x0032,
0x1fb5, 0x1f6c, 0x00e1,
@@ -1410,6 +1476,15 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+void mdp4_mixer1_csc_setup(void)
+{
+ /* rgb2yuv */
+ mdp4_mixer1_csc_mv_setup();
+ mdp4_mixer1_csc_pre_bv_setup();
+ mdp4_mixer1_csc_post_bv_setup();
+ mdp4_mixer1_csc_pre_lv_setup();
+ mdp4_mixer1_csc_post_lv_setup();
+}
char gc_lut[] = {
0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
diff --git a/drivers/video/msm/mipi_dsi.c b/drivers/video/msm/mipi_dsi.c
index c18f2a0..00256e6 100644
--- a/drivers/video/msm/mipi_dsi.c
+++ b/drivers/video/msm/mipi_dsi.c
@@ -87,6 +87,7 @@
if (mdp_rev >= MDP_REV_41) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
+ mipi_dsi_mdp_busy_wait(mfd);
} else {
mdp3_dsi_cmd_dma_busy_wait(mfd);
}
diff --git a/drivers/video/msm/mipi_dsi.h b/drivers/video/msm/mipi_dsi.h
index 14d6bd9..9907109 100644
--- a/drivers/video/msm/mipi_dsi.h
+++ b/drivers/video/msm/mipi_dsi.h
@@ -222,6 +222,17 @@
#define DTYPE_PERIPHERAL_OFF 0x22
#define DTYPE_PERIPHERAL_ON 0x32
+/*
+ * dcs response
+ */
+#define DTYPE_ACK_ERR_RESP 0x02
+#define DTYPE_EOT_RESP 0x08 /* end of tx */
+#define DTYPE_GEN_READ1_RESP 0x11 /* 1 parameter, short */
+#define DTYPE_GEN_READ2_RESP 0x12 /* 2 parameter, short */
+#define DTYPE_GEN_LREAD_RESP 0x1a
+#define DTYPE_DCS_LREAD_RESP 0x1c
+#define DTYPE_DCS_READ1_RESP 0x21 /* 1 parameter, short */
+#define DTYPE_DCS_READ2_RESP 0x22 /* 2 parameter, short */
struct dsi_cmd_desc {
int dtype;
@@ -261,7 +272,7 @@
void mipi_dsi_op_mode_config(int mode);
void mipi_dsi_cmd_mode_ctrl(int enable);
void mdp4_dsi_cmd_trigger(void);
-void mipi_dsi_cmd_mdp_sw_trigger(void);
+void mipi_dsi_cmd_mdp_start(void);
void mipi_dsi_cmd_bta_sw_trigger(void);
void mipi_dsi_ack_err_status(void);
void mipi_dsi_set_tear_on(struct msm_fb_data_type *mfd);
@@ -276,6 +287,7 @@
void mipi_dsi_post_kickoff_del(struct dsi_kickoff_action *act);
void mipi_dsi_controller_cfg(int enable);
void mipi_dsi_sw_reset(void);
+void mipi_dsi_mdp_busy_wait(struct msm_fb_data_type *mfd);
irqreturn_t mipi_dsi_isr(int irq, void *ptr);
diff --git a/drivers/video/msm/mipi_dsi_host.c b/drivers/video/msm/mipi_dsi_host.c
index 0697aac..9caa154 100644
--- a/drivers/video/msm/mipi_dsi_host.c
+++ b/drivers/video/msm/mipi_dsi_host.c
@@ -41,10 +41,12 @@
int mipi_dsi_clk_on;
static struct completion dsi_dma_comp;
+static struct completion dsi_mdp_comp;
static struct dsi_buf dsi_tx_buf;
static int dsi_irq_enabled;
-static int dsi_cmd_trigger;
-static spinlock_t dsi_lock;
+static spinlock_t dsi_irq_lock;
+static spinlock_t dsi_mdp_lock;
+static int dsi_mdp_busy;
static struct list_head pre_kickoff_list;
static struct list_head post_kickoff_list;
@@ -52,54 +54,44 @@
void mipi_dsi_init(void)
{
init_completion(&dsi_dma_comp);
+ init_completion(&dsi_mdp_comp);
mipi_dsi_buf_alloc(&dsi_tx_buf, DSI_BUF_SIZE);
- spin_lock_init(&dsi_lock);
+ spin_lock_init(&dsi_irq_lock);
+ spin_lock_init(&dsi_mdp_lock);
INIT_LIST_HEAD(&pre_kickoff_list);
INIT_LIST_HEAD(&post_kickoff_list);
}
-void mipi_dsi_enable_irq(enum dsi_trigger_type type)
+void mipi_dsi_enable_irq(void)
{
unsigned long flags;
- spin_lock_irqsave(&dsi_lock, flags);
- if (type == DSI_CMD_MODE_DMA)
- dsi_cmd_trigger = 1;
-
- pr_debug("%s(): dsi_irq_enabled %u, dsi_cmd_trigger %u\n",
- __func__, dsi_irq_enabled, dsi_cmd_trigger);
-
+ spin_lock_irqsave(&dsi_irq_lock, flags);
if (dsi_irq_enabled) {
pr_debug("%s: IRQ aleady enabled\n", __func__);
- spin_unlock_irqrestore(&dsi_lock, flags);
+ spin_unlock_irqrestore(&dsi_irq_lock, flags);
return;
}
dsi_irq_enabled = 1;
enable_irq(dsi_irq);
- spin_unlock_irqrestore(&dsi_lock, flags);
+ spin_unlock_irqrestore(&dsi_irq_lock, flags);
}
-void mipi_dsi_disable_irq(enum dsi_trigger_type type)
+void mipi_dsi_disable_irq(void)
{
unsigned long flags;
- spin_lock_irqsave(&dsi_lock, flags);
- if (type == DSI_CMD_MODE_DMA)
- dsi_cmd_trigger = 0;
-
- pr_debug("%s(): dsi_irq_enabled %u, dsi_cmd_trigger %u\n",
- __func__, dsi_irq_enabled, dsi_cmd_trigger);
-
+ spin_lock_irqsave(&dsi_irq_lock, flags);
if (dsi_irq_enabled == 0) {
pr_debug("%s: IRQ already disabled\n", __func__);
- spin_unlock_irqrestore(&dsi_lock, flags);
+ spin_unlock_irqrestore(&dsi_irq_lock, flags);
return;
}
dsi_irq_enabled = 0;
disable_irq(dsi_irq);
- spin_unlock_irqrestore(&dsi_lock, flags);
+ spin_unlock_irqrestore(&dsi_irq_lock, flags);
}
/*
@@ -108,19 +100,16 @@
*/
void mipi_dsi_disable_irq_nosync(void)
{
- spin_lock(&dsi_lock);
- pr_debug("%s(): dsi_irq_enabled %u, dsi_cmd_trigger %u\n",
- __func__, dsi_irq_enabled, dsi_cmd_trigger);
-
- if (dsi_irq_enabled == 0 || dsi_cmd_trigger == 1) {
+ spin_lock(&dsi_irq_lock);
+ if (dsi_irq_enabled == 0) {
pr_debug("%s: IRQ cannot be disabled\n", __func__);
- spin_unlock(&dsi_lock);
+ spin_unlock(&dsi_irq_lock);
return;
}
dsi_irq_enabled = 0;
disable_irq_nosync(dsi_irq);
- spin_unlock(&dsi_lock);
+ spin_unlock(&dsi_irq_lock);
}
void mipi_dsi_turn_on_clks(void)
@@ -728,6 +717,43 @@
return len;
}
+/*
+ * mipi_dsi_short_read1_resp: 1 parameter
+ */
+static int mipi_dsi_short_read1_resp(struct dsi_buf *rp)
+{
+ /* strip out dcs type */
+ rp->data++;
+ rp->len = 1;
+ return rp->len;
+}
+
+/*
+ * mipi_dsi_short_read2_resp: 2 parameter
+ */
+static int mipi_dsi_short_read2_resp(struct dsi_buf *rp)
+{
+ /* strip out dcs type */
+ rp->data++;
+ rp->len = 2;
+ return rp->len;
+}
+
+static int mipi_dsi_long_read_resp(struct dsi_buf *rp)
+{
+ short len;
+
+ len = rp->data[2];
+ len <<= 8;
+ len |= rp->data[1];
+ /* strip out dcs header */
+ rp->data += 4;
+ rp->len -= 4;
+ /* strip out 2 bytes of checksum */
+ rp->len -= 2;
+ return len;
+}
+
void mipi_dsi_host_init(struct mipi_panel_info *pinfo)
{
uint32 dsi_ctrl, intr_ctrl;
@@ -936,12 +962,42 @@
wmb();
}
-void mipi_dsi_cmd_mdp_sw_trigger(void)
+void mipi_dsi_mdp_busy_wait(struct msm_fb_data_type *mfd)
{
- mipi_dsi_pre_kickoff_action();
- mipi_dsi_enable_irq(DSI_CMD_MODE_MDP);
- MIPI_OUTP(MIPI_DSI_BASE + 0x090, 0x01); /* trigger */
- wmb();
+ unsigned long flag;
+ int need_wait = 0;
+
+ pr_debug("%s: start pid=%d\n",
+ __func__, current->pid);
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ if (dsi_mdp_busy == TRUE) {
+ INIT_COMPLETION(dsi_mdp_comp);
+ need_wait++;
+ }
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
+
+ if (need_wait) {
+ /* wait until DMA finishes the current job */
+ pr_debug("%s: pending pid=%d\n",
+ __func__, current->pid);
+ wait_for_completion(&dsi_mdp_comp);
+ }
+ pr_debug("%s: done pid=%d\n",
+ __func__, current->pid);
+}
+
+void mipi_dsi_cmd_mdp_start(void)
+{
+ unsigned long flag;
+
+
+ if (!in_interrupt())
+ mipi_dsi_pre_kickoff_action();
+
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ mipi_dsi_enable_irq();
+ dsi_mdp_busy = TRUE;
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
}
@@ -1024,6 +1080,7 @@
struct dsi_cmd_desc *cm;
uint32 dsi_ctrl, ctrl;
int i, video_mode;
+ unsigned long flag;
/* turn on cmd mode
* for video mode, do not send cmds more than
@@ -1050,7 +1107,11 @@
}
}
- mipi_dsi_enable_irq(DSI_CMD_MODE_DMA);
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ mipi_dsi_enable_irq();
+ dsi_mdp_busy = TRUE;
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
+
cm = cmds;
mipi_dsi_buf_init(tp);
for (i = 0; i < cnt; i++) {
@@ -1061,7 +1122,12 @@
msleep(cm->wait);
cm++;
}
- mipi_dsi_disable_irq(DSI_CMD_MODE_DMA);
+
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ dsi_mdp_busy = FALSE;
+ mipi_dsi_disable_irq();
+ complete(&dsi_mdp_comp);
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
if (video_mode)
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, dsi_ctrl); /* restore */
@@ -1091,10 +1157,14 @@
*/
int mipi_dsi_cmds_rx(struct msm_fb_data_type *mfd,
struct dsi_buf *tp, struct dsi_buf *rp,
- struct dsi_cmd_desc *cmds, int len)
+ struct dsi_cmd_desc *cmds, int rlen)
{
- int cnt;
- static int pkt_size;
+ int cnt, len, diff, pkt_size;
+ unsigned long flag;
+ char cmd;
+
+ len = rlen;
+ diff = 0;
if (len <= 2)
cnt = 4; /* short read */
@@ -1108,6 +1178,7 @@
len = MIPI_DSI_LEN; /* 8 bytes at most */
len = (len + 3) & ~0x03; /* len 4 bytes align */
+ diff = len - rlen;
/*
* add extra 2 bytes to len to have overall
* packet size is multipe by 4. This also make
@@ -1128,16 +1199,17 @@
#endif
}
- mipi_dsi_enable_irq(DSI_CMD_MODE_DMA);
- if (pkt_size != len) {
- /* set new max pkt size */
- pkt_size = len;
- max_pktsize[0] = pkt_size;
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ mipi_dsi_enable_irq();
+ dsi_mdp_busy = TRUE;
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
- mipi_dsi_buf_init(tp);
- mipi_dsi_cmd_dma_add(tp, pkt_size_cmd);
- mipi_dsi_cmd_dma_tx(tp);
- }
+ /* packet size need to be set at every read */
+ pkt_size = len;
+ max_pktsize[0] = pkt_size;
+ mipi_dsi_buf_init(tp);
+ mipi_dsi_cmd_dma_add(tp, pkt_size_cmd);
+ mipi_dsi_cmd_dma_tx(tp);
mipi_dsi_buf_init(tp);
mipi_dsi_cmd_dma_add(tp, cmds);
@@ -1149,21 +1221,36 @@
* return data from client is ready and stored
* at RDBK_DATA register already
*/
+ mipi_dsi_buf_init(rp);
mipi_dsi_cmd_dma_rx(rp, cnt);
- mipi_dsi_disable_irq(DSI_CMD_MODE_DMA);
+ spin_lock_irqsave(&dsi_mdp_lock, flag);
+ dsi_mdp_busy = FALSE;
+ mipi_dsi_disable_irq();
+ complete(&dsi_mdp_comp);
+ spin_unlock_irqrestore(&dsi_mdp_lock, flag);
- /* strip off dcs header & crc */
- if (cnt > 4) { /* long response */
- if (mfd->panel_info.mipi.fixed_packet_size)
- rp->data += (cnt - len - 6); /* skip padding */
-
- rp->data += 4; /* skip dcs header */
- rp->len -= 6; /* deduct 4 bytes header + 2 bytes crc */
+ cmd = rp->data[0];
+ switch (cmd) {
+ case DTYPE_ACK_ERR_RESP:
+ pr_debug("%s: rx ACK_ERR_PACLAGE\n", __func__);
+ break;
+ case DTYPE_GEN_READ1_RESP:
+ case DTYPE_DCS_READ1_RESP:
+ mipi_dsi_short_read1_resp(rp);
+ break;
+ case DTYPE_GEN_READ2_RESP:
+ case DTYPE_DCS_READ2_RESP:
+ mipi_dsi_short_read2_resp(rp);
+ break;
+ case DTYPE_GEN_LREAD_RESP:
+ case DTYPE_DCS_LREAD_RESP:
+ mipi_dsi_long_read_resp(rp);
rp->len -= 2; /* extra 2 bytes added */
- } else {
- rp->data += 1; /* skip dcs short header */
- rp->len -= 2; /* deduct 1 byte header + 1 byte ecc */
+ rp->len -= diff; /* align bytes */
+ break;
+ default:
+ break;
}
return rp->len;
@@ -1343,6 +1430,10 @@
}
if (isr & DSI_INTR_CMD_MDP_DONE) {
+ spin_lock(&dsi_mdp_lock);
+ dsi_mdp_busy = FALSE;
+ spin_unlock(&dsi_mdp_lock);
+ complete(&dsi_mdp_comp);
mipi_dsi_disable_irq_nosync();
mipi_dsi_post_kickoff_action();
}
diff --git a/drivers/video/msm/mipi_novatek.c b/drivers/video/msm/mipi_novatek.c
index c6fdeff..cb4bd1b 100644
--- a/drivers/video/msm/mipi_novatek.c
+++ b/drivers/video/msm/mipi_novatek.c
@@ -312,9 +312,6 @@
tp = &novatek_tx_buf;
rp = &novatek_rx_buf;
- mipi_dsi_buf_init(rp);
- mipi_dsi_buf_init(tp);
-
cmd = &novatek_manufacture_id_cmd;
mipi_dsi_cmds_rx(mfd, tp, rp, cmd, 3);
lp = (uint32 *)rp->data;
@@ -445,6 +442,7 @@
/* mdp4_dsi_cmd_busy_wait: will turn on dsi clock also */
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_dsi_blt_dmap_busy_wait(mfd);
+ mipi_dsi_mdp_busy_wait(mfd);
led_pwm1[1] = (unsigned char)(mfd->bl_level);
mipi_dsi_cmds_tx(mfd, &novatek_tx_buf, novatek_cmd_backlight_cmds,
@@ -550,7 +548,7 @@
}
static struct device_attribute mipi_dsi_3d_barrier_attributes[] = {
- __ATTR(enable_3d_barrier, 0666, mipi_dsi_3d_barrier_read,
+ __ATTR(enable_3d_barrier, 0664, mipi_dsi_3d_barrier_read,
mipi_dsi_3d_barrier_write),
};
diff --git a/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c b/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
index 19c91f4..fbd2495 100644
--- a/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
+++ b/drivers/video/msm/mipi_novatek_cmd_qhd_pt.c
@@ -79,7 +79,7 @@
pinfo.mipi.t_clk_post = 0x22;
pinfo.mipi.t_clk_pre = 0x3f;
pinfo.mipi.stream = 0; /* dma_p */
- pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW;
+ pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
pinfo.mipi.te_sel = 1; /* TE from vsycn gpio */
pinfo.mipi.interleave_max = 1;
diff --git a/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c b/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
index ed34aa7..2c02490 100644
--- a/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
+++ b/drivers/video/msm/mipi_toshiba_video_wsvga_pt.c
@@ -29,7 +29,7 @@
/* strength */
{0xff, 0x00, 0x06, 0x00},
/* pll control */
- {0x0, 0x7f, 0x1, 0x1a, 0x00, 0x50, 0x48, 0x63,
+ {0x0, 0x7f, 0x31, 0xda, 0x00, 0x50, 0x48, 0x63,
0x41, 0x0f, 0x01,
0x00, 0x14, 0x03, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01 },
};
diff --git a/drivers/video/msm/mipi_truly.c b/drivers/video/msm/mipi_truly.c
new file mode 100644
index 0000000..a2060f0
--- /dev/null
+++ b/drivers/video/msm/mipi_truly.c
@@ -0,0 +1,259 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "msm_fb.h"
+#include "mipi_dsi.h"
+#include "mipi_truly.h"
+
+static struct msm_panel_common_pdata *mipi_truly_pdata;
+static struct dsi_buf truly_tx_buf;
+static struct dsi_buf truly_rx_buf;
+
+#define TRULY_CMD_DELAY 0
+#define TRULY_SLEEP_OFF_DELAY 150
+#define TRULY_DISPLAY_ON_DELAY 150
+#define GPIO_TRULY_LCD_RESET 129
+
+static int prev_bl = 17;
+
+static char extend_cmd_enable[4] = {0xB9, 0xFF, 0x83, 0x69};
+static char display_setting[16] = {
+ 0xB2, 0x00, 0x23, 0x62,
+ 0x62, 0x70, 0x00, 0xFF,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x03, 0x00, 0x01,
+};
+static char wave_cycle_setting[6] = {0xB4, 0x00, 0x1D, 0x5F, 0x0E, 0x06};
+static char gip_setting[27] = {
+ 0xD5, 0x00, 0x04, 0x03,
+ 0x00, 0x01, 0x05, 0x1C,
+ 0x70, 0x01, 0x03, 0x00,
+ 0x00, 0x40, 0x06, 0x51,
+ 0x07, 0x00, 0x00, 0x41,
+ 0x06, 0x50, 0x07, 0x07,
+ 0x0F, 0x04, 0x00,
+};
+static char power_setting[20] = {
+ 0xB1, 0x01, 0x00, 0x34,
+ 0x06, 0x00, 0x0F, 0x0F,
+ 0x2A, 0x32, 0x3F, 0x3F,
+ 0x07, 0x3A, 0x01, 0xE6,
+ 0xE6, 0xE6, 0xE6, 0xE6,
+};
+static char vcom_setting[3] = {0xB6, 0x56, 0x56};
+static char pannel_setting[2] = {0xCC, 0x02};
+static char gamma_setting[35] = {
+ 0xE0, 0x00, 0x1D, 0x22,
+ 0x38, 0x3D, 0x3F, 0x2E,
+ 0x4A, 0x06, 0x0D, 0x0F,
+ 0x13, 0x15, 0x13, 0x16,
+ 0x10, 0x19, 0x00, 0x1D,
+ 0x22, 0x38, 0x3D, 0x3F,
+ 0x2E, 0x4A, 0x06, 0x0D,
+ 0x0F, 0x13, 0x15, 0x13,
+ 0x16, 0x10, 0x19,
+};
+static char mipi_setting[14] = {
+ 0xBA, 0x00, 0xA0, 0xC6,
+ 0x00, 0x0A, 0x00, 0x10,
+ 0x30, 0x6F, 0x02, 0x11,
+ 0x18, 0x40,
+};
+static char exit_sleep[2] = {0x11, 0x00};
+static char display_on[2] = {0x29, 0x00};
+static char display_off[2] = {0x28, 0x00};
+static char enter_sleep[2] = {0x10, 0x00};
+
+static struct dsi_cmd_desc truly_display_off_cmds[] = {
+ {DTYPE_DCS_WRITE, 1, 0, 0, 10, sizeof(display_off), display_off},
+ {DTYPE_DCS_WRITE, 1, 0, 0, 120, sizeof(enter_sleep), enter_sleep}
+};
+
+static struct dsi_cmd_desc truly_display_on_cmds[] = {
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(extend_cmd_enable), extend_cmd_enable},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(display_setting), display_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(wave_cycle_setting), wave_cycle_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(gip_setting), gip_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(power_setting), power_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(vcom_setting), vcom_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(pannel_setting), pannel_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(gamma_setting), gamma_setting},
+ {DTYPE_GEN_LWRITE, 1, 0, 0, TRULY_CMD_DELAY,
+ sizeof(mipi_setting), mipi_setting},
+ {DTYPE_DCS_WRITE, 1, 0, 0, TRULY_SLEEP_OFF_DELAY,
+ sizeof(exit_sleep), exit_sleep},
+ {DTYPE_DCS_WRITE, 1, 0, 0, TRULY_DISPLAY_ON_DELAY,
+ sizeof(display_on), display_on},
+};
+
+static int mipi_truly_lcd_on(struct platform_device *pdev)
+{
+ struct msm_fb_data_type *mfd;
+
+ mfd = platform_get_drvdata(pdev);
+
+ if (!mfd)
+ return -ENODEV;
+ if (mfd->key != MFD_KEY)
+ return -EINVAL;
+
+ msleep(20);
+ mipi_dsi_cmds_tx(mfd, &truly_tx_buf, truly_display_on_cmds,
+ ARRAY_SIZE(truly_display_on_cmds));
+
+ return 0;
+}
+
+static int mipi_truly_lcd_off(struct platform_device *pdev)
+{
+ struct msm_fb_data_type *mfd;
+
+ mfd = platform_get_drvdata(pdev);
+
+ if (!mfd)
+ return -ENODEV;
+ if (mfd->key != MFD_KEY)
+ return -EINVAL;
+
+ mipi_dsi_cmds_tx(mfd, &truly_tx_buf, truly_display_off_cmds,
+ ARRAY_SIZE(truly_display_off_cmds));
+
+ return 0;
+}
+
+#define BL_LEVEL 17
+static void mipi_truly_set_backlight(struct msm_fb_data_type *mfd)
+{
+ int step = 0, i = 0;
+ int bl_level = mfd->bl_level;
+
+ /* real backlight level, 1 - max, 16 - min, 17 - off */
+ bl_level = BL_LEVEL - bl_level;
+
+ if (bl_level > prev_bl) {
+ step = bl_level - prev_bl;
+ if (bl_level == BL_LEVEL)
+ step--;
+ } else if (bl_level < prev_bl) {
+ step = bl_level + 16 - prev_bl;
+ } else {
+ pr_debug("%s: no change\n", __func__);
+ return;
+ }
+
+ if (bl_level == BL_LEVEL) {
+ /* turn off backlight */
+ mipi_truly_pdata->pmic_backlight(0);
+ } else {
+ if (prev_bl == BL_LEVEL) {
+ /* turn on backlight */
+ mipi_truly_pdata->pmic_backlight(1);
+ udelay(30);
+ }
+ /* adjust backlight level */
+ for (i = 0; i < step; i++) {
+ mipi_truly_pdata->pmic_backlight(0);
+ udelay(1);
+ mipi_truly_pdata->pmic_backlight(1);
+ udelay(1);
+ }
+ }
+ msleep(20);
+ prev_bl = bl_level;
+
+ return;
+}
+
+static int __devinit mipi_truly_lcd_probe(struct platform_device *pdev)
+{
+ if (pdev->id == 0) {
+ mipi_truly_pdata = pdev->dev.platform_data;
+ return 0;
+ }
+
+ msm_fb_add_device(pdev);
+
+ return 0;
+}
+
+static struct platform_driver this_driver = {
+ .probe = mipi_truly_lcd_probe,
+ .driver = {
+ .name = "mipi_truly",
+ },
+};
+
+static struct msm_fb_panel_data truly_panel_data = {
+ .on = mipi_truly_lcd_on,
+ .off = mipi_truly_lcd_off,
+ .set_backlight = mipi_truly_set_backlight,
+};
+
+static int ch_used[3];
+
+int mipi_truly_device_register(struct msm_panel_info *pinfo,
+ u32 channel, u32 panel)
+{
+ struct platform_device *pdev = NULL;
+ int ret;
+
+ if ((channel >= 3) || ch_used[channel])
+ return -ENODEV;
+
+ ch_used[channel] = TRUE;
+
+ pdev = platform_device_alloc("mipi_truly", (panel << 8)|channel);
+
+ if (!pdev)
+ return -ENOMEM;
+
+ truly_panel_data.panel_info = *pinfo;
+
+ ret = platform_device_add_data(pdev, &truly_panel_data,
+ sizeof(truly_panel_data));
+ if (ret) {
+ pr_err("%s: platform_device_add_data failed!\n", __func__);
+ goto err_device_put;
+ }
+
+ ret = platform_device_add(pdev);
+
+ if (ret) {
+ pr_err("%s: platform_device_register failed!\n", __func__);
+ goto err_device_put;
+ }
+
+ return 0;
+
+err_device_put:
+ platform_device_put(pdev);
+ return ret;
+}
+
+static int __init mipi_truly_lcd_init(void)
+{
+ mipi_dsi_buf_alloc(&truly_tx_buf, DSI_BUF_SIZE);
+ mipi_dsi_buf_alloc(&truly_rx_buf, DSI_BUF_SIZE);
+
+ return platform_driver_register(&this_driver);
+}
+
+module_init(mipi_truly_lcd_init);
diff --git a/drivers/video/msm/mipi_truly.h b/drivers/video/msm/mipi_truly.h
new file mode 100644
index 0000000..900e6f6
--- /dev/null
+++ b/drivers/video/msm/mipi_truly.h
@@ -0,0 +1,21 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MIPI_TRULY_H
+#define MIPI_TRULY_H
+
+/* #define MIPI_TRULY_FAKE_PANEL */ /* FAKE PANEL for test */
+
+int mipi_truly_device_register(struct msm_panel_info *pinfo,
+ u32 channel, u32 panel);
+
+#endif /* MIPI_TRULY_H */
diff --git a/drivers/video/msm/mipi_truly_video_wvga_pt.c b/drivers/video/msm/mipi_truly_video_wvga_pt.c
new file mode 100644
index 0000000..931c564
--- /dev/null
+++ b/drivers/video/msm/mipi_truly_video_wvga_pt.c
@@ -0,0 +1,110 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "msm_fb.h"
+#include "mipi_dsi.h"
+#include "mipi_truly.h"
+
+static struct msm_panel_info pinfo;
+
+static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
+ /* DSI Bit Clock at 500 MHz, 2 lane, RGB888 */
+ /* regulator */
+ {0x03, 0x01, 0x01, 0x00},
+ /* timing */
+ {0xb9, 0x8e, 0x1f, 0x00, 0x98, 0x9c, 0x22, 0x90,
+ 0x18, 0x03, 0x04},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xbb, 0x02, 0x06, 0x00},
+ /* pll control */
+ {0x00, 0xec, 0x31, 0xd2, 0x00, 0x40, 0x37, 0x62,
+ 0x01, 0x0f, 0x07,
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x0, 0x20, 0x0, 0x02, 0x0},
+};
+
+static int __init mipi_video_truly_wvga_pt_init(void)
+{
+ int ret;
+
+#ifdef CONFIG_FB_MSM_MIPI_PANEL_DETECT
+ if (msm_fb_detect_client("mipi_video_truly_wvga"))
+ return 0;
+#endif
+
+ pinfo.xres = 480;
+ pinfo.yres = 800;
+ pinfo.type = MIPI_VIDEO_PANEL;
+ pinfo.pdest = DISPLAY_1;
+ pinfo.wait_cycle = 0;
+ pinfo.bpp = 24;
+ pinfo.lcdc.h_back_porch = 100;
+ pinfo.lcdc.h_front_porch = 100;
+ pinfo.lcdc.h_pulse_width = 8;
+ pinfo.lcdc.v_back_porch = 20;
+ pinfo.lcdc.v_front_porch = 20;
+ pinfo.lcdc.v_pulse_width = 1;
+ pinfo.lcdc.border_clr = 0; /* blk */
+ pinfo.lcdc.underflow_clr = 0xff; /* blue */
+ /* number of dot_clk cycles HSYNC active edge
+ is delayed from VSYNC active edge */
+ pinfo.lcdc.hsync_skew = 0;
+ pinfo.clk_rate = 499000000;
+ pinfo.bl_max = 15;
+ pinfo.bl_min = 1;
+ pinfo.fb_num = 2;
+
+ pinfo.mipi.mode = DSI_VIDEO_MODE;
+ pinfo.mipi.pulse_mode_hsa_he = TRUE; /* send HSA and HE following
+ VS/VE packet */
+ pinfo.mipi.hfp_power_stop = TRUE; /* LP-11 during the HFP period */
+ pinfo.mipi.hbp_power_stop = TRUE; /* LP-11 during the HBP period */
+ pinfo.mipi.hsa_power_stop = TRUE; /* LP-11 during the HSA period */
+ /* LP-11 or let Command Mode Engine send packets in
+ HS or LP mode for the BLLP of the last line of a frame */
+ pinfo.mipi.eof_bllp_power_stop = TRUE;
+ /* LP-11 or let Command Mode Engine send packets in
+ HS or LP mode for packets sent during BLLP period */
+ pinfo.mipi.bllp_power_stop = TRUE;
+
+ pinfo.mipi.traffic_mode = DSI_BURST_MODE;
+ pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+ pinfo.mipi.vc = 0;
+ pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB; /* RGB */
+ pinfo.mipi.data_lane0 = TRUE;
+ pinfo.mipi.data_lane1 = TRUE;
+
+ pinfo.mipi.t_clk_post = 0x20;
+ pinfo.mipi.t_clk_pre = 0x2f;
+
+ pinfo.mipi.stream = 0; /* dma_p */
+ pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
+ pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+ pinfo.mipi.frame_rate = 60; /* FIXME */
+
+ pinfo.mipi.dsi_phy_db = &dsi_video_mode_phy_db;
+ pinfo.mipi.dlane_swap = 0x01;
+ pinfo.mipi.tx_eot_append = 0x01; /* append EOT at the end
+ of data burst */
+
+ ret = mipi_truly_device_register(&pinfo, MIPI_DSI_PRIM,
+ MIPI_DSI_PANEL_WVGA_PT);
+
+ if (ret)
+ pr_err("%s: failed to register device!\n", __func__);
+
+ return ret;
+}
+
+module_init(mipi_video_truly_wvga_pt_init);
diff --git a/drivers/video/msm/msm_fb.c b/drivers/video/msm/msm_fb.c
index bde0573..94c38ff 100644
--- a/drivers/video/msm/msm_fb.c
+++ b/drivers/video/msm/msm_fb.c
@@ -2690,6 +2690,11 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
}
+#else
+static void msmfb_set_color_conv(struct mdp_csc *p)
+{
+ mdp4_vg_csc_update(p);
+}
#endif
static int msmfb_notify_update(struct fb_info *info, unsigned long *argp)
@@ -2726,6 +2731,8 @@
struct mdp_histogram hist;
#ifndef CONFIG_FB_MSM_MDP40
struct mdp_ccs ccs_matrix;
+#else
+ struct mdp_csc csc_matrix;
#endif
struct mdp_page_protection fb_page_protection;
int ret = 0;
@@ -2805,7 +2812,16 @@
msmfb_set_color_conv(&ccs_matrix) ;
up(&msm_fb_ioctl_ppp_sem);
#else
- ret = -EINVAL;
+ ret = copy_from_user(&csc_matrix, argp, sizeof(csc_matrix));
+ if (ret) {
+ pr_err("%s:MSMFB_SET_CSC_MATRIX ioctl failed\n",
+ __func__);
+ return ret;
+ }
+ down(&msm_fb_ioctl_ppp_sem);
+ msmfb_set_color_conv(&csc_matrix);
+ up(&msm_fb_ioctl_ppp_sem);
+
#endif
break;
@@ -3002,8 +3018,13 @@
* at panel_info
*
*/
- if (type == HDMI_PANEL || type == DTV_PANEL || type == TV_PANEL)
+ if (type == HDMI_PANEL || type == DTV_PANEL || type == TV_PANEL) {
+#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
+ pdata->panel_info.fb_num = 2;
+#else
pdata->panel_info.fb_num = 1;
+#endif
+ }
else
pdata->panel_info.fb_num = MSM_FB_NUM;
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
index 87ed889..cc35ea3 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_interrupt_handler.c
@@ -877,25 +877,31 @@
vidc_1080p_clear_returned_channel_inst_id();
ddl = ddl_get_current_ddl_client_for_channel_id(ddl_context,
ddl_context->response_cmd_ch_id);
- if (!ddl || (!DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_WAIT_FOR_EOS_DONE))) {
- DDL_MSG_ERROR("STATE-CRITICAL-EOSFRMDONE");
- ddl_client_fatal_cb(ddl);
+ if (ddl == NULL) {
+ DDL_MSG_ERROR("NO_DDL_CONTEXT");
} else {
- struct ddl_encoder_data *encoder = &(ddl->codec_data.encoder);
- vidc_1080p_get_encode_frame_info(&encoder->enc_frame_info);
- ddl_handle_enc_frame_done(ddl);
- DDL_MSG_LOW("encoder_eos_done");
- ddl->cmd_state = DDL_CMD_INVALID;
- DDL_MSG_LOW("ddl_state_transition: %s ~~>"
+ if (!DDLCLIENT_STATE_IS(ddl, DDL_CLIENT_WAIT_FOR_EOS_DONE)) {
+ DDL_MSG_ERROR("STATE-CRITICAL-EOSFRMDONE");
+ ddl_client_fatal_cb(ddl);
+ } else {
+ struct ddl_encoder_data *encoder =
+ &(ddl->codec_data.encoder);
+ vidc_1080p_get_encode_frame_info(
+ &encoder->enc_frame_info);
+ ddl_handle_enc_frame_done(ddl);
+ DDL_MSG_LOW("encoder_eos_done");
+ ddl->cmd_state = DDL_CMD_INVALID;
+ DDL_MSG_LOW("ddl_state_transition: %s ~~>"
"DDL_CLIENT_WAIT_FOR_FRAME",
ddl_get_state_string(ddl->client_state));
- ddl->client_state = DDL_CLIENT_WAIT_FOR_FRAME;
- DDL_MSG_LOW("eos_done");
- ddl_context->ddl_callback(VCD_EVT_RESP_EOS_DONE,
- VCD_S_SUCCESS, NULL, 0,
- (u32 *)ddl, ddl->client_data);
- ddl_release_command_channel(ddl_context,
- ddl->command_channel);
+ ddl->client_state = DDL_CLIENT_WAIT_FOR_FRAME;
+ DDL_MSG_LOW("eos_done");
+ ddl_context->ddl_callback(VCD_EVT_RESP_EOS_DONE,
+ VCD_S_SUCCESS, NULL, 0,
+ (u32 *)ddl, ddl->client_data);
+ ddl_release_command_channel(ddl_context,
+ ddl->command_channel);
+ }
}
}
@@ -1133,11 +1139,25 @@
vidc_sm_get_metadata_status(&ddl->shared_mem
[ddl->command_channel],
&decoder->meta_data_exists);
- if (decoder->output_order == VCD_DEC_ORDER_DISPLAY)
+ if (decoder->output_order == VCD_DEC_ORDER_DISPLAY) {
vidc_sm_get_frame_tags(&ddl->shared_mem
[ddl->command_channel],
&dec_disp_info->tag_top,
&dec_disp_info->tag_bottom);
+ if (dec_disp_info->display_correct ==
+ VIDC_1080P_DECODE_NOT_CORRECT ||
+ dec_disp_info->display_correct ==
+ VIDC_1080P_DECODE_APPROX_CORRECT)
+ output_vcd_frm->flags |=
+ VCD_FRAME_FLAG_DATACORRUPT;
+ } else {
+ if (dec_disp_info->decode_correct ==
+ VIDC_1080P_DECODE_NOT_CORRECT ||
+ dec_disp_info->decode_correct ==
+ VIDC_1080P_DECODE_APPROX_CORRECT)
+ output_vcd_frm->flags |=
+ VCD_FRAME_FLAG_DATACORRUPT;
+ }
output_vcd_frm->ip_frm_tag = dec_disp_info->tag_top;
vidc_sm_get_picture_times(&ddl->shared_mem
[ddl->command_channel],
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
index bb26c51..0405513 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_properties.c
@@ -834,38 +834,55 @@
break;
case VCD_I_RECON_BUFFERS:
{
- int index;
+ int index, index_hw_bufs = -1;
struct vcd_property_enc_recon_buffer *recon_buffers =
(struct vcd_property_enc_recon_buffer *)property_value;
for (index = 0; index < 4; index++) {
- if (!encoder->hw_bufs.dpb_y[index].align_physical_addr)
+ if (!encoder->hw_bufs.dpb_y[index].
+ align_physical_addr) {
+ index_hw_bufs = index;
break;
- else
+ } else
continue;
- }
- if (property_hdr->sz == sizeof(struct
- vcd_property_enc_recon_buffer)) {
- encoder->hw_bufs.dpb_y[index].align_physical_addr =
- recon_buffers->physical_addr;
- encoder->hw_bufs.dpb_y[index].align_virtual_addr =
- recon_buffers->kernel_virtual_addr;
- encoder->hw_bufs.dpb_y[index].buffer_size =
- recon_buffers->buffer_size;
- encoder->hw_bufs.dpb_c[index].align_physical_addr =
- recon_buffers->physical_addr + ddl_get_yuv_buf_size(
- encoder->frame_size.width, encoder->frame_size.
- height, DDL_YUV_BUF_TYPE_TILE);
- encoder->hw_bufs.dpb_c[index].align_virtual_addr =
- recon_buffers->kernel_virtual_addr +
- recon_buffers->ysize;
- DDL_MSG_LOW("Y::KVirt: %p,KPhys: %p"
- "UV::KVirt: %p,KPhys: %p\n",
- encoder->hw_bufs.dpb_y[index].align_virtual_addr,
- encoder->hw_bufs.dpb_y[index].align_physical_addr,
- encoder->hw_bufs.dpb_c[index].align_virtual_addr,
- encoder->hw_bufs.dpb_c[index].align_physical_addr);
- vcd_status = VCD_S_SUCCESS;
- }
+ }
+ if (index_hw_bufs == -1) {
+ DDL_MSG_HIGH("ERROR: value of index_hw_bufs");
+ vcd_status = VCD_ERR_ILLEGAL_PARM;
+ } else {
+ if (property_hdr->sz == sizeof(struct
+ vcd_property_enc_recon_buffer)) {
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_physical_addr =
+ recon_buffers->physical_addr;
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_virtual_addr =
+ recon_buffers->kernel_virtual_addr;
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ buffer_size = recon_buffers->buffer_size;
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_physical_addr =
+ recon_buffers->physical_addr +
+ ddl_get_yuv_buf_size(
+ encoder->frame_size.width,
+ encoder->frame_size.height,
+ DDL_YUV_BUF_TYPE_TILE);
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_virtual_addr =
+ recon_buffers->kernel_virtual_addr +
+ recon_buffers->ysize;
+ DDL_MSG_LOW("Y::KVirt: %p,KPhys: %p"
+ "UV::KVirt: %p,KPhys: %p\n",
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_virtual_addr,
+ encoder->hw_bufs.dpb_y[index_hw_bufs].
+ align_physical_addr,
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_virtual_addr,
+ encoder->hw_bufs.dpb_c[index_hw_bufs].
+ align_physical_addr);
+ vcd_status = VCD_S_SUCCESS;
+ }
+ }
}
break;
case VCD_I_FREE_RECON_BUFFERS:
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
index e9d4353..ac05364 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.c
@@ -200,6 +200,10 @@
#define VIDC_SM_CHROMA_ADDR_CHANGE_BMASK 0x00000001
#define VIDC_SM_CHROMA_ADDR_CHANGE_SHFT 0
+#define VIDC_SM_SEI_ENABLE_ADDR 0x0180
+#define VIDC_SM_SEI_ENABLE_RECOVERY_POINT_SEI_BMSK 0x00000001
+#define VIDC_SM_SEI_ENABLE_RECOVERY_POINT_SEI_SHFT 0
+
#define DDL_MEM_WRITE_32(base, offset, val) ddl_mem_write_32(\
(u32 *) ((u8 *) (base)->align_virtual_addr + (offset)), (val))
#define DDL_MEM_READ_32(base, offset) ddl_mem_read_32(\
@@ -686,7 +690,7 @@
enum vidc_sm_mpeg4_profileinfo profile_info)
{
u32 profile_enforce = 0;
- if (shared_mem) {
+ if (shared_mem != NULL) {
profile_enforce = 1;
switch (profile_info) {
case VIDC_SM_PROFILE_INFO_ASP:
@@ -700,6 +704,17 @@
profile_enforce = 0;
break;
}
+ DDL_MEM_WRITE_32(shared_mem, 0x15c, profile_enforce);
}
- DDL_MEM_WRITE_32(shared_mem, 0x15c, profile_enforce);
+}
+void vidc_sm_set_decoder_sei_enable(struct ddl_buf_addr *shared_mem,
+ u32 sei_enable)
+{
+ DDL_MEM_WRITE_32(shared_mem, VIDC_SM_SEI_ENABLE_ADDR, sei_enable);
+}
+
+void vidc_sm_get_decoder_sei_enable(struct ddl_buf_addr *shared_mem,
+ u32 *sei_enable)
+{
+ *sei_enable = DDL_MEM_READ_32(shared_mem, VIDC_SM_SEI_ENABLE_ADDR);
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.h b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.h
index c6eed86..8a4b598 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.h
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_shared_mem.h
@@ -47,6 +47,7 @@
#define VIDC_SM_LEVEL_VC1_ADV_3 (3)
#define VIDC_SM_LEVEL_VC1_ADV_4 (4)
+#define VIDC_SM_RECOVERY_POINT_SEI (1)
enum VIDC_SM_frame_skip {
VIDC_SM_FRAME_SKIP_DISABLE = 0,
VIDC_SM_FRAME_SKIP_ENABLE_LEVEL = 1,
@@ -163,4 +164,8 @@
u32 addr_change);
void vidc_sm_set_mpeg4_profile_override(struct ddl_buf_addr *shared_mem,
enum vidc_sm_mpeg4_profileinfo profile_info);
+void vidc_sm_set_decoder_sei_enable(struct ddl_buf_addr *shared_mem,
+ u32 sei_enable);
+void vidc_sm_get_decoder_sei_enable(struct ddl_buf_addr *shared_mem,
+ u32 *sei_enable);
#endif
diff --git a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
index 8ba90a9..8b293b6 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vcd_ddl_vidc.c
@@ -246,6 +246,10 @@
vidc_sm_set_mpeg4_profile_override(
&ddl->shared_mem[ddl->command_channel],
VIDC_SM_PROFILE_INFO_ASP);
+ if (VCD_CODEC_H264 == decoder->codec.codec)
+ vidc_sm_set_decoder_sei_enable(
+ &ddl->shared_mem[ddl->command_channel],
+ VIDC_SM_RECOVERY_POINT_SEI);
ddl_context->vidc_decode_seq_start[ddl->command_channel](
&seq_start_param);
}
diff --git a/drivers/video/msm/vidc/1080p/ddl/vidc.c b/drivers/video/msm/vidc/1080p/ddl/vidc.c
index ae918f0..5b4cdee 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vidc.c
+++ b/drivers/video/msm/vidc/1080p/ddl/vidc.c
@@ -36,6 +36,8 @@
#define VIDC_1080P_SI_RG7_DISPLAY_CROP_MASK 0x00000040
#define VIDC_1080P_SI_RG7_DISPLAY_CROP_SHIFT 6
+#define VIDC_1080P_SI_RG7_DISPLAY_CORRECT_MASK 0x00000180
+#define VIDC_1080P_SI_RG7_DISPLAY_CORRECT_SHIFT 7
#define VIDC_1080P_SI_RG8_DECODE_FRAMETYPE_MASK 0x00000007
#define VIDC_1080P_SI_RG10_NUM_DPB_BMSK 0x00003fff
@@ -54,6 +56,8 @@
#define VIDC_1080P_SI_RG11_DECODE_CROPP_MASK 0x00000100
#define VIDC_1080P_SI_RG11_DECODE_CROPP_SHIFT 8
+#define VIDC_1080P_SI_RG11_DECODE_CORRECT_MASK 0x00000600
+#define VIDC_1080P_SI_RG11_DECODE_CORRECT_SHIFT 9
#define VIDC_1080P_BASE_OFFSET_SHIFT 11
@@ -501,6 +505,9 @@
dec_disp_info->disp_crop_exists = VIDC_GETFIELD(display_result,
VIDC_1080P_SI_RG7_DISPLAY_CROP_MASK,
VIDC_1080P_SI_RG7_DISPLAY_CROP_SHIFT);
+ dec_disp_info->display_correct = VIDC_GETFIELD(display_result,
+ VIDC_1080P_SI_RG7_DISPLAY_CORRECT_MASK,
+ VIDC_1080P_SI_RG7_DISPLAY_CORRECT_SHIFT);
}
void vidc_1080p_get_decode_frame(
@@ -535,6 +542,9 @@
dec_disp_info->dec_crop_exists = VIDC_GETFIELD(decode_result,
VIDC_1080P_SI_RG11_DECODE_CROPP_MASK,
VIDC_1080P_SI_RG11_DECODE_CROPP_SHIFT);
+ dec_disp_info->decode_correct = VIDC_GETFIELD(decode_result,
+ VIDC_1080P_SI_RG11_DECODE_CORRECT_MASK,
+ VIDC_1080P_SI_RG11_DECODE_CORRECT_SHIFT);
}
void vidc_1080p_decode_seq_start_ch0(
diff --git a/drivers/video/msm/vidc/1080p/ddl/vidc.h b/drivers/video/msm/vidc/1080p/ddl/vidc.h
index f871509..415030a 100644
--- a/drivers/video/msm/vidc/1080p/ddl/vidc.h
+++ b/drivers/video/msm/vidc/1080p/ddl/vidc.h
@@ -270,6 +270,12 @@
VIDC_1080P_DECODE_FRAMETYPE_OTHERS = 4,
VIDC_1080P_DECODE_FRAMETYPE_32BIT = 0x7FFFFFFF
};
+enum vidc_1080P_decode_frame_correct_type {
+ VIDC_1080P_DECODE_NOT_CORRECT = 0,
+ VIDC_1080P_DECODE_CORRECT = 1,
+ VIDC_1080P_DECODE_APPROX_CORRECT = 2,
+ VIDC_1080P_DECODE_CORRECTTYPE_32BIT = 0x7FFFFFFF
+};
enum vidc_1080p_encode_frame{
VIDC_1080P_ENCODE_FRAMETYPE_NOT_CODED = 0,
VIDC_1080P_ENCODE_FRAMETYPE_I = 1,
@@ -417,6 +423,8 @@
enum vidc_1080p_display_status decode_status;
enum vidc_1080p_display_coding display_coding;
enum vidc_1080p_display_coding decode_coding;
+ enum vidc_1080P_decode_frame_correct_type display_correct;
+ enum vidc_1080P_decode_frame_correct_type decode_correct;
enum vidc_1080p_decode_frame input_frame;
};
void vidc_1080p_do_sw_reset(enum vidc_1080p_reset init_flag);
diff --git a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
index 501a4592..8f745ec 100644
--- a/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/1080p/resource_tracker/vcd_res_tracker.c
@@ -47,16 +47,16 @@
goto bail_out;
}
resource_context.vcodec_clk = clk_get(resource_context.device,
- "vcodec_clk");
+ "core_clk");
if (IS_ERR(resource_context.vcodec_clk)) {
- VCDRES_MSG_ERROR("%s(): vcodec_clk get failed\n",
+ VCDRES_MSG_ERROR("%s(): core_clk get failed\n",
__func__);
goto bail_out;
}
resource_context.vcodec_pclk = clk_get(resource_context.device,
- "vcodec_pclk");
+ "iface_clk");
if (IS_ERR(resource_context.vcodec_pclk)) {
- VCDRES_MSG_ERROR("%s(): vcodec_pclk get failed\n",
+ VCDRES_MSG_ERROR("%s(): iface_clk get failed\n",
__func__);
goto release_vcodec_clk;
}
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
index fe3bfaa..54d48b8 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
@@ -277,29 +277,29 @@
__func__, rc);
resource_context.pclk = clk_get(resource_context.device,
- "mfc_pclk");
+ "iface_clk");
if (IS_ERR(resource_context.pclk)) {
- VCDRES_MSG_ERROR("%s(): mfc_pclk get failed\n"
+ VCDRES_MSG_ERROR("%s(): iface_clk get failed\n"
, __func__);
goto disable_regulator;
}
resource_context.hclk = clk_get(resource_context.device,
- "mfc_clk");
+ "core_clk");
if (IS_ERR(resource_context.hclk)) {
- VCDRES_MSG_ERROR("%s(): mfc_clk get failed\n"
+ VCDRES_MSG_ERROR("%s(): core_clk get failed\n"
, __func__);
goto release_pclk;
}
resource_context.hclk_div2 =
- clk_get(resource_context.device, "mfc_div2_clk");
+ clk_get(resource_context.device, "core_div2_clk");
if (IS_ERR(resource_context.hclk_div2)) {
- VCDRES_MSG_ERROR("%s(): mfc_div2_clk get failed\n"
+ VCDRES_MSG_ERROR("%s(): core_div2_clk get failed\n"
, __func__);
goto release_hclk_pclk;
}
@@ -407,7 +407,7 @@
{
VCDRES_MSG_MED("\n res_trk_power_up():: "
"Calling AXI add requirement\n");
- ebi1_clk = clk_get(NULL, "ebi1_vcd_clk");
+ ebi1_clk = clk_get(NULL, "mem_clk");
if (IS_ERR(ebi1_clk)) {
VCDRES_MSG_ERROR("Request AXI bus QOS fails.");
return false;
diff --git a/drivers/video/msm/vidc/common/vcd/vcd_api.h b/drivers/video/msm/vidc/common/vcd/vcd_api.h
index 5735ce2..dec0326 100644
--- a/drivers/video/msm/vidc/common/vcd/vcd_api.h
+++ b/drivers/video/msm/vidc/common/vcd/vcd_api.h
@@ -17,6 +17,7 @@
#define VCD_FRAME_FLAG_EOS 0x00000001
#define VCD_FRAME_FLAG_DECODEONLY 0x00000004
+#define VCD_FRAME_FLAG_DATACORRUPT 0x00000008
#define VCD_FRAME_FLAG_ENDOFFRAME 0x00000010
#define VCD_FRAME_FLAG_SYNCFRAME 0x00000020
#define VCD_FRAME_FLAG_EXTRADATA 0x00000040
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index e46dab1..e3fbecb 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -200,6 +200,7 @@
header-y += inotify.h
header-y += input.h
header-y += ioctl.h
+header-y += ion.h
header-y += ip.h
header-y += ip6_tunnel.h
header-y += ip_vs.h
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index 91d67d5..5c94a3c 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -40,8 +40,10 @@
#define APQ8060_MACHINE_ID 86
#define AO8960_MACHINE_ID 87
#define MSM8660_MACHINE_ID 71
+#define APQ8064_MACHINE_ID 109
#define APQ8060_TOOLS_ID 4062
#define AO8960_TOOLS_ID 4064
+#define APQ8064_TOOLS_ID 4072
#define MSG_MASK_0 (0x00000001)
#define MSG_MASK_1 (0x00000002)
diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h
index c4627cb..e50f98b 100644
--- a/include/linux/eeprom_93cx6.h
+++ b/include/linux/eeprom_93cx6.h
@@ -33,6 +33,7 @@
#define PCI_EEPROM_WIDTH_93C86 8
#define PCI_EEPROM_WIDTH_OPCODE 3
#define PCI_EEPROM_WRITE_OPCODE 0x05
+#define PCI_EEPROM_ERASE_OPCODE 0x07
#define PCI_EEPROM_READ_OPCODE 0x06
#define PCI_EEPROM_EWDS_OPCODE 0x10
#define PCI_EEPROM_EWEN_OPCODE 0x13
@@ -46,6 +47,7 @@
* @register_write(struct eeprom_93cx6 *eeprom): handler to
* write to the eeprom register by using all reg_* fields.
* @width: eeprom width, should be one of the PCI_EEPROM_WIDTH_* defines
+ * @drive_data: Set if we're driving the data line.
* @reg_data_in: register field to indicate data input
* @reg_data_out: register field to indicate data output
* @reg_data_clock: register field to set the data clock
@@ -62,6 +64,7 @@
int width;
+ char drive_data;
char reg_data_in;
char reg_data_out;
char reg_data_clock;
@@ -72,3 +75,8 @@
const u8 word, u16 *data);
extern void eeprom_93cx6_multiread(struct eeprom_93cx6 *eeprom,
const u8 word, __le16 *data, const u16 words);
+
+extern void eeprom_93cx6_wren(struct eeprom_93cx6 *eeprom, bool enable);
+
+extern void eeprom_93cx6_write(struct eeprom_93cx6 *eeprom,
+ u8 addr, u16 data);
diff --git a/include/linux/idle_stats_device.h b/include/linux/idle_stats_device.h
index 0b1ee39..7906d18 100644
--- a/include/linux/idle_stats_device.h
+++ b/include/linux/idle_stats_device.h
@@ -9,6 +9,7 @@
#define MSM_IDLE_STATS_EVENT_BUSY_TIMER_EXPIRED_RESET 2
#define MSM_IDLE_STATS_EVENT_COLLECTION_NEARLY_FULL 4
#define MSM_IDLE_STATS_EVENT_COLLECTION_FULL 8
+#define MSM_IDLE_STATS_EVENT_IDLE_TIMER_EXPIRED 16
/*
* All time, timer, and time interval values are in units of
diff --git a/include/linux/ion.h b/include/linux/ion.h
index df44376..ece819d 100644
--- a/include/linux/ion.h
+++ b/include/linux/ion.h
@@ -19,7 +19,6 @@
#include <linux/ioctl.h>
#include <linux/types.h>
-#include <mach/ion.h>
struct ion_handle;
@@ -74,6 +73,7 @@
#define ION_IS_CACHED(__flags) ((__flags) & (1 << ION_CACHE_SHIFT))
#ifdef __KERNEL__
+#include <mach/ion.h>
struct ion_device;
struct ion_heap;
struct ion_mapper;
diff --git a/include/linux/mfd/pm8xxx/pm8018.h b/include/linux/mfd/pm8xxx/pm8018.h
index ac7231a..69e781c 100644
--- a/include/linux/mfd/pm8xxx/pm8018.h
+++ b/include/linux/mfd/pm8xxx/pm8018.h
@@ -26,6 +26,7 @@
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/regulator/pm8018-regulator.h>
+#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#define PM8018_CORE_DEV_NAME "pm8018-core"
@@ -50,6 +51,9 @@
#define PM8018_PWRKEY_REL_IRQ PM8018_IRQ_BLOCK_BIT(6, 2)
#define PM8018_PWRKEY_PRESS_IRQ PM8018_IRQ_BLOCK_BIT(6, 3)
+#define PM8018_ADC_EOC_USR_IRQ PM8018_IRQ_BLOCK_BIT(9, 6)
+#define PM8018_ADC_BATT_TEMP_WARM_IRQ PM8018_IRQ_BLOCK_BIT(9, 1)
+#define PM8018_ADC_BATT_TEMP_COLD_IRQ PM8018_IRQ_BLOCK_BIT(9, 0)
struct pm8018_platform_data {
struct pm8xxx_irq_platform_data *irq_pdata;
@@ -59,6 +63,7 @@
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8018_regulator_platform_data *regulator_pdatas;
+ struct pm8xxx_adc_platform_data *adc_pdata;
int num_regulators;
};
diff --git a/include/linux/mfd/pm8xxx/pm8xxx-adc.h b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
new file mode 100644
index 0000000..aa642cc
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8xxx-adc.h
@@ -0,0 +1,574 @@
+/*
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921/8018 ADC driver header file
+ *
+ */
+
+#ifndef __PM8XXX_ADC_H
+#define __PM8XXX_ADC_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+
+/**
+ * enum pm8xxx_adc_channels - PM8XXX AMUX arbiter channels
+ * %CHANNEL_VCOIN: Backup voltage for certain register set
+ * %CHANNEL_VBAT: Battery voltage
+ * %CHANNEL_DCIN: Charger input voltage without internal OVP
+ * %CHANNEL_ICHG: Charge-current monitor
+ * %CHANNEL_VPH_PWR: Main system power
+ * %CHANNEL_IBAT: Battery charge current
+ * %CHANNEL_MPP_1: 16:1 pre-mux unity scale MPP input
+ * %CHANNEL_MPP_2: 16:1 pre-mux 1/3 scale MPP input
+ * %CHANNEL_BATT_THERM: Battery temperature
+ * %CHANNEL_BATT_ID: Battery detection
+ * %CHANNEL_USBIN: Charger input voltage with internal OVP
+ * %CHANNEL_DIE_TEMP: Pmic_die temperature
+ * %CHANNEL_625MV: 625mv reference channel
+ * %CHANNEL_125V: 1.25v reference channel
+ * %CHANNEL_CHG_TEMP: Charger temperature
+ * %CHANNEL_MUXOFF: Channel to reduce input load on the mux
+ * %CHANNEL_NONE: Do not use this channel
+ */
+enum pm8xxx_adc_channels {
+ CHANNEL_VCOIN = 0,
+ CHANNEL_VBAT,
+ CHANNEL_DCIN,
+ CHANNEL_ICHG,
+ CHANNEL_VPH_PWR,
+ CHANNEL_IBAT,
+ CHANNEL_MPP_1,
+ CHANNEL_MPP_2,
+ CHANNEL_BATT_THERM,
+ CHANNEL_BATT_ID,
+ CHANNEL_USBIN,
+ CHANNEL_DIE_TEMP,
+ CHANNEL_625MV,
+ CHANNEL_125V,
+ CHANNEL_CHG_TEMP,
+ CHANNEL_MUXOFF,
+ CHANNEL_NONE,
+ ADC_MPP_1_ATEST_8 = 20,
+ ADC_MPP_1_USB_SNS_DIV20,
+ ADC_MPP_1_DCIN_SNS_DIV20,
+ ADC_MPP_1_AMUX3,
+ ADC_MPP_1_AMUX4,
+ ADC_MPP_1_AMUX5,
+ ADC_MPP_1_AMUX6,
+ ADC_MPP_1_AMUX7,
+ ADC_MPP_1_AMUX8,
+ ADC_MPP_1_ATEST_1,
+ ADC_MPP_1_ATEST_2,
+ ADC_MPP_1_ATEST_3,
+ ADC_MPP_1_ATEST_4,
+ ADC_MPP_1_ATEST_5,
+ ADC_MPP_1_ATEST_6,
+ ADC_MPP_1_ATEST_7,
+ ADC_MPP_1_CHANNEL_NONE,
+ ADC_MPP_2_ATEST_8 = 40,
+ ADC_MPP_2_USB_SNS_DIV20,
+ ADC_MPP_2_DCIN_SNS_DIV20,
+ ADC_MPP_2_AMUX3,
+ ADC_MPP_2_AMUX4,
+ ADC_MPP_2_AMUX5,
+ ADC_MPP_2_AMUX6,
+ ADC_MPP_2_AMUX7,
+ ADC_MPP_2_AMUX8,
+ ADC_MPP_2_ATEST_1,
+ ADC_MPP_2_ATEST_2,
+ ADC_MPP_2_ATEST_3,
+ ADC_MPP_2_ATEST_4,
+ ADC_MPP_2_ATEST_5,
+ ADC_MPP_2_ATEST_6,
+ ADC_MPP_2_ATEST_7,
+ ADC_MPP_2_CHANNEL_NONE,
+};
+
+#define PM8XXX_ADC_PMIC_0 0x0
+
+#define PM8XXX_CHANNEL_ADC_625_MV 625
+#define PM8XXX_CHANNEL_MPP_SCALE1_IDX 20
+#define PM8XXX_CHANNEL_MPP_SCALE3_IDX 40
+
+#define PM8XXX_AMUX_MPP_3 0x3
+#define PM8XXX_AMUX_MPP_4 0x4
+#define PM8XXX_AMUX_MPP_5 0x5
+#define PM8XXX_AMUX_MPP_6 0x6
+#define PM8XXX_AMUX_MPP_7 0x7
+#define PM8XXX_AMUX_MPP_8 0x8
+
+#define PM8XXX_ADC_DEV_NAME "pm8xxx-adc"
+
+/**
+ * enum pm8xxx_adc_decimation_type - Sampling rate supported
+ * %ADC_DECIMATION_TYPE1: 512
+ * %ADC_DECIMATION_TYPE2: 1K
+ * %ADC_DECIMATION_TYPE3: 2K
+ * %ADC_DECIMATION_TYPE4: 4k
+ * %ADC_DECIMATION_NONE: Do not use this Sampling type
+ *
+ * The Sampling rate is specific to each channel of the PM8XXX ADC arbiter.
+ */
+enum pm8xxx_adc_decimation_type {
+ ADC_DECIMATION_TYPE1 = 0,
+ ADC_DECIMATION_TYPE2,
+ ADC_DECIMATION_TYPE3,
+ ADC_DECIMATION_TYPE4,
+ ADC_DECIMATION_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_calib_type - PM8XXX ADC Calibration type
+ * %ADC_CALIB_ABSOLUTE: Use 625mV and 1.25V reference channels
+ * %ADC_CALIB_RATIOMETRIC: Use reference Voltage/GND
+ * %ADC_CALIB_CONFIG_NONE: Do not use this calibration type
+ *
+ * Use the input reference voltage depending on the calibration type
+ * to calcluate the offset and gain parameters. The calibration is
+ * specific to each channel of the PM8XXX ADC.
+ */
+enum pm8xxx_adc_calib_type {
+ ADC_CALIB_ABSOLUTE = 0,
+ ADC_CALIB_RATIOMETRIC,
+ ADC_CALIB_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_channel_scaling_param - pre-scaling AMUX ratio
+ * %CHAN_PATH_SCALING1: ratio of {1, 1}
+ * %CHAN_PATH_SCALING2: ratio of {1, 3}
+ * %CHAN_PATH_SCALING3: ratio of {1, 4}
+ * %CHAN_PATH_SCALING4: ratio of {1, 6}
+ * %CHAN_PATH_NONE: Do not use this pre-scaling ratio type
+ *
+ * The pre-scaling is applied for signals to be within the voltage range
+ * of the ADC.
+ */
+enum pm8xxx_adc_channel_scaling_param {
+ CHAN_PATH_SCALING1 = 0,
+ CHAN_PATH_SCALING2,
+ CHAN_PATH_SCALING3,
+ CHAN_PATH_SCALING4,
+ CHAN_PATH_SCALING_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_amux_input_rsv - HK/XOADC reference voltage
+ * %AMUX_RSV0: XO_IN/XOADC_GND
+ * %AMUX_RSV1: PMIC_IN/XOADC_GND
+ * %AMUX_RSV2: PMIC_IN/BMS_CSP
+ * %AMUX_RSV3: not used
+ * %AMUX_RSV4: XOADC_GND/XOADC_GND
+ * %AMUX_RSV5: XOADC_VREF/XOADC_GND
+ * %AMUX_NONE: Do not use this input reference voltage selection
+ */
+enum pm8xxx_adc_amux_input_rsv {
+ AMUX_RSV0 = 0,
+ AMUX_RSV1,
+ AMUX_RSV2,
+ AMUX_RSV3,
+ AMUX_RSV4,
+ AMUX_RSV5,
+ AMUX_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_premux_mpp_scale_type - 16:1 pre-mux scale ratio
+ * %PREMUX_MPP_SCALE_0: No scaling to the input signal
+ * %PREMUX_MPP_SCALE_1: Unity scaling selected by the user for MPP input
+ * %PREMUX_MPP_SCALE_1_DIV3: 1/3 pre-scale to the input MPP signal
+ * %PREMUX_MPP_NONE: Do not use this pre-scale mpp type
+ */
+enum pm8xxx_adc_premux_mpp_scale_type {
+ PREMUX_MPP_SCALE_0 = 0,
+ PREMUX_MPP_SCALE_1,
+ PREMUX_MPP_SCALE_1_DIV3,
+ PREMUX_MPP_NONE,
+};
+
+/**
+ * enum pm8xxx_adc_scale_fn_type - Scaling function for pm8921 pre calibrated
+ * digital data relative to ADC reference
+ * %ADC_SCALE_DEFAULT: Default scaling to convert raw adc code to voltage
+ * %ADC_SCALE_BATT_THERM: Conversion to temperature based on btm parameters
+ * %ADC_SCALE_PMIC_THERM: Returns result in milli degree's Centigrade
+ * %ADC_SCALE_XTERN_CHGR_CUR: Returns current across 0.1 ohm resistor
+ * %ADC_SCALE_XOTHERM: Returns XO thermistor voltage in degree's Centigrade
+ * %ADC_SCALE_NONE: Do not use this scaling type
+ */
+enum pm8xxx_adc_scale_fn_type {
+ ADC_SCALE_DEFAULT = 0,
+ ADC_SCALE_BATT_THERM,
+ ADC_SCALE_PA_THERM,
+ ADC_SCALE_PMIC_THERM,
+ ADC_SCALE_XOTHERM,
+ ADC_SCALE_NONE,
+};
+
+/**
+ * struct pm8xxx_adc_linear_graph - Represent ADC characteristics
+ * @offset: Offset with respect to the actual curve
+ * @dy: Numerator slope to calculate the gain
+ * @dx: Denominator slope to calculate the gain
+ *
+ * Each ADC device has different offset and gain parameters which are computed
+ * to calibrate the device.
+ */
+struct pm8xxx_adc_linear_graph {
+ int32_t offset;
+ int32_t dy;
+ int32_t dx;
+};
+
+/**
+ * struct pm8xxx_adc_map_pt - Map the graph representation for ADC channel
+ * @x: Represent the ADC digitized code
+ * @y: Represent the physical data which can be temperature, voltage,
+ * resistance
+ */
+struct pm8xxx_adc_map_pt {
+ int32_t x;
+ int32_t y;
+};
+
+/**
+ * struct pm8xxx_adc_scaling_ratio - Represent scaling ratio for adc input
+ * @num: Numerator scaling parameter
+ * @den: Denominator scaling parameter
+ */
+struct pm8xxx_adc_scaling_ratio {
+ int32_t num;
+ int32_t den;
+};
+
+/**
+ * struct pm8xxx_adc_properties - Represent the ADC properties
+ * @adc_reference: Reference voltage for PM8XXX ADC
+ * @bitresolution: ADC bit resolution for PM8XXX ADC
+ * @biploar: Polarity for PM8XXX ADC
+ */
+struct pm8xxx_adc_properties {
+ uint32_t adc_vdd_reference;
+ uint32_t bitresolution;
+ bool bipolar;
+};
+
+/**
+ * struct pm8xxx_adc_chan_properties - Represent channel properties of the ADC
+ * @offset_gain_numerator: The inverse numerator of the gain applied to the
+ * input channel
+ * @offset_gain_denominator: The inverse denominator of the gain applied to the
+ * input channel
+ * @adc_graph: ADC graph for the channel of struct type pm8xxx_adc_linear_graph
+ */
+struct pm8xxx_adc_chan_properties {
+ uint32_t offset_gain_numerator;
+ uint32_t offset_gain_denominator;
+ struct pm8xxx_adc_linear_graph adc_graph[2];
+};
+
+/**
+ * struct pm8xxx_adc_chan_result - Represent the result of the PM8XXX ADC
+ * @chan: The channel number of the requested conversion
+ * @adc_code: The pre-calibrated digital output of a given ADC relative to the
+ * the ADC reference
+ * @measurement: In units specific for a given ADC; most ADC uses reference
+ * voltage but some ADC uses reference current. This measurement
+ * here is a number relative to a reference of a given ADC
+ * @physical: The data meaningful for each individual channel whether it is
+ * voltage, current, temperature, etc.
+ */
+struct pm8xxx_adc_chan_result {
+ uint32_t chan;
+ int32_t adc_code;
+ int64_t measurement;
+ int64_t physical;
+};
+
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_scale_default() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: Physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_tdkntcg_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature of the xo therm in mili
+ degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_batt_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pa_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Returns the temperature in degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+/**
+ * pm8xxx_adc_scale_pmic_therm() - Scales the pre-calibrated digital output
+ * of an ADC to the ADC reference and compensates for the
+ * gain and offset. Performs the AMUX out as 2mv/K and returns
+ * the temperature in mili degC.
+ * @adc_code: pre-calibrated digital ouput of the ADC.
+ * @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
+ * reference voltage.
+ * @chan_prop: individual channel properties to compensate the i/p scaling,
+ * slope and offset.
+ * @chan_rslt: physical result to be stored.
+ */
+int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt);
+#else
+static inline int32_t pm8xxx_adc_scale_default(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+static inline int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
+ const struct pm8xxx_adc_properties *adc_prop,
+ const struct pm8xxx_adc_chan_properties *chan_prop,
+ struct pm8xxx_adc_chan_result *chan_rslt)
+{ return -ENXIO; }
+#endif
+
+/**
+ * struct pm8xxx_adc_scale_fn - Scaling function prototype
+ * @chan: Function pointer to one of the scaling functions
+ * which takes the adc properties, channel properties,
+ * and returns the physical result
+ */
+struct pm8xxx_adc_scale_fn {
+ int32_t (*chan) (int32_t,
+ const struct pm8xxx_adc_properties *,
+ const struct pm8xxx_adc_chan_properties *,
+ struct pm8xxx_adc_chan_result *);
+};
+
+/**
+ * struct pm8xxx_adc_amux - AMUX properties for individual channel
+ * @name: Channel name
+ * @channel_name: Channel in integer used from pm8xxx_adc_channels
+ * @chan_path_prescaling: Channel scaling performed on the input signal
+ * @adc_rsv: Input reference Voltage/GND selection to the ADC
+ * @adc_decimation: Sampling rate desired for the channel
+ * adc_scale_fn: Scaling function to convert to the data meaningful for
+ * each individual channel whether it is voltage, current,
+ * temperature, etc and compensates the channel properties
+ */
+struct pm8xxx_adc_amux {
+ char *name;
+ enum pm8xxx_adc_channels channel_name;
+ enum pm8xxx_adc_channel_scaling_param chan_path_prescaling;
+ enum pm8xxx_adc_amux_input_rsv adc_rsv;
+ enum pm8xxx_adc_decimation_type adc_decimation;
+ enum pm8xxx_adc_scale_fn_type adc_scale_fn;
+};
+
+/**
+ * struct pm8xxx_adc_arb_btm_param - PM8XXX ADC BTM parameters to set threshold
+ * temperature for client notification
+ * @low_thr_temp: low temperature threshold request for notification
+ * @high_thr_temp: high temperature threshold request for notification
+ * @low_thr_voltage: low temperature converted to voltage by arbiter driver
+ * @high_thr_voltage: high temperature converted to voltage by arbiter driver
+ * @interval: Interval period to check for temperature notification
+ * @btm_warm_fn: Remote function call for warm threshold.
+ * @btm_cool_fn: Remote function call for cold threshold.
+ *
+ * BTM client passes the parameters to be set for the
+ * temperature threshold notifications. The client is
+ * responsible for setting the new threshold
+ * levels once the thresholds are reached
+ */
+struct pm8xxx_adc_arb_btm_param {
+ uint32_t low_thr_temp;
+ uint32_t high_thr_temp;
+ uint64_t low_thr_voltage;
+ uint64_t high_thr_voltage;
+ int32_t interval;
+ void (*btm_warm_fn) (bool);
+ void (*btm_cool_fn) (bool);
+};
+
+int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *);
+
+/**
+ * struct pm8xxx_adc_platform_data - PM8XXX ADC platform data
+ * @adc_prop: ADC specific parameters, voltage and channel setup
+ * @adc_channel: Channel properties of the ADC arbiter
+ * @adc_num_board_channel: Number of channels added in the board file
+ * @adc_mpp_base: PM8XXX MPP0 base passed from board file. This is used
+ * to offset the PM8XXX MPP passed to configure the
+ * the MPP to AMUX mapping.
+ */
+struct pm8xxx_adc_platform_data {
+ struct pm8xxx_adc_properties *adc_prop;
+ struct pm8xxx_adc_amux *adc_channel;
+ uint32_t adc_num_board_channel;
+ uint32_t adc_mpp_base;
+};
+
+/* Public API */
+#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
+ || defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
+/**
+ * pm8xxx_adc_read() - Performs ADC read on the channel.
+ * @channel: Input channel to perform the ADC read.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_mpp_config_read() - Configure's the PM8XXX MPP
+ * to AMUX6 and performs an ADC read.
+ *
+ * On PM8921 ADC the MPP needs to first be configured
+ * as an analog input to the AMUX pre-mux channel before
+ * issuing a read request. PM8921 MPP 8 is mapped to AMUX8
+ * and is common between remote processor's.
+ *
+ * On PM8018 ADC the MPP is directly connected to the AMUX
+ * pre-mux. Therefore clients of the PM8018 MPP do not need
+ * to configure the MPP as an analog input to the pre-mux.
+ * Clients can directly issue request on the pre-mux AMUX
+ * channel to read the ADC on the MPP. Clients can directly
+ * call the pm8xxx_adc_read().
+ * @mpp_num PM8XXX MPP number to configure to AMUX6.
+ * @channel: Input channel to perform the ADC read.
+ * a) 'ADC_MPP_1_AMUX6' if the input voltage is less than 1.8V
+ * b) 'ADC_MPP_2_AMUX6' if the input voltage is greater then 1.8V
+ * the input voltage is pre-divided by 3 and passed to the ADC.
+ * The appropriate scaling function needs to be selected to let
+ * the driver know a post scaling is required before returning
+ * the result.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result);
+/**
+ * pm8xxx_adc_btm_start() - Configure the BTM registers and start
+ monitoring the BATT_THERM channel for
+ threshold warm/cold temperature set
+ by the Battery client. The btm_start
+ api is to be used after calling the
+ pm8xxx_btm_configure() api which sets
+ the temperature thresholds, interval
+ and functions to call when warm/cold
+ events are triggered.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_start(void);
+
+/**
+ * pm8xxx_adc_btm_end() - Configures the BTM registers to stop
+ * monitoring the BATT_THERM channel for
+ * warm/cold events and disables the
+ * interval timer.
+ * @param: none.
+ */
+uint32_t pm8xxx_adc_btm_end(void);
+
+/**
+ * pm8xxx_adc_btm_configure() - Configures the BATT_THERM channel
+ * parameters for warm/cold thresholds.
+ * Sets the interval timer for perfoming
+ * reading the temperature done by the HW.
+ * @btm_param: Structure pointer of type adc_arb_btm_param *
+ * which client provides for threshold warm/cold,
+ * interval and functions to call when warm/cold
+ * events are triggered.
+ */
+uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *);
+#else
+static inline uint32_t pm8xxx_adc_read(uint32_t channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
+ enum pm8xxx_adc_channels channel,
+ struct pm8xxx_adc_chan_result *result)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_start(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_end(void)
+{ return -ENXIO; }
+static inline uint32_t pm8xxx_adc_btm_configure(
+ struct pm8xxx_adc_arb_btm_param *param)
+{ return -ENXIO; }
+#endif
+
+#endif /* PM8XXX_ADC_H */
diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h
index 14f1983..bb3f98a 100644
--- a/include/linux/mfd/pm8xxx/rtc.h
+++ b/include/linux/mfd/pm8xxx/rtc.h
@@ -20,6 +20,7 @@
*/
struct pm8xxx_rtc_platform_data {
bool rtc_write_enable;
+ bool rtc_alarm_powerup;
};
#endif /* __RTC_PM8XXX_H__ */
diff --git a/include/linux/mfd/pmic8058.h b/include/linux/mfd/pmic8058.h
index 8370f18..4d9f257 100644
--- a/include/linux/mfd/pmic8058.h
+++ b/include/linux/mfd/pmic8058.h
@@ -80,6 +80,7 @@
struct pm8058_platform_data {
/* This table is only needed for misc interrupts. */
int irq_base;
+ int irq;
int (*init)(struct pm8058_chip *pm_chip);
int num_subdevs;
diff --git a/include/linux/msm_kgsl.h b/include/linux/msm_kgsl.h
index ae26f27..b55cfe1 100644
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -27,6 +27,9 @@
#define KGSL_MAX_PWRLEVELS 5
+#define KGSL_CONVERT_TO_MBPS(val) \
+ (val*1000*1000U)
+
/* device id */
enum kgsl_deviceid {
KGSL_DEVICE_3D0 = 0x00000000,
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index 26994fc..a739761 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -79,6 +79,7 @@
MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
+ MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
@@ -164,6 +165,15 @@
uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
};
+struct mdp_csc {
+ int id;
+ uint32_t csc_mv[9];
+ uint32_t csc_pre_bv[3];
+ uint32_t csc_post_bv[3];
+ uint32_t csc_pre_lv[6];
+ uint32_t csc_post_lv[6];
+};
+
/* The version of the mdp_blit_req structure so that
* user applications can selectively decide which functionality
* to include
diff --git a/include/linux/rq_stats.h b/include/linux/rq_stats.h
new file mode 100644
index 0000000..e04063f
--- /dev/null
+++ b/include/linux/rq_stats.h
@@ -0,0 +1,31 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+struct rq_data {
+ unsigned int rq_avg;
+ unsigned long rq_poll_jiffies;
+ unsigned long def_timer_jiffies;
+ unsigned long rq_poll_last_jiffy;
+ unsigned long rq_poll_total_jiffies;
+ unsigned long def_timer_last_jiffy;
+ unsigned int def_interval;
+ int64_t def_start_time;
+ struct attribute_group *attr_group;
+ struct kobject *kobj;
+ struct work_struct def_timer_work;
+ int init;
+};
+
+extern spinlock_t rq_lock;
+extern struct rq_data rq_info;
+extern struct workqueue_struct *rq_wq;
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 1e158f5..d776718 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -237,4 +237,9 @@
#define PHY_OTG_COMP_DISABLED BIT(2)
};
+struct msm_hsic_host_platform_data {
+ unsigned strobe;
+ unsigned data;
+};
+
#endif
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 55dc134..79b0415 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -38,6 +38,7 @@
#define ULPI_RUN (1 << 30)
#define ULPI_WRITE (1 << 29)
#define ULPI_READ (0 << 29)
+#define ULPI_SYNC_STATE (1 << 27)
#define ULPI_ADDR(n) (((n) & 255) << 16)
#define ULPI_DATA(n) ((n) & 255)
#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 3c47a92..befd768 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -239,11 +239,26 @@
uint32_t vb;
};
-struct msm_isp_stats_event_ctrl {
+struct msm_mctl_pp_cmd_ack_event {
+ uint32_t cmd; /* VPE_CMD_ZOOM? */
+ int status; /* 0 done, < 0 err */
+ uint32_t cookie; /* daemon's cookie */
+};
+
+struct msm_mctl_pp_event_info {
+ int32_t event;
+ union {
+ struct msm_mctl_pp_cmd_ack_event ack;
+ };
+};
+
+struct msm_isp_event_ctrl {
unsigned short resptype;
union {
struct msm_cam_evt_msg isp_msg;
struct msm_ctrl_cmd ctrl;
+ struct msm_cam_evt_divert_frame div_frame;
+ struct msm_mctl_pp_event_info pp_event_info;
} isp_data;
};
@@ -795,7 +810,9 @@
uint16_t y_output;
uint16_t line_length_pclk;
uint16_t frame_length_lines;
- uint32_t pixel_clk;
+ uint32_t vt_pixel_clk;
+ uint32_t op_pixel_clk;
+ uint16_t binning_factor;
};
struct sensor_output_info_t {
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index fd46692..f6668ef 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -156,7 +156,7 @@
#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
#define VFE_CMD_XBAR_CFG 112
-#define VFE_CMD_EZTUNE_CFG 113
+#define VFE_CMD_MODULE_CFG 113
#define VFE_CMD_ZSL 114
#define VFE_CMD_LINEARIZATION_UPDATE 115
#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
@@ -273,12 +273,6 @@
/* TBD: 3D related */
};
-struct msm_mctl_pp_cmd_ack_event {
- uint32_t cmd; /* VPE_CMD_ZOOM? */
- int status; /* 0 done, < 0 err */
- uint32_t cookie; /* daemon's cookie */
-};
-
struct msm_pp_frame_sp {
unsigned long phy_addr;
uint32_t y_off;
@@ -307,13 +301,5 @@
};
};
-struct msm_mctl_pp_event_info {
- int32_t event;
- union {
- struct msm_mctl_pp_cmd_ack_event ack;
- };
-};
-
-
#endif /*__MSM_ISP_H__*/
diff --git a/include/media/radio-iris.h b/include/media/radio-iris.h
index 37ec48a..359668b 100644
--- a/include/media/radio-iris.h
+++ b/include/media/radio-iris.h
@@ -41,6 +41,9 @@
#define RADIO_HCI_EVENT_PKT 0x14
/*HCI reponce packets*/
#define MAX_RIVA_PEEK_RSP_SIZE 251
+/* default data access */
+#define DEFAULT_DATA_OFFSET 2
+#define DEFAULT_DATA_SIZE 249
/* HCI timeouts */
#define RADIO_HCI_TIMEOUT (10000) /* 10 seconds */
@@ -292,11 +295,14 @@
struct hci_fm_def_data_rd_req {
__u8 mode;
__u8 length;
+ __u8 param_len;
+ __u8 param;
} __packed;
struct hci_fm_def_data_wr_req {
- struct hci_fm_def_data_rd_req data_rd;
- __u8 data[256];
+ __u8 mode;
+ __u8 length;
+ __u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_riva_data {
@@ -447,7 +453,7 @@
struct hci_fm_data_rd_rsp {
__u8 status;
__u8 ret_data_len;
- __u8 data[256];
+ __u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_feature_list_rsp {
@@ -540,6 +546,9 @@
V4L2_CID_PRIVATE_IRIS_TX_TONE,
V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS,
V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER,/*0x8000028*/
+ V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,/*using private CIDs
+ under userclass*/
+ V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
};
@@ -606,6 +615,7 @@
IRIS_BUF_PEEK,
IRIS_BUF_SSBI_PEEK,
IRIS_BUF_RDS_CNTRS,
+ IRIS_BUF_RD_DEFAULT,
IRIS_BUF_MAX
};
@@ -702,6 +712,7 @@
#define RIVA_PEEK_PARAM 0x6
#define RIVA_PEEK_LEN_OFSET 0x6
#define SSBI_PEEK_LEN 0x01
+
int hci_def_data_read(struct hci_fm_def_data_rd_req *arg,
struct radio_hci_dev *hdev);
int hci_def_data_write(struct hci_fm_def_data_wr_req *arg,
diff --git a/include/media/tavarua.h b/include/media/tavarua.h
index ad9eafb..aafa5d0 100644
--- a/include/media/tavarua.h
+++ b/include/media/tavarua.h
@@ -145,7 +145,9 @@
* Here We have IOCTl's that are specifici to IRIS
* (V4L2_CID_PRIVATE_BASE+0x1D--V4L2_CID_PRIVATE_BASE+0x27)
*/
- V4L2_CID_PRIVATE_TAVARUA_SET_NOTCH_FILTER = V4L2_CID_PRIVATE_BASE + 0x28
+ V4L2_CID_PRIVATE_TAVARUA_SET_NOTCH_FILTER =
+ V4L2_CID_PRIVATE_BASE + 0x28,
+ V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH
};
enum tavarua_buf_t {
@@ -305,6 +307,10 @@
RDS_AF_JUMP,
};
+enum audio_path {
+ FM_DIGITAL_PATH,
+ FM_ANALOG_PATH
+};
#define SRCH_MODE 0x07
#define SRCH_DIR 0x08 /* 0-up 1-down */
#define SCAN_DWELL 0x70
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index aa6aeb9..b67803a 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -708,6 +708,12 @@
__le16 sco_max_pkt;
} __packed;
+#define HCI_OP_WRITE_CURRENT_IAC_LAP 0x0c3a
+struct hci_cp_write_current_iac_lap {
+ __u8 num_current_iac;
+ __u8 lap[6];
+} __packed;
+
#define HCI_OP_WRITE_INQUIRY_MODE 0x0c45
#define HCI_MAX_EIR_LENGTH 240
diff --git a/include/net/bluetooth/l2cap.h b/include/net/bluetooth/l2cap.h
index 04f01b7..b98af28 100644
--- a/include/net/bluetooth/l2cap.h
+++ b/include/net/bluetooth/l2cap.h
@@ -648,6 +648,11 @@
#define L2CAP_AMP_STATE_WAIT_PREPARE 11
#define L2CAP_AMP_STATE_RESEGMENT 12
+#define L2CAP_ATT_ERROR 0x01
+#define L2CAP_ATT_RESPONSE_BIT 0x01
+#define L2CAP_ATT_INDICATE 0x1D
+#define L2CAP_ATT_NOT_SUPPORTED 0x06
+
#define __delta_seq(x, y, pi) ((x) >= (y) ? (x) - (y) : \
(pi)->tx_win_max + 1 - (y) + (x))
#define __next_seq(x, pi) ((x + 1) & ((pi)->tx_win_max))
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 5e855dbf..208c157 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -90,6 +90,8 @@
__u8 major;
__u8 minor;
} __packed;
+#define MGMT_MAJOR_CLASS_MASK 0x1F
+#define MGMT_MAJOR_CLASS_LIMITED 0x20
#define MGMT_OP_SET_SERVICE_CACHE 0x000C
struct mgmt_cp_set_service_cache {
@@ -214,6 +216,8 @@
bdaddr_t bdaddr;
} __packed;
+#define MGMT_OP_SET_LIMIT_DISCOVERABLE 0x001F
+
#define MGMT_EV_CMD_COMPLETE 0x0001
struct mgmt_ev_cmd_complete {
__le16 opcode;
diff --git a/kernel/power/wakelock.c b/kernel/power/wakelock.c
index 9f77f61..e9f49b5 100644
--- a/kernel/power/wakelock.c
+++ b/kernel/power/wakelock.c
@@ -386,7 +386,8 @@
if (debug_mask & DEBUG_SUSPEND)
pr_info("power_suspend_late return %d\n", ret);
- msm_suspend_check_done = 1;
+ if (ret == 0)
+ msm_suspend_check_done = 1;
return ret;
}
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index d5097c4..2480d18 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -20,11 +20,17 @@
#include <linux/profile.h>
#include <linux/sched.h>
#include <linux/module.h>
+#include <linux/rq_stats.h>
#include <asm/irq_regs.h>
#include "tick-internal.h"
+
+struct rq_data rq_info;
+struct workqueue_struct *rq_wq;
+spinlock_t rq_lock;
+
/*
* Per cpu nohz control structure
*/
@@ -711,6 +717,50 @@
* High resolution timer specific code
*/
#ifdef CONFIG_HIGH_RES_TIMERS
+static void update_rq_stats(void)
+{
+ unsigned long jiffy_gap = 0;
+ unsigned int rq_avg = 0;
+ unsigned long flags = 0;
+
+ jiffy_gap = jiffies - rq_info.rq_poll_last_jiffy;
+
+ if (jiffy_gap >= rq_info.rq_poll_jiffies) {
+
+ spin_lock_irqsave(&rq_lock, flags);
+
+ if (!rq_info.rq_avg)
+ rq_info.rq_poll_total_jiffies = 0;
+
+ rq_avg = nr_running() * 10;
+
+ if (rq_info.rq_poll_total_jiffies) {
+ rq_avg = (rq_avg * jiffy_gap) +
+ (rq_info.rq_avg *
+ rq_info.rq_poll_total_jiffies);
+ do_div(rq_avg,
+ rq_info.rq_poll_total_jiffies + jiffy_gap);
+ }
+
+ rq_info.rq_avg = rq_avg;
+ rq_info.rq_poll_total_jiffies += jiffy_gap;
+ rq_info.rq_poll_last_jiffy = jiffies;
+
+ spin_unlock_irqrestore(&rq_lock, flags);
+ }
+}
+
+static void wakeup_user(void)
+{
+ unsigned long jiffy_gap;
+
+ jiffy_gap = jiffies - rq_info.def_timer_last_jiffy;
+
+ if (jiffy_gap >= rq_info.def_timer_jiffies) {
+ rq_info.def_timer_last_jiffy = jiffies;
+ queue_work(rq_wq, &rq_info.def_timer_work);
+ }
+}
/*
* We rearm the timer until we get disabled by the idle code.
* Called with interrupts disabled and timer->base->cpu_base->lock held.
@@ -758,6 +808,20 @@
}
update_process_times(user_mode(regs));
profile_tick(CPU_PROFILING);
+
+
+ if ((rq_info.init == 1) && (cpu == 0)) {
+
+ /*
+ * update run queue statistics
+ */
+ update_rq_stats();
+
+ /*
+ * wakeup user if needed
+ */
+ wakeup_user();
+ }
}
hrtimer_forward(timer, now, tick_period);
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index c6b006a..6a9e368 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -413,7 +413,7 @@
config DEBUG_KMEMLEAK
bool "Kernel memory leak detector"
- depends on DEBUG_KERNEL && EXPERIMENTAL && !MEMORY_HOTPLUG && \
+ depends on DEBUG_KERNEL && EXPERIMENTAL && \
(X86 || ARM || PPC || MIPS || S390 || SPARC64 || SUPERH || MICROBLAZE || TILE)
select DEBUG_FS
diff --git a/mm/kmemleak.c b/mm/kmemleak.c
index aacee45..4facb03 100644
--- a/mm/kmemleak.c
+++ b/mm/kmemleak.c
@@ -100,6 +100,7 @@
#include <linux/kmemcheck.h>
#include <linux/kmemleak.h>
+#include <linux/memory_hotplug.h>
/*
* Kmemleak configuration and common defines.
@@ -1220,9 +1221,9 @@
#endif
/*
- * Struct page scanning for each node. The code below is not yet safe
- * with MEMORY_HOTPLUG.
+ * Struct page scanning for each node.
*/
+ lock_memory_hotplug();
for_each_online_node(i) {
pg_data_t *pgdat = NODE_DATA(i);
unsigned long start_pfn = pgdat->node_start_pfn;
@@ -1241,6 +1242,7 @@
scan_block(page, page + 1, NULL, 1);
}
}
+ unlock_memory_hotplug();
/*
* Scanning the task stacks (may introduce false negatives).
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index dea21c1..c21eb88 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -7081,6 +7081,10 @@
static inline int l2cap_att_channel(struct l2cap_conn *conn, __le16 cid, struct sk_buff *skb)
{
struct sock *sk;
+ struct sk_buff *skb_rsp;
+ struct l2cap_hdr *lh;
+ u8 err_rsp[] = {L2CAP_ATT_ERROR, 0x00, 0x00, 0x00,
+ L2CAP_ATT_NOT_SUPPORTED};
sk = l2cap_get_sock_by_fixed_scid(0, cid, conn->src, conn->dst);
if (!sk)
@@ -7100,6 +7104,25 @@
goto done;
drop:
+ if (skb->data[0] & L2CAP_ATT_RESPONSE_BIT &&
+ skb->data[0] != L2CAP_ATT_INDICATE)
+ goto free_skb;
+
+ /* If this is an incoming PDU that requires a response, respond with
+ * a generic error so remote device doesn't hang */
+
+ skb_rsp = bt_skb_alloc(sizeof(err_rsp) + L2CAP_HDR_SIZE, GFP_ATOMIC);
+ if (!skb_rsp)
+ goto free_skb;
+
+ lh = (struct l2cap_hdr *) skb_put(skb_rsp, L2CAP_HDR_SIZE);
+ lh->len = cpu_to_le16(sizeof(err_rsp));
+ lh->cid = cpu_to_le16(L2CAP_CID_LE_DATA);
+ err_rsp[1] = skb->data[0];
+ memcpy(skb_put(skb_rsp, sizeof(err_rsp)), err_rsp, sizeof(err_rsp));
+ hci_send_acl(conn->hcon, NULL, skb_rsp, 0);
+
+free_skb:
kfree_skb(skb);
done:
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index a328db9..ea72708 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -409,6 +409,124 @@
return err;
}
+static u8 get_service_classes(struct hci_dev *hdev)
+{
+ struct list_head *p;
+ u8 val = 0;
+
+ list_for_each(p, &hdev->uuids) {
+ struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
+
+ val |= uuid->svc_hint;
+ }
+
+ return val;
+}
+
+static int update_class(struct hci_dev *hdev)
+{
+ u8 cod[3];
+
+ BT_DBG("%s", hdev->name);
+
+ if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
+ return 0;
+
+ cod[0] = hdev->minor_class;
+ cod[1] = hdev->major_class;
+ cod[2] = get_service_classes(hdev);
+
+ if (memcmp(cod, hdev->dev_class, 3) == 0)
+ return 0;
+
+ return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
+}
+
+static int set_limited_discoverable(struct sock *sk, u16 index,
+ unsigned char *data, u16 len)
+{
+ struct mgmt_mode *cp;
+ struct hci_dev *hdev;
+ struct pending_cmd *cmd;
+ struct hci_cp_write_current_iac_lap dcp;
+ int update_cod;
+ int err = 0;
+ /* General Inquiry LAP: 0x9E8B33, Limited Inquiry LAP: 0x9E8B00 */
+ u8 lap[] = { 0x33, 0x8b, 0x9e, 0x00, 0x8b, 0x9e };
+
+ cp = (void *) data;
+
+ BT_DBG("hci%u discoverable: %d", index, cp->val);
+
+ if (!cp || len != sizeof(*cp))
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EINVAL);
+
+ hdev = hci_dev_get(index);
+ if (!hdev)
+ return cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENODEV);
+
+ hci_dev_lock(hdev);
+
+ if (!test_bit(HCI_UP, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ ENETDOWN);
+ goto failed;
+ }
+
+ if (mgmt_pending_find(MGMT_OP_SET_LIMIT_DISCOVERABLE, index)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EBUSY);
+ goto failed;
+ }
+
+ if (cp->val == test_bit(HCI_ISCAN, &hdev->flags) &&
+ test_bit(HCI_PSCAN, &hdev->flags)) {
+ err = cmd_status(sk, index, MGMT_OP_SET_LIMIT_DISCOVERABLE,
+ EALREADY);
+ goto failed;
+ }
+
+ cmd = mgmt_pending_add(sk, MGMT_OP_SET_LIMIT_DISCOVERABLE, index, data,
+ len);
+ if (!cmd) {
+ err = -ENOMEM;
+ goto failed;
+ }
+
+ memset(&dcp, 0, sizeof(dcp));
+ dcp.num_current_iac = cp->val ? 2 : 1;
+ memcpy(&dcp.lap, lap, dcp.num_current_iac * 3);
+ update_cod = 1;
+
+ if (cp->val) {
+ if (hdev->major_class & MGMT_MAJOR_CLASS_LIMITED)
+ update_cod = 0;
+ hdev->major_class |= MGMT_MAJOR_CLASS_LIMITED;
+ } else {
+ if (!(hdev->major_class & MGMT_MAJOR_CLASS_LIMITED))
+ update_cod = 0;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_LIMITED;
+ }
+
+ if (update_cod)
+ err = update_class(hdev);
+
+ if (err >= 0)
+ err = hci_send_cmd(hdev, HCI_OP_WRITE_CURRENT_IAC_LAP,
+ sizeof(dcp), &dcp);
+
+ if (err < 0)
+ mgmt_pending_remove(cmd);
+
+failed:
+ hci_dev_unlock(hdev);
+ hci_dev_put(hdev);
+
+ return err;
+}
+
static int set_discoverable(struct sock *sk, u16 index, unsigned char *data,
u16 len)
{
@@ -751,39 +869,6 @@
return hci_send_cmd(hdev, HCI_OP_WRITE_EIR, sizeof(cp), &cp);
}
-static u8 get_service_classes(struct hci_dev *hdev)
-{
- struct list_head *p;
- u8 val = 0;
-
- list_for_each(p, &hdev->uuids) {
- struct bt_uuid *uuid = list_entry(p, struct bt_uuid, list);
-
- val |= uuid->svc_hint;
- }
-
- return val;
-}
-
-static int update_class(struct hci_dev *hdev)
-{
- u8 cod[3];
-
- BT_DBG("%s", hdev->name);
-
- if (test_bit(HCI_SERVICE_CACHE, &hdev->flags))
- return 0;
-
- cod[0] = hdev->minor_class;
- cod[1] = hdev->major_class;
- cod[2] = get_service_classes(hdev);
-
- if (memcmp(cod, hdev->dev_class, 3) == 0)
- return 0;
-
- return hci_send_cmd(hdev, HCI_OP_WRITE_CLASS_OF_DEV, sizeof(cod), cod);
-}
-
static int add_uuid(struct sock *sk, u16 index, unsigned char *data, u16 len)
{
struct mgmt_cp_add_uuid *cp;
@@ -912,7 +997,8 @@
hci_dev_lock(hdev);
- hdev->major_class = cp->major;
+ hdev->major_class &= ~MGMT_MAJOR_CLASS_MASK;
+ hdev->major_class |= cp->major & MGMT_MAJOR_CLASS_MASK;
hdev->minor_class = cp->minor;
err = update_class(hdev);
@@ -2111,6 +2197,10 @@
case MGMT_OP_SET_DISCOVERABLE:
err = set_discoverable(sk, index, buf + sizeof(*hdr), len);
break;
+ case MGMT_OP_SET_LIMIT_DISCOVERABLE:
+ err = set_limited_discoverable(sk, index, buf + sizeof(*hdr),
+ len);
+ break;
case MGMT_OP_SET_CONNECTABLE:
err = set_connectable(sk, index, buf + sizeof(*hdr), len);
break;
diff --git a/net/bluetooth/smp.c b/net/bluetooth/smp.c
index a6e2aab..94d0f06 100644
--- a/net/bluetooth/smp.c
+++ b/net/bluetooth/smp.c
@@ -438,6 +438,7 @@
smp_send_cmd(conn, SMP_CMD_PAIRING_FAIL, sizeof(reason),
&reason);
del_timer(&hcon->smp_timer);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
mgmt_auth_failed(hcon->hdev->id, conn->dst, reason);
hci_conn_put(hcon);
} else if (hcon->cfm_pending) {
@@ -686,6 +687,8 @@
set_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
+ hci_conn_hold(hcon);
+
return 0;
}
@@ -846,7 +849,8 @@
reason = 0;
err = -EPERM;
del_timer(&hcon->smp_timer);
- mgmt_auth_failed(hcon->hdev->id, conn->dst, skb->data[1]);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
+ mgmt_auth_failed(hcon->hdev->id, conn->dst, skb->data[0]);
hci_conn_put(hcon);
break;
@@ -895,6 +899,7 @@
smp_send_cmd(conn, SMP_CMD_PAIRING_FAIL, sizeof(reason),
&reason);
del_timer(&hcon->smp_timer);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
mgmt_auth_failed(hcon->hdev->id, conn->dst, reason);
hci_conn_put(hcon);
}
@@ -989,6 +994,7 @@
hcon->disconn_cfm_cb(hcon, 0);
del_timer(&hcon->smp_timer);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
mgmt_auth_failed(hcon->hdev->id, conn->dst, SMP_UNSPECIFIED);
hci_conn_put(hcon);
}
@@ -1002,6 +1008,8 @@
BT_DBG("smp: %d %d %d", status, encrypt, hcon->sec_req);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &hcon->pend);
+
if (!status && encrypt && !hcon->sec_req)
smp_distribute_keys(conn, 0);
@@ -1009,6 +1017,9 @@
else if (hcon->sec_req && (status || !encrypt))
smp_conn_security(conn, hcon->sec_level);
+ else
+ hci_conn_put(hcon);
+
return 0;
}
@@ -1020,6 +1031,7 @@
BT_DBG("%p", conn);
smp_send_cmd(conn, SMP_CMD_PAIRING_FAIL, sizeof(reason), &reason);
+ clear_bit(HCI_CONN_ENCRYPT_PEND, &conn->hcon->pend);
mgmt_auth_failed(conn->hcon->hdev->id, conn->dst, SMP_UNSPECIFIED);
hci_conn_put(conn->hcon);
}
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index c96213d..de6f8e1 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -1229,7 +1229,6 @@
my @setup_docs = ();
my $setup_docs = 0;
- my $in_code_block = 0;
my $exec_file = "";
my $shorttext = BEFORE_SHORTTEXT;
@@ -1375,6 +1374,7 @@
if ($line =~ /^diff --git.*?(\S+)$/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@;
+ $exec_file = $realfile;
} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
$realfile = $1;
@@ -1389,16 +1389,14 @@
if ($realfile =~ m@^include/asm/@) {
ERROR("do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
}
- $in_code_block = 1;
+ $exec_file = "";
next;
}
elsif ($rawline =~ /^diff.+a\/(.+)\sb\/.+$/) {
$exec_file = $1;
- $in_code_block = 0;
}
#Check state to make sure we aren't in code block.
- elsif (!$in_code_block &&
- ($exec_file =~ /^.+\.[chS]$/ or
+ elsif (($exec_file =~ /^.+\.[chS]$/ or
$exec_file =~ /^.+\.txt$/ or
$exec_file =~ /^.+\.ihex$/ or
$exec_file =~ /^.+\.hex$/ or
diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index d169001..0000869 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -47,6 +47,14 @@
TABLA_BANDGAP_MBHC_MODE,
};
+struct mbhc_micbias_regs {
+ u16 cfilt_val;
+ u16 cfilt_ctl;
+ u16 mbhc_reg;
+ u16 int_rbias;
+ u16 ctl_reg;
+};
+
struct tabla_priv {
struct snd_soc_codec *codec;
u32 adc_count;
@@ -72,6 +80,10 @@
bool no_mic_headset_override;
/* Delayed work to report long button press */
struct delayed_work btn0_dwork;
+
+ struct mbhc_micbias_regs mbhc_bias_regs;
+ u8 cfilt_k_value;
+ bool mbhc_micbias_switched;
};
#ifdef CONFIG_DEBUG_FS
@@ -240,7 +252,14 @@
digital_gain),
SOC_SINGLE_S8_TLV("DEC10 Volume", TABLA_A_CDC_TX10_VOL_CTL_GAIN, -84,
40, digital_gain),
-
+ SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", TABLA_A_CDC_IIR1_GAIN_B1_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", TABLA_A_CDC_IIR1_GAIN_B2_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", TABLA_A_CDC_IIR1_GAIN_B3_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", TABLA_A_CDC_IIR1_GAIN_B4_CTL, -84,
+ 40, digital_gain),
SOC_SINGLE_TLV("ADC1 Volume", TABLA_A_TX_1_2_EN, 5, 3, 0, analog_gain),
SOC_SINGLE_TLV("ADC2 Volume", TABLA_A_TX_1_2_EN, 1, 3, 0, analog_gain),
SOC_SINGLE_TLV("ADC3 Volume", TABLA_A_TX_3_4_EN, 5, 3, 0, analog_gain),
@@ -900,6 +919,103 @@
}
}
+static int tabla_find_k_value(unsigned int ldoh_v, unsigned int cfilt_mv)
+{
+ int rc = -EINVAL;
+ unsigned min_mv, max_mv;
+
+ switch (ldoh_v) {
+ case TABLA_LDOH_1P95_V:
+ min_mv = 160;
+ max_mv = 1800;
+ break;
+ case TABLA_LDOH_2P35_V:
+ min_mv = 200;
+ max_mv = 2200;
+ break;
+ case TABLA_LDOH_2P75_V:
+ min_mv = 240;
+ max_mv = 2600;
+ break;
+ case TABLA_LDOH_2P85_V:
+ min_mv = 250;
+ max_mv = 2700;
+ break;
+ default:
+ goto done;
+ }
+
+ if (cfilt_mv < min_mv || cfilt_mv > max_mv)
+ goto done;
+
+ for (rc = 4; rc <= 44; rc++) {
+ min_mv = max_mv * (rc) / 44;
+ if (min_mv >= cfilt_mv) {
+ rc -= 4;
+ break;
+ }
+ }
+done:
+ return rc;
+}
+
+static bool tabla_is_hph_pa_on(struct snd_soc_codec *codec)
+{
+ u8 hph_reg_val = 0;
+ hph_reg_val = snd_soc_read(codec, TABLA_A_RX_HPH_CNP_EN);
+
+ return (hph_reg_val & 0x30) ? true : false;
+}
+
+static void tabla_codec_switch_micbias(struct snd_soc_codec *codec,
+ int vddio_switch)
+{
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ int cfilt_k_val;
+
+ switch (vddio_switch) {
+ case 1:
+ if (tabla->mbhc_polling_active) {
+ /* Enable Mic Bias switch to VDDIO */
+ tabla->cfilt_k_value = snd_soc_read(codec,
+ tabla->mbhc_bias_regs.cfilt_val);
+ cfilt_k_val = tabla_find_k_value(
+ tabla->pdata->micbias.ldoh_v, 1800);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_val,
+ 0xFC, (cfilt_k_val << 2));
+
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x80);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x10, 0x00);
+
+ tabla->mbhc_micbias_switched = true;
+ pr_debug("%s: Enabled MBHC Mic bias to VDDIO Switch\n",
+ __func__);
+ }
+ break;
+
+ case 0:
+ if (tabla->mbhc_micbias_switched) {
+ /* Disable Mic Bias switch to VDDIO */
+ if (tabla->cfilt_k_value != 0)
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_val, 0XFC,
+ tabla->cfilt_k_value);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x10, 0x00);
+
+ tabla->mbhc_micbias_switched = false;
+ pr_debug("%s: Disabled MBHC Mic bias to VDDIO Switch\n",
+ __func__);
+ }
+ break;
+ }
+}
+
static int tabla_codec_enable_micbias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
@@ -941,6 +1057,11 @@
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ /* Decide whether to switch the micbias for MBHC */
+ if ((w->reg == tabla->mbhc_bias_regs.ctl_reg)
+ && tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+
snd_soc_update_bits(codec, w->reg, 0x0E, 0x0A);
tabla_codec_update_cfilt_usage(codec, cfilt_sel_val, 1);
@@ -959,7 +1080,13 @@
tabla_codec_start_hs_polling(codec);
}
break;
+
case SND_SOC_DAPM_POST_PMD:
+
+ if ((w->reg == tabla->mbhc_bias_regs.ctl_reg)
+ && tabla_is_hph_pa_on(codec))
+ tabla_codec_switch_micbias(codec, 1);
+
if (strnstr(w->name, internal1_text, 30))
snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
else if (strnstr(w->name, internal2_text, 30))
@@ -1065,16 +1192,30 @@
return 0;
}
-
static int tabla_hph_pa_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
-
+ struct snd_soc_codec *codec = w->codec;
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ u8 mbhc_micb_ctl_val;
pr_debug("%s: event = %d\n", __func__, event);
switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ mbhc_micb_ctl_val = snd_soc_read(codec,
+ tabla->mbhc_bias_regs.ctl_reg);
+
+ if (!(mbhc_micb_ctl_val & 0x80)
+ && !tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 1);
+
+ break;
+
case SND_SOC_DAPM_POST_PMD:
+ if (tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+
pr_debug("%s: sleep 10 ms after %s PA disable.\n", __func__,
w->name);
usleep_range(10000, 10000);
@@ -1084,6 +1225,59 @@
return 0;
}
+static void tabla_get_mbhc_micbias_regs(struct snd_soc_codec *codec,
+ struct mbhc_micbias_regs *micbias_regs)
+{
+ struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
+ struct tabla_mbhc_calibration *calibration = tabla->calibration;
+ unsigned int cfilt;
+
+ switch (calibration->bias) {
+ case TABLA_MICBIAS1:
+ cfilt = tabla->pdata->micbias.bias1_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_1_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_1_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_1_CTL;
+ break;
+ case TABLA_MICBIAS2:
+ cfilt = tabla->pdata->micbias.bias2_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_2_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_2_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_2_CTL;
+ break;
+ case TABLA_MICBIAS3:
+ cfilt = tabla->pdata->micbias.bias3_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_3_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_3_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_3_CTL;
+ break;
+ case TABLA_MICBIAS4:
+ cfilt = tabla->pdata->micbias.bias4_cfilt_sel;
+ micbias_regs->mbhc_reg = TABLA_A_MICB_4_MBHC;
+ micbias_regs->int_rbias = TABLA_A_MICB_4_INT_RBIAS;
+ micbias_regs->ctl_reg = TABLA_A_MICB_4_CTL;
+ break;
+ default:
+ /* Should never reach here */
+ pr_err("%s: Invalid MIC BIAS for MBHC\n", __func__);
+ }
+
+ switch (cfilt) {
+ case TABLA_CFILT1_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_1_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_1_CTL;
+ break;
+ case TABLA_CFILT2_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_2_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_2_CTL;
+ break;
+ case TABLA_CFILT3_SEL:
+ micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_3_VAL;
+ micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_3_CTL;
+ break;
+ }
+}
+
static const struct snd_soc_dapm_widget tabla_dapm_widgets[] = {
/*RX stuff */
SND_SOC_DAPM_OUTPUT("EAR"),
@@ -1099,14 +1293,14 @@
/* Headphone */
SND_SOC_DAPM_OUTPUT("HEADPHONE"),
SND_SOC_DAPM_PGA_E("HPHL", TABLA_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
- tabla_hph_pa_event, SND_SOC_DAPM_POST_PMD),
-
+ tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HPHL DAC", TABLA_A_RX_HPH_L_DAC_CTL, 7, 0,
hphl_switch, ARRAY_SIZE(hphl_switch)),
SND_SOC_DAPM_PGA_E("HPHR", TABLA_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
- tabla_hph_pa_event, SND_SOC_DAPM_POST_PMD),
-
+ tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HPHR DAC", TABLA_A_RX_HPH_R_DAC_CTL, 7, 0,
hphr_switch, ARRAY_SIZE(hphr_switch)),
@@ -1741,9 +1935,11 @@
static void tabla_codec_calibrate_hs_polling(struct snd_soc_codec *codec)
{
/* TODO store register values in calibration */
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0x20);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0xFF);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B10_CTL, 0xFF);
- snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL, 0x00);
+ snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL, 0x20);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL, 0x08);
snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0xEE);
@@ -1816,21 +2012,6 @@
return 0;
}
-static int tabla_digital_mute(struct snd_soc_dai *codec_dai, int mute)
-{
- struct snd_soc_codec *codec = codec_dai->codec;
-
- pr_debug("%s %d\n", __func__, mute);
-
- /* TODO mute TX */
- if (mute)
- snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL, 0x01, 0x01);
- else
- snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL, 0x01, 0x00);
-
- return 0;
-}
-
static int tabla_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
@@ -1941,7 +2122,6 @@
.hw_params = tabla_hw_params,
.set_sysclk = tabla_set_dai_sysclk,
.set_fmt = tabla_set_dai_fmt,
- .digital_mute = tabla_digital_mute,
};
static struct snd_soc_dai_driver tabla_dai[] = {
@@ -2028,10 +2208,7 @@
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
- int micbias_ctl_reg, micbias_cfilt_ctl_reg,
- micbias_mbhc_reg;
short bias_value;
- unsigned int cfilt_sel;
if (!calibration) {
pr_err("Error, no tabla calibration\n");
@@ -2050,49 +2227,12 @@
snd_soc_update_bits(codec, TABLA_A_TX_COM_BIAS, 0xE0, 0xE0);
- /* select cfilt separately from the micbias line in the platform data */
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_ctl_reg = TABLA_A_MICB_1_CTL;
- cfilt_sel = tabla->pdata->micbias.bias1_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- break;
- case TABLA_MICBIAS2:
- micbias_ctl_reg = TABLA_A_MICB_2_CTL;
- cfilt_sel = tabla->pdata->micbias.bias2_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- break;
- case TABLA_MICBIAS3:
- micbias_ctl_reg = TABLA_A_MICB_3_CTL;
- cfilt_sel = tabla->pdata->micbias.bias3_cfilt_sel;
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- break;
- case TABLA_MICBIAS4:
- pr_err("%s: Error, microphone bias 4 not supported\n",
- __func__);
- return -EINVAL;
- default:
- pr_err("Error, invalid mic bias line\n");
- return -EINVAL;
- }
- switch (cfilt_sel) {
- case TABLA_CFILT1_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_1_CTL;
- break;
- case TABLA_CFILT2_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_2_CTL;
- break;
- case TABLA_CFILT3_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_3_CTL;
- break;
- default: /* default should not happen as check should have been done */
- return -EINVAL;
- }
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_ctl, 0x70, 0x00);
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x70, 0x00);
-
- snd_soc_update_bits(codec, micbias_ctl_reg, 0x1F, 0x16);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.ctl_reg, 0x1F, 0x16);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
@@ -2108,13 +2248,11 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x6);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x10, 0x10);
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x01);
-
tabla_codec_calibrate_hs_polling(codec);
bias_value = tabla_codec_measure_micbias_voltage(codec, 0);
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x40, 0x40);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.cfilt_ctl, 0x40, 0x40);
snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
return bias_value;
@@ -2126,7 +2264,6 @@
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
int central_bias_enabled = 0;
- int micbias_int_reg, micbias_ctl_reg, micbias_mbhc_reg;
if (!calibration) {
pr_err("Error, no tabla calibration\n");
@@ -2135,10 +2272,45 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x1, 0);
- if (insertion)
+ if (insertion) {
+ /* Make sure mic bias and Mic line schmitt trigger
+ * are turned OFF
+ */
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg,
+ 0x81, 0x01);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x90, 0x00);
+
+ /* Enable HPH Schmitt Trigger */
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x13);
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x0C,
+ calibration->hph_current << 2);
+
+ /* Turn off HPH PAs during insertion detection to avoid false
+ * insertion interrupts
+ */
+ if (tabla->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
+ snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
+
+ /* setup for insetion detection */
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0);
- else
+ } else {
+ /* Make sure the HPH schmitt trigger is OFF */
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x12, 0x00);
+
+ /* enable the mic line schmitt trigger */
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x60,
+ calibration->mic_current << 5);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x80, 0x80);
+ usleep_range(calibration->mic_pid, calibration->mic_pid);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
+ 0x10, 0x10);
+
+ /* Setup for low power removal detection */
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0x2);
+ }
if (snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x4) {
if (!(tabla->clock_active)) {
@@ -2153,42 +2325,7 @@
0x06, 0);
}
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0xC,
- calibration->hph_current << 2);
-
- /* Turn off HPH PAs during insertion detection to avoid false
- * insertion interrupts
- */
- snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
- snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x13);
-
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- micbias_int_reg = TABLA_A_MICB_1_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_1_CTL;
- break;
- case TABLA_MICBIAS2:
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- micbias_int_reg = TABLA_A_MICB_2_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_2_CTL;
- break;
- case TABLA_MICBIAS3:
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- micbias_int_reg = TABLA_A_MICB_3_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_3_CTL;
- break;
- case TABLA_MICBIAS4:
- micbias_mbhc_reg = TABLA_A_MICB_4_MBHC;
- micbias_int_reg = TABLA_A_MICB_4_INT_RBIAS;
- micbias_ctl_reg = TABLA_A_MICB_4_CTL;
- break;
- default:
- pr_err("Error, invalid mic bias line\n");
- return -EINVAL;
- }
- snd_soc_update_bits(codec, micbias_int_reg, 0x80, 0);
- snd_soc_update_bits(codec, micbias_ctl_reg, 0x1, 0);
+ snd_soc_update_bits(codec, tabla->mbhc_bias_regs.int_rbias, 0x80, 0);
/* If central bandgap disabled */
if (!(snd_soc_read(codec, TABLA_A_PIN_CTL_OE1) & 1)) {
@@ -2208,12 +2345,6 @@
if (central_bias_enabled)
snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x1, 0);
}
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x60,
- calibration->mic_current << 5);
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x80, 0x80);
- usleep_range(calibration->mic_pid, calibration->mic_pid);
-
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x10, 0x10);
snd_soc_update_bits(codec, TABLA_A_MICB_4_MBHC, 0x3, calibration->bias);
@@ -2244,6 +2375,7 @@
}
}
+
int tabla_hs_detect(struct snd_soc_codec *codec,
struct snd_soc_jack *headset_jack, struct snd_soc_jack *button_jack,
struct tabla_mbhc_calibration *calibration)
@@ -2257,6 +2389,7 @@
tabla->headset_jack = headset_jack;
tabla->button_jack = button_jack;
tabla->calibration = calibration;
+ tabla_get_mbhc_micbias_regs(codec, &tabla->mbhc_bias_regs);
INIT_DELAYED_WORK(&tabla->btn0_dwork, btn0_lpress_fn);
return tabla_codec_enable_hs_detect(codec, 1);
@@ -2273,9 +2406,12 @@
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_POTENTIAL);
bias_value = tabla_codec_read_dce_result(codec);
- pr_debug("%s: button press interrupt, bias value is %d\n",
+ pr_debug("%s: button press interrupt, bias value(DCE Read)=%d\n",
__func__, bias_value);
+ bias_value = tabla_codec_read_sta_result(codec);
+ pr_debug("%s: button press interrupt, bias value(STA Read)=%d\n",
+ __func__, bias_value);
/*
* TODO: If button pressed is not button 0,
* report the button press event immediately.
@@ -2299,6 +2435,10 @@
pr_debug("%s\n", __func__);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_RELEASE);
+ mic_voltage = tabla_codec_read_dce_result(codec);
+ pr_debug("%s: Microphone Voltage on release(DCE Read) = %d\n",
+ __func__, mic_voltage);
+
if (priv->buttons_pressed & SND_JACK_BTN_0) {
ret = cancel_delayed_work(&priv->btn0_dwork);
@@ -2315,7 +2455,7 @@
mic_voltage =
tabla_codec_measure_micbias_voltage(codec, 0);
- pr_debug("%s: Microphone Voltage on release = %d\n",
+ pr_debug("%s: Mic Voltage on release(new STA) = %d\n",
__func__, mic_voltage);
if (mic_voltage < -2000 || mic_voltage > -670) {
@@ -2348,7 +2488,6 @@
{
struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
struct tabla_mbhc_calibration *calibration = tabla->calibration;
- int micbias_mbhc_reg;
if (!tabla->mclk_enabled && !tabla->mbhc_polling_active)
tabla_codec_enable_config_mode(codec, 1);
@@ -2356,24 +2495,8 @@
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x0);
- switch (calibration->bias) {
- case TABLA_MICBIAS1:
- micbias_mbhc_reg = TABLA_A_MICB_1_MBHC;
- break;
- case TABLA_MICBIAS2:
- micbias_mbhc_reg = TABLA_A_MICB_2_MBHC;
- break;
- case TABLA_MICBIAS3:
- micbias_mbhc_reg = TABLA_A_MICB_3_MBHC;
- break;
- case TABLA_MICBIAS4:
- micbias_mbhc_reg = TABLA_A_MICB_4_MBHC;
- break;
- default:
- pr_err("Error, invalid mic bias line\n");
- return;
- }
- snd_soc_update_bits(codec, micbias_mbhc_reg, 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x00);
usleep_range(calibration->shutdown_plug_removal,
calibration->shutdown_plug_removal);
@@ -2404,59 +2527,48 @@
struct tabla_priv *priv = data;
struct snd_soc_codec *codec = priv->codec;
int ldo_h_on, micb_cfilt_on;
- int micbias_cfilt_ctl_reg, cfilt_sel;
short mic_voltage;
short threshold_no_mic = 0xF7F6;
short threshold_fake_insert = 0xFD30;
+ u8 is_removal;
pr_debug("%s\n", __func__);
tabla_disable_irq(codec->control_data, TABLA_IRQ_MBHC_INSERTION);
+ is_removal = snd_soc_read(codec, TABLA_A_CDC_MBHC_INT_CTL) & 0x02;
+ snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x03, 0x00);
- switch (priv->calibration->bias) {
- case TABLA_MICBIAS1:
- cfilt_sel = priv->pdata->micbias.bias1_cfilt_sel;
- break;
- case TABLA_MICBIAS2:
- cfilt_sel = priv->pdata->micbias.bias2_cfilt_sel;
- break;
- case TABLA_MICBIAS3:
- cfilt_sel = priv->pdata->micbias.bias3_cfilt_sel;
- break;
- default:
- pr_err("%s: Error, invalid mic bias line, bias value = %d\n",
- __func__, priv->calibration->bias);
- return IRQ_HANDLED;
- }
-
- switch (cfilt_sel) {
- case TABLA_CFILT1_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_1_CTL;
- break;
- case TABLA_CFILT2_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_2_CTL;
- break;
- case TABLA_CFILT3_SEL:
- micbias_cfilt_ctl_reg = TABLA_A_MICB_CFILT_3_CTL;
- break;
- default: /* default should not happen as check should have been done */
- pr_err("%s: Invalid cfilt select, cfilt_sel = %d\n",
- __func__, cfilt_sel);
- return IRQ_HANDLED;
- }
+ /* Turn off both HPH and MIC line schmitt triggers */
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.mbhc_reg,
+ 0x90, 0x00);
+ snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
ldo_h_on = snd_soc_read(codec, TABLA_A_LDO_H_MODE_1) & 0x80;
- micb_cfilt_on = snd_soc_read(codec, micbias_cfilt_ctl_reg) & 0x80;
+ micb_cfilt_on = snd_soc_read(codec,
+ priv->mbhc_bias_regs.cfilt_ctl) & 0x80;
if (!ldo_h_on)
snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x80);
if (!micb_cfilt_on)
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x80, 0x80);
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.cfilt_ctl,
+ 0x80, 0x80);
usleep_range(priv->calibration->setup_plug_removal_delay,
priv->calibration->setup_plug_removal_delay);
- if (snd_soc_read(codec, TABLA_A_CDC_MBHC_INT_CTL) & 0x02) {
+ if (!ldo_h_on)
+ snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x0);
+ if (!micb_cfilt_on)
+ snd_soc_update_bits(codec, priv->mbhc_bias_regs.cfilt_ctl,
+ 0x80, 0x0);
+
+ if (is_removal) {
+ /*
+ * If headphone is removed while playback is in progress,
+ * it is possible that micbias will be switched to VDDIO.
+ */
+ if (priv->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
if (priv->headset_jack) {
pr_debug("%s: Reporting removal\n", __func__);
snd_soc_jack_report(priv->headset_jack, 0,
@@ -2467,11 +2579,6 @@
return IRQ_HANDLED;
}
- if (!ldo_h_on)
- snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x80, 0x0);
- if (!micb_cfilt_on)
- snd_soc_update_bits(codec, micbias_cfilt_ctl_reg, 0x80, 0x0);
-
mic_voltage = tabla_codec_setup_hs_polling(codec);
if (mic_voltage > threshold_fake_insert) {
@@ -2526,6 +2633,13 @@
pr_debug("False alarm, headset not actually removed\n");
tabla_codec_start_hs_polling(codec);
} else {
+ /*
+ * If this removal is not false, first check the micbias
+ * switch status and switch it to LDOH if it is already
+ * switched to VDDIO.
+ */
+ if (priv->mbhc_micbias_switched)
+ tabla_codec_switch_micbias(codec, 0);
if (priv->headset_jack) {
pr_debug("%s: Reporting removal\n", __func__);
snd_soc_jack_report(priv->headset_jack, 0,
@@ -2567,45 +2681,6 @@
return IRQ_HANDLED;
}
-static int tabla_find_k_value(unsigned int ldoh_v, unsigned int cfilt_mv)
-{
- int rc = -EINVAL;
- unsigned min_mv, max_mv;
-
- switch (ldoh_v) {
- case TABLA_LDOH_1P95_V:
- min_mv = 160;
- max_mv = 1800;
- break;
- case TABLA_LDOH_2P35_V:
- min_mv = 200;
- max_mv = 2200;
- break;
- case TABLA_LDOH_2P75_V:
- min_mv = 240;
- max_mv = 2600;
- break;
- case TABLA_LDOH_2P85_V:
- min_mv = 250;
- max_mv = 2700;
- break;
- default:
- goto done;
- }
-
- if (cfilt_mv < min_mv || cfilt_mv > max_mv)
- goto done;
-
- for (rc = 4; rc <= 44; rc++) {
- min_mv = max_mv * (rc) / 44;
- if (min_mv >= cfilt_mv) {
- rc -= 4;
- break;
- }
- }
-done:
- return rc;
-}
static int tabla_handle_pdata(struct tabla_priv *tabla)
{
@@ -2804,6 +2879,12 @@
return -ENOMEM;
}
+ /* Make sure mbhc micbias register addresses are zeroed out */
+ memset(&tabla->mbhc_bias_regs, 0,
+ sizeof(struct mbhc_micbias_regs));
+ tabla->cfilt_k_value = 0;
+ tabla->mbhc_micbias_switched = false;
+
snd_soc_codec_set_drvdata(codec, tabla);
tabla->mclk_enabled = false;
diff --git a/sound/soc/msm/msm-pcm-lpa.c b/sound/soc/msm/msm-pcm-lpa.c
index eeb163e..2719d22 100644
--- a/sound/soc/msm/msm-pcm-lpa.c
+++ b/sound/soc/msm/msm-pcm-lpa.c
@@ -79,9 +79,11 @@
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_aio_write_param param;
struct audio_buffer *buf = prtd->audio_client->port[IN].buf;
+ unsigned long flag = 0;
int i = 0;
pr_debug("%s\n", __func__);
+ spin_lock_irqsave(&the_locks.event_lock, flag);
switch (opcode) {
case ASM_DATA_EVENT_WRITE_DONE: {
uint32_t *ptrmem = (uint32_t *)¶m;
@@ -163,6 +165,7 @@
pr_debug("Not Supported Event opcode[0x%x]\n", opcode);
break;
}
+ spin_unlock_irqrestore(&the_locks.event_lock, flag);
}
static int msm_pcm_playback_prepare(struct snd_pcm_substream *substream)
@@ -201,6 +204,7 @@
pr_debug("%s\n", __func__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
+ prtd->pcm_irq_pos = 0;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pr_debug("SNDRV_PCM_TRIGGER_START\n");
@@ -511,6 +515,7 @@
static int __init msm_soc_platform_init(void)
{
+ spin_lock_init(&the_locks.event_lock);
init_waitqueue_head(&the_locks.enable_wait);
init_waitqueue_head(&the_locks.eos_wait);
init_waitqueue_head(&the_locks.write_wait);
diff --git a/sound/soc/msm/msm-pcm-q6.c b/sound/soc/msm/msm-pcm-q6.c
index 367a3e7..49324a9 100644
--- a/sound/soc/msm/msm-pcm-q6.c
+++ b/sound/soc/msm/msm-pcm-q6.c
@@ -71,9 +71,9 @@
.rate_max = 48000,
.channels_min = 1,
.channels_max = 2,
- .buffer_bytes_max = 4096 * 8,
- .period_bytes_min = 4096,
- .period_bytes_max = 4096,
+ .buffer_bytes_max = 2048 * 8,
+ .period_bytes_min = 2048,
+ .period_bytes_max = 2048,
.periods_min = 8,
.periods_max = 8,
.fifo_size = 0,
diff --git a/sound/soc/msm/msm-pcm-q6.h b/sound/soc/msm/msm-pcm-q6.h
index 42e54de..214bd9d 100644
--- a/sound/soc/msm/msm-pcm-q6.h
+++ b/sound/soc/msm/msm-pcm-q6.h
@@ -43,6 +43,7 @@
};
struct audio_locks {
+ spinlock_t event_lock;
wait_queue_head_t read_wait;
wait_queue_head_t write_wait;
wait_queue_head_t eos_wait;
diff --git a/sound/soc/msm/msm8960.c b/sound/soc/msm/msm8960.c
index 548b834..bbb0789 100644
--- a/sound/soc/msm/msm8960.c
+++ b/sound/soc/msm/msm8960.c
@@ -447,11 +447,8 @@
{"DMIC5", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic5"},
-};
-
-static const struct snd_soc_dapm_route cdp_audio_map[] = {
- /** Digital Mic GM4 on CDP mainboard.
- * Connected to DMIC6 input on Tabla codec.
+ /* Tabla digital Mic6 - back bottom digital Mic on Liquid and
+ * bottom mic on CDP. FLUID/MTP do not have dmic6 installed.
*/
{"DMIC6", NULL, "MIC BIAS4 External"},
{"MIC BIAS4 External", NULL, "Digital Mic6"},
@@ -584,16 +581,6 @@
snd_soc_dapm_add_routes(dapm, common_audio_map,
ARRAY_SIZE(common_audio_map));
- if (machine_is_msm8960_cdp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_mtp())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
- else if (machine_is_msm8960_fluid())
- snd_soc_dapm_add_routes(dapm, cdp_audio_map,
- ARRAY_SIZE(cdp_audio_map));
-
snd_soc_dapm_enable_pin(dapm, "Ext Spk");
snd_soc_dapm_sync(dapm);
diff --git a/sound/soc/msm/qdsp6/q6asm.c b/sound/soc/msm/qdsp6/q6asm.c
index 9c54548..052286b 100644
--- a/sound/soc/msm/qdsp6/q6asm.c
+++ b/sound/soc/msm/qdsp6/q6asm.c
@@ -790,7 +790,7 @@
do_gettimeofday(&in_cont_tv);
pr_err("In_CONT:previous read buffer done \
at %ld sec %ld microsec\n",\
- out_cont_tv.tv_sec, out_cont_tv.tv_usec);
+ in_cont_tv.tv_sec, in_cont_tv.tv_usec);
}
}
#endif