| commit | 948c93e9dde8e153775b90fe87c2da638aaa9986 | [log] [tgz] |
|---|---|---|
| author | pfang <fangpan@codeaurora.org> | Wed Mar 20 17:04:18 2013 -0700 |
| committer | pfang <fangpan@codeaurora.org> | Thu Mar 21 10:29:12 2013 -0700 |
| tree | 0663be9da4fa67c683fa2dde74cbd7cb57c98922 | |
| parent | db0ca0bff9c53e87a7bd0c5da2b8c61cfe2c33e4 [diff] |
msm: clock-8226: Change axi_clk max frequency The max frequency 266000 is a round value now. If DDR run with 533Mhz, will require instantaneous bandwidth 4264000, which need clock to be 266500 at least. So change the max value to precise value. Change-Id: I9b1ac160ff5e817c919d39d548d9c0eee89e1a67 Signed-off-by: Pan Fang <fangpan@codeaurora.org>